drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "core.h"
  21 #include "hw.h"
  22 #include "reg.h"
  23 #include "phy.h"
  24 #include "initvals.h"
  25
  26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
  27
  28 extern struct hal_percal_data iq_cal_multi_sample;
  29 extern struct hal_percal_data iq_cal_single_sample;
  30 extern struct hal_percal_data adc_gain_cal_multi_sample;
  31 extern struct hal_percal_data adc_gain_cal_single_sample;
  32 extern struct hal_percal_data adc_dc_cal_multi_sample;
  33 extern struct hal_percal_data adc_dc_cal_single_sample;
  34 extern struct hal_percal_data adc_init_dc_cal;
  35
  36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
  37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
  38                               enum ath9k_ht_macmode macmode);
  39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
  40                               struct ar5416_eeprom *pEepData,
  41                               u32 reg, u32 value);
  42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  44
  45 /********************/
  46 /* Helper Functions */
  47 /********************/
  48
  49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
  50 {
  51         if (ah->ah_curchan != NULL)
  52                 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
  53         else
  54                 return clks / CLOCK_RATE[ATH9K_MODE_11B];
  55 }
  56
  57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
  58 {
  59         struct ath9k_channel *chan = ah->ah_curchan;
  60
  61         if (chan && IS_CHAN_HT40(chan))
  62                 return ath9k_hw_mac_usec(ah, clks) / 2;
  63         else
  64                 return ath9k_hw_mac_usec(ah, clks);
  65 }
  66
  67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
  68 {
  69         if (ah->ah_curchan != NULL)
  70                 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
  71                         ah->ah_curchan)];
  72         else
  73                 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
  74 }
  75
  76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
  77 {
  78         struct ath9k_channel *chan = ah->ah_curchan;
  79
  80         if (chan && IS_CHAN_HT40(chan))
  81                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  82         else
  83                 return ath9k_hw_mac_clks(ah, usecs);
  84 }
  85
  86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
  87                                const struct ath9k_channel *chan)
  88 {
  89         if (IS_CHAN_B(chan))
  90                 return ATH9K_MODE_11B;
  91         if (IS_CHAN_G(chan))
  92                 return ATH9K_MODE_11G;
  93
  94         return ATH9K_MODE_11A;
  95 }
  96
  97 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
  98 {
  99         int i;
 100
 101         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
 102                 if ((REG_READ(ah, reg) & mask) == val)
 103                         return true;
 104
 105                 udelay(AH_TIME_QUANTUM);
 106         }
 107
 108         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 109                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 110                 reg, REG_READ(ah, reg), mask, val);
 111
 112         return false;
 113 }
 114
 115 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 116 {
 117         u32 retval;
 118         int i;
 119
 120         for (i = 0, retval = 0; i < n; i++) {
 121                 retval = (retval << 1) | (val & 1);
 122                 val >>= 1;
 123         }
 124         return retval;
 125 }
 126
 127 bool ath9k_get_channel_edges(struct ath_hal *ah,
 128                              u16 flags, u16 *low,
 129                              u16 *high)
 130 {
 131         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 132
 133         if (flags & CHANNEL_5GHZ) {
 134                 *low = pCap->low_5ghz_chan;
 135                 *high = pCap->high_5ghz_chan;
 136                 return true;
 137         }
 138         if ((flags & CHANNEL_2GHZ)) {
 139                 *low = pCap->low_2ghz_chan;
 140                 *high = pCap->high_2ghz_chan;
 141                 return true;
 142         }
 143         return false;
 144 }
 145
 146 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 147                            struct ath_rate_table *rates,
 148                            u32 frameLen, u16 rateix,
 149                            bool shortPreamble)
 150 {
 151         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 152         u32 kbps;
 153
 154         kbps = rates->info[rateix].ratekbps;
 155
 156         if (kbps == 0)
 157                 return 0;
 158
 159         switch (rates->info[rateix].phy) {
 160         case WLAN_RC_PHY_CCK:
 161                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 162                 if (shortPreamble && rates->info[rateix].short_preamble)
 163                         phyTime >>= 1;
 164                 numBits = frameLen << 3;
 165                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 166                 break;
 167         case WLAN_RC_PHY_OFDM:
 168                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_QUARTER
 173                                 + OFDM_PREAMBLE_TIME_QUARTER
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 175                 } else if (ah->ah_curchan &&
 176                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 177                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 178                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 179                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 180                         txTime = OFDM_SIFS_TIME_HALF +
 181                                 OFDM_PREAMBLE_TIME_HALF
 182                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 183                 } else {
 184                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 185                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 186                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 187                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 188                                 + (numSymbols * OFDM_SYMBOL_TIME);
 189                 }
 190                 break;
 191         default:
 192                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 193                         "Unknown phy %u (rate ix %u)\n",
 194                         rates->info[rateix].phy, rateix);
 195                 txTime = 0;
 196                 break;
 197         }
 198
 199         return txTime;
 200 }
 201
 202 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
 203 {
 204         if (flags & CHANNEL_2GHZ) {
 205                 if (freq == 2484)
 206                         return 14;
 207                 if (freq < 2484)
 208                         return (freq - 2407) / 5;
 209                 else
 210                         return 15 + ((freq - 2512) / 20);
 211         } else if (flags & CHANNEL_5GHZ) {
 212                 if (ath9k_regd_is_public_safety_sku(ah) &&
 213                     IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 214                         return ((freq * 10) +
 215                                 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
 216                 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
 217                         return (freq - 4000) / 5;
 218                 } else {
 219                         return (freq - 5000) / 5;
 220                 }
 221         } else {
 222                 if (freq == 2484)
 223                         return 14;
 224                 if (freq < 2484)
 225                         return (freq - 2407) / 5;
 226                 if (freq < 5000) {
 227                         if (ath9k_regd_is_public_safety_sku(ah)
 228                             && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
 229                                 return ((freq * 10) +
 230                                         (((freq % 5) ==
 231                                           2) ? 5 : 0) - 49400) / 5;
 232                         } else if (freq > 4900) {
 233                                 return (freq - 4000) / 5;
 234                         } else {
 235                                 return 15 + ((freq - 2512) / 20);
 236                         }
 237                 }
 238                 return (freq - 5000) / 5;
 239         }
 240 }
 241
 242 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 243                                   struct ath9k_channel *chan,
 244                                   struct chan_centers *centers)
 245 {
 246         int8_t extoff;
 247         struct ath_hal_5416 *ahp = AH5416(ah);
 248
 249         if (!IS_CHAN_HT40(chan)) {
 250                 centers->ctl_center = centers->ext_center =
 251                         centers->synth_center = chan->channel;
 252                 return;
 253         }
 254
 255         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 256             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 257                 centers->synth_center =
 258                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 259                 extoff = 1;
 260         } else {
 261                 centers->synth_center =
 262                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 263                 extoff = -1;
 264         }
 265
 266         centers->ctl_center =
 267                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 268         centers->ext_center =
 269                 centers->synth_center + (extoff *
 270                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 271                           HT40_CHANNEL_CENTER_SHIFT : 15));
 272
 273 }
 274
 275 /******************/
 276 /* Chip Revisions */
 277 /******************/
 278
 279 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 280 {
 281         u32 val;
 282
 283         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 284
 285         if (val == 0xFF) {
 286                 val = REG_READ(ah, AR_SREV);
 287                 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 288                 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
 289                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 290         } else {
 291                 if (!AR_SREV_9100(ah))
 292                         ah->ah_macVersion = MS(val, AR_SREV_VERSION);
 293
 294                 ah->ah_macRev = val & AR_SREV_REVISION;
 295
 296                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
 297                         ah->ah_isPciExpress = true;
 298         }
 299 }
 300
 301 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
 302 {
 303         u32 val;
 304         int i;
 305
 306         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 307
 308         for (i = 0; i < 8; i++)
 309                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 310         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 311         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 312
 313         return ath9k_hw_reverse_bits(val, 8);
 314 }
 315
 316 /************************************/
 317 /* HW Attach, Detach, Init Routines */
 318 /************************************/
 319
 320 static void ath9k_hw_disablepcie(struct ath_hal *ah)
 321 {
 322         if (!AR_SREV_9100(ah))
 323                 return;
 324
 325         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 326         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 327         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 328         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 329         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 330         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 331         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 332         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 333         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 334
 335         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 336 }
 337
 338 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 339 {
 340         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 341         u32 regHold[2];
 342         u32 patternData[4] = { 0x55555555,
 343                                0xaaaaaaaa,
 344                                0x66666666,
 345                                0x99999999 };
 346         int i, j;
 347
 348         for (i = 0; i < 2; i++) {
 349                 u32 addr = regAddr[i];
 350                 u32 wrData, rdData;
 351
 352                 regHold[i] = REG_READ(ah, addr);
 353                 for (j = 0; j < 0x100; j++) {
 354                         wrData = (j << 16) | j;
 355                         REG_WRITE(ah, addr, wrData);
 356                         rdData = REG_READ(ah, addr);
 357                         if (rdData != wrData) {
 358                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 359                                         "address test failed "
 360                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 361                                         addr, wrData, rdData);
 362                                 return false;
 363                         }
 364                 }
 365                 for (j = 0; j < 4; j++) {
 366                         wrData = patternData[j];
 367                         REG_WRITE(ah, addr, wrData);
 368                         rdData = REG_READ(ah, addr);
 369                         if (wrData != rdData) {
 370                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 371                                         "address test failed "
 372                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 373                                         addr, wrData, rdData);
 374                                 return false;
 375                         }
 376                 }
 377                 REG_WRITE(ah, regAddr[i], regHold[i]);
 378         }
 379         udelay(100);
 380         return true;
 381 }
 382
 383 static const char *ath9k_hw_devname(u16 devid)
 384 {
 385         switch (devid) {
 386         case AR5416_DEVID_PCI:
 387                 return "Atheros 5416";
 388         case AR5416_DEVID_PCIE:
 389                 return "Atheros 5418";
 390         case AR9160_DEVID_PCI:
 391                 return "Atheros 9160";
 392         case AR9280_DEVID_PCI:
 393         case AR9280_DEVID_PCIE:
 394                 return "Atheros 9280";
 395         }
 396
 397         return NULL;
 398 }
 399
 400 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 401 {
 402         int i;
 403
 404         ah->ah_config.dma_beacon_response_time = 2;
 405         ah->ah_config.sw_beacon_response_time = 10;
 406         ah->ah_config.additional_swba_backoff = 0;
 407         ah->ah_config.ack_6mb = 0x0;
 408         ah->ah_config.cwm_ignore_extcca = 0;
 409         ah->ah_config.pcie_powersave_enable = 0;
 410         ah->ah_config.pcie_l1skp_enable = 0;
 411         ah->ah_config.pcie_clock_req = 0;
 412         ah->ah_config.pcie_power_reset = 0x100;
 413         ah->ah_config.pcie_restore = 0;
 414         ah->ah_config.pcie_waen = 0;
 415         ah->ah_config.analog_shiftreg = 1;
 416         ah->ah_config.ht_enable = 1;
 417         ah->ah_config.ofdm_trig_low = 200;
 418         ah->ah_config.ofdm_trig_high = 500;
 419         ah->ah_config.cck_trig_high = 200;
 420         ah->ah_config.cck_trig_low = 100;
 421         ah->ah_config.enable_ani = 1;
 422         ah->ah_config.noise_immunity_level = 4;
 423         ah->ah_config.ofdm_weaksignal_det = 1;
 424         ah->ah_config.cck_weaksignal_thr = 0;
 425         ah->ah_config.spur_immunity_level = 2;
 426         ah->ah_config.firstep_level = 0;
 427         ah->ah_config.rssi_thr_high = 40;
 428         ah->ah_config.rssi_thr_low = 7;
 429         ah->ah_config.diversity_control = 0;
 430         ah->ah_config.antenna_switch_swap = 0;
 431
 432         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 433                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 434                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 435         }
 436
 437         ah->ah_config.intr_mitigation = 1;
 438 }
 439
 440 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 441                                               struct ath_softc *sc,
 442                                               void __iomem *mem,
 443                                               int *status)
 444 {
 445         static const u8 defbssidmask[ETH_ALEN] =
 446                 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 447         struct ath_hal_5416 *ahp;
 448         struct ath_hal *ah;
 449
 450         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 451         if (ahp == NULL) {
 452                 DPRINTF(sc, ATH_DBG_FATAL,
 453                         "Cannot allocate memory for state block\n");
 454                 *status = -ENOMEM;
 455                 return NULL;
 456         }
 457
 458         ah = &ahp->ah;
 459         ah->ah_sc = sc;
 460         ah->ah_sh = mem;
 461         ah->ah_magic = AR5416_MAGIC;
 462         ah->ah_countryCode = CTRY_DEFAULT;
 463         ah->ah_devid = devid;
 464         ah->ah_subvendorid = 0;
 465
 466         ah->ah_flags = 0;
 467         if ((devid == AR5416_AR9100_DEVID))
 468                 ah->ah_macVersion = AR_SREV_VERSION_9100;
 469         if (!AR_SREV_9100(ah))
 470                 ah->ah_flags = AH_USE_EEPROM;
 471
 472         ah->ah_powerLimit = MAX_RATE_POWER;
 473         ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
 474         ahp->ah_atimWindow = 0;
 475         ahp->ah_diversityControl = ah->ah_config.diversity_control;
 476         ahp->ah_antennaSwitchSwap =
 477                 ah->ah_config.antenna_switch_swap;
 478         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 479         ahp->ah_beaconInterval = 100;
 480         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
 481         ahp->ah_slottime = (u32) -1;
 482         ahp->ah_acktimeout = (u32) -1;
 483         ahp->ah_ctstimeout = (u32) -1;
 484         ahp->ah_globaltxtimeout = (u32) -1;
 485         memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
 486
 487         ahp->ah_gBeaconRate = 0;
 488
 489         return ahp;
 490 }
 491
 492 static int ath9k_hw_rfattach(struct ath_hal *ah)
 493 {
 494         bool rfStatus = false;
 495         int ecode = 0;
 496
 497         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 498         if (!rfStatus) {
 499                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 500                         "RF setup failed, status %u\n", ecode);
 501                 return ecode;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int ath9k_hw_rf_claim(struct ath_hal *ah)
 508 {
 509         u32 val;
 510
 511         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 512
 513         val = ath9k_hw_get_radiorev(ah);
 514         switch (val & AR_RADIO_SREV_MAJOR) {
 515         case 0:
 516                 val = AR_RAD5133_SREV_MAJOR;
 517                 break;
 518         case AR_RAD5133_SREV_MAJOR:
 519         case AR_RAD5122_SREV_MAJOR:
 520         case AR_RAD2133_SREV_MAJOR:
 521         case AR_RAD2122_SREV_MAJOR:
 522                 break;
 523         default:
 524                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 525                         "5G Radio Chip Rev 0x%02X is not "
 526                         "supported by this driver\n",
 527                         ah->ah_analog5GhzRev);
 528                 return -EOPNOTSUPP;
 529         }
 530
 531         ah->ah_analog5GhzRev = val;
 532
 533         return 0;
 534 }
 535
 536 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
 537 {
 538         u32 sum;
 539         int i;
 540         u16 eeval;
 541         struct ath_hal_5416 *ahp = AH5416(ah);
 542
 543         sum = 0;
 544         for (i = 0; i < 3; i++) {
 545                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 546                 sum += eeval;
 547                 ahp->ah_macaddr[2 * i] = eeval >> 8;
 548                 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
 549         }
 550         if (sum == 0 || sum == 0xffff * 3) {
 551                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 552                         "mac address read failed: %pM\n",
 553                         ahp->ah_macaddr);
 554                 return -EADDRNOTAVAIL;
 555         }
 556
 557         return 0;
 558 }
 559
 560 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
 561 {
 562         u32 rxgain_type;
 563         struct ath_hal_5416 *ahp = AH5416(ah);
 564
 565         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 566                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 567
 568                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 569                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 570                         ar9280Modes_backoff_13db_rxgain_9280_2,
 571                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 572                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 573                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 574                         ar9280Modes_backoff_23db_rxgain_9280_2,
 575                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 576                 else
 577                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 578                         ar9280Modes_original_rxgain_9280_2,
 579                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 580         } else
 581                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 582                         ar9280Modes_original_rxgain_9280_2,
 583                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 584 }
 585
 586 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
 587 {
 588         u32 txgain_type;
 589         struct ath_hal_5416 *ahp = AH5416(ah);
 590
 591         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 592                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 593
 594                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 595                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 596                         ar9280Modes_high_power_tx_gain_9280_2,
 597                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 598                 else
 599                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 600                         ar9280Modes_original_tx_gain_9280_2,
 601                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 602         } else
 603                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 604                 ar9280Modes_original_tx_gain_9280_2,
 605                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 606 }
 607
 608 static int ath9k_hw_post_attach(struct ath_hal *ah)
 609 {
 610         int ecode;
 611
 612         if (!ath9k_hw_chip_test(ah)) {
 613                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 614                         "hardware self-test failed\n");
 615                 return -ENODEV;
 616         }
 617
 618         ecode = ath9k_hw_rf_claim(ah);
 619         if (ecode != 0)
 620                 return ecode;
 621
 622         ecode = ath9k_hw_eeprom_attach(ah);
 623         if (ecode != 0)
 624                 return ecode;
 625         ecode = ath9k_hw_rfattach(ah);
 626         if (ecode != 0)
 627                 return ecode;
 628
 629         if (!AR_SREV_9100(ah)) {
 630                 ath9k_hw_ani_setup(ah);
 631                 ath9k_hw_ani_attach(ah);
 632         }
 633
 634         return 0;
 635 }
 636
 637 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 638                                           void __iomem *mem, int *status)
 639 {
 640         struct ath_hal_5416 *ahp;
 641         struct ath_hal *ah;
 642         int ecode;
 643 #ifndef CONFIG_SLOW_ANT_DIV
 644         u32 i;
 645         u32 j;
 646 #endif
 647
 648         ahp = ath9k_hw_newstate(devid, sc, mem, status);
 649         if (ahp == NULL)
 650                 return NULL;
 651
 652         ah = &ahp->ah;
 653
 654         ath9k_hw_set_defaults(ah);
 655
 656         if (ah->ah_config.intr_mitigation != 0)
 657                 ahp->ah_intrMitigation = true;
 658
 659         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 660                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 661                 ecode = -EIO;
 662                 goto bad;
 663         }
 664
 665         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 666                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 667                 ecode = -EIO;
 668                 goto bad;
 669         }
 670
 671         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 672                 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
 673                         ah->ah_config.serialize_regmode =
 674                                 SER_REG_MODE_ON;
 675                 } else {
 676                         ah->ah_config.serialize_regmode =
 677                                 SER_REG_MODE_OFF;
 678                 }
 679         }
 680
 681         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 682                 "serialize_regmode is %d\n",
 683                 ah->ah_config.serialize_regmode);
 684
 685         if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
 686             (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
 687             (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
 688             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
 689                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 690                         "Mac Chip Rev 0x%02x.%x is not supported by "
 691                         "this driver\n", ah->ah_macVersion, ah->ah_macRev);
 692                 ecode = -EOPNOTSUPP;
 693                 goto bad;
 694         }
 695
 696         if (AR_SREV_9100(ah)) {
 697                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 698                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
 699                 ah->ah_isPciExpress = false;
 700         }
 701         ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 702
 703         if (AR_SREV_9160_10_OR_LATER(ah)) {
 704                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 705                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
 706                         ahp->ah_adcGainCalData.calData =
 707                                 &adc_gain_cal_single_sample;
 708                         ahp->ah_adcDcCalData.calData =
 709                                 &adc_dc_cal_single_sample;
 710                         ahp->ah_adcDcCalInitData.calData =
 711                                 &adc_init_dc_cal;
 712                 } else {
 713                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 714                         ahp->ah_adcGainCalData.calData =
 715                                 &adc_gain_cal_multi_sample;
 716                         ahp->ah_adcDcCalData.calData =
 717                                 &adc_dc_cal_multi_sample;
 718                         ahp->ah_adcDcCalInitData.calData =
 719                                 &adc_init_dc_cal;
 720                 }
 721                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 722         }
 723
 724         if (AR_SREV_9160(ah)) {
 725                 ah->ah_config.enable_ani = 1;
 726                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 727                                         ATH9K_ANI_FIRSTEP_LEVEL);
 728         } else {
 729                 ahp->ah_ani_function = ATH9K_ANI_ALL;
 730                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 731                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 732                 }
 733         }
 734
 735         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 736                 "This Mac Chip Rev 0x%02x.%x is \n",
 737                 ah->ah_macVersion, ah->ah_macRev);
 738
 739         if (AR_SREV_9280_20_OR_LATER(ah)) {
 740                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
 741                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 742                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
 743                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 744
 745                 if (ah->ah_config.pcie_clock_req) {
 746                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 747                                ar9280PciePhy_clkreq_off_L1_9280,
 748                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 749                 } else {
 750                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 751                                ar9280PciePhy_clkreq_always_on_L1_9280,
 752                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 753                 }
 754                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
 755                                ar9280Modes_fast_clock_9280_2,
 756                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 757         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 758                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
 759                                ARRAY_SIZE(ar9280Modes_9280), 6);
 760                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
 761                                ARRAY_SIZE(ar9280Common_9280), 2);
 762         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 763                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
 764                                ARRAY_SIZE(ar5416Modes_9160), 6);
 765                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
 766                                ARRAY_SIZE(ar5416Common_9160), 2);
 767                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
 768                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 769                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 770                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 771                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
 772                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 773                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
 774                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 775                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
 776                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 777                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
 778                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 779                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 780                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 781                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
 782                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 783                 if (AR_SREV_9160_11(ah)) {
 784                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
 785                                        ar5416Addac_91601_1,
 786                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 787                 } else {
 788                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
 789                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 790                 }
 791         } else if (AR_SREV_9100_OR_LATER(ah)) {
 792                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
 793                                ARRAY_SIZE(ar5416Modes_9100), 6);
 794                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
 795                                ARRAY_SIZE(ar5416Common_9100), 2);
 796                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
 797                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 798                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 799                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 800                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
 801                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 802                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
 803                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 804                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
 805                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 806                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
 807                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 808                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 809                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 810                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
 811                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 812                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
 813                                ARRAY_SIZE(ar5416Addac_9100), 2);
 814         } else {
 815                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
 816                                ARRAY_SIZE(ar5416Modes), 6);
 817                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
 818                                ARRAY_SIZE(ar5416Common), 2);
 819                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
 820                                ARRAY_SIZE(ar5416Bank0), 2);
 821                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
 822                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 823                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
 824                                ARRAY_SIZE(ar5416Bank1), 2);
 825                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
 826                                ARRAY_SIZE(ar5416Bank2), 2);
 827                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
 828                                ARRAY_SIZE(ar5416Bank3), 3);
 829                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
 830                                ARRAY_SIZE(ar5416Bank6), 3);
 831                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
 832                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 833                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
 834                                ARRAY_SIZE(ar5416Bank7), 2);
 835                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
 836                                ARRAY_SIZE(ar5416Addac), 2);
 837         }
 838
 839         if (ah->ah_isPciExpress)
 840                 ath9k_hw_configpcipowersave(ah, 0);
 841         else
 842                 ath9k_hw_disablepcie(ah);
 843
 844         ecode = ath9k_hw_post_attach(ah);
 845         if (ecode != 0)
 846                 goto bad;
 847
 848         /* rxgain table */
 849         if (AR_SREV_9280_20_OR_LATER(ah))
 850                 ath9k_hw_init_rxgain_ini(ah);
 851
 852         /* txgain table */
 853         if (AR_SREV_9280_20_OR_LATER(ah))
 854                 ath9k_hw_init_txgain_ini(ah);
 855
 856 #ifndef CONFIG_SLOW_ANT_DIV
 857         if (ah->ah_devid == AR9280_DEVID_PCI) {
 858                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
 859                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 860
 861                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
 862                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 863
 864                                 INI_RA(&ahp->ah_iniModes, i, j) =
 865                                         ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
 866                                                            reg, val);
 867                         }
 868                 }
 869         }
 870 #endif
 871         if (!ath9k_hw_fill_cap_info(ah)) {
 872                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 873                         "failed ath9k_hw_fill_cap_info\n");
 874                 ecode = -EINVAL;
 875                 goto bad;
 876         }
 877
 878         ecode = ath9k_hw_init_macaddr(ah);
 879         if (ecode != 0) {
 880                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 881                         "failed initializing mac address\n");
 882                 goto bad;
 883         }
 884
 885         if (AR_SREV_9285(ah))
 886                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 887         else
 888                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 889
 890         ath9k_init_nfcal_hist_buffer(ah);
 891
 892         return ah;
 893 bad:
 894         if (ahp)
 895                 ath9k_hw_detach((struct ath_hal *) ahp);
 896         if (status)
 897                 *status = ecode;
 898
 899         return NULL;
 900 }
 901
 902 static void ath9k_hw_init_bb(struct ath_hal *ah,
 903                              struct ath9k_channel *chan)
 904 {
 905         u32 synthDelay;
 906
 907         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 908         if (IS_CHAN_B(chan))
 909                 synthDelay = (4 * synthDelay) / 22;
 910         else
 911                 synthDelay /= 10;
 912
 913         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 914
 915         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 916 }
 917
 918 static void ath9k_hw_init_qos(struct ath_hal *ah)
 919 {
 920         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 921         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 922
 923         REG_WRITE(ah, AR_QOS_NO_ACK,
 924                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 925                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 926                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 927
 928         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 929         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 930         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 931         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 932         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 933 }
 934
 935 static void ath9k_hw_init_pll(struct ath_hal *ah,
 936                               struct ath9k_channel *chan)
 937 {
 938         u32 pll;
 939
 940         if (AR_SREV_9100(ah)) {
 941                 if (chan && IS_CHAN_5GHZ(chan))
 942                         pll = 0x1450;
 943                 else
 944                         pll = 0x1458;
 945         } else {
 946                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 947                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 948
 949                         if (chan && IS_CHAN_HALF_RATE(chan))
 950                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 951                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 952                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 953
 954                         if (chan && IS_CHAN_5GHZ(chan)) {
 955                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 956
 957
 958                                 if (AR_SREV_9280_20(ah)) {
 959                                         if (((chan->channel % 20) == 0)
 960                                             || ((chan->channel % 10) == 0))
 961                                                 pll = 0x2850;
 962                                         else
 963                                                 pll = 0x142c;
 964                                 }
 965                         } else {
 966                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 967                         }
 968
 969                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 970
 971                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 972
 973                         if (chan && IS_CHAN_HALF_RATE(chan))
 974                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 975                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 976                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 977
 978                         if (chan && IS_CHAN_5GHZ(chan))
 979                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 980                         else
 981                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 982                 } else {
 983                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 984
 985                         if (chan && IS_CHAN_HALF_RATE(chan))
 986                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 987                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 988                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 989
 990                         if (chan && IS_CHAN_5GHZ(chan))
 991                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 992                         else
 993                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 994                 }
 995         }
 996         REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
 997
 998         udelay(RTC_PLL_SETTLE_DELAY);
 999
1000         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1001 }
1002
1003 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1004 {
1005         struct ath_hal_5416 *ahp = AH5416(ah);
1006         int rx_chainmask, tx_chainmask;
1007
1008         rx_chainmask = ahp->ah_rxchainmask;
1009         tx_chainmask = ahp->ah_txchainmask;
1010
1011         switch (rx_chainmask) {
1012         case 0x5:
1013                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1014                             AR_PHY_SWAP_ALT_CHAIN);
1015         case 0x3:
1016                 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1017                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1018                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1019                         break;
1020                 }
1021         case 0x1:
1022         case 0x2:
1023                 if (!AR_SREV_9280(ah))
1024                         break;
1025         case 0x7:
1026                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1027                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1028                 break;
1029         default:
1030                 break;
1031         }
1032
1033         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1034         if (tx_chainmask == 0x5) {
1035                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1036                             AR_PHY_SWAP_ALT_CHAIN);
1037         }
1038         if (AR_SREV_9100(ah))
1039                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1040                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1041 }
1042
1043 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode)
1044 {
1045         struct ath_hal_5416 *ahp = AH5416(ah);
1046
1047         ahp->ah_maskReg = AR_IMR_TXERR |
1048                 AR_IMR_TXURN |
1049                 AR_IMR_RXERR |
1050                 AR_IMR_RXORN |
1051                 AR_IMR_BCNMISC;
1052
1053         if (ahp->ah_intrMitigation)
1054                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1055         else
1056                 ahp->ah_maskReg |= AR_IMR_RXOK;
1057
1058         ahp->ah_maskReg |= AR_IMR_TXOK;
1059
1060         if (opmode == ATH9K_M_HOSTAP)
1061                 ahp->ah_maskReg |= AR_IMR_MIB;
1062
1063         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1064         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1065
1066         if (!AR_SREV_9100(ah)) {
1067                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1068                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1069                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1070         }
1071 }
1072
1073 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1074 {
1075         struct ath_hal_5416 *ahp = AH5416(ah);
1076
1077         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1078                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1079                 ahp->ah_acktimeout = (u32) -1;
1080                 return false;
1081         } else {
1082                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1083                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1084                 ahp->ah_acktimeout = us;
1085                 return true;
1086         }
1087 }
1088
1089 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1090 {
1091         struct ath_hal_5416 *ahp = AH5416(ah);
1092
1093         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1094                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1095                 ahp->ah_ctstimeout = (u32) -1;
1096                 return false;
1097         } else {
1098                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1099                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1100                 ahp->ah_ctstimeout = us;
1101                 return true;
1102         }
1103 }
1104
1105 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1106 {
1107         struct ath_hal_5416 *ahp = AH5416(ah);
1108
1109         if (tu > 0xFFFF) {
1110                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1111                         "bad global tx timeout %u\n", tu);
1112                 ahp->ah_globaltxtimeout = (u32) -1;
1113                 return false;
1114         } else {
1115                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1116                 ahp->ah_globaltxtimeout = tu;
1117                 return true;
1118         }
1119 }
1120
1121 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1122 {
1123         struct ath_hal_5416 *ahp = AH5416(ah);
1124
1125         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1126                 ahp->ah_miscMode);
1127
1128         if (ahp->ah_miscMode != 0)
1129                 REG_WRITE(ah, AR_PCU_MISC,
1130                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1131         if (ahp->ah_slottime != (u32) -1)
1132                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1133         if (ahp->ah_acktimeout != (u32) -1)
1134                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1135         if (ahp->ah_ctstimeout != (u32) -1)
1136                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1137         if (ahp->ah_globaltxtimeout != (u32) -1)
1138                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1139 }
1140
1141 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1142 {
1143         return vendorid == ATHEROS_VENDOR_ID ?
1144                 ath9k_hw_devname(devid) : NULL;
1145 }
1146
1147 void ath9k_hw_detach(struct ath_hal *ah)
1148 {
1149         if (!AR_SREV_9100(ah))
1150                 ath9k_hw_ani_detach(ah);
1151
1152         ath9k_hw_rfdetach(ah);
1153         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1154         kfree(ah);
1155 }
1156
1157 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1158                                 void __iomem *mem, int *error)
1159 {
1160         struct ath_hal *ah = NULL;
1161
1162         switch (devid) {
1163         case AR5416_DEVID_PCI:
1164         case AR5416_DEVID_PCIE:
1165         case AR9160_DEVID_PCI:
1166         case AR9280_DEVID_PCI:
1167         case AR9280_DEVID_PCIE:
1168                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1169                 break;
1170         default:
1171                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1172                         "devid=0x%x not supported.\n", devid);
1173                 ah = NULL;
1174                 *error = -ENXIO;
1175                 break;
1176         }
1177
1178         return ah;
1179 }
1180
1181 /*******/
1182 /* INI */
1183 /*******/
1184
1185 static void ath9k_hw_override_ini(struct ath_hal *ah,
1186                                   struct ath9k_channel *chan)
1187 {
1188         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1189             AR_SREV_9280_10_OR_LATER(ah))
1190                 return;
1191
1192         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1193 }
1194
1195 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1196                               struct ar5416_eeprom *pEepData,
1197                               u32 reg, u32 value)
1198 {
1199         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1200
1201         switch (ah->ah_devid) {
1202         case AR9280_DEVID_PCI:
1203                 if (reg == 0x7894) {
1204                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1205                                 "ini VAL: %x  EEPROM: %x\n", value,
1206                                 (pBase->version & 0xff));
1207
1208                         if ((pBase->version & 0xff) > 0x0a) {
1209                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1210                                         "PWDCLKIND: %d\n",
1211                                         pBase->pwdclkind);
1212                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1213                                 value |= AR_AN_TOP2_PWDCLKIND &
1214                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1215                         } else {
1216                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1217                                         "PWDCLKIND Earlier Rev\n");
1218                         }
1219
1220                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1221                                 "final ini VAL: %x\n", value);
1222                 }
1223                 break;
1224         }
1225
1226         return value;
1227 }
1228
1229 static int ath9k_hw_process_ini(struct ath_hal *ah,
1230                                 struct ath9k_channel *chan,
1231                                 enum ath9k_ht_macmode macmode)
1232 {
1233         int i, regWrites = 0;
1234         struct ath_hal_5416 *ahp = AH5416(ah);
1235         u32 modesIndex, freqIndex;
1236         int status;
1237
1238         switch (chan->chanmode) {
1239         case CHANNEL_A:
1240         case CHANNEL_A_HT20:
1241                 modesIndex = 1;
1242                 freqIndex = 1;
1243                 break;
1244         case CHANNEL_A_HT40PLUS:
1245         case CHANNEL_A_HT40MINUS:
1246                 modesIndex = 2;
1247                 freqIndex = 1;
1248                 break;
1249         case CHANNEL_G:
1250         case CHANNEL_G_HT20:
1251         case CHANNEL_B:
1252                 modesIndex = 4;
1253                 freqIndex = 2;
1254                 break;
1255         case CHANNEL_G_HT40PLUS:
1256         case CHANNEL_G_HT40MINUS:
1257                 modesIndex = 3;
1258                 freqIndex = 2;
1259                 break;
1260
1261         default:
1262                 return -EINVAL;
1263         }
1264
1265         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1266
1267         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1268
1269         ath9k_hw_set_addac(ah, chan);
1270
1271         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1272                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1273         } else {
1274                 struct ar5416IniArray temp;
1275                 u32 addacSize =
1276                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1277                         ahp->ah_iniAddac.ia_columns;
1278
1279                 memcpy(ahp->ah_addac5416_21,
1280                        ahp->ah_iniAddac.ia_array, addacSize);
1281
1282                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1283
1284                 temp.ia_array = ahp->ah_addac5416_21;
1285                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1286                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1287                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1288         }
1289
1290         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1291
1292         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1293                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1294                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1295
1296 #ifdef CONFIG_SLOW_ANT_DIV
1297                 if (ah->ah_devid == AR9280_DEVID_PCI)
1298                         val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val);
1299 #endif
1300
1301                 REG_WRITE(ah, reg, val);
1302
1303                 if (reg >= 0x7800 && reg < 0x78a0
1304                     && ah->ah_config.analog_shiftreg) {
1305                         udelay(100);
1306                 }
1307
1308                 DO_DELAY(regWrites);
1309         }
1310
1311         if (AR_SREV_9280_20_OR_LATER(ah))
1312                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1313
1314         if (AR_SREV_9280_20_OR_LATER(ah))
1315                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1316
1317         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1318                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1319                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1320
1321                 REG_WRITE(ah, reg, val);
1322
1323                 if (reg >= 0x7800 && reg < 0x78a0
1324                     && ah->ah_config.analog_shiftreg) {
1325                         udelay(100);
1326                 }
1327
1328                 DO_DELAY(regWrites);
1329         }
1330
1331         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1332
1333         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1334                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1335                                 regWrites);
1336         }
1337
1338         ath9k_hw_override_ini(ah, chan);
1339         ath9k_hw_set_regs(ah, chan, macmode);
1340         ath9k_hw_init_chain_masks(ah);
1341
1342         status = ath9k_hw_set_txpower(ah, chan,
1343                                       ath9k_regd_get_ctl(ah, chan),
1344                                       ath9k_regd_get_antenna_allowed(ah,
1345                                                                      chan),
1346                                       chan->maxRegTxPower * 2,
1347                                       min((u32) MAX_RATE_POWER,
1348                                           (u32) ah->ah_powerLimit));
1349         if (status != 0) {
1350                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1351                         "error init'ing transmit power\n");
1352                 return -EIO;
1353         }
1354
1355         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1356                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1357                         "ar5416SetRfRegs failed\n");
1358                 return -EIO;
1359         }
1360
1361         return 0;
1362 }
1363
1364 /****************************************/
1365 /* Reset and Channel Switching Routines */
1366 /****************************************/
1367
1368 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1369 {
1370         u32 rfMode = 0;
1371
1372         if (chan == NULL)
1373                 return;
1374
1375         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1376                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1377
1378         if (!AR_SREV_9280_10_OR_LATER(ah))
1379                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1380                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1381
1382         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1383                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1384
1385         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1386 }
1387
1388 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1389 {
1390         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1391 }
1392
1393 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1394 {
1395         u32 regval;
1396
1397         regval = REG_READ(ah, AR_AHB_MODE);
1398         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1399
1400         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1401         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1402
1403         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1404
1405         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1406         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1407
1408         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1409
1410         if (AR_SREV_9285(ah)) {
1411                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1412                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1413         } else {
1414                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1415                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1416         }
1417 }
1418
1419 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1420 {
1421         u32 val;
1422
1423         val = REG_READ(ah, AR_STA_ID1);
1424         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1425         switch (opmode) {
1426         case ATH9K_M_HOSTAP:
1427                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1428                           | AR_STA_ID1_KSRCH_MODE);
1429                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1430                 break;
1431         case ATH9K_M_IBSS:
1432                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1433                           | AR_STA_ID1_KSRCH_MODE);
1434                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1435                 break;
1436         case ATH9K_M_STA:
1437         case ATH9K_M_MONITOR:
1438                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1439                 break;
1440         }
1441 }
1442
1443 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1444                                                  u32 coef_scaled,
1445                                                  u32 *coef_mantissa,
1446                                                  u32 *coef_exponent)
1447 {
1448         u32 coef_exp, coef_man;
1449
1450         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1451                 if ((coef_scaled >> coef_exp) & 0x1)
1452                         break;
1453
1454         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1455
1456         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1457
1458         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1459         *coef_exponent = coef_exp - 16;
1460 }
1461
1462 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1463                                      struct ath9k_channel *chan)
1464 {
1465         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1466         u32 clockMhzScaled = 0x64000000;
1467         struct chan_centers centers;
1468
1469         if (IS_CHAN_HALF_RATE(chan))
1470                 clockMhzScaled = clockMhzScaled >> 1;
1471         else if (IS_CHAN_QUARTER_RATE(chan))
1472                 clockMhzScaled = clockMhzScaled >> 2;
1473
1474         ath9k_hw_get_channel_centers(ah, chan, &centers);
1475         coef_scaled = clockMhzScaled / centers.synth_center;
1476
1477         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1478                                       &ds_coef_exp);
1479
1480         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1481                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1482         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1483                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1484
1485         coef_scaled = (9 * coef_scaled) / 10;
1486
1487         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1488                                       &ds_coef_exp);
1489
1490         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1491                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1492         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1493                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1494 }
1495
1496 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1497 {
1498         u32 rst_flags;
1499         u32 tmpReg;
1500
1501         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1502                   AR_RTC_FORCE_WAKE_ON_INT);
1503
1504         if (AR_SREV_9100(ah)) {
1505                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1506                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1507         } else {
1508                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1509                 if (tmpReg &
1510                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1511                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1512                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1513                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1514                 } else {
1515                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1516                 }
1517
1518                 rst_flags = AR_RTC_RC_MAC_WARM;
1519                 if (type == ATH9K_RESET_COLD)
1520                         rst_flags |= AR_RTC_RC_MAC_COLD;
1521         }
1522
1523         REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1524         udelay(50);
1525
1526         REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1527         if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1528                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1529                         "RTC stuck in MAC reset\n");
1530                 return false;
1531         }
1532
1533         if (!AR_SREV_9100(ah))
1534                 REG_WRITE(ah, AR_RC, 0);
1535
1536         ath9k_hw_init_pll(ah, NULL);
1537
1538         if (AR_SREV_9100(ah))
1539                 udelay(50);
1540
1541         return true;
1542 }
1543
1544 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1545 {
1546         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1547                   AR_RTC_FORCE_WAKE_ON_INT);
1548
1549         REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1550         REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1551
1552         if (!ath9k_hw_wait(ah,
1553                            AR_RTC_STATUS,
1554                            AR_RTC_STATUS_M,
1555                            AR_RTC_STATUS_ON)) {
1556                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1557                 return false;
1558         }
1559
1560         ath9k_hw_read_revisions(ah);
1561
1562         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1563 }
1564
1565 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1566 {
1567         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1568                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1569
1570         switch (type) {
1571         case ATH9K_RESET_POWER_ON:
1572                 return ath9k_hw_set_reset_power_on(ah);
1573                 break;
1574         case ATH9K_RESET_WARM:
1575         case ATH9K_RESET_COLD:
1576                 return ath9k_hw_set_reset(ah, type);
1577                 break;
1578         default:
1579                 return false;
1580         }
1581 }
1582
1583 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1584                               enum ath9k_ht_macmode macmode)
1585 {
1586         u32 phymode;
1587         struct ath_hal_5416 *ahp = AH5416(ah);
1588
1589         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1590                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1591
1592         if (IS_CHAN_HT40(chan)) {
1593                 phymode |= AR_PHY_FC_DYN2040_EN;
1594
1595                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1596                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1597                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1598
1599                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1600                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1601         }
1602         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1603
1604         ath9k_hw_set11nmac2040(ah, macmode);
1605
1606         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1607         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1608 }
1609
1610 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1611                                 struct ath9k_channel *chan)
1612 {
1613         struct ath_hal_5416 *ahp = AH5416(ah);
1614
1615         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1616                 return false;
1617
1618         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1619                 return false;
1620
1621         ahp->ah_chipFullSleep = false;
1622
1623         ath9k_hw_init_pll(ah, chan);
1624
1625         ath9k_hw_set_rfmode(ah, chan);
1626
1627         return true;
1628 }
1629
1630 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1631                                                  struct ath9k_channel *chan)
1632 {
1633         if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1634                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1635                         "invalid channel %u/0x%x; not marked as "
1636                         "2GHz or 5GHz\n", chan->channel, chan->channelFlags);
1637                 return NULL;
1638         }
1639
1640         if (!IS_CHAN_OFDM(chan) &&
1641             !IS_CHAN_B(chan) &&
1642             !IS_CHAN_HT20(chan) &&
1643             !IS_CHAN_HT40(chan)) {
1644                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1645                         "invalid channel %u/0x%x; not marked as "
1646                         "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1647                         chan->channel, chan->channelFlags);
1648                 return NULL;
1649         }
1650
1651         return ath9k_regd_check_channel(ah, chan);
1652 }
1653
1654 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1655                                     struct ath9k_channel *chan,
1656                                     enum ath9k_ht_macmode macmode)
1657 {
1658         u32 synthDelay, qnum;
1659
1660         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1661                 if (ath9k_hw_numtxpending(ah, qnum)) {
1662                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1663                                 "Transmit frames pending on queue %d\n", qnum);
1664                         return false;
1665                 }
1666         }
1667
1668         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1669         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1670                            AR_PHY_RFBUS_GRANT_EN)) {
1671                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1672                         "Could not kill baseband RX\n");
1673                 return false;
1674         }
1675
1676         ath9k_hw_set_regs(ah, chan, macmode);
1677
1678         if (AR_SREV_9280_10_OR_LATER(ah)) {
1679                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1680                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1681                                 "failed to set channel\n");
1682                         return false;
1683                 }
1684         } else {
1685                 if (!(ath9k_hw_set_channel(ah, chan))) {
1686                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1687                                 "failed to set channel\n");
1688                         return false;
1689                 }
1690         }
1691
1692         if (ath9k_hw_set_txpower(ah, chan,
1693                                  ath9k_regd_get_ctl(ah, chan),
1694                                  ath9k_regd_get_antenna_allowed(ah, chan),
1695                                  chan->maxRegTxPower * 2,
1696                                  min((u32) MAX_RATE_POWER,
1697                                      (u32) ah->ah_powerLimit)) != 0) {
1698                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1699                         "error init'ing transmit power\n");
1700                 return false;
1701         }
1702
1703         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1704         if (IS_CHAN_B(chan))
1705                 synthDelay = (4 * synthDelay) / 22;
1706         else
1707                 synthDelay /= 10;
1708
1709         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1710
1711         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1712
1713         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1714                 ath9k_hw_set_delta_slope(ah, chan);
1715
1716         if (AR_SREV_9280_10_OR_LATER(ah))
1717                 ath9k_hw_9280_spur_mitigate(ah, chan);
1718         else
1719                 ath9k_hw_spur_mitigate(ah, chan);
1720
1721         if (!chan->oneTimeCalsDone)
1722                 chan->oneTimeCalsDone = true;
1723
1724         return true;
1725 }
1726
1727 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1728 {
1729         int bb_spur = AR_NO_SPUR;
1730         int freq;
1731         int bin, cur_bin;
1732         int bb_spur_off, spur_subchannel_sd;
1733         int spur_freq_sd;
1734         int spur_delta_phase;
1735         int denominator;
1736         int upper, lower, cur_vit_mask;
1737         int tmp, newVal;
1738         int i;
1739         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1740                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1741         };
1742         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1743                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1744         };
1745         int inc[4] = { 0, 100, 0, 0 };
1746         struct chan_centers centers;
1747
1748         int8_t mask_m[123];
1749         int8_t mask_p[123];
1750         int8_t mask_amt;
1751         int tmp_mask;
1752         int cur_bb_spur;
1753         bool is2GHz = IS_CHAN_2GHZ(chan);
1754
1755         memset(&mask_m, 0, sizeof(int8_t) * 123);
1756         memset(&mask_p, 0, sizeof(int8_t) * 123);
1757
1758         ath9k_hw_get_channel_centers(ah, chan, &centers);
1759         freq = centers.synth_center;
1760
1761         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1762         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1763                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1764
1765                 if (is2GHz)
1766                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1767                 else
1768                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1769
1770                 if (AR_NO_SPUR == cur_bb_spur)
1771                         break;
1772                 cur_bb_spur = cur_bb_spur - freq;
1773
1774                 if (IS_CHAN_HT40(chan)) {
1775                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1776                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1777                                 bb_spur = cur_bb_spur;
1778                                 break;
1779                         }
1780                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1781                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1782                         bb_spur = cur_bb_spur;
1783                         break;
1784                 }
1785         }
1786
1787         if (AR_NO_SPUR == bb_spur) {
1788                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1789                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1790                 return;
1791         } else {
1792                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1793                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1794         }
1795
1796         bin = bb_spur * 320;
1797
1798         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1799
1800         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1801                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1802                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1803                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1804         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1805
1806         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1807                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1808                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1809                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1810                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1811         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1812
1813         if (IS_CHAN_HT40(chan)) {
1814                 if (bb_spur < 0) {
1815                         spur_subchannel_sd = 1;
1816                         bb_spur_off = bb_spur + 10;
1817                 } else {
1818                         spur_subchannel_sd = 0;
1819                         bb_spur_off = bb_spur - 10;
1820                 }
1821         } else {
1822                 spur_subchannel_sd = 0;
1823                 bb_spur_off = bb_spur;
1824         }
1825
1826         if (IS_CHAN_HT40(chan))
1827                 spur_delta_phase =
1828                         ((bb_spur * 262144) /
1829                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1830         else
1831                 spur_delta_phase =
1832                         ((bb_spur * 524288) /
1833                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1834
1835         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1836         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1837
1838         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1839                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1840                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1841         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1842
1843         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1844         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1845
1846         cur_bin = -6000;
1847         upper = bin + 100;
1848         lower = bin - 100;
1849
1850         for (i = 0; i < 4; i++) {
1851                 int pilot_mask = 0;
1852                 int chan_mask = 0;
1853                 int bp = 0;
1854                 for (bp = 0; bp < 30; bp++) {
1855                         if ((cur_bin > lower) && (cur_bin < upper)) {
1856                                 pilot_mask = pilot_mask | 0x1 << bp;
1857                                 chan_mask = chan_mask | 0x1 << bp;
1858                         }
1859                         cur_bin += 100;
1860                 }
1861                 cur_bin += inc[i];
1862                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1863                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1864         }
1865
1866         cur_vit_mask = 6100;
1867         upper = bin + 120;
1868         lower = bin - 120;
1869
1870         for (i = 0; i < 123; i++) {
1871                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1872
1873                         /* workaround for gcc bug #37014 */
1874                         volatile int tmp = abs(cur_vit_mask - bin);
1875
1876                         if (tmp < 75)
1877                                 mask_amt = 1;
1878                         else
1879                                 mask_amt = 0;
1880                         if (cur_vit_mask < 0)
1881                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1882                         else
1883                                 mask_p[cur_vit_mask / 100] = mask_amt;
1884                 }
1885                 cur_vit_mask -= 100;
1886         }
1887
1888         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1889                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1890                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1891                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1892                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1893                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1894                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1895                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1896         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1897         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1898
1899         tmp_mask = (mask_m[31] << 28)
1900                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1901                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1902                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1903                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1904                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1905                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1906                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1907         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1908         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1909
1910         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1911                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1912                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1913                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1914                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1915                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1916                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1917                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1918         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1919         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1920
1921         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1922                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1923                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1924                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1925                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1926                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1927                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1928                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1929         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1930         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1931
1932         tmp_mask = (mask_p[15] << 28)
1933                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1934                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1935                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1936                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1937                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1938                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1939                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1940         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1941         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1942
1943         tmp_mask = (mask_p[30] << 28)
1944                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1945                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1946                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1947                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1948                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1949                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1950                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1951         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1952         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1953
1954         tmp_mask = (mask_p[45] << 28)
1955                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1956                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1957                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1958                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1959                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1960                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1961                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1962         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1963         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1964
1965         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1966                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1967                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1968                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1969                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1970                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1971                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1972                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1973         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1974         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1975 }
1976
1977 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1978 {
1979         int bb_spur = AR_NO_SPUR;
1980         int bin, cur_bin;
1981         int spur_freq_sd;
1982         int spur_delta_phase;
1983         int denominator;
1984         int upper, lower, cur_vit_mask;
1985         int tmp, new;
1986         int i;
1987         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1988                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1989         };
1990         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1991                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1992         };
1993         int inc[4] = { 0, 100, 0, 0 };
1994
1995         int8_t mask_m[123];
1996         int8_t mask_p[123];
1997         int8_t mask_amt;
1998         int tmp_mask;
1999         int cur_bb_spur;
2000         bool is2GHz = IS_CHAN_2GHZ(chan);
2001
2002         memset(&mask_m, 0, sizeof(int8_t) * 123);
2003         memset(&mask_p, 0, sizeof(int8_t) * 123);
2004
2005         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2006                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2007                 if (AR_NO_SPUR == cur_bb_spur)
2008                         break;
2009                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2010                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2011                         bb_spur = cur_bb_spur;
2012                         break;
2013                 }
2014         }
2015
2016         if (AR_NO_SPUR == bb_spur)
2017                 return;
2018
2019         bin = bb_spur * 32;
2020
2021         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2022         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2023                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2024                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2025                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2026
2027         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2028
2029         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2030                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2031                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2032                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2033                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2034         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2035
2036         spur_delta_phase = ((bb_spur * 524288) / 100) &
2037                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2038
2039         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2040         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2041
2042         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2043                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2044                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2045         REG_WRITE(ah, AR_PHY_TIMING11, new);
2046
2047         cur_bin = -6000;
2048         upper = bin + 100;
2049         lower = bin - 100;
2050
2051         for (i = 0; i < 4; i++) {
2052                 int pilot_mask = 0;
2053                 int chan_mask = 0;
2054                 int bp = 0;
2055                 for (bp = 0; bp < 30; bp++) {
2056                         if ((cur_bin > lower) && (cur_bin < upper)) {
2057                                 pilot_mask = pilot_mask | 0x1 << bp;
2058                                 chan_mask = chan_mask | 0x1 << bp;
2059                         }
2060                         cur_bin += 100;
2061                 }
2062                 cur_bin += inc[i];
2063                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2064                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2065         }
2066
2067         cur_vit_mask = 6100;
2068         upper = bin + 120;
2069         lower = bin - 120;
2070
2071         for (i = 0; i < 123; i++) {
2072                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2073
2074                         /* workaround for gcc bug #37014 */
2075                         volatile int tmp = abs(cur_vit_mask - bin);
2076
2077                         if (tmp < 75)
2078                                 mask_amt = 1;
2079                         else
2080                                 mask_amt = 0;
2081                         if (cur_vit_mask < 0)
2082                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2083                         else
2084                                 mask_p[cur_vit_mask / 100] = mask_amt;
2085                 }
2086                 cur_vit_mask -= 100;
2087         }
2088
2089         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2090                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2091                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2092                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2093                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2094                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2095                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2096                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2097         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2098         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2099
2100         tmp_mask = (mask_m[31] << 28)
2101                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2102                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2103                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2104                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2105                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2106                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2107                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2108         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2109         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2110
2111         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2112                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2113                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2114                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2115                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2116                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2117                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2118                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2119         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2120         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2121
2122         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2123                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2124                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2125                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2126                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2127                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2128                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2129                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2130         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2131         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2132
2133         tmp_mask = (mask_p[15] << 28)
2134                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2135                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2136                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2137                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2138                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2139                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2140                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2141         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2142         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2143
2144         tmp_mask = (mask_p[30] << 28)
2145                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2146                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2147                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2148                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2149                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2150                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2151                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2152         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2153         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2154
2155         tmp_mask = (mask_p[45] << 28)
2156                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2157                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2158                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2159                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2160                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2161                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2162                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2163         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2164         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2165
2166         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2167                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2168                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2169                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2170                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2171                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2172                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2173                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2174         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2175         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2176 }
2177
2178 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2179                     enum ath9k_ht_macmode macmode,
2180                     u8 txchainmask, u8 rxchainmask,
2181                     enum ath9k_ht_extprotspacing extprotspacing,
2182                     bool bChannelChange, int *status)
2183 {
2184         u32 saveLedState;
2185         struct ath_hal_5416 *ahp = AH5416(ah);
2186         struct ath9k_channel *curchan = ah->ah_curchan;
2187         u32 saveDefAntenna;
2188         u32 macStaId1;
2189         int ecode;
2190         int i, rx_chainmask;
2191
2192         ahp->ah_extprotspacing = extprotspacing;
2193         ahp->ah_txchainmask = txchainmask;
2194         ahp->ah_rxchainmask = rxchainmask;
2195
2196         if (AR_SREV_9280(ah)) {
2197                 ahp->ah_txchainmask &= 0x3;
2198                 ahp->ah_rxchainmask &= 0x3;
2199         }
2200
2201         if (ath9k_hw_check_chan(ah, chan) == NULL) {
2202                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2203                         "invalid channel %u/0x%x; no mapping\n",
2204                         chan->channel, chan->channelFlags);
2205                 ecode = -EINVAL;
2206                 goto bad;
2207         }
2208
2209         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2210                 ecode = -EIO;
2211                 goto bad;
2212         }
2213
2214         if (curchan)
2215                 ath9k_hw_getnf(ah, curchan);
2216
2217         if (bChannelChange &&
2218             (ahp->ah_chipFullSleep != true) &&
2219             (ah->ah_curchan != NULL) &&
2220             (chan->channel != ah->ah_curchan->channel) &&
2221             ((chan->channelFlags & CHANNEL_ALL) ==
2222              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2223             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2224                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2225
2226                 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2227                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2228                         ath9k_hw_start_nfcal(ah);
2229                         return true;
2230                 }
2231         }
2232
2233         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2234         if (saveDefAntenna == 0)
2235                 saveDefAntenna = 1;
2236
2237         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2238
2239         saveLedState = REG_READ(ah, AR_CFG_LED) &
2240                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2241                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2242
2243         ath9k_hw_mark_phy_inactive(ah);
2244
2245         if (!ath9k_hw_chip_reset(ah, chan)) {
2246                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2247                 ecode = -EINVAL;
2248                 goto bad;
2249         }
2250
2251         if (AR_SREV_9280(ah)) {
2252                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2253                             AR_GPIO_JTAG_DISABLE);
2254
2255                 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2256                         if (IS_CHAN_5GHZ(chan))
2257                                 ath9k_hw_set_gpio(ah, 9, 0);
2258                         else
2259                                 ath9k_hw_set_gpio(ah, 9, 1);
2260                 }
2261                 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2262         }
2263
2264         ecode = ath9k_hw_process_ini(ah, chan, macmode);
2265         if (ecode != 0) {
2266                 ecode = -EINVAL;
2267                 goto bad;
2268         }
2269
2270         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2271                 ath9k_hw_set_delta_slope(ah, chan);
2272
2273         if (AR_SREV_9280_10_OR_LATER(ah))
2274                 ath9k_hw_9280_spur_mitigate(ah, chan);
2275         else
2276                 ath9k_hw_spur_mitigate(ah, chan);
2277
2278         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2279                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2280                         "error setting board options\n");
2281                 ecode = -EIO;
2282                 goto bad;
2283         }
2284
2285         ath9k_hw_decrease_chain_power(ah, chan);
2286
2287         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2288         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2289                   | macStaId1
2290                   | AR_STA_ID1_RTS_USE_DEF
2291                   | (ah->ah_config.
2292                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2293                   | ahp->ah_staId1Defaults);
2294         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2295
2296         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2297         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2298
2299         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2300
2301         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2302         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2303                   ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2304
2305         REG_WRITE(ah, AR_ISR, ~0);
2306
2307         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2308
2309         if (AR_SREV_9280_10_OR_LATER(ah)) {
2310                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2311                         ecode = -EIO;
2312                         goto bad;
2313                 }
2314         } else {
2315                 if (!(ath9k_hw_set_channel(ah, chan))) {
2316                         ecode = -EIO;
2317                         goto bad;
2318                 }
2319         }
2320
2321         for (i = 0; i < AR_NUM_DCU; i++)
2322                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2323
2324         ahp->ah_intrTxqs = 0;
2325         for (i = 0; i < ah->ah_caps.total_queues; i++)
2326                 ath9k_hw_resettxqueue(ah, i);
2327
2328         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2329         ath9k_hw_init_qos(ah);
2330
2331 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2332         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2333                 ath9k_enable_rfkill(ah);
2334 #endif
2335         ath9k_hw_init_user_settings(ah);
2336
2337         REG_WRITE(ah, AR_STA_ID1,
2338                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2339
2340         ath9k_hw_set_dma(ah);
2341
2342         REG_WRITE(ah, AR_OBS, 8);
2343
2344         if (ahp->ah_intrMitigation) {
2345
2346                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2347                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2348         }
2349
2350         ath9k_hw_init_bb(ah, chan);
2351
2352         if (!ath9k_hw_init_cal(ah, chan)){
2353                 ecode = -EIO;;
2354                 goto bad;
2355         }
2356
2357         rx_chainmask = ahp->ah_rxchainmask;
2358         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2359                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2360                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2361         }
2362
2363         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2364
2365         if (AR_SREV_9100(ah)) {
2366                 u32 mask;
2367                 mask = REG_READ(ah, AR_CFG);
2368                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2369                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2370                                 "CFG Byte Swap Set 0x%x\n", mask);
2371                 } else {
2372                         mask =
2373                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2374                         REG_WRITE(ah, AR_CFG, mask);
2375                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2376                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2377                 }
2378         } else {
2379 #ifdef __BIG_ENDIAN
2380                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2381 #endif
2382         }
2383
2384         return true;
2385 bad:
2386         if (status)
2387                 *status = ecode;
2388         return false;
2389 }
2390
2391 /************************/
2392 /* Key Cache Management */
2393 /************************/
2394
2395 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2396 {
2397         u32 keyType;
2398
2399         if (entry >= ah->ah_caps.keycache_size) {
2400                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2401                         "entry %u out of range\n", entry);
2402                 return false;
2403         }
2404
2405         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2406
2407         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2408         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2409         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2410         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2411         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2412         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2413         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2414         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2415
2416         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2417                 u16 micentry = entry + 64;
2418
2419                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2420                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2421                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2422                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2423
2424         }
2425
2426         if (ah->ah_curchan == NULL)
2427                 return true;
2428
2429         return true;
2430 }
2431
2432 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2433 {
2434         u32 macHi, macLo;
2435
2436         if (entry >= ah->ah_caps.keycache_size) {
2437                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2438                         "entry %u out of range\n", entry);
2439                 return false;
2440         }
2441
2442         if (mac != NULL) {
2443                 macHi = (mac[5] << 8) | mac[4];
2444                 macLo = (mac[3] << 24) |
2445                         (mac[2] << 16) |
2446                         (mac[1] << 8) |
2447                         mac[0];
2448                 macLo >>= 1;
2449                 macLo |= (macHi & 1) << 31;
2450                 macHi >>= 1;
2451         } else {
2452                 macLo = macHi = 0;
2453         }
2454         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2455         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2456
2457         return true;
2458 }
2459
2460 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2461                                  const struct ath9k_keyval *k,
2462                                  const u8 *mac, int xorKey)
2463 {
2464         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2465         u32 key0, key1, key2, key3, key4;
2466         u32 keyType;
2467         u32 xorMask = xorKey ?
2468                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2469                  | ATH9K_KEY_XOR) : 0;
2470         struct ath_hal_5416 *ahp = AH5416(ah);
2471
2472         if (entry >= pCap->keycache_size) {
2473                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2474                         "entry %u out of range\n", entry);
2475                 return false;
2476         }
2477
2478         switch (k->kv_type) {
2479         case ATH9K_CIPHER_AES_OCB:
2480                 keyType = AR_KEYTABLE_TYPE_AES;
2481                 break;
2482         case ATH9K_CIPHER_AES_CCM:
2483                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2484                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2485                                 "AES-CCM not supported by mac rev 0x%x\n",
2486                                 ah->ah_macRev);
2487                         return false;
2488                 }
2489                 keyType = AR_KEYTABLE_TYPE_CCM;
2490                 break;
2491         case ATH9K_CIPHER_TKIP:
2492                 keyType = AR_KEYTABLE_TYPE_TKIP;
2493                 if (ATH9K_IS_MIC_ENABLED(ah)
2494                     && entry + 64 >= pCap->keycache_size) {
2495                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2496                                 "entry %u inappropriate for TKIP\n", entry);
2497                         return false;
2498                 }
2499                 break;
2500         case ATH9K_CIPHER_WEP:
2501                 if (k->kv_len < LEN_WEP40) {
2502                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2503                                 "WEP key length %u too small\n", k->kv_len);
2504                         return false;
2505                 }
2506                 if (k->kv_len <= LEN_WEP40)
2507                         keyType = AR_KEYTABLE_TYPE_40;
2508                 else if (k->kv_len <= LEN_WEP104)
2509                         keyType = AR_KEYTABLE_TYPE_104;
2510                 else
2511                         keyType = AR_KEYTABLE_TYPE_128;
2512                 break;
2513         case ATH9K_CIPHER_CLR:
2514                 keyType = AR_KEYTABLE_TYPE_CLR;
2515                 break;
2516         default:
2517                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2518                         "cipher %u not supported\n", k->kv_type);
2519                 return false;
2520         }
2521
2522         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2523         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2524         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2525         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2526         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2527         if (k->kv_len <= LEN_WEP104)
2528                 key4 &= 0xff;
2529
2530         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2531                 u16 micentry = entry + 64;
2532
2533                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2534                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2535                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2536                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2537                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2538                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2539                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2540
2541                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2542                         u32 mic0, mic1, mic2, mic3, mic4;
2543
2544                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2545                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2546                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2547                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2548                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2549                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2550                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2551                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2552                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2553                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2554                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2555                                   AR_KEYTABLE_TYPE_CLR);
2556
2557                 } else {
2558                         u32 mic0, mic2;
2559
2560                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2561                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2562                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2563                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2564                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2565                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2566                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2567                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2568                                   AR_KEYTABLE_TYPE_CLR);
2569                 }
2570                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2571                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2572                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2573                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2574         } else {
2575                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2576                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2577                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2578                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2579                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2580                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2581
2582                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2583         }
2584
2585         if (ah->ah_curchan == NULL)
2586                 return true;
2587
2588         return true;
2589 }
2590
2591 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2592 {
2593         if (entry < ah->ah_caps.keycache_size) {
2594                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2595                 if (val & AR_KEYTABLE_VALID)
2596                         return true;
2597         }
2598         return false;
2599 }
2600
2601 /******************************/
2602 /* Power Management (Chipset) */
2603 /******************************/
2604
2605 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2606 {
2607         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2608         if (setChip) {
2609                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2610                             AR_RTC_FORCE_WAKE_EN);
2611                 if (!AR_SREV_9100(ah))
2612                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2613
2614                 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2615                             AR_RTC_RESET_EN);
2616         }
2617 }
2618
2619 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2620 {
2621         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2622         if (setChip) {
2623                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2624
2625                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2626                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2627                                   AR_RTC_FORCE_WAKE_ON_INT);
2628                 } else {
2629                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2630                                     AR_RTC_FORCE_WAKE_EN);
2631                 }
2632         }
2633 }
2634
2635 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2636                                      int setChip)
2637 {
2638         u32 val;
2639         int i;
2640
2641         if (setChip) {
2642                 if ((REG_READ(ah, AR_RTC_STATUS) &
2643                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2644                         if (ath9k_hw_set_reset_reg(ah,
2645                                            ATH9K_RESET_POWER_ON) != true) {
2646                                 return false;
2647                         }
2648                 }
2649                 if (AR_SREV_9100(ah))
2650                         REG_SET_BIT(ah, AR_RTC_RESET,
2651                                     AR_RTC_RESET_EN);
2652
2653                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2654                             AR_RTC_FORCE_WAKE_EN);
2655                 udelay(50);
2656
2657                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2658                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2659                         if (val == AR_RTC_STATUS_ON)
2660                                 break;
2661                         udelay(50);
2662                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2663                                     AR_RTC_FORCE_WAKE_EN);
2664                 }
2665                 if (i == 0) {
2666                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2667                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2668                         return false;
2669                 }
2670         }
2671
2672         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2673
2674         return true;
2675 }
2676
2677 bool ath9k_hw_setpower(struct ath_hal *ah,
2678                        enum ath9k_power_mode mode)
2679 {
2680         struct ath_hal_5416 *ahp = AH5416(ah);
2681         static const char *modes[] = {
2682                 "AWAKE",
2683                 "FULL-SLEEP",
2684                 "NETWORK SLEEP",
2685                 "UNDEFINED"
2686         };
2687         int status = true, setChip = true;
2688
2689         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2690                 modes[ahp->ah_powerMode], modes[mode],
2691                 setChip ? "set chip " : "");
2692
2693         switch (mode) {
2694         case ATH9K_PM_AWAKE:
2695                 status = ath9k_hw_set_power_awake(ah, setChip);
2696                 break;
2697         case ATH9K_PM_FULL_SLEEP:
2698                 ath9k_set_power_sleep(ah, setChip);
2699                 ahp->ah_chipFullSleep = true;
2700                 break;
2701         case ATH9K_PM_NETWORK_SLEEP:
2702                 ath9k_set_power_network_sleep(ah, setChip);
2703                 break;
2704         default:
2705                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2706                         "Unknown power mode %u\n", mode);
2707                 return false;
2708         }
2709         ahp->ah_powerMode = mode;
2710
2711         return status;
2712 }
2713
2714 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2715 {
2716         struct ath_hal_5416 *ahp = AH5416(ah);
2717         u8 i;
2718
2719         if (ah->ah_isPciExpress != true)
2720                 return;
2721
2722         if (ah->ah_config.pcie_powersave_enable == 2)
2723                 return;
2724
2725         if (restore)
2726                 return;
2727
2728         if (AR_SREV_9280_20_OR_LATER(ah)) {
2729                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2730                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2731                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2732                 }
2733                 udelay(1000);
2734         } else if (AR_SREV_9280(ah) &&
2735                    (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2736                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2737                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2738
2739                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2740                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2741                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2742
2743                 if (ah->ah_config.pcie_clock_req)
2744                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2745                 else
2746                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2747
2748                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2749                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2750                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2751
2752                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2753
2754                 udelay(1000);
2755         } else {
2756                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2757                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2758                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2759                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2760                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2761                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2762                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2763                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2764                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2765                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2766         }
2767
2768         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2769
2770         if (ah->ah_config.pcie_waen) {
2771                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2772         } else {
2773                 if (AR_SREV_9280(ah))
2774                         REG_WRITE(ah, AR_WA, 0x0040073f);
2775                 else
2776                         REG_WRITE(ah, AR_WA, 0x0000073f);
2777         }
2778 }
2779
2780 /**********************/
2781 /* Interrupt Handling */
2782 /**********************/
2783
2784 bool ath9k_hw_intrpend(struct ath_hal *ah)
2785 {
2786         u32 host_isr;
2787
2788         if (AR_SREV_9100(ah))
2789                 return true;
2790
2791         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2792         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2793                 return true;
2794
2795         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2796         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2797             && (host_isr != AR_INTR_SPURIOUS))
2798                 return true;
2799
2800         return false;
2801 }
2802
2803 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2804 {
2805         u32 isr = 0;
2806         u32 mask2 = 0;
2807         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2808         u32 sync_cause = 0;
2809         bool fatal_int = false;
2810         struct ath_hal_5416 *ahp = AH5416(ah);
2811
2812         if (!AR_SREV_9100(ah)) {
2813                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2814                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2815                             == AR_RTC_STATUS_ON) {
2816                                 isr = REG_READ(ah, AR_ISR);
2817                         }
2818                 }
2819
2820                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2821                         AR_INTR_SYNC_DEFAULT;
2822
2823                 *masked = 0;
2824
2825                 if (!isr && !sync_cause)
2826                         return false;
2827         } else {
2828                 *masked = 0;
2829                 isr = REG_READ(ah, AR_ISR);
2830         }
2831
2832         if (isr) {
2833                 if (isr & AR_ISR_BCNMISC) {
2834                         u32 isr2;
2835                         isr2 = REG_READ(ah, AR_ISR_S2);
2836                         if (isr2 & AR_ISR_S2_TIM)
2837                                 mask2 |= ATH9K_INT_TIM;
2838                         if (isr2 & AR_ISR_S2_DTIM)
2839                                 mask2 |= ATH9K_INT_DTIM;
2840                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2841                                 mask2 |= ATH9K_INT_DTIMSYNC;
2842                         if (isr2 & (AR_ISR_S2_CABEND))
2843                                 mask2 |= ATH9K_INT_CABEND;
2844                         if (isr2 & AR_ISR_S2_GTT)
2845                                 mask2 |= ATH9K_INT_GTT;
2846                         if (isr2 & AR_ISR_S2_CST)
2847                                 mask2 |= ATH9K_INT_CST;
2848                 }
2849
2850                 isr = REG_READ(ah, AR_ISR_RAC);
2851                 if (isr == 0xffffffff) {
2852                         *masked = 0;
2853                         return false;
2854                 }
2855
2856                 *masked = isr & ATH9K_INT_COMMON;
2857
2858                 if (ahp->ah_intrMitigation) {
2859                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2860                                 *masked |= ATH9K_INT_RX;
2861                 }
2862
2863                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2864                         *masked |= ATH9K_INT_RX;
2865                 if (isr &
2866                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2867                      AR_ISR_TXEOL)) {
2868                         u32 s0_s, s1_s;
2869
2870                         *masked |= ATH9K_INT_TX;
2871
2872                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2873                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2874                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2875
2876                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2877                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2878                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2879                 }
2880
2881                 if (isr & AR_ISR_RXORN) {
2882                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2883                                 "receive FIFO overrun interrupt\n");
2884                 }
2885
2886                 if (!AR_SREV_9100(ah)) {
2887                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2888                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2889                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2890                                         *masked |= ATH9K_INT_TIM_TIMER;
2891                         }
2892                 }
2893
2894                 *masked |= mask2;
2895         }
2896
2897         if (AR_SREV_9100(ah))
2898                 return true;
2899
2900         if (sync_cause) {
2901                 fatal_int =
2902                         (sync_cause &
2903                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2904                         ? true : false;
2905
2906                 if (fatal_int) {
2907                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2908                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2909                                         "received PCI FATAL interrupt\n");
2910                         }
2911                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2912                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2913                                         "received PCI PERR interrupt\n");
2914                         }
2915                 }
2916                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2917                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2918                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2919                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2920                         REG_WRITE(ah, AR_RC, 0);
2921                         *masked |= ATH9K_INT_FATAL;
2922                 }
2923                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2924                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2925                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2926                 }
2927
2928                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2929                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2930         }
2931
2932         return true;
2933 }
2934
2935 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2936 {
2937         return AH5416(ah)->ah_maskReg;
2938 }
2939
2940 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2941 {
2942         struct ath_hal_5416 *ahp = AH5416(ah);
2943         u32 omask = ahp->ah_maskReg;
2944         u32 mask, mask2;
2945         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2946
2947         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2948
2949         if (omask & ATH9K_INT_GLOBAL) {
2950                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2951                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2952                 (void) REG_READ(ah, AR_IER);
2953                 if (!AR_SREV_9100(ah)) {
2954                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2955                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2956
2957                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2958                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2959                 }
2960         }
2961
2962         mask = ints & ATH9K_INT_COMMON;
2963         mask2 = 0;
2964
2965         if (ints & ATH9K_INT_TX) {
2966                 if (ahp->ah_txOkInterruptMask)
2967                         mask |= AR_IMR_TXOK;
2968                 if (ahp->ah_txDescInterruptMask)
2969                         mask |= AR_IMR_TXDESC;
2970                 if (ahp->ah_txErrInterruptMask)
2971                         mask |= AR_IMR_TXERR;
2972                 if (ahp->ah_txEolInterruptMask)
2973                         mask |= AR_IMR_TXEOL;
2974         }
2975         if (ints & ATH9K_INT_RX) {
2976                 mask |= AR_IMR_RXERR;
2977                 if (ahp->ah_intrMitigation)
2978                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2979                 else
2980                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2981                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2982                         mask |= AR_IMR_GENTMR;
2983         }
2984
2985         if (ints & (ATH9K_INT_BMISC)) {
2986                 mask |= AR_IMR_BCNMISC;
2987                 if (ints & ATH9K_INT_TIM)
2988                         mask2 |= AR_IMR_S2_TIM;
2989                 if (ints & ATH9K_INT_DTIM)
2990                         mask2 |= AR_IMR_S2_DTIM;
2991                 if (ints & ATH9K_INT_DTIMSYNC)
2992                         mask2 |= AR_IMR_S2_DTIMSYNC;
2993                 if (ints & ATH9K_INT_CABEND)
2994                         mask2 |= (AR_IMR_S2_CABEND);
2995         }
2996
2997         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2998                 mask |= AR_IMR_BCNMISC;
2999                 if (ints & ATH9K_INT_GTT)
3000                         mask2 |= AR_IMR_S2_GTT;
3001                 if (ints & ATH9K_INT_CST)
3002                         mask2 |= AR_IMR_S2_CST;
3003         }
3004
3005         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3006         REG_WRITE(ah, AR_IMR, mask);
3007         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3008                                            AR_IMR_S2_DTIM |
3009                                            AR_IMR_S2_DTIMSYNC |
3010                                            AR_IMR_S2_CABEND |
3011                                            AR_IMR_S2_CABTO |
3012                                            AR_IMR_S2_TSFOOR |
3013                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3014         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3015         ahp->ah_maskReg = ints;
3016
3017         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3018                 if (ints & ATH9K_INT_TIM_TIMER)
3019                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3020                 else
3021                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3022         }
3023
3024         if (ints & ATH9K_INT_GLOBAL) {
3025                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3026                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3027                 if (!AR_SREV_9100(ah)) {
3028                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3029                                   AR_INTR_MAC_IRQ);
3030                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3031
3032
3033                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3034                                   AR_INTR_SYNC_DEFAULT);
3035                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3036                                   AR_INTR_SYNC_DEFAULT);
3037                 }
3038                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3039                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3040         }
3041
3042         return omask;
3043 }
3044
3045 /*******************/
3046 /* Beacon Handling */
3047 /*******************/
3048
3049 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3050 {
3051         struct ath_hal_5416 *ahp = AH5416(ah);
3052         int flags = 0;
3053
3054         ahp->ah_beaconInterval = beacon_period;
3055
3056         switch (ah->ah_opmode) {
3057         case ATH9K_M_STA:
3058         case ATH9K_M_MONITOR:
3059                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3060                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3061                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3062                 flags |= AR_TBTT_TIMER_EN;
3063                 break;
3064         case ATH9K_M_IBSS:
3065                 REG_SET_BIT(ah, AR_TXCFG,
3066                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3067                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3068                           TU_TO_USEC(next_beacon +
3069                                      (ahp->ah_atimWindow ? ahp->
3070                                       ah_atimWindow : 1)));
3071                 flags |= AR_NDP_TIMER_EN;
3072         case ATH9K_M_HOSTAP:
3073                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3074                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3075                           TU_TO_USEC(next_beacon -
3076                                      ah->ah_config.
3077                                      dma_beacon_response_time));
3078                 REG_WRITE(ah, AR_NEXT_SWBA,
3079                           TU_TO_USEC(next_beacon -
3080                                      ah->ah_config.
3081                                      sw_beacon_response_time));
3082                 flags |=
3083                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3084                 break;
3085         }
3086
3087         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3088         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3089         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3090         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3091
3092         beacon_period &= ~ATH9K_BEACON_ENA;
3093         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3094                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3095                 ath9k_hw_reset_tsf(ah);
3096         }
3097
3098         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3099 }
3100
3101 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3102                                     const struct ath9k_beacon_state *bs)
3103 {
3104         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3105         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3106
3107         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3108
3109         REG_WRITE(ah, AR_BEACON_PERIOD,
3110                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3111         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3112                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3113
3114         REG_RMW_FIELD(ah, AR_RSSI_THR,
3115                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3116
3117         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3118
3119         if (bs->bs_sleepduration > beaconintval)
3120                 beaconintval = bs->bs_sleepduration;
3121
3122         dtimperiod = bs->bs_dtimperiod;
3123         if (bs->bs_sleepduration > dtimperiod)
3124                 dtimperiod = bs->bs_sleepduration;
3125
3126         if (beaconintval == dtimperiod)
3127                 nextTbtt = bs->bs_nextdtim;
3128         else
3129                 nextTbtt = bs->bs_nexttbtt;
3130
3131         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3132         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3133         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3134         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3135
3136         REG_WRITE(ah, AR_NEXT_DTIM,
3137                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3138         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3139
3140         REG_WRITE(ah, AR_SLEEP1,
3141                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3142                   | AR_SLEEP1_ASSUME_DTIM);
3143
3144         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3145                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3146         else
3147                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3148
3149         REG_WRITE(ah, AR_SLEEP2,
3150                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3151
3152         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3153         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3154
3155         REG_SET_BIT(ah, AR_TIMER_MODE,
3156                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3157                     AR_DTIM_TIMER_EN);
3158
3159 }
3160
3161 /*******************/
3162 /* HW Capabilities */
3163 /*******************/
3164
3165 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3166 {
3167         struct ath_hal_5416 *ahp = AH5416(ah);
3168         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3169         u16 capField = 0, eeval;
3170
3171         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3172
3173         ah->ah_currentRD = eeval;
3174
3175         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3176         ah->ah_currentRDExt = eeval;
3177
3178         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3179
3180         if (ah->ah_opmode != ATH9K_M_HOSTAP &&
3181             ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3182                 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3183                         ah->ah_currentRD += 5;
3184                 else if (ah->ah_currentRD == 0x41)
3185                         ah->ah_currentRD = 0x43;
3186                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3187                         "regdomain mapped to 0x%x\n", ah->ah_currentRD);
3188         }
3189
3190         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3191         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3192
3193         if (eeval & AR5416_OPFLAGS_11A) {
3194                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3195                 if (ah->ah_config.ht_enable) {
3196                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3197                                 set_bit(ATH9K_MODE_11NA_HT20,
3198                                         pCap->wireless_modes);
3199                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3200                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3201                                         pCap->wireless_modes);
3202                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3203                                         pCap->wireless_modes);
3204                         }
3205                 }
3206         }
3207
3208         if (eeval & AR5416_OPFLAGS_11G) {
3209                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3210                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3211                 if (ah->ah_config.ht_enable) {
3212                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3213                                 set_bit(ATH9K_MODE_11NG_HT20,
3214                                         pCap->wireless_modes);
3215                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3216                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3217                                         pCap->wireless_modes);
3218                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3219                                         pCap->wireless_modes);
3220                         }
3221                 }
3222         }
3223
3224         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3225         if ((ah->ah_isPciExpress)
3226             || (eeval & AR5416_OPFLAGS_11A)) {
3227                 pCap->rx_chainmask =
3228                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3229         } else {
3230                 pCap->rx_chainmask =
3231                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3232         }
3233
3234         if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3235                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3236
3237         pCap->low_2ghz_chan = 2312;
3238         pCap->high_2ghz_chan = 2732;
3239
3240         pCap->low_5ghz_chan = 4920;
3241         pCap->high_5ghz_chan = 6100;
3242
3243         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3244         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3245         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3246
3247         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3248         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3249         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3250
3251         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3252
3253         if (ah->ah_config.ht_enable)
3254                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3255         else
3256                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3257
3258         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3259         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3260         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3261         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3262
3263         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3264                 pCap->total_queues =
3265                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3266         else
3267                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3268
3269         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3270                 pCap->keycache_size =
3271                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3272         else
3273                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3274
3275         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3276         pCap->num_mr_retries = 4;
3277         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3278
3279         if (AR_SREV_9280_10_OR_LATER(ah))
3280                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3281         else
3282                 pCap->num_gpio_pins = AR_NUM_GPIO;
3283
3284         if (AR_SREV_9280_10_OR_LATER(ah)) {
3285                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3286                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3287         } else {
3288                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3289                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3290         }
3291
3292         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3293                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3294                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3295         } else {
3296                 pCap->rts_aggr_limit = (8 * 1024);
3297         }
3298
3299         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3300
3301 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3302         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3303         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3304                 ah->ah_rfkill_gpio =
3305                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3306                 ah->ah_rfkill_polarity =
3307                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3308
3309                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3310         }
3311 #endif
3312
3313         if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3314             (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3315             (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3316             (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3317             (ah->ah_macVersion == AR_SREV_VERSION_9280))
3318                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3319         else
3320                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3321
3322         if (AR_SREV_9280(ah))
3323                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3324         else
3325                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3326
3327         if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3328                 pCap->reg_cap =
3329                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3330                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3331                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3332                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3333         } else {
3334                 pCap->reg_cap =
3335                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3336                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3337         }
3338
3339         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3340
3341         pCap->num_antcfg_5ghz =
3342                 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ);
3343         pCap->num_antcfg_2ghz =
3344                 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ);
3345
3346         return true;
3347 }
3348
3349 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3350                             u32 capability, u32 *result)
3351 {
3352         struct ath_hal_5416 *ahp = AH5416(ah);
3353         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3354
3355         switch (type) {
3356         case ATH9K_CAP_CIPHER:
3357                 switch (capability) {
3358                 case ATH9K_CIPHER_AES_CCM:
3359                 case ATH9K_CIPHER_AES_OCB:
3360                 case ATH9K_CIPHER_TKIP:
3361                 case ATH9K_CIPHER_WEP:
3362                 case ATH9K_CIPHER_MIC:
3363                 case ATH9K_CIPHER_CLR:
3364                         return true;
3365                 default:
3366                         return false;
3367                 }
3368         case ATH9K_CAP_TKIP_MIC:
3369                 switch (capability) {
3370                 case 0:
3371                         return true;
3372                 case 1:
3373                         return (ahp->ah_staId1Defaults &
3374                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3375                         false;
3376                 }
3377         case ATH9K_CAP_TKIP_SPLIT:
3378                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3379                         false : true;
3380         case ATH9K_CAP_WME_TKIPMIC:
3381                 return 0;
3382         case ATH9K_CAP_PHYCOUNTERS:
3383                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3384         case ATH9K_CAP_DIVERSITY:
3385                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3386                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3387                         true : false;
3388         case ATH9K_CAP_PHYDIAG:
3389                 return true;
3390         case ATH9K_CAP_MCAST_KEYSRCH:
3391                 switch (capability) {
3392                 case 0:
3393                         return true;
3394                 case 1:
3395                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3396                                 return false;
3397                         } else {
3398                                 return (ahp->ah_staId1Defaults &
3399                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3400                                         false;
3401                         }
3402                 }
3403                 return false;
3404         case ATH9K_CAP_TSF_ADJUST:
3405                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3406                         true : false;
3407         case ATH9K_CAP_RFSILENT:
3408                 if (capability == 3)
3409                         return false;
3410         case ATH9K_CAP_ANT_CFG_2GHZ:
3411                 *result = pCap->num_antcfg_2ghz;
3412                 return true;
3413         case ATH9K_CAP_ANT_CFG_5GHZ:
3414                 *result = pCap->num_antcfg_5ghz;
3415                 return true;
3416         case ATH9K_CAP_TXPOW:
3417                 switch (capability) {
3418                 case 0:
3419                         return 0;
3420                 case 1:
3421                         *result = ah->ah_powerLimit;
3422                         return 0;
3423                 case 2:
3424                         *result = ah->ah_maxPowerLevel;
3425                         return 0;
3426                 case 3:
3427                         *result = ah->ah_tpScale;
3428                         return 0;
3429                 }
3430                 return false;
3431         default:
3432                 return false;
3433         }
3434 }
3435
3436 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3437                             u32 capability, u32 setting, int *status)
3438 {
3439         struct ath_hal_5416 *ahp = AH5416(ah);
3440         u32 v;
3441
3442         switch (type) {
3443         case ATH9K_CAP_TKIP_MIC:
3444                 if (setting)
3445                         ahp->ah_staId1Defaults |=
3446                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3447                 else
3448                         ahp->ah_staId1Defaults &=
3449                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3450                 return true;
3451         case ATH9K_CAP_DIVERSITY:
3452                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3453                 if (setting)
3454                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3455                 else
3456                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3457                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3458                 return true;
3459         case ATH9K_CAP_MCAST_KEYSRCH:
3460                 if (setting)
3461                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3462                 else
3463                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3464                 return true;
3465         case ATH9K_CAP_TSF_ADJUST:
3466                 if (setting)
3467                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3468                 else
3469                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3470                 return true;
3471         default:
3472                 return false;
3473         }
3474 }
3475
3476 /****************************/
3477 /* GPIO / RFKILL / Antennae */
3478 /****************************/
3479
3480 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3481                                          u32 gpio, u32 type)
3482 {
3483         int addr;
3484         u32 gpio_shift, tmp;
3485
3486         if (gpio > 11)
3487                 addr = AR_GPIO_OUTPUT_MUX3;
3488         else if (gpio > 5)
3489                 addr = AR_GPIO_OUTPUT_MUX2;
3490         else
3491                 addr = AR_GPIO_OUTPUT_MUX1;
3492
3493         gpio_shift = (gpio % 6) * 5;
3494
3495         if (AR_SREV_9280_20_OR_LATER(ah)
3496             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3497                 REG_RMW(ah, addr, (type << gpio_shift),
3498                         (0x1f << gpio_shift));
3499         } else {
3500                 tmp = REG_READ(ah, addr);
3501                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3502                 tmp &= ~(0x1f << gpio_shift);
3503                 tmp |= (type << gpio_shift);
3504                 REG_WRITE(ah, addr, tmp);
3505         }
3506 }
3507
3508 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3509 {
3510         u32 gpio_shift;
3511
3512         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3513
3514         gpio_shift = gpio << 1;
3515
3516         REG_RMW(ah,
3517                 AR_GPIO_OE_OUT,
3518                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3519                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3520 }
3521
3522 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3523 {
3524         if (gpio >= ah->ah_caps.num_gpio_pins)
3525                 return 0xffffffff;
3526
3527         if (AR_SREV_9280_10_OR_LATER(ah)) {
3528                 return (MS
3529                         (REG_READ(ah, AR_GPIO_IN_OUT),
3530                          AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3531         } else {
3532                 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3533                         AR_GPIO_BIT(gpio)) != 0;
3534         }
3535 }
3536
3537 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3538                          u32 ah_signal_type)
3539 {
3540         u32 gpio_shift;
3541
3542         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3543
3544         gpio_shift = 2 * gpio;
3545
3546         REG_RMW(ah,
3547                 AR_GPIO_OE_OUT,
3548                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3549                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3550 }
3551
3552 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3553 {
3554         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3555                 AR_GPIO_BIT(gpio));
3556 }
3557
3558 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3559 void ath9k_enable_rfkill(struct ath_hal *ah)
3560 {
3561         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3562                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3563
3564         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3565                     AR_GPIO_INPUT_MUX2_RFSILENT);
3566
3567         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3568         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3569 }
3570 #endif
3571
3572 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3573 {
3574         struct ath9k_channel *chan = ah->ah_curchan;
3575         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3576         u16 ant_config;
3577         u32 halNumAntConfig;
3578
3579         halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3580                 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3581
3582         if (cfg < halNumAntConfig) {
3583                 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3584                                                      cfg, &ant_config)) {
3585                         REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3586                         return 0;
3587                 }
3588         }
3589
3590         return -EINVAL;
3591 }
3592
3593 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3594 {
3595         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3596 }
3597
3598 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3599 {
3600         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3601 }
3602
3603 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3604                                enum ath9k_ant_setting settings,
3605                                struct ath9k_channel *chan,
3606                                u8 *tx_chainmask,
3607                                u8 *rx_chainmask,
3608                                u8 *antenna_cfgd)
3609 {
3610         struct ath_hal_5416 *ahp = AH5416(ah);
3611         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3612
3613         if (AR_SREV_9280(ah)) {
3614                 if (!tx_chainmask_cfg) {
3615
3616                         tx_chainmask_cfg = *tx_chainmask;
3617                         rx_chainmask_cfg = *rx_chainmask;
3618                 }
3619
3620                 switch (settings) {
3621                 case ATH9K_ANT_FIXED_A:
3622                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3623                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3624                         *antenna_cfgd = true;
3625                         break;
3626                 case ATH9K_ANT_FIXED_B:
3627                         if (ah->ah_caps.tx_chainmask >
3628                             ATH9K_ANTENNA1_CHAINMASK) {
3629                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3630                         }
3631                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3632                         *antenna_cfgd = true;
3633                         break;
3634                 case ATH9K_ANT_VARIABLE:
3635                         *tx_chainmask = tx_chainmask_cfg;
3636                         *rx_chainmask = rx_chainmask_cfg;
3637                         *antenna_cfgd = true;
3638                         break;
3639                 default:
3640                         break;
3641                 }
3642         } else {
3643                 ahp->ah_diversityControl = settings;
3644         }
3645
3646         return true;
3647 }
3648
3649 /*********************/
3650 /* General Operation */
3651 /*********************/
3652
3653 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3654 {
3655         u32 bits = REG_READ(ah, AR_RX_FILTER);
3656         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3657
3658         if (phybits & AR_PHY_ERR_RADAR)
3659                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3660         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3661                 bits |= ATH9K_RX_FILTER_PHYERR;
3662
3663         return bits;
3664 }
3665
3666 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3667 {
3668         u32 phybits;
3669
3670         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3671         phybits = 0;
3672         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3673                 phybits |= AR_PHY_ERR_RADAR;
3674         if (bits & ATH9K_RX_FILTER_PHYERR)
3675                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3676         REG_WRITE(ah, AR_PHY_ERR, phybits);
3677
3678         if (phybits)
3679                 REG_WRITE(ah, AR_RXCFG,
3680                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3681         else
3682                 REG_WRITE(ah, AR_RXCFG,
3683                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3684 }
3685
3686 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3687 {
3688         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3689 }
3690
3691 bool ath9k_hw_disable(struct ath_hal *ah)
3692 {
3693         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3694                 return false;
3695
3696         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3697 }
3698
3699 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3700 {
3701         struct ath9k_channel *chan = ah->ah_curchan;
3702
3703         ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3704
3705         if (ath9k_hw_set_txpower(ah, chan,
3706                                  ath9k_regd_get_ctl(ah, chan),
3707                                  ath9k_regd_get_antenna_allowed(ah, chan),
3708                                  chan->maxRegTxPower * 2,
3709                                  min((u32) MAX_RATE_POWER,
3710                                      (u32) ah->ah_powerLimit)) != 0)
3711                 return false;
3712
3713         return true;
3714 }
3715
3716 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3717 {
3718         struct ath_hal_5416 *ahp = AH5416(ah);
3719
3720         memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3721 }
3722
3723 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3724 {
3725         struct ath_hal_5416 *ahp = AH5416(ah);
3726
3727         memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3728
3729         return true;
3730 }
3731
3732 void ath9k_hw_setopmode(struct ath_hal *ah)
3733 {
3734         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3735 }
3736
3737 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3738 {
3739         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3740         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3741 }
3742
3743 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3744 {
3745         struct ath_hal_5416 *ahp = AH5416(ah);
3746
3747         memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3748 }
3749
3750 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3751 {
3752         struct ath_hal_5416 *ahp = AH5416(ah);
3753
3754         memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3755
3756         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3757         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3758
3759         return true;
3760 }
3761
3762 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3763 {
3764         struct ath_hal_5416 *ahp = AH5416(ah);
3765
3766         memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3767         ahp->ah_assocId = assocId;
3768
3769         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3770         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3771                   ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3772 }
3773
3774 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3775 {
3776         u64 tsf;
3777
3778         tsf = REG_READ(ah, AR_TSF_U32);
3779         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3780
3781         return tsf;
3782 }
3783
3784 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3785 {
3786         int count;
3787
3788         count = 0;
3789         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3790                 count++;
3791                 if (count > 10) {
3792                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3793                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3794                         break;
3795                 }
3796                 udelay(10);
3797         }
3798         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3799 }
3800
3801 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3802 {
3803         struct ath_hal_5416 *ahp = AH5416(ah);
3804
3805         if (setting)
3806                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3807         else
3808                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3809
3810         return true;
3811 }
3812
3813 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3814 {
3815         struct ath_hal_5416 *ahp = AH5416(ah);
3816
3817         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3818                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3819                 ahp->ah_slottime = (u32) -1;
3820                 return false;
3821         } else {
3822                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3823                 ahp->ah_slottime = us;
3824                 return true;
3825         }
3826 }
3827
3828 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3829 {
3830         u32 macmode;
3831
3832         if (mode == ATH9K_HT_MACMODE_2040 &&
3833             !ah->ah_config.cwm_ignore_extcca)
3834                 macmode = AR_2040_JOINED_RX_CLEAR;
3835         else
3836                 macmode = 0;
3837
3838         REG_WRITE(ah, AR_2040_MODE, macmode);
3839 }