drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  88 {
  89         int i;
  90
  91         BUG_ON(timeout < AH_TIME_QUANTUM);
  92
  93         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  94                 if ((REG_READ(ah, reg) & mask) == val)
  95                         return true;
  96
  97                 udelay(AH_TIME_QUANTUM);
  98         }
  99
 100         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 101                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 102                 timeout, reg, REG_READ(ah, reg), mask, val);
 103
 104         return false;
 105 }
 106
 107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 108 {
 109         u32 retval;
 110         int i;
 111
 112         for (i = 0, retval = 0; i < n; i++) {
 113                 retval = (retval << 1) | (val & 1);
 114                 val >>= 1;
 115         }
 116         return retval;
 117 }
 118
 119 bool ath9k_get_channel_edges(struct ath_hw *ah,
 120                              u16 flags, u16 *low,
 121                              u16 *high)
 122 {
 123         struct ath9k_hw_capabilities *pCap = &ah->caps;
 124
 125         if (flags & CHANNEL_5GHZ) {
 126                 *low = pCap->low_5ghz_chan;
 127                 *high = pCap->high_5ghz_chan;
 128                 return true;
 129         }
 130         if ((flags & CHANNEL_2GHZ)) {
 131                 *low = pCap->low_2ghz_chan;
 132                 *high = pCap->high_2ghz_chan;
 133                 return true;
 134         }
 135         return false;
 136 }
 137
 138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 139                            struct ath_rate_table *rates,
 140                            u32 frameLen, u16 rateix,
 141                            bool shortPreamble)
 142 {
 143         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 144         u32 kbps;
 145
 146         kbps = rates->info[rateix].ratekbps;
 147
 148         if (kbps == 0)
 149                 return 0;
 150
 151         switch (rates->info[rateix].phy) {
 152         case WLAN_RC_PHY_CCK:
 153                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 154                 if (shortPreamble && rates->info[rateix].short_preamble)
 155                         phyTime >>= 1;
 156                 numBits = frameLen << 3;
 157                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 158                 break;
 159         case WLAN_RC_PHY_OFDM:
 160                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 161                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 162                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 163                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 164                         txTime = OFDM_SIFS_TIME_QUARTER
 165                                 + OFDM_PREAMBLE_TIME_QUARTER
 166                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 167                 } else if (ah->curchan &&
 168                            IS_CHAN_HALF_RATE(ah->curchan)) {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME_HALF +
 173                                 OFDM_PREAMBLE_TIME_HALF
 174                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 175                 } else {
 176                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 177                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 178                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 179                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 180                                 + (numSymbols * OFDM_SYMBOL_TIME);
 181                 }
 182                 break;
 183         default:
 184                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 185                         "Unknown phy %u (rate ix %u)\n",
 186                         rates->info[rateix].phy, rateix);
 187                 txTime = 0;
 188                 break;
 189         }
 190
 191         return txTime;
 192 }
 193
 194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 195                                   struct ath9k_channel *chan,
 196                                   struct chan_centers *centers)
 197 {
 198         int8_t extoff;
 199
 200         if (!IS_CHAN_HT40(chan)) {
 201                 centers->ctl_center = centers->ext_center =
 202                         centers->synth_center = chan->channel;
 203                 return;
 204         }
 205
 206         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 207             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 208                 centers->synth_center =
 209                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 210                 extoff = 1;
 211         } else {
 212                 centers->synth_center =
 213                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 214                 extoff = -1;
 215         }
 216
 217         centers->ctl_center =
 218                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 219         centers->ext_center =
 220                 centers->synth_center + (extoff *
 221                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 222                           HT40_CHANNEL_CENTER_SHIFT : 15));
 223 }
 224
 225 /******************/
 226 /* Chip Revisions */
 227 /******************/
 228
 229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 230 {
 231         u32 val;
 232
 233         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 234
 235         if (val == 0xFF) {
 236                 val = REG_READ(ah, AR_SREV);
 237                 ah->hw_version.macVersion =
 238                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 239                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 240                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 241         } else {
 242                 if (!AR_SREV_9100(ah))
 243                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 244
 245                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 246
 247                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 248                         ah->is_pciexpress = true;
 249         }
 250 }
 251
 252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 253 {
 254         u32 val;
 255         int i;
 256
 257         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 258
 259         for (i = 0; i < 8; i++)
 260                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 261         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 262         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 263
 264         return ath9k_hw_reverse_bits(val, 8);
 265 }
 266
 267 /************************************/
 268 /* HW Attach, Detach, Init Routines */
 269 /************************************/
 270
 271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 272 {
 273         if (AR_SREV_9100(ah))
 274                 return;
 275
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 280         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 281         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 282         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 283         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 284         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 285
 286         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 287 }
 288
 289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 290 {
 291         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 292         u32 regHold[2];
 293         u32 patternData[4] = { 0x55555555,
 294                                0xaaaaaaaa,
 295                                0x66666666,
 296                                0x99999999 };
 297         int i, j;
 298
 299         for (i = 0; i < 2; i++) {
 300                 u32 addr = regAddr[i];
 301                 u32 wrData, rdData;
 302
 303                 regHold[i] = REG_READ(ah, addr);
 304                 for (j = 0; j < 0x100; j++) {
 305                         wrData = (j << 16) | j;
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (rdData != wrData) {
 309                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 310                                         "address test failed "
 311                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 312                                         addr, wrData, rdData);
 313                                 return false;
 314                         }
 315                 }
 316                 for (j = 0; j < 4; j++) {
 317                         wrData = patternData[j];
 318                         REG_WRITE(ah, addr, wrData);
 319                         rdData = REG_READ(ah, addr);
 320                         if (wrData != rdData) {
 321                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 322                                         "address test failed "
 323                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 324                                         addr, wrData, rdData);
 325                                 return false;
 326                         }
 327                 }
 328                 REG_WRITE(ah, regAddr[i], regHold[i]);
 329         }
 330         udelay(100);
 331
 332         return true;
 333 }
 334
 335 static const char *ath9k_hw_devname(u16 devid)
 336 {
 337         switch (devid) {
 338         case AR5416_DEVID_PCI:
 339                 return "Atheros 5416";
 340         case AR5416_DEVID_PCIE:
 341                 return "Atheros 5418";
 342         case AR9160_DEVID_PCI:
 343                 return "Atheros 9160";
 344         case AR5416_AR9100_DEVID:
 345                 return "Atheros 9100";
 346         case AR9280_DEVID_PCI:
 347         case AR9280_DEVID_PCIE:
 348                 return "Atheros 9280";
 349         case AR9285_DEVID_PCIE:
 350                 return "Atheros 9285";
 351         }
 352
 353         return NULL;
 354 }
 355
 356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 357 {
 358         int i;
 359
 360         ah->config.dma_beacon_response_time = 2;
 361         ah->config.sw_beacon_response_time = 10;
 362         ah->config.additional_swba_backoff = 0;
 363         ah->config.ack_6mb = 0x0;
 364         ah->config.cwm_ignore_extcca = 0;
 365         ah->config.pcie_powersave_enable = 0;
 366         ah->config.pcie_l1skp_enable = 0;
 367         ah->config.pcie_clock_req = 0;
 368         ah->config.pcie_power_reset = 0x100;
 369         ah->config.pcie_restore = 0;
 370         ah->config.pcie_waen = 0;
 371         ah->config.analog_shiftreg = 1;
 372         ah->config.ht_enable = 1;
 373         ah->config.ofdm_trig_low = 200;
 374         ah->config.ofdm_trig_high = 500;
 375         ah->config.cck_trig_high = 200;
 376         ah->config.cck_trig_low = 100;
 377         ah->config.enable_ani = 1;
 378         ah->config.noise_immunity_level = 4;
 379         ah->config.ofdm_weaksignal_det = 1;
 380         ah->config.cck_weaksignal_thr = 0;
 381         ah->config.spur_immunity_level = 2;
 382         ah->config.firstep_level = 0;
 383         ah->config.rssi_thr_high = 40;
 384         ah->config.rssi_thr_low = 7;
 385         ah->config.diversity_control = 0;
 386         ah->config.antenna_switch_swap = 0;
 387
 388         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 389                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 390                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 391         }
 392
 393         ah->config.intr_mitigation = 1;
 394
 395         /*
 396          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 397          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 398          * This means we use it for all AR5416 devices, and the few
 399          * minor PCI AR9280 devices out there.
 400          *
 401          * Serialization is required because these devices do not handle
 402          * well the case of two concurrent reads/writes due to the latency
 403          * involved. During one read/write another read/write can be issued
 404          * on another CPU while the previous read/write may still be working
 405          * on our hardware, if we hit this case the hardware poops in a loop.
 406          * We prevent this by serializing reads and writes.
 407          *
 408          * This issue is not present on PCI-Express devices or pre-AR5416
 409          * devices (legacy, 802.11abg).
 410          */
 411         if (num_possible_cpus() > 1)
 412                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 413 }
 414
 415 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 416                                         int *status)
 417 {
 418         struct ath_hw *ah;
 419
 420         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 421         if (ah == NULL) {
 422                 DPRINTF(sc, ATH_DBG_FATAL,
 423                         "Cannot allocate memory for state block\n");
 424                 *status = -ENOMEM;
 425                 return NULL;
 426         }
 427
 428         ah->ah_sc = sc;
 429         ah->hw_version.magic = AR5416_MAGIC;
 430         ah->regulatory.country_code = CTRY_DEFAULT;
 431         ah->hw_version.devid = devid;
 432         ah->hw_version.subvendorid = 0;
 433
 434         ah->ah_flags = 0;
 435         if ((devid == AR5416_AR9100_DEVID))
 436                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 437         if (!AR_SREV_9100(ah))
 438                 ah->ah_flags = AH_USE_EEPROM;
 439
 440         ah->regulatory.power_limit = MAX_RATE_POWER;
 441         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 442         ah->atim_window = 0;
 443         ah->diversity_control = ah->config.diversity_control;
 444         ah->antenna_switch_swap =
 445                 ah->config.antenna_switch_swap;
 446         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 447         ah->beacon_interval = 100;
 448         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 449         ah->slottime = (u32) -1;
 450         ah->acktimeout = (u32) -1;
 451         ah->ctstimeout = (u32) -1;
 452         ah->globaltxtimeout = (u32) -1;
 453
 454         ah->gbeacon_rate = 0;
 455
 456         return ah;
 457 }
 458
 459 static int ath9k_hw_rfattach(struct ath_hw *ah)
 460 {
 461         bool rfStatus = false;
 462         int ecode = 0;
 463
 464         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 465         if (!rfStatus) {
 466                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 467                         "RF setup failed, status %u\n", ecode);
 468                 return ecode;
 469         }
 470
 471         return 0;
 472 }
 473
 474 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 475 {
 476         u32 val;
 477
 478         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 479
 480         val = ath9k_hw_get_radiorev(ah);
 481         switch (val & AR_RADIO_SREV_MAJOR) {
 482         case 0:
 483                 val = AR_RAD5133_SREV_MAJOR;
 484                 break;
 485         case AR_RAD5133_SREV_MAJOR:
 486         case AR_RAD5122_SREV_MAJOR:
 487         case AR_RAD2133_SREV_MAJOR:
 488         case AR_RAD2122_SREV_MAJOR:
 489                 break;
 490         default:
 491                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 492                         "5G Radio Chip Rev 0x%02X is not "
 493                         "supported by this driver\n",
 494                         ah->hw_version.analog5GhzRev);
 495                 return -EOPNOTSUPP;
 496         }
 497
 498         ah->hw_version.analog5GhzRev = val;
 499
 500         return 0;
 501 }
 502
 503 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 504 {
 505         u32 sum;
 506         int i;
 507         u16 eeval;
 508
 509         sum = 0;
 510         for (i = 0; i < 3; i++) {
 511                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 512                 sum += eeval;
 513                 ah->macaddr[2 * i] = eeval >> 8;
 514                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 515         }
 516         if (sum == 0 || sum == 0xffff * 3) {
 517                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 518                         "mac address read failed: %pM\n",
 519                         ah->macaddr);
 520                 return -EADDRNOTAVAIL;
 521         }
 522
 523         return 0;
 524 }
 525
 526 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 527 {
 528         u32 rxgain_type;
 529
 530         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 531                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 532
 533                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 534                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 535                         ar9280Modes_backoff_13db_rxgain_9280_2,
 536                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 537                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 538                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 539                         ar9280Modes_backoff_23db_rxgain_9280_2,
 540                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 541                 else
 542                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 543                         ar9280Modes_original_rxgain_9280_2,
 544                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 545         } else {
 546                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 547                         ar9280Modes_original_rxgain_9280_2,
 548                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 549         }
 550 }
 551
 552 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 553 {
 554         u32 txgain_type;
 555
 556         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 557                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 558
 559                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 560                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 561                         ar9280Modes_high_power_tx_gain_9280_2,
 562                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 563                 else
 564                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 565                         ar9280Modes_original_tx_gain_9280_2,
 566                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 567         } else {
 568                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 569                 ar9280Modes_original_tx_gain_9280_2,
 570                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 571         }
 572 }
 573
 574 static int ath9k_hw_post_attach(struct ath_hw *ah)
 575 {
 576         int ecode;
 577
 578         if (!ath9k_hw_chip_test(ah)) {
 579                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 580                         "hardware self-test failed\n");
 581                 return -ENODEV;
 582         }
 583
 584         ecode = ath9k_hw_rf_claim(ah);
 585         if (ecode != 0)
 586                 return ecode;
 587
 588         ecode = ath9k_hw_eeprom_attach(ah);
 589         if (ecode != 0)
 590                 return ecode;
 591
 592         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 593                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 594
 595         ecode = ath9k_hw_rfattach(ah);
 596         if (ecode != 0)
 597                 return ecode;
 598
 599         if (!AR_SREV_9100(ah)) {
 600                 ath9k_hw_ani_setup(ah);
 601                 ath9k_hw_ani_attach(ah);
 602         }
 603
 604         return 0;
 605 }
 606
 607 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 608                                          int *status)
 609 {
 610         struct ath_hw *ah;
 611         int ecode;
 612         u32 i, j;
 613
 614         ah = ath9k_hw_newstate(devid, sc, status);
 615         if (ah == NULL)
 616                 return NULL;
 617
 618         ath9k_hw_set_defaults(ah);
 619
 620         if (ah->config.intr_mitigation != 0)
 621                 ah->intr_mitigation = true;
 622
 623         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 624                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 625                 ecode = -EIO;
 626                 goto bad;
 627         }
 628
 629         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 630                 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 631                 ecode = -EIO;
 632                 goto bad;
 633         }
 634
 635         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 636                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 637                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 638                         ah->config.serialize_regmode =
 639                                 SER_REG_MODE_ON;
 640                 } else {
 641                         ah->config.serialize_regmode =
 642                                 SER_REG_MODE_OFF;
 643                 }
 644         }
 645
 646         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 647                 ah->config.serialize_regmode);
 648
 649         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 650             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 651             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 652             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 653                 DPRINTF(sc, ATH_DBG_RESET,
 654                         "Mac Chip Rev 0x%02x.%x is not supported by "
 655                         "this driver\n", ah->hw_version.macVersion,
 656                         ah->hw_version.macRev);
 657                 ecode = -EOPNOTSUPP;
 658                 goto bad;
 659         }
 660
 661         if (AR_SREV_9100(ah)) {
 662                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 663                 ah->supp_cals = IQ_MISMATCH_CAL;
 664                 ah->is_pciexpress = false;
 665         }
 666         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 667
 668         if (AR_SREV_9160_10_OR_LATER(ah)) {
 669                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 670                         ah->iq_caldata.calData = &iq_cal_single_sample;
 671                         ah->adcgain_caldata.calData =
 672                                 &adc_gain_cal_single_sample;
 673                         ah->adcdc_caldata.calData =
 674                                 &adc_dc_cal_single_sample;
 675                         ah->adcdc_calinitdata.calData =
 676                                 &adc_init_dc_cal;
 677                 } else {
 678                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 679                         ah->adcgain_caldata.calData =
 680                                 &adc_gain_cal_multi_sample;
 681                         ah->adcdc_caldata.calData =
 682                                 &adc_dc_cal_multi_sample;
 683                         ah->adcdc_calinitdata.calData =
 684                                 &adc_init_dc_cal;
 685                 }
 686                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 687         }
 688
 689         ah->ani_function = ATH9K_ANI_ALL;
 690         if (AR_SREV_9280_10_OR_LATER(ah))
 691                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 692
 693         DPRINTF(sc, ATH_DBG_RESET,
 694                 "This Mac Chip Rev 0x%02x.%x is \n",
 695                 ah->hw_version.macVersion, ah->hw_version.macRev);
 696
 697         if (AR_SREV_9285_12_OR_LATER(ah)) {
 698
 699                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 700                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 701                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 702                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 703
 704                 if (ah->config.pcie_clock_req) {
 705                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 706                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 707                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 708                 } else {
 709                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 710                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 711                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 712                                   2);
 713                 }
 714         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 715                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 716                                ARRAY_SIZE(ar9285Modes_9285), 6);
 717                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 718                                ARRAY_SIZE(ar9285Common_9285), 2);
 719
 720                 if (ah->config.pcie_clock_req) {
 721                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 722                         ar9285PciePhy_clkreq_off_L1_9285,
 723                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 724                 } else {
 725                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 726                         ar9285PciePhy_clkreq_always_on_L1_9285,
 727                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 728                 }
 729         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 730                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 731                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 732                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 733                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 734
 735                 if (ah->config.pcie_clock_req) {
 736                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 737                                ar9280PciePhy_clkreq_off_L1_9280,
 738                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 739                 } else {
 740                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 741                                ar9280PciePhy_clkreq_always_on_L1_9280,
 742                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 743                 }
 744                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 745                                ar9280Modes_fast_clock_9280_2,
 746                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 747         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 748                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 749                                ARRAY_SIZE(ar9280Modes_9280), 6);
 750                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 751                                ARRAY_SIZE(ar9280Common_9280), 2);
 752         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 753                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 754                                ARRAY_SIZE(ar5416Modes_9160), 6);
 755                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 756                                ARRAY_SIZE(ar5416Common_9160), 2);
 757                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 758                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 759                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 760                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 761                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 762                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 763                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 764                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 765                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 766                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 767                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 768                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 769                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 770                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 771                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 772                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 773                 if (AR_SREV_9160_11(ah)) {
 774                         INIT_INI_ARRAY(&ah->iniAddac,
 775                                        ar5416Addac_91601_1,
 776                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 777                 } else {
 778                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 779                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 780                 }
 781         } else if (AR_SREV_9100_OR_LATER(ah)) {
 782                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 783                                ARRAY_SIZE(ar5416Modes_9100), 6);
 784                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 785                                ARRAY_SIZE(ar5416Common_9100), 2);
 786                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 787                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 788                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 789                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 790                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 791                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 792                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 793                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 794                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 795                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 796                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 797                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 798                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 799                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 800                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 801                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 802                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 803                                ARRAY_SIZE(ar5416Addac_9100), 2);
 804         } else {
 805                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 806                                ARRAY_SIZE(ar5416Modes), 6);
 807                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 808                                ARRAY_SIZE(ar5416Common), 2);
 809                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 810                                ARRAY_SIZE(ar5416Bank0), 2);
 811                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 812                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 813                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 814                                ARRAY_SIZE(ar5416Bank1), 2);
 815                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 816                                ARRAY_SIZE(ar5416Bank2), 2);
 817                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 818                                ARRAY_SIZE(ar5416Bank3), 3);
 819                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 820                                ARRAY_SIZE(ar5416Bank6), 3);
 821                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 822                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 823                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 824                                ARRAY_SIZE(ar5416Bank7), 2);
 825                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 826                                ARRAY_SIZE(ar5416Addac), 2);
 827         }
 828
 829         if (ah->is_pciexpress)
 830                 ath9k_hw_configpcipowersave(ah, 0);
 831         else
 832                 ath9k_hw_disablepcie(ah);
 833
 834         ecode = ath9k_hw_post_attach(ah);
 835         if (ecode != 0)
 836                 goto bad;
 837
 838         if (AR_SREV_9285_12_OR_LATER(ah)) {
 839                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 840
 841                 /* txgain table */
 842                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 843                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 844                         ar9285Modes_high_power_tx_gain_9285_1_2,
 845                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 846                 } else {
 847                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 848                         ar9285Modes_original_tx_gain_9285_1_2,
 849                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 850                 }
 851
 852         }
 853
 854         /* rxgain table */
 855         if (AR_SREV_9280_20(ah))
 856                 ath9k_hw_init_rxgain_ini(ah);
 857
 858         /* txgain table */
 859         if (AR_SREV_9280_20(ah))
 860                 ath9k_hw_init_txgain_ini(ah);
 861
 862         if (!ath9k_hw_fill_cap_info(ah)) {
 863                 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
 864                 ecode = -EINVAL;
 865                 goto bad;
 866         }
 867
 868         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 869             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 870
 871                 /* EEPROM Fixup */
 872                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 873                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 874
 875                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 876                                 u32 val = INI_RA(&ah->iniModes, i, j);
 877
 878                                 INI_RA(&ah->iniModes, i, j) =
 879                                         ath9k_hw_ini_fixup(ah,
 880                                                            &ah->eeprom.def,
 881                                                            reg, val);
 882                         }
 883                 }
 884         }
 885
 886         ecode = ath9k_hw_init_macaddr(ah);
 887         if (ecode != 0) {
 888                 DPRINTF(sc, ATH_DBG_RESET,
 889                         "failed initializing mac address\n");
 890                 goto bad;
 891         }
 892
 893         if (AR_SREV_9285(ah))
 894                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 895         else
 896                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 897
 898         ath9k_init_nfcal_hist_buffer(ah);
 899
 900         return ah;
 901 bad:
 902         if (ah)
 903                 ath9k_hw_detach(ah);
 904         if (status)
 905                 *status = ecode;
 906
 907         return NULL;
 908 }
 909
 910 static void ath9k_hw_init_bb(struct ath_hw *ah,
 911                              struct ath9k_channel *chan)
 912 {
 913         u32 synthDelay;
 914
 915         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 916         if (IS_CHAN_B(chan))
 917                 synthDelay = (4 * synthDelay) / 22;
 918         else
 919                 synthDelay /= 10;
 920
 921         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 922
 923         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 924 }
 925
 926 static void ath9k_hw_init_qos(struct ath_hw *ah)
 927 {
 928         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 929         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 930
 931         REG_WRITE(ah, AR_QOS_NO_ACK,
 932                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 933                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 934                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 935
 936         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 937         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 938         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 939         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 940         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 941 }
 942
 943 static void ath9k_hw_init_pll(struct ath_hw *ah,
 944                               struct ath9k_channel *chan)
 945 {
 946         u32 pll;
 947
 948         if (AR_SREV_9100(ah)) {
 949                 if (chan && IS_CHAN_5GHZ(chan))
 950                         pll = 0x1450;
 951                 else
 952                         pll = 0x1458;
 953         } else {
 954                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 955                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 956
 957                         if (chan && IS_CHAN_HALF_RATE(chan))
 958                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 959                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 960                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 961
 962                         if (chan && IS_CHAN_5GHZ(chan)) {
 963                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 964
 965
 966                                 if (AR_SREV_9280_20(ah)) {
 967                                         if (((chan->channel % 20) == 0)
 968                                             || ((chan->channel % 10) == 0))
 969                                                 pll = 0x2850;
 970                                         else
 971                                                 pll = 0x142c;
 972                                 }
 973                         } else {
 974                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 975                         }
 976
 977                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 978
 979                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 980
 981                         if (chan && IS_CHAN_HALF_RATE(chan))
 982                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 983                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 984                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 985
 986                         if (chan && IS_CHAN_5GHZ(chan))
 987                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 988                         else
 989                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 990                 } else {
 991                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 992
 993                         if (chan && IS_CHAN_HALF_RATE(chan))
 994                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 995                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 996                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 997
 998                         if (chan && IS_CHAN_5GHZ(chan))
 999                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1000                         else
1001                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1002                 }
1003         }
1004         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1005
1006         udelay(RTC_PLL_SETTLE_DELAY);
1007
1008         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1009 }
1010
1011 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1012 {
1013         int rx_chainmask, tx_chainmask;
1014
1015         rx_chainmask = ah->rxchainmask;
1016         tx_chainmask = ah->txchainmask;
1017
1018         switch (rx_chainmask) {
1019         case 0x5:
1020                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1021                             AR_PHY_SWAP_ALT_CHAIN);
1022         case 0x3:
1023                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1024                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1025                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1026                         break;
1027                 }
1028         case 0x1:
1029         case 0x2:
1030         case 0x7:
1031                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1032                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1033                 break;
1034         default:
1035                 break;
1036         }
1037
1038         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1039         if (tx_chainmask == 0x5) {
1040                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1041                             AR_PHY_SWAP_ALT_CHAIN);
1042         }
1043         if (AR_SREV_9100(ah))
1044                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1045                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1046 }
1047
1048 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1049                                           enum nl80211_iftype opmode)
1050 {
1051         ah->mask_reg = AR_IMR_TXERR |
1052                 AR_IMR_TXURN |
1053                 AR_IMR_RXERR |
1054                 AR_IMR_RXORN |
1055                 AR_IMR_BCNMISC;
1056
1057         if (ah->intr_mitigation)
1058                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1059         else
1060                 ah->mask_reg |= AR_IMR_RXOK;
1061
1062         ah->mask_reg |= AR_IMR_TXOK;
1063
1064         if (opmode == NL80211_IFTYPE_AP)
1065                 ah->mask_reg |= AR_IMR_MIB;
1066
1067         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1068         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1069
1070         if (!AR_SREV_9100(ah)) {
1071                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1072                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1073                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1074         }
1075 }
1076
1077 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1078 {
1079         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1080                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1081                 ah->acktimeout = (u32) -1;
1082                 return false;
1083         } else {
1084                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1085                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1086                 ah->acktimeout = us;
1087                 return true;
1088         }
1089 }
1090
1091 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1092 {
1093         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1094                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1095                 ah->ctstimeout = (u32) -1;
1096                 return false;
1097         } else {
1098                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1099                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1100                 ah->ctstimeout = us;
1101                 return true;
1102         }
1103 }
1104
1105 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1106 {
1107         if (tu > 0xFFFF) {
1108                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1109                         "bad global tx timeout %u\n", tu);
1110                 ah->globaltxtimeout = (u32) -1;
1111                 return false;
1112         } else {
1113                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1114                 ah->globaltxtimeout = tu;
1115                 return true;
1116         }
1117 }
1118
1119 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1120 {
1121         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1122                 ah->misc_mode);
1123
1124         if (ah->misc_mode != 0)
1125                 REG_WRITE(ah, AR_PCU_MISC,
1126                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1127         if (ah->slottime != (u32) -1)
1128                 ath9k_hw_setslottime(ah, ah->slottime);
1129         if (ah->acktimeout != (u32) -1)
1130                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1131         if (ah->ctstimeout != (u32) -1)
1132                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1133         if (ah->globaltxtimeout != (u32) -1)
1134                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1135 }
1136
1137 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1138 {
1139         return vendorid == ATHEROS_VENDOR_ID ?
1140                 ath9k_hw_devname(devid) : NULL;
1141 }
1142
1143 void ath9k_hw_detach(struct ath_hw *ah)
1144 {
1145         if (!AR_SREV_9100(ah))
1146                 ath9k_hw_ani_detach(ah);
1147
1148         ath9k_hw_rfdetach(ah);
1149         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1150         kfree(ah);
1151 }
1152
1153 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1154 {
1155         struct ath_hw *ah = NULL;
1156
1157         switch (devid) {
1158         case AR5416_DEVID_PCI:
1159         case AR5416_DEVID_PCIE:
1160         case AR5416_AR9100_DEVID:
1161         case AR9160_DEVID_PCI:
1162         case AR9280_DEVID_PCI:
1163         case AR9280_DEVID_PCIE:
1164         case AR9285_DEVID_PCIE:
1165                 ah = ath9k_hw_do_attach(devid, sc, error);
1166                 break;
1167         default:
1168                 *error = -ENXIO;
1169                 break;
1170         }
1171
1172         return ah;
1173 }
1174
1175 /*******/
1176 /* INI */
1177 /*******/
1178
1179 static void ath9k_hw_override_ini(struct ath_hw *ah,
1180                                   struct ath9k_channel *chan)
1181 {
1182         /*
1183          * Set the RX_ABORT and RX_DIS and clear if off only after
1184          * RXE is set for MAC. This prevents frames with corrupted
1185          * descriptor status.
1186          */
1187         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1188
1189
1190         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1191             AR_SREV_9280_10_OR_LATER(ah))
1192                 return;
1193
1194         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1195 }
1196
1197 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1198                               struct ar5416_eeprom_def *pEepData,
1199                               u32 reg, u32 value)
1200 {
1201         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1202
1203         switch (ah->hw_version.devid) {
1204         case AR9280_DEVID_PCI:
1205                 if (reg == 0x7894) {
1206                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1207                                 "ini VAL: %x  EEPROM: %x\n", value,
1208                                 (pBase->version & 0xff));
1209
1210                         if ((pBase->version & 0xff) > 0x0a) {
1211                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1212                                         "PWDCLKIND: %d\n",
1213                                         pBase->pwdclkind);
1214                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1215                                 value |= AR_AN_TOP2_PWDCLKIND &
1216                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1217                         } else {
1218                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1219                                         "PWDCLKIND Earlier Rev\n");
1220                         }
1221
1222                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1223                                 "final ini VAL: %x\n", value);
1224                 }
1225                 break;
1226         }
1227
1228         return value;
1229 }
1230
1231 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1232                               struct ar5416_eeprom_def *pEepData,
1233                               u32 reg, u32 value)
1234 {
1235         if (ah->eep_map == EEP_MAP_4KBITS)
1236                 return value;
1237         else
1238                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1239 }
1240
1241 static void ath9k_olc_init(struct ath_hw *ah)
1242 {
1243         u32 i;
1244
1245         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1246                 ah->originalGain[i] =
1247                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1248                                         AR_PHY_TX_GAIN);
1249         ah->PDADCdelta = 0;
1250 }
1251
1252 static int ath9k_hw_process_ini(struct ath_hw *ah,
1253                                 struct ath9k_channel *chan,
1254                                 enum ath9k_ht_macmode macmode)
1255 {
1256         int i, regWrites = 0;
1257         struct ieee80211_channel *channel = chan->chan;
1258         u32 modesIndex, freqIndex;
1259         int status;
1260
1261         switch (chan->chanmode) {
1262         case CHANNEL_A:
1263         case CHANNEL_A_HT20:
1264                 modesIndex = 1;
1265                 freqIndex = 1;
1266                 break;
1267         case CHANNEL_A_HT40PLUS:
1268         case CHANNEL_A_HT40MINUS:
1269                 modesIndex = 2;
1270                 freqIndex = 1;
1271                 break;
1272         case CHANNEL_G:
1273         case CHANNEL_G_HT20:
1274         case CHANNEL_B:
1275                 modesIndex = 4;
1276                 freqIndex = 2;
1277                 break;
1278         case CHANNEL_G_HT40PLUS:
1279         case CHANNEL_G_HT40MINUS:
1280                 modesIndex = 3;
1281                 freqIndex = 2;
1282                 break;
1283
1284         default:
1285                 return -EINVAL;
1286         }
1287
1288         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1289         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1290         ah->eep_ops->set_addac(ah, chan);
1291
1292         if (AR_SREV_5416_22_OR_LATER(ah)) {
1293                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1294         } else {
1295                 struct ar5416IniArray temp;
1296                 u32 addacSize =
1297                         sizeof(u32) * ah->iniAddac.ia_rows *
1298                         ah->iniAddac.ia_columns;
1299
1300                 memcpy(ah->addac5416_21,
1301                        ah->iniAddac.ia_array, addacSize);
1302
1303                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1304
1305                 temp.ia_array = ah->addac5416_21;
1306                 temp.ia_columns = ah->iniAddac.ia_columns;
1307                 temp.ia_rows = ah->iniAddac.ia_rows;
1308                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1309         }
1310
1311         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1312
1313         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1314                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1315                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1316
1317                 REG_WRITE(ah, reg, val);
1318
1319                 if (reg >= 0x7800 && reg < 0x78a0
1320                     && ah->config.analog_shiftreg) {
1321                         udelay(100);
1322                 }
1323
1324                 DO_DELAY(regWrites);
1325         }
1326
1327         if (AR_SREV_9280(ah))
1328                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1329
1330         if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1331             AR_SREV_9285_12_OR_LATER(ah)))
1332                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1333
1334         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1335                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1336                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1337
1338                 REG_WRITE(ah, reg, val);
1339
1340                 if (reg >= 0x7800 && reg < 0x78a0
1341                     && ah->config.analog_shiftreg) {
1342                         udelay(100);
1343                 }
1344
1345                 DO_DELAY(regWrites);
1346         }
1347
1348         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1349
1350         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1351                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1352                                 regWrites);
1353         }
1354
1355         ath9k_hw_override_ini(ah, chan);
1356         ath9k_hw_set_regs(ah, chan, macmode);
1357         ath9k_hw_init_chain_masks(ah);
1358
1359         if (OLC_FOR_AR9280_20_LATER)
1360                 ath9k_olc_init(ah);
1361
1362         status = ah->eep_ops->set_txpower(ah, chan,
1363                                   ath9k_regd_get_ctl(ah, chan),
1364                                   channel->max_antenna_gain * 2,
1365                                   channel->max_power * 2,
1366                                   min((u32) MAX_RATE_POWER,
1367                                       (u32) ah->regulatory.power_limit));
1368         if (status != 0) {
1369                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1370                         "error init'ing transmit power\n");
1371                 return -EIO;
1372         }
1373
1374         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1375                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1376                         "ar5416SetRfRegs failed\n");
1377                 return -EIO;
1378         }
1379
1380         return 0;
1381 }
1382
1383 /****************************************/
1384 /* Reset and Channel Switching Routines */
1385 /****************************************/
1386
1387 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1388 {
1389         u32 rfMode = 0;
1390
1391         if (chan == NULL)
1392                 return;
1393
1394         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1395                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1396
1397         if (!AR_SREV_9280_10_OR_LATER(ah))
1398                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1399                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1400
1401         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1402                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1403
1404         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1405 }
1406
1407 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1408 {
1409         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1410 }
1411
1412 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1413 {
1414         u32 regval;
1415
1416         regval = REG_READ(ah, AR_AHB_MODE);
1417         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1418
1419         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1420         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1421
1422         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1423
1424         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1425         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1426
1427         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1428
1429         if (AR_SREV_9285(ah)) {
1430                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1431                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1432         } else {
1433                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1434                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1435         }
1436 }
1437
1438 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1439 {
1440         u32 val;
1441
1442         val = REG_READ(ah, AR_STA_ID1);
1443         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1444         switch (opmode) {
1445         case NL80211_IFTYPE_AP:
1446                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1447                           | AR_STA_ID1_KSRCH_MODE);
1448                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1449                 break;
1450         case NL80211_IFTYPE_ADHOC:
1451         case NL80211_IFTYPE_MESH_POINT:
1452                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1453                           | AR_STA_ID1_KSRCH_MODE);
1454                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1455                 break;
1456         case NL80211_IFTYPE_STATION:
1457         case NL80211_IFTYPE_MONITOR:
1458                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1459                 break;
1460         }
1461 }
1462
1463 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1464                                                  u32 coef_scaled,
1465                                                  u32 *coef_mantissa,
1466                                                  u32 *coef_exponent)
1467 {
1468         u32 coef_exp, coef_man;
1469
1470         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1471                 if ((coef_scaled >> coef_exp) & 0x1)
1472                         break;
1473
1474         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1475
1476         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1477
1478         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1479         *coef_exponent = coef_exp - 16;
1480 }
1481
1482 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1483                                      struct ath9k_channel *chan)
1484 {
1485         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1486         u32 clockMhzScaled = 0x64000000;
1487         struct chan_centers centers;
1488
1489         if (IS_CHAN_HALF_RATE(chan))
1490                 clockMhzScaled = clockMhzScaled >> 1;
1491         else if (IS_CHAN_QUARTER_RATE(chan))
1492                 clockMhzScaled = clockMhzScaled >> 2;
1493
1494         ath9k_hw_get_channel_centers(ah, chan, &centers);
1495         coef_scaled = clockMhzScaled / centers.synth_center;
1496
1497         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1498                                       &ds_coef_exp);
1499
1500         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1501                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1502         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1503                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1504
1505         coef_scaled = (9 * coef_scaled) / 10;
1506
1507         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1508                                       &ds_coef_exp);
1509
1510         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1511                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1512         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1513                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1514 }
1515
1516 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1517 {
1518         u32 rst_flags;
1519         u32 tmpReg;
1520
1521         if (AR_SREV_9100(ah)) {
1522                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1523                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1524                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1525                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1526                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1527         }
1528
1529         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1530                   AR_RTC_FORCE_WAKE_ON_INT);
1531
1532         if (AR_SREV_9100(ah)) {
1533                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1534                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1535         } else {
1536                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1537                 if (tmpReg &
1538                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1539                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1540                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1541                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1542                 } else {
1543                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1544                 }
1545
1546                 rst_flags = AR_RTC_RC_MAC_WARM;
1547                 if (type == ATH9K_RESET_COLD)
1548                         rst_flags |= AR_RTC_RC_MAC_COLD;
1549         }
1550
1551         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1552         udelay(50);
1553
1554         REG_WRITE(ah, AR_RTC_RC, 0);
1555         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1556                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1557                         "RTC stuck in MAC reset\n");
1558                 return false;
1559         }
1560
1561         if (!AR_SREV_9100(ah))
1562                 REG_WRITE(ah, AR_RC, 0);
1563
1564         ath9k_hw_init_pll(ah, NULL);
1565
1566         if (AR_SREV_9100(ah))
1567                 udelay(50);
1568
1569         return true;
1570 }
1571
1572 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1573 {
1574         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1575                   AR_RTC_FORCE_WAKE_ON_INT);
1576
1577         REG_WRITE(ah, AR_RTC_RESET, 0);
1578         udelay(2);
1579         REG_WRITE(ah, AR_RTC_RESET, 1);
1580
1581         if (!ath9k_hw_wait(ah,
1582                            AR_RTC_STATUS,
1583                            AR_RTC_STATUS_M,
1584                            AR_RTC_STATUS_ON,
1585                            AH_WAIT_TIMEOUT)) {
1586                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1587                 return false;
1588         }
1589
1590         ath9k_hw_read_revisions(ah);
1591
1592         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1593 }
1594
1595 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1596 {
1597         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1598                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1599
1600         switch (type) {
1601         case ATH9K_RESET_POWER_ON:
1602                 return ath9k_hw_set_reset_power_on(ah);
1603                 break;
1604         case ATH9K_RESET_WARM:
1605         case ATH9K_RESET_COLD:
1606                 return ath9k_hw_set_reset(ah, type);
1607                 break;
1608         default:
1609                 return false;
1610         }
1611 }
1612
1613 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1614                               enum ath9k_ht_macmode macmode)
1615 {
1616         u32 phymode;
1617         u32 enableDacFifo = 0;
1618
1619         if (AR_SREV_9285_10_OR_LATER(ah))
1620                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1621                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1622
1623         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1624                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1625
1626         if (IS_CHAN_HT40(chan)) {
1627                 phymode |= AR_PHY_FC_DYN2040_EN;
1628
1629                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1630                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1631                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1632
1633                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1634                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1635         }
1636         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1637
1638         ath9k_hw_set11nmac2040(ah, macmode);
1639
1640         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1641         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1642 }
1643
1644 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1645                                 struct ath9k_channel *chan)
1646 {
1647         if (OLC_FOR_AR9280_20_LATER) {
1648                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1649                         return false;
1650         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1651                 return false;
1652
1653         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1654                 return false;
1655
1656         ah->chip_fullsleep = false;
1657         ath9k_hw_init_pll(ah, chan);
1658         ath9k_hw_set_rfmode(ah, chan);
1659
1660         return true;
1661 }
1662
1663 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1664                                     struct ath9k_channel *chan,
1665                                     enum ath9k_ht_macmode macmode)
1666 {
1667         struct ieee80211_channel *channel = chan->chan;
1668         u32 synthDelay, qnum;
1669
1670         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1671                 if (ath9k_hw_numtxpending(ah, qnum)) {
1672                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1673                                 "Transmit frames pending on queue %d\n", qnum);
1674                         return false;
1675                 }
1676         }
1677
1678         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1679         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1680                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1681                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1682                         "Could not kill baseband RX\n");
1683                 return false;
1684         }
1685
1686         ath9k_hw_set_regs(ah, chan, macmode);
1687
1688         if (AR_SREV_9280_10_OR_LATER(ah)) {
1689                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1690                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1691                                 "failed to set channel\n");
1692                         return false;
1693                 }
1694         } else {
1695                 if (!(ath9k_hw_set_channel(ah, chan))) {
1696                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1697                                 "failed to set channel\n");
1698                         return false;
1699                 }
1700         }
1701
1702         if (ah->eep_ops->set_txpower(ah, chan,
1703                              ath9k_regd_get_ctl(ah, chan),
1704                              channel->max_antenna_gain * 2,
1705                              channel->max_power * 2,
1706                              min((u32) MAX_RATE_POWER,
1707                                  (u32) ah->regulatory.power_limit)) != 0) {
1708                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1709                         "error init'ing transmit power\n");
1710                 return false;
1711         }
1712
1713         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1714         if (IS_CHAN_B(chan))
1715                 synthDelay = (4 * synthDelay) / 22;
1716         else
1717                 synthDelay /= 10;
1718
1719         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1720
1721         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1722
1723         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1724                 ath9k_hw_set_delta_slope(ah, chan);
1725
1726         if (AR_SREV_9280_10_OR_LATER(ah))
1727                 ath9k_hw_9280_spur_mitigate(ah, chan);
1728         else
1729                 ath9k_hw_spur_mitigate(ah, chan);
1730
1731         if (!chan->oneTimeCalsDone)
1732                 chan->oneTimeCalsDone = true;
1733
1734         return true;
1735 }
1736
1737 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1738 {
1739         int bb_spur = AR_NO_SPUR;
1740         int freq;
1741         int bin, cur_bin;
1742         int bb_spur_off, spur_subchannel_sd;
1743         int spur_freq_sd;
1744         int spur_delta_phase;
1745         int denominator;
1746         int upper, lower, cur_vit_mask;
1747         int tmp, newVal;
1748         int i;
1749         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1750                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1751         };
1752         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1753                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1754         };
1755         int inc[4] = { 0, 100, 0, 0 };
1756         struct chan_centers centers;
1757
1758         int8_t mask_m[123];
1759         int8_t mask_p[123];
1760         int8_t mask_amt;
1761         int tmp_mask;
1762         int cur_bb_spur;
1763         bool is2GHz = IS_CHAN_2GHZ(chan);
1764
1765         memset(&mask_m, 0, sizeof(int8_t) * 123);
1766         memset(&mask_p, 0, sizeof(int8_t) * 123);
1767
1768         ath9k_hw_get_channel_centers(ah, chan, &centers);
1769         freq = centers.synth_center;
1770
1771         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1772         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1773                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1774
1775                 if (is2GHz)
1776                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1777                 else
1778                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1779
1780                 if (AR_NO_SPUR == cur_bb_spur)
1781                         break;
1782                 cur_bb_spur = cur_bb_spur - freq;
1783
1784                 if (IS_CHAN_HT40(chan)) {
1785                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1786                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1787                                 bb_spur = cur_bb_spur;
1788                                 break;
1789                         }
1790                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1791                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1792                         bb_spur = cur_bb_spur;
1793                         break;
1794                 }
1795         }
1796
1797         if (AR_NO_SPUR == bb_spur) {
1798                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1799                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1800                 return;
1801         } else {
1802                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1803                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1804         }
1805
1806         bin = bb_spur * 320;
1807
1808         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1809
1810         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1811                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1812                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1813                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1814         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1815
1816         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1817                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1818                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1819                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1820                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1821         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1822
1823         if (IS_CHAN_HT40(chan)) {
1824                 if (bb_spur < 0) {
1825                         spur_subchannel_sd = 1;
1826                         bb_spur_off = bb_spur + 10;
1827                 } else {
1828                         spur_subchannel_sd = 0;
1829                         bb_spur_off = bb_spur - 10;
1830                 }
1831         } else {
1832                 spur_subchannel_sd = 0;
1833                 bb_spur_off = bb_spur;
1834         }
1835
1836         if (IS_CHAN_HT40(chan))
1837                 spur_delta_phase =
1838                         ((bb_spur * 262144) /
1839                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1840         else
1841                 spur_delta_phase =
1842                         ((bb_spur * 524288) /
1843                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1844
1845         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1846         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1847
1848         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1849                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1850                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1851         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1852
1853         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1854         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1855
1856         cur_bin = -6000;
1857         upper = bin + 100;
1858         lower = bin - 100;
1859
1860         for (i = 0; i < 4; i++) {
1861                 int pilot_mask = 0;
1862                 int chan_mask = 0;
1863                 int bp = 0;
1864                 for (bp = 0; bp < 30; bp++) {
1865                         if ((cur_bin > lower) && (cur_bin < upper)) {
1866                                 pilot_mask = pilot_mask | 0x1 << bp;
1867                                 chan_mask = chan_mask | 0x1 << bp;
1868                         }
1869                         cur_bin += 100;
1870                 }
1871                 cur_bin += inc[i];
1872                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1873                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1874         }
1875
1876         cur_vit_mask = 6100;
1877         upper = bin + 120;
1878         lower = bin - 120;
1879
1880         for (i = 0; i < 123; i++) {
1881                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1882
1883                         /* workaround for gcc bug #37014 */
1884                         volatile int tmp_v = abs(cur_vit_mask - bin);
1885
1886                         if (tmp_v < 75)
1887                                 mask_amt = 1;
1888                         else
1889                                 mask_amt = 0;
1890                         if (cur_vit_mask < 0)
1891                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1892                         else
1893                                 mask_p[cur_vit_mask / 100] = mask_amt;
1894                 }
1895                 cur_vit_mask -= 100;
1896         }
1897
1898         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1899                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1900                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1901                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1902                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1903                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1904                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1905                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1906         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1907         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1908
1909         tmp_mask = (mask_m[31] << 28)
1910                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1911                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1912                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1913                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1914                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1915                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1916                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1917         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1918         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1919
1920         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1921                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1922                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1923                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1924                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1925                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1926                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1927                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1928         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1929         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1930
1931         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1932                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1933                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1934                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1935                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1936                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1937                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1938                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1939         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1940         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1941
1942         tmp_mask = (mask_p[15] << 28)
1943                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1944                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1945                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1946                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1947                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1948                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1949                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1950         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1951         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1952
1953         tmp_mask = (mask_p[30] << 28)
1954                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1955                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1956                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1957                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1958                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1959                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1960                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1961         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1962         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1963
1964         tmp_mask = (mask_p[45] << 28)
1965                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1966                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1967                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1968                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1969                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1970                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1971                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1972         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1973         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1974
1975         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1976                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1977                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1978                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1979                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1980                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1981                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1982                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1983         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1984         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1985 }
1986
1987 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1988 {
1989         int bb_spur = AR_NO_SPUR;
1990         int bin, cur_bin;
1991         int spur_freq_sd;
1992         int spur_delta_phase;
1993         int denominator;
1994         int upper, lower, cur_vit_mask;
1995         int tmp, new;
1996         int i;
1997         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1998                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1999         };
2000         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2001                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2002         };
2003         int inc[4] = { 0, 100, 0, 0 };
2004
2005         int8_t mask_m[123];
2006         int8_t mask_p[123];
2007         int8_t mask_amt;
2008         int tmp_mask;
2009         int cur_bb_spur;
2010         bool is2GHz = IS_CHAN_2GHZ(chan);
2011
2012         memset(&mask_m, 0, sizeof(int8_t) * 123);
2013         memset(&mask_p, 0, sizeof(int8_t) * 123);
2014
2015         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2016                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2017                 if (AR_NO_SPUR == cur_bb_spur)
2018                         break;
2019                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2020                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2021                         bb_spur = cur_bb_spur;
2022                         break;
2023                 }
2024         }
2025
2026         if (AR_NO_SPUR == bb_spur)
2027                 return;
2028
2029         bin = bb_spur * 32;
2030
2031         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2032         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2033                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2034                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2035                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2036
2037         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2038
2039         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2040                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2041                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2042                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2043                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2044         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2045
2046         spur_delta_phase = ((bb_spur * 524288) / 100) &
2047                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2048
2049         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2050         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2051
2052         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2053                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2054                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2055         REG_WRITE(ah, AR_PHY_TIMING11, new);
2056
2057         cur_bin = -6000;
2058         upper = bin + 100;
2059         lower = bin - 100;
2060
2061         for (i = 0; i < 4; i++) {
2062                 int pilot_mask = 0;
2063                 int chan_mask = 0;
2064                 int bp = 0;
2065                 for (bp = 0; bp < 30; bp++) {
2066                         if ((cur_bin > lower) && (cur_bin < upper)) {
2067                                 pilot_mask = pilot_mask | 0x1 << bp;
2068                                 chan_mask = chan_mask | 0x1 << bp;
2069                         }
2070                         cur_bin += 100;
2071                 }
2072                 cur_bin += inc[i];
2073                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2074                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2075         }
2076
2077         cur_vit_mask = 6100;
2078         upper = bin + 120;
2079         lower = bin - 120;
2080
2081         for (i = 0; i < 123; i++) {
2082                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2083
2084                         /* workaround for gcc bug #37014 */
2085                         volatile int tmp_v = abs(cur_vit_mask - bin);
2086
2087                         if (tmp_v < 75)
2088                                 mask_amt = 1;
2089                         else
2090                                 mask_amt = 0;
2091                         if (cur_vit_mask < 0)
2092                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2093                         else
2094                                 mask_p[cur_vit_mask / 100] = mask_amt;
2095                 }
2096                 cur_vit_mask -= 100;
2097         }
2098
2099         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2100                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2101                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2102                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2103                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2104                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2105                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2106                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2107         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2108         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2109
2110         tmp_mask = (mask_m[31] << 28)
2111                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2112                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2113                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2114                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2115                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2116                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2117                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2118         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2119         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2120
2121         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2122                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2123                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2124                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2125                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2126                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2127                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2128                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2129         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2130         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2131
2132         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2133                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2134                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2135                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2136                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2137                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2138                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2139                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2140         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2141         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2142
2143         tmp_mask = (mask_p[15] << 28)
2144                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2145                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2146                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2147                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2148                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2149                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2150                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2151         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2152         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2153
2154         tmp_mask = (mask_p[30] << 28)
2155                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2156                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2157                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2158                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2159                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2160                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2161                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2162         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2163         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2164
2165         tmp_mask = (mask_p[45] << 28)
2166                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2167                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2168                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2169                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2170                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2171                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2172                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2173         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2174         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2175
2176         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2177                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2178                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2179                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2180                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2181                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2182                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2183                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2184         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2185         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2186 }
2187
2188 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2189                     bool bChannelChange)
2190 {
2191         u32 saveLedState;
2192         struct ath_softc *sc = ah->ah_sc;
2193         struct ath9k_channel *curchan = ah->curchan;
2194         u32 saveDefAntenna;
2195         u32 macStaId1;
2196         int i, rx_chainmask, r;
2197
2198         ah->extprotspacing = sc->ht_extprotspacing;
2199         ah->txchainmask = sc->tx_chainmask;
2200         ah->rxchainmask = sc->rx_chainmask;
2201
2202         if (AR_SREV_9285(ah)) {
2203                 ah->txchainmask &= 0x1;
2204                 ah->rxchainmask &= 0x1;
2205         } else if (AR_SREV_9280(ah)) {
2206                 ah->txchainmask &= 0x3;
2207                 ah->rxchainmask &= 0x3;
2208         }
2209
2210         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2211                 return -EIO;
2212
2213         if (curchan)
2214                 ath9k_hw_getnf(ah, curchan);
2215
2216         if (bChannelChange &&
2217             (ah->chip_fullsleep != true) &&
2218             (ah->curchan != NULL) &&
2219             (chan->channel != ah->curchan->channel) &&
2220             ((chan->channelFlags & CHANNEL_ALL) ==
2221              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2222             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2223                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2224
2225                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2226                         ath9k_hw_loadnf(ah, ah->curchan);
2227                         ath9k_hw_start_nfcal(ah);
2228                         return 0;
2229                 }
2230         }
2231
2232         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2233         if (saveDefAntenna == 0)
2234                 saveDefAntenna = 1;
2235
2236         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2237
2238         saveLedState = REG_READ(ah, AR_CFG_LED) &
2239                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2240                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2241
2242         ath9k_hw_mark_phy_inactive(ah);
2243
2244         if (!ath9k_hw_chip_reset(ah, chan)) {
2245                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2246                 return -EINVAL;
2247         }
2248
2249         if (AR_SREV_9280_10_OR_LATER(ah))
2250                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2251
2252         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2253         if (r)
2254                 return r;
2255
2256         /* Setup MFP options for CCMP */
2257         if (AR_SREV_9280_20_OR_LATER(ah)) {
2258                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2259                  * frames when constructing CCMP AAD. */
2260                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2261                               0xc7ff);
2262                 ah->sw_mgmt_crypto = false;
2263         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2264                 /* Disable hardware crypto for management frames */
2265                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2266                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2267                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2268                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2269                 ah->sw_mgmt_crypto = true;
2270         } else
2271                 ah->sw_mgmt_crypto = true;
2272
2273         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2274                 ath9k_hw_set_delta_slope(ah, chan);
2275
2276         if (AR_SREV_9280_10_OR_LATER(ah))
2277                 ath9k_hw_9280_spur_mitigate(ah, chan);
2278         else
2279                 ath9k_hw_spur_mitigate(ah, chan);
2280
2281         ah->eep_ops->set_board_values(ah, chan);
2282
2283         ath9k_hw_decrease_chain_power(ah, chan);
2284
2285         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2286         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2287                   | macStaId1
2288                   | AR_STA_ID1_RTS_USE_DEF
2289                   | (ah->config.
2290                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2291                   | ah->sta_id1_defaults);
2292         ath9k_hw_set_operating_mode(ah, ah->opmode);
2293
2294         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2295         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2296
2297         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2298
2299         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2300         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2301                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2302
2303         REG_WRITE(ah, AR_ISR, ~0);
2304
2305         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2306
2307         if (AR_SREV_9280_10_OR_LATER(ah)) {
2308                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2309                         return -EIO;
2310         } else {
2311                 if (!(ath9k_hw_set_channel(ah, chan)))
2312                         return -EIO;
2313         }
2314
2315         for (i = 0; i < AR_NUM_DCU; i++)
2316                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2317
2318         ah->intr_txqs = 0;
2319         for (i = 0; i < ah->caps.total_queues; i++)
2320                 ath9k_hw_resettxqueue(ah, i);
2321
2322         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2323         ath9k_hw_init_qos(ah);
2324
2325 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2326         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2327                 ath9k_enable_rfkill(ah);
2328 #endif
2329         ath9k_hw_init_user_settings(ah);
2330
2331         REG_WRITE(ah, AR_STA_ID1,
2332                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2333
2334         ath9k_hw_set_dma(ah);
2335
2336         REG_WRITE(ah, AR_OBS, 8);
2337
2338         if (ah->intr_mitigation) {
2339
2340                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2341                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2342         }
2343
2344         ath9k_hw_init_bb(ah, chan);
2345
2346         if (!ath9k_hw_init_cal(ah, chan))
2347                 return -EIO;;
2348
2349         rx_chainmask = ah->rxchainmask;
2350         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2351                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2352                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2353         }
2354
2355         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2356
2357         if (AR_SREV_9100(ah)) {
2358                 u32 mask;
2359                 mask = REG_READ(ah, AR_CFG);
2360                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2361                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2362                                 "CFG Byte Swap Set 0x%x\n", mask);
2363                 } else {
2364                         mask =
2365                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2366                         REG_WRITE(ah, AR_CFG, mask);
2367                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2368                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2369                 }
2370         } else {
2371 #ifdef __BIG_ENDIAN
2372                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2373 #endif
2374         }
2375
2376         return 0;
2377 }
2378
2379 /************************/
2380 /* Key Cache Management */
2381 /************************/
2382
2383 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2384 {
2385         u32 keyType;
2386
2387         if (entry >= ah->caps.keycache_size) {
2388                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2389                         "entry %u out of range\n", entry);
2390                 return false;
2391         }
2392
2393         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2394
2395         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2396         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2397         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2398         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2399         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2400         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2401         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2402         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2403
2404         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2405                 u16 micentry = entry + 64;
2406
2407                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2408                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2409                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2410                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2411
2412         }
2413
2414         if (ah->curchan == NULL)
2415                 return true;
2416
2417         return true;
2418 }
2419
2420 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2421 {
2422         u32 macHi, macLo;
2423
2424         if (entry >= ah->caps.keycache_size) {
2425                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2426                         "entry %u out of range\n", entry);
2427                 return false;
2428         }
2429
2430         if (mac != NULL) {
2431                 macHi = (mac[5] << 8) | mac[4];
2432                 macLo = (mac[3] << 24) |
2433                         (mac[2] << 16) |
2434                         (mac[1] << 8) |
2435                         mac[0];
2436                 macLo >>= 1;
2437                 macLo |= (macHi & 1) << 31;
2438                 macHi >>= 1;
2439         } else {
2440                 macLo = macHi = 0;
2441         }
2442         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2443         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2444
2445         return true;
2446 }
2447
2448 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2449                                  const struct ath9k_keyval *k,
2450                                  const u8 *mac)
2451 {
2452         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2453         u32 key0, key1, key2, key3, key4;
2454         u32 keyType;
2455
2456         if (entry >= pCap->keycache_size) {
2457                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2458                         "entry %u out of range\n", entry);
2459                 return false;
2460         }
2461
2462         switch (k->kv_type) {
2463         case ATH9K_CIPHER_AES_OCB:
2464                 keyType = AR_KEYTABLE_TYPE_AES;
2465                 break;
2466         case ATH9K_CIPHER_AES_CCM:
2467                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2468                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2469                                 "AES-CCM not supported by mac rev 0x%x\n",
2470                                 ah->hw_version.macRev);
2471                         return false;
2472                 }
2473                 keyType = AR_KEYTABLE_TYPE_CCM;
2474                 break;
2475         case ATH9K_CIPHER_TKIP:
2476                 keyType = AR_KEYTABLE_TYPE_TKIP;
2477                 if (ATH9K_IS_MIC_ENABLED(ah)
2478                     && entry + 64 >= pCap->keycache_size) {
2479                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2480                                 "entry %u inappropriate for TKIP\n", entry);
2481                         return false;
2482                 }
2483                 break;
2484         case ATH9K_CIPHER_WEP:
2485                 if (k->kv_len < LEN_WEP40) {
2486                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2487                                 "WEP key length %u too small\n", k->kv_len);
2488                         return false;
2489                 }
2490                 if (k->kv_len <= LEN_WEP40)
2491                         keyType = AR_KEYTABLE_TYPE_40;
2492                 else if (k->kv_len <= LEN_WEP104)
2493                         keyType = AR_KEYTABLE_TYPE_104;
2494                 else
2495                         keyType = AR_KEYTABLE_TYPE_128;
2496                 break;
2497         case ATH9K_CIPHER_CLR:
2498                 keyType = AR_KEYTABLE_TYPE_CLR;
2499                 break;
2500         default:
2501                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2502                         "cipher %u not supported\n", k->kv_type);
2503                 return false;
2504         }
2505
2506         key0 = get_unaligned_le32(k->kv_val + 0);
2507         key1 = get_unaligned_le16(k->kv_val + 4);
2508         key2 = get_unaligned_le32(k->kv_val + 6);
2509         key3 = get_unaligned_le16(k->kv_val + 10);
2510         key4 = get_unaligned_le32(k->kv_val + 12);
2511         if (k->kv_len <= LEN_WEP104)
2512                 key4 &= 0xff;
2513
2514         /*
2515          * Note: Key cache registers access special memory area that requires
2516          * two 32-bit writes to actually update the values in the internal
2517          * memory. Consequently, the exact order and pairs used here must be
2518          * maintained.
2519          */
2520
2521         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2522                 u16 micentry = entry + 64;
2523
2524                 /*
2525                  * Write inverted key[47:0] first to avoid Michael MIC errors
2526                  * on frames that could be sent or received at the same time.
2527                  * The correct key will be written in the end once everything
2528                  * else is ready.
2529                  */
2530                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2531                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2532
2533                 /* Write key[95:48] */
2534                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2535                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2536
2537                 /* Write key[127:96] and key type */
2538                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2539                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2540
2541                 /* Write MAC address for the entry */
2542                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2543
2544                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2545                         /*
2546                          * TKIP uses two key cache entries:
2547                          * Michael MIC TX/RX keys in the same key cache entry
2548                          * (idx = main index + 64):
2549                          * key0 [31:0] = RX key [31:0]
2550                          * key1 [15:0] = TX key [31:16]
2551                          * key1 [31:16] = reserved
2552                          * key2 [31:0] = RX key [63:32]
2553                          * key3 [15:0] = TX key [15:0]
2554                          * key3 [31:16] = reserved
2555                          * key4 [31:0] = TX key [63:32]
2556                          */
2557                         u32 mic0, mic1, mic2, mic3, mic4;
2558
2559                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2560                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2561                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2562                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2563                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2564
2565                         /* Write RX[31:0] and TX[31:16] */
2566                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2567                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2568
2569                         /* Write RX[63:32] and TX[15:0] */
2570                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2571                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2572
2573                         /* Write TX[63:32] and keyType(reserved) */
2574                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2575                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2576                                   AR_KEYTABLE_TYPE_CLR);
2577
2578                 } else {
2579                         /*
2580                          * TKIP uses four key cache entries (two for group
2581                          * keys):
2582                          * Michael MIC TX/RX keys are in different key cache
2583                          * entries (idx = main index + 64 for TX and
2584                          * main index + 32 + 96 for RX):
2585                          * key0 [31:0] = TX/RX MIC key [31:0]
2586                          * key1 [31:0] = reserved
2587                          * key2 [31:0] = TX/RX MIC key [63:32]
2588                          * key3 [31:0] = reserved
2589                          * key4 [31:0] = reserved
2590                          *
2591                          * Upper layer code will call this function separately
2592                          * for TX and RX keys when these registers offsets are
2593                          * used.
2594                          */
2595                         u32 mic0, mic2;
2596
2597                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2598                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2599
2600                         /* Write MIC key[31:0] */
2601                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2602                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2603
2604                         /* Write MIC key[63:32] */
2605                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2606                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2607
2608                         /* Write TX[63:32] and keyType(reserved) */
2609                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2610                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2611                                   AR_KEYTABLE_TYPE_CLR);
2612                 }
2613
2614                 /* MAC address registers are reserved for the MIC entry */
2615                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2616                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2617
2618                 /*
2619                  * Write the correct (un-inverted) key[47:0] last to enable
2620                  * TKIP now that all other registers are set with correct
2621                  * values.
2622                  */
2623                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2624                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2625         } else {
2626                 /* Write key[47:0] */
2627                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2628                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2629
2630                 /* Write key[95:48] */
2631                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2632                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2633
2634                 /* Write key[127:96] and key type */
2635                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2636                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2637
2638                 /* Write MAC address for the entry */
2639                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2640         }
2641
2642         return true;
2643 }
2644
2645 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2646 {
2647         if (entry < ah->caps.keycache_size) {
2648                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2649                 if (val & AR_KEYTABLE_VALID)
2650                         return true;
2651         }
2652         return false;
2653 }
2654
2655 /******************************/
2656 /* Power Management (Chipset) */
2657 /******************************/
2658
2659 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2660 {
2661         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2662         if (setChip) {
2663                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2664                             AR_RTC_FORCE_WAKE_EN);
2665                 if (!AR_SREV_9100(ah))
2666                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2667
2668                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2669                             AR_RTC_RESET_EN);
2670         }
2671 }
2672
2673 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2674 {
2675         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2676         if (setChip) {
2677                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2678
2679                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2680                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2681                                   AR_RTC_FORCE_WAKE_ON_INT);
2682                 } else {
2683                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2684                                     AR_RTC_FORCE_WAKE_EN);
2685                 }
2686         }
2687 }
2688
2689 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2690 {
2691         u32 val;
2692         int i;
2693
2694         if (setChip) {
2695                 if ((REG_READ(ah, AR_RTC_STATUS) &
2696                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2697                         if (ath9k_hw_set_reset_reg(ah,
2698                                            ATH9K_RESET_POWER_ON) != true) {
2699                                 return false;
2700                         }
2701                 }
2702                 if (AR_SREV_9100(ah))
2703                         REG_SET_BIT(ah, AR_RTC_RESET,
2704                                     AR_RTC_RESET_EN);
2705
2706                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2707                             AR_RTC_FORCE_WAKE_EN);
2708                 udelay(50);
2709
2710                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2711                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2712                         if (val == AR_RTC_STATUS_ON)
2713                                 break;
2714                         udelay(50);
2715                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2716                                     AR_RTC_FORCE_WAKE_EN);
2717                 }
2718                 if (i == 0) {
2719                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2720                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2721                         return false;
2722                 }
2723         }
2724
2725         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2726
2727         return true;
2728 }
2729
2730 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2731 {
2732         int status = true, setChip = true;
2733         static const char *modes[] = {
2734                 "AWAKE",
2735                 "FULL-SLEEP",
2736                 "NETWORK SLEEP",
2737                 "UNDEFINED"
2738         };
2739
2740         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2741                 modes[ah->power_mode], modes[mode],
2742                 setChip ? "set chip " : "");
2743
2744         switch (mode) {
2745         case ATH9K_PM_AWAKE:
2746                 status = ath9k_hw_set_power_awake(ah, setChip);
2747                 break;
2748         case ATH9K_PM_FULL_SLEEP:
2749                 ath9k_set_power_sleep(ah, setChip);
2750                 ah->chip_fullsleep = true;
2751                 break;
2752         case ATH9K_PM_NETWORK_SLEEP:
2753                 ath9k_set_power_network_sleep(ah, setChip);
2754                 break;
2755         default:
2756                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2757                         "Unknown power mode %u\n", mode);
2758                 return false;
2759         }
2760         ah->power_mode = mode;
2761
2762         return status;
2763 }
2764
2765 /*
2766  * Helper for ASPM support.
2767  *
2768  * Disable PLL when in L0s as well as receiver clock when in L1.
2769  * This power saving option must be enabled through the SerDes.
2770  *
2771  * Programming the SerDes must go through the same 288 bit serial shift
2772  * register as the other analog registers.  Hence the 9 writes.
2773  */
2774 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2775 {
2776         u8 i;
2777
2778         if (ah->is_pciexpress != true)
2779                 return;
2780
2781         /* Do not touch SerDes registers */
2782         if (ah->config.pcie_powersave_enable == 2)
2783                 return;
2784
2785         /* Nothing to do on restore for 11N */
2786         if (restore)
2787                 return;
2788
2789         if (AR_SREV_9280_20_OR_LATER(ah)) {
2790                 /*
2791                  * AR9280 2.0 or later chips use SerDes values from the
2792                  * initvals.h initialized depending on chipset during
2793                  * ath9k_hw_do_attach()
2794                  */
2795                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2796                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2797                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2798                 }
2799         } else if (AR_SREV_9280(ah) &&
2800                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2801                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2802                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2803
2804                 /* RX shut off when elecidle is asserted */
2805                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2806                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2807                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2808
2809                 /* Shut off CLKREQ active in L1 */
2810                 if (ah->config.pcie_clock_req)
2811                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2812                 else
2813                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2814
2815                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2816                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2817                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2818
2819                 /* Load the new settings */
2820                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2821
2822         } else {
2823                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2824                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2825
2826                 /* RX shut off when elecidle is asserted */
2827                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2828                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2829                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2830
2831                 /*
2832                  * Ignore ah->ah_config.pcie_clock_req setting for
2833                  * pre-AR9280 11n
2834                  */
2835                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2836
2837                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2838                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2839                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2840
2841                 /* Load the new settings */
2842                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2843         }
2844
2845         udelay(1000);
2846
2847         /* set bit 19 to allow forcing of pcie core into L1 state */
2848         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2849
2850         /* Several PCIe massages to ensure proper behaviour */
2851         if (ah->config.pcie_waen) {
2852                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2853         } else {
2854                 if (AR_SREV_9285(ah))
2855                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2856                 /*
2857                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2858                  * otherwise card may disappear.
2859                  */
2860                 else if (AR_SREV_9280(ah))
2861                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2862                 else
2863                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2864         }
2865 }
2866
2867 /**********************/
2868 /* Interrupt Handling */
2869 /**********************/
2870
2871 bool ath9k_hw_intrpend(struct ath_hw *ah)
2872 {
2873         u32 host_isr;
2874
2875         if (AR_SREV_9100(ah))
2876                 return true;
2877
2878         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2879         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2880                 return true;
2881
2882         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2883         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2884             && (host_isr != AR_INTR_SPURIOUS))
2885                 return true;
2886
2887         return false;
2888 }
2889
2890 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2891 {
2892         u32 isr = 0;
2893         u32 mask2 = 0;
2894         struct ath9k_hw_capabilities *pCap = &ah->caps;
2895         u32 sync_cause = 0;
2896         bool fatal_int = false;
2897
2898         if (!AR_SREV_9100(ah)) {
2899                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2900                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2901                             == AR_RTC_STATUS_ON) {
2902                                 isr = REG_READ(ah, AR_ISR);
2903                         }
2904                 }
2905
2906                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2907                         AR_INTR_SYNC_DEFAULT;
2908
2909                 *masked = 0;
2910
2911                 if (!isr && !sync_cause)
2912                         return false;
2913         } else {
2914                 *masked = 0;
2915                 isr = REG_READ(ah, AR_ISR);
2916         }
2917
2918         if (isr) {
2919                 if (isr & AR_ISR_BCNMISC) {
2920                         u32 isr2;
2921                         isr2 = REG_READ(ah, AR_ISR_S2);
2922                         if (isr2 & AR_ISR_S2_TIM)
2923                                 mask2 |= ATH9K_INT_TIM;
2924                         if (isr2 & AR_ISR_S2_DTIM)
2925                                 mask2 |= ATH9K_INT_DTIM;
2926                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2927                                 mask2 |= ATH9K_INT_DTIMSYNC;
2928                         if (isr2 & (AR_ISR_S2_CABEND))
2929                                 mask2 |= ATH9K_INT_CABEND;
2930                         if (isr2 & AR_ISR_S2_GTT)
2931                                 mask2 |= ATH9K_INT_GTT;
2932                         if (isr2 & AR_ISR_S2_CST)
2933                                 mask2 |= ATH9K_INT_CST;
2934                         if (isr2 & AR_ISR_S2_TSFOOR)
2935                                 mask2 |= ATH9K_INT_TSFOOR;
2936                 }
2937
2938                 isr = REG_READ(ah, AR_ISR_RAC);
2939                 if (isr == 0xffffffff) {
2940                         *masked = 0;
2941                         return false;
2942                 }
2943
2944                 *masked = isr & ATH9K_INT_COMMON;
2945
2946                 if (ah->intr_mitigation) {
2947                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2948                                 *masked |= ATH9K_INT_RX;
2949                 }
2950
2951                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2952                         *masked |= ATH9K_INT_RX;
2953                 if (isr &
2954                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2955                      AR_ISR_TXEOL)) {
2956                         u32 s0_s, s1_s;
2957
2958                         *masked |= ATH9K_INT_TX;
2959
2960                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2961                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2962                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2963
2964                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2965                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2966                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2967                 }
2968
2969                 if (isr & AR_ISR_RXORN) {
2970                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2971                                 "receive FIFO overrun interrupt\n");
2972                 }
2973
2974                 if (!AR_SREV_9100(ah)) {
2975                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2976                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2977                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2978                                         *masked |= ATH9K_INT_TIM_TIMER;
2979                         }
2980                 }
2981
2982                 *masked |= mask2;
2983         }
2984
2985         if (AR_SREV_9100(ah))
2986                 return true;
2987
2988         if (sync_cause) {
2989                 fatal_int =
2990                         (sync_cause &
2991                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2992                         ? true : false;
2993
2994                 if (fatal_int) {
2995                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2996                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2997                                         "received PCI FATAL interrupt\n");
2998                         }
2999                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3000                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3001                                         "received PCI PERR interrupt\n");
3002                         }
3003                 }
3004                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3005                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3006                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3007                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3008                         REG_WRITE(ah, AR_RC, 0);
3009                         *masked |= ATH9K_INT_FATAL;
3010                 }
3011                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3012                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3013                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3014                 }
3015
3016                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3017                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3018         }
3019
3020         return true;
3021 }
3022
3023 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3024 {
3025         return ah->mask_reg;
3026 }
3027
3028 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3029 {
3030         u32 omask = ah->mask_reg;
3031         u32 mask, mask2;
3032         struct ath9k_hw_capabilities *pCap = &ah->caps;
3033
3034         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3035
3036         if (omask & ATH9K_INT_GLOBAL) {
3037                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3038                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3039                 (void) REG_READ(ah, AR_IER);
3040                 if (!AR_SREV_9100(ah)) {
3041                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3042                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3043
3044                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3045                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3046                 }
3047         }
3048
3049         mask = ints & ATH9K_INT_COMMON;
3050         mask2 = 0;
3051
3052         if (ints & ATH9K_INT_TX) {
3053                 if (ah->txok_interrupt_mask)
3054                         mask |= AR_IMR_TXOK;
3055                 if (ah->txdesc_interrupt_mask)
3056                         mask |= AR_IMR_TXDESC;
3057                 if (ah->txerr_interrupt_mask)
3058                         mask |= AR_IMR_TXERR;
3059                 if (ah->txeol_interrupt_mask)
3060                         mask |= AR_IMR_TXEOL;
3061         }
3062         if (ints & ATH9K_INT_RX) {
3063                 mask |= AR_IMR_RXERR;
3064                 if (ah->intr_mitigation)
3065                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3066                 else
3067                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3068                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3069                         mask |= AR_IMR_GENTMR;
3070         }
3071
3072         if (ints & (ATH9K_INT_BMISC)) {
3073                 mask |= AR_IMR_BCNMISC;
3074                 if (ints & ATH9K_INT_TIM)
3075                         mask2 |= AR_IMR_S2_TIM;
3076                 if (ints & ATH9K_INT_DTIM)
3077                         mask2 |= AR_IMR_S2_DTIM;
3078                 if (ints & ATH9K_INT_DTIMSYNC)
3079                         mask2 |= AR_IMR_S2_DTIMSYNC;
3080                 if (ints & ATH9K_INT_CABEND)
3081                         mask2 |= AR_IMR_S2_CABEND;
3082                 if (ints & ATH9K_INT_TSFOOR)
3083                         mask2 |= AR_IMR_S2_TSFOOR;
3084         }
3085
3086         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3087                 mask |= AR_IMR_BCNMISC;
3088                 if (ints & ATH9K_INT_GTT)
3089                         mask2 |= AR_IMR_S2_GTT;
3090                 if (ints & ATH9K_INT_CST)
3091                         mask2 |= AR_IMR_S2_CST;
3092         }
3093
3094         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3095         REG_WRITE(ah, AR_IMR, mask);
3096         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3097                                            AR_IMR_S2_DTIM |
3098                                            AR_IMR_S2_DTIMSYNC |
3099                                            AR_IMR_S2_CABEND |
3100                                            AR_IMR_S2_CABTO |
3101                                            AR_IMR_S2_TSFOOR |
3102                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3103         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3104         ah->mask_reg = ints;
3105
3106         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3107                 if (ints & ATH9K_INT_TIM_TIMER)
3108                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3109                 else
3110                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3111         }
3112
3113         if (ints & ATH9K_INT_GLOBAL) {
3114                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3115                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3116                 if (!AR_SREV_9100(ah)) {
3117                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3118                                   AR_INTR_MAC_IRQ);
3119                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3120
3121
3122                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3123                                   AR_INTR_SYNC_DEFAULT);
3124                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3125                                   AR_INTR_SYNC_DEFAULT);
3126                 }
3127                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3128                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3129         }
3130
3131         return omask;
3132 }
3133
3134 /*******************/
3135 /* Beacon Handling */
3136 /*******************/
3137
3138 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3139 {
3140         int flags = 0;
3141
3142         ah->beacon_interval = beacon_period;
3143
3144         switch (ah->opmode) {
3145         case NL80211_IFTYPE_STATION:
3146         case NL80211_IFTYPE_MONITOR:
3147                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3148                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3149                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3150                 flags |= AR_TBTT_TIMER_EN;
3151                 break;
3152         case NL80211_IFTYPE_ADHOC:
3153         case NL80211_IFTYPE_MESH_POINT:
3154                 REG_SET_BIT(ah, AR_TXCFG,
3155                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3156                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3157                           TU_TO_USEC(next_beacon +
3158                                      (ah->atim_window ? ah->
3159                                       atim_window : 1)));
3160                 flags |= AR_NDP_TIMER_EN;
3161         case NL80211_IFTYPE_AP:
3162                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3163                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3164                           TU_TO_USEC(next_beacon -
3165                                      ah->config.
3166                                      dma_beacon_response_time));
3167                 REG_WRITE(ah, AR_NEXT_SWBA,
3168                           TU_TO_USEC(next_beacon -
3169                                      ah->config.
3170                                      sw_beacon_response_time));
3171                 flags |=
3172                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3173                 break;
3174         default:
3175                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3176                         "%s: unsupported opmode: %d\n",
3177                         __func__, ah->opmode);
3178                 return;
3179                 break;
3180         }
3181
3182         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3183         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3184         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3185         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3186
3187         beacon_period &= ~ATH9K_BEACON_ENA;
3188         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3189                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3190                 ath9k_hw_reset_tsf(ah);
3191         }
3192
3193         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3194 }
3195
3196 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3197                                     const struct ath9k_beacon_state *bs)
3198 {
3199         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3200         struct ath9k_hw_capabilities *pCap = &ah->caps;
3201
3202         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3203
3204         REG_WRITE(ah, AR_BEACON_PERIOD,
3205                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3206         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3207                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3208
3209         REG_RMW_FIELD(ah, AR_RSSI_THR,
3210                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3211
3212         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3213
3214         if (bs->bs_sleepduration > beaconintval)
3215                 beaconintval = bs->bs_sleepduration;
3216
3217         dtimperiod = bs->bs_dtimperiod;
3218         if (bs->bs_sleepduration > dtimperiod)
3219                 dtimperiod = bs->bs_sleepduration;
3220
3221         if (beaconintval == dtimperiod)
3222                 nextTbtt = bs->bs_nextdtim;
3223         else
3224                 nextTbtt = bs->bs_nexttbtt;
3225
3226         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3227         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3228         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3229         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3230
3231         REG_WRITE(ah, AR_NEXT_DTIM,
3232                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3233         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3234
3235         REG_WRITE(ah, AR_SLEEP1,
3236                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3237                   | AR_SLEEP1_ASSUME_DTIM);
3238
3239         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3240                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3241         else
3242                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3243
3244         REG_WRITE(ah, AR_SLEEP2,
3245                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3246
3247         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3248         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3249
3250         REG_SET_BIT(ah, AR_TIMER_MODE,
3251                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3252                     AR_DTIM_TIMER_EN);
3253
3254         /* TSF Out of Range Threshold */
3255         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3256 }
3257
3258 /*******************/
3259 /* HW Capabilities */
3260 /*******************/
3261
3262 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3263 {
3264         struct ath9k_hw_capabilities *pCap = &ah->caps;
3265         u16 capField = 0, eeval;
3266
3267         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3268         ah->regulatory.current_rd = eeval;
3269
3270         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3271         if (AR_SREV_9285_10_OR_LATER(ah))
3272                 eeval |= AR9285_RDEXT_DEFAULT;
3273         ah->regulatory.current_rd_ext = eeval;
3274
3275         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3276
3277         if (ah->opmode != NL80211_IFTYPE_AP &&
3278             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3279                 if (ah->regulatory.current_rd == 0x64 ||
3280                     ah->regulatory.current_rd == 0x65)
3281                         ah->regulatory.current_rd += 5;
3282                 else if (ah->regulatory.current_rd == 0x41)
3283                         ah->regulatory.current_rd = 0x43;
3284                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3285                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3286         }
3287
3288         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3289         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3290
3291         if (eeval & AR5416_OPFLAGS_11A) {
3292                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3293                 if (ah->config.ht_enable) {
3294                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3295                                 set_bit(ATH9K_MODE_11NA_HT20,
3296                                         pCap->wireless_modes);
3297                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3298                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3299                                         pCap->wireless_modes);
3300                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3301                                         pCap->wireless_modes);
3302                         }
3303                 }
3304         }
3305
3306         if (eeval & AR5416_OPFLAGS_11G) {
3307                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3308                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3309                 if (ah->config.ht_enable) {
3310                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3311                                 set_bit(ATH9K_MODE_11NG_HT20,
3312                                         pCap->wireless_modes);
3313                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3314                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3315                                         pCap->wireless_modes);
3316                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3317                                         pCap->wireless_modes);
3318                         }
3319                 }
3320         }
3321
3322         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3323         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3324             !(eeval & AR5416_OPFLAGS_11A))
3325                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3326         else
3327                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3328
3329         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3330                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3331
3332         pCap->low_2ghz_chan = 2312;
3333         pCap->high_2ghz_chan = 2732;
3334
3335         pCap->low_5ghz_chan = 4920;
3336         pCap->high_5ghz_chan = 6100;
3337
3338         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3339         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3340         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3341
3342         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3343         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3344         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3345
3346         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3347
3348         if (ah->config.ht_enable)
3349                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3350         else
3351                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3352
3353         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3354         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3355         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3356         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3357
3358         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3359                 pCap->total_queues =
3360                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3361         else
3362                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3363
3364         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3365                 pCap->keycache_size =
3366                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3367         else
3368                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3369
3370         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3371         pCap->num_mr_retries = 4;
3372         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3373
3374         if (AR_SREV_9285_10_OR_LATER(ah))
3375                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3376         else if (AR_SREV_9280_10_OR_LATER(ah))
3377                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3378         else
3379                 pCap->num_gpio_pins = AR_NUM_GPIO;
3380
3381         if (AR_SREV_9280_10_OR_LATER(ah)) {
3382                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3383                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3384         } else {
3385                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3386                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3387         }
3388
3389         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3390                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3391                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3392         } else {
3393                 pCap->rts_aggr_limit = (8 * 1024);
3394         }
3395
3396         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3397
3398 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3399         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3400         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3401                 ah->rfkill_gpio =
3402                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3403                 ah->rfkill_polarity =
3404                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3405
3406                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3407         }
3408 #endif
3409
3410         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3411             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3412             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3413             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3414             (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3415                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3416         else
3417                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3418
3419         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3420                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3421         else
3422                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3423
3424         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3425                 pCap->reg_cap =
3426                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3427                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3428                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3429                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3430         } else {
3431                 pCap->reg_cap =
3432                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3433                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3434         }
3435
3436         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3437
3438         pCap->num_antcfg_5ghz =
3439                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3440         pCap->num_antcfg_2ghz =
3441                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3442
3443         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3444                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3445                 ah->btactive_gpio = 6;
3446                 ah->wlanactive_gpio = 5;
3447         }
3448
3449         return true;
3450 }
3451
3452 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3453                             u32 capability, u32 *result)
3454 {
3455         switch (type) {
3456         case ATH9K_CAP_CIPHER:
3457                 switch (capability) {
3458                 case ATH9K_CIPHER_AES_CCM:
3459                 case ATH9K_CIPHER_AES_OCB:
3460                 case ATH9K_CIPHER_TKIP:
3461                 case ATH9K_CIPHER_WEP:
3462                 case ATH9K_CIPHER_MIC:
3463                 case ATH9K_CIPHER_CLR:
3464                         return true;
3465                 default:
3466                         return false;
3467                 }
3468         case ATH9K_CAP_TKIP_MIC:
3469                 switch (capability) {
3470                 case 0:
3471                         return true;
3472                 case 1:
3473                         return (ah->sta_id1_defaults &
3474                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3475                         false;
3476                 }
3477         case ATH9K_CAP_TKIP_SPLIT:
3478                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3479                         false : true;
3480         case ATH9K_CAP_DIVERSITY:
3481                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3482                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3483                         true : false;
3484         case ATH9K_CAP_MCAST_KEYSRCH:
3485                 switch (capability) {
3486                 case 0:
3487                         return true;
3488                 case 1:
3489                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3490                                 return false;
3491                         } else {
3492                                 return (ah->sta_id1_defaults &
3493                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3494                                         false;
3495                         }
3496                 }
3497                 return false;
3498         case ATH9K_CAP_TXPOW:
3499                 switch (capability) {
3500                 case 0:
3501                         return 0;
3502                 case 1:
3503                         *result = ah->regulatory.power_limit;
3504                         return 0;
3505                 case 2:
3506                         *result = ah->regulatory.max_power_level;
3507                         return 0;
3508                 case 3:
3509                         *result = ah->regulatory.tp_scale;
3510                         return 0;
3511                 }
3512                 return false;
3513         case ATH9K_CAP_DS:
3514                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3515                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3516                         ? false : true;
3517         default:
3518                 return false;
3519         }
3520 }
3521
3522 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3523                             u32 capability, u32 setting, int *status)
3524 {
3525         u32 v;
3526
3527         switch (type) {
3528         case ATH9K_CAP_TKIP_MIC:
3529                 if (setting)
3530                         ah->sta_id1_defaults |=
3531                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3532                 else
3533                         ah->sta_id1_defaults &=
3534                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3535                 return true;
3536         case ATH9K_CAP_DIVERSITY:
3537                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3538                 if (setting)
3539                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3540                 else
3541                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3542                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3543                 return true;
3544         case ATH9K_CAP_MCAST_KEYSRCH:
3545                 if (setting)
3546                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3547                 else
3548                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3549                 return true;
3550         default:
3551                 return false;
3552         }
3553 }
3554
3555 /****************************/
3556 /* GPIO / RFKILL / Antennae */
3557 /****************************/
3558
3559 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3560                                          u32 gpio, u32 type)
3561 {
3562         int addr;
3563         u32 gpio_shift, tmp;
3564
3565         if (gpio > 11)
3566                 addr = AR_GPIO_OUTPUT_MUX3;
3567         else if (gpio > 5)
3568                 addr = AR_GPIO_OUTPUT_MUX2;
3569         else
3570                 addr = AR_GPIO_OUTPUT_MUX1;
3571
3572         gpio_shift = (gpio % 6) * 5;
3573
3574         if (AR_SREV_9280_20_OR_LATER(ah)
3575             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3576                 REG_RMW(ah, addr, (type << gpio_shift),
3577                         (0x1f << gpio_shift));
3578         } else {
3579                 tmp = REG_READ(ah, addr);
3580                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3581                 tmp &= ~(0x1f << gpio_shift);
3582                 tmp |= (type << gpio_shift);
3583                 REG_WRITE(ah, addr, tmp);
3584         }
3585 }
3586
3587 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3588 {
3589         u32 gpio_shift;
3590
3591         ASSERT(gpio < ah->caps.num_gpio_pins);
3592
3593         gpio_shift = gpio << 1;
3594
3595         REG_RMW(ah,
3596                 AR_GPIO_OE_OUT,
3597                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3598                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3599 }
3600
3601 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3602 {
3603 #define MS_REG_READ(x, y) \
3604         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3605
3606         if (gpio >= ah->caps.num_gpio_pins)
3607                 return 0xffffffff;
3608
3609         if (AR_SREV_9285_10_OR_LATER(ah))
3610                 return MS_REG_READ(AR9285, gpio) != 0;
3611         else if (AR_SREV_9280_10_OR_LATER(ah))
3612                 return MS_REG_READ(AR928X, gpio) != 0;
3613         else
3614                 return MS_REG_READ(AR, gpio) != 0;
3615 }
3616
3617 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3618                          u32 ah_signal_type)
3619 {
3620         u32 gpio_shift;
3621
3622         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3623
3624         gpio_shift = 2 * gpio;
3625
3626         REG_RMW(ah,
3627                 AR_GPIO_OE_OUT,
3628                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3629                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3630 }
3631
3632 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3633 {
3634         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3635                 AR_GPIO_BIT(gpio));
3636 }
3637
3638 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3639 void ath9k_enable_rfkill(struct ath_hw *ah)
3640 {
3641         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3642                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3643
3644         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3645                     AR_GPIO_INPUT_MUX2_RFSILENT);
3646
3647         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3648         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3649 }
3650 #endif
3651
3652 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3653 {
3654         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3655 }
3656
3657 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3658 {
3659         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3660 }
3661
3662 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3663                                enum ath9k_ant_setting settings,
3664                                struct ath9k_channel *chan,
3665                                u8 *tx_chainmask,
3666                                u8 *rx_chainmask,
3667                                u8 *antenna_cfgd)
3668 {
3669         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3670
3671         if (AR_SREV_9280(ah)) {
3672                 if (!tx_chainmask_cfg) {
3673
3674                         tx_chainmask_cfg = *tx_chainmask;
3675                         rx_chainmask_cfg = *rx_chainmask;
3676                 }
3677
3678                 switch (settings) {
3679                 case ATH9K_ANT_FIXED_A:
3680                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3681                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3682                         *antenna_cfgd = true;
3683                         break;
3684                 case ATH9K_ANT_FIXED_B:
3685                         if (ah->caps.tx_chainmask >
3686                             ATH9K_ANTENNA1_CHAINMASK) {
3687                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3688                         }
3689                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3690                         *antenna_cfgd = true;
3691                         break;
3692                 case ATH9K_ANT_VARIABLE:
3693                         *tx_chainmask = tx_chainmask_cfg;
3694                         *rx_chainmask = rx_chainmask_cfg;
3695                         *antenna_cfgd = true;
3696                         break;
3697                 default:
3698                         break;
3699                 }
3700         } else {
3701                 ah->diversity_control = settings;
3702         }
3703
3704         return true;
3705 }
3706
3707 /*********************/
3708 /* General Operation */
3709 /*********************/
3710
3711 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3712 {
3713         u32 bits = REG_READ(ah, AR_RX_FILTER);
3714         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3715
3716         if (phybits & AR_PHY_ERR_RADAR)
3717                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3718         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3719                 bits |= ATH9K_RX_FILTER_PHYERR;
3720
3721         return bits;
3722 }
3723
3724 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3725 {
3726         u32 phybits;
3727
3728         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3729         phybits = 0;
3730         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3731                 phybits |= AR_PHY_ERR_RADAR;
3732         if (bits & ATH9K_RX_FILTER_PHYERR)
3733                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3734         REG_WRITE(ah, AR_PHY_ERR, phybits);
3735
3736         if (phybits)
3737                 REG_WRITE(ah, AR_RXCFG,
3738                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3739         else
3740                 REG_WRITE(ah, AR_RXCFG,
3741                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3742 }
3743
3744 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3745 {
3746         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3747 }
3748
3749 bool ath9k_hw_disable(struct ath_hw *ah)
3750 {
3751         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3752                 return false;
3753
3754         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3755 }
3756
3757 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3758 {
3759         struct ath9k_channel *chan = ah->curchan;
3760         struct ieee80211_channel *channel = chan->chan;
3761
3762         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3763
3764         if (ah->eep_ops->set_txpower(ah, chan,
3765                              ath9k_regd_get_ctl(ah, chan),
3766                              channel->max_antenna_gain * 2,
3767                              channel->max_power * 2,
3768                              min((u32) MAX_RATE_POWER,
3769                                  (u32) ah->regulatory.power_limit)) != 0)
3770                 return false;
3771
3772         return true;
3773 }
3774
3775 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3776 {
3777         memcpy(ah->macaddr, mac, ETH_ALEN);
3778 }
3779
3780 void ath9k_hw_setopmode(struct ath_hw *ah)
3781 {
3782         ath9k_hw_set_operating_mode(ah, ah->opmode);
3783 }
3784
3785 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3786 {
3787         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3788         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3789 }
3790
3791 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3792 {
3793         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3794         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3795 }
3796
3797 void ath9k_hw_write_associd(struct ath_softc *sc)
3798 {
3799         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3800         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3801                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3802 }
3803
3804 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3805 {
3806         u64 tsf;
3807
3808         tsf = REG_READ(ah, AR_TSF_U32);
3809         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3810
3811         return tsf;
3812 }
3813
3814 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3815 {
3816         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3817         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3818 }
3819
3820 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3821 {
3822         int count;
3823
3824         count = 0;
3825         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3826                 count++;
3827                 if (count > 10) {
3828                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3829                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3830                         break;
3831                 }
3832                 udelay(10);
3833         }
3834         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3835 }
3836
3837 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3838 {
3839         if (setting)
3840                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3841         else
3842                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3843
3844         return true;
3845 }
3846
3847 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3848 {
3849         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3850                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3851                 ah->slottime = (u32) -1;
3852                 return false;
3853         } else {
3854                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3855                 ah->slottime = us;
3856                 return true;
3857         }
3858 }
3859
3860 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3861 {
3862         u32 macmode;
3863
3864         if (mode == ATH9K_HT_MACMODE_2040 &&
3865             !ah->config.cwm_ignore_extcca)
3866                 macmode = AR_2040_JOINED_RX_CLEAR;
3867         else
3868                 macmode = 0;
3869
3870         REG_WRITE(ah, AR_2040_MODE, macmode);
3871 }
3872
3873 /***************************/
3874 /*  Bluetooth Coexistence  */
3875 /***************************/
3876
3877 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3878 {
3879         /* connect bt_active to baseband */
3880         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3881                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3882                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3883
3884         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3885                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3886
3887         /* Set input mux for bt_active to gpio pin */
3888         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3889                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3890                         ah->btactive_gpio);
3891
3892         /* Configure the desired gpio port for input */
3893         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3894
3895         /* Configure the desired GPIO port for TX_FRAME output */
3896         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3897                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3898 }