2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
35 static u16 bits_per_symbol[][2] = {
37 { 26, 54 }, /* 0: BPSK */
38 { 52, 108 }, /* 1: QPSK 1/2 */
39 { 78, 162 }, /* 2: QPSK 3/4 */
40 { 104, 216 }, /* 3: 16-QAM 1/2 */
41 { 156, 324 }, /* 4: 16-QAM 3/4 */
42 { 208, 432 }, /* 5: 64-QAM 2/3 */
43 { 234, 486 }, /* 6: 64-QAM 3/4 */
44 { 260, 540 }, /* 7: 64-QAM 5/6 */
47 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
49 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
50 struct ath_atx_tid *tid,
51 struct list_head *bf_head);
52 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
53 struct ath_txq *txq, struct list_head *bf_q,
54 struct ath_tx_status *ts, int txok, int sendbar);
55 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
56 struct list_head *head);
57 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
58 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
59 struct ath_tx_status *ts, int nframes, int nbad,
60 int txok, bool update_rc);
61 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
71 static int ath_max_4ms_framelen[4][32] = {
73 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
74 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
75 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
76 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
79 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
80 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
81 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
82 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
85 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
86 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
87 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
88 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
91 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
92 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
93 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
94 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
98 /*********************/
99 /* Aggregation logic */
100 /*********************/
102 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
104 struct ath_atx_ac *ac = tid->ac;
113 list_add_tail(&tid->list, &ac->tid_q);
119 list_add_tail(&ac->list, &txq->axq_acq);
122 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
124 struct ath_txq *txq = tid->ac->txq;
126 WARN_ON(!tid->paused);
128 spin_lock_bh(&txq->axq_lock);
131 if (list_empty(&tid->buf_q))
134 ath_tx_queue_tid(txq, tid);
135 ath_txq_schedule(sc, txq);
137 spin_unlock_bh(&txq->axq_lock);
140 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
142 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
143 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
144 sizeof(tx_info->rate_driver_data));
145 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
148 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
150 struct ath_txq *txq = tid->ac->txq;
152 struct list_head bf_head;
153 struct ath_tx_status ts;
154 struct ath_frame_info *fi;
156 INIT_LIST_HEAD(&bf_head);
158 memset(&ts, 0, sizeof(ts));
159 spin_lock_bh(&txq->axq_lock);
161 while (!list_empty(&tid->buf_q)) {
162 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
163 list_move_tail(&bf->list, &bf_head);
165 spin_unlock_bh(&txq->axq_lock);
166 fi = get_frame_info(bf->bf_mpdu);
168 ath_tx_update_baw(sc, tid, fi->seqno);
169 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
171 ath_tx_send_normal(sc, txq, NULL, &bf_head);
173 spin_lock_bh(&txq->axq_lock);
176 spin_unlock_bh(&txq->axq_lock);
179 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
184 index = ATH_BA_INDEX(tid->seq_start, seqno);
185 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
187 __clear_bit(cindex, tid->tx_buf);
189 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
190 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
191 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
195 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
200 index = ATH_BA_INDEX(tid->seq_start, seqno);
201 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
202 __set_bit(cindex, tid->tx_buf);
204 if (index >= ((tid->baw_tail - tid->baw_head) &
205 (ATH_TID_MAX_BUFS - 1))) {
206 tid->baw_tail = cindex;
207 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
212 * TODO: For frame(s) that are in the retry state, we will reuse the
213 * sequence number(s) without setting the retry bit. The
214 * alternative is to give up on these and BAR the receiver's window
217 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
218 struct ath_atx_tid *tid)
222 struct list_head bf_head;
223 struct ath_tx_status ts;
224 struct ath_frame_info *fi;
226 memset(&ts, 0, sizeof(ts));
227 INIT_LIST_HEAD(&bf_head);
230 if (list_empty(&tid->buf_q))
233 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
234 list_move_tail(&bf->list, &bf_head);
236 fi = get_frame_info(bf->bf_mpdu);
238 ath_tx_update_baw(sc, tid, fi->seqno);
240 spin_unlock(&txq->axq_lock);
241 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
242 spin_lock(&txq->axq_lock);
245 tid->seq_next = tid->seq_start;
246 tid->baw_tail = tid->baw_head;
249 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
252 struct ath_frame_info *fi = get_frame_info(skb);
253 struct ieee80211_hdr *hdr;
255 TX_STAT_INC(txq->axq_qnum, a_retries);
256 if (fi->retries++ > 0)
259 hdr = (struct ieee80211_hdr *)skb->data;
260 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
263 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
265 struct ath_buf *bf = NULL;
267 spin_lock_bh(&sc->tx.txbuflock);
269 if (unlikely(list_empty(&sc->tx.txbuf))) {
270 spin_unlock_bh(&sc->tx.txbuflock);
274 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
277 spin_unlock_bh(&sc->tx.txbuflock);
282 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
284 spin_lock_bh(&sc->tx.txbuflock);
285 list_add_tail(&bf->list, &sc->tx.txbuf);
286 spin_unlock_bh(&sc->tx.txbuflock);
289 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
293 tbf = ath_tx_get_buffer(sc);
297 ATH_TXBUF_RESET(tbf);
299 tbf->bf_mpdu = bf->bf_mpdu;
300 tbf->bf_buf_addr = bf->bf_buf_addr;
301 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
302 tbf->bf_state = bf->bf_state;
307 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
308 struct ath_tx_status *ts, int txok,
309 int *nframes, int *nbad)
311 struct ath_frame_info *fi;
313 u32 ba[WME_BA_BMP_SIZE >> 5];
320 isaggr = bf_isaggr(bf);
322 seq_st = ts->ts_seqnum;
323 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
327 fi = get_frame_info(bf->bf_mpdu);
328 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
331 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
339 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
340 struct ath_buf *bf, struct list_head *bf_q,
341 struct ath_tx_status *ts, int txok, bool retry)
343 struct ath_node *an = NULL;
345 struct ieee80211_sta *sta;
346 struct ieee80211_hw *hw = sc->hw;
347 struct ieee80211_hdr *hdr;
348 struct ieee80211_tx_info *tx_info;
349 struct ath_atx_tid *tid = NULL;
350 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
351 struct list_head bf_head, bf_pending;
352 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
353 u32 ba[WME_BA_BMP_SIZE >> 5];
354 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
355 bool rc_update = true;
356 struct ieee80211_tx_rate rates[4];
357 struct ath_frame_info *fi;
362 hdr = (struct ieee80211_hdr *)skb->data;
364 tx_info = IEEE80211_SKB_CB(skb);
366 memcpy(rates, tx_info->control.rates, sizeof(rates));
370 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
374 INIT_LIST_HEAD(&bf_head);
376 bf_next = bf->bf_next;
378 bf->bf_state.bf_type |= BUF_XRETRY;
379 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
380 !bf->bf_stale || bf_next != NULL)
381 list_move_tail(&bf->list, &bf_head);
383 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
384 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
392 an = (struct ath_node *)sta->drv_priv;
393 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
394 tid = ATH_AN_2_TID(an, tidno);
397 * The hardware occasionally sends a tx status for the wrong TID.
398 * In this case, the BA status cannot be considered valid and all
399 * subframes need to be retransmitted
401 if (tidno != ts->tid)
404 isaggr = bf_isaggr(bf);
405 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
407 if (isaggr && txok) {
408 if (ts->ts_flags & ATH9K_TX_BA) {
409 seq_st = ts->ts_seqnum;
410 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
413 * AR5416 can become deaf/mute when BA
414 * issue happens. Chip needs to be reset.
415 * But AP code may have sychronization issues
416 * when perform internal reset in this routine.
417 * Only enable reset in STA mode for now.
419 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
424 INIT_LIST_HEAD(&bf_pending);
425 INIT_LIST_HEAD(&bf_head);
427 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
429 txfail = txpending = sendbar = 0;
430 bf_next = bf->bf_next;
433 tx_info = IEEE80211_SKB_CB(skb);
434 fi = get_frame_info(skb);
436 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
437 /* transmit completion, subframe is
438 * acked by block ack */
440 } else if (!isaggr && txok) {
441 /* transmit completion */
444 if (!(tid->state & AGGR_CLEANUP) && retry) {
445 if (fi->retries < ATH_MAX_SW_RETRIES) {
446 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
449 bf->bf_state.bf_type |= BUF_XRETRY;
456 * cleanup in progress, just fail
457 * the un-acked sub-frames
463 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
466 * Make sure the last desc is reclaimed if it
467 * not a holding desc.
469 if (!bf_last->bf_stale)
470 list_move_tail(&bf->list, &bf_head);
472 INIT_LIST_HEAD(&bf_head);
474 BUG_ON(list_empty(bf_q));
475 list_move_tail(&bf->list, &bf_head);
478 if (!txpending || (tid->state & AGGR_CLEANUP)) {
480 * complete the acked-ones/xretried ones; update
483 spin_lock_bh(&txq->axq_lock);
484 ath_tx_update_baw(sc, tid, fi->seqno);
485 spin_unlock_bh(&txq->axq_lock);
487 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
488 memcpy(tx_info->control.rates, rates, sizeof(rates));
489 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
492 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
495 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
498 /* retry the un-acked ones */
499 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
500 if (bf->bf_next == NULL && bf_last->bf_stale) {
503 tbf = ath_clone_txbuf(sc, bf_last);
505 * Update tx baw and complete the
506 * frame with failed status if we
510 spin_lock_bh(&txq->axq_lock);
511 ath_tx_update_baw(sc, tid, fi->seqno);
512 spin_unlock_bh(&txq->axq_lock);
514 bf->bf_state.bf_type |=
516 ath_tx_rc_status(sc, bf, ts, nframes,
518 ath_tx_complete_buf(sc, bf, txq,
524 ath9k_hw_cleartxdesc(sc->sc_ah,
526 list_add_tail(&tbf->list, &bf_head);
529 * Clear descriptor status words for
532 ath9k_hw_cleartxdesc(sc->sc_ah,
538 * Put this buffer to the temporary pending
539 * queue to retain ordering
541 list_splice_tail_init(&bf_head, &bf_pending);
547 /* prepend un-acked frames to the beginning of the pending frame queue */
548 if (!list_empty(&bf_pending)) {
549 spin_lock_bh(&txq->axq_lock);
550 list_splice(&bf_pending, &tid->buf_q);
551 ath_tx_queue_tid(txq, tid);
552 spin_unlock_bh(&txq->axq_lock);
555 if (tid->state & AGGR_CLEANUP) {
556 ath_tx_flush_tid(sc, tid);
558 if (tid->baw_head == tid->baw_tail) {
559 tid->state &= ~AGGR_ADDBA_COMPLETE;
560 tid->state &= ~AGGR_CLEANUP;
567 ath_reset(sc, false);
570 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
571 struct ath_atx_tid *tid)
574 struct ieee80211_tx_info *tx_info;
575 struct ieee80211_tx_rate *rates;
576 u32 max_4ms_framelen, frmlen;
577 u16 aggr_limit, legacy = 0;
581 tx_info = IEEE80211_SKB_CB(skb);
582 rates = tx_info->control.rates;
585 * Find the lowest frame length among the rate series that will have a
586 * 4ms transmit duration.
587 * TODO - TXOP limit needs to be considered.
589 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
591 for (i = 0; i < 4; i++) {
592 if (rates[i].count) {
594 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
599 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
604 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
607 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
608 max_4ms_framelen = min(max_4ms_framelen, frmlen);
613 * limit aggregate size by the minimum rate if rate selected is
614 * not a probe rate, if rate selected is a probe rate then
615 * avoid aggregation of this packet.
617 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
620 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
621 aggr_limit = min((max_4ms_framelen * 3) / 8,
622 (u32)ATH_AMPDU_LIMIT_MAX);
624 aggr_limit = min(max_4ms_framelen,
625 (u32)ATH_AMPDU_LIMIT_MAX);
628 * h/w can accept aggregates upto 16 bit lengths (65535).
629 * The IE, however can hold upto 65536, which shows up here
630 * as zero. Ignore 65536 since we are constrained by hw.
632 if (tid->an->maxampdu)
633 aggr_limit = min(aggr_limit, tid->an->maxampdu);
639 * Returns the number of delimiters to be added to
640 * meet the minimum required mpdudensity.
642 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
643 struct ath_buf *bf, u16 frmlen)
645 struct sk_buff *skb = bf->bf_mpdu;
646 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
647 u32 nsymbits, nsymbols;
650 int width, streams, half_gi, ndelim, mindelim;
651 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
653 /* Select standard number of delimiters based on frame length alone */
654 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
657 * If encryption enabled, hardware requires some more padding between
659 * TODO - this could be improved to be dependent on the rate.
660 * The hardware can keep up at lower rates, but not higher rates
662 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
663 ndelim += ATH_AGGR_ENCRYPTDELIM;
666 * Convert desired mpdu density from microeconds to bytes based
667 * on highest rate in rate series (i.e. first rate) to determine
668 * required minimum length for subframe. Take into account
669 * whether high rate is 20 or 40Mhz and half or full GI.
671 * If there is no mpdu density restriction, no further calculation
675 if (tid->an->mpdudensity == 0)
678 rix = tx_info->control.rates[0].idx;
679 flags = tx_info->control.rates[0].flags;
680 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
681 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
684 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
686 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
691 streams = HT_RC_2_STREAMS(rix);
692 nsymbits = bits_per_symbol[rix % 8][width] * streams;
693 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
695 if (frmlen < minlen) {
696 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
697 ndelim = max(mindelim, ndelim);
703 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
705 struct ath_atx_tid *tid,
706 struct list_head *bf_q,
709 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
710 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
711 int rl = 0, nframes = 0, ndelim, prev_al = 0;
712 u16 aggr_limit = 0, al = 0, bpad = 0,
713 al_delta, h_baw = tid->baw_size / 2;
714 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
715 struct ieee80211_tx_info *tx_info;
716 struct ath_frame_info *fi;
718 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
721 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
722 fi = get_frame_info(bf->bf_mpdu);
724 /* do not step over block-ack window */
725 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
726 status = ATH_AGGR_BAW_CLOSED;
731 aggr_limit = ath_lookup_rate(sc, bf, tid);
735 /* do not exceed aggregation limit */
736 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
739 (aggr_limit < (al + bpad + al_delta + prev_al))) {
740 status = ATH_AGGR_LIMITED;
744 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
745 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
746 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
749 /* do not exceed subframe limit */
750 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
751 status = ATH_AGGR_LIMITED;
756 /* add padding for previous frame to aggregation length */
757 al += bpad + al_delta;
760 * Get the delimiters needed to meet the MPDU
761 * density for this node.
763 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
764 bpad = PADBYTES(al_delta) + (ndelim << 2);
767 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
769 /* link buffers of this frame to the aggregate */
771 ath_tx_addto_baw(sc, tid, fi->seqno);
772 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
773 list_move_tail(&bf->list, bf_q);
775 bf_prev->bf_next = bf;
776 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
781 } while (!list_empty(&tid->buf_q));
789 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
790 struct ath_atx_tid *tid)
793 enum ATH_AGGR_STATUS status;
794 struct ath_frame_info *fi;
795 struct list_head bf_q;
799 if (list_empty(&tid->buf_q))
802 INIT_LIST_HEAD(&bf_q);
804 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
807 * no frames picked up to be aggregated;
808 * block-ack window is not open.
810 if (list_empty(&bf_q))
813 bf = list_first_entry(&bf_q, struct ath_buf, list);
814 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
816 /* if only one frame, send as non-aggregate */
817 if (bf == bf->bf_lastbf) {
818 fi = get_frame_info(bf->bf_mpdu);
820 bf->bf_state.bf_type &= ~BUF_AGGR;
821 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
822 ath_buf_set_rate(sc, bf, fi->framelen);
823 ath_tx_txqaddbuf(sc, txq, &bf_q);
827 /* setup first desc of aggregate */
828 bf->bf_state.bf_type |= BUF_AGGR;
829 ath_buf_set_rate(sc, bf, aggr_len);
830 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
832 /* anchor last desc of aggregate */
833 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
835 ath_tx_txqaddbuf(sc, txq, &bf_q);
836 TX_STAT_INC(txq->axq_qnum, a_aggr);
838 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
839 status != ATH_AGGR_BAW_CLOSED);
842 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
845 struct ath_atx_tid *txtid;
848 an = (struct ath_node *)sta->drv_priv;
849 txtid = ATH_AN_2_TID(an, tid);
851 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
854 txtid->state |= AGGR_ADDBA_PROGRESS;
855 txtid->paused = true;
856 *ssn = txtid->seq_start = txtid->seq_next;
858 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
859 txtid->baw_head = txtid->baw_tail = 0;
864 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
866 struct ath_node *an = (struct ath_node *)sta->drv_priv;
867 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
868 struct ath_txq *txq = txtid->ac->txq;
870 if (txtid->state & AGGR_CLEANUP)
873 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
874 txtid->state &= ~AGGR_ADDBA_PROGRESS;
878 spin_lock_bh(&txq->axq_lock);
879 txtid->paused = true;
882 * If frames are still being transmitted for this TID, they will be
883 * cleaned up during tx completion. To prevent race conditions, this
884 * TID can only be reused after all in-progress subframes have been
887 if (txtid->baw_head != txtid->baw_tail)
888 txtid->state |= AGGR_CLEANUP;
890 txtid->state &= ~AGGR_ADDBA_COMPLETE;
891 spin_unlock_bh(&txq->axq_lock);
893 ath_tx_flush_tid(sc, txtid);
896 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
898 struct ath_atx_tid *txtid;
901 an = (struct ath_node *)sta->drv_priv;
903 if (sc->sc_flags & SC_OP_TXAGGR) {
904 txtid = ATH_AN_2_TID(an, tid);
906 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
907 txtid->state |= AGGR_ADDBA_COMPLETE;
908 txtid->state &= ~AGGR_ADDBA_PROGRESS;
909 ath_tx_resume_tid(sc, txtid);
913 /********************/
914 /* Queue Management */
915 /********************/
917 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
920 struct ath_atx_ac *ac, *ac_tmp;
921 struct ath_atx_tid *tid, *tid_tmp;
923 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
926 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
927 list_del(&tid->list);
929 ath_tid_drain(sc, txq, tid);
934 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
936 struct ath_hw *ah = sc->sc_ah;
937 struct ath_common *common = ath9k_hw_common(ah);
938 struct ath9k_tx_queue_info qi;
939 static const int subtype_txq_to_hwq[] = {
940 [WME_AC_BE] = ATH_TXQ_AC_BE,
941 [WME_AC_BK] = ATH_TXQ_AC_BK,
942 [WME_AC_VI] = ATH_TXQ_AC_VI,
943 [WME_AC_VO] = ATH_TXQ_AC_VO,
947 memset(&qi, 0, sizeof(qi));
948 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
949 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
950 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
951 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
952 qi.tqi_physCompBuf = 0;
955 * Enable interrupts only for EOL and DESC conditions.
956 * We mark tx descriptors to receive a DESC interrupt
957 * when a tx queue gets deep; otherwise waiting for the
958 * EOL to reap descriptors. Note that this is done to
959 * reduce interrupt load and this only defers reaping
960 * descriptors, never transmitting frames. Aside from
961 * reducing interrupts this also permits more concurrency.
962 * The only potential downside is if the tx queue backs
963 * up in which case the top half of the kernel may backup
964 * due to a lack of tx descriptors.
966 * The UAPSD queue is an exception, since we take a desc-
967 * based intr on the EOSP frames.
969 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
970 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
971 TXQ_FLAG_TXERRINT_ENABLE;
973 if (qtype == ATH9K_TX_QUEUE_UAPSD)
974 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
976 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
977 TXQ_FLAG_TXDESCINT_ENABLE;
979 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
980 if (axq_qnum == -1) {
982 * NB: don't print a message, this happens
983 * normally on parts with too few tx queues
987 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
988 ath_err(common, "qnum %u out of range, max %zu!\n",
989 axq_qnum, ARRAY_SIZE(sc->tx.txq));
990 ath9k_hw_releasetxqueue(ah, axq_qnum);
993 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
994 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
996 txq->axq_qnum = axq_qnum;
997 txq->mac80211_qnum = -1;
998 txq->axq_link = NULL;
999 INIT_LIST_HEAD(&txq->axq_q);
1000 INIT_LIST_HEAD(&txq->axq_acq);
1001 spin_lock_init(&txq->axq_lock);
1003 txq->axq_ampdu_depth = 0;
1004 txq->axq_tx_inprogress = false;
1005 sc->tx.txqsetup |= 1<<axq_qnum;
1007 txq->txq_headidx = txq->txq_tailidx = 0;
1008 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1009 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1010 INIT_LIST_HEAD(&txq->txq_fifo_pending);
1012 return &sc->tx.txq[axq_qnum];
1015 int ath_txq_update(struct ath_softc *sc, int qnum,
1016 struct ath9k_tx_queue_info *qinfo)
1018 struct ath_hw *ah = sc->sc_ah;
1020 struct ath9k_tx_queue_info qi;
1022 if (qnum == sc->beacon.beaconq) {
1024 * XXX: for beacon queue, we just save the parameter.
1025 * It will be picked up by ath_beaconq_config when
1028 sc->beacon.beacon_qi = *qinfo;
1032 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1034 ath9k_hw_get_txq_props(ah, qnum, &qi);
1035 qi.tqi_aifs = qinfo->tqi_aifs;
1036 qi.tqi_cwmin = qinfo->tqi_cwmin;
1037 qi.tqi_cwmax = qinfo->tqi_cwmax;
1038 qi.tqi_burstTime = qinfo->tqi_burstTime;
1039 qi.tqi_readyTime = qinfo->tqi_readyTime;
1041 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1042 ath_err(ath9k_hw_common(sc->sc_ah),
1043 "Unable to update hardware queue %u!\n", qnum);
1046 ath9k_hw_resettxqueue(ah, qnum);
1052 int ath_cabq_update(struct ath_softc *sc)
1054 struct ath9k_tx_queue_info qi;
1055 int qnum = sc->beacon.cabq->axq_qnum;
1057 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1059 * Ensure the readytime % is within the bounds.
1061 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1062 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1063 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1064 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1066 qi.tqi_readyTime = (sc->beacon_interval *
1067 sc->config.cabqReadytime) / 100;
1068 ath_txq_update(sc, qnum, &qi);
1073 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1075 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1076 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1080 * Drain a given TX queue (could be Beacon or Data)
1082 * This assumes output has been stopped and
1083 * we do not need to block ath_tx_tasklet.
1085 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1087 struct ath_buf *bf, *lastbf;
1088 struct list_head bf_head;
1089 struct ath_tx_status ts;
1091 memset(&ts, 0, sizeof(ts));
1092 INIT_LIST_HEAD(&bf_head);
1095 spin_lock_bh(&txq->axq_lock);
1097 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1098 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1099 txq->txq_headidx = txq->txq_tailidx = 0;
1100 spin_unlock_bh(&txq->axq_lock);
1103 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1104 struct ath_buf, list);
1107 if (list_empty(&txq->axq_q)) {
1108 txq->axq_link = NULL;
1109 spin_unlock_bh(&txq->axq_lock);
1112 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1116 list_del(&bf->list);
1117 spin_unlock_bh(&txq->axq_lock);
1119 ath_tx_return_buffer(sc, bf);
1124 lastbf = bf->bf_lastbf;
1126 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1127 list_cut_position(&bf_head,
1128 &txq->txq_fifo[txq->txq_tailidx],
1130 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1132 /* remove ath_buf's of the same mpdu from txq */
1133 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1137 if (bf_is_ampdu_not_probing(bf))
1138 txq->axq_ampdu_depth--;
1139 spin_unlock_bh(&txq->axq_lock);
1142 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1145 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1148 spin_lock_bh(&txq->axq_lock);
1149 txq->axq_tx_inprogress = false;
1150 spin_unlock_bh(&txq->axq_lock);
1152 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1153 spin_lock_bh(&txq->axq_lock);
1154 while (!list_empty(&txq->txq_fifo_pending)) {
1155 bf = list_first_entry(&txq->txq_fifo_pending,
1156 struct ath_buf, list);
1157 list_cut_position(&bf_head,
1158 &txq->txq_fifo_pending,
1159 &bf->bf_lastbf->list);
1160 spin_unlock_bh(&txq->axq_lock);
1163 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1166 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1168 spin_lock_bh(&txq->axq_lock);
1170 spin_unlock_bh(&txq->axq_lock);
1173 /* flush any pending frames if aggregation is enabled */
1174 if (sc->sc_flags & SC_OP_TXAGGR) {
1176 spin_lock_bh(&txq->axq_lock);
1177 ath_txq_drain_pending_buffers(sc, txq);
1178 spin_unlock_bh(&txq->axq_lock);
1183 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1185 struct ath_hw *ah = sc->sc_ah;
1186 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1187 struct ath_txq *txq;
1190 if (sc->sc_flags & SC_OP_INVALID)
1193 /* Stop beacon queue */
1194 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1196 /* Stop data queues */
1197 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1198 if (ATH_TXQ_SETUP(sc, i)) {
1199 txq = &sc->tx.txq[i];
1200 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1201 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1206 ath_err(common, "Failed to stop TX DMA!\n");
1208 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1209 if (!ATH_TXQ_SETUP(sc, i))
1213 * The caller will resume queues with ieee80211_wake_queues.
1214 * Mark the queue as not stopped to prevent ath_tx_complete
1215 * from waking the queue too early.
1217 txq = &sc->tx.txq[i];
1218 txq->stopped = false;
1219 ath_draintxq(sc, txq, retry_tx);
1225 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1227 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1228 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1231 /* For each axq_acq entry, for each tid, try to schedule packets
1232 * for transmit until ampdu_depth has reached min Q depth.
1234 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1236 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1237 struct ath_atx_tid *tid, *last_tid;
1239 if (list_empty(&txq->axq_acq) ||
1240 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1243 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1244 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1246 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1247 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1248 list_del(&ac->list);
1251 while (!list_empty(&ac->tid_q)) {
1252 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1254 list_del(&tid->list);
1260 ath_tx_sched_aggr(sc, txq, tid);
1263 * add tid to round-robin queue if more frames
1264 * are pending for the tid
1266 if (!list_empty(&tid->buf_q))
1267 ath_tx_queue_tid(txq, tid);
1269 if (tid == last_tid ||
1270 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1274 if (!list_empty(&ac->tid_q)) {
1277 list_add_tail(&ac->list, &txq->axq_acq);
1281 if (ac == last_ac ||
1282 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1292 * Insert a chain of ath_buf (descriptors) on a txq and
1293 * assume the descriptors are already chained together by caller.
1295 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1296 struct list_head *head)
1298 struct ath_hw *ah = sc->sc_ah;
1299 struct ath_common *common = ath9k_hw_common(ah);
1303 * Insert the frame on the outbound list and
1304 * pass it on to the hardware.
1307 if (list_empty(head))
1310 bf = list_first_entry(head, struct ath_buf, list);
1312 ath_dbg(common, ATH_DBG_QUEUE,
1313 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1315 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1316 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1317 list_splice_tail_init(head, &txq->txq_fifo_pending);
1320 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1321 ath_dbg(common, ATH_DBG_XMIT,
1322 "Initializing tx fifo %d which is non-empty\n",
1324 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1325 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1326 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1327 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1328 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1329 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1330 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1332 list_splice_tail_init(head, &txq->axq_q);
1334 if (txq->axq_link == NULL) {
1335 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1336 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1337 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1338 txq->axq_qnum, ito64(bf->bf_daddr),
1341 *txq->axq_link = bf->bf_daddr;
1342 ath_dbg(common, ATH_DBG_XMIT,
1343 "link[%u] (%p)=%llx (%p)\n",
1344 txq->axq_qnum, txq->axq_link,
1345 ito64(bf->bf_daddr), bf->bf_desc);
1347 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1349 TX_STAT_INC(txq->axq_qnum, txstart);
1350 ath9k_hw_txstart(ah, txq->axq_qnum);
1353 if (bf_is_ampdu_not_probing(bf))
1354 txq->axq_ampdu_depth++;
1357 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1358 struct ath_buf *bf, struct ath_tx_control *txctl)
1360 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1361 struct list_head bf_head;
1363 bf->bf_state.bf_type |= BUF_AMPDU;
1366 * Do not queue to h/w when any of the following conditions is true:
1367 * - there are pending frames in software queue
1368 * - the TID is currently paused for ADDBA/BAR request
1369 * - seqno is not within block-ack window
1370 * - h/w queue depth exceeds low water mark
1372 if (!list_empty(&tid->buf_q) || tid->paused ||
1373 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1374 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1376 * Add this frame to software queue for scheduling later
1379 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1380 list_add_tail(&bf->list, &tid->buf_q);
1381 ath_tx_queue_tid(txctl->txq, tid);
1385 INIT_LIST_HEAD(&bf_head);
1386 list_add(&bf->list, &bf_head);
1388 /* Add sub-frame to BAW */
1390 ath_tx_addto_baw(sc, tid, fi->seqno);
1392 /* Queue to h/w without aggregation */
1393 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1395 ath_buf_set_rate(sc, bf, fi->framelen);
1396 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1399 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1400 struct ath_atx_tid *tid,
1401 struct list_head *bf_head)
1403 struct ath_frame_info *fi;
1406 bf = list_first_entry(bf_head, struct ath_buf, list);
1407 bf->bf_state.bf_type &= ~BUF_AMPDU;
1409 /* update starting sequence number for subsequent ADDBA request */
1411 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1414 fi = get_frame_info(bf->bf_mpdu);
1415 ath_buf_set_rate(sc, bf, fi->framelen);
1416 ath_tx_txqaddbuf(sc, txq, bf_head);
1417 TX_STAT_INC(txq->axq_qnum, queued);
1420 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1422 struct ieee80211_hdr *hdr;
1423 enum ath9k_pkt_type htype;
1426 hdr = (struct ieee80211_hdr *)skb->data;
1427 fc = hdr->frame_control;
1429 if (ieee80211_is_beacon(fc))
1430 htype = ATH9K_PKT_TYPE_BEACON;
1431 else if (ieee80211_is_probe_resp(fc))
1432 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1433 else if (ieee80211_is_atim(fc))
1434 htype = ATH9K_PKT_TYPE_ATIM;
1435 else if (ieee80211_is_pspoll(fc))
1436 htype = ATH9K_PKT_TYPE_PSPOLL;
1438 htype = ATH9K_PKT_TYPE_NORMAL;
1443 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1446 struct ath_wiphy *aphy = hw->priv;
1447 struct ath_softc *sc = aphy->sc;
1448 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1449 struct ieee80211_sta *sta = tx_info->control.sta;
1450 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1451 struct ieee80211_hdr *hdr;
1452 struct ath_frame_info *fi = get_frame_info(skb);
1453 struct ath_node *an;
1454 struct ath_atx_tid *tid;
1455 enum ath9k_key_type keytype;
1459 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1461 hdr = (struct ieee80211_hdr *)skb->data;
1462 if (sta && ieee80211_is_data_qos(hdr->frame_control) &&
1463 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1465 an = (struct ath_node *) sta->drv_priv;
1466 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1469 * Override seqno set by upper layer with the one
1470 * in tx aggregation state.
1472 tid = ATH_AN_2_TID(an, tidno);
1473 seqno = tid->seq_next;
1474 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1475 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1478 memset(fi, 0, sizeof(*fi));
1480 fi->keyix = hw_key->hw_key_idx;
1482 fi->keyix = ATH9K_TXKEYIX_INVALID;
1483 fi->keytype = keytype;
1484 fi->framelen = framelen;
1488 static int setup_tx_flags(struct sk_buff *skb)
1490 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1493 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1494 flags |= ATH9K_TXDESC_INTREQ;
1496 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1497 flags |= ATH9K_TXDESC_NOACK;
1499 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1500 flags |= ATH9K_TXDESC_LDPC;
1507 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1508 * width - 0 for 20 MHz, 1 for 40 MHz
1509 * half_gi - to use 4us v/s 3.6 us for symbol time
1511 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1512 int width, int half_gi, bool shortPreamble)
1514 u32 nbits, nsymbits, duration, nsymbols;
1517 /* find number of symbols: PLCP + data */
1518 streams = HT_RC_2_STREAMS(rix);
1519 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1520 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1521 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1524 duration = SYMBOL_TIME(nsymbols);
1526 duration = SYMBOL_TIME_HALFGI(nsymbols);
1528 /* addup duration for legacy/ht training and signal fields */
1529 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1534 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1536 struct ath_hw *ah = sc->sc_ah;
1537 struct ath9k_channel *curchan = ah->curchan;
1538 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1539 (curchan->channelFlags & CHANNEL_5GHZ) &&
1540 (chainmask == 0x7) && (rate < 0x90))
1546 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1548 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1549 struct ath9k_11n_rate_series series[4];
1550 struct sk_buff *skb;
1551 struct ieee80211_tx_info *tx_info;
1552 struct ieee80211_tx_rate *rates;
1553 const struct ieee80211_rate *rate;
1554 struct ieee80211_hdr *hdr;
1556 u8 rix = 0, ctsrate = 0;
1559 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1562 tx_info = IEEE80211_SKB_CB(skb);
1563 rates = tx_info->control.rates;
1564 hdr = (struct ieee80211_hdr *)skb->data;
1565 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1568 * We check if Short Preamble is needed for the CTS rate by
1569 * checking the BSS's global flag.
1570 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1572 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1573 ctsrate = rate->hw_value;
1574 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1575 ctsrate |= rate->hw_value_short;
1577 for (i = 0; i < 4; i++) {
1578 bool is_40, is_sgi, is_sp;
1581 if (!rates[i].count || (rates[i].idx < 0))
1585 series[i].Tries = rates[i].count;
1587 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1588 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1589 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1590 flags |= ATH9K_TXDESC_RTSENA;
1591 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1592 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1593 flags |= ATH9K_TXDESC_CTSENA;
1596 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1597 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1598 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1599 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1601 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1602 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1603 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1605 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1607 series[i].Rate = rix | 0x80;
1608 series[i].ChSel = ath_txchainmask_reduction(sc,
1609 common->tx_chainmask, series[i].Rate);
1610 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1611 is_40, is_sgi, is_sp);
1612 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1613 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1618 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1619 !(rate->flags & IEEE80211_RATE_ERP_G))
1620 phy = WLAN_RC_PHY_CCK;
1622 phy = WLAN_RC_PHY_OFDM;
1624 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1625 series[i].Rate = rate->hw_value;
1626 if (rate->hw_value_short) {
1627 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1628 series[i].Rate |= rate->hw_value_short;
1633 if (bf->bf_state.bfs_paprd)
1634 series[i].ChSel = common->tx_chainmask;
1636 series[i].ChSel = ath_txchainmask_reduction(sc,
1637 common->tx_chainmask, series[i].Rate);
1639 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1640 phy, rate->bitrate * 100, len, rix, is_sp);
1643 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1644 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1645 flags &= ~ATH9K_TXDESC_RTSENA;
1647 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1648 if (flags & ATH9K_TXDESC_RTSENA)
1649 flags &= ~ATH9K_TXDESC_CTSENA;
1651 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1652 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1653 bf->bf_lastbf->bf_desc,
1654 !is_pspoll, ctsrate,
1655 0, series, 4, flags);
1657 if (sc->config.ath_aggr_prot && flags)
1658 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1661 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1662 struct ath_txq *txq,
1663 struct sk_buff *skb)
1665 struct ath_wiphy *aphy = hw->priv;
1666 struct ath_softc *sc = aphy->sc;
1667 struct ath_hw *ah = sc->sc_ah;
1668 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1669 struct ath_frame_info *fi = get_frame_info(skb);
1671 struct ath_desc *ds;
1674 bf = ath_tx_get_buffer(sc);
1676 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1680 ATH_TXBUF_RESET(bf);
1682 bf->bf_flags = setup_tx_flags(skb);
1685 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1686 skb->len, DMA_TO_DEVICE);
1687 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1689 bf->bf_buf_addr = 0;
1690 ath_err(ath9k_hw_common(sc->sc_ah),
1691 "dma_mapping_error() on TX\n");
1692 ath_tx_return_buffer(sc, bf);
1696 frm_type = get_hw_packet_type(skb);
1699 ath9k_hw_set_desc_link(ah, ds, 0);
1701 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1702 fi->keyix, fi->keytype, bf->bf_flags);
1704 ath9k_hw_filltxdesc(ah, ds,
1705 skb->len, /* segment length */
1706 true, /* first segment */
1707 true, /* last segment */
1708 ds, /* first descriptor */
1716 /* FIXME: tx power */
1717 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1718 struct ath_tx_control *txctl)
1720 struct sk_buff *skb = bf->bf_mpdu;
1721 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1722 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1723 struct list_head bf_head;
1724 struct ath_atx_tid *tid = NULL;
1727 spin_lock_bh(&txctl->txq->axq_lock);
1729 if (ieee80211_is_data_qos(hdr->frame_control) && txctl->an) {
1730 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1731 IEEE80211_QOS_CTL_TID_MASK;
1732 tid = ATH_AN_2_TID(txctl->an, tidno);
1734 WARN_ON(tid->ac->txq != txctl->txq);
1737 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1739 * Try aggregation if it's a unicast data frame
1740 * and the destination is HT capable.
1742 ath_tx_send_ampdu(sc, tid, bf, txctl);
1744 INIT_LIST_HEAD(&bf_head);
1745 list_add_tail(&bf->list, &bf_head);
1747 bf->bf_state.bfs_ftype = txctl->frame_type;
1748 bf->bf_state.bfs_paprd = txctl->paprd;
1750 if (bf->bf_state.bfs_paprd)
1751 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1752 bf->bf_state.bfs_paprd);
1754 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1757 spin_unlock_bh(&txctl->txq->axq_lock);
1760 /* Upon failure caller should free skb */
1761 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1762 struct ath_tx_control *txctl)
1764 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1765 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1766 struct ieee80211_sta *sta = info->control.sta;
1767 struct ath_wiphy *aphy = hw->priv;
1768 struct ath_softc *sc = aphy->sc;
1769 struct ath_txq *txq = txctl->txq;
1771 int padpos, padsize;
1772 int frmlen = skb->len + FCS_LEN;
1775 /* NOTE: sta can be NULL according to net/mac80211.h */
1777 txctl->an = (struct ath_node *)sta->drv_priv;
1779 if (info->control.hw_key)
1780 frmlen += info->control.hw_key->icv_len;
1783 * As a temporary workaround, assign seq# here; this will likely need
1784 * to be cleaned up to work better with Beacon transmission and virtual
1787 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1788 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1789 sc->tx.seq_no += 0x10;
1790 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1791 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1794 /* Add the padding after the header if this is not already done */
1795 padpos = ath9k_cmn_padpos(hdr->frame_control);
1796 padsize = padpos & 3;
1797 if (padsize && skb->len > padpos) {
1798 if (skb_headroom(skb) < padsize)
1801 skb_push(skb, padsize);
1802 memmove(skb->data, skb->data + padsize, padpos);
1805 setup_frame_info(hw, skb, frmlen);
1808 * At this point, the vif, hw_key and sta pointers in the tx control
1809 * info are no longer valid (overwritten by the ath_frame_info data.
1812 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1816 q = skb_get_queue_mapping(skb);
1817 spin_lock_bh(&txq->axq_lock);
1818 if (txq == sc->tx.txq_map[q] &&
1819 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1820 ieee80211_stop_queue(sc->hw, q);
1823 spin_unlock_bh(&txq->axq_lock);
1825 ath_tx_start_dma(sc, bf, txctl);
1834 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1835 int tx_flags, int ftype, struct ath_txq *txq)
1837 struct ieee80211_hw *hw = sc->hw;
1838 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1839 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1840 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1841 int q, padpos, padsize;
1843 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1845 if (tx_flags & ATH_TX_BAR)
1846 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1848 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1849 /* Frame was ACKed */
1850 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1853 padpos = ath9k_cmn_padpos(hdr->frame_control);
1854 padsize = padpos & 3;
1855 if (padsize && skb->len>padpos+padsize) {
1857 * Remove MAC header padding before giving the frame back to
1860 memmove(skb->data + padsize, skb->data, padpos);
1861 skb_pull(skb, padsize);
1864 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1865 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1866 ath_dbg(common, ATH_DBG_PS,
1867 "Going back to sleep after having received TX status (0x%lx)\n",
1868 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1870 PS_WAIT_FOR_PSPOLL_DATA |
1871 PS_WAIT_FOR_TX_ACK));
1874 q = skb_get_queue_mapping(skb);
1875 if (txq == sc->tx.txq_map[q]) {
1876 spin_lock_bh(&txq->axq_lock);
1877 if (WARN_ON(--txq->pending_frames < 0))
1878 txq->pending_frames = 0;
1880 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1881 ieee80211_wake_queue(sc->hw, q);
1884 spin_unlock_bh(&txq->axq_lock);
1887 ieee80211_tx_status(hw, skb);
1890 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1891 struct ath_txq *txq, struct list_head *bf_q,
1892 struct ath_tx_status *ts, int txok, int sendbar)
1894 struct sk_buff *skb = bf->bf_mpdu;
1895 unsigned long flags;
1899 tx_flags = ATH_TX_BAR;
1902 tx_flags |= ATH_TX_ERROR;
1904 if (bf_isxretried(bf))
1905 tx_flags |= ATH_TX_XRETRY;
1908 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1909 bf->bf_buf_addr = 0;
1911 if (bf->bf_state.bfs_paprd) {
1912 if (!sc->paprd_pending)
1913 dev_kfree_skb_any(skb);
1915 complete(&sc->paprd_complete);
1917 ath_debug_stat_tx(sc, bf, ts);
1918 ath_tx_complete(sc, skb, tx_flags,
1919 bf->bf_state.bfs_ftype, txq);
1921 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1922 * accidentally reference it later.
1927 * Return the list of ath_buf of this mpdu to free queue
1929 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1930 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1931 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1934 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1935 struct ath_tx_status *ts, int nframes, int nbad,
1936 int txok, bool update_rc)
1938 struct sk_buff *skb = bf->bf_mpdu;
1939 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1940 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1941 struct ieee80211_hw *hw = sc->hw;
1942 struct ath_hw *ah = sc->sc_ah;
1946 tx_info->status.ack_signal = ts->ts_rssi;
1948 tx_rateindex = ts->ts_rateindex;
1949 WARN_ON(tx_rateindex >= hw->max_rates);
1951 if (ts->ts_status & ATH9K_TXERR_FILT)
1952 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1953 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1954 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1956 BUG_ON(nbad > nframes);
1958 tx_info->status.ampdu_len = nframes;
1959 tx_info->status.ampdu_ack_len = nframes - nbad;
1962 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1963 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1965 * If an underrun error is seen assume it as an excessive
1966 * retry only if max frame trigger level has been reached
1967 * (2 KB for single stream, and 4 KB for dual stream).
1968 * Adjust the long retry as if the frame was tried
1969 * hw->max_rate_tries times to affect how rate control updates
1970 * PER for the failed rate.
1971 * In case of congestion on the bus penalizing this type of
1972 * underruns should help hardware actually transmit new frames
1973 * successfully by eventually preferring slower rates.
1974 * This itself should also alleviate congestion on the bus.
1976 if (ieee80211_is_data(hdr->frame_control) &&
1977 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1978 ATH9K_TX_DELIM_UNDERRUN)) &&
1979 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
1980 tx_info->status.rates[tx_rateindex].count =
1984 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1985 tx_info->status.rates[i].count = 0;
1986 tx_info->status.rates[i].idx = -1;
1989 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
1992 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1994 struct ath_hw *ah = sc->sc_ah;
1995 struct ath_common *common = ath9k_hw_common(ah);
1996 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1997 struct list_head bf_head;
1998 struct ath_desc *ds;
1999 struct ath_tx_status ts;
2003 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2004 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2008 spin_lock_bh(&txq->axq_lock);
2009 if (list_empty(&txq->axq_q)) {
2010 txq->axq_link = NULL;
2011 if (sc->sc_flags & SC_OP_TXAGGR)
2012 ath_txq_schedule(sc, txq);
2013 spin_unlock_bh(&txq->axq_lock);
2016 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2019 * There is a race condition that a BH gets scheduled
2020 * after sw writes TxE and before hw re-load the last
2021 * descriptor to get the newly chained one.
2022 * Software must keep the last DONE descriptor as a
2023 * holding descriptor - software does so by marking
2024 * it with the STALE flag.
2029 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2030 spin_unlock_bh(&txq->axq_lock);
2033 bf = list_entry(bf_held->list.next,
2034 struct ath_buf, list);
2038 lastbf = bf->bf_lastbf;
2039 ds = lastbf->bf_desc;
2041 memset(&ts, 0, sizeof(ts));
2042 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2043 if (status == -EINPROGRESS) {
2044 spin_unlock_bh(&txq->axq_lock);
2047 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2050 * Remove ath_buf's of the same transmit unit from txq,
2051 * however leave the last descriptor back as the holding
2052 * descriptor for hw.
2054 lastbf->bf_stale = true;
2055 INIT_LIST_HEAD(&bf_head);
2056 if (!list_is_singular(&lastbf->list))
2057 list_cut_position(&bf_head,
2058 &txq->axq_q, lastbf->list.prev);
2061 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2062 txq->axq_tx_inprogress = false;
2064 list_del(&bf_held->list);
2066 if (bf_is_ampdu_not_probing(bf))
2067 txq->axq_ampdu_depth--;
2068 spin_unlock_bh(&txq->axq_lock);
2071 ath_tx_return_buffer(sc, bf_held);
2073 if (!bf_isampdu(bf)) {
2075 * This frame is sent out as a single frame.
2076 * Use hardware retry status for this frame.
2078 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2079 bf->bf_state.bf_type |= BUF_XRETRY;
2080 ath_tx_rc_status(sc, bf, &ts, 1, txok ? 0 : 1, txok, true);
2084 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
2087 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2089 spin_lock_bh(&txq->axq_lock);
2091 if (sc->sc_flags & SC_OP_TXAGGR)
2092 ath_txq_schedule(sc, txq);
2093 spin_unlock_bh(&txq->axq_lock);
2097 static void ath_tx_complete_poll_work(struct work_struct *work)
2099 struct ath_softc *sc = container_of(work, struct ath_softc,
2100 tx_complete_work.work);
2101 struct ath_txq *txq;
2103 bool needreset = false;
2104 #ifdef CONFIG_ATH9K_DEBUGFS
2105 sc->tx_complete_poll_work_seen++;
2108 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2109 if (ATH_TXQ_SETUP(sc, i)) {
2110 txq = &sc->tx.txq[i];
2111 spin_lock_bh(&txq->axq_lock);
2112 if (txq->axq_depth) {
2113 if (txq->axq_tx_inprogress) {
2115 spin_unlock_bh(&txq->axq_lock);
2118 txq->axq_tx_inprogress = true;
2121 /* If the queue has pending buffers, then it
2122 * should be doing tx work (and have axq_depth).
2123 * Shouldn't get to this state I think..but
2126 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) &&
2127 (txq->pending_frames > 0 ||
2128 !list_empty(&txq->axq_acq) ||
2130 ath_err(ath9k_hw_common(sc->sc_ah),
2131 "txq: %p axq_qnum: %u,"
2132 " mac80211_qnum: %i"
2134 " pending frames: %i"
2135 " axq_acq empty: %i"
2137 " axq_depth: 0 Attempting to"
2138 " restart tx logic.\n",
2142 txq->pending_frames,
2143 list_empty(&txq->axq_acq),
2145 ath_txq_schedule(sc, txq);
2148 spin_unlock_bh(&txq->axq_lock);
2152 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2153 "tx hung, resetting the chip\n");
2154 ath9k_ps_wakeup(sc);
2155 ath_reset(sc, true);
2156 ath9k_ps_restore(sc);
2159 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2160 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2165 void ath_tx_tasklet(struct ath_softc *sc)
2168 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2170 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2172 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2173 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2174 ath_tx_processq(sc, &sc->tx.txq[i]);
2178 void ath_tx_edma_tasklet(struct ath_softc *sc)
2180 struct ath_tx_status txs;
2181 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2182 struct ath_hw *ah = sc->sc_ah;
2183 struct ath_txq *txq;
2184 struct ath_buf *bf, *lastbf;
2185 struct list_head bf_head;
2190 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2191 if (status == -EINPROGRESS)
2193 if (status == -EIO) {
2194 ath_dbg(common, ATH_DBG_XMIT,
2195 "Error processing tx status\n");
2199 /* Skip beacon completions */
2200 if (txs.qid == sc->beacon.beaconq)
2203 txq = &sc->tx.txq[txs.qid];
2205 spin_lock_bh(&txq->axq_lock);
2206 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2207 spin_unlock_bh(&txq->axq_lock);
2211 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2212 struct ath_buf, list);
2213 lastbf = bf->bf_lastbf;
2215 INIT_LIST_HEAD(&bf_head);
2216 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2218 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2220 txq->axq_tx_inprogress = false;
2221 if (bf_is_ampdu_not_probing(bf))
2222 txq->axq_ampdu_depth--;
2223 spin_unlock_bh(&txq->axq_lock);
2225 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2227 if (!bf_isampdu(bf)) {
2228 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2229 bf->bf_state.bf_type |= BUF_XRETRY;
2230 ath_tx_rc_status(sc, bf, &txs, 1, txok ? 0 : 1, txok, true);
2234 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
2237 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2240 spin_lock_bh(&txq->axq_lock);
2242 if (!list_empty(&txq->txq_fifo_pending)) {
2243 INIT_LIST_HEAD(&bf_head);
2244 bf = list_first_entry(&txq->txq_fifo_pending,
2245 struct ath_buf, list);
2246 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2247 &bf->bf_lastbf->list);
2248 ath_tx_txqaddbuf(sc, txq, &bf_head);
2249 } else if (sc->sc_flags & SC_OP_TXAGGR)
2250 ath_txq_schedule(sc, txq);
2251 spin_unlock_bh(&txq->axq_lock);
2259 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2261 struct ath_descdma *dd = &sc->txsdma;
2262 u8 txs_len = sc->sc_ah->caps.txs_len;
2264 dd->dd_desc_len = size * txs_len;
2265 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2266 &dd->dd_desc_paddr, GFP_KERNEL);
2273 static int ath_tx_edma_init(struct ath_softc *sc)
2277 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2279 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2280 sc->txsdma.dd_desc_paddr,
2281 ATH_TXSTATUS_RING_SIZE);
2286 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2288 struct ath_descdma *dd = &sc->txsdma;
2290 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2294 int ath_tx_init(struct ath_softc *sc, int nbufs)
2296 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2299 spin_lock_init(&sc->tx.txbuflock);
2301 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2305 "Failed to allocate tx descriptors: %d\n", error);
2309 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2310 "beacon", ATH_BCBUF, 1, 1);
2313 "Failed to allocate beacon descriptors: %d\n", error);
2317 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2319 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2320 error = ath_tx_edma_init(sc);
2332 void ath_tx_cleanup(struct ath_softc *sc)
2334 if (sc->beacon.bdma.dd_desc_len != 0)
2335 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2337 if (sc->tx.txdma.dd_desc_len != 0)
2338 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2340 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2341 ath_tx_edma_cleanup(sc);
2344 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2346 struct ath_atx_tid *tid;
2347 struct ath_atx_ac *ac;
2350 for (tidno = 0, tid = &an->tid[tidno];
2351 tidno < WME_NUM_TID;
2355 tid->seq_start = tid->seq_next = 0;
2356 tid->baw_size = WME_MAX_BA;
2357 tid->baw_head = tid->baw_tail = 0;
2359 tid->paused = false;
2360 tid->state &= ~AGGR_CLEANUP;
2361 INIT_LIST_HEAD(&tid->buf_q);
2362 acno = TID_TO_WME_AC(tidno);
2363 tid->ac = &an->ac[acno];
2364 tid->state &= ~AGGR_ADDBA_COMPLETE;
2365 tid->state &= ~AGGR_ADDBA_PROGRESS;
2368 for (acno = 0, ac = &an->ac[acno];
2369 acno < WME_NUM_AC; acno++, ac++) {
2371 ac->txq = sc->tx.txq_map[acno];
2372 INIT_LIST_HEAD(&ac->tid_q);
2376 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2378 struct ath_atx_ac *ac;
2379 struct ath_atx_tid *tid;
2380 struct ath_txq *txq;
2383 for (tidno = 0, tid = &an->tid[tidno];
2384 tidno < WME_NUM_TID; tidno++, tid++) {
2389 spin_lock_bh(&txq->axq_lock);
2392 list_del(&tid->list);
2397 list_del(&ac->list);
2398 tid->ac->sched = false;
2401 ath_tid_drain(sc, txq, tid);
2402 tid->state &= ~AGGR_ADDBA_COMPLETE;
2403 tid->state &= ~AGGR_CLEANUP;
2405 spin_unlock_bh(&txq->axq_lock);