drivers/net/wireless/ath/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 static char *dev_info = "ath9k";
  21
  22 MODULE_AUTHOR("Atheros Communications");
  23 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  24 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  25 MODULE_LICENSE("Dual BSD/GPL");
  26
  27 static int modparam_nohwcrypt;
  28 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  30
  31 /* We use the hw_value as an index into our private channel structure */
  32
  33 #define CHAN2G(_freq, _idx)  { \
  34         .center_freq = (_freq), \
  35         .hw_value = (_idx), \
  36         .max_power = 20, \
  37 }
  38
  39 #define CHAN5G(_freq, _idx) { \
  40         .band = IEEE80211_BAND_5GHZ, \
  41         .center_freq = (_freq), \
  42         .hw_value = (_idx), \
  43         .max_power = 20, \
  44 }
  45
  46 /* Some 2 GHz radios are actually tunable on 2312-2732
  47  * on 5 MHz steps, we support the channels which we know
  48  * we have calibration data for all cards though to make
  49  * this static */
  50 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  51         CHAN2G(2412, 0), /* Channel 1 */
  52         CHAN2G(2417, 1), /* Channel 2 */
  53         CHAN2G(2422, 2), /* Channel 3 */
  54         CHAN2G(2427, 3), /* Channel 4 */
  55         CHAN2G(2432, 4), /* Channel 5 */
  56         CHAN2G(2437, 5), /* Channel 6 */
  57         CHAN2G(2442, 6), /* Channel 7 */
  58         CHAN2G(2447, 7), /* Channel 8 */
  59         CHAN2G(2452, 8), /* Channel 9 */
  60         CHAN2G(2457, 9), /* Channel 10 */
  61         CHAN2G(2462, 10), /* Channel 11 */
  62         CHAN2G(2467, 11), /* Channel 12 */
  63         CHAN2G(2472, 12), /* Channel 13 */
  64         CHAN2G(2484, 13), /* Channel 14 */
  65 };
  66
  67 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  68  * on 5 MHz steps, we support the channels which we know
  69  * we have calibration data for all cards though to make
  70  * this static */
  71 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  72         /* _We_ call this UNII 1 */
  73         CHAN5G(5180, 14), /* Channel 36 */
  74         CHAN5G(5200, 15), /* Channel 40 */
  75         CHAN5G(5220, 16), /* Channel 44 */
  76         CHAN5G(5240, 17), /* Channel 48 */
  77         /* _We_ call this UNII 2 */
  78         CHAN5G(5260, 18), /* Channel 52 */
  79         CHAN5G(5280, 19), /* Channel 56 */
  80         CHAN5G(5300, 20), /* Channel 60 */
  81         CHAN5G(5320, 21), /* Channel 64 */
  82         /* _We_ call this "Middle band" */
  83         CHAN5G(5500, 22), /* Channel 100 */
  84         CHAN5G(5520, 23), /* Channel 104 */
  85         CHAN5G(5540, 24), /* Channel 108 */
  86         CHAN5G(5560, 25), /* Channel 112 */
  87         CHAN5G(5580, 26), /* Channel 116 */
  88         CHAN5G(5600, 27), /* Channel 120 */
  89         CHAN5G(5620, 28), /* Channel 124 */
  90         CHAN5G(5640, 29), /* Channel 128 */
  91         CHAN5G(5660, 30), /* Channel 132 */
  92         CHAN5G(5680, 31), /* Channel 136 */
  93         CHAN5G(5700, 32), /* Channel 140 */
  94         /* _We_ call this UNII 3 */
  95         CHAN5G(5745, 33), /* Channel 149 */
  96         CHAN5G(5765, 34), /* Channel 153 */
  97         CHAN5G(5785, 35), /* Channel 157 */
  98         CHAN5G(5805, 36), /* Channel 161 */
  99         CHAN5G(5825, 37), /* Channel 165 */
 100 };
 101
 102 static void ath_cache_conf_rate(struct ath_softc *sc,
 103                                 struct ieee80211_conf *conf)
 104 {
 105         switch (conf->channel->band) {
 106         case IEEE80211_BAND_2GHZ:
 107                 if (conf_is_ht20(conf))
 108                         sc->cur_rate_table =
 109                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 110                 else if (conf_is_ht40_minus(conf))
 111                         sc->cur_rate_table =
 112                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 113                 else if (conf_is_ht40_plus(conf))
 114                         sc->cur_rate_table =
 115                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 116                 else
 117                         sc->cur_rate_table =
 118                           sc->hw_rate_table[ATH9K_MODE_11G];
 119                 break;
 120         case IEEE80211_BAND_5GHZ:
 121                 if (conf_is_ht20(conf))
 122                         sc->cur_rate_table =
 123                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 124                 else if (conf_is_ht40_minus(conf))
 125                         sc->cur_rate_table =
 126                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 127                 else if (conf_is_ht40_plus(conf))
 128                         sc->cur_rate_table =
 129                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 130                 else
 131                         sc->cur_rate_table =
 132                           sc->hw_rate_table[ATH9K_MODE_11A];
 133                 break;
 134         default:
 135                 BUG_ON(1);
 136                 break;
 137         }
 138 }
 139
 140 static void ath_update_txpow(struct ath_softc *sc)
 141 {
 142         struct ath_hw *ah = sc->sc_ah;
 143         u32 txpow;
 144
 145         if (sc->curtxpow != sc->config.txpowlimit) {
 146                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 147                 /* read back in case value is clamped */
 148                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 149                 sc->curtxpow = txpow;
 150         }
 151 }
 152
 153 static u8 parse_mpdudensity(u8 mpdudensity)
 154 {
 155         /*
 156          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 157          *   0 for no restriction
 158          *   1 for 1/4 us
 159          *   2 for 1/2 us
 160          *   3 for 1 us
 161          *   4 for 2 us
 162          *   5 for 4 us
 163          *   6 for 8 us
 164          *   7 for 16 us
 165          */
 166         switch (mpdudensity) {
 167         case 0:
 168                 return 0;
 169         case 1:
 170         case 2:
 171         case 3:
 172                 /* Our lower layer calculations limit our precision to
 173                    1 microsecond */
 174                 return 1;
 175         case 4:
 176                 return 2;
 177         case 5:
 178                 return 4;
 179         case 6:
 180                 return 8;
 181         case 7:
 182                 return 16;
 183         default:
 184                 return 0;
 185         }
 186 }
 187
 188 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 189 {
 190         const struct ath_rate_table *rate_table = NULL;
 191         struct ieee80211_supported_band *sband;
 192         struct ieee80211_rate *rate;
 193         int i, maxrates;
 194
 195         switch (band) {
 196         case IEEE80211_BAND_2GHZ:
 197                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 198                 break;
 199         case IEEE80211_BAND_5GHZ:
 200                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 201                 break;
 202         default:
 203                 break;
 204         }
 205
 206         if (rate_table == NULL)
 207                 return;
 208
 209         sband = &sc->sbands[band];
 210         rate = sc->rates[band];
 211
 212         if (rate_table->rate_cnt > ATH_RATE_MAX)
 213                 maxrates = ATH_RATE_MAX;
 214         else
 215                 maxrates = rate_table->rate_cnt;
 216
 217         for (i = 0; i < maxrates; i++) {
 218                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 219                 rate[i].hw_value = rate_table->info[i].ratecode;
 220                 if (rate_table->info[i].short_preamble) {
 221                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 222                                 rate_table->info[i].short_preamble;
 223                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 224                 }
 225                 sband->n_bitrates++;
 226
 227                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 228                         rate[i].bitrate / 10, rate[i].hw_value);
 229         }
 230 }
 231
 232 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
 233                                                 struct ieee80211_hw *hw)
 234 {
 235         struct ieee80211_channel *curchan = hw->conf.channel;
 236         struct ath9k_channel *channel;
 237         u8 chan_idx;
 238
 239         chan_idx = curchan->hw_value;
 240         channel = &sc->sc_ah->channels[chan_idx];
 241         ath9k_update_ichannel(sc, hw, channel);
 242         return channel;
 243 }
 244
 245 /*
 246  * Set/change channels.  If the channel is really being changed, it's done
 247  * by reseting the chip.  To accomplish this we must first cleanup any pending
 248  * DMA, then restart stuff.
 249 */
 250 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 251                     struct ath9k_channel *hchan)
 252 {
 253         struct ath_hw *ah = sc->sc_ah;
 254         bool fastcc = true, stopped;
 255         struct ieee80211_channel *channel = hw->conf.channel;
 256         int r;
 257
 258         if (sc->sc_flags & SC_OP_INVALID)
 259                 return -EIO;
 260
 261         ath9k_ps_wakeup(sc);
 262
 263         /*
 264          * This is only performed if the channel settings have
 265          * actually changed.
 266          *
 267          * To switch channels clear any pending DMA operations;
 268          * wait long enough for the RX fifo to drain, reset the
 269          * hardware at the new frequency, and then re-enable
 270          * the relevant bits of the h/w.
 271          */
 272         ath9k_hw_set_interrupts(ah, 0);
 273         ath_drain_all_txq(sc, false);
 274         stopped = ath_stoprecv(sc);
 275
 276         /* XXX: do not flush receive queue here. We don't want
 277          * to flush data frames already in queue because of
 278          * changing channel. */
 279
 280         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 281                 fastcc = false;
 282
 283         DPRINTF(sc, ATH_DBG_CONFIG,
 284                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 285                 sc->sc_ah->curchan->channel,
 286                 channel->center_freq, sc->tx_chan_width);
 287
 288         spin_lock_bh(&sc->sc_resetlock);
 289
 290         r = ath9k_hw_reset(ah, hchan, fastcc);
 291         if (r) {
 292                 DPRINTF(sc, ATH_DBG_FATAL,
 293                         "Unable to reset channel (%u Mhz) "
 294                         "reset status %d\n",
 295                         channel->center_freq, r);
 296                 spin_unlock_bh(&sc->sc_resetlock);
 297                 goto ps_restore;
 298         }
 299         spin_unlock_bh(&sc->sc_resetlock);
 300
 301         sc->sc_flags &= ~SC_OP_FULL_RESET;
 302
 303         if (ath_startrecv(sc) != 0) {
 304                 DPRINTF(sc, ATH_DBG_FATAL,
 305                         "Unable to restart recv logic\n");
 306                 r = -EIO;
 307                 goto ps_restore;
 308         }
 309
 310         ath_cache_conf_rate(sc, &hw->conf);
 311         ath_update_txpow(sc);
 312         ath9k_hw_set_interrupts(ah, sc->imask);
 313
 314  ps_restore:
 315         ath9k_ps_restore(sc);
 316         return r;
 317 }
 318
 319 /*
 320  *  This routine performs the periodic noise floor calibration function
 321  *  that is used to adjust and optimize the chip performance.  This
 322  *  takes environmental changes (location, temperature) into account.
 323  *  When the task is complete, it reschedules itself depending on the
 324  *  appropriate interval that was calculated.
 325  */
 326 static void ath_ani_calibrate(unsigned long data)
 327 {
 328         struct ath_softc *sc = (struct ath_softc *)data;
 329         struct ath_hw *ah = sc->sc_ah;
 330         bool longcal = false;
 331         bool shortcal = false;
 332         bool aniflag = false;
 333         unsigned int timestamp = jiffies_to_msecs(jiffies);
 334         u32 cal_interval, short_cal_interval;
 335
 336         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 337                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 338
 339         /*
 340         * don't calibrate when we're scanning.
 341         * we are most likely not on our home channel.
 342         */
 343         spin_lock(&sc->ani_lock);
 344         if (sc->sc_flags & SC_OP_SCANNING)
 345                 goto set_timer;
 346
 347         /* Only calibrate if awake */
 348         if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
 349                 goto set_timer;
 350
 351         ath9k_ps_wakeup(sc);
 352
 353         /* Long calibration runs independently of short calibration. */
 354         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 355                 longcal = true;
 356                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 357                 sc->ani.longcal_timer = timestamp;
 358         }
 359
 360         /* Short calibration applies only while caldone is false */
 361         if (!sc->ani.caldone) {
 362                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 363                         shortcal = true;
 364                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 365                         sc->ani.shortcal_timer = timestamp;
 366                         sc->ani.resetcal_timer = timestamp;
 367                 }
 368         } else {
 369                 if ((timestamp - sc->ani.resetcal_timer) >=
 370                     ATH_RESTART_CALINTERVAL) {
 371                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 372                         if (sc->ani.caldone)
 373                                 sc->ani.resetcal_timer = timestamp;
 374                 }
 375         }
 376
 377         /* Verify whether we must check ANI */
 378         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 379                 aniflag = true;
 380                 sc->ani.checkani_timer = timestamp;
 381         }
 382
 383         /* Skip all processing if there's nothing to do. */
 384         if (longcal || shortcal || aniflag) {
 385                 /* Call ANI routine if necessary */
 386                 if (aniflag)
 387                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 388
 389                 /* Perform calibration if necessary */
 390                 if (longcal || shortcal) {
 391                         sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
 392                                                      sc->rx_chainmask, longcal);
 393
 394                         if (longcal)
 395                                 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
 396                                                                      ah->curchan);
 397
 398                         DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
 399                                 ah->curchan->channel, ah->curchan->channelFlags,
 400                                 sc->ani.noise_floor);
 401                 }
 402         }
 403
 404         ath9k_ps_restore(sc);
 405
 406 set_timer:
 407         spin_unlock(&sc->ani_lock);
 408         /*
 409         * Set timer interval based on previous results.
 410         * The interval must be the shortest necessary to satisfy ANI,
 411         * short calibration and long calibration.
 412         */
 413         cal_interval = ATH_LONG_CALINTERVAL;
 414         if (sc->sc_ah->config.enable_ani)
 415                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 416         if (!sc->ani.caldone)
 417                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 418
 419         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 420 }
 421
 422 static void ath_start_ani(struct ath_softc *sc)
 423 {
 424         unsigned long timestamp = jiffies_to_msecs(jiffies);
 425
 426         sc->ani.longcal_timer = timestamp;
 427         sc->ani.shortcal_timer = timestamp;
 428         sc->ani.checkani_timer = timestamp;
 429
 430         mod_timer(&sc->ani.timer,
 431                   jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 432 }
 433
 434 /*
 435  * Update tx/rx chainmask. For legacy association,
 436  * hard code chainmask to 1x1, for 11n association, use
 437  * the chainmask configuration, for bt coexistence, use
 438  * the chainmask configuration even in legacy mode.
 439  */
 440 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 441 {
 442         if (is_ht ||
 443             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 444                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 445                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 446         } else {
 447                 sc->tx_chainmask = 1;
 448                 sc->rx_chainmask = 1;
 449         }
 450
 451         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 452                 sc->tx_chainmask, sc->rx_chainmask);
 453 }
 454
 455 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 456 {
 457         struct ath_node *an;
 458
 459         an = (struct ath_node *)sta->drv_priv;
 460
 461         if (sc->sc_flags & SC_OP_TXAGGR) {
 462                 ath_tx_node_init(sc, an);
 463                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
 464                                      sta->ht_cap.ampdu_factor);
 465                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 466                 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
 467         }
 468 }
 469
 470 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 471 {
 472         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 473
 474         if (sc->sc_flags & SC_OP_TXAGGR)
 475                 ath_tx_node_cleanup(sc, an);
 476 }
 477
 478 static void ath9k_tasklet(unsigned long data)
 479 {
 480         struct ath_softc *sc = (struct ath_softc *)data;
 481         u32 status = sc->intrstatus;
 482
 483         ath9k_ps_wakeup(sc);
 484
 485         if (status & ATH9K_INT_FATAL) {
 486                 ath_reset(sc, false);
 487                 ath9k_ps_restore(sc);
 488                 return;
 489         }
 490
 491         if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 492                 spin_lock_bh(&sc->rx.rxflushlock);
 493                 ath_rx_tasklet(sc, 0);
 494                 spin_unlock_bh(&sc->rx.rxflushlock);
 495         }
 496
 497         if (status & ATH9K_INT_TX)
 498                 ath_tx_tasklet(sc);
 499
 500         if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
 501                 /*
 502                  * TSF sync does not look correct; remain awake to sync with
 503                  * the next Beacon.
 504                  */
 505                 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
 506                 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
 507         }
 508
 509         /* re-enable hardware interrupt */
 510         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 511         ath9k_ps_restore(sc);
 512 }
 513
 514 irqreturn_t ath_isr(int irq, void *dev)
 515 {
 516 #define SCHED_INTR (                            \
 517                 ATH9K_INT_FATAL |               \
 518                 ATH9K_INT_RXORN |               \
 519                 ATH9K_INT_RXEOL |               \
 520                 ATH9K_INT_RX |                  \
 521                 ATH9K_INT_TX |                  \
 522                 ATH9K_INT_BMISS |               \
 523                 ATH9K_INT_CST |                 \
 524                 ATH9K_INT_TSFOOR)
 525
 526         struct ath_softc *sc = dev;
 527         struct ath_hw *ah = sc->sc_ah;
 528         enum ath9k_int status;
 529         bool sched = false;
 530
 531         /*
 532          * The hardware is not ready/present, don't
 533          * touch anything. Note this can happen early
 534          * on if the IRQ is shared.
 535          */
 536         if (sc->sc_flags & SC_OP_INVALID)
 537                 return IRQ_NONE;
 538
 539
 540         /* shared irq, not for us */
 541
 542         if (!ath9k_hw_intrpend(ah))
 543                 return IRQ_NONE;
 544
 545         /*
 546          * Figure out the reason(s) for the interrupt.  Note
 547          * that the hal returns a pseudo-ISR that may include
 548          * bits we haven't explicitly enabled so we mask the
 549          * value to insure we only process bits we requested.
 550          */
 551         ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 552         status &= sc->imask;    /* discard unasked-for bits */
 553
 554         /*
 555          * If there are no status bits set, then this interrupt was not
 556          * for me (should have been caught above).
 557          */
 558         if (!status)
 559                 return IRQ_NONE;
 560
 561         /* Cache the status */
 562         sc->intrstatus = status;
 563
 564         if (status & SCHED_INTR)
 565                 sched = true;
 566
 567         /*
 568          * If a FATAL or RXORN interrupt is received, we have to reset the
 569          * chip immediately.
 570          */
 571         if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
 572                 goto chip_reset;
 573
 574         if (status & ATH9K_INT_SWBA)
 575                 tasklet_schedule(&sc->bcon_tasklet);
 576
 577         if (status & ATH9K_INT_TXURN)
 578                 ath9k_hw_updatetxtriglevel(ah, true);
 579
 580         if (status & ATH9K_INT_MIB) {
 581                 /*
 582                  * Disable interrupts until we service the MIB
 583                  * interrupt; otherwise it will continue to
 584                  * fire.
 585                  */
 586                 ath9k_hw_set_interrupts(ah, 0);
 587                 /*
 588                  * Let the hal handle the event. We assume
 589                  * it will clear whatever condition caused
 590                  * the interrupt.
 591                  */
 592                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 593                 ath9k_hw_set_interrupts(ah, sc->imask);
 594         }
 595
 596         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
 597                 if (status & ATH9K_INT_TIM_TIMER) {
 598                         /* Clear RxAbort bit so that we can
 599                          * receive frames */
 600                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 601                         ath9k_hw_setrxabort(sc->sc_ah, 0);
 602                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 603                 }
 604
 605 chip_reset:
 606
 607         ath_debug_stat_interrupt(sc, status);
 608
 609         if (sched) {
 610                 /* turn off every interrupt except SWBA */
 611                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 612                 tasklet_schedule(&sc->intr_tq);
 613         }
 614
 615         return IRQ_HANDLED;
 616
 617 #undef SCHED_INTR
 618 }
 619
 620 static u32 ath_get_extchanmode(struct ath_softc *sc,
 621                                struct ieee80211_channel *chan,
 622                                enum nl80211_channel_type channel_type)
 623 {
 624         u32 chanmode = 0;
 625
 626         switch (chan->band) {
 627         case IEEE80211_BAND_2GHZ:
 628                 switch(channel_type) {
 629                 case NL80211_CHAN_NO_HT:
 630                 case NL80211_CHAN_HT20:
 631                         chanmode = CHANNEL_G_HT20;
 632                         break;
 633                 case NL80211_CHAN_HT40PLUS:
 634                         chanmode = CHANNEL_G_HT40PLUS;
 635                         break;
 636                 case NL80211_CHAN_HT40MINUS:
 637                         chanmode = CHANNEL_G_HT40MINUS;
 638                         break;
 639                 }
 640                 break;
 641         case IEEE80211_BAND_5GHZ:
 642                 switch(channel_type) {
 643                 case NL80211_CHAN_NO_HT:
 644                 case NL80211_CHAN_HT20:
 645                         chanmode = CHANNEL_A_HT20;
 646                         break;
 647                 case NL80211_CHAN_HT40PLUS:
 648                         chanmode = CHANNEL_A_HT40PLUS;
 649                         break;
 650                 case NL80211_CHAN_HT40MINUS:
 651                         chanmode = CHANNEL_A_HT40MINUS;
 652                         break;
 653                 }
 654                 break;
 655         default:
 656                 break;
 657         }
 658
 659         return chanmode;
 660 }
 661
 662 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 663                            struct ath9k_keyval *hk, const u8 *addr,
 664                            bool authenticator)
 665 {
 666         const u8 *key_rxmic;
 667         const u8 *key_txmic;
 668
 669         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 670         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 671
 672         if (addr == NULL) {
 673                 /*
 674                  * Group key installation - only two key cache entries are used
 675                  * regardless of splitmic capability since group key is only
 676                  * used either for TX or RX.
 677                  */
 678                 if (authenticator) {
 679                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 680                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 681                 } else {
 682                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 683                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 684                 }
 685                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 686         }
 687         if (!sc->splitmic) {
 688                 /* TX and RX keys share the same key cache entry. */
 689                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 690                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 691                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 692         }
 693
 694         /* Separate key cache entries for TX and RX */
 695
 696         /* TX key goes at first index, RX key at +32. */
 697         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 698         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 699                 /* TX MIC entry failed. No need to proceed further */
 700                 DPRINTF(sc, ATH_DBG_FATAL,
 701                         "Setting TX MIC Key Failed\n");
 702                 return 0;
 703         }
 704
 705         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 706         /* XXX delete tx key on failure? */
 707         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 708 }
 709
 710 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 711 {
 712         int i;
 713
 714         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 715                 if (test_bit(i, sc->keymap) ||
 716                     test_bit(i + 64, sc->keymap))
 717                         continue; /* At least one part of TKIP key allocated */
 718                 if (sc->splitmic &&
 719                     (test_bit(i + 32, sc->keymap) ||
 720                      test_bit(i + 64 + 32, sc->keymap)))
 721                         continue; /* At least one part of TKIP key allocated */
 722
 723                 /* Found a free slot for a TKIP key */
 724                 return i;
 725         }
 726         return -1;
 727 }
 728
 729 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 730 {
 731         int i;
 732
 733         /* First, try to find slots that would not be available for TKIP. */
 734         if (sc->splitmic) {
 735                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 736                         if (!test_bit(i, sc->keymap) &&
 737                             (test_bit(i + 32, sc->keymap) ||
 738                              test_bit(i + 64, sc->keymap) ||
 739                              test_bit(i + 64 + 32, sc->keymap)))
 740                                 return i;
 741                         if (!test_bit(i + 32, sc->keymap) &&
 742                             (test_bit(i, sc->keymap) ||
 743                              test_bit(i + 64, sc->keymap) ||
 744                              test_bit(i + 64 + 32, sc->keymap)))
 745                                 return i + 32;
 746                         if (!test_bit(i + 64, sc->keymap) &&
 747                             (test_bit(i , sc->keymap) ||
 748                              test_bit(i + 32, sc->keymap) ||
 749                              test_bit(i + 64 + 32, sc->keymap)))
 750                                 return i + 64;
 751                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 752                             (test_bit(i, sc->keymap) ||
 753                              test_bit(i + 32, sc->keymap) ||
 754                              test_bit(i + 64, sc->keymap)))
 755                                 return i + 64 + 32;
 756                 }
 757         } else {
 758                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 759                         if (!test_bit(i, sc->keymap) &&
 760                             test_bit(i + 64, sc->keymap))
 761                                 return i;
 762                         if (test_bit(i, sc->keymap) &&
 763                             !test_bit(i + 64, sc->keymap))
 764                                 return i + 64;
 765                 }
 766         }
 767
 768         /* No partially used TKIP slots, pick any available slot */
 769         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 770                 /* Do not allow slots that could be needed for TKIP group keys
 771                  * to be used. This limitation could be removed if we know that
 772                  * TKIP will not be used. */
 773                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 774                         continue;
 775                 if (sc->splitmic) {
 776                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 777                                 continue;
 778                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 779                                 continue;
 780                 }
 781
 782                 if (!test_bit(i, sc->keymap))
 783                         return i; /* Found a free slot for a key */
 784         }
 785
 786         /* No free slot found */
 787         return -1;
 788 }
 789
 790 static int ath_key_config(struct ath_softc *sc,
 791                           struct ieee80211_vif *vif,
 792                           struct ieee80211_sta *sta,
 793                           struct ieee80211_key_conf *key)
 794 {
 795         struct ath9k_keyval hk;
 796         const u8 *mac = NULL;
 797         int ret = 0;
 798         int idx;
 799
 800         memset(&hk, 0, sizeof(hk));
 801
 802         switch (key->alg) {
 803         case ALG_WEP:
 804                 hk.kv_type = ATH9K_CIPHER_WEP;
 805                 break;
 806         case ALG_TKIP:
 807                 hk.kv_type = ATH9K_CIPHER_TKIP;
 808                 break;
 809         case ALG_CCMP:
 810                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 811                 break;
 812         default:
 813                 return -EOPNOTSUPP;
 814         }
 815
 816         hk.kv_len = key->keylen;
 817         memcpy(hk.kv_val, key->key, key->keylen);
 818
 819         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 820                 /* For now, use the default keys for broadcast keys. This may
 821                  * need to change with virtual interfaces. */
 822                 idx = key->keyidx;
 823         } else if (key->keyidx) {
 824                 if (WARN_ON(!sta))
 825                         return -EOPNOTSUPP;
 826                 mac = sta->addr;
 827
 828                 if (vif->type != NL80211_IFTYPE_AP) {
 829                         /* Only keyidx 0 should be used with unicast key, but
 830                          * allow this for client mode for now. */
 831                         idx = key->keyidx;
 832                 } else
 833                         return -EIO;
 834         } else {
 835                 if (WARN_ON(!sta))
 836                         return -EOPNOTSUPP;
 837                 mac = sta->addr;
 838
 839                 if (key->alg == ALG_TKIP)
 840                         idx = ath_reserve_key_cache_slot_tkip(sc);
 841                 else
 842                         idx = ath_reserve_key_cache_slot(sc);
 843                 if (idx < 0)
 844                         return -ENOSPC; /* no free key cache entries */
 845         }
 846
 847         if (key->alg == ALG_TKIP)
 848                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 849                                       vif->type == NL80211_IFTYPE_AP);
 850         else
 851                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 852
 853         if (!ret)
 854                 return -EIO;
 855
 856         set_bit(idx, sc->keymap);
 857         if (key->alg == ALG_TKIP) {
 858                 set_bit(idx + 64, sc->keymap);
 859                 if (sc->splitmic) {
 860                         set_bit(idx + 32, sc->keymap);
 861                         set_bit(idx + 64 + 32, sc->keymap);
 862                 }
 863         }
 864
 865         return idx;
 866 }
 867
 868 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 869 {
 870         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 871         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 872                 return;
 873
 874         clear_bit(key->hw_key_idx, sc->keymap);
 875         if (key->alg != ALG_TKIP)
 876                 return;
 877
 878         clear_bit(key->hw_key_idx + 64, sc->keymap);
 879         if (sc->splitmic) {
 880                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 881                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 882         }
 883 }
 884
 885 static void setup_ht_cap(struct ath_softc *sc,
 886                          struct ieee80211_sta_ht_cap *ht_info)
 887 {
 888         u8 tx_streams, rx_streams;
 889
 890         ht_info->ht_supported = true;
 891         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 892                        IEEE80211_HT_CAP_SM_PS |
 893                        IEEE80211_HT_CAP_SGI_40 |
 894                        IEEE80211_HT_CAP_DSSSCCK40;
 895
 896         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 897         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 898
 899         /* set up supported mcs set */
 900         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 901         tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
 902         rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
 903
 904         if (tx_streams != rx_streams) {
 905                 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
 906                         tx_streams, rx_streams);
 907                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 908                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 909                                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 910         }
 911
 912         ht_info->mcs.rx_mask[0] = 0xff;
 913         if (rx_streams >= 2)
 914                 ht_info->mcs.rx_mask[1] = 0xff;
 915
 916         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 917 }
 918
 919 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 920                                  struct ieee80211_vif *vif,
 921                                  struct ieee80211_bss_conf *bss_conf)
 922 {
 923
 924         if (bss_conf->assoc) {
 925                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 926                         bss_conf->aid, sc->curbssid);
 927
 928                 /* New association, store aid */
 929                 sc->curaid = bss_conf->aid;
 930                 ath9k_hw_write_associd(sc);
 931
 932                 /*
 933                  * Request a re-configuration of Beacon related timers
 934                  * on the receipt of the first Beacon frame (i.e.,
 935                  * after time sync with the AP).
 936                  */
 937                 sc->sc_flags |= SC_OP_BEACON_SYNC;
 938
 939                 /* Configure the beacon */
 940                 ath_beacon_config(sc, vif);
 941
 942                 /* Reset rssi stats */
 943                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 944                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 945                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 946                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 947
 948                 ath_start_ani(sc);
 949         } else {
 950                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
 951                 sc->curaid = 0;
 952                 /* Stop ANI */
 953                 del_timer_sync(&sc->ani.timer);
 954         }
 955 }
 956
 957 /********************************/
 958 /*       LED functions          */
 959 /********************************/
 960
 961 static void ath_led_blink_work(struct work_struct *work)
 962 {
 963         struct ath_softc *sc = container_of(work, struct ath_softc,
 964                                             ath_led_blink_work.work);
 965
 966         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 967                 return;
 968
 969         if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
 970             (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
 971                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
 972         else
 973                 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
 974                                   (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 975
 976         ieee80211_queue_delayed_work(sc->hw,
 977                                      &sc->ath_led_blink_work,
 978                                      (sc->sc_flags & SC_OP_LED_ON) ?
 979                                         msecs_to_jiffies(sc->led_off_duration) :
 980                                         msecs_to_jiffies(sc->led_on_duration));
 981
 982         sc->led_on_duration = sc->led_on_cnt ?
 983                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
 984                         ATH_LED_ON_DURATION_IDLE;
 985         sc->led_off_duration = sc->led_off_cnt ?
 986                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
 987                         ATH_LED_OFF_DURATION_IDLE;
 988         sc->led_on_cnt = sc->led_off_cnt = 0;
 989         if (sc->sc_flags & SC_OP_LED_ON)
 990                 sc->sc_flags &= ~SC_OP_LED_ON;
 991         else
 992                 sc->sc_flags |= SC_OP_LED_ON;
 993 }
 994
 995 static void ath_led_brightness(struct led_classdev *led_cdev,
 996                                enum led_brightness brightness)
 997 {
 998         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 999         struct ath_softc *sc = led->sc;
1000
1001         switch (brightness) {
1002         case LED_OFF:
1003                 if (led->led_type == ATH_LED_ASSOC ||
1004                     led->led_type == ATH_LED_RADIO) {
1005                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1006                                 (led->led_type == ATH_LED_RADIO));
1007                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1008                         if (led->led_type == ATH_LED_RADIO)
1009                                 sc->sc_flags &= ~SC_OP_LED_ON;
1010                 } else {
1011                         sc->led_off_cnt++;
1012                 }
1013                 break;
1014         case LED_FULL:
1015                 if (led->led_type == ATH_LED_ASSOC) {
1016                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1017                         ieee80211_queue_delayed_work(sc->hw,
1018                                                      &sc->ath_led_blink_work, 0);
1019                 } else if (led->led_type == ATH_LED_RADIO) {
1020                         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1021                         sc->sc_flags |= SC_OP_LED_ON;
1022                 } else {
1023                         sc->led_on_cnt++;
1024                 }
1025                 break;
1026         default:
1027                 break;
1028         }
1029 }
1030
1031 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1032                             char *trigger)
1033 {
1034         int ret;
1035
1036         led->sc = sc;
1037         led->led_cdev.name = led->name;
1038         led->led_cdev.default_trigger = trigger;
1039         led->led_cdev.brightness_set = ath_led_brightness;
1040
1041         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1042         if (ret)
1043                 DPRINTF(sc, ATH_DBG_FATAL,
1044                         "Failed to register led:%s", led->name);
1045         else
1046                 led->registered = 1;
1047         return ret;
1048 }
1049
1050 static void ath_unregister_led(struct ath_led *led)
1051 {
1052         if (led->registered) {
1053                 led_classdev_unregister(&led->led_cdev);
1054                 led->registered = 0;
1055         }
1056 }
1057
1058 static void ath_deinit_leds(struct ath_softc *sc)
1059 {
1060         ath_unregister_led(&sc->assoc_led);
1061         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1062         ath_unregister_led(&sc->tx_led);
1063         ath_unregister_led(&sc->rx_led);
1064         ath_unregister_led(&sc->radio_led);
1065         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1066 }
1067
1068 static void ath_init_leds(struct ath_softc *sc)
1069 {
1070         char *trigger;
1071         int ret;
1072
1073         if (AR_SREV_9287(sc->sc_ah))
1074                 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1075         else
1076                 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1077
1078         /* Configure gpio 1 for output */
1079         ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1080                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1081         /* LED off, active low */
1082         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1083
1084         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1085
1086         trigger = ieee80211_get_radio_led_name(sc->hw);
1087         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1088                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1089         ret = ath_register_led(sc, &sc->radio_led, trigger);
1090         sc->radio_led.led_type = ATH_LED_RADIO;
1091         if (ret)
1092                 goto fail;
1093
1094         trigger = ieee80211_get_assoc_led_name(sc->hw);
1095         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1096                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1097         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1098         sc->assoc_led.led_type = ATH_LED_ASSOC;
1099         if (ret)
1100                 goto fail;
1101
1102         trigger = ieee80211_get_tx_led_name(sc->hw);
1103         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1104                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1105         ret = ath_register_led(sc, &sc->tx_led, trigger);
1106         sc->tx_led.led_type = ATH_LED_TX;
1107         if (ret)
1108                 goto fail;
1109
1110         trigger = ieee80211_get_rx_led_name(sc->hw);
1111         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1112                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1113         ret = ath_register_led(sc, &sc->rx_led, trigger);
1114         sc->rx_led.led_type = ATH_LED_RX;
1115         if (ret)
1116                 goto fail;
1117
1118         return;
1119
1120 fail:
1121         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1122         ath_deinit_leds(sc);
1123 }
1124
1125 void ath_radio_enable(struct ath_softc *sc)
1126 {
1127         struct ath_hw *ah = sc->sc_ah;
1128         struct ieee80211_channel *channel = sc->hw->conf.channel;
1129         int r;
1130
1131         ath9k_ps_wakeup(sc);
1132         ath9k_hw_configpcipowersave(ah, 0);
1133
1134         if (!ah->curchan)
1135                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1136
1137         spin_lock_bh(&sc->sc_resetlock);
1138         r = ath9k_hw_reset(ah, ah->curchan, false);
1139         if (r) {
1140                 DPRINTF(sc, ATH_DBG_FATAL,
1141                         "Unable to reset channel %u (%uMhz) ",
1142                         "reset status %d\n",
1143                         channel->center_freq, r);
1144         }
1145         spin_unlock_bh(&sc->sc_resetlock);
1146
1147         ath_update_txpow(sc);
1148         if (ath_startrecv(sc) != 0) {
1149                 DPRINTF(sc, ATH_DBG_FATAL,
1150                         "Unable to restart recv logic\n");
1151                 return;
1152         }
1153
1154         if (sc->sc_flags & SC_OP_BEACONS)
1155                 ath_beacon_config(sc, NULL);    /* restart beacons */
1156
1157         /* Re-Enable  interrupts */
1158         ath9k_hw_set_interrupts(ah, sc->imask);
1159
1160         /* Enable LED */
1161         ath9k_hw_cfg_output(ah, ah->led_pin,
1162                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1163         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1164
1165         ieee80211_wake_queues(sc->hw);
1166         ath9k_ps_restore(sc);
1167 }
1168
1169 void ath_radio_disable(struct ath_softc *sc)
1170 {
1171         struct ath_hw *ah = sc->sc_ah;
1172         struct ieee80211_channel *channel = sc->hw->conf.channel;
1173         int r;
1174
1175         ath9k_ps_wakeup(sc);
1176         ieee80211_stop_queues(sc->hw);
1177
1178         /* Disable LED */
1179         ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1180         ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1181
1182         /* Disable interrupts */
1183         ath9k_hw_set_interrupts(ah, 0);
1184
1185         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1186         ath_stoprecv(sc);               /* turn off frame recv */
1187         ath_flushrecv(sc);              /* flush recv queue */
1188
1189         if (!ah->curchan)
1190                 ah->curchan = ath_get_curchannel(sc, sc->hw);
1191
1192         spin_lock_bh(&sc->sc_resetlock);
1193         r = ath9k_hw_reset(ah, ah->curchan, false);
1194         if (r) {
1195                 DPRINTF(sc, ATH_DBG_FATAL,
1196                         "Unable to reset channel %u (%uMhz) "
1197                         "reset status %d\n",
1198                         channel->center_freq, r);
1199         }
1200         spin_unlock_bh(&sc->sc_resetlock);
1201
1202         ath9k_hw_phy_disable(ah);
1203         ath9k_hw_configpcipowersave(ah, 1);
1204         ath9k_ps_restore(sc);
1205         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1206 }
1207
1208 /*******************/
1209 /*      Rfkill     */
1210 /*******************/
1211
1212 static bool ath_is_rfkill_set(struct ath_softc *sc)
1213 {
1214         struct ath_hw *ah = sc->sc_ah;
1215
1216         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1217                                   ah->rfkill_polarity;
1218 }
1219
1220 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1221 {
1222         struct ath_wiphy *aphy = hw->priv;
1223         struct ath_softc *sc = aphy->sc;
1224         bool blocked = !!ath_is_rfkill_set(sc);
1225
1226         wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1227
1228         if (blocked)
1229                 ath_radio_disable(sc);
1230         else
1231                 ath_radio_enable(sc);
1232 }
1233
1234 static void ath_start_rfkill_poll(struct ath_softc *sc)
1235 {
1236         struct ath_hw *ah = sc->sc_ah;
1237
1238         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1239                 wiphy_rfkill_start_polling(sc->hw->wiphy);
1240 }
1241
1242 void ath_cleanup(struct ath_softc *sc)
1243 {
1244         ath_detach(sc);
1245         free_irq(sc->irq, sc);
1246         ath_bus_cleanup(sc);
1247         kfree(sc->sec_wiphy);
1248         ieee80211_free_hw(sc->hw);
1249 }
1250
1251 void ath_detach(struct ath_softc *sc)
1252 {
1253         struct ieee80211_hw *hw = sc->hw;
1254         int i = 0;
1255
1256         ath9k_ps_wakeup(sc);
1257
1258         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1259
1260         ath_deinit_leds(sc);
1261
1262         for (i = 0; i < sc->num_sec_wiphy; i++) {
1263                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1264                 if (aphy == NULL)
1265                         continue;
1266                 sc->sec_wiphy[i] = NULL;
1267                 ieee80211_unregister_hw(aphy->hw);
1268                 ieee80211_free_hw(aphy->hw);
1269         }
1270         ieee80211_unregister_hw(hw);
1271         ath_rx_cleanup(sc);
1272         ath_tx_cleanup(sc);
1273
1274         tasklet_kill(&sc->intr_tq);
1275         tasklet_kill(&sc->bcon_tasklet);
1276
1277         if (!(sc->sc_flags & SC_OP_INVALID))
1278                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1279
1280         /* cleanup tx queues */
1281         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1282                 if (ATH_TXQ_SETUP(sc, i))
1283                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1284
1285         ath9k_hw_detach(sc->sc_ah);
1286         sc->sc_ah = NULL;
1287         ath9k_exit_debug(sc);
1288 }
1289
1290 static int ath9k_reg_notifier(struct wiphy *wiphy,
1291                               struct regulatory_request *request)
1292 {
1293         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1294         struct ath_wiphy *aphy = hw->priv;
1295         struct ath_softc *sc = aphy->sc;
1296         struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1297
1298         return ath_reg_notifier_apply(wiphy, request, reg);
1299 }
1300
1301 /*
1302  * Initialize and fill ath_softc, ath_sofct is the
1303  * "Software Carrier" struct. Historically it has existed
1304  * to allow the separation between hardware specific
1305  * variables (now in ath_hw) and driver specific variables.
1306  */
1307 static int ath_init_softc(u16 devid, struct ath_softc *sc)
1308 {
1309         struct ath_hw *ah = NULL;
1310         int r = 0, i;
1311         int csz = 0;
1312
1313         /* XXX: hardware will not be ready until ath_open() being called */
1314         sc->sc_flags |= SC_OP_INVALID;
1315
1316         if (ath9k_init_debug(sc) < 0)
1317                 printk(KERN_ERR "Unable to create debugfs files\n");
1318
1319         spin_lock_init(&sc->wiphy_lock);
1320         spin_lock_init(&sc->sc_resetlock);
1321         spin_lock_init(&sc->sc_serial_rw);
1322         spin_lock_init(&sc->ani_lock);
1323         spin_lock_init(&sc->sc_pm_lock);
1324         mutex_init(&sc->mutex);
1325         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1326         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1327                      (unsigned long)sc);
1328
1329         /*
1330          * Cache line size is used to size and align various
1331          * structures used to communicate with the hardware.
1332          */
1333         ath_read_cachesize(sc, &csz);
1334         /* XXX assert csz is non-zero */
1335         sc->common.cachelsz = csz << 2; /* convert to bytes */
1336
1337         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1338         if (!ah) {
1339                 r = -ENOMEM;
1340                 goto bad_no_ah;
1341         }
1342
1343         ah->ah_sc = sc;
1344         ah->hw_version.devid = devid;
1345         sc->sc_ah = ah;
1346
1347         r = ath9k_hw_init(ah);
1348         if (r) {
1349                 DPRINTF(sc, ATH_DBG_FATAL,
1350                         "Unable to initialize hardware; "
1351                         "initialization status: %d\n", r);
1352                 goto bad;
1353         }
1354
1355         /* Get the hardware key cache size. */
1356         sc->keymax = ah->caps.keycache_size;
1357         if (sc->keymax > ATH_KEYMAX) {
1358                 DPRINTF(sc, ATH_DBG_ANY,
1359                         "Warning, using only %u entries in %u key cache\n",
1360                         ATH_KEYMAX, sc->keymax);
1361                 sc->keymax = ATH_KEYMAX;
1362         }
1363
1364         /*
1365          * Reset the key cache since some parts do not
1366          * reset the contents on initial power up.
1367          */
1368         for (i = 0; i < sc->keymax; i++)
1369                 ath9k_hw_keyreset(ah, (u16) i);
1370
1371         /* default to MONITOR mode */
1372         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1373
1374         /* Setup rate tables */
1375
1376         ath_rate_attach(sc);
1377         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1378         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1379
1380         /*
1381          * Allocate hardware transmit queues: one queue for
1382          * beacon frames and one data queue for each QoS
1383          * priority.  Note that the hal handles reseting
1384          * these queues at the needed time.
1385          */
1386         sc->beacon.beaconq = ath_beaconq_setup(ah);
1387         if (sc->beacon.beaconq == -1) {
1388                 DPRINTF(sc, ATH_DBG_FATAL,
1389                         "Unable to setup a beacon xmit queue\n");
1390                 r = -EIO;
1391                 goto bad2;
1392         }
1393         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1394         if (sc->beacon.cabq == NULL) {
1395                 DPRINTF(sc, ATH_DBG_FATAL,
1396                         "Unable to setup CAB xmit queue\n");
1397                 r = -EIO;
1398                 goto bad2;
1399         }
1400
1401         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1402         ath_cabq_update(sc);
1403
1404         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1405                 sc->tx.hwq_map[i] = -1;
1406
1407         /* Setup data queues */
1408         /* NB: ensure BK queue is the lowest priority h/w queue */
1409         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1410                 DPRINTF(sc, ATH_DBG_FATAL,
1411                         "Unable to setup xmit queue for BK traffic\n");
1412                 r = -EIO;
1413                 goto bad2;
1414         }
1415
1416         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1417                 DPRINTF(sc, ATH_DBG_FATAL,
1418                         "Unable to setup xmit queue for BE traffic\n");
1419                 r = -EIO;
1420                 goto bad2;
1421         }
1422         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1423                 DPRINTF(sc, ATH_DBG_FATAL,
1424                         "Unable to setup xmit queue for VI traffic\n");
1425                 r = -EIO;
1426                 goto bad2;
1427         }
1428         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1429                 DPRINTF(sc, ATH_DBG_FATAL,
1430                         "Unable to setup xmit queue for VO traffic\n");
1431                 r = -EIO;
1432                 goto bad2;
1433         }
1434
1435         /* Initializes the noise floor to a reasonable default value.
1436          * Later on this will be updated during ANI processing. */
1437
1438         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1439         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1440
1441         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1442                                    ATH9K_CIPHER_TKIP, NULL)) {
1443                 /*
1444                  * Whether we should enable h/w TKIP MIC.
1445                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1446                  * report WMM capable, so it's always safe to turn on
1447                  * TKIP MIC in this case.
1448                  */
1449                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1450                                        0, 1, NULL);
1451         }
1452
1453         /*
1454          * Check whether the separate key cache entries
1455          * are required to handle both tx+rx MIC keys.
1456          * With split mic keys the number of stations is limited
1457          * to 27 otherwise 59.
1458          */
1459         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1460                                    ATH9K_CIPHER_TKIP, NULL)
1461             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1462                                       ATH9K_CIPHER_MIC, NULL)
1463             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1464                                       0, NULL))
1465                 sc->splitmic = 1;
1466
1467         /* turn on mcast key search if possible */
1468         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1469                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1470                                              1, NULL);
1471
1472         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1473
1474         /* 11n Capabilities */
1475         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1476                 sc->sc_flags |= SC_OP_TXAGGR;
1477                 sc->sc_flags |= SC_OP_RXAGGR;
1478         }
1479
1480         sc->tx_chainmask = ah->caps.tx_chainmask;
1481         sc->rx_chainmask = ah->caps.rx_chainmask;
1482
1483         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1484         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1485
1486         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1487                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1488
1489         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1490
1491         /* initialize beacon slots */
1492         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1493                 sc->beacon.bslot[i] = NULL;
1494                 sc->beacon.bslot_aphy[i] = NULL;
1495         }
1496
1497         /* setup channels and rates */
1498
1499         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1500         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1501                 sc->rates[IEEE80211_BAND_2GHZ];
1502         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1503         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1504                 ARRAY_SIZE(ath9k_2ghz_chantable);
1505
1506         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1507                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1508                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1509                         sc->rates[IEEE80211_BAND_5GHZ];
1510                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1511                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1512                         ARRAY_SIZE(ath9k_5ghz_chantable);
1513         }
1514
1515         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1516                 ath9k_hw_btcoex_enable(sc->sc_ah);
1517
1518         return 0;
1519 bad2:
1520         /* cleanup tx queues */
1521         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1522                 if (ATH_TXQ_SETUP(sc, i))
1523                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1524 bad:
1525         ath9k_hw_detach(ah);
1526         sc->sc_ah = NULL;
1527 bad_no_ah:
1528         ath9k_exit_debug(sc);
1529
1530         return r;
1531 }
1532
1533 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1534 {
1535         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1536                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1537                 IEEE80211_HW_SIGNAL_DBM |
1538                 IEEE80211_HW_AMPDU_AGGREGATION |
1539                 IEEE80211_HW_SUPPORTS_PS |
1540                 IEEE80211_HW_PS_NULLFUNC_STACK |
1541                 IEEE80211_HW_SPECTRUM_MGMT;
1542
1543         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1544                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1545
1546         hw->wiphy->interface_modes =
1547                 BIT(NL80211_IFTYPE_AP) |
1548                 BIT(NL80211_IFTYPE_STATION) |
1549                 BIT(NL80211_IFTYPE_ADHOC) |
1550                 BIT(NL80211_IFTYPE_MESH_POINT);
1551
1552         hw->queues = 4;
1553         hw->max_rates = 4;
1554         hw->channel_change_time = 5000;
1555         hw->max_listen_interval = 10;
1556         /* Hardware supports 10 but we use 4 */
1557         hw->max_rate_tries = 4;
1558         hw->sta_data_size = sizeof(struct ath_node);
1559         hw->vif_data_size = sizeof(struct ath_vif);
1560
1561         hw->rate_control_algorithm = "ath9k_rate_control";
1562
1563         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1564                 &sc->sbands[IEEE80211_BAND_2GHZ];
1565         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1566                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1567                         &sc->sbands[IEEE80211_BAND_5GHZ];
1568 }
1569
1570 /* Device driver core initialization */
1571 int ath_init_device(u16 devid, struct ath_softc *sc)
1572 {
1573         struct ieee80211_hw *hw = sc->hw;
1574         int error = 0, i;
1575         struct ath_regulatory *reg;
1576
1577         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1578
1579         error = ath_init_softc(devid, sc);
1580         if (error != 0)
1581                 return error;
1582
1583         /* get mac address from hardware and set in mac80211 */
1584
1585         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1586
1587         ath_set_hw_capab(sc, hw);
1588
1589         error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1590                               ath9k_reg_notifier);
1591         if (error)
1592                 return error;
1593
1594         reg = &sc->sc_ah->regulatory;
1595
1596         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1597                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1598                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1599                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1600         }
1601
1602         /* initialize tx/rx engine */
1603         error = ath_tx_init(sc, ATH_TXBUF);
1604         if (error != 0)
1605                 goto error_attach;
1606
1607         error = ath_rx_init(sc, ATH_RXBUF);
1608         if (error != 0)
1609                 goto error_attach;
1610
1611         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1612         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1613         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1614
1615         error = ieee80211_register_hw(hw);
1616
1617         if (!ath_is_world_regd(reg)) {
1618                 error = regulatory_hint(hw->wiphy, reg->alpha2);
1619                 if (error)
1620                         goto error_attach;
1621         }
1622
1623         /* Initialize LED control */
1624         ath_init_leds(sc);
1625
1626         ath_start_rfkill_poll(sc);
1627
1628         return 0;
1629
1630 error_attach:
1631         /* cleanup tx queues */
1632         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1633                 if (ATH_TXQ_SETUP(sc, i))
1634                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1635
1636         ath9k_hw_detach(sc->sc_ah);
1637         sc->sc_ah = NULL;
1638         ath9k_exit_debug(sc);
1639
1640         return error;
1641 }
1642
1643 int ath_reset(struct ath_softc *sc, bool retry_tx)
1644 {
1645         struct ath_hw *ah = sc->sc_ah;
1646         struct ieee80211_hw *hw = sc->hw;
1647         int r;
1648
1649         ath9k_hw_set_interrupts(ah, 0);
1650         ath_drain_all_txq(sc, retry_tx);
1651         ath_stoprecv(sc);
1652         ath_flushrecv(sc);
1653
1654         spin_lock_bh(&sc->sc_resetlock);
1655         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1656         if (r)
1657                 DPRINTF(sc, ATH_DBG_FATAL,
1658                         "Unable to reset hardware; reset status %d\n", r);
1659         spin_unlock_bh(&sc->sc_resetlock);
1660
1661         if (ath_startrecv(sc) != 0)
1662                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1663
1664         /*
1665          * We may be doing a reset in response to a request
1666          * that changes the channel so update any state that
1667          * might change as a result.
1668          */
1669         ath_cache_conf_rate(sc, &hw->conf);
1670
1671         ath_update_txpow(sc);
1672
1673         if (sc->sc_flags & SC_OP_BEACONS)
1674                 ath_beacon_config(sc, NULL);    /* restart beacons */
1675
1676         ath9k_hw_set_interrupts(ah, sc->imask);
1677
1678         if (retry_tx) {
1679                 int i;
1680                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1681                         if (ATH_TXQ_SETUP(sc, i)) {
1682                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1683                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1684                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1685                         }
1686                 }
1687         }
1688
1689         return r;
1690 }
1691
1692 /*
1693  *  This function will allocate both the DMA descriptor structure, and the
1694  *  buffers it contains.  These are used to contain the descriptors used
1695  *  by the system.
1696 */
1697 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1698                       struct list_head *head, const char *name,
1699                       int nbuf, int ndesc)
1700 {
1701 #define DS2PHYS(_dd, _ds)                                               \
1702         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1703 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1704 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1705
1706         struct ath_desc *ds;
1707         struct ath_buf *bf;
1708         int i, bsize, error;
1709
1710         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1711                 name, nbuf, ndesc);
1712
1713         INIT_LIST_HEAD(head);
1714         /* ath_desc must be a multiple of DWORDs */
1715         if ((sizeof(struct ath_desc) % 4) != 0) {
1716                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1717                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1718                 error = -ENOMEM;
1719                 goto fail;
1720         }
1721
1722         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1723
1724         /*
1725          * Need additional DMA memory because we can't use
1726          * descriptors that cross the 4K page boundary. Assume
1727          * one skipped descriptor per 4K page.
1728          */
1729         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1730                 u32 ndesc_skipped =
1731                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1732                 u32 dma_len;
1733
1734                 while (ndesc_skipped) {
1735                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1736                         dd->dd_desc_len += dma_len;
1737
1738                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1739                 };
1740         }
1741
1742         /* allocate descriptors */
1743         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1744                                          &dd->dd_desc_paddr, GFP_KERNEL);
1745         if (dd->dd_desc == NULL) {
1746                 error = -ENOMEM;
1747                 goto fail;
1748         }
1749         ds = dd->dd_desc;
1750         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1751                 name, ds, (u32) dd->dd_desc_len,
1752                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1753
1754         /* allocate buffers */
1755         bsize = sizeof(struct ath_buf) * nbuf;
1756         bf = kzalloc(bsize, GFP_KERNEL);
1757         if (bf == NULL) {
1758                 error = -ENOMEM;
1759                 goto fail2;
1760         }
1761         dd->dd_bufptr = bf;
1762
1763         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1764                 bf->bf_desc = ds;
1765                 bf->bf_daddr = DS2PHYS(dd, ds);
1766
1767                 if (!(sc->sc_ah->caps.hw_caps &
1768                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1769                         /*
1770                          * Skip descriptor addresses which can cause 4KB
1771                          * boundary crossing (addr + length) with a 32 dword
1772                          * descriptor fetch.
1773                          */
1774                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1775                                 ASSERT((caddr_t) bf->bf_desc <
1776                                        ((caddr_t) dd->dd_desc +
1777                                         dd->dd_desc_len));
1778
1779                                 ds += ndesc;
1780                                 bf->bf_desc = ds;
1781                                 bf->bf_daddr = DS2PHYS(dd, ds);
1782                         }
1783                 }
1784                 list_add_tail(&bf->list, head);
1785         }
1786         return 0;
1787 fail2:
1788         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1789                           dd->dd_desc_paddr);
1790 fail:
1791         memset(dd, 0, sizeof(*dd));
1792         return error;
1793 #undef ATH_DESC_4KB_BOUND_CHECK
1794 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1795 #undef DS2PHYS
1796 }
1797
1798 void ath_descdma_cleanup(struct ath_softc *sc,
1799                          struct ath_descdma *dd,
1800                          struct list_head *head)
1801 {
1802         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1803                           dd->dd_desc_paddr);
1804
1805         INIT_LIST_HEAD(head);
1806         kfree(dd->dd_bufptr);
1807         memset(dd, 0, sizeof(*dd));
1808 }
1809
1810 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1811 {
1812         int qnum;
1813
1814         switch (queue) {
1815         case 0:
1816                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1817                 break;
1818         case 1:
1819                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1820                 break;
1821         case 2:
1822                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1823                 break;
1824         case 3:
1825                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1826                 break;
1827         default:
1828                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1829                 break;
1830         }
1831
1832         return qnum;
1833 }
1834
1835 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1836 {
1837         int qnum;
1838
1839         switch (queue) {
1840         case ATH9K_WME_AC_VO:
1841                 qnum = 0;
1842                 break;
1843         case ATH9K_WME_AC_VI:
1844                 qnum = 1;
1845                 break;
1846         case ATH9K_WME_AC_BE:
1847                 qnum = 2;
1848                 break;
1849         case ATH9K_WME_AC_BK:
1850                 qnum = 3;
1851                 break;
1852         default:
1853                 qnum = -1;
1854                 break;
1855         }
1856
1857         return qnum;
1858 }
1859
1860 /* XXX: Remove me once we don't depend on ath9k_channel for all
1861  * this redundant data */
1862 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1863                            struct ath9k_channel *ichan)
1864 {
1865         struct ieee80211_channel *chan = hw->conf.channel;
1866         struct ieee80211_conf *conf = &hw->conf;
1867
1868         ichan->channel = chan->center_freq;
1869         ichan->chan = chan;
1870
1871         if (chan->band == IEEE80211_BAND_2GHZ) {
1872                 ichan->chanmode = CHANNEL_G;
1873                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1874         } else {
1875                 ichan->chanmode = CHANNEL_A;
1876                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1877         }
1878
1879         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1880
1881         if (conf_is_ht(conf)) {
1882                 if (conf_is_ht40(conf))
1883                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1884
1885                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1886                                             conf->channel_type);
1887         }
1888 }
1889
1890 /**********************/
1891 /* mac80211 callbacks */
1892 /**********************/
1893
1894 static int ath9k_start(struct ieee80211_hw *hw)
1895 {
1896         struct ath_wiphy *aphy = hw->priv;
1897         struct ath_softc *sc = aphy->sc;
1898         struct ieee80211_channel *curchan = hw->conf.channel;
1899         struct ath9k_channel *init_channel;
1900         int r;
1901
1902         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1903                 "initial channel: %d MHz\n", curchan->center_freq);
1904
1905         mutex_lock(&sc->mutex);
1906
1907         if (ath9k_wiphy_started(sc)) {
1908                 if (sc->chan_idx == curchan->hw_value) {
1909                         /*
1910                          * Already on the operational channel, the new wiphy
1911                          * can be marked active.
1912                          */
1913                         aphy->state = ATH_WIPHY_ACTIVE;
1914                         ieee80211_wake_queues(hw);
1915                 } else {
1916                         /*
1917                          * Another wiphy is on another channel, start the new
1918                          * wiphy in paused state.
1919                          */
1920                         aphy->state = ATH_WIPHY_PAUSED;
1921                         ieee80211_stop_queues(hw);
1922                 }
1923                 mutex_unlock(&sc->mutex);
1924                 return 0;
1925         }
1926         aphy->state = ATH_WIPHY_ACTIVE;
1927
1928         /* setup initial channel */
1929
1930         sc->chan_idx = curchan->hw_value;
1931
1932         init_channel = ath_get_curchannel(sc, hw);
1933
1934         /* Reset SERDES registers */
1935         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1936
1937         /*
1938          * The basic interface to setting the hardware in a good
1939          * state is ``reset''.  On return the hardware is known to
1940          * be powered up and with interrupts disabled.  This must
1941          * be followed by initialization of the appropriate bits
1942          * and then setup of the interrupt mask.
1943          */
1944         spin_lock_bh(&sc->sc_resetlock);
1945         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1946         if (r) {
1947                 DPRINTF(sc, ATH_DBG_FATAL,
1948                         "Unable to reset hardware; reset status %d "
1949                         "(freq %u MHz)\n", r,
1950                         curchan->center_freq);
1951                 spin_unlock_bh(&sc->sc_resetlock);
1952                 goto mutex_unlock;
1953         }
1954         spin_unlock_bh(&sc->sc_resetlock);
1955
1956         /*
1957          * This is needed only to setup initial state
1958          * but it's best done after a reset.
1959          */
1960         ath_update_txpow(sc);
1961
1962         /*
1963          * Setup the hardware after reset:
1964          * The receive engine is set going.
1965          * Frame transmit is handled entirely
1966          * in the frame output path; there's nothing to do
1967          * here except setup the interrupt mask.
1968          */
1969         if (ath_startrecv(sc) != 0) {
1970                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1971                 r = -EIO;
1972                 goto mutex_unlock;
1973         }
1974
1975         /* Setup our intr mask. */
1976         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
1977                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1978                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1979
1980         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
1981                 sc->imask |= ATH9K_INT_GTT;
1982
1983         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
1984                 sc->imask |= ATH9K_INT_CST;
1985
1986         ath_cache_conf_rate(sc, &hw->conf);
1987
1988         sc->sc_flags &= ~SC_OP_INVALID;
1989
1990         /* Disable BMISS interrupt when we're not associated */
1991         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1992         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
1993
1994         ieee80211_wake_queues(hw);
1995
1996         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
1997
1998 mutex_unlock:
1999         mutex_unlock(&sc->mutex);
2000
2001         return r;
2002 }
2003
2004 static int ath9k_tx(struct ieee80211_hw *hw,
2005                     struct sk_buff *skb)
2006 {
2007         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2008         struct ath_wiphy *aphy = hw->priv;
2009         struct ath_softc *sc = aphy->sc;
2010         struct ath_tx_control txctl;
2011         int hdrlen, padsize;
2012
2013         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2014                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2015                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2016                 goto exit;
2017         }
2018
2019         if (sc->ps_enabled) {
2020                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2021                 /*
2022                  * mac80211 does not set PM field for normal data frames, so we
2023                  * need to update that based on the current PS mode.
2024                  */
2025                 if (ieee80211_is_data(hdr->frame_control) &&
2026                     !ieee80211_is_nullfunc(hdr->frame_control) &&
2027                     !ieee80211_has_pm(hdr->frame_control)) {
2028                         DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2029                                 "while in PS mode\n");
2030                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2031                 }
2032         }
2033
2034         if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2035                 /*
2036                  * We are using PS-Poll and mac80211 can request TX while in
2037                  * power save mode. Need to wake up hardware for the TX to be
2038                  * completed and if needed, also for RX of buffered frames.
2039                  */
2040                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2041                 ath9k_ps_wakeup(sc);
2042                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2043                 if (ieee80211_is_pspoll(hdr->frame_control)) {
2044                         DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2045                                 "buffered frame\n");
2046                         sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2047                 } else {
2048                         DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2049                         sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2050                 }
2051                 /*
2052                  * The actual restore operation will happen only after
2053                  * the sc_flags bit is cleared. We are just dropping
2054                  * the ps_usecount here.
2055                  */
2056                 ath9k_ps_restore(sc);
2057         }
2058
2059         memset(&txctl, 0, sizeof(struct ath_tx_control));
2060
2061         /*
2062          * As a temporary workaround, assign seq# here; this will likely need
2063          * to be cleaned up to work better with Beacon transmission and virtual
2064          * BSSes.
2065          */
2066         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2067                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2068                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2069                         sc->tx.seq_no += 0x10;
2070                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2071                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2072         }
2073
2074         /* Add the padding after the header if this is not already done */
2075         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2076         if (hdrlen & 3) {
2077                 padsize = hdrlen % 4;
2078                 if (skb_headroom(skb) < padsize)
2079                         return -1;
2080                 skb_push(skb, padsize);
2081                 memmove(skb->data, skb->data + padsize, hdrlen);
2082         }
2083
2084         /* Check if a tx queue is available */
2085
2086         txctl.txq = ath_test_get_txq(sc, skb);
2087         if (!txctl.txq)
2088                 goto exit;
2089
2090         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2091
2092         if (ath_tx_start(hw, skb, &txctl) != 0) {
2093                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2094                 goto exit;
2095         }
2096
2097         return 0;
2098 exit:
2099         dev_kfree_skb_any(skb);
2100         return 0;
2101 }
2102
2103 static void ath9k_stop(struct ieee80211_hw *hw)
2104 {
2105         struct ath_wiphy *aphy = hw->priv;
2106         struct ath_softc *sc = aphy->sc;
2107
2108         aphy->state = ATH_WIPHY_INACTIVE;
2109
2110         cancel_delayed_work_sync(&sc->ath_led_blink_work);
2111         cancel_delayed_work_sync(&sc->tx_complete_work);
2112
2113         if (!sc->num_sec_wiphy) {
2114                 cancel_delayed_work_sync(&sc->wiphy_work);
2115                 cancel_work_sync(&sc->chan_work);
2116         }
2117
2118         if (sc->sc_flags & SC_OP_INVALID) {
2119                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2120                 return;
2121         }
2122
2123         mutex_lock(&sc->mutex);
2124
2125         cancel_delayed_work_sync(&sc->tx_complete_work);
2126
2127         if (ath9k_wiphy_started(sc)) {
2128                 mutex_unlock(&sc->mutex);
2129                 return; /* another wiphy still in use */
2130         }
2131
2132         /* make sure h/w will not generate any interrupt
2133          * before setting the invalid flag. */
2134         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2135
2136         if (!(sc->sc_flags & SC_OP_INVALID)) {
2137                 ath_drain_all_txq(sc, false);
2138                 ath_stoprecv(sc);
2139                 ath9k_hw_phy_disable(sc->sc_ah);
2140         } else
2141                 sc->rx.rxlink = NULL;
2142
2143         wiphy_rfkill_stop_polling(sc->hw->wiphy);
2144
2145         /* disable HAL and put h/w to sleep */
2146         ath9k_hw_disable(sc->sc_ah);
2147         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2148         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
2149
2150         sc->sc_flags |= SC_OP_INVALID;
2151
2152         mutex_unlock(&sc->mutex);
2153
2154         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2155 }
2156
2157 static int ath9k_add_interface(struct ieee80211_hw *hw,
2158                                struct ieee80211_if_init_conf *conf)
2159 {
2160         struct ath_wiphy *aphy = hw->priv;
2161         struct ath_softc *sc = aphy->sc;
2162         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2163         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2164         int ret = 0;
2165
2166         mutex_lock(&sc->mutex);
2167
2168         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2169             sc->nvifs > 0) {
2170                 ret = -ENOBUFS;
2171                 goto out;
2172         }
2173
2174         switch (conf->type) {
2175         case NL80211_IFTYPE_STATION:
2176                 ic_opmode = NL80211_IFTYPE_STATION;
2177                 break;
2178         case NL80211_IFTYPE_ADHOC:
2179         case NL80211_IFTYPE_AP:
2180         case NL80211_IFTYPE_MESH_POINT:
2181                 if (sc->nbcnvifs >= ATH_BCBUF) {
2182                         ret = -ENOBUFS;
2183                         goto out;
2184                 }
2185                 ic_opmode = conf->type;
2186                 break;
2187         default:
2188                 DPRINTF(sc, ATH_DBG_FATAL,
2189                         "Interface type %d not yet supported\n", conf->type);
2190                 ret = -EOPNOTSUPP;
2191                 goto out;
2192         }
2193
2194         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2195
2196         /* Set the VIF opmode */
2197         avp->av_opmode = ic_opmode;
2198         avp->av_bslot = -1;
2199
2200         sc->nvifs++;
2201
2202         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2203                 ath9k_set_bssid_mask(hw);
2204
2205         if (sc->nvifs > 1)
2206                 goto out; /* skip global settings for secondary vif */
2207
2208         if (ic_opmode == NL80211_IFTYPE_AP) {
2209                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2210                 sc->sc_flags |= SC_OP_TSF_RESET;
2211         }
2212
2213         /* Set the device opmode */
2214         sc->sc_ah->opmode = ic_opmode;
2215
2216         /*
2217          * Enable MIB interrupts when there are hardware phy counters.
2218          * Note we only do this (at the moment) for station mode.
2219          */
2220         if ((conf->type == NL80211_IFTYPE_STATION) ||
2221             (conf->type == NL80211_IFTYPE_ADHOC) ||
2222             (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2223                 sc->imask |= ATH9K_INT_MIB;
2224                 sc->imask |= ATH9K_INT_TSFOOR;
2225         }
2226
2227         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2228
2229         if (conf->type == NL80211_IFTYPE_AP    ||
2230             conf->type == NL80211_IFTYPE_ADHOC ||
2231             conf->type == NL80211_IFTYPE_MONITOR)
2232                 ath_start_ani(sc);
2233
2234 out:
2235         mutex_unlock(&sc->mutex);
2236         return ret;
2237 }
2238
2239 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2240                                    struct ieee80211_if_init_conf *conf)
2241 {
2242         struct ath_wiphy *aphy = hw->priv;
2243         struct ath_softc *sc = aphy->sc;
2244         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2245         int i;
2246
2247         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2248
2249         mutex_lock(&sc->mutex);
2250
2251         /* Stop ANI */
2252         del_timer_sync(&sc->ani.timer);
2253
2254         /* Reclaim beacon resources */
2255         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2256             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2257             (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2258                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2259                 ath_beacon_return(sc, avp);
2260         }
2261
2262         sc->sc_flags &= ~SC_OP_BEACONS;
2263
2264         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2265                 if (sc->beacon.bslot[i] == conf->vif) {
2266                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2267                                "slot\n", __func__);
2268                         sc->beacon.bslot[i] = NULL;
2269                         sc->beacon.bslot_aphy[i] = NULL;
2270                 }
2271         }
2272
2273         sc->nvifs--;
2274
2275         mutex_unlock(&sc->mutex);
2276 }
2277
2278 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2279 {
2280         struct ath_wiphy *aphy = hw->priv;
2281         struct ath_softc *sc = aphy->sc;
2282         struct ieee80211_conf *conf = &hw->conf;
2283         struct ath_hw *ah = sc->sc_ah;
2284         bool all_wiphys_idle = false, disable_radio = false;
2285
2286         mutex_lock(&sc->mutex);
2287
2288         /* Leave this as the first check */
2289         if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2290
2291                 spin_lock_bh(&sc->wiphy_lock);
2292                 all_wiphys_idle =  ath9k_all_wiphys_idle(sc);
2293                 spin_unlock_bh(&sc->wiphy_lock);
2294
2295                 if (conf->flags & IEEE80211_CONF_IDLE){
2296                         if (all_wiphys_idle)
2297                                 disable_radio = true;
2298                 }
2299                 else if (all_wiphys_idle) {
2300                         ath_radio_enable(sc);
2301                         DPRINTF(sc, ATH_DBG_CONFIG,
2302                                 "not-idle: enabling radio\n");
2303                 }
2304         }
2305
2306         if (changed & IEEE80211_CONF_CHANGE_PS) {
2307                 if (conf->flags & IEEE80211_CONF_PS) {
2308                         if (!(ah->caps.hw_caps &
2309                               ATH9K_HW_CAP_AUTOSLEEP)) {
2310                                 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2311                                         sc->imask |= ATH9K_INT_TIM_TIMER;
2312                                         ath9k_hw_set_interrupts(sc->sc_ah,
2313                                                         sc->imask);
2314                                 }
2315                                 ath9k_hw_setrxabort(sc->sc_ah, 1);
2316                         }
2317                         sc->ps_enabled = true;
2318                 } else {
2319                         sc->ps_enabled = false;
2320                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2321                         if (!(ah->caps.hw_caps &
2322                               ATH9K_HW_CAP_AUTOSLEEP)) {
2323                                 ath9k_hw_setrxabort(sc->sc_ah, 0);
2324                                 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2325                                                   SC_OP_WAIT_FOR_CAB |
2326                                                   SC_OP_WAIT_FOR_PSPOLL_DATA |
2327                                                   SC_OP_WAIT_FOR_TX_ACK);
2328                                 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2329                                         sc->imask &= ~ATH9K_INT_TIM_TIMER;
2330                                         ath9k_hw_set_interrupts(sc->sc_ah,
2331                                                         sc->imask);
2332                                 }
2333                         }
2334                 }
2335         }
2336
2337         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2338                 struct ieee80211_channel *curchan = hw->conf.channel;
2339                 int pos = curchan->hw_value;
2340
2341                 aphy->chan_idx = pos;
2342                 aphy->chan_is_ht = conf_is_ht(conf);
2343
2344                 if (aphy->state == ATH_WIPHY_SCAN ||
2345                     aphy->state == ATH_WIPHY_ACTIVE)
2346                         ath9k_wiphy_pause_all_forced(sc, aphy);
2347                 else {
2348                         /*
2349                          * Do not change operational channel based on a paused
2350                          * wiphy changes.
2351                          */
2352                         goto skip_chan_change;
2353                 }
2354
2355                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2356                         curchan->center_freq);
2357
2358                 /* XXX: remove me eventualy */
2359                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2360
2361                 ath_update_chainmask(sc, conf_is_ht(conf));
2362
2363                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2364                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2365                         mutex_unlock(&sc->mutex);
2366                         return -EINVAL;
2367                 }
2368         }
2369
2370 skip_chan_change:
2371         if (changed & IEEE80211_CONF_CHANGE_POWER)
2372                 sc->config.txpowlimit = 2 * conf->power_level;
2373
2374         if (disable_radio) {
2375                 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2376                 ath_radio_disable(sc);
2377         }
2378
2379         mutex_unlock(&sc->mutex);
2380
2381         return 0;
2382 }
2383
2384 #define SUPPORTED_FILTERS                       \
2385         (FIF_PROMISC_IN_BSS |                   \
2386         FIF_ALLMULTI |                          \
2387         FIF_CONTROL |                           \
2388         FIF_PSPOLL |                            \
2389         FIF_OTHER_BSS |                         \
2390         FIF_BCN_PRBRESP_PROMISC |               \
2391         FIF_FCSFAIL)
2392
2393 /* FIXME: sc->sc_full_reset ? */
2394 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2395                                    unsigned int changed_flags,
2396                                    unsigned int *total_flags,
2397                                    int mc_count,
2398                                    struct dev_mc_list *mclist)
2399 {
2400         struct ath_wiphy *aphy = hw->priv;
2401         struct ath_softc *sc = aphy->sc;
2402         u32 rfilt;
2403
2404         changed_flags &= SUPPORTED_FILTERS;
2405         *total_flags &= SUPPORTED_FILTERS;
2406
2407         sc->rx.rxfilter = *total_flags;
2408         ath9k_ps_wakeup(sc);
2409         rfilt = ath_calcrxfilter(sc);
2410         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2411         ath9k_ps_restore(sc);
2412
2413         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2414 }
2415
2416 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2417                              struct ieee80211_vif *vif,
2418                              enum sta_notify_cmd cmd,
2419                              struct ieee80211_sta *sta)
2420 {
2421         struct ath_wiphy *aphy = hw->priv;
2422         struct ath_softc *sc = aphy->sc;
2423
2424         switch (cmd) {
2425         case STA_NOTIFY_ADD:
2426                 ath_node_attach(sc, sta);
2427                 break;
2428         case STA_NOTIFY_REMOVE:
2429                 ath_node_detach(sc, sta);
2430                 break;
2431         default:
2432                 break;
2433         }
2434 }
2435
2436 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2437                          const struct ieee80211_tx_queue_params *params)
2438 {
2439         struct ath_wiphy *aphy = hw->priv;
2440         struct ath_softc *sc = aphy->sc;
2441         struct ath9k_tx_queue_info qi;
2442         int ret = 0, qnum;
2443
2444         if (queue >= WME_NUM_AC)
2445                 return 0;
2446
2447         mutex_lock(&sc->mutex);
2448
2449         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2450
2451         qi.tqi_aifs = params->aifs;
2452         qi.tqi_cwmin = params->cw_min;
2453         qi.tqi_cwmax = params->cw_max;
2454         qi.tqi_burstTime = params->txop;
2455         qnum = ath_get_hal_qnum(queue, sc);
2456
2457         DPRINTF(sc, ATH_DBG_CONFIG,
2458                 "Configure tx [queue/halq] [%d/%d],  "
2459                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2460                 queue, qnum, params->aifs, params->cw_min,
2461                 params->cw_max, params->txop);
2462
2463         ret = ath_txq_update(sc, qnum, &qi);
2464         if (ret)
2465                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2466
2467         mutex_unlock(&sc->mutex);
2468
2469         return ret;
2470 }
2471
2472 static int ath9k_set_key(struct ieee80211_hw *hw,
2473                          enum set_key_cmd cmd,
2474                          struct ieee80211_vif *vif,
2475                          struct ieee80211_sta *sta,
2476                          struct ieee80211_key_conf *key)
2477 {
2478         struct ath_wiphy *aphy = hw->priv;
2479         struct ath_softc *sc = aphy->sc;
2480         int ret = 0;
2481
2482         if (modparam_nohwcrypt)
2483                 return -ENOSPC;
2484
2485         mutex_lock(&sc->mutex);
2486         ath9k_ps_wakeup(sc);
2487         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
2488
2489         switch (cmd) {
2490         case SET_KEY:
2491                 ret = ath_key_config(sc, vif, sta, key);
2492                 if (ret >= 0) {
2493                         key->hw_key_idx = ret;
2494                         /* push IV and Michael MIC generation to stack */
2495                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2496                         if (key->alg == ALG_TKIP)
2497                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2498                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2499                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2500                         ret = 0;
2501                 }
2502                 break;
2503         case DISABLE_KEY:
2504                 ath_key_delete(sc, key);
2505                 break;
2506         default:
2507                 ret = -EINVAL;
2508         }
2509
2510         ath9k_ps_restore(sc);
2511         mutex_unlock(&sc->mutex);
2512
2513         return ret;
2514 }
2515
2516 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2517                                    struct ieee80211_vif *vif,
2518                                    struct ieee80211_bss_conf *bss_conf,
2519                                    u32 changed)
2520 {
2521         struct ath_wiphy *aphy = hw->priv;
2522         struct ath_softc *sc = aphy->sc;
2523         struct ath_hw *ah = sc->sc_ah;
2524         struct ath_vif *avp = (void *)vif->drv_priv;
2525         u32 rfilt = 0;
2526         int error, i;
2527
2528         mutex_lock(&sc->mutex);
2529
2530         /*
2531          * TODO: Need to decide which hw opmode to use for
2532          *       multi-interface cases
2533          * XXX: This belongs into add_interface!
2534          */
2535         if (vif->type == NL80211_IFTYPE_AP &&
2536             ah->opmode != NL80211_IFTYPE_AP) {
2537                 ah->opmode = NL80211_IFTYPE_STATION;
2538                 ath9k_hw_setopmode(ah);
2539                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2540                 sc->curaid = 0;
2541                 ath9k_hw_write_associd(sc);
2542                 /* Request full reset to get hw opmode changed properly */
2543                 sc->sc_flags |= SC_OP_FULL_RESET;
2544         }
2545
2546         if ((changed & BSS_CHANGED_BSSID) &&
2547             !is_zero_ether_addr(bss_conf->bssid)) {
2548                 switch (vif->type) {
2549                 case NL80211_IFTYPE_STATION:
2550                 case NL80211_IFTYPE_ADHOC:
2551                 case NL80211_IFTYPE_MESH_POINT:
2552                         /* Set BSSID */
2553                         memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2554                         memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2555                         sc->curaid = 0;
2556                         ath9k_hw_write_associd(sc);
2557
2558                         /* Set aggregation protection mode parameters */
2559                         sc->config.ath_aggr_prot = 0;
2560
2561                         DPRINTF(sc, ATH_DBG_CONFIG,
2562                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2563                                 rfilt, sc->curbssid, sc->curaid);
2564
2565                         /* need to reconfigure the beacon */
2566                         sc->sc_flags &= ~SC_OP_BEACONS ;
2567
2568                         break;
2569                 default:
2570                         break;
2571                 }
2572         }
2573
2574         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2575             (vif->type == NL80211_IFTYPE_AP) ||
2576             (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2577                 if ((changed & BSS_CHANGED_BEACON) ||
2578                     (changed & BSS_CHANGED_BEACON_ENABLED &&
2579                      bss_conf->enable_beacon)) {
2580                         /*
2581                          * Allocate and setup the beacon frame.
2582                          *
2583                          * Stop any previous beacon DMA.  This may be
2584                          * necessary, for example, when an ibss merge
2585                          * causes reconfiguration; we may be called
2586                          * with beacon transmission active.
2587                          */
2588                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2589
2590                         error = ath_beacon_alloc(aphy, vif);
2591                         if (!error)
2592                                 ath_beacon_config(sc, vif);
2593                 }
2594         }
2595
2596         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2597         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2598                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2599                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2600                                 ath9k_hw_keysetmac(sc->sc_ah,
2601                                                    (u16)i,
2602                                                    sc->curbssid);
2603         }
2604
2605         /* Only legacy IBSS for now */
2606         if (vif->type == NL80211_IFTYPE_ADHOC)
2607                 ath_update_chainmask(sc, 0);
2608
2609         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2610                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2611                         bss_conf->use_short_preamble);
2612                 if (bss_conf->use_short_preamble)
2613                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2614                 else
2615                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2616         }
2617
2618         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2619                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2620                         bss_conf->use_cts_prot);
2621                 if (bss_conf->use_cts_prot &&
2622                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2623                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2624                 else
2625                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2626         }
2627
2628         if (changed & BSS_CHANGED_ASSOC) {
2629                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2630                         bss_conf->assoc);
2631                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2632         }
2633
2634         /*
2635          * The HW TSF has to be reset when the beacon interval changes.
2636          * We set the flag here, and ath_beacon_config_ap() would take this
2637          * into account when it gets called through the subsequent
2638          * config_interface() call - with IFCC_BEACON in the changed field.
2639          */
2640
2641         if (changed & BSS_CHANGED_BEACON_INT) {
2642                 sc->sc_flags |= SC_OP_TSF_RESET;
2643                 sc->beacon_interval = bss_conf->beacon_int;
2644         }
2645
2646         mutex_unlock(&sc->mutex);
2647 }
2648
2649 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2650 {
2651         u64 tsf;
2652         struct ath_wiphy *aphy = hw->priv;
2653         struct ath_softc *sc = aphy->sc;
2654
2655         mutex_lock(&sc->mutex);
2656         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2657         mutex_unlock(&sc->mutex);
2658
2659         return tsf;
2660 }
2661
2662 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2663 {
2664         struct ath_wiphy *aphy = hw->priv;
2665         struct ath_softc *sc = aphy->sc;
2666
2667         mutex_lock(&sc->mutex);
2668         ath9k_hw_settsf64(sc->sc_ah, tsf);
2669         mutex_unlock(&sc->mutex);
2670 }
2671
2672 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2673 {
2674         struct ath_wiphy *aphy = hw->priv;
2675         struct ath_softc *sc = aphy->sc;
2676
2677         mutex_lock(&sc->mutex);
2678         ath9k_hw_reset_tsf(sc->sc_ah);
2679         mutex_unlock(&sc->mutex);
2680 }
2681
2682 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2683                               enum ieee80211_ampdu_mlme_action action,
2684                               struct ieee80211_sta *sta,
2685                               u16 tid, u16 *ssn)
2686 {
2687         struct ath_wiphy *aphy = hw->priv;
2688         struct ath_softc *sc = aphy->sc;
2689         int ret = 0;
2690
2691         switch (action) {
2692         case IEEE80211_AMPDU_RX_START:
2693                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2694                         ret = -ENOTSUPP;
2695                 break;
2696         case IEEE80211_AMPDU_RX_STOP:
2697                 break;
2698         case IEEE80211_AMPDU_TX_START:
2699                 ath_tx_aggr_start(sc, sta, tid, ssn);
2700                 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2701                 break;
2702         case IEEE80211_AMPDU_TX_STOP:
2703                 ath_tx_aggr_stop(sc, sta, tid);
2704                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2705                 break;
2706         case IEEE80211_AMPDU_TX_OPERATIONAL:
2707                 ath_tx_aggr_resume(sc, sta, tid);
2708                 break;
2709         default:
2710                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2711         }
2712
2713         return ret;
2714 }
2715
2716 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2717 {
2718         struct ath_wiphy *aphy = hw->priv;
2719         struct ath_softc *sc = aphy->sc;
2720
2721         if (ath9k_wiphy_scanning(sc)) {
2722                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2723                        "same time\n");
2724                 /*
2725                  * Do not allow the concurrent scanning state for now. This
2726                  * could be improved with scanning control moved into ath9k.
2727                  */
2728                 return;
2729         }
2730
2731         aphy->state = ATH_WIPHY_SCAN;
2732         ath9k_wiphy_pause_all_forced(sc, aphy);
2733
2734         spin_lock_bh(&sc->ani_lock);
2735         sc->sc_flags |= SC_OP_SCANNING;
2736         spin_unlock_bh(&sc->ani_lock);
2737 }
2738
2739 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2740 {
2741         struct ath_wiphy *aphy = hw->priv;
2742         struct ath_softc *sc = aphy->sc;
2743
2744         spin_lock_bh(&sc->ani_lock);
2745         aphy->state = ATH_WIPHY_ACTIVE;
2746         sc->sc_flags &= ~SC_OP_SCANNING;
2747         sc->sc_flags |= SC_OP_FULL_RESET;
2748         spin_unlock_bh(&sc->ani_lock);
2749 }
2750
2751 struct ieee80211_ops ath9k_ops = {
2752         .tx                 = ath9k_tx,
2753         .start              = ath9k_start,
2754         .stop               = ath9k_stop,
2755         .add_interface      = ath9k_add_interface,
2756         .remove_interface   = ath9k_remove_interface,
2757         .config             = ath9k_config,
2758         .configure_filter   = ath9k_configure_filter,
2759         .sta_notify         = ath9k_sta_notify,
2760         .conf_tx            = ath9k_conf_tx,
2761         .bss_info_changed   = ath9k_bss_info_changed,
2762         .set_key            = ath9k_set_key,
2763         .get_tsf            = ath9k_get_tsf,
2764         .set_tsf            = ath9k_set_tsf,
2765         .reset_tsf          = ath9k_reset_tsf,
2766         .ampdu_action       = ath9k_ampdu_action,
2767         .sw_scan_start      = ath9k_sw_scan_start,
2768         .sw_scan_complete   = ath9k_sw_scan_complete,
2769         .rfkill_poll        = ath9k_rfkill_poll_state,
2770 };
2771
2772 static struct {
2773         u32 version;
2774         const char * name;
2775 } ath_mac_bb_names[] = {
2776         { AR_SREV_VERSION_5416_PCI,     "5416" },
2777         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2778         { AR_SREV_VERSION_9100,         "9100" },
2779         { AR_SREV_VERSION_9160,         "9160" },
2780         { AR_SREV_VERSION_9280,         "9280" },
2781         { AR_SREV_VERSION_9285,         "9285" },
2782         { AR_SREV_VERSION_9287,         "9287" }
2783 };
2784
2785 static struct {
2786         u16 version;
2787         const char * name;
2788 } ath_rf_names[] = {
2789         { 0,                            "5133" },
2790         { AR_RAD5133_SREV_MAJOR,        "5133" },
2791         { AR_RAD5122_SREV_MAJOR,        "5122" },
2792         { AR_RAD2133_SREV_MAJOR,        "2133" },
2793         { AR_RAD2122_SREV_MAJOR,        "2122" }
2794 };
2795
2796 /*
2797  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2798  */
2799 const char *
2800 ath_mac_bb_name(u32 mac_bb_version)
2801 {
2802         int i;
2803
2804         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2805                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2806                         return ath_mac_bb_names[i].name;
2807                 }
2808         }
2809
2810         return "????";
2811 }
2812
2813 /*
2814  * Return the RF name. "????" is returned if the RF is unknown.
2815  */
2816 const char *
2817 ath_rf_name(u16 rf_version)
2818 {
2819         int i;
2820
2821         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2822                 if (ath_rf_names[i].version == rf_version) {
2823                         return ath_rf_names[i].name;
2824                 }
2825         }
2826
2827         return "????";
2828 }
2829
2830 static int __init ath9k_init(void)
2831 {
2832         int error;
2833
2834         /* Register rate control algorithm */
2835         error = ath_rate_control_register();
2836         if (error != 0) {
2837                 printk(KERN_ERR
2838                         "ath9k: Unable to register rate control "
2839                         "algorithm: %d\n",
2840                         error);
2841                 goto err_out;
2842         }
2843
2844         error = ath9k_debug_create_root();
2845         if (error) {
2846                 printk(KERN_ERR
2847                         "ath9k: Unable to create debugfs root: %d\n",
2848                         error);
2849                 goto err_rate_unregister;
2850         }
2851
2852         error = ath_pci_init();
2853         if (error < 0) {
2854                 printk(KERN_ERR
2855                         "ath9k: No PCI devices found, driver not installed.\n");
2856                 error = -ENODEV;
2857                 goto err_remove_root;
2858         }
2859
2860         error = ath_ahb_init();
2861         if (error < 0) {
2862                 error = -ENODEV;
2863                 goto err_pci_exit;
2864         }
2865
2866         return 0;
2867
2868  err_pci_exit:
2869         ath_pci_exit();
2870
2871  err_remove_root:
2872         ath9k_debug_remove_root();
2873  err_rate_unregister:
2874         ath_rate_control_unregister();
2875  err_out:
2876         return error;
2877 }
2878 module_init(ath9k_init);
2879
2880 static void __exit ath9k_exit(void)
2881 {
2882         ath_ahb_exit();
2883         ath_pci_exit();
2884         ath9k_debug_remove_root();
2885         ath_rate_control_unregister();
2886         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2887 }
2888 module_exit(ath9k_exit);