2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
40 /********************/
41 /* Helper Functions */
42 /********************/
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
63 return ath9k_hw_mac_usec(ah, clks);
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
84 return ath9k_hw_mac_clks(ah, usecs);
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
97 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
99 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
103 iowrite32(val, ah->ah_sc->mem + reg_offset);
106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
109 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
111 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
115 val = ioread32(ah->ah_sc->mem + reg_offset);
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
123 BUG_ON(timeout < AH_TIME_QUANTUM);
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
129 udelay(AH_TIME_QUANTUM);
132 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
144 for (i = 0, retval = 0; i < n; i++) {
145 retval = (retval << 1) | (val & 1);
151 bool ath9k_get_channel_edges(struct ath_hw *ah,
155 struct ath9k_hw_capabilities *pCap = &ah->caps;
157 if (flags & CHANNEL_5GHZ) {
158 *low = pCap->low_5ghz_chan;
159 *high = pCap->high_5ghz_chan;
162 if ((flags & CHANNEL_2GHZ)) {
163 *low = pCap->low_2ghz_chan;
164 *high = pCap->high_2ghz_chan;
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 const struct ath_rate_table *rates,
172 u32 frameLen, u16 rateix,
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
178 kbps = rates->info[rateix].ratekbps;
183 switch (rates->info[rateix].phy) {
184 case WLAN_RC_PHY_CCK:
185 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 if (shortPreamble && rates->info[rateix].short_preamble)
188 numBits = frameLen << 3;
189 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
191 case WLAN_RC_PHY_OFDM:
192 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199 } else if (ah->curchan &&
200 IS_CHAN_HALF_RATE(ah->curchan)) {
201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME_HALF +
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212 + (numSymbols * OFDM_SYMBOL_TIME);
216 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217 "Unknown phy %u (rate ix %u)\n",
218 rates->info[rateix].phy, rateix);
226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
232 if (!IS_CHAN_HT40(chan)) {
233 centers->ctl_center = centers->ext_center =
234 centers->synth_center = chan->channel;
238 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240 centers->synth_center =
241 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
244 centers->synth_center =
245 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
249 centers->ctl_center =
250 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 centers->ext_center =
252 centers->synth_center + (extoff *
253 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254 HT40_CHANNEL_CENTER_SHIFT : 15));
261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
265 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macVersion =
270 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
274 if (!AR_SREV_9100(ah))
275 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
277 ah->hw_version.macRev = val & AR_SREV_REVISION;
279 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280 ah->is_pciexpress = true;
284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
289 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
291 for (i = 0; i < 8; i++)
292 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
296 return ath9k_hw_reverse_bits(val, 8);
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
305 if (AR_SREV_9100(ah))
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
323 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
325 u32 patternData[4] = { 0x55555555,
331 for (i = 0; i < 2; i++) {
332 u32 addr = regAddr[i];
335 regHold[i] = REG_READ(ah, addr);
336 for (j = 0; j < 0x100; j++) {
337 wrData = (j << 16) | j;
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (rdData != wrData) {
341 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344 addr, wrData, rdData);
348 for (j = 0; j < 4; j++) {
349 wrData = patternData[j];
350 REG_WRITE(ah, addr, wrData);
351 rdData = REG_READ(ah, addr);
352 if (wrData != rdData) {
353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354 "address test failed "
355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356 addr, wrData, rdData);
360 REG_WRITE(ah, regAddr[i], regHold[i]);
367 static const char *ath9k_hw_devname(u16 devid)
370 case AR5416_DEVID_PCI:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR5416_AR9100_DEVID:
377 return "Atheros 9100";
378 case AR9280_DEVID_PCI:
379 case AR9280_DEVID_PCIE:
380 return "Atheros 9280";
381 case AR9285_DEVID_PCIE:
382 return "Atheros 9285";
383 case AR5416_DEVID_AR9287_PCI:
384 case AR5416_DEVID_AR9287_PCIE:
385 return "Atheros 9287";
391 static void ath9k_hw_set_defaults(struct ath_hw *ah)
395 ah->config.dma_beacon_response_time = 2;
396 ah->config.sw_beacon_response_time = 10;
397 ah->config.additional_swba_backoff = 0;
398 ah->config.ack_6mb = 0x0;
399 ah->config.cwm_ignore_extcca = 0;
400 ah->config.pcie_powersave_enable = 0;
401 ah->config.pcie_clock_req = 0;
402 ah->config.pcie_waen = 0;
403 ah->config.analog_shiftreg = 1;
404 ah->config.ht_enable = 1;
405 ah->config.ofdm_trig_low = 200;
406 ah->config.ofdm_trig_high = 500;
407 ah->config.cck_trig_high = 200;
408 ah->config.cck_trig_low = 100;
409 ah->config.enable_ani = 1;
410 ah->config.diversity_control = 0;
411 ah->config.antenna_switch_swap = 0;
413 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
414 ah->config.spurchans[i][0] = AR_NO_SPUR;
415 ah->config.spurchans[i][1] = AR_NO_SPUR;
418 ah->config.intr_mitigation = true;
421 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
422 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
423 * This means we use it for all AR5416 devices, and the few
424 * minor PCI AR9280 devices out there.
426 * Serialization is required because these devices do not handle
427 * well the case of two concurrent reads/writes due to the latency
428 * involved. During one read/write another read/write can be issued
429 * on another CPU while the previous read/write may still be working
430 * on our hardware, if we hit this case the hardware poops in a loop.
431 * We prevent this by serializing reads and writes.
433 * This issue is not present on PCI-Express devices or pre-AR5416
434 * devices (legacy, 802.11abg).
436 if (num_possible_cpus() > 1)
437 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
440 static void ath9k_hw_newstate(struct ath_hw *ah)
442 ah->hw_version.magic = AR5416_MAGIC;
443 ah->regulatory.country_code = CTRY_DEFAULT;
444 ah->hw_version.subvendorid = 0;
447 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
448 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
449 if (!AR_SREV_9100(ah))
450 ah->ah_flags = AH_USE_EEPROM;
452 ah->regulatory.power_limit = MAX_RATE_POWER;
453 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
455 ah->diversity_control = ah->config.diversity_control;
456 ah->antenna_switch_swap =
457 ah->config.antenna_switch_swap;
458 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
459 ah->beacon_interval = 100;
460 ah->enable_32kHz_clock = DONT_USE_32KHZ;
461 ah->slottime = (u32) -1;
462 ah->acktimeout = (u32) -1;
463 ah->ctstimeout = (u32) -1;
464 ah->globaltxtimeout = (u32) -1;
466 ah->gbeacon_rate = 0;
468 ah->power_mode = ATH9K_PM_UNDEFINED;
471 static int ath9k_hw_rfattach(struct ath_hw *ah)
473 bool rfStatus = false;
476 rfStatus = ath9k_hw_init_rf(ah, &ecode);
478 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
479 "RF setup failed, status: %u\n", ecode);
486 static int ath9k_hw_rf_claim(struct ath_hw *ah)
490 REG_WRITE(ah, AR_PHY(0), 0x00000007);
492 val = ath9k_hw_get_radiorev(ah);
493 switch (val & AR_RADIO_SREV_MAJOR) {
495 val = AR_RAD5133_SREV_MAJOR;
497 case AR_RAD5133_SREV_MAJOR:
498 case AR_RAD5122_SREV_MAJOR:
499 case AR_RAD2133_SREV_MAJOR:
500 case AR_RAD2122_SREV_MAJOR:
503 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
504 "Radio Chip Rev 0x%02X not supported\n",
505 val & AR_RADIO_SREV_MAJOR);
509 ah->hw_version.analog5GhzRev = val;
514 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
521 for (i = 0; i < 3; i++) {
522 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
524 ah->macaddr[2 * i] = eeval >> 8;
525 ah->macaddr[2 * i + 1] = eeval & 0xff;
527 if (sum == 0 || sum == 0xffff * 3)
528 return -EADDRNOTAVAIL;
533 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
537 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
538 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
540 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
541 INIT_INI_ARRAY(&ah->iniModesRxGain,
542 ar9280Modes_backoff_13db_rxgain_9280_2,
543 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
544 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
545 INIT_INI_ARRAY(&ah->iniModesRxGain,
546 ar9280Modes_backoff_23db_rxgain_9280_2,
547 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
549 INIT_INI_ARRAY(&ah->iniModesRxGain,
550 ar9280Modes_original_rxgain_9280_2,
551 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
553 INIT_INI_ARRAY(&ah->iniModesRxGain,
554 ar9280Modes_original_rxgain_9280_2,
555 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
559 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
563 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
564 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
566 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
567 INIT_INI_ARRAY(&ah->iniModesTxGain,
568 ar9280Modes_high_power_tx_gain_9280_2,
569 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
571 INIT_INI_ARRAY(&ah->iniModesTxGain,
572 ar9280Modes_original_tx_gain_9280_2,
573 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
575 INIT_INI_ARRAY(&ah->iniModesTxGain,
576 ar9280Modes_original_tx_gain_9280_2,
577 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
581 static int ath9k_hw_post_attach(struct ath_hw *ah)
585 if (!ath9k_hw_chip_test(ah))
588 ecode = ath9k_hw_rf_claim(ah);
592 ecode = ath9k_hw_eeprom_attach(ah);
596 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
597 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
599 ecode = ath9k_hw_rfattach(ah);
603 if (!AR_SREV_9100(ah)) {
604 ath9k_hw_ani_setup(ah);
605 ath9k_hw_ani_attach(ah);
611 static bool ath9k_hw_devid_supported(u16 devid)
614 case AR5416_DEVID_PCI:
615 case AR5416_DEVID_PCIE:
616 case AR5416_AR9100_DEVID:
617 case AR9160_DEVID_PCI:
618 case AR9280_DEVID_PCI:
619 case AR9280_DEVID_PCIE:
620 case AR9285_DEVID_PCIE:
621 case AR5416_DEVID_AR9287_PCI:
622 case AR5416_DEVID_AR9287_PCIE:
630 int ath9k_hw_attach(struct ath_hw *ah, struct ath_softc *sc)
635 if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
640 ath9k_hw_newstate(ah);
641 ath9k_hw_set_defaults(ah);
643 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
644 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
649 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
650 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
655 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
656 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
657 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
658 ah->config.serialize_regmode =
661 ah->config.serialize_regmode =
666 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
667 ah->config.serialize_regmode);
669 switch (ah->hw_version.macVersion) {
670 case AR_SREV_VERSION_5416_PCI:
671 case AR_SREV_VERSION_5416_PCIE:
672 case AR_SREV_VERSION_9160:
673 case AR_SREV_VERSION_9100:
674 case AR_SREV_VERSION_9280:
675 case AR_SREV_VERSION_9285:
676 case AR_SREV_VERSION_9287:
679 DPRINTF(sc, ATH_DBG_FATAL,
680 "Mac Chip Rev 0x%02x.%x is not supported by "
681 "this driver\n", ah->hw_version.macVersion,
682 ah->hw_version.macRev);
687 if (AR_SREV_9100(ah)) {
688 ah->iq_caldata.calData = &iq_cal_multi_sample;
689 ah->supp_cals = IQ_MISMATCH_CAL;
690 ah->is_pciexpress = false;
692 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
694 if (AR_SREV_9160_10_OR_LATER(ah)) {
695 if (AR_SREV_9280_10_OR_LATER(ah)) {
696 ah->iq_caldata.calData = &iq_cal_single_sample;
697 ah->adcgain_caldata.calData =
698 &adc_gain_cal_single_sample;
699 ah->adcdc_caldata.calData =
700 &adc_dc_cal_single_sample;
701 ah->adcdc_calinitdata.calData =
704 ah->iq_caldata.calData = &iq_cal_multi_sample;
705 ah->adcgain_caldata.calData =
706 &adc_gain_cal_multi_sample;
707 ah->adcdc_caldata.calData =
708 &adc_dc_cal_multi_sample;
709 ah->adcdc_calinitdata.calData =
712 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
715 ah->ani_function = ATH9K_ANI_ALL;
716 if (AR_SREV_9280_10_OR_LATER(ah))
717 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
718 if (AR_SREV_9287_11_OR_LATER(ah)) {
719 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
720 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
721 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
722 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
723 if (ah->config.pcie_clock_req)
724 INIT_INI_ARRAY(&ah->iniPcieSerdes,
725 ar9287PciePhy_clkreq_off_L1_9287_1_1,
726 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
728 INIT_INI_ARRAY(&ah->iniPcieSerdes,
729 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
730 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
732 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
733 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
734 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
735 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
736 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
738 if (ah->config.pcie_clock_req)
739 INIT_INI_ARRAY(&ah->iniPcieSerdes,
740 ar9287PciePhy_clkreq_off_L1_9287_1_0,
741 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
743 INIT_INI_ARRAY(&ah->iniPcieSerdes,
744 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
745 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
747 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
750 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
751 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
752 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
753 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
755 if (ah->config.pcie_clock_req) {
756 INIT_INI_ARRAY(&ah->iniPcieSerdes,
757 ar9285PciePhy_clkreq_off_L1_9285_1_2,
758 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
760 INIT_INI_ARRAY(&ah->iniPcieSerdes,
761 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
762 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
765 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
766 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
767 ARRAY_SIZE(ar9285Modes_9285), 6);
768 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
769 ARRAY_SIZE(ar9285Common_9285), 2);
771 if (ah->config.pcie_clock_req) {
772 INIT_INI_ARRAY(&ah->iniPcieSerdes,
773 ar9285PciePhy_clkreq_off_L1_9285,
774 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
776 INIT_INI_ARRAY(&ah->iniPcieSerdes,
777 ar9285PciePhy_clkreq_always_on_L1_9285,
778 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
780 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
781 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
782 ARRAY_SIZE(ar9280Modes_9280_2), 6);
783 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
784 ARRAY_SIZE(ar9280Common_9280_2), 2);
786 if (ah->config.pcie_clock_req) {
787 INIT_INI_ARRAY(&ah->iniPcieSerdes,
788 ar9280PciePhy_clkreq_off_L1_9280,
789 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
791 INIT_INI_ARRAY(&ah->iniPcieSerdes,
792 ar9280PciePhy_clkreq_always_on_L1_9280,
793 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
795 INIT_INI_ARRAY(&ah->iniModesAdditional,
796 ar9280Modes_fast_clock_9280_2,
797 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
798 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
799 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
800 ARRAY_SIZE(ar9280Modes_9280), 6);
801 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
802 ARRAY_SIZE(ar9280Common_9280), 2);
803 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
804 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
805 ARRAY_SIZE(ar5416Modes_9160), 6);
806 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
807 ARRAY_SIZE(ar5416Common_9160), 2);
808 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
809 ARRAY_SIZE(ar5416Bank0_9160), 2);
810 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
811 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
812 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
813 ARRAY_SIZE(ar5416Bank1_9160), 2);
814 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
815 ARRAY_SIZE(ar5416Bank2_9160), 2);
816 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
817 ARRAY_SIZE(ar5416Bank3_9160), 3);
818 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
819 ARRAY_SIZE(ar5416Bank6_9160), 3);
820 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
821 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
822 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
823 ARRAY_SIZE(ar5416Bank7_9160), 2);
824 if (AR_SREV_9160_11(ah)) {
825 INIT_INI_ARRAY(&ah->iniAddac,
827 ARRAY_SIZE(ar5416Addac_91601_1), 2);
829 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
830 ARRAY_SIZE(ar5416Addac_9160), 2);
832 } else if (AR_SREV_9100_OR_LATER(ah)) {
833 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
834 ARRAY_SIZE(ar5416Modes_9100), 6);
835 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
836 ARRAY_SIZE(ar5416Common_9100), 2);
837 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
838 ARRAY_SIZE(ar5416Bank0_9100), 2);
839 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
840 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
841 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
842 ARRAY_SIZE(ar5416Bank1_9100), 2);
843 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
844 ARRAY_SIZE(ar5416Bank2_9100), 2);
845 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
846 ARRAY_SIZE(ar5416Bank3_9100), 3);
847 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
848 ARRAY_SIZE(ar5416Bank6_9100), 3);
849 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
850 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
851 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
852 ARRAY_SIZE(ar5416Bank7_9100), 2);
853 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
854 ARRAY_SIZE(ar5416Addac_9100), 2);
856 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
857 ARRAY_SIZE(ar5416Modes), 6);
858 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
859 ARRAY_SIZE(ar5416Common), 2);
860 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
861 ARRAY_SIZE(ar5416Bank0), 2);
862 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
863 ARRAY_SIZE(ar5416BB_RfGain), 3);
864 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
865 ARRAY_SIZE(ar5416Bank1), 2);
866 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
867 ARRAY_SIZE(ar5416Bank2), 2);
868 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
869 ARRAY_SIZE(ar5416Bank3), 3);
870 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
871 ARRAY_SIZE(ar5416Bank6), 3);
872 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
873 ARRAY_SIZE(ar5416Bank6TPC), 3);
874 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
875 ARRAY_SIZE(ar5416Bank7), 2);
876 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
877 ARRAY_SIZE(ar5416Addac), 2);
880 if (ah->is_pciexpress)
881 ath9k_hw_configpcipowersave(ah, 0);
883 ath9k_hw_disablepcie(ah);
885 r = ath9k_hw_post_attach(ah);
889 if (AR_SREV_9287_11(ah))
890 INIT_INI_ARRAY(&ah->iniModesRxGain,
891 ar9287Modes_rx_gain_9287_1_1,
892 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
893 else if (AR_SREV_9287_10(ah))
894 INIT_INI_ARRAY(&ah->iniModesRxGain,
895 ar9287Modes_rx_gain_9287_1_0,
896 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
897 else if (AR_SREV_9280_20(ah))
898 ath9k_hw_init_rxgain_ini(ah);
900 if (AR_SREV_9287_11(ah)) {
901 INIT_INI_ARRAY(&ah->iniModesTxGain,
902 ar9287Modes_tx_gain_9287_1_1,
903 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
904 } else if (AR_SREV_9287_10(ah)) {
905 INIT_INI_ARRAY(&ah->iniModesTxGain,
906 ar9287Modes_tx_gain_9287_1_0,
907 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
908 } else if (AR_SREV_9280_20(ah)) {
909 ath9k_hw_init_txgain_ini(ah);
910 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
911 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
914 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
915 INIT_INI_ARRAY(&ah->iniModesTxGain,
916 ar9285Modes_high_power_tx_gain_9285_1_2,
917 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
919 INIT_INI_ARRAY(&ah->iniModesTxGain,
920 ar9285Modes_original_tx_gain_9285_1_2,
921 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
926 ath9k_hw_fill_cap_info(ah);
928 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
929 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
932 for (i = 0; i < ah->iniModes.ia_rows; i++) {
933 u32 reg = INI_RA(&ah->iniModes, i, 0);
935 for (j = 1; j < ah->iniModes.ia_columns; j++) {
936 u32 val = INI_RA(&ah->iniModes, i, j);
938 INI_RA(&ah->iniModes, i, j) =
939 ath9k_hw_ini_fixup(ah,
946 r = ath9k_hw_init_macaddr(ah);
948 DPRINTF(sc, ATH_DBG_FATAL,
949 "Failed to initialize MAC address\n");
953 if (AR_SREV_9285(ah))
954 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
956 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
958 ath9k_init_nfcal_hist_buffer(ah);
966 static void ath9k_hw_init_bb(struct ath_hw *ah,
967 struct ath9k_channel *chan)
971 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
973 synthDelay = (4 * synthDelay) / 22;
977 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
979 udelay(synthDelay + BASE_ACTIVATE_DELAY);
982 static void ath9k_hw_init_qos(struct ath_hw *ah)
984 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
985 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
987 REG_WRITE(ah, AR_QOS_NO_ACK,
988 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
989 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
990 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
992 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
993 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
994 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
995 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
996 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
999 static void ath9k_hw_init_pll(struct ath_hw *ah,
1000 struct ath9k_channel *chan)
1004 if (AR_SREV_9100(ah)) {
1005 if (chan && IS_CHAN_5GHZ(chan))
1010 if (AR_SREV_9280_10_OR_LATER(ah)) {
1011 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1013 if (chan && IS_CHAN_HALF_RATE(chan))
1014 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1015 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1016 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1018 if (chan && IS_CHAN_5GHZ(chan)) {
1019 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1022 if (AR_SREV_9280_20(ah)) {
1023 if (((chan->channel % 20) == 0)
1024 || ((chan->channel % 10) == 0))
1030 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1033 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1035 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1037 if (chan && IS_CHAN_HALF_RATE(chan))
1038 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1039 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1040 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1042 if (chan && IS_CHAN_5GHZ(chan))
1043 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1045 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1047 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1049 if (chan && IS_CHAN_HALF_RATE(chan))
1050 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1051 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1052 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1054 if (chan && IS_CHAN_5GHZ(chan))
1055 pll |= SM(0xa, AR_RTC_PLL_DIV);
1057 pll |= SM(0xb, AR_RTC_PLL_DIV);
1060 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1062 udelay(RTC_PLL_SETTLE_DELAY);
1064 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1067 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1069 int rx_chainmask, tx_chainmask;
1071 rx_chainmask = ah->rxchainmask;
1072 tx_chainmask = ah->txchainmask;
1074 switch (rx_chainmask) {
1076 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1077 AR_PHY_SWAP_ALT_CHAIN);
1079 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1080 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1081 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1087 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1088 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1094 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1095 if (tx_chainmask == 0x5) {
1096 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1097 AR_PHY_SWAP_ALT_CHAIN);
1099 if (AR_SREV_9100(ah))
1100 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1101 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1104 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1105 enum nl80211_iftype opmode)
1107 ah->mask_reg = AR_IMR_TXERR |
1113 if (ah->config.intr_mitigation)
1114 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1116 ah->mask_reg |= AR_IMR_RXOK;
1118 ah->mask_reg |= AR_IMR_TXOK;
1120 if (opmode == NL80211_IFTYPE_AP)
1121 ah->mask_reg |= AR_IMR_MIB;
1123 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1124 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1126 if (!AR_SREV_9100(ah)) {
1127 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1128 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1129 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1133 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1135 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1136 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1137 ah->acktimeout = (u32) -1;
1140 REG_RMW_FIELD(ah, AR_TIME_OUT,
1141 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1142 ah->acktimeout = us;
1147 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1149 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1150 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1151 ah->ctstimeout = (u32) -1;
1154 REG_RMW_FIELD(ah, AR_TIME_OUT,
1155 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1156 ah->ctstimeout = us;
1161 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1164 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1165 "bad global tx timeout %u\n", tu);
1166 ah->globaltxtimeout = (u32) -1;
1169 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1170 ah->globaltxtimeout = tu;
1175 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1177 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1180 if (ah->misc_mode != 0)
1181 REG_WRITE(ah, AR_PCU_MISC,
1182 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1183 if (ah->slottime != (u32) -1)
1184 ath9k_hw_setslottime(ah, ah->slottime);
1185 if (ah->acktimeout != (u32) -1)
1186 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1187 if (ah->ctstimeout != (u32) -1)
1188 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1189 if (ah->globaltxtimeout != (u32) -1)
1190 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1193 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1195 return vendorid == ATHEROS_VENDOR_ID ?
1196 ath9k_hw_devname(devid) : NULL;
1199 void ath9k_hw_detach(struct ath_hw *ah)
1201 if (!AR_SREV_9100(ah))
1202 ath9k_hw_ani_detach(ah);
1204 ath9k_hw_rfdetach(ah);
1205 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1213 static void ath9k_hw_override_ini(struct ath_hw *ah,
1214 struct ath9k_channel *chan)
1217 * Set the RX_ABORT and RX_DIS and clear if off only after
1218 * RXE is set for MAC. This prevents frames with corrupted
1219 * descriptor status.
1221 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1224 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1225 AR_SREV_9280_10_OR_LATER(ah))
1228 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1231 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1232 struct ar5416_eeprom_def *pEepData,
1235 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1237 switch (ah->hw_version.devid) {
1238 case AR9280_DEVID_PCI:
1239 if (reg == 0x7894) {
1240 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1241 "ini VAL: %x EEPROM: %x\n", value,
1242 (pBase->version & 0xff));
1244 if ((pBase->version & 0xff) > 0x0a) {
1245 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1248 value &= ~AR_AN_TOP2_PWDCLKIND;
1249 value |= AR_AN_TOP2_PWDCLKIND &
1250 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1252 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1253 "PWDCLKIND Earlier Rev\n");
1256 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1257 "final ini VAL: %x\n", value);
1265 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1266 struct ar5416_eeprom_def *pEepData,
1269 if (ah->eep_map == EEP_MAP_4KBITS)
1272 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1275 static void ath9k_olc_init(struct ath_hw *ah)
1279 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1280 ah->originalGain[i] =
1281 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1286 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1287 struct ath9k_channel *chan)
1289 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1291 if (IS_CHAN_B(chan))
1293 else if (IS_CHAN_G(chan))
1301 static int ath9k_hw_process_ini(struct ath_hw *ah,
1302 struct ath9k_channel *chan,
1303 enum ath9k_ht_macmode macmode)
1305 int i, regWrites = 0;
1306 struct ieee80211_channel *channel = chan->chan;
1307 u32 modesIndex, freqIndex;
1309 switch (chan->chanmode) {
1311 case CHANNEL_A_HT20:
1315 case CHANNEL_A_HT40PLUS:
1316 case CHANNEL_A_HT40MINUS:
1321 case CHANNEL_G_HT20:
1326 case CHANNEL_G_HT40PLUS:
1327 case CHANNEL_G_HT40MINUS:
1336 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1337 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1338 ah->eep_ops->set_addac(ah, chan);
1340 if (AR_SREV_5416_22_OR_LATER(ah)) {
1341 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1343 struct ar5416IniArray temp;
1345 sizeof(u32) * ah->iniAddac.ia_rows *
1346 ah->iniAddac.ia_columns;
1348 memcpy(ah->addac5416_21,
1349 ah->iniAddac.ia_array, addacSize);
1351 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1353 temp.ia_array = ah->addac5416_21;
1354 temp.ia_columns = ah->iniAddac.ia_columns;
1355 temp.ia_rows = ah->iniAddac.ia_rows;
1356 REG_WRITE_ARRAY(&temp, 1, regWrites);
1359 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1361 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1362 u32 reg = INI_RA(&ah->iniModes, i, 0);
1363 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1365 REG_WRITE(ah, reg, val);
1367 if (reg >= 0x7800 && reg < 0x78a0
1368 && ah->config.analog_shiftreg) {
1372 DO_DELAY(regWrites);
1375 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1376 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1378 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1379 AR_SREV_9287_10_OR_LATER(ah))
1380 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1382 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1383 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1384 u32 val = INI_RA(&ah->iniCommon, i, 1);
1386 REG_WRITE(ah, reg, val);
1388 if (reg >= 0x7800 && reg < 0x78a0
1389 && ah->config.analog_shiftreg) {
1393 DO_DELAY(regWrites);
1396 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1398 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1399 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1403 ath9k_hw_override_ini(ah, chan);
1404 ath9k_hw_set_regs(ah, chan, macmode);
1405 ath9k_hw_init_chain_masks(ah);
1407 if (OLC_FOR_AR9280_20_LATER)
1410 ah->eep_ops->set_txpower(ah, chan,
1411 ath9k_regd_get_ctl(&ah->regulatory, chan),
1412 channel->max_antenna_gain * 2,
1413 channel->max_power * 2,
1414 min((u32) MAX_RATE_POWER,
1415 (u32) ah->regulatory.power_limit));
1417 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1418 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1419 "ar5416SetRfRegs failed\n");
1426 /****************************************/
1427 /* Reset and Channel Switching Routines */
1428 /****************************************/
1430 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1437 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1438 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1440 if (!AR_SREV_9280_10_OR_LATER(ah))
1441 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1442 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1444 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1445 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1447 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1450 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1452 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1455 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1459 regval = REG_READ(ah, AR_AHB_MODE);
1460 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1462 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1463 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1465 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1467 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1468 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1470 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1472 if (AR_SREV_9285(ah)) {
1473 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1474 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1476 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1477 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1481 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1485 val = REG_READ(ah, AR_STA_ID1);
1486 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1488 case NL80211_IFTYPE_AP:
1489 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1490 | AR_STA_ID1_KSRCH_MODE);
1491 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1493 case NL80211_IFTYPE_ADHOC:
1494 case NL80211_IFTYPE_MESH_POINT:
1495 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1496 | AR_STA_ID1_KSRCH_MODE);
1497 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1499 case NL80211_IFTYPE_STATION:
1500 case NL80211_IFTYPE_MONITOR:
1501 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1506 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1511 u32 coef_exp, coef_man;
1513 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1514 if ((coef_scaled >> coef_exp) & 0x1)
1517 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1519 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1521 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1522 *coef_exponent = coef_exp - 16;
1525 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1526 struct ath9k_channel *chan)
1528 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1529 u32 clockMhzScaled = 0x64000000;
1530 struct chan_centers centers;
1532 if (IS_CHAN_HALF_RATE(chan))
1533 clockMhzScaled = clockMhzScaled >> 1;
1534 else if (IS_CHAN_QUARTER_RATE(chan))
1535 clockMhzScaled = clockMhzScaled >> 2;
1537 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1538 coef_scaled = clockMhzScaled / centers.synth_center;
1540 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1543 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1544 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1545 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1546 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1548 coef_scaled = (9 * coef_scaled) / 10;
1550 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1553 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1554 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1555 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1556 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1559 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1564 if (AR_SREV_9100(ah)) {
1565 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1566 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1567 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1568 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1569 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1572 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1573 AR_RTC_FORCE_WAKE_ON_INT);
1575 if (AR_SREV_9100(ah)) {
1576 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1577 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1579 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1581 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1582 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1583 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1584 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1586 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1589 rst_flags = AR_RTC_RC_MAC_WARM;
1590 if (type == ATH9K_RESET_COLD)
1591 rst_flags |= AR_RTC_RC_MAC_COLD;
1594 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1597 REG_WRITE(ah, AR_RTC_RC, 0);
1598 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1599 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1600 "RTC stuck in MAC reset\n");
1604 if (!AR_SREV_9100(ah))
1605 REG_WRITE(ah, AR_RC, 0);
1607 ath9k_hw_init_pll(ah, NULL);
1609 if (AR_SREV_9100(ah))
1615 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1617 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1618 AR_RTC_FORCE_WAKE_ON_INT);
1620 REG_WRITE(ah, AR_RTC_RESET, 0);
1622 REG_WRITE(ah, AR_RTC_RESET, 1);
1624 if (!ath9k_hw_wait(ah,
1629 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1633 ath9k_hw_read_revisions(ah);
1635 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1638 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1640 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1641 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1644 case ATH9K_RESET_POWER_ON:
1645 return ath9k_hw_set_reset_power_on(ah);
1646 case ATH9K_RESET_WARM:
1647 case ATH9K_RESET_COLD:
1648 return ath9k_hw_set_reset(ah, type);
1654 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1655 enum ath9k_ht_macmode macmode)
1658 u32 enableDacFifo = 0;
1660 if (AR_SREV_9285_10_OR_LATER(ah))
1661 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1662 AR_PHY_FC_ENABLE_DAC_FIFO);
1664 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1665 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1667 if (IS_CHAN_HT40(chan)) {
1668 phymode |= AR_PHY_FC_DYN2040_EN;
1670 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1671 (chan->chanmode == CHANNEL_G_HT40PLUS))
1672 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1674 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1675 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1677 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1679 ath9k_hw_set11nmac2040(ah, macmode);
1681 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1682 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1685 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1686 struct ath9k_channel *chan)
1688 if (OLC_FOR_AR9280_20_LATER) {
1689 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1691 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1694 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1697 ah->chip_fullsleep = false;
1698 ath9k_hw_init_pll(ah, chan);
1699 ath9k_hw_set_rfmode(ah, chan);
1704 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1705 struct ath9k_channel *chan,
1706 enum ath9k_ht_macmode macmode)
1708 struct ieee80211_channel *channel = chan->chan;
1709 u32 synthDelay, qnum;
1711 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1712 if (ath9k_hw_numtxpending(ah, qnum)) {
1713 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1714 "Transmit frames pending on queue %d\n", qnum);
1719 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1720 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1721 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1722 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1723 "Could not kill baseband RX\n");
1727 ath9k_hw_set_regs(ah, chan, macmode);
1729 if (AR_SREV_9280_10_OR_LATER(ah)) {
1730 ath9k_hw_ar9280_set_channel(ah, chan);
1732 if (!(ath9k_hw_set_channel(ah, chan))) {
1733 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1734 "Failed to set channel\n");
1739 ah->eep_ops->set_txpower(ah, chan,
1740 ath9k_regd_get_ctl(&ah->regulatory, chan),
1741 channel->max_antenna_gain * 2,
1742 channel->max_power * 2,
1743 min((u32) MAX_RATE_POWER,
1744 (u32) ah->regulatory.power_limit));
1746 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1747 if (IS_CHAN_B(chan))
1748 synthDelay = (4 * synthDelay) / 22;
1752 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1754 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1756 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1757 ath9k_hw_set_delta_slope(ah, chan);
1759 if (AR_SREV_9280_10_OR_LATER(ah))
1760 ath9k_hw_9280_spur_mitigate(ah, chan);
1762 ath9k_hw_spur_mitigate(ah, chan);
1764 if (!chan->oneTimeCalsDone)
1765 chan->oneTimeCalsDone = true;
1770 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1772 int bb_spur = AR_NO_SPUR;
1775 int bb_spur_off, spur_subchannel_sd;
1777 int spur_delta_phase;
1779 int upper, lower, cur_vit_mask;
1782 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1783 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1785 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1786 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1788 int inc[4] = { 0, 100, 0, 0 };
1789 struct chan_centers centers;
1796 bool is2GHz = IS_CHAN_2GHZ(chan);
1798 memset(&mask_m, 0, sizeof(int8_t) * 123);
1799 memset(&mask_p, 0, sizeof(int8_t) * 123);
1801 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1802 freq = centers.synth_center;
1804 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1805 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1806 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1809 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1811 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1813 if (AR_NO_SPUR == cur_bb_spur)
1815 cur_bb_spur = cur_bb_spur - freq;
1817 if (IS_CHAN_HT40(chan)) {
1818 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1819 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1820 bb_spur = cur_bb_spur;
1823 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1824 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1825 bb_spur = cur_bb_spur;
1830 if (AR_NO_SPUR == bb_spur) {
1831 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1832 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1835 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1836 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1839 bin = bb_spur * 320;
1841 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1843 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1844 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1845 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1846 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1847 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1849 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1850 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1851 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1852 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1853 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1854 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1856 if (IS_CHAN_HT40(chan)) {
1858 spur_subchannel_sd = 1;
1859 bb_spur_off = bb_spur + 10;
1861 spur_subchannel_sd = 0;
1862 bb_spur_off = bb_spur - 10;
1865 spur_subchannel_sd = 0;
1866 bb_spur_off = bb_spur;
1869 if (IS_CHAN_HT40(chan))
1871 ((bb_spur * 262144) /
1872 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1875 ((bb_spur * 524288) /
1876 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1878 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1879 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1881 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1882 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1883 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1884 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1886 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1887 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1893 for (i = 0; i < 4; i++) {
1897 for (bp = 0; bp < 30; bp++) {
1898 if ((cur_bin > lower) && (cur_bin < upper)) {
1899 pilot_mask = pilot_mask | 0x1 << bp;
1900 chan_mask = chan_mask | 0x1 << bp;
1905 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1906 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1909 cur_vit_mask = 6100;
1913 for (i = 0; i < 123; i++) {
1914 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1916 /* workaround for gcc bug #37014 */
1917 volatile int tmp_v = abs(cur_vit_mask - bin);
1923 if (cur_vit_mask < 0)
1924 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1926 mask_p[cur_vit_mask / 100] = mask_amt;
1928 cur_vit_mask -= 100;
1931 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1932 | (mask_m[48] << 26) | (mask_m[49] << 24)
1933 | (mask_m[50] << 22) | (mask_m[51] << 20)
1934 | (mask_m[52] << 18) | (mask_m[53] << 16)
1935 | (mask_m[54] << 14) | (mask_m[55] << 12)
1936 | (mask_m[56] << 10) | (mask_m[57] << 8)
1937 | (mask_m[58] << 6) | (mask_m[59] << 4)
1938 | (mask_m[60] << 2) | (mask_m[61] << 0);
1939 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1940 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1942 tmp_mask = (mask_m[31] << 28)
1943 | (mask_m[32] << 26) | (mask_m[33] << 24)
1944 | (mask_m[34] << 22) | (mask_m[35] << 20)
1945 | (mask_m[36] << 18) | (mask_m[37] << 16)
1946 | (mask_m[48] << 14) | (mask_m[39] << 12)
1947 | (mask_m[40] << 10) | (mask_m[41] << 8)
1948 | (mask_m[42] << 6) | (mask_m[43] << 4)
1949 | (mask_m[44] << 2) | (mask_m[45] << 0);
1950 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1951 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1953 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1954 | (mask_m[18] << 26) | (mask_m[18] << 24)
1955 | (mask_m[20] << 22) | (mask_m[20] << 20)
1956 | (mask_m[22] << 18) | (mask_m[22] << 16)
1957 | (mask_m[24] << 14) | (mask_m[24] << 12)
1958 | (mask_m[25] << 10) | (mask_m[26] << 8)
1959 | (mask_m[27] << 6) | (mask_m[28] << 4)
1960 | (mask_m[29] << 2) | (mask_m[30] << 0);
1961 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1962 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1964 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1965 | (mask_m[2] << 26) | (mask_m[3] << 24)
1966 | (mask_m[4] << 22) | (mask_m[5] << 20)
1967 | (mask_m[6] << 18) | (mask_m[7] << 16)
1968 | (mask_m[8] << 14) | (mask_m[9] << 12)
1969 | (mask_m[10] << 10) | (mask_m[11] << 8)
1970 | (mask_m[12] << 6) | (mask_m[13] << 4)
1971 | (mask_m[14] << 2) | (mask_m[15] << 0);
1972 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1973 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1975 tmp_mask = (mask_p[15] << 28)
1976 | (mask_p[14] << 26) | (mask_p[13] << 24)
1977 | (mask_p[12] << 22) | (mask_p[11] << 20)
1978 | (mask_p[10] << 18) | (mask_p[9] << 16)
1979 | (mask_p[8] << 14) | (mask_p[7] << 12)
1980 | (mask_p[6] << 10) | (mask_p[5] << 8)
1981 | (mask_p[4] << 6) | (mask_p[3] << 4)
1982 | (mask_p[2] << 2) | (mask_p[1] << 0);
1983 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1984 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1986 tmp_mask = (mask_p[30] << 28)
1987 | (mask_p[29] << 26) | (mask_p[28] << 24)
1988 | (mask_p[27] << 22) | (mask_p[26] << 20)
1989 | (mask_p[25] << 18) | (mask_p[24] << 16)
1990 | (mask_p[23] << 14) | (mask_p[22] << 12)
1991 | (mask_p[21] << 10) | (mask_p[20] << 8)
1992 | (mask_p[19] << 6) | (mask_p[18] << 4)
1993 | (mask_p[17] << 2) | (mask_p[16] << 0);
1994 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1995 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1997 tmp_mask = (mask_p[45] << 28)
1998 | (mask_p[44] << 26) | (mask_p[43] << 24)
1999 | (mask_p[42] << 22) | (mask_p[41] << 20)
2000 | (mask_p[40] << 18) | (mask_p[39] << 16)
2001 | (mask_p[38] << 14) | (mask_p[37] << 12)
2002 | (mask_p[36] << 10) | (mask_p[35] << 8)
2003 | (mask_p[34] << 6) | (mask_p[33] << 4)
2004 | (mask_p[32] << 2) | (mask_p[31] << 0);
2005 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2006 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2008 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2009 | (mask_p[59] << 26) | (mask_p[58] << 24)
2010 | (mask_p[57] << 22) | (mask_p[56] << 20)
2011 | (mask_p[55] << 18) | (mask_p[54] << 16)
2012 | (mask_p[53] << 14) | (mask_p[52] << 12)
2013 | (mask_p[51] << 10) | (mask_p[50] << 8)
2014 | (mask_p[49] << 6) | (mask_p[48] << 4)
2015 | (mask_p[47] << 2) | (mask_p[46] << 0);
2016 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2017 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2020 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2022 int bb_spur = AR_NO_SPUR;
2025 int spur_delta_phase;
2027 int upper, lower, cur_vit_mask;
2030 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2031 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2033 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2034 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2036 int inc[4] = { 0, 100, 0, 0 };
2043 bool is2GHz = IS_CHAN_2GHZ(chan);
2045 memset(&mask_m, 0, sizeof(int8_t) * 123);
2046 memset(&mask_p, 0, sizeof(int8_t) * 123);
2048 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2049 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2050 if (AR_NO_SPUR == cur_bb_spur)
2052 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2053 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2054 bb_spur = cur_bb_spur;
2059 if (AR_NO_SPUR == bb_spur)
2064 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2065 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2066 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2067 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2068 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2070 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2072 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2073 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2074 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2075 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2076 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2077 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2079 spur_delta_phase = ((bb_spur * 524288) / 100) &
2080 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2082 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2083 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2085 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2086 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2087 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2088 REG_WRITE(ah, AR_PHY_TIMING11, new);
2094 for (i = 0; i < 4; i++) {
2098 for (bp = 0; bp < 30; bp++) {
2099 if ((cur_bin > lower) && (cur_bin < upper)) {
2100 pilot_mask = pilot_mask | 0x1 << bp;
2101 chan_mask = chan_mask | 0x1 << bp;
2106 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2107 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2110 cur_vit_mask = 6100;
2114 for (i = 0; i < 123; i++) {
2115 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2117 /* workaround for gcc bug #37014 */
2118 volatile int tmp_v = abs(cur_vit_mask - bin);
2124 if (cur_vit_mask < 0)
2125 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2127 mask_p[cur_vit_mask / 100] = mask_amt;
2129 cur_vit_mask -= 100;
2132 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2133 | (mask_m[48] << 26) | (mask_m[49] << 24)
2134 | (mask_m[50] << 22) | (mask_m[51] << 20)
2135 | (mask_m[52] << 18) | (mask_m[53] << 16)
2136 | (mask_m[54] << 14) | (mask_m[55] << 12)
2137 | (mask_m[56] << 10) | (mask_m[57] << 8)
2138 | (mask_m[58] << 6) | (mask_m[59] << 4)
2139 | (mask_m[60] << 2) | (mask_m[61] << 0);
2140 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2141 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2143 tmp_mask = (mask_m[31] << 28)
2144 | (mask_m[32] << 26) | (mask_m[33] << 24)
2145 | (mask_m[34] << 22) | (mask_m[35] << 20)
2146 | (mask_m[36] << 18) | (mask_m[37] << 16)
2147 | (mask_m[48] << 14) | (mask_m[39] << 12)
2148 | (mask_m[40] << 10) | (mask_m[41] << 8)
2149 | (mask_m[42] << 6) | (mask_m[43] << 4)
2150 | (mask_m[44] << 2) | (mask_m[45] << 0);
2151 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2152 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2154 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2155 | (mask_m[18] << 26) | (mask_m[18] << 24)
2156 | (mask_m[20] << 22) | (mask_m[20] << 20)
2157 | (mask_m[22] << 18) | (mask_m[22] << 16)
2158 | (mask_m[24] << 14) | (mask_m[24] << 12)
2159 | (mask_m[25] << 10) | (mask_m[26] << 8)
2160 | (mask_m[27] << 6) | (mask_m[28] << 4)
2161 | (mask_m[29] << 2) | (mask_m[30] << 0);
2162 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2163 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2165 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2166 | (mask_m[2] << 26) | (mask_m[3] << 24)
2167 | (mask_m[4] << 22) | (mask_m[5] << 20)
2168 | (mask_m[6] << 18) | (mask_m[7] << 16)
2169 | (mask_m[8] << 14) | (mask_m[9] << 12)
2170 | (mask_m[10] << 10) | (mask_m[11] << 8)
2171 | (mask_m[12] << 6) | (mask_m[13] << 4)
2172 | (mask_m[14] << 2) | (mask_m[15] << 0);
2173 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2174 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2176 tmp_mask = (mask_p[15] << 28)
2177 | (mask_p[14] << 26) | (mask_p[13] << 24)
2178 | (mask_p[12] << 22) | (mask_p[11] << 20)
2179 | (mask_p[10] << 18) | (mask_p[9] << 16)
2180 | (mask_p[8] << 14) | (mask_p[7] << 12)
2181 | (mask_p[6] << 10) | (mask_p[5] << 8)
2182 | (mask_p[4] << 6) | (mask_p[3] << 4)
2183 | (mask_p[2] << 2) | (mask_p[1] << 0);
2184 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2185 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2187 tmp_mask = (mask_p[30] << 28)
2188 | (mask_p[29] << 26) | (mask_p[28] << 24)
2189 | (mask_p[27] << 22) | (mask_p[26] << 20)
2190 | (mask_p[25] << 18) | (mask_p[24] << 16)
2191 | (mask_p[23] << 14) | (mask_p[22] << 12)
2192 | (mask_p[21] << 10) | (mask_p[20] << 8)
2193 | (mask_p[19] << 6) | (mask_p[18] << 4)
2194 | (mask_p[17] << 2) | (mask_p[16] << 0);
2195 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2196 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2198 tmp_mask = (mask_p[45] << 28)
2199 | (mask_p[44] << 26) | (mask_p[43] << 24)
2200 | (mask_p[42] << 22) | (mask_p[41] << 20)
2201 | (mask_p[40] << 18) | (mask_p[39] << 16)
2202 | (mask_p[38] << 14) | (mask_p[37] << 12)
2203 | (mask_p[36] << 10) | (mask_p[35] << 8)
2204 | (mask_p[34] << 6) | (mask_p[33] << 4)
2205 | (mask_p[32] << 2) | (mask_p[31] << 0);
2206 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2207 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2209 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2210 | (mask_p[59] << 26) | (mask_p[58] << 24)
2211 | (mask_p[57] << 22) | (mask_p[56] << 20)
2212 | (mask_p[55] << 18) | (mask_p[54] << 16)
2213 | (mask_p[53] << 14) | (mask_p[52] << 12)
2214 | (mask_p[51] << 10) | (mask_p[50] << 8)
2215 | (mask_p[49] << 6) | (mask_p[48] << 4)
2216 | (mask_p[47] << 2) | (mask_p[46] << 0);
2217 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2218 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2221 static void ath9k_enable_rfkill(struct ath_hw *ah)
2223 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2224 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2226 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2227 AR_GPIO_INPUT_MUX2_RFSILENT);
2229 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2230 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2233 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2234 bool bChannelChange)
2237 struct ath_softc *sc = ah->ah_sc;
2238 struct ath9k_channel *curchan = ah->curchan;
2241 int i, rx_chainmask, r;
2243 ah->extprotspacing = sc->ht_extprotspacing;
2244 ah->txchainmask = sc->tx_chainmask;
2245 ah->rxchainmask = sc->rx_chainmask;
2247 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2251 ath9k_hw_getnf(ah, curchan);
2253 if (bChannelChange &&
2254 (ah->chip_fullsleep != true) &&
2255 (ah->curchan != NULL) &&
2256 (chan->channel != ah->curchan->channel) &&
2257 ((chan->channelFlags & CHANNEL_ALL) ==
2258 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2259 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2260 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2262 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2263 ath9k_hw_loadnf(ah, ah->curchan);
2264 ath9k_hw_start_nfcal(ah);
2269 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2270 if (saveDefAntenna == 0)
2273 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2275 saveLedState = REG_READ(ah, AR_CFG_LED) &
2276 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2277 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2279 ath9k_hw_mark_phy_inactive(ah);
2281 if (!ath9k_hw_chip_reset(ah, chan)) {
2282 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2286 if (AR_SREV_9280_10_OR_LATER(ah))
2287 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2289 if (AR_SREV_9287_10_OR_LATER(ah)) {
2290 /* Enable ASYNC FIFO */
2291 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2292 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2293 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2294 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2295 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2296 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2297 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2299 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2303 /* Setup MFP options for CCMP */
2304 if (AR_SREV_9280_20_OR_LATER(ah)) {
2305 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2306 * frames when constructing CCMP AAD. */
2307 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2309 ah->sw_mgmt_crypto = false;
2310 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2311 /* Disable hardware crypto for management frames */
2312 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2313 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2314 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2315 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2316 ah->sw_mgmt_crypto = true;
2318 ah->sw_mgmt_crypto = true;
2320 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2321 ath9k_hw_set_delta_slope(ah, chan);
2323 if (AR_SREV_9280_10_OR_LATER(ah))
2324 ath9k_hw_9280_spur_mitigate(ah, chan);
2326 ath9k_hw_spur_mitigate(ah, chan);
2328 ah->eep_ops->set_board_values(ah, chan);
2330 ath9k_hw_decrease_chain_power(ah, chan);
2332 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2333 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2335 | AR_STA_ID1_RTS_USE_DEF
2337 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2338 | ah->sta_id1_defaults);
2339 ath9k_hw_set_operating_mode(ah, ah->opmode);
2341 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2342 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2344 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2346 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2347 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2348 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2350 REG_WRITE(ah, AR_ISR, ~0);
2352 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2354 if (AR_SREV_9280_10_OR_LATER(ah))
2355 ath9k_hw_ar9280_set_channel(ah, chan);
2357 if (!(ath9k_hw_set_channel(ah, chan)))
2360 for (i = 0; i < AR_NUM_DCU; i++)
2361 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2364 for (i = 0; i < ah->caps.total_queues; i++)
2365 ath9k_hw_resettxqueue(ah, i);
2367 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2368 ath9k_hw_init_qos(ah);
2370 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2371 ath9k_enable_rfkill(ah);
2373 ath9k_hw_init_user_settings(ah);
2375 if (AR_SREV_9287_10_OR_LATER(ah)) {
2376 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2377 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2378 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2379 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2380 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2381 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2383 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2384 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2386 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2387 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2388 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2389 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2391 if (AR_SREV_9287_10_OR_LATER(ah)) {
2392 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2393 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2396 REG_WRITE(ah, AR_STA_ID1,
2397 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2399 ath9k_hw_set_dma(ah);
2401 REG_WRITE(ah, AR_OBS, 8);
2403 if (ah->config.intr_mitigation) {
2404 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2405 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2408 ath9k_hw_init_bb(ah, chan);
2410 if (!ath9k_hw_init_cal(ah, chan))
2413 rx_chainmask = ah->rxchainmask;
2414 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2415 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2416 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2419 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2421 if (AR_SREV_9100(ah)) {
2423 mask = REG_READ(ah, AR_CFG);
2424 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2425 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2426 "CFG Byte Swap Set 0x%x\n", mask);
2429 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2430 REG_WRITE(ah, AR_CFG, mask);
2431 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2432 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2436 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2443 /************************/
2444 /* Key Cache Management */
2445 /************************/
2447 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2451 if (entry >= ah->caps.keycache_size) {
2452 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2453 "keychache entry %u out of range\n", entry);
2457 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2459 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2460 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2461 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2462 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2463 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2464 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2465 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2466 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2468 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2469 u16 micentry = entry + 64;
2471 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2472 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2473 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2474 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2478 if (ah->curchan == NULL)
2484 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2488 if (entry >= ah->caps.keycache_size) {
2489 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2490 "keychache entry %u out of range\n", entry);
2495 macHi = (mac[5] << 8) | mac[4];
2496 macLo = (mac[3] << 24) |
2501 macLo |= (macHi & 1) << 31;
2506 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2507 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2512 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2513 const struct ath9k_keyval *k,
2516 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2517 u32 key0, key1, key2, key3, key4;
2520 if (entry >= pCap->keycache_size) {
2521 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2522 "keycache entry %u out of range\n", entry);
2526 switch (k->kv_type) {
2527 case ATH9K_CIPHER_AES_OCB:
2528 keyType = AR_KEYTABLE_TYPE_AES;
2530 case ATH9K_CIPHER_AES_CCM:
2531 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2532 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2533 "AES-CCM not supported by mac rev 0x%x\n",
2534 ah->hw_version.macRev);
2537 keyType = AR_KEYTABLE_TYPE_CCM;
2539 case ATH9K_CIPHER_TKIP:
2540 keyType = AR_KEYTABLE_TYPE_TKIP;
2541 if (ATH9K_IS_MIC_ENABLED(ah)
2542 && entry + 64 >= pCap->keycache_size) {
2543 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2544 "entry %u inappropriate for TKIP\n", entry);
2548 case ATH9K_CIPHER_WEP:
2549 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2550 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2551 "WEP key length %u too small\n", k->kv_len);
2554 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2555 keyType = AR_KEYTABLE_TYPE_40;
2556 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2557 keyType = AR_KEYTABLE_TYPE_104;
2559 keyType = AR_KEYTABLE_TYPE_128;
2561 case ATH9K_CIPHER_CLR:
2562 keyType = AR_KEYTABLE_TYPE_CLR;
2565 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2566 "cipher %u not supported\n", k->kv_type);
2570 key0 = get_unaligned_le32(k->kv_val + 0);
2571 key1 = get_unaligned_le16(k->kv_val + 4);
2572 key2 = get_unaligned_le32(k->kv_val + 6);
2573 key3 = get_unaligned_le16(k->kv_val + 10);
2574 key4 = get_unaligned_le32(k->kv_val + 12);
2575 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2579 * Note: Key cache registers access special memory area that requires
2580 * two 32-bit writes to actually update the values in the internal
2581 * memory. Consequently, the exact order and pairs used here must be
2585 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2586 u16 micentry = entry + 64;
2589 * Write inverted key[47:0] first to avoid Michael MIC errors
2590 * on frames that could be sent or received at the same time.
2591 * The correct key will be written in the end once everything
2594 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2595 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2597 /* Write key[95:48] */
2598 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2599 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2601 /* Write key[127:96] and key type */
2602 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2603 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2605 /* Write MAC address for the entry */
2606 (void) ath9k_hw_keysetmac(ah, entry, mac);
2608 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2610 * TKIP uses two key cache entries:
2611 * Michael MIC TX/RX keys in the same key cache entry
2612 * (idx = main index + 64):
2613 * key0 [31:0] = RX key [31:0]
2614 * key1 [15:0] = TX key [31:16]
2615 * key1 [31:16] = reserved
2616 * key2 [31:0] = RX key [63:32]
2617 * key3 [15:0] = TX key [15:0]
2618 * key3 [31:16] = reserved
2619 * key4 [31:0] = TX key [63:32]
2621 u32 mic0, mic1, mic2, mic3, mic4;
2623 mic0 = get_unaligned_le32(k->kv_mic + 0);
2624 mic2 = get_unaligned_le32(k->kv_mic + 4);
2625 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2626 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2627 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2629 /* Write RX[31:0] and TX[31:16] */
2630 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2631 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2633 /* Write RX[63:32] and TX[15:0] */
2634 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2635 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2637 /* Write TX[63:32] and keyType(reserved) */
2638 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2639 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2640 AR_KEYTABLE_TYPE_CLR);
2644 * TKIP uses four key cache entries (two for group
2646 * Michael MIC TX/RX keys are in different key cache
2647 * entries (idx = main index + 64 for TX and
2648 * main index + 32 + 96 for RX):
2649 * key0 [31:0] = TX/RX MIC key [31:0]
2650 * key1 [31:0] = reserved
2651 * key2 [31:0] = TX/RX MIC key [63:32]
2652 * key3 [31:0] = reserved
2653 * key4 [31:0] = reserved
2655 * Upper layer code will call this function separately
2656 * for TX and RX keys when these registers offsets are
2661 mic0 = get_unaligned_le32(k->kv_mic + 0);
2662 mic2 = get_unaligned_le32(k->kv_mic + 4);
2664 /* Write MIC key[31:0] */
2665 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2666 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2668 /* Write MIC key[63:32] */
2669 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2670 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2672 /* Write TX[63:32] and keyType(reserved) */
2673 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2674 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2675 AR_KEYTABLE_TYPE_CLR);
2678 /* MAC address registers are reserved for the MIC entry */
2679 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2680 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2683 * Write the correct (un-inverted) key[47:0] last to enable
2684 * TKIP now that all other registers are set with correct
2687 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2688 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2690 /* Write key[47:0] */
2691 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2692 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2694 /* Write key[95:48] */
2695 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2696 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2698 /* Write key[127:96] and key type */
2699 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2700 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2702 /* Write MAC address for the entry */
2703 (void) ath9k_hw_keysetmac(ah, entry, mac);
2709 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2711 if (entry < ah->caps.keycache_size) {
2712 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2713 if (val & AR_KEYTABLE_VALID)
2719 /******************************/
2720 /* Power Management (Chipset) */
2721 /******************************/
2723 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2725 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2727 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2728 AR_RTC_FORCE_WAKE_EN);
2729 if (!AR_SREV_9100(ah))
2730 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2732 REG_CLR_BIT(ah, (AR_RTC_RESET),
2737 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2739 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2741 struct ath9k_hw_capabilities *pCap = &ah->caps;
2743 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2744 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2745 AR_RTC_FORCE_WAKE_ON_INT);
2747 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2748 AR_RTC_FORCE_WAKE_EN);
2753 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2759 if ((REG_READ(ah, AR_RTC_STATUS) &
2760 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2761 if (ath9k_hw_set_reset_reg(ah,
2762 ATH9K_RESET_POWER_ON) != true) {
2766 if (AR_SREV_9100(ah))
2767 REG_SET_BIT(ah, AR_RTC_RESET,
2770 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2771 AR_RTC_FORCE_WAKE_EN);
2774 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2775 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2776 if (val == AR_RTC_STATUS_ON)
2779 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2780 AR_RTC_FORCE_WAKE_EN);
2783 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2784 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2789 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2794 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2795 enum ath9k_power_mode mode)
2797 int status = true, setChip = true;
2798 static const char *modes[] = {
2805 if (ah->power_mode == mode)
2808 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2809 modes[ah->power_mode], modes[mode]);
2812 case ATH9K_PM_AWAKE:
2813 status = ath9k_hw_set_power_awake(ah, setChip);
2815 case ATH9K_PM_FULL_SLEEP:
2816 ath9k_set_power_sleep(ah, setChip);
2817 ah->chip_fullsleep = true;
2819 case ATH9K_PM_NETWORK_SLEEP:
2820 ath9k_set_power_network_sleep(ah, setChip);
2823 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2824 "Unknown power mode %u\n", mode);
2827 ah->power_mode = mode;
2832 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2834 unsigned long flags;
2837 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2838 ret = ath9k_hw_setpower_nolock(ah, mode);
2839 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2844 void ath9k_ps_wakeup(struct ath_softc *sc)
2846 unsigned long flags;
2848 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2849 if (++sc->ps_usecount != 1)
2852 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2855 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2858 void ath9k_ps_restore(struct ath_softc *sc)
2860 unsigned long flags;
2862 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2863 if (--sc->ps_usecount != 0)
2866 if (sc->ps_enabled &&
2867 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2868 SC_OP_WAIT_FOR_CAB |
2869 SC_OP_WAIT_FOR_PSPOLL_DATA |
2870 SC_OP_WAIT_FOR_TX_ACK)))
2871 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2874 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2878 * Helper for ASPM support.
2880 * Disable PLL when in L0s as well as receiver clock when in L1.
2881 * This power saving option must be enabled through the SerDes.
2883 * Programming the SerDes must go through the same 288 bit serial shift
2884 * register as the other analog registers. Hence the 9 writes.
2886 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2890 if (ah->is_pciexpress != true)
2893 /* Do not touch SerDes registers */
2894 if (ah->config.pcie_powersave_enable == 2)
2897 /* Nothing to do on restore for 11N */
2901 if (AR_SREV_9280_20_OR_LATER(ah)) {
2903 * AR9280 2.0 or later chips use SerDes values from the
2904 * initvals.h initialized depending on chipset during
2907 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2908 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2909 INI_RA(&ah->iniPcieSerdes, i, 1));
2911 } else if (AR_SREV_9280(ah) &&
2912 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2913 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2914 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2916 /* RX shut off when elecidle is asserted */
2917 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2918 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2919 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2921 /* Shut off CLKREQ active in L1 */
2922 if (ah->config.pcie_clock_req)
2923 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2925 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2927 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2928 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2929 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2931 /* Load the new settings */
2932 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2935 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2936 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2938 /* RX shut off when elecidle is asserted */
2939 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2940 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2941 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2944 * Ignore ah->ah_config.pcie_clock_req setting for
2947 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2949 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2950 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2951 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2953 /* Load the new settings */
2954 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2959 /* set bit 19 to allow forcing of pcie core into L1 state */
2960 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2962 /* Several PCIe massages to ensure proper behaviour */
2963 if (ah->config.pcie_waen) {
2964 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2966 if (AR_SREV_9285(ah))
2967 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2969 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2970 * otherwise card may disappear.
2972 else if (AR_SREV_9280(ah))
2973 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2975 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2979 /**********************/
2980 /* Interrupt Handling */
2981 /**********************/
2983 bool ath9k_hw_intrpend(struct ath_hw *ah)
2987 if (AR_SREV_9100(ah))
2990 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2991 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2994 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2995 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2996 && (host_isr != AR_INTR_SPURIOUS))
3002 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3006 struct ath9k_hw_capabilities *pCap = &ah->caps;
3008 bool fatal_int = false;
3010 if (!AR_SREV_9100(ah)) {
3011 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3012 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3013 == AR_RTC_STATUS_ON) {
3014 isr = REG_READ(ah, AR_ISR);
3018 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3019 AR_INTR_SYNC_DEFAULT;
3023 if (!isr && !sync_cause)
3027 isr = REG_READ(ah, AR_ISR);
3031 if (isr & AR_ISR_BCNMISC) {
3033 isr2 = REG_READ(ah, AR_ISR_S2);
3034 if (isr2 & AR_ISR_S2_TIM)
3035 mask2 |= ATH9K_INT_TIM;
3036 if (isr2 & AR_ISR_S2_DTIM)
3037 mask2 |= ATH9K_INT_DTIM;
3038 if (isr2 & AR_ISR_S2_DTIMSYNC)
3039 mask2 |= ATH9K_INT_DTIMSYNC;
3040 if (isr2 & (AR_ISR_S2_CABEND))
3041 mask2 |= ATH9K_INT_CABEND;
3042 if (isr2 & AR_ISR_S2_GTT)
3043 mask2 |= ATH9K_INT_GTT;
3044 if (isr2 & AR_ISR_S2_CST)
3045 mask2 |= ATH9K_INT_CST;
3046 if (isr2 & AR_ISR_S2_TSFOOR)
3047 mask2 |= ATH9K_INT_TSFOOR;
3050 isr = REG_READ(ah, AR_ISR_RAC);
3051 if (isr == 0xffffffff) {
3056 *masked = isr & ATH9K_INT_COMMON;
3058 if (ah->config.intr_mitigation) {
3059 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3060 *masked |= ATH9K_INT_RX;
3063 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3064 *masked |= ATH9K_INT_RX;
3066 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3070 *masked |= ATH9K_INT_TX;
3072 s0_s = REG_READ(ah, AR_ISR_S0_S);
3073 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3074 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3076 s1_s = REG_READ(ah, AR_ISR_S1_S);
3077 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3078 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3081 if (isr & AR_ISR_RXORN) {
3082 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3083 "receive FIFO overrun interrupt\n");
3086 if (!AR_SREV_9100(ah)) {
3087 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3088 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3089 if (isr5 & AR_ISR_S5_TIM_TIMER)
3090 *masked |= ATH9K_INT_TIM_TIMER;
3097 if (AR_SREV_9100(ah))
3103 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3107 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3108 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3109 "received PCI FATAL interrupt\n");
3111 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3112 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3113 "received PCI PERR interrupt\n");
3115 *masked |= ATH9K_INT_FATAL;
3117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3118 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3119 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3120 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3121 REG_WRITE(ah, AR_RC, 0);
3122 *masked |= ATH9K_INT_FATAL;
3124 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3125 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3126 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3129 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3130 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3136 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3138 u32 omask = ah->mask_reg;
3140 struct ath9k_hw_capabilities *pCap = &ah->caps;
3142 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3144 if (omask & ATH9K_INT_GLOBAL) {
3145 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3146 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3147 (void) REG_READ(ah, AR_IER);
3148 if (!AR_SREV_9100(ah)) {
3149 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3150 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3152 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3153 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3157 mask = ints & ATH9K_INT_COMMON;
3160 if (ints & ATH9K_INT_TX) {
3161 if (ah->txok_interrupt_mask)
3162 mask |= AR_IMR_TXOK;
3163 if (ah->txdesc_interrupt_mask)
3164 mask |= AR_IMR_TXDESC;
3165 if (ah->txerr_interrupt_mask)
3166 mask |= AR_IMR_TXERR;
3167 if (ah->txeol_interrupt_mask)
3168 mask |= AR_IMR_TXEOL;
3170 if (ints & ATH9K_INT_RX) {
3171 mask |= AR_IMR_RXERR;
3172 if (ah->config.intr_mitigation)
3173 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3175 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3176 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3177 mask |= AR_IMR_GENTMR;
3180 if (ints & (ATH9K_INT_BMISC)) {
3181 mask |= AR_IMR_BCNMISC;
3182 if (ints & ATH9K_INT_TIM)
3183 mask2 |= AR_IMR_S2_TIM;
3184 if (ints & ATH9K_INT_DTIM)
3185 mask2 |= AR_IMR_S2_DTIM;
3186 if (ints & ATH9K_INT_DTIMSYNC)
3187 mask2 |= AR_IMR_S2_DTIMSYNC;
3188 if (ints & ATH9K_INT_CABEND)
3189 mask2 |= AR_IMR_S2_CABEND;
3190 if (ints & ATH9K_INT_TSFOOR)
3191 mask2 |= AR_IMR_S2_TSFOOR;
3194 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3195 mask |= AR_IMR_BCNMISC;
3196 if (ints & ATH9K_INT_GTT)
3197 mask2 |= AR_IMR_S2_GTT;
3198 if (ints & ATH9K_INT_CST)
3199 mask2 |= AR_IMR_S2_CST;
3202 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3203 REG_WRITE(ah, AR_IMR, mask);
3204 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3206 AR_IMR_S2_DTIMSYNC |
3210 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3211 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3212 ah->mask_reg = ints;
3214 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3215 if (ints & ATH9K_INT_TIM_TIMER)
3216 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3218 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3221 if (ints & ATH9K_INT_GLOBAL) {
3222 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3223 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3224 if (!AR_SREV_9100(ah)) {
3225 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3227 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3230 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3231 AR_INTR_SYNC_DEFAULT);
3232 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3233 AR_INTR_SYNC_DEFAULT);
3235 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3236 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3242 /*******************/
3243 /* Beacon Handling */
3244 /*******************/
3246 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3250 ah->beacon_interval = beacon_period;
3252 switch (ah->opmode) {
3253 case NL80211_IFTYPE_STATION:
3254 case NL80211_IFTYPE_MONITOR:
3255 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3256 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3257 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3258 flags |= AR_TBTT_TIMER_EN;
3260 case NL80211_IFTYPE_ADHOC:
3261 case NL80211_IFTYPE_MESH_POINT:
3262 REG_SET_BIT(ah, AR_TXCFG,
3263 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3264 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3265 TU_TO_USEC(next_beacon +
3266 (ah->atim_window ? ah->
3268 flags |= AR_NDP_TIMER_EN;
3269 case NL80211_IFTYPE_AP:
3270 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3271 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3272 TU_TO_USEC(next_beacon -
3274 dma_beacon_response_time));
3275 REG_WRITE(ah, AR_NEXT_SWBA,
3276 TU_TO_USEC(next_beacon -
3278 sw_beacon_response_time));
3280 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3283 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3284 "%s: unsupported opmode: %d\n",
3285 __func__, ah->opmode);
3290 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3291 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3292 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3293 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3295 beacon_period &= ~ATH9K_BEACON_ENA;
3296 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3297 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3298 ath9k_hw_reset_tsf(ah);
3301 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3304 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3305 const struct ath9k_beacon_state *bs)
3307 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3308 struct ath9k_hw_capabilities *pCap = &ah->caps;
3310 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3312 REG_WRITE(ah, AR_BEACON_PERIOD,
3313 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3314 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3315 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3317 REG_RMW_FIELD(ah, AR_RSSI_THR,
3318 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3320 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3322 if (bs->bs_sleepduration > beaconintval)
3323 beaconintval = bs->bs_sleepduration;
3325 dtimperiod = bs->bs_dtimperiod;
3326 if (bs->bs_sleepduration > dtimperiod)
3327 dtimperiod = bs->bs_sleepduration;
3329 if (beaconintval == dtimperiod)
3330 nextTbtt = bs->bs_nextdtim;
3332 nextTbtt = bs->bs_nexttbtt;
3334 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3335 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3336 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3337 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3339 REG_WRITE(ah, AR_NEXT_DTIM,
3340 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3341 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3343 REG_WRITE(ah, AR_SLEEP1,
3344 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3345 | AR_SLEEP1_ASSUME_DTIM);
3347 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3348 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3350 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3352 REG_WRITE(ah, AR_SLEEP2,
3353 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3355 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3356 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3358 REG_SET_BIT(ah, AR_TIMER_MODE,
3359 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3362 /* TSF Out of Range Threshold */
3363 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3366 /*******************/
3367 /* HW Capabilities */
3368 /*******************/
3370 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3372 struct ath9k_hw_capabilities *pCap = &ah->caps;
3373 u16 capField = 0, eeval;
3375 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3376 ah->regulatory.current_rd = eeval;
3378 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3379 if (AR_SREV_9285_10_OR_LATER(ah))
3380 eeval |= AR9285_RDEXT_DEFAULT;
3381 ah->regulatory.current_rd_ext = eeval;
3383 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3385 if (ah->opmode != NL80211_IFTYPE_AP &&
3386 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3387 if (ah->regulatory.current_rd == 0x64 ||
3388 ah->regulatory.current_rd == 0x65)
3389 ah->regulatory.current_rd += 5;
3390 else if (ah->regulatory.current_rd == 0x41)
3391 ah->regulatory.current_rd = 0x43;
3392 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3393 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3396 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3397 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3399 if (eeval & AR5416_OPFLAGS_11A) {
3400 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3401 if (ah->config.ht_enable) {
3402 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3403 set_bit(ATH9K_MODE_11NA_HT20,
3404 pCap->wireless_modes);
3405 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3406 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3407 pCap->wireless_modes);
3408 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3409 pCap->wireless_modes);
3414 if (eeval & AR5416_OPFLAGS_11G) {
3415 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3416 if (ah->config.ht_enable) {
3417 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3418 set_bit(ATH9K_MODE_11NG_HT20,
3419 pCap->wireless_modes);
3420 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3421 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3422 pCap->wireless_modes);
3423 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3424 pCap->wireless_modes);
3429 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3430 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3431 !(eeval & AR5416_OPFLAGS_11A))
3432 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3434 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3436 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3437 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3439 pCap->low_2ghz_chan = 2312;
3440 pCap->high_2ghz_chan = 2732;
3442 pCap->low_5ghz_chan = 4920;
3443 pCap->high_5ghz_chan = 6100;
3445 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3446 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3447 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3449 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3450 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3451 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3453 if (ah->config.ht_enable)
3454 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3456 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3458 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3459 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3460 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3461 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3463 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3464 pCap->total_queues =
3465 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3467 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3469 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3470 pCap->keycache_size =
3471 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3473 pCap->keycache_size = AR_KEYTABLE_SIZE;
3475 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3476 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3478 if (AR_SREV_9285_10_OR_LATER(ah))
3479 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3480 else if (AR_SREV_9280_10_OR_LATER(ah))
3481 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3483 pCap->num_gpio_pins = AR_NUM_GPIO;
3485 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3486 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3487 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3489 pCap->rts_aggr_limit = (8 * 1024);
3492 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3494 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3495 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3496 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3498 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3499 ah->rfkill_polarity =
3500 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3502 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3506 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3507 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3508 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3509 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3510 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3511 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3512 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3514 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3516 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3517 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3519 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3521 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3523 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3524 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3525 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3526 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3529 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3530 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3533 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3535 pCap->num_antcfg_5ghz =
3536 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3537 pCap->num_antcfg_2ghz =
3538 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3540 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3541 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3542 ah->btactive_gpio = 6;
3543 ah->wlanactive_gpio = 5;
3547 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3548 u32 capability, u32 *result)
3551 case ATH9K_CAP_CIPHER:
3552 switch (capability) {
3553 case ATH9K_CIPHER_AES_CCM:
3554 case ATH9K_CIPHER_AES_OCB:
3555 case ATH9K_CIPHER_TKIP:
3556 case ATH9K_CIPHER_WEP:
3557 case ATH9K_CIPHER_MIC:
3558 case ATH9K_CIPHER_CLR:
3563 case ATH9K_CAP_TKIP_MIC:
3564 switch (capability) {
3568 return (ah->sta_id1_defaults &
3569 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3572 case ATH9K_CAP_TKIP_SPLIT:
3573 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3575 case ATH9K_CAP_DIVERSITY:
3576 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3577 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3579 case ATH9K_CAP_MCAST_KEYSRCH:
3580 switch (capability) {
3584 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3587 return (ah->sta_id1_defaults &
3588 AR_STA_ID1_MCAST_KSRCH) ? true :
3593 case ATH9K_CAP_TXPOW:
3594 switch (capability) {
3598 *result = ah->regulatory.power_limit;
3601 *result = ah->regulatory.max_power_level;
3604 *result = ah->regulatory.tp_scale;
3609 return (AR_SREV_9280_20_OR_LATER(ah) &&
3610 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3617 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3618 u32 capability, u32 setting, int *status)
3623 case ATH9K_CAP_TKIP_MIC:
3625 ah->sta_id1_defaults |=
3626 AR_STA_ID1_CRPT_MIC_ENABLE;
3628 ah->sta_id1_defaults &=
3629 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3631 case ATH9K_CAP_DIVERSITY:
3632 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3634 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3636 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3637 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3639 case ATH9K_CAP_MCAST_KEYSRCH:
3641 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3643 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3650 /****************************/
3651 /* GPIO / RFKILL / Antennae */
3652 /****************************/
3654 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3658 u32 gpio_shift, tmp;
3661 addr = AR_GPIO_OUTPUT_MUX3;
3663 addr = AR_GPIO_OUTPUT_MUX2;
3665 addr = AR_GPIO_OUTPUT_MUX1;
3667 gpio_shift = (gpio % 6) * 5;
3669 if (AR_SREV_9280_20_OR_LATER(ah)
3670 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3671 REG_RMW(ah, addr, (type << gpio_shift),
3672 (0x1f << gpio_shift));
3674 tmp = REG_READ(ah, addr);
3675 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3676 tmp &= ~(0x1f << gpio_shift);
3677 tmp |= (type << gpio_shift);
3678 REG_WRITE(ah, addr, tmp);
3682 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3686 ASSERT(gpio < ah->caps.num_gpio_pins);
3688 gpio_shift = gpio << 1;
3692 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3693 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3696 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3698 #define MS_REG_READ(x, y) \
3699 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3701 if (gpio >= ah->caps.num_gpio_pins)
3704 if (AR_SREV_9287_10_OR_LATER(ah))
3705 return MS_REG_READ(AR9287, gpio) != 0;
3706 else if (AR_SREV_9285_10_OR_LATER(ah))
3707 return MS_REG_READ(AR9285, gpio) != 0;
3708 else if (AR_SREV_9280_10_OR_LATER(ah))
3709 return MS_REG_READ(AR928X, gpio) != 0;
3711 return MS_REG_READ(AR, gpio) != 0;
3714 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3719 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3721 gpio_shift = 2 * gpio;
3725 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3726 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3729 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3731 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3735 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3737 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3740 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3742 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3745 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3746 enum ath9k_ant_setting settings,
3747 struct ath9k_channel *chan,
3752 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3754 if (AR_SREV_9280(ah)) {
3755 if (!tx_chainmask_cfg) {
3757 tx_chainmask_cfg = *tx_chainmask;
3758 rx_chainmask_cfg = *rx_chainmask;
3762 case ATH9K_ANT_FIXED_A:
3763 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3764 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3765 *antenna_cfgd = true;
3767 case ATH9K_ANT_FIXED_B:
3768 if (ah->caps.tx_chainmask >
3769 ATH9K_ANTENNA1_CHAINMASK) {
3770 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3772 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3773 *antenna_cfgd = true;
3775 case ATH9K_ANT_VARIABLE:
3776 *tx_chainmask = tx_chainmask_cfg;
3777 *rx_chainmask = rx_chainmask_cfg;
3778 *antenna_cfgd = true;
3784 ah->diversity_control = settings;
3790 /*********************/
3791 /* General Operation */
3792 /*********************/
3794 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3796 u32 bits = REG_READ(ah, AR_RX_FILTER);
3797 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3799 if (phybits & AR_PHY_ERR_RADAR)
3800 bits |= ATH9K_RX_FILTER_PHYRADAR;
3801 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3802 bits |= ATH9K_RX_FILTER_PHYERR;
3807 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3811 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3813 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3814 phybits |= AR_PHY_ERR_RADAR;
3815 if (bits & ATH9K_RX_FILTER_PHYERR)
3816 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3817 REG_WRITE(ah, AR_PHY_ERR, phybits);
3820 REG_WRITE(ah, AR_RXCFG,
3821 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3823 REG_WRITE(ah, AR_RXCFG,
3824 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3827 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3829 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3832 bool ath9k_hw_disable(struct ath_hw *ah)
3834 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3837 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3840 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3842 struct ath9k_channel *chan = ah->curchan;
3843 struct ieee80211_channel *channel = chan->chan;
3845 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3847 ah->eep_ops->set_txpower(ah, chan,
3848 ath9k_regd_get_ctl(&ah->regulatory, chan),
3849 channel->max_antenna_gain * 2,
3850 channel->max_power * 2,
3851 min((u32) MAX_RATE_POWER,
3852 (u32) ah->regulatory.power_limit));
3855 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3857 memcpy(ah->macaddr, mac, ETH_ALEN);
3860 void ath9k_hw_setopmode(struct ath_hw *ah)
3862 ath9k_hw_set_operating_mode(ah, ah->opmode);
3865 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3867 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3868 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3871 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3873 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3874 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3877 void ath9k_hw_write_associd(struct ath_softc *sc)
3879 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3880 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3881 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3884 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3888 tsf = REG_READ(ah, AR_TSF_U32);
3889 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3894 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3896 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3897 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3900 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3902 ath9k_ps_wakeup(ah->ah_sc);
3903 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3904 AH_TSF_WRITE_TIMEOUT))
3905 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3906 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3908 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3909 ath9k_ps_restore(ah->ah_sc);
3912 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3915 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3917 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3922 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3924 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3925 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3926 ah->slottime = (u32) -1;
3929 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3935 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3939 if (mode == ATH9K_HT_MACMODE_2040 &&
3940 !ah->config.cwm_ignore_extcca)
3941 macmode = AR_2040_JOINED_RX_CLEAR;
3945 REG_WRITE(ah, AR_2040_MODE, macmode);
3948 /***************************/
3949 /* Bluetooth Coexistence */
3950 /***************************/
3952 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3954 /* connect bt_active to baseband */
3955 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3956 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3957 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3959 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3960 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3962 /* Set input mux for bt_active to gpio pin */
3963 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3964 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3967 /* Configure the desired gpio port for input */
3968 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3970 /* Configure the desired GPIO port for TX_FRAME output */
3971 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3972 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);