drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 /*
  88  * Read and write, they both share the same lock. We do this to serialize
  89  * reads and writes on Atheros 802.11n PCI devices only. This is required
  90  * as the FIFO on these devices can only accept sanely 2 requests. After
  91  * that the device goes bananas. Serializing the reads/writes prevents this
  92  * from happening.
  93  */
  94
  95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  96 {
  97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  98                 unsigned long flags;
  99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 102         } else
 103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 104 }
 105
 106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 107 {
 108         u32 val;
 109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 110                 unsigned long flags;
 111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 112                 val = ioread32(ah->ah_sc->mem + reg_offset);
 113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 114         } else
 115                 val = ioread32(ah->ah_sc->mem + reg_offset);
 116         return val;
 117 }
 118
 119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 120 {
 121         int i;
 122
 123         BUG_ON(timeout < AH_TIME_QUANTUM);
 124
 125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 126                 if ((REG_READ(ah, reg) & mask) == val)
 127                         return true;
 128
 129                 udelay(AH_TIME_QUANTUM);
 130         }
 131
 132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 134                 timeout, reg, REG_READ(ah, reg), mask, val);
 135
 136         return false;
 137 }
 138
 139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 140 {
 141         u32 retval;
 142         int i;
 143
 144         for (i = 0, retval = 0; i < n; i++) {
 145                 retval = (retval << 1) | (val & 1);
 146                 val >>= 1;
 147         }
 148         return retval;
 149 }
 150
 151 bool ath9k_get_channel_edges(struct ath_hw *ah,
 152                              u16 flags, u16 *low,
 153                              u16 *high)
 154 {
 155         struct ath9k_hw_capabilities *pCap = &ah->caps;
 156
 157         if (flags & CHANNEL_5GHZ) {
 158                 *low = pCap->low_5ghz_chan;
 159                 *high = pCap->high_5ghz_chan;
 160                 return true;
 161         }
 162         if ((flags & CHANNEL_2GHZ)) {
 163                 *low = pCap->low_2ghz_chan;
 164                 *high = pCap->high_2ghz_chan;
 165                 return true;
 166         }
 167         return false;
 168 }
 169
 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 171                            const struct ath_rate_table *rates,
 172                            u32 frameLen, u16 rateix,
 173                            bool shortPreamble)
 174 {
 175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 176         u32 kbps;
 177
 178         kbps = rates->info[rateix].ratekbps;
 179
 180         if (kbps == 0)
 181                 return 0;
 182
 183         switch (rates->info[rateix].phy) {
 184         case WLAN_RC_PHY_CCK:
 185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 186                 if (shortPreamble && rates->info[rateix].short_preamble)
 187                         phyTime >>= 1;
 188                 numBits = frameLen << 3;
 189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 190                 break;
 191         case WLAN_RC_PHY_OFDM:
 192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME_QUARTER
 197                                 + OFDM_PREAMBLE_TIME_QUARTER
 198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 199                 } else if (ah->curchan &&
 200                            IS_CHAN_HALF_RATE(ah->curchan)) {
 201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 204                         txTime = OFDM_SIFS_TIME_HALF +
 205                                 OFDM_PREAMBLE_TIME_HALF
 206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 207                 } else {
 208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 212                                 + (numSymbols * OFDM_SYMBOL_TIME);
 213                 }
 214                 break;
 215         default:
 216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 217                         "Unknown phy %u (rate ix %u)\n",
 218                         rates->info[rateix].phy, rateix);
 219                 txTime = 0;
 220                 break;
 221         }
 222
 223         return txTime;
 224 }
 225
 226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 227                                   struct ath9k_channel *chan,
 228                                   struct chan_centers *centers)
 229 {
 230         int8_t extoff;
 231
 232         if (!IS_CHAN_HT40(chan)) {
 233                 centers->ctl_center = centers->ext_center =
 234                         centers->synth_center = chan->channel;
 235                 return;
 236         }
 237
 238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 240                 centers->synth_center =
 241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 242                 extoff = 1;
 243         } else {
 244                 centers->synth_center =
 245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 246                 extoff = -1;
 247         }
 248
 249         centers->ctl_center =
 250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 251         centers->ext_center =
 252                 centers->synth_center + (extoff *
 253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 254                           HT40_CHANNEL_CENTER_SHIFT : 15));
 255 }
 256
 257 /******************/
 258 /* Chip Revisions */
 259 /******************/
 260
 261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 262 {
 263         u32 val;
 264
 265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 266
 267         if (val == 0xFF) {
 268                 val = REG_READ(ah, AR_SREV);
 269                 ah->hw_version.macVersion =
 270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 273         } else {
 274                 if (!AR_SREV_9100(ah))
 275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 276
 277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 278
 279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 280                         ah->is_pciexpress = true;
 281         }
 282 }
 283
 284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 285 {
 286         u32 val;
 287         int i;
 288
 289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 290
 291         for (i = 0; i < 8; i++)
 292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 295
 296         return ath9k_hw_reverse_bits(val, 8);
 297 }
 298
 299 /************************************/
 300 /* HW Attach, Detach, Init Routines */
 301 /************************************/
 302
 303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 304 {
 305         if (AR_SREV_9100(ah))
 306                 return;
 307
 308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 317
 318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 319 }
 320
 321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 322 {
 323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 324         u32 regHold[2];
 325         u32 patternData[4] = { 0x55555555,
 326                                0xaaaaaaaa,
 327                                0x66666666,
 328                                0x99999999 };
 329         int i, j;
 330
 331         for (i = 0; i < 2; i++) {
 332                 u32 addr = regAddr[i];
 333                 u32 wrData, rdData;
 334
 335                 regHold[i] = REG_READ(ah, addr);
 336                 for (j = 0; j < 0x100; j++) {
 337                         wrData = (j << 16) | j;
 338                         REG_WRITE(ah, addr, wrData);
 339                         rdData = REG_READ(ah, addr);
 340                         if (rdData != wrData) {
 341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 342                                         "address test failed "
 343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 344                                         addr, wrData, rdData);
 345                                 return false;
 346                         }
 347                 }
 348                 for (j = 0; j < 4; j++) {
 349                         wrData = patternData[j];
 350                         REG_WRITE(ah, addr, wrData);
 351                         rdData = REG_READ(ah, addr);
 352                         if (wrData != rdData) {
 353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 354                                         "address test failed "
 355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 356                                         addr, wrData, rdData);
 357                                 return false;
 358                         }
 359                 }
 360                 REG_WRITE(ah, regAddr[i], regHold[i]);
 361         }
 362         udelay(100);
 363
 364         return true;
 365 }
 366
 367 static const char *ath9k_hw_devname(u16 devid)
 368 {
 369         switch (devid) {
 370         case AR5416_DEVID_PCI:
 371                 return "Atheros 5416";
 372         case AR5416_DEVID_PCIE:
 373                 return "Atheros 5418";
 374         case AR9160_DEVID_PCI:
 375                 return "Atheros 9160";
 376         case AR5416_AR9100_DEVID:
 377                 return "Atheros 9100";
 378         case AR9280_DEVID_PCI:
 379         case AR9280_DEVID_PCIE:
 380                 return "Atheros 9280";
 381         case AR9285_DEVID_PCIE:
 382                 return "Atheros 9285";
 383         case AR5416_DEVID_AR9287_PCI:
 384         case AR5416_DEVID_AR9287_PCIE:
 385                 return "Atheros 9287";
 386         }
 387
 388         return NULL;
 389 }
 390
 391 static void ath9k_hw_init_config(struct ath_hw *ah)
 392 {
 393         int i;
 394
 395         ah->config.dma_beacon_response_time = 2;
 396         ah->config.sw_beacon_response_time = 10;
 397         ah->config.additional_swba_backoff = 0;
 398         ah->config.ack_6mb = 0x0;
 399         ah->config.cwm_ignore_extcca = 0;
 400         ah->config.pcie_powersave_enable = 0;
 401         ah->config.pcie_clock_req = 0;
 402         ah->config.pcie_waen = 0;
 403         ah->config.analog_shiftreg = 1;
 404         ah->config.ht_enable = 1;
 405         ah->config.ofdm_trig_low = 200;
 406         ah->config.ofdm_trig_high = 500;
 407         ah->config.cck_trig_high = 200;
 408         ah->config.cck_trig_low = 100;
 409         ah->config.enable_ani = 1;
 410         ah->config.diversity_control = 0;
 411         ah->config.antenna_switch_swap = 0;
 412
 413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 416         }
 417
 418         ah->config.intr_mitigation = true;
 419
 420         /*
 421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 423          * This means we use it for all AR5416 devices, and the few
 424          * minor PCI AR9280 devices out there.
 425          *
 426          * Serialization is required because these devices do not handle
 427          * well the case of two concurrent reads/writes due to the latency
 428          * involved. During one read/write another read/write can be issued
 429          * on another CPU while the previous read/write may still be working
 430          * on our hardware, if we hit this case the hardware poops in a loop.
 431          * We prevent this by serializing reads and writes.
 432          *
 433          * This issue is not present on PCI-Express devices or pre-AR5416
 434          * devices (legacy, 802.11abg).
 435          */
 436         if (num_possible_cpus() > 1)
 437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 438 }
 439
 440 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 441 {
 442         ah->hw_version.magic = AR5416_MAGIC;
 443         ah->regulatory.country_code = CTRY_DEFAULT;
 444         ah->hw_version.subvendorid = 0;
 445
 446         ah->ah_flags = 0;
 447         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 448                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 449         if (!AR_SREV_9100(ah))
 450                 ah->ah_flags = AH_USE_EEPROM;
 451
 452         ah->regulatory.power_limit = MAX_RATE_POWER;
 453         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 454         ah->atim_window = 0;
 455         ah->diversity_control = ah->config.diversity_control;
 456         ah->antenna_switch_swap =
 457                 ah->config.antenna_switch_swap;
 458         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 459         ah->beacon_interval = 100;
 460         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 461         ah->slottime = (u32) -1;
 462         ah->acktimeout = (u32) -1;
 463         ah->ctstimeout = (u32) -1;
 464         ah->globaltxtimeout = (u32) -1;
 465
 466         ah->gbeacon_rate = 0;
 467
 468         ah->power_mode = ATH9K_PM_UNDEFINED;
 469 }
 470
 471 static int ath9k_hw_rfattach(struct ath_hw *ah)
 472 {
 473         bool rfStatus = false;
 474         int ecode = 0;
 475
 476         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 477         if (!rfStatus) {
 478                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 479                         "RF setup failed, status: %u\n", ecode);
 480                 return ecode;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 487 {
 488         u32 val;
 489
 490         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 491
 492         val = ath9k_hw_get_radiorev(ah);
 493         switch (val & AR_RADIO_SREV_MAJOR) {
 494         case 0:
 495                 val = AR_RAD5133_SREV_MAJOR;
 496                 break;
 497         case AR_RAD5133_SREV_MAJOR:
 498         case AR_RAD5122_SREV_MAJOR:
 499         case AR_RAD2133_SREV_MAJOR:
 500         case AR_RAD2122_SREV_MAJOR:
 501                 break;
 502         default:
 503                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 504                         "Radio Chip Rev 0x%02X not supported\n",
 505                         val & AR_RADIO_SREV_MAJOR);
 506                 return -EOPNOTSUPP;
 507         }
 508
 509         ah->hw_version.analog5GhzRev = val;
 510
 511         return 0;
 512 }
 513
 514 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 515 {
 516         u32 sum;
 517         int i;
 518         u16 eeval;
 519
 520         sum = 0;
 521         for (i = 0; i < 3; i++) {
 522                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 523                 sum += eeval;
 524                 ah->macaddr[2 * i] = eeval >> 8;
 525                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 526         }
 527         if (sum == 0 || sum == 0xffff * 3)
 528                 return -EADDRNOTAVAIL;
 529
 530         return 0;
 531 }
 532
 533 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 534 {
 535         u32 rxgain_type;
 536
 537         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 538                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 539
 540                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 541                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 542                         ar9280Modes_backoff_13db_rxgain_9280_2,
 543                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 544                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 545                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 546                         ar9280Modes_backoff_23db_rxgain_9280_2,
 547                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 548                 else
 549                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 550                         ar9280Modes_original_rxgain_9280_2,
 551                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 552         } else {
 553                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 554                         ar9280Modes_original_rxgain_9280_2,
 555                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 556         }
 557 }
 558
 559 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 560 {
 561         u32 txgain_type;
 562
 563         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 564                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 565
 566                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 567                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 568                         ar9280Modes_high_power_tx_gain_9280_2,
 569                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 570                 else
 571                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 572                         ar9280Modes_original_tx_gain_9280_2,
 573                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 574         } else {
 575                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 576                 ar9280Modes_original_tx_gain_9280_2,
 577                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 578         }
 579 }
 580
 581 static int ath9k_hw_post_init(struct ath_hw *ah)
 582 {
 583         int ecode;
 584
 585         if (!ath9k_hw_chip_test(ah))
 586                 return -ENODEV;
 587
 588         ecode = ath9k_hw_rf_claim(ah);
 589         if (ecode != 0)
 590                 return ecode;
 591
 592         ecode = ath9k_hw_eeprom_init(ah);
 593         if (ecode != 0)
 594                 return ecode;
 595
 596         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 597                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 598
 599         ecode = ath9k_hw_rfattach(ah);
 600         if (ecode != 0)
 601                 return ecode;
 602
 603         if (!AR_SREV_9100(ah)) {
 604                 ath9k_hw_ani_setup(ah);
 605                 ath9k_hw_ani_init(ah);
 606         }
 607
 608         return 0;
 609 }
 610
 611 static bool ath9k_hw_devid_supported(u16 devid)
 612 {
 613         switch (devid) {
 614         case AR5416_DEVID_PCI:
 615         case AR5416_DEVID_PCIE:
 616         case AR5416_AR9100_DEVID:
 617         case AR9160_DEVID_PCI:
 618         case AR9280_DEVID_PCI:
 619         case AR9280_DEVID_PCIE:
 620         case AR9285_DEVID_PCIE:
 621         case AR5416_DEVID_AR9287_PCI:
 622         case AR5416_DEVID_AR9287_PCIE:
 623                 return true;
 624         default:
 625                 break;
 626         }
 627         return false;
 628 }
 629
 630 static bool ath9k_hw_macversion_supported(u32 macversion)
 631 {
 632         switch (macversion) {
 633         case AR_SREV_VERSION_5416_PCI:
 634         case AR_SREV_VERSION_5416_PCIE:
 635         case AR_SREV_VERSION_9160:
 636         case AR_SREV_VERSION_9100:
 637         case AR_SREV_VERSION_9280:
 638         case AR_SREV_VERSION_9285:
 639         case AR_SREV_VERSION_9287:
 640                 return true;
 641         default:
 642                 break;
 643         }
 644         return false;
 645 }
 646
 647 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 648 {
 649         if (AR_SREV_9160_10_OR_LATER(ah)) {
 650                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 651                         ah->iq_caldata.calData = &iq_cal_single_sample;
 652                         ah->adcgain_caldata.calData =
 653                                 &adc_gain_cal_single_sample;
 654                         ah->adcdc_caldata.calData =
 655                                 &adc_dc_cal_single_sample;
 656                         ah->adcdc_calinitdata.calData =
 657                                 &adc_init_dc_cal;
 658                 } else {
 659                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 660                         ah->adcgain_caldata.calData =
 661                                 &adc_gain_cal_multi_sample;
 662                         ah->adcdc_caldata.calData =
 663                                 &adc_dc_cal_multi_sample;
 664                         ah->adcdc_calinitdata.calData =
 665                                 &adc_init_dc_cal;
 666                 }
 667                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 668         }
 669 }
 670
 671 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 672 {
 673         if (AR_SREV_9287_11_OR_LATER(ah)) {
 674                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 675                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 676                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 677                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 678                 if (ah->config.pcie_clock_req)
 679                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 680                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 681                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 682                 else
 683                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 684                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 685                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 686                                         2);
 687         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 688                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 689                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 690                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 691                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 692
 693                 if (ah->config.pcie_clock_req)
 694                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 695                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 696                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 697                 else
 698                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 699                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 700                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 701                                   2);
 702         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 703
 704
 705                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 706                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 707                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 708                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 709
 710                 if (ah->config.pcie_clock_req) {
 711                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 712                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 713                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 714                 } else {
 715                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 716                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 717                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 718                                   2);
 719                 }
 720         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 721                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 722                                ARRAY_SIZE(ar9285Modes_9285), 6);
 723                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 724                                ARRAY_SIZE(ar9285Common_9285), 2);
 725
 726                 if (ah->config.pcie_clock_req) {
 727                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 728                         ar9285PciePhy_clkreq_off_L1_9285,
 729                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 730                 } else {
 731                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 732                         ar9285PciePhy_clkreq_always_on_L1_9285,
 733                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 734                 }
 735         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 736                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 737                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 738                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 739                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 740
 741                 if (ah->config.pcie_clock_req) {
 742                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 743                                ar9280PciePhy_clkreq_off_L1_9280,
 744                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 745                 } else {
 746                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 747                                ar9280PciePhy_clkreq_always_on_L1_9280,
 748                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 749                 }
 750                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 751                                ar9280Modes_fast_clock_9280_2,
 752                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 753         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 754                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 755                                ARRAY_SIZE(ar9280Modes_9280), 6);
 756                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 757                                ARRAY_SIZE(ar9280Common_9280), 2);
 758         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 759                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 760                                ARRAY_SIZE(ar5416Modes_9160), 6);
 761                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 762                                ARRAY_SIZE(ar5416Common_9160), 2);
 763                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 764                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 765                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 766                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 767                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 768                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 769                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 770                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 771                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 772                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 773                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 774                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 775                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 776                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 777                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 778                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 779                 if (AR_SREV_9160_11(ah)) {
 780                         INIT_INI_ARRAY(&ah->iniAddac,
 781                                        ar5416Addac_91601_1,
 782                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 783                 } else {
 784                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 785                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 786                 }
 787         } else if (AR_SREV_9100_OR_LATER(ah)) {
 788                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 789                                ARRAY_SIZE(ar5416Modes_9100), 6);
 790                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 791                                ARRAY_SIZE(ar5416Common_9100), 2);
 792                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 793                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 794                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 795                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 796                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 797                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 798                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 799                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 800                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 801                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 802                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 803                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 804                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 805                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 806                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 807                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 808                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 809                                ARRAY_SIZE(ar5416Addac_9100), 2);
 810         } else {
 811                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 812                                ARRAY_SIZE(ar5416Modes), 6);
 813                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 814                                ARRAY_SIZE(ar5416Common), 2);
 815                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 816                                ARRAY_SIZE(ar5416Bank0), 2);
 817                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 818                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 819                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 820                                ARRAY_SIZE(ar5416Bank1), 2);
 821                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 822                                ARRAY_SIZE(ar5416Bank2), 2);
 823                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 824                                ARRAY_SIZE(ar5416Bank3), 3);
 825                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 826                                ARRAY_SIZE(ar5416Bank6), 3);
 827                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 828                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 829                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 830                                ARRAY_SIZE(ar5416Bank7), 2);
 831                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 832                                ARRAY_SIZE(ar5416Addac), 2);
 833         }
 834 }
 835
 836 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 837 {
 838         if (AR_SREV_9287_11(ah))
 839                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 840                 ar9287Modes_rx_gain_9287_1_1,
 841                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 842         else if (AR_SREV_9287_10(ah))
 843                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 844                 ar9287Modes_rx_gain_9287_1_0,
 845                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 846         else if (AR_SREV_9280_20(ah))
 847                 ath9k_hw_init_rxgain_ini(ah);
 848
 849         if (AR_SREV_9287_11(ah)) {
 850                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 851                 ar9287Modes_tx_gain_9287_1_1,
 852                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 853         } else if (AR_SREV_9287_10(ah)) {
 854                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 855                 ar9287Modes_tx_gain_9287_1_0,
 856                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 857         } else if (AR_SREV_9280_20(ah)) {
 858                 ath9k_hw_init_txgain_ini(ah);
 859         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 860                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 861
 862                 /* txgain table */
 863                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 864                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 865                         ar9285Modes_high_power_tx_gain_9285_1_2,
 866                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 867                 } else {
 868                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 869                         ar9285Modes_original_tx_gain_9285_1_2,
 870                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 871                 }
 872
 873         }
 874 }
 875
 876 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
 877 {
 878         u32 i, j;
 879
 880         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 881             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 882
 883                 /* EEPROM Fixup */
 884                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 885                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 886
 887                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 888                                 u32 val = INI_RA(&ah->iniModes, i, j);
 889
 890                                 INI_RA(&ah->iniModes, i, j) =
 891                                         ath9k_hw_ini_fixup(ah,
 892                                                            &ah->eeprom.def,
 893                                                            reg, val);
 894                         }
 895                 }
 896         }
 897 }
 898
 899 int ath9k_hw_init(struct ath_hw *ah)
 900 {
 901         int r;
 902
 903         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 904                 r = -EOPNOTSUPP;
 905                 goto bad;
 906         }
 907
 908         ath9k_hw_init_defaults(ah);
 909         ath9k_hw_init_config(ah);
 910
 911         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 912                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 913                 r = -EIO;
 914                 goto bad;
 915         }
 916
 917         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 918                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 919                 r = -EIO;
 920                 goto bad;
 921         }
 922
 923         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 924                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 925                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 926                         ah->config.serialize_regmode =
 927                                 SER_REG_MODE_ON;
 928                 } else {
 929                         ah->config.serialize_regmode =
 930                                 SER_REG_MODE_OFF;
 931                 }
 932         }
 933
 934         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 935                 ah->config.serialize_regmode);
 936
 937         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 938                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 939                         "Mac Chip Rev 0x%02x.%x is not supported by "
 940                         "this driver\n", ah->hw_version.macVersion,
 941                         ah->hw_version.macRev);
 942                 r = -EOPNOTSUPP;
 943                 goto bad;
 944         }
 945
 946         if (AR_SREV_9100(ah)) {
 947                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 948                 ah->supp_cals = IQ_MISMATCH_CAL;
 949                 ah->is_pciexpress = false;
 950         }
 951         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 952
 953         ath9k_hw_init_cal_settings(ah);
 954
 955         ah->ani_function = ATH9K_ANI_ALL;
 956         if (AR_SREV_9280_10_OR_LATER(ah))
 957                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 958
 959         ath9k_hw_init_mode_regs(ah);
 960
 961         if (ah->is_pciexpress)
 962                 ath9k_hw_configpcipowersave(ah, 0);
 963         else
 964                 ath9k_hw_disablepcie(ah);
 965
 966         r = ath9k_hw_post_init(ah);
 967         if (r)
 968                 goto bad;
 969
 970         ath9k_hw_init_mode_gain_regs(ah);
 971         ath9k_hw_fill_cap_info(ah);
 972         ath9k_hw_init_11a_eeprom_fix(ah);
 973
 974         r = ath9k_hw_init_macaddr(ah);
 975         if (r) {
 976                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 977                         "Failed to initialize MAC address\n");
 978                 goto bad;
 979         }
 980
 981         if (AR_SREV_9285(ah))
 982                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 983         else
 984                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 985
 986         ath9k_init_nfcal_hist_buffer(ah);
 987
 988         return 0;
 989 bad:
 990         ath9k_hw_detach(ah);
 991         return r;
 992 }
 993
 994 static void ath9k_hw_init_bb(struct ath_hw *ah,
 995                              struct ath9k_channel *chan)
 996 {
 997         u32 synthDelay;
 998
 999         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1000         if (IS_CHAN_B(chan))
1001                 synthDelay = (4 * synthDelay) / 22;
1002         else
1003                 synthDelay /= 10;
1004
1005         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1006
1007         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1008 }
1009
1010 static void ath9k_hw_init_qos(struct ath_hw *ah)
1011 {
1012         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1013         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1014
1015         REG_WRITE(ah, AR_QOS_NO_ACK,
1016                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1017                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1018                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1019
1020         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1021         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1022         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1023         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1024         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1025 }
1026
1027 static void ath9k_hw_init_pll(struct ath_hw *ah,
1028                               struct ath9k_channel *chan)
1029 {
1030         u32 pll;
1031
1032         if (AR_SREV_9100(ah)) {
1033                 if (chan && IS_CHAN_5GHZ(chan))
1034                         pll = 0x1450;
1035                 else
1036                         pll = 0x1458;
1037         } else {
1038                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1039                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1040
1041                         if (chan && IS_CHAN_HALF_RATE(chan))
1042                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1043                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1044                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1045
1046                         if (chan && IS_CHAN_5GHZ(chan)) {
1047                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1048
1049
1050                                 if (AR_SREV_9280_20(ah)) {
1051                                         if (((chan->channel % 20) == 0)
1052                                             || ((chan->channel % 10) == 0))
1053                                                 pll = 0x2850;
1054                                         else
1055                                                 pll = 0x142c;
1056                                 }
1057                         } else {
1058                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1059                         }
1060
1061                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1062
1063                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1064
1065                         if (chan && IS_CHAN_HALF_RATE(chan))
1066                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1067                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1068                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1069
1070                         if (chan && IS_CHAN_5GHZ(chan))
1071                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1072                         else
1073                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1074                 } else {
1075                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1076
1077                         if (chan && IS_CHAN_HALF_RATE(chan))
1078                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1079                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1080                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1081
1082                         if (chan && IS_CHAN_5GHZ(chan))
1083                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1084                         else
1085                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1086                 }
1087         }
1088         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1089
1090         udelay(RTC_PLL_SETTLE_DELAY);
1091
1092         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1093 }
1094
1095 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1096 {
1097         int rx_chainmask, tx_chainmask;
1098
1099         rx_chainmask = ah->rxchainmask;
1100         tx_chainmask = ah->txchainmask;
1101
1102         switch (rx_chainmask) {
1103         case 0x5:
1104                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1105                             AR_PHY_SWAP_ALT_CHAIN);
1106         case 0x3:
1107                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1108                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1109                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1110                         break;
1111                 }
1112         case 0x1:
1113         case 0x2:
1114         case 0x7:
1115                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1116                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1117                 break;
1118         default:
1119                 break;
1120         }
1121
1122         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1123         if (tx_chainmask == 0x5) {
1124                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1125                             AR_PHY_SWAP_ALT_CHAIN);
1126         }
1127         if (AR_SREV_9100(ah))
1128                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1129                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1130 }
1131
1132 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1133                                           enum nl80211_iftype opmode)
1134 {
1135         ah->mask_reg = AR_IMR_TXERR |
1136                 AR_IMR_TXURN |
1137                 AR_IMR_RXERR |
1138                 AR_IMR_RXORN |
1139                 AR_IMR_BCNMISC;
1140
1141         if (ah->config.intr_mitigation)
1142                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1143         else
1144                 ah->mask_reg |= AR_IMR_RXOK;
1145
1146         ah->mask_reg |= AR_IMR_TXOK;
1147
1148         if (opmode == NL80211_IFTYPE_AP)
1149                 ah->mask_reg |= AR_IMR_MIB;
1150
1151         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1152         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1153
1154         if (!AR_SREV_9100(ah)) {
1155                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1156                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1157                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1158         }
1159 }
1160
1161 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1162 {
1163         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1164                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1165                 ah->acktimeout = (u32) -1;
1166                 return false;
1167         } else {
1168                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1169                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1170                 ah->acktimeout = us;
1171                 return true;
1172         }
1173 }
1174
1175 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1176 {
1177         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1178                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1179                 ah->ctstimeout = (u32) -1;
1180                 return false;
1181         } else {
1182                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1183                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1184                 ah->ctstimeout = us;
1185                 return true;
1186         }
1187 }
1188
1189 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1190 {
1191         if (tu > 0xFFFF) {
1192                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1193                         "bad global tx timeout %u\n", tu);
1194                 ah->globaltxtimeout = (u32) -1;
1195                 return false;
1196         } else {
1197                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1198                 ah->globaltxtimeout = tu;
1199                 return true;
1200         }
1201 }
1202
1203 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1204 {
1205         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1206                 ah->misc_mode);
1207
1208         if (ah->misc_mode != 0)
1209                 REG_WRITE(ah, AR_PCU_MISC,
1210                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1211         if (ah->slottime != (u32) -1)
1212                 ath9k_hw_setslottime(ah, ah->slottime);
1213         if (ah->acktimeout != (u32) -1)
1214                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1215         if (ah->ctstimeout != (u32) -1)
1216                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1217         if (ah->globaltxtimeout != (u32) -1)
1218                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1219 }
1220
1221 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1222 {
1223         return vendorid == ATHEROS_VENDOR_ID ?
1224                 ath9k_hw_devname(devid) : NULL;
1225 }
1226
1227 void ath9k_hw_detach(struct ath_hw *ah)
1228 {
1229         if (!AR_SREV_9100(ah))
1230                 ath9k_hw_ani_disable(ah);
1231
1232         ath9k_hw_rf_free(ah);
1233         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1234         kfree(ah);
1235         ah = NULL;
1236 }
1237
1238 /*******/
1239 /* INI */
1240 /*******/
1241
1242 static void ath9k_hw_override_ini(struct ath_hw *ah,
1243                                   struct ath9k_channel *chan)
1244 {
1245         /*
1246          * Set the RX_ABORT and RX_DIS and clear if off only after
1247          * RXE is set for MAC. This prevents frames with corrupted
1248          * descriptor status.
1249          */
1250         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1251
1252
1253         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1254             AR_SREV_9280_10_OR_LATER(ah))
1255                 return;
1256
1257         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1258 }
1259
1260 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1261                               struct ar5416_eeprom_def *pEepData,
1262                               u32 reg, u32 value)
1263 {
1264         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1265
1266         switch (ah->hw_version.devid) {
1267         case AR9280_DEVID_PCI:
1268                 if (reg == 0x7894) {
1269                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1270                                 "ini VAL: %x  EEPROM: %x\n", value,
1271                                 (pBase->version & 0xff));
1272
1273                         if ((pBase->version & 0xff) > 0x0a) {
1274                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1275                                         "PWDCLKIND: %d\n",
1276                                         pBase->pwdclkind);
1277                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1278                                 value |= AR_AN_TOP2_PWDCLKIND &
1279                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1280                         } else {
1281                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1282                                         "PWDCLKIND Earlier Rev\n");
1283                         }
1284
1285                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1286                                 "final ini VAL: %x\n", value);
1287                 }
1288                 break;
1289         }
1290
1291         return value;
1292 }
1293
1294 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1295                               struct ar5416_eeprom_def *pEepData,
1296                               u32 reg, u32 value)
1297 {
1298         if (ah->eep_map == EEP_MAP_4KBITS)
1299                 return value;
1300         else
1301                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1302 }
1303
1304 static void ath9k_olc_init(struct ath_hw *ah)
1305 {
1306         u32 i;
1307
1308         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1309                 ah->originalGain[i] =
1310                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1311                                         AR_PHY_TX_GAIN);
1312         ah->PDADCdelta = 0;
1313 }
1314
1315 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1316                               struct ath9k_channel *chan)
1317 {
1318         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1319
1320         if (IS_CHAN_B(chan))
1321                 ctl |= CTL_11B;
1322         else if (IS_CHAN_G(chan))
1323                 ctl |= CTL_11G;
1324         else
1325                 ctl |= CTL_11A;
1326
1327         return ctl;
1328 }
1329
1330 static int ath9k_hw_process_ini(struct ath_hw *ah,
1331                                 struct ath9k_channel *chan,
1332                                 enum ath9k_ht_macmode macmode)
1333 {
1334         int i, regWrites = 0;
1335         struct ieee80211_channel *channel = chan->chan;
1336         u32 modesIndex, freqIndex;
1337
1338         switch (chan->chanmode) {
1339         case CHANNEL_A:
1340         case CHANNEL_A_HT20:
1341                 modesIndex = 1;
1342                 freqIndex = 1;
1343                 break;
1344         case CHANNEL_A_HT40PLUS:
1345         case CHANNEL_A_HT40MINUS:
1346                 modesIndex = 2;
1347                 freqIndex = 1;
1348                 break;
1349         case CHANNEL_G:
1350         case CHANNEL_G_HT20:
1351         case CHANNEL_B:
1352                 modesIndex = 4;
1353                 freqIndex = 2;
1354                 break;
1355         case CHANNEL_G_HT40PLUS:
1356         case CHANNEL_G_HT40MINUS:
1357                 modesIndex = 3;
1358                 freqIndex = 2;
1359                 break;
1360
1361         default:
1362                 return -EINVAL;
1363         }
1364
1365         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1366         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1367         ah->eep_ops->set_addac(ah, chan);
1368
1369         if (AR_SREV_5416_22_OR_LATER(ah)) {
1370                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1371         } else {
1372                 struct ar5416IniArray temp;
1373                 u32 addacSize =
1374                         sizeof(u32) * ah->iniAddac.ia_rows *
1375                         ah->iniAddac.ia_columns;
1376
1377                 memcpy(ah->addac5416_21,
1378                        ah->iniAddac.ia_array, addacSize);
1379
1380                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1381
1382                 temp.ia_array = ah->addac5416_21;
1383                 temp.ia_columns = ah->iniAddac.ia_columns;
1384                 temp.ia_rows = ah->iniAddac.ia_rows;
1385                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1386         }
1387
1388         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1389
1390         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1391                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1392                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1393
1394                 REG_WRITE(ah, reg, val);
1395
1396                 if (reg >= 0x7800 && reg < 0x78a0
1397                     && ah->config.analog_shiftreg) {
1398                         udelay(100);
1399                 }
1400
1401                 DO_DELAY(regWrites);
1402         }
1403
1404         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1405                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1406
1407         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1408             AR_SREV_9287_10_OR_LATER(ah))
1409                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1410
1411         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1412                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1413                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1414
1415                 REG_WRITE(ah, reg, val);
1416
1417                 if (reg >= 0x7800 && reg < 0x78a0
1418                     && ah->config.analog_shiftreg) {
1419                         udelay(100);
1420                 }
1421
1422                 DO_DELAY(regWrites);
1423         }
1424
1425         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1426
1427         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1428                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1429                                 regWrites);
1430         }
1431
1432         ath9k_hw_override_ini(ah, chan);
1433         ath9k_hw_set_regs(ah, chan, macmode);
1434         ath9k_hw_init_chain_masks(ah);
1435
1436         if (OLC_FOR_AR9280_20_LATER)
1437                 ath9k_olc_init(ah);
1438
1439         ah->eep_ops->set_txpower(ah, chan,
1440                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1441                                  channel->max_antenna_gain * 2,
1442                                  channel->max_power * 2,
1443                                  min((u32) MAX_RATE_POWER,
1444                                  (u32) ah->regulatory.power_limit));
1445
1446         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1447                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1448                         "ar5416SetRfRegs failed\n");
1449                 return -EIO;
1450         }
1451
1452         return 0;
1453 }
1454
1455 /****************************************/
1456 /* Reset and Channel Switching Routines */
1457 /****************************************/
1458
1459 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1460 {
1461         u32 rfMode = 0;
1462
1463         if (chan == NULL)
1464                 return;
1465
1466         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1467                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1468
1469         if (!AR_SREV_9280_10_OR_LATER(ah))
1470                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1471                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1472
1473         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1474                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1475
1476         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1477 }
1478
1479 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1480 {
1481         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1482 }
1483
1484 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1485 {
1486         u32 regval;
1487
1488         regval = REG_READ(ah, AR_AHB_MODE);
1489         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1490
1491         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1492         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1493
1494         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1495
1496         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1497         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1498
1499         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1500
1501         if (AR_SREV_9285(ah)) {
1502                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1503                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1504         } else {
1505                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1506                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1507         }
1508 }
1509
1510 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1511 {
1512         u32 val;
1513
1514         val = REG_READ(ah, AR_STA_ID1);
1515         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1516         switch (opmode) {
1517         case NL80211_IFTYPE_AP:
1518                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1519                           | AR_STA_ID1_KSRCH_MODE);
1520                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1521                 break;
1522         case NL80211_IFTYPE_ADHOC:
1523         case NL80211_IFTYPE_MESH_POINT:
1524                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1525                           | AR_STA_ID1_KSRCH_MODE);
1526                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1527                 break;
1528         case NL80211_IFTYPE_STATION:
1529         case NL80211_IFTYPE_MONITOR:
1530                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1531                 break;
1532         }
1533 }
1534
1535 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1536                                                  u32 coef_scaled,
1537                                                  u32 *coef_mantissa,
1538                                                  u32 *coef_exponent)
1539 {
1540         u32 coef_exp, coef_man;
1541
1542         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1543                 if ((coef_scaled >> coef_exp) & 0x1)
1544                         break;
1545
1546         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1547
1548         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1549
1550         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1551         *coef_exponent = coef_exp - 16;
1552 }
1553
1554 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1555                                      struct ath9k_channel *chan)
1556 {
1557         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1558         u32 clockMhzScaled = 0x64000000;
1559         struct chan_centers centers;
1560
1561         if (IS_CHAN_HALF_RATE(chan))
1562                 clockMhzScaled = clockMhzScaled >> 1;
1563         else if (IS_CHAN_QUARTER_RATE(chan))
1564                 clockMhzScaled = clockMhzScaled >> 2;
1565
1566         ath9k_hw_get_channel_centers(ah, chan, &centers);
1567         coef_scaled = clockMhzScaled / centers.synth_center;
1568
1569         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1570                                       &ds_coef_exp);
1571
1572         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1573                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1574         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1575                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1576
1577         coef_scaled = (9 * coef_scaled) / 10;
1578
1579         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1580                                       &ds_coef_exp);
1581
1582         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1583                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1584         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1585                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1586 }
1587
1588 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1589 {
1590         u32 rst_flags;
1591         u32 tmpReg;
1592
1593         if (AR_SREV_9100(ah)) {
1594                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1595                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1596                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1597                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1598                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1599         }
1600
1601         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1602                   AR_RTC_FORCE_WAKE_ON_INT);
1603
1604         if (AR_SREV_9100(ah)) {
1605                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1606                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1607         } else {
1608                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1609                 if (tmpReg &
1610                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1611                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1612                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1613                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1614                 } else {
1615                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1616                 }
1617
1618                 rst_flags = AR_RTC_RC_MAC_WARM;
1619                 if (type == ATH9K_RESET_COLD)
1620                         rst_flags |= AR_RTC_RC_MAC_COLD;
1621         }
1622
1623         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1624         udelay(50);
1625
1626         REG_WRITE(ah, AR_RTC_RC, 0);
1627         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1628                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1629                         "RTC stuck in MAC reset\n");
1630                 return false;
1631         }
1632
1633         if (!AR_SREV_9100(ah))
1634                 REG_WRITE(ah, AR_RC, 0);
1635
1636         ath9k_hw_init_pll(ah, NULL);
1637
1638         if (AR_SREV_9100(ah))
1639                 udelay(50);
1640
1641         return true;
1642 }
1643
1644 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1645 {
1646         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1647                   AR_RTC_FORCE_WAKE_ON_INT);
1648
1649         REG_WRITE(ah, AR_RTC_RESET, 0);
1650         udelay(2);
1651         REG_WRITE(ah, AR_RTC_RESET, 1);
1652
1653         if (!ath9k_hw_wait(ah,
1654                            AR_RTC_STATUS,
1655                            AR_RTC_STATUS_M,
1656                            AR_RTC_STATUS_ON,
1657                            AH_WAIT_TIMEOUT)) {
1658                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1659                 return false;
1660         }
1661
1662         ath9k_hw_read_revisions(ah);
1663
1664         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1665 }
1666
1667 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1668 {
1669         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1670                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1671
1672         switch (type) {
1673         case ATH9K_RESET_POWER_ON:
1674                 return ath9k_hw_set_reset_power_on(ah);
1675         case ATH9K_RESET_WARM:
1676         case ATH9K_RESET_COLD:
1677                 return ath9k_hw_set_reset(ah, type);
1678         default:
1679                 return false;
1680         }
1681 }
1682
1683 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1684                               enum ath9k_ht_macmode macmode)
1685 {
1686         u32 phymode;
1687         u32 enableDacFifo = 0;
1688
1689         if (AR_SREV_9285_10_OR_LATER(ah))
1690                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1691                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1692
1693         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1694                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1695
1696         if (IS_CHAN_HT40(chan)) {
1697                 phymode |= AR_PHY_FC_DYN2040_EN;
1698
1699                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1700                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1701                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1702
1703                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1704                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1705         }
1706         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1707
1708         ath9k_hw_set11nmac2040(ah, macmode);
1709
1710         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1711         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1712 }
1713
1714 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1715                                 struct ath9k_channel *chan)
1716 {
1717         if (OLC_FOR_AR9280_20_LATER) {
1718                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1719                         return false;
1720         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1721                 return false;
1722
1723         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1724                 return false;
1725
1726         ah->chip_fullsleep = false;
1727         ath9k_hw_init_pll(ah, chan);
1728         ath9k_hw_set_rfmode(ah, chan);
1729
1730         return true;
1731 }
1732
1733 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1734                                     struct ath9k_channel *chan,
1735                                     enum ath9k_ht_macmode macmode)
1736 {
1737         struct ieee80211_channel *channel = chan->chan;
1738         u32 synthDelay, qnum;
1739
1740         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1741                 if (ath9k_hw_numtxpending(ah, qnum)) {
1742                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1743                                 "Transmit frames pending on queue %d\n", qnum);
1744                         return false;
1745                 }
1746         }
1747
1748         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1749         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1750                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1751                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1752                         "Could not kill baseband RX\n");
1753                 return false;
1754         }
1755
1756         ath9k_hw_set_regs(ah, chan, macmode);
1757
1758         if (AR_SREV_9280_10_OR_LATER(ah)) {
1759                 ath9k_hw_ar9280_set_channel(ah, chan);
1760         } else {
1761                 if (!(ath9k_hw_set_channel(ah, chan))) {
1762                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1763                                 "Failed to set channel\n");
1764                         return false;
1765                 }
1766         }
1767
1768         ah->eep_ops->set_txpower(ah, chan,
1769                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1770                              channel->max_antenna_gain * 2,
1771                              channel->max_power * 2,
1772                              min((u32) MAX_RATE_POWER,
1773                              (u32) ah->regulatory.power_limit));
1774
1775         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1776         if (IS_CHAN_B(chan))
1777                 synthDelay = (4 * synthDelay) / 22;
1778         else
1779                 synthDelay /= 10;
1780
1781         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1782
1783         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1784
1785         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1786                 ath9k_hw_set_delta_slope(ah, chan);
1787
1788         if (AR_SREV_9280_10_OR_LATER(ah))
1789                 ath9k_hw_9280_spur_mitigate(ah, chan);
1790         else
1791                 ath9k_hw_spur_mitigate(ah, chan);
1792
1793         if (!chan->oneTimeCalsDone)
1794                 chan->oneTimeCalsDone = true;
1795
1796         return true;
1797 }
1798
1799 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1800 {
1801         int bb_spur = AR_NO_SPUR;
1802         int freq;
1803         int bin, cur_bin;
1804         int bb_spur_off, spur_subchannel_sd;
1805         int spur_freq_sd;
1806         int spur_delta_phase;
1807         int denominator;
1808         int upper, lower, cur_vit_mask;
1809         int tmp, newVal;
1810         int i;
1811         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1812                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1813         };
1814         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1815                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1816         };
1817         int inc[4] = { 0, 100, 0, 0 };
1818         struct chan_centers centers;
1819
1820         int8_t mask_m[123];
1821         int8_t mask_p[123];
1822         int8_t mask_amt;
1823         int tmp_mask;
1824         int cur_bb_spur;
1825         bool is2GHz = IS_CHAN_2GHZ(chan);
1826
1827         memset(&mask_m, 0, sizeof(int8_t) * 123);
1828         memset(&mask_p, 0, sizeof(int8_t) * 123);
1829
1830         ath9k_hw_get_channel_centers(ah, chan, &centers);
1831         freq = centers.synth_center;
1832
1833         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1834         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1835                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1836
1837                 if (is2GHz)
1838                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1839                 else
1840                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1841
1842                 if (AR_NO_SPUR == cur_bb_spur)
1843                         break;
1844                 cur_bb_spur = cur_bb_spur - freq;
1845
1846                 if (IS_CHAN_HT40(chan)) {
1847                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1848                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1849                                 bb_spur = cur_bb_spur;
1850                                 break;
1851                         }
1852                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1853                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1854                         bb_spur = cur_bb_spur;
1855                         break;
1856                 }
1857         }
1858
1859         if (AR_NO_SPUR == bb_spur) {
1860                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1861                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1862                 return;
1863         } else {
1864                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1865                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1866         }
1867
1868         bin = bb_spur * 320;
1869
1870         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1871
1872         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1873                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1874                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1875                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1876         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1877
1878         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1879                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1880                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1881                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1882                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1883         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1884
1885         if (IS_CHAN_HT40(chan)) {
1886                 if (bb_spur < 0) {
1887                         spur_subchannel_sd = 1;
1888                         bb_spur_off = bb_spur + 10;
1889                 } else {
1890                         spur_subchannel_sd = 0;
1891                         bb_spur_off = bb_spur - 10;
1892                 }
1893         } else {
1894                 spur_subchannel_sd = 0;
1895                 bb_spur_off = bb_spur;
1896         }
1897
1898         if (IS_CHAN_HT40(chan))
1899                 spur_delta_phase =
1900                         ((bb_spur * 262144) /
1901                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1902         else
1903                 spur_delta_phase =
1904                         ((bb_spur * 524288) /
1905                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1906
1907         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1908         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1909
1910         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1911                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1912                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1913         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1914
1915         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1916         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1917
1918         cur_bin = -6000;
1919         upper = bin + 100;
1920         lower = bin - 100;
1921
1922         for (i = 0; i < 4; i++) {
1923                 int pilot_mask = 0;
1924                 int chan_mask = 0;
1925                 int bp = 0;
1926                 for (bp = 0; bp < 30; bp++) {
1927                         if ((cur_bin > lower) && (cur_bin < upper)) {
1928                                 pilot_mask = pilot_mask | 0x1 << bp;
1929                                 chan_mask = chan_mask | 0x1 << bp;
1930                         }
1931                         cur_bin += 100;
1932                 }
1933                 cur_bin += inc[i];
1934                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1935                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1936         }
1937
1938         cur_vit_mask = 6100;
1939         upper = bin + 120;
1940         lower = bin - 120;
1941
1942         for (i = 0; i < 123; i++) {
1943                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1944
1945                         /* workaround for gcc bug #37014 */
1946                         volatile int tmp_v = abs(cur_vit_mask - bin);
1947
1948                         if (tmp_v < 75)
1949                                 mask_amt = 1;
1950                         else
1951                                 mask_amt = 0;
1952                         if (cur_vit_mask < 0)
1953                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1954                         else
1955                                 mask_p[cur_vit_mask / 100] = mask_amt;
1956                 }
1957                 cur_vit_mask -= 100;
1958         }
1959
1960         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1961                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1962                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1963                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1964                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1965                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1966                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1967                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1968         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1969         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1970
1971         tmp_mask = (mask_m[31] << 28)
1972                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1973                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1974                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1975                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1976                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1977                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1978                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1979         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1980         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1981
1982         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1983                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1984                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1985                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1986                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1987                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1988                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1989                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1990         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1991         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1992
1993         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1994                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1995                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1996                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1997                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1998                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1999                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2000                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2001         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2002         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2003
2004         tmp_mask = (mask_p[15] << 28)
2005                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2006                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2007                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2008                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2009                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2010                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2011                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2012         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2013         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2014
2015         tmp_mask = (mask_p[30] << 28)
2016                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2017                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2018                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2019                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2020                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2021                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2022                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2023         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2024         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2025
2026         tmp_mask = (mask_p[45] << 28)
2027                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2028                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2029                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2030                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2031                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2032                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2033                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2034         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2035         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2036
2037         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2038                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2039                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2040                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2041                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2042                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2043                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2044                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2045         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2046         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2047 }
2048
2049 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2050 {
2051         int bb_spur = AR_NO_SPUR;
2052         int bin, cur_bin;
2053         int spur_freq_sd;
2054         int spur_delta_phase;
2055         int denominator;
2056         int upper, lower, cur_vit_mask;
2057         int tmp, new;
2058         int i;
2059         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2060                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2061         };
2062         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2063                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2064         };
2065         int inc[4] = { 0, 100, 0, 0 };
2066
2067         int8_t mask_m[123];
2068         int8_t mask_p[123];
2069         int8_t mask_amt;
2070         int tmp_mask;
2071         int cur_bb_spur;
2072         bool is2GHz = IS_CHAN_2GHZ(chan);
2073
2074         memset(&mask_m, 0, sizeof(int8_t) * 123);
2075         memset(&mask_p, 0, sizeof(int8_t) * 123);
2076
2077         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2078                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2079                 if (AR_NO_SPUR == cur_bb_spur)
2080                         break;
2081                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2082                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2083                         bb_spur = cur_bb_spur;
2084                         break;
2085                 }
2086         }
2087
2088         if (AR_NO_SPUR == bb_spur)
2089                 return;
2090
2091         bin = bb_spur * 32;
2092
2093         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2094         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2095                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2096                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2097                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2098
2099         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2100
2101         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2102                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2103                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2104                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2105                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2106         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2107
2108         spur_delta_phase = ((bb_spur * 524288) / 100) &
2109                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2110
2111         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2112         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2113
2114         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2115                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2116                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2117         REG_WRITE(ah, AR_PHY_TIMING11, new);
2118
2119         cur_bin = -6000;
2120         upper = bin + 100;
2121         lower = bin - 100;
2122
2123         for (i = 0; i < 4; i++) {
2124                 int pilot_mask = 0;
2125                 int chan_mask = 0;
2126                 int bp = 0;
2127                 for (bp = 0; bp < 30; bp++) {
2128                         if ((cur_bin > lower) && (cur_bin < upper)) {
2129                                 pilot_mask = pilot_mask | 0x1 << bp;
2130                                 chan_mask = chan_mask | 0x1 << bp;
2131                         }
2132                         cur_bin += 100;
2133                 }
2134                 cur_bin += inc[i];
2135                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2136                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2137         }
2138
2139         cur_vit_mask = 6100;
2140         upper = bin + 120;
2141         lower = bin - 120;
2142
2143         for (i = 0; i < 123; i++) {
2144                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2145
2146                         /* workaround for gcc bug #37014 */
2147                         volatile int tmp_v = abs(cur_vit_mask - bin);
2148
2149                         if (tmp_v < 75)
2150                                 mask_amt = 1;
2151                         else
2152                                 mask_amt = 0;
2153                         if (cur_vit_mask < 0)
2154                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2155                         else
2156                                 mask_p[cur_vit_mask / 100] = mask_amt;
2157                 }
2158                 cur_vit_mask -= 100;
2159         }
2160
2161         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2162                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2163                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2164                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2165                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2166                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2167                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2168                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2169         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2170         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2171
2172         tmp_mask = (mask_m[31] << 28)
2173                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2174                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2175                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2176                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2177                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2178                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2179                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2180         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2181         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2182
2183         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2184                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2185                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2186                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2187                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2188                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2189                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2190                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2191         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2192         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2193
2194         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2195                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2196                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2197                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2198                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2199                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2200                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2201                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2202         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2203         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2204
2205         tmp_mask = (mask_p[15] << 28)
2206                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2207                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2208                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2209                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2210                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2211                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2212                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2213         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2214         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2215
2216         tmp_mask = (mask_p[30] << 28)
2217                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2218                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2219                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2220                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2221                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2222                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2223                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2224         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2225         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2226
2227         tmp_mask = (mask_p[45] << 28)
2228                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2229                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2230                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2231                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2232                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2233                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2234                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2235         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2236         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2237
2238         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2239                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2240                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2241                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2242                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2243                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2244                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2245                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2246         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2247         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2248 }
2249
2250 static void ath9k_enable_rfkill(struct ath_hw *ah)
2251 {
2252         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2253                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2254
2255         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2256                     AR_GPIO_INPUT_MUX2_RFSILENT);
2257
2258         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2259         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2260 }
2261
2262 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2263                     bool bChannelChange)
2264 {
2265         u32 saveLedState;
2266         struct ath_softc *sc = ah->ah_sc;
2267         struct ath9k_channel *curchan = ah->curchan;
2268         u32 saveDefAntenna;
2269         u32 macStaId1;
2270         int i, rx_chainmask, r;
2271
2272         ah->extprotspacing = sc->ht_extprotspacing;
2273         ah->txchainmask = sc->tx_chainmask;
2274         ah->rxchainmask = sc->rx_chainmask;
2275
2276         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2277                 return -EIO;
2278
2279         if (curchan)
2280                 ath9k_hw_getnf(ah, curchan);
2281
2282         if (bChannelChange &&
2283             (ah->chip_fullsleep != true) &&
2284             (ah->curchan != NULL) &&
2285             (chan->channel != ah->curchan->channel) &&
2286             ((chan->channelFlags & CHANNEL_ALL) ==
2287              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2288             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2289                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2290
2291                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2292                         ath9k_hw_loadnf(ah, ah->curchan);
2293                         ath9k_hw_start_nfcal(ah);
2294                         return 0;
2295                 }
2296         }
2297
2298         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2299         if (saveDefAntenna == 0)
2300                 saveDefAntenna = 1;
2301
2302         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2303
2304         saveLedState = REG_READ(ah, AR_CFG_LED) &
2305                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2306                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2307
2308         ath9k_hw_mark_phy_inactive(ah);
2309
2310         if (!ath9k_hw_chip_reset(ah, chan)) {
2311                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2312                 return -EINVAL;
2313         }
2314
2315         if (AR_SREV_9280_10_OR_LATER(ah))
2316                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2317
2318         if (AR_SREV_9287_10_OR_LATER(ah)) {
2319                 /* Enable ASYNC FIFO */
2320                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2321                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2322                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2323                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2324                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2325                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2326                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2327         }
2328         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2329         if (r)
2330                 return r;
2331
2332         /* Setup MFP options for CCMP */
2333         if (AR_SREV_9280_20_OR_LATER(ah)) {
2334                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2335                  * frames when constructing CCMP AAD. */
2336                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2337                               0xc7ff);
2338                 ah->sw_mgmt_crypto = false;
2339         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2340                 /* Disable hardware crypto for management frames */
2341                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2342                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2343                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2344                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2345                 ah->sw_mgmt_crypto = true;
2346         } else
2347                 ah->sw_mgmt_crypto = true;
2348
2349         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2350                 ath9k_hw_set_delta_slope(ah, chan);
2351
2352         if (AR_SREV_9280_10_OR_LATER(ah))
2353                 ath9k_hw_9280_spur_mitigate(ah, chan);
2354         else
2355                 ath9k_hw_spur_mitigate(ah, chan);
2356
2357         ah->eep_ops->set_board_values(ah, chan);
2358
2359         ath9k_hw_decrease_chain_power(ah, chan);
2360
2361         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2362         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2363                   | macStaId1
2364                   | AR_STA_ID1_RTS_USE_DEF
2365                   | (ah->config.
2366                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2367                   | ah->sta_id1_defaults);
2368         ath9k_hw_set_operating_mode(ah, ah->opmode);
2369
2370         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2371         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2372
2373         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2374
2375         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2376         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2377                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2378
2379         REG_WRITE(ah, AR_ISR, ~0);
2380
2381         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2382
2383         if (AR_SREV_9280_10_OR_LATER(ah))
2384                 ath9k_hw_ar9280_set_channel(ah, chan);
2385         else
2386                 if (!(ath9k_hw_set_channel(ah, chan)))
2387                         return -EIO;
2388
2389         for (i = 0; i < AR_NUM_DCU; i++)
2390                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2391
2392         ah->intr_txqs = 0;
2393         for (i = 0; i < ah->caps.total_queues; i++)
2394                 ath9k_hw_resettxqueue(ah, i);
2395
2396         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2397         ath9k_hw_init_qos(ah);
2398
2399         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2400                 ath9k_enable_rfkill(ah);
2401
2402         ath9k_hw_init_user_settings(ah);
2403
2404         if (AR_SREV_9287_10_OR_LATER(ah)) {
2405                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2406                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2407                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2408                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2409                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2410                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2411
2412                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2413                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2414
2415                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2416                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2417                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2418                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2419         }
2420         if (AR_SREV_9287_10_OR_LATER(ah)) {
2421                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2422                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2423         }
2424
2425         REG_WRITE(ah, AR_STA_ID1,
2426                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2427
2428         ath9k_hw_set_dma(ah);
2429
2430         REG_WRITE(ah, AR_OBS, 8);
2431
2432         if (ah->config.intr_mitigation) {
2433                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2434                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2435         }
2436
2437         ath9k_hw_init_bb(ah, chan);
2438
2439         if (!ath9k_hw_init_cal(ah, chan))
2440                 return -EIO;
2441
2442         rx_chainmask = ah->rxchainmask;
2443         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2444                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2445                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2446         }
2447
2448         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2449
2450         if (AR_SREV_9100(ah)) {
2451                 u32 mask;
2452                 mask = REG_READ(ah, AR_CFG);
2453                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2454                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2455                                 "CFG Byte Swap Set 0x%x\n", mask);
2456                 } else {
2457                         mask =
2458                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2459                         REG_WRITE(ah, AR_CFG, mask);
2460                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2461                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2462                 }
2463         } else {
2464 #ifdef __BIG_ENDIAN
2465                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2466 #endif
2467         }
2468
2469         return 0;
2470 }
2471
2472 /************************/
2473 /* Key Cache Management */
2474 /************************/
2475
2476 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2477 {
2478         u32 keyType;
2479
2480         if (entry >= ah->caps.keycache_size) {
2481                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2482                         "keychache entry %u out of range\n", entry);
2483                 return false;
2484         }
2485
2486         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2487
2488         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2489         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2490         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2491         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2492         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2493         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2494         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2495         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2496
2497         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2498                 u16 micentry = entry + 64;
2499
2500                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2501                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2502                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2503                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2504
2505         }
2506
2507         if (ah->curchan == NULL)
2508                 return true;
2509
2510         return true;
2511 }
2512
2513 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2514 {
2515         u32 macHi, macLo;
2516
2517         if (entry >= ah->caps.keycache_size) {
2518                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2519                         "keychache entry %u out of range\n", entry);
2520                 return false;
2521         }
2522
2523         if (mac != NULL) {
2524                 macHi = (mac[5] << 8) | mac[4];
2525                 macLo = (mac[3] << 24) |
2526                         (mac[2] << 16) |
2527                         (mac[1] << 8) |
2528                         mac[0];
2529                 macLo >>= 1;
2530                 macLo |= (macHi & 1) << 31;
2531                 macHi >>= 1;
2532         } else {
2533                 macLo = macHi = 0;
2534         }
2535         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2536         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2537
2538         return true;
2539 }
2540
2541 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2542                                  const struct ath9k_keyval *k,
2543                                  const u8 *mac)
2544 {
2545         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2546         u32 key0, key1, key2, key3, key4;
2547         u32 keyType;
2548
2549         if (entry >= pCap->keycache_size) {
2550                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2551                         "keycache entry %u out of range\n", entry);
2552                 return false;
2553         }
2554
2555         switch (k->kv_type) {
2556         case ATH9K_CIPHER_AES_OCB:
2557                 keyType = AR_KEYTABLE_TYPE_AES;
2558                 break;
2559         case ATH9K_CIPHER_AES_CCM:
2560                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2561                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2562                                 "AES-CCM not supported by mac rev 0x%x\n",
2563                                 ah->hw_version.macRev);
2564                         return false;
2565                 }
2566                 keyType = AR_KEYTABLE_TYPE_CCM;
2567                 break;
2568         case ATH9K_CIPHER_TKIP:
2569                 keyType = AR_KEYTABLE_TYPE_TKIP;
2570                 if (ATH9K_IS_MIC_ENABLED(ah)
2571                     && entry + 64 >= pCap->keycache_size) {
2572                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2573                                 "entry %u inappropriate for TKIP\n", entry);
2574                         return false;
2575                 }
2576                 break;
2577         case ATH9K_CIPHER_WEP:
2578                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2579                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2580                                 "WEP key length %u too small\n", k->kv_len);
2581                         return false;
2582                 }
2583                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2584                         keyType = AR_KEYTABLE_TYPE_40;
2585                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2586                         keyType = AR_KEYTABLE_TYPE_104;
2587                 else
2588                         keyType = AR_KEYTABLE_TYPE_128;
2589                 break;
2590         case ATH9K_CIPHER_CLR:
2591                 keyType = AR_KEYTABLE_TYPE_CLR;
2592                 break;
2593         default:
2594                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2595                         "cipher %u not supported\n", k->kv_type);
2596                 return false;
2597         }
2598
2599         key0 = get_unaligned_le32(k->kv_val + 0);
2600         key1 = get_unaligned_le16(k->kv_val + 4);
2601         key2 = get_unaligned_le32(k->kv_val + 6);
2602         key3 = get_unaligned_le16(k->kv_val + 10);
2603         key4 = get_unaligned_le32(k->kv_val + 12);
2604         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2605                 key4 &= 0xff;
2606
2607         /*
2608          * Note: Key cache registers access special memory area that requires
2609          * two 32-bit writes to actually update the values in the internal
2610          * memory. Consequently, the exact order and pairs used here must be
2611          * maintained.
2612          */
2613
2614         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2615                 u16 micentry = entry + 64;
2616
2617                 /*
2618                  * Write inverted key[47:0] first to avoid Michael MIC errors
2619                  * on frames that could be sent or received at the same time.
2620                  * The correct key will be written in the end once everything
2621                  * else is ready.
2622                  */
2623                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2624                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2625
2626                 /* Write key[95:48] */
2627                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2628                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2629
2630                 /* Write key[127:96] and key type */
2631                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2632                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2633
2634                 /* Write MAC address for the entry */
2635                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2636
2637                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2638                         /*
2639                          * TKIP uses two key cache entries:
2640                          * Michael MIC TX/RX keys in the same key cache entry
2641                          * (idx = main index + 64):
2642                          * key0 [31:0] = RX key [31:0]
2643                          * key1 [15:0] = TX key [31:16]
2644                          * key1 [31:16] = reserved
2645                          * key2 [31:0] = RX key [63:32]
2646                          * key3 [15:0] = TX key [15:0]
2647                          * key3 [31:16] = reserved
2648                          * key4 [31:0] = TX key [63:32]
2649                          */
2650                         u32 mic0, mic1, mic2, mic3, mic4;
2651
2652                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2653                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2654                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2655                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2656                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2657
2658                         /* Write RX[31:0] and TX[31:16] */
2659                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2660                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2661
2662                         /* Write RX[63:32] and TX[15:0] */
2663                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2664                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2665
2666                         /* Write TX[63:32] and keyType(reserved) */
2667                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2668                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2669                                   AR_KEYTABLE_TYPE_CLR);
2670
2671                 } else {
2672                         /*
2673                          * TKIP uses four key cache entries (two for group
2674                          * keys):
2675                          * Michael MIC TX/RX keys are in different key cache
2676                          * entries (idx = main index + 64 for TX and
2677                          * main index + 32 + 96 for RX):
2678                          * key0 [31:0] = TX/RX MIC key [31:0]
2679                          * key1 [31:0] = reserved
2680                          * key2 [31:0] = TX/RX MIC key [63:32]
2681                          * key3 [31:0] = reserved
2682                          * key4 [31:0] = reserved
2683                          *
2684                          * Upper layer code will call this function separately
2685                          * for TX and RX keys when these registers offsets are
2686                          * used.
2687                          */
2688                         u32 mic0, mic2;
2689
2690                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2691                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2692
2693                         /* Write MIC key[31:0] */
2694                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2695                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2696
2697                         /* Write MIC key[63:32] */
2698                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2699                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2700
2701                         /* Write TX[63:32] and keyType(reserved) */
2702                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2703                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2704                                   AR_KEYTABLE_TYPE_CLR);
2705                 }
2706
2707                 /* MAC address registers are reserved for the MIC entry */
2708                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2709                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2710
2711                 /*
2712                  * Write the correct (un-inverted) key[47:0] last to enable
2713                  * TKIP now that all other registers are set with correct
2714                  * values.
2715                  */
2716                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2717                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2718         } else {
2719                 /* Write key[47:0] */
2720                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2721                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2722
2723                 /* Write key[95:48] */
2724                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2725                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2726
2727                 /* Write key[127:96] and key type */
2728                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2729                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2730
2731                 /* Write MAC address for the entry */
2732                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2733         }
2734
2735         return true;
2736 }
2737
2738 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2739 {
2740         if (entry < ah->caps.keycache_size) {
2741                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2742                 if (val & AR_KEYTABLE_VALID)
2743                         return true;
2744         }
2745         return false;
2746 }
2747
2748 /******************************/
2749 /* Power Management (Chipset) */
2750 /******************************/
2751
2752 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2753 {
2754         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2755         if (setChip) {
2756                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2757                             AR_RTC_FORCE_WAKE_EN);
2758                 if (!AR_SREV_9100(ah))
2759                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2760
2761                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2762                             AR_RTC_RESET_EN);
2763         }
2764 }
2765
2766 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2767 {
2768         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2769         if (setChip) {
2770                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2771
2772                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2773                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2774                                   AR_RTC_FORCE_WAKE_ON_INT);
2775                 } else {
2776                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2777                                     AR_RTC_FORCE_WAKE_EN);
2778                 }
2779         }
2780 }
2781
2782 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2783 {
2784         u32 val;
2785         int i;
2786
2787         if (setChip) {
2788                 if ((REG_READ(ah, AR_RTC_STATUS) &
2789                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2790                         if (ath9k_hw_set_reset_reg(ah,
2791                                            ATH9K_RESET_POWER_ON) != true) {
2792                                 return false;
2793                         }
2794                 }
2795                 if (AR_SREV_9100(ah))
2796                         REG_SET_BIT(ah, AR_RTC_RESET,
2797                                     AR_RTC_RESET_EN);
2798
2799                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2800                             AR_RTC_FORCE_WAKE_EN);
2801                 udelay(50);
2802
2803                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2804                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2805                         if (val == AR_RTC_STATUS_ON)
2806                                 break;
2807                         udelay(50);
2808                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2809                                     AR_RTC_FORCE_WAKE_EN);
2810                 }
2811                 if (i == 0) {
2812                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2813                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2814                         return false;
2815                 }
2816         }
2817
2818         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2819
2820         return true;
2821 }
2822
2823 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2824                                      enum ath9k_power_mode mode)
2825 {
2826         int status = true, setChip = true;
2827         static const char *modes[] = {
2828                 "AWAKE",
2829                 "FULL-SLEEP",
2830                 "NETWORK SLEEP",
2831                 "UNDEFINED"
2832         };
2833
2834         if (ah->power_mode == mode)
2835                 return status;
2836
2837         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2838                 modes[ah->power_mode], modes[mode]);
2839
2840         switch (mode) {
2841         case ATH9K_PM_AWAKE:
2842                 status = ath9k_hw_set_power_awake(ah, setChip);
2843                 break;
2844         case ATH9K_PM_FULL_SLEEP:
2845                 ath9k_set_power_sleep(ah, setChip);
2846                 ah->chip_fullsleep = true;
2847                 break;
2848         case ATH9K_PM_NETWORK_SLEEP:
2849                 ath9k_set_power_network_sleep(ah, setChip);
2850                 break;
2851         default:
2852                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2853                         "Unknown power mode %u\n", mode);
2854                 return false;
2855         }
2856         ah->power_mode = mode;
2857
2858         return status;
2859 }
2860
2861 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2862 {
2863         unsigned long flags;
2864         bool ret;
2865
2866         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2867         ret = ath9k_hw_setpower_nolock(ah, mode);
2868         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2869
2870         return ret;
2871 }
2872
2873 void ath9k_ps_wakeup(struct ath_softc *sc)
2874 {
2875         unsigned long flags;
2876
2877         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2878         if (++sc->ps_usecount != 1)
2879                 goto unlock;
2880
2881         ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2882
2883  unlock:
2884         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2885 }
2886
2887 void ath9k_ps_restore(struct ath_softc *sc)
2888 {
2889         unsigned long flags;
2890
2891         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2892         if (--sc->ps_usecount != 0)
2893                 goto unlock;
2894
2895         if (sc->ps_enabled &&
2896             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2897                               SC_OP_WAIT_FOR_CAB |
2898                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2899                               SC_OP_WAIT_FOR_TX_ACK)))
2900                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2901
2902  unlock:
2903         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2904 }
2905
2906 /*
2907  * Helper for ASPM support.
2908  *
2909  * Disable PLL when in L0s as well as receiver clock when in L1.
2910  * This power saving option must be enabled through the SerDes.
2911  *
2912  * Programming the SerDes must go through the same 288 bit serial shift
2913  * register as the other analog registers.  Hence the 9 writes.
2914  */
2915 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2916 {
2917         u8 i;
2918
2919         if (ah->is_pciexpress != true)
2920                 return;
2921
2922         /* Do not touch SerDes registers */
2923         if (ah->config.pcie_powersave_enable == 2)
2924                 return;
2925
2926         /* Nothing to do on restore for 11N */
2927         if (restore)
2928                 return;
2929
2930         if (AR_SREV_9280_20_OR_LATER(ah)) {
2931                 /*
2932                  * AR9280 2.0 or later chips use SerDes values from the
2933                  * initvals.h initialized depending on chipset during
2934                  * ath9k_hw_init()
2935                  */
2936                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2937                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2938                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2939                 }
2940         } else if (AR_SREV_9280(ah) &&
2941                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2942                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2943                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2944
2945                 /* RX shut off when elecidle is asserted */
2946                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2947                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2948                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2949
2950                 /* Shut off CLKREQ active in L1 */
2951                 if (ah->config.pcie_clock_req)
2952                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2953                 else
2954                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2955
2956                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2957                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2958                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2959
2960                 /* Load the new settings */
2961                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2962
2963         } else {
2964                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2965                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2966
2967                 /* RX shut off when elecidle is asserted */
2968                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2969                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2970                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2971
2972                 /*
2973                  * Ignore ah->ah_config.pcie_clock_req setting for
2974                  * pre-AR9280 11n
2975                  */
2976                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2977
2978                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2979                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2980                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2981
2982                 /* Load the new settings */
2983                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2984         }
2985
2986         udelay(1000);
2987
2988         /* set bit 19 to allow forcing of pcie core into L1 state */
2989         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2990
2991         /* Several PCIe massages to ensure proper behaviour */
2992         if (ah->config.pcie_waen) {
2993                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2994         } else {
2995                 if (AR_SREV_9285(ah))
2996                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2997                 /*
2998                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2999                  * otherwise card may disappear.
3000                  */
3001                 else if (AR_SREV_9280(ah))
3002                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
3003                 else
3004                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3005         }
3006 }
3007
3008 /**********************/
3009 /* Interrupt Handling */
3010 /**********************/
3011
3012 bool ath9k_hw_intrpend(struct ath_hw *ah)
3013 {
3014         u32 host_isr;
3015
3016         if (AR_SREV_9100(ah))
3017                 return true;
3018
3019         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3020         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3021                 return true;
3022
3023         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3024         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3025             && (host_isr != AR_INTR_SPURIOUS))
3026                 return true;
3027
3028         return false;
3029 }
3030
3031 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3032 {
3033         u32 isr = 0;
3034         u32 mask2 = 0;
3035         struct ath9k_hw_capabilities *pCap = &ah->caps;
3036         u32 sync_cause = 0;
3037         bool fatal_int = false;
3038
3039         if (!AR_SREV_9100(ah)) {
3040                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3041                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3042                             == AR_RTC_STATUS_ON) {
3043                                 isr = REG_READ(ah, AR_ISR);
3044                         }
3045                 }
3046
3047                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3048                         AR_INTR_SYNC_DEFAULT;
3049
3050                 *masked = 0;
3051
3052                 if (!isr && !sync_cause)
3053                         return false;
3054         } else {
3055                 *masked = 0;
3056                 isr = REG_READ(ah, AR_ISR);
3057         }
3058
3059         if (isr) {
3060                 if (isr & AR_ISR_BCNMISC) {
3061                         u32 isr2;
3062                         isr2 = REG_READ(ah, AR_ISR_S2);
3063                         if (isr2 & AR_ISR_S2_TIM)
3064                                 mask2 |= ATH9K_INT_TIM;
3065                         if (isr2 & AR_ISR_S2_DTIM)
3066                                 mask2 |= ATH9K_INT_DTIM;
3067                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3068                                 mask2 |= ATH9K_INT_DTIMSYNC;
3069                         if (isr2 & (AR_ISR_S2_CABEND))
3070                                 mask2 |= ATH9K_INT_CABEND;
3071                         if (isr2 & AR_ISR_S2_GTT)
3072                                 mask2 |= ATH9K_INT_GTT;
3073                         if (isr2 & AR_ISR_S2_CST)
3074                                 mask2 |= ATH9K_INT_CST;
3075                         if (isr2 & AR_ISR_S2_TSFOOR)
3076                                 mask2 |= ATH9K_INT_TSFOOR;
3077                 }
3078
3079                 isr = REG_READ(ah, AR_ISR_RAC);
3080                 if (isr == 0xffffffff) {
3081                         *masked = 0;
3082                         return false;
3083                 }
3084
3085                 *masked = isr & ATH9K_INT_COMMON;
3086
3087                 if (ah->config.intr_mitigation) {
3088                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3089                                 *masked |= ATH9K_INT_RX;
3090                 }
3091
3092                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3093                         *masked |= ATH9K_INT_RX;
3094                 if (isr &
3095                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3096                      AR_ISR_TXEOL)) {
3097                         u32 s0_s, s1_s;
3098
3099                         *masked |= ATH9K_INT_TX;
3100
3101                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3102                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3103                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3104
3105                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3106                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3107                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3108                 }
3109
3110                 if (isr & AR_ISR_RXORN) {
3111                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3112                                 "receive FIFO overrun interrupt\n");
3113                 }
3114
3115                 if (!AR_SREV_9100(ah)) {
3116                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3117                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3118                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3119                                         *masked |= ATH9K_INT_TIM_TIMER;
3120                         }
3121                 }
3122
3123                 *masked |= mask2;
3124         }
3125
3126         if (AR_SREV_9100(ah))
3127                 return true;
3128
3129         if (sync_cause) {
3130                 fatal_int =
3131                         (sync_cause &
3132                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3133                         ? true : false;
3134
3135                 if (fatal_int) {
3136                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3137                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3138                                         "received PCI FATAL interrupt\n");
3139                         }
3140                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3141                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3142                                         "received PCI PERR interrupt\n");
3143                         }
3144                         *masked |= ATH9K_INT_FATAL;
3145                 }
3146                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3147                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3148                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3149                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3150                         REG_WRITE(ah, AR_RC, 0);
3151                         *masked |= ATH9K_INT_FATAL;
3152                 }
3153                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3154                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3155                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3156                 }
3157
3158                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3159                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3160         }
3161
3162         return true;
3163 }
3164
3165 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3166 {
3167         u32 omask = ah->mask_reg;
3168         u32 mask, mask2;
3169         struct ath9k_hw_capabilities *pCap = &ah->caps;
3170
3171         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3172
3173         if (omask & ATH9K_INT_GLOBAL) {
3174                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3175                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3176                 (void) REG_READ(ah, AR_IER);
3177                 if (!AR_SREV_9100(ah)) {
3178                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3179                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3180
3181                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3182                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3183                 }
3184         }
3185
3186         mask = ints & ATH9K_INT_COMMON;
3187         mask2 = 0;
3188
3189         if (ints & ATH9K_INT_TX) {
3190                 if (ah->txok_interrupt_mask)
3191                         mask |= AR_IMR_TXOK;
3192                 if (ah->txdesc_interrupt_mask)
3193                         mask |= AR_IMR_TXDESC;
3194                 if (ah->txerr_interrupt_mask)
3195                         mask |= AR_IMR_TXERR;
3196                 if (ah->txeol_interrupt_mask)
3197                         mask |= AR_IMR_TXEOL;
3198         }
3199         if (ints & ATH9K_INT_RX) {
3200                 mask |= AR_IMR_RXERR;
3201                 if (ah->config.intr_mitigation)
3202                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3203                 else
3204                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3205                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3206                         mask |= AR_IMR_GENTMR;
3207         }
3208
3209         if (ints & (ATH9K_INT_BMISC)) {
3210                 mask |= AR_IMR_BCNMISC;
3211                 if (ints & ATH9K_INT_TIM)
3212                         mask2 |= AR_IMR_S2_TIM;
3213                 if (ints & ATH9K_INT_DTIM)
3214                         mask2 |= AR_IMR_S2_DTIM;
3215                 if (ints & ATH9K_INT_DTIMSYNC)
3216                         mask2 |= AR_IMR_S2_DTIMSYNC;
3217                 if (ints & ATH9K_INT_CABEND)
3218                         mask2 |= AR_IMR_S2_CABEND;
3219                 if (ints & ATH9K_INT_TSFOOR)
3220                         mask2 |= AR_IMR_S2_TSFOOR;
3221         }
3222
3223         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3224                 mask |= AR_IMR_BCNMISC;
3225                 if (ints & ATH9K_INT_GTT)
3226                         mask2 |= AR_IMR_S2_GTT;
3227                 if (ints & ATH9K_INT_CST)
3228                         mask2 |= AR_IMR_S2_CST;
3229         }
3230
3231         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3232         REG_WRITE(ah, AR_IMR, mask);
3233         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3234                                            AR_IMR_S2_DTIM |
3235                                            AR_IMR_S2_DTIMSYNC |
3236                                            AR_IMR_S2_CABEND |
3237                                            AR_IMR_S2_CABTO |
3238                                            AR_IMR_S2_TSFOOR |
3239                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3240         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3241         ah->mask_reg = ints;
3242
3243         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3244                 if (ints & ATH9K_INT_TIM_TIMER)
3245                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3246                 else
3247                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3248         }
3249
3250         if (ints & ATH9K_INT_GLOBAL) {
3251                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3252                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3253                 if (!AR_SREV_9100(ah)) {
3254                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3255                                   AR_INTR_MAC_IRQ);
3256                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3257
3258
3259                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3260                                   AR_INTR_SYNC_DEFAULT);
3261                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3262                                   AR_INTR_SYNC_DEFAULT);
3263                 }
3264                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3265                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3266         }
3267
3268         return omask;
3269 }
3270
3271 /*******************/
3272 /* Beacon Handling */
3273 /*******************/
3274
3275 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3276 {
3277         int flags = 0;
3278
3279         ah->beacon_interval = beacon_period;
3280
3281         switch (ah->opmode) {
3282         case NL80211_IFTYPE_STATION:
3283         case NL80211_IFTYPE_MONITOR:
3284                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3285                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3286                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3287                 flags |= AR_TBTT_TIMER_EN;
3288                 break;
3289         case NL80211_IFTYPE_ADHOC:
3290         case NL80211_IFTYPE_MESH_POINT:
3291                 REG_SET_BIT(ah, AR_TXCFG,
3292                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3293                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3294                           TU_TO_USEC(next_beacon +
3295                                      (ah->atim_window ? ah->
3296                                       atim_window : 1)));
3297                 flags |= AR_NDP_TIMER_EN;
3298         case NL80211_IFTYPE_AP:
3299                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3300                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3301                           TU_TO_USEC(next_beacon -
3302                                      ah->config.
3303                                      dma_beacon_response_time));
3304                 REG_WRITE(ah, AR_NEXT_SWBA,
3305                           TU_TO_USEC(next_beacon -
3306                                      ah->config.
3307                                      sw_beacon_response_time));
3308                 flags |=
3309                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3310                 break;
3311         default:
3312                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3313                         "%s: unsupported opmode: %d\n",
3314                         __func__, ah->opmode);
3315                 return;
3316                 break;
3317         }
3318
3319         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3320         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3321         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3322         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3323
3324         beacon_period &= ~ATH9K_BEACON_ENA;
3325         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3326                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3327                 ath9k_hw_reset_tsf(ah);
3328         }
3329
3330         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3331 }
3332
3333 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3334                                     const struct ath9k_beacon_state *bs)
3335 {
3336         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3337         struct ath9k_hw_capabilities *pCap = &ah->caps;
3338
3339         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3340
3341         REG_WRITE(ah, AR_BEACON_PERIOD,
3342                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3343         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3344                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3345
3346         REG_RMW_FIELD(ah, AR_RSSI_THR,
3347                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3348
3349         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3350
3351         if (bs->bs_sleepduration > beaconintval)
3352                 beaconintval = bs->bs_sleepduration;
3353
3354         dtimperiod = bs->bs_dtimperiod;
3355         if (bs->bs_sleepduration > dtimperiod)
3356                 dtimperiod = bs->bs_sleepduration;
3357
3358         if (beaconintval == dtimperiod)
3359                 nextTbtt = bs->bs_nextdtim;
3360         else
3361                 nextTbtt = bs->bs_nexttbtt;
3362
3363         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3364         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3365         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3366         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3367
3368         REG_WRITE(ah, AR_NEXT_DTIM,
3369                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3370         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3371
3372         REG_WRITE(ah, AR_SLEEP1,
3373                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3374                   | AR_SLEEP1_ASSUME_DTIM);
3375
3376         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3377                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3378         else
3379                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3380
3381         REG_WRITE(ah, AR_SLEEP2,
3382                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3383
3384         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3385         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3386
3387         REG_SET_BIT(ah, AR_TIMER_MODE,
3388                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3389                     AR_DTIM_TIMER_EN);
3390
3391         /* TSF Out of Range Threshold */
3392         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3393 }
3394
3395 /*******************/
3396 /* HW Capabilities */
3397 /*******************/
3398
3399 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3400 {
3401         struct ath9k_hw_capabilities *pCap = &ah->caps;
3402         u16 capField = 0, eeval;
3403
3404         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3405         ah->regulatory.current_rd = eeval;
3406
3407         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3408         if (AR_SREV_9285_10_OR_LATER(ah))
3409                 eeval |= AR9285_RDEXT_DEFAULT;
3410         ah->regulatory.current_rd_ext = eeval;
3411
3412         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3413
3414         if (ah->opmode != NL80211_IFTYPE_AP &&
3415             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3416                 if (ah->regulatory.current_rd == 0x64 ||
3417                     ah->regulatory.current_rd == 0x65)
3418                         ah->regulatory.current_rd += 5;
3419                 else if (ah->regulatory.current_rd == 0x41)
3420                         ah->regulatory.current_rd = 0x43;
3421                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3422                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3423         }
3424
3425         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3426         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3427
3428         if (eeval & AR5416_OPFLAGS_11A) {
3429                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3430                 if (ah->config.ht_enable) {
3431                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3432                                 set_bit(ATH9K_MODE_11NA_HT20,
3433                                         pCap->wireless_modes);
3434                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3435                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3436                                         pCap->wireless_modes);
3437                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3438                                         pCap->wireless_modes);
3439                         }
3440                 }
3441         }
3442
3443         if (eeval & AR5416_OPFLAGS_11G) {
3444                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3445                 if (ah->config.ht_enable) {
3446                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3447                                 set_bit(ATH9K_MODE_11NG_HT20,
3448                                         pCap->wireless_modes);
3449                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3450                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3451                                         pCap->wireless_modes);
3452                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3453                                         pCap->wireless_modes);
3454                         }
3455                 }
3456         }
3457
3458         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3459         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3460             !(eeval & AR5416_OPFLAGS_11A))
3461                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3462         else
3463                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3464
3465         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3466                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3467
3468         pCap->low_2ghz_chan = 2312;
3469         pCap->high_2ghz_chan = 2732;
3470
3471         pCap->low_5ghz_chan = 4920;
3472         pCap->high_5ghz_chan = 6100;
3473
3474         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3475         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3476         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3477
3478         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3479         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3480         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3481
3482         if (ah->config.ht_enable)
3483                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3484         else
3485                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3486
3487         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3488         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3489         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3490         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3491
3492         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3493                 pCap->total_queues =
3494                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3495         else
3496                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3497
3498         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3499                 pCap->keycache_size =
3500                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3501         else
3502                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3503
3504         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3505         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3506
3507         if (AR_SREV_9285_10_OR_LATER(ah))
3508                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3509         else if (AR_SREV_9280_10_OR_LATER(ah))
3510                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3511         else
3512                 pCap->num_gpio_pins = AR_NUM_GPIO;
3513
3514         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3515                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3516                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3517         } else {
3518                 pCap->rts_aggr_limit = (8 * 1024);
3519         }
3520
3521         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3522
3523 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3524         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3525         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3526                 ah->rfkill_gpio =
3527                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3528                 ah->rfkill_polarity =
3529                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3530
3531                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3532         }
3533 #endif
3534
3535         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3536             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3537             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3538             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3539             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3540             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3541                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3542         else
3543                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3544
3545         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3546                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3547         else
3548                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3549
3550         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3551                 pCap->reg_cap =
3552                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3553                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3554                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3555                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3556         } else {
3557                 pCap->reg_cap =
3558                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3559                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3560         }
3561
3562         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3563
3564         pCap->num_antcfg_5ghz =
3565                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3566         pCap->num_antcfg_2ghz =
3567                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3568
3569         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3570                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3571                 ah->btactive_gpio = 6;
3572                 ah->wlanactive_gpio = 5;
3573         }
3574 }
3575
3576 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3577                             u32 capability, u32 *result)
3578 {
3579         switch (type) {
3580         case ATH9K_CAP_CIPHER:
3581                 switch (capability) {
3582                 case ATH9K_CIPHER_AES_CCM:
3583                 case ATH9K_CIPHER_AES_OCB:
3584                 case ATH9K_CIPHER_TKIP:
3585                 case ATH9K_CIPHER_WEP:
3586                 case ATH9K_CIPHER_MIC:
3587                 case ATH9K_CIPHER_CLR:
3588                         return true;
3589                 default:
3590                         return false;
3591                 }
3592         case ATH9K_CAP_TKIP_MIC:
3593                 switch (capability) {
3594                 case 0:
3595                         return true;
3596                 case 1:
3597                         return (ah->sta_id1_defaults &
3598                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3599                         false;
3600                 }
3601         case ATH9K_CAP_TKIP_SPLIT:
3602                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3603                         false : true;
3604         case ATH9K_CAP_DIVERSITY:
3605                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3606                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3607                         true : false;
3608         case ATH9K_CAP_MCAST_KEYSRCH:
3609                 switch (capability) {
3610                 case 0:
3611                         return true;
3612                 case 1:
3613                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3614                                 return false;
3615                         } else {
3616                                 return (ah->sta_id1_defaults &
3617                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3618                                         false;
3619                         }
3620                 }
3621                 return false;
3622         case ATH9K_CAP_TXPOW:
3623                 switch (capability) {
3624                 case 0:
3625                         return 0;
3626                 case 1:
3627                         *result = ah->regulatory.power_limit;
3628                         return 0;
3629                 case 2:
3630                         *result = ah->regulatory.max_power_level;
3631                         return 0;
3632                 case 3:
3633                         *result = ah->regulatory.tp_scale;
3634                         return 0;
3635                 }
3636                 return false;
3637         case ATH9K_CAP_DS:
3638                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3639                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3640                         ? false : true;
3641         default:
3642                 return false;
3643         }
3644 }
3645
3646 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3647                             u32 capability, u32 setting, int *status)
3648 {
3649         u32 v;
3650
3651         switch (type) {
3652         case ATH9K_CAP_TKIP_MIC:
3653                 if (setting)
3654                         ah->sta_id1_defaults |=
3655                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3656                 else
3657                         ah->sta_id1_defaults &=
3658                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3659                 return true;
3660         case ATH9K_CAP_DIVERSITY:
3661                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3662                 if (setting)
3663                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3664                 else
3665                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3666                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3667                 return true;
3668         case ATH9K_CAP_MCAST_KEYSRCH:
3669                 if (setting)
3670                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3671                 else
3672                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3673                 return true;
3674         default:
3675                 return false;
3676         }
3677 }
3678
3679 /****************************/
3680 /* GPIO / RFKILL / Antennae */
3681 /****************************/
3682
3683 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3684                                          u32 gpio, u32 type)
3685 {
3686         int addr;
3687         u32 gpio_shift, tmp;
3688
3689         if (gpio > 11)
3690                 addr = AR_GPIO_OUTPUT_MUX3;
3691         else if (gpio > 5)
3692                 addr = AR_GPIO_OUTPUT_MUX2;
3693         else
3694                 addr = AR_GPIO_OUTPUT_MUX1;
3695
3696         gpio_shift = (gpio % 6) * 5;
3697
3698         if (AR_SREV_9280_20_OR_LATER(ah)
3699             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3700                 REG_RMW(ah, addr, (type << gpio_shift),
3701                         (0x1f << gpio_shift));
3702         } else {
3703                 tmp = REG_READ(ah, addr);
3704                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3705                 tmp &= ~(0x1f << gpio_shift);
3706                 tmp |= (type << gpio_shift);
3707                 REG_WRITE(ah, addr, tmp);
3708         }
3709 }
3710
3711 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3712 {
3713         u32 gpio_shift;
3714
3715         ASSERT(gpio < ah->caps.num_gpio_pins);
3716
3717         gpio_shift = gpio << 1;
3718
3719         REG_RMW(ah,
3720                 AR_GPIO_OE_OUT,
3721                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3722                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3723 }
3724
3725 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3726 {
3727 #define MS_REG_READ(x, y) \
3728         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3729
3730         if (gpio >= ah->caps.num_gpio_pins)
3731                 return 0xffffffff;
3732
3733         if (AR_SREV_9287_10_OR_LATER(ah))
3734                 return MS_REG_READ(AR9287, gpio) != 0;
3735         else if (AR_SREV_9285_10_OR_LATER(ah))
3736                 return MS_REG_READ(AR9285, gpio) != 0;
3737         else if (AR_SREV_9280_10_OR_LATER(ah))
3738                 return MS_REG_READ(AR928X, gpio) != 0;
3739         else
3740                 return MS_REG_READ(AR, gpio) != 0;
3741 }
3742
3743 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3744                          u32 ah_signal_type)
3745 {
3746         u32 gpio_shift;
3747
3748         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3749
3750         gpio_shift = 2 * gpio;
3751
3752         REG_RMW(ah,
3753                 AR_GPIO_OE_OUT,
3754                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3755                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3756 }
3757
3758 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3759 {
3760         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3761                 AR_GPIO_BIT(gpio));
3762 }
3763
3764 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3765 {
3766         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3767 }
3768
3769 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3770 {
3771         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3772 }
3773
3774 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3775                                enum ath9k_ant_setting settings,
3776                                struct ath9k_channel *chan,
3777                                u8 *tx_chainmask,
3778                                u8 *rx_chainmask,
3779                                u8 *antenna_cfgd)
3780 {
3781         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3782
3783         if (AR_SREV_9280(ah)) {
3784                 if (!tx_chainmask_cfg) {
3785
3786                         tx_chainmask_cfg = *tx_chainmask;
3787                         rx_chainmask_cfg = *rx_chainmask;
3788                 }
3789
3790                 switch (settings) {
3791                 case ATH9K_ANT_FIXED_A:
3792                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3793                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3794                         *antenna_cfgd = true;
3795                         break;
3796                 case ATH9K_ANT_FIXED_B:
3797                         if (ah->caps.tx_chainmask >
3798                             ATH9K_ANTENNA1_CHAINMASK) {
3799                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3800                         }
3801                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3802                         *antenna_cfgd = true;
3803                         break;
3804                 case ATH9K_ANT_VARIABLE:
3805                         *tx_chainmask = tx_chainmask_cfg;
3806                         *rx_chainmask = rx_chainmask_cfg;
3807                         *antenna_cfgd = true;
3808                         break;
3809                 default:
3810                         break;
3811                 }
3812         } else {
3813                 ah->diversity_control = settings;
3814         }
3815
3816         return true;
3817 }
3818
3819 /*********************/
3820 /* General Operation */
3821 /*********************/
3822
3823 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3824 {
3825         u32 bits = REG_READ(ah, AR_RX_FILTER);
3826         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3827
3828         if (phybits & AR_PHY_ERR_RADAR)
3829                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3830         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3831                 bits |= ATH9K_RX_FILTER_PHYERR;
3832
3833         return bits;
3834 }
3835
3836 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3837 {
3838         u32 phybits;
3839
3840         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3841         phybits = 0;
3842         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3843                 phybits |= AR_PHY_ERR_RADAR;
3844         if (bits & ATH9K_RX_FILTER_PHYERR)
3845                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3846         REG_WRITE(ah, AR_PHY_ERR, phybits);
3847
3848         if (phybits)
3849                 REG_WRITE(ah, AR_RXCFG,
3850                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3851         else
3852                 REG_WRITE(ah, AR_RXCFG,
3853                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3854 }
3855
3856 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3857 {
3858         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3859 }
3860
3861 bool ath9k_hw_disable(struct ath_hw *ah)
3862 {
3863         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3864                 return false;
3865
3866         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3867 }
3868
3869 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3870 {
3871         struct ath9k_channel *chan = ah->curchan;
3872         struct ieee80211_channel *channel = chan->chan;
3873
3874         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3875
3876         ah->eep_ops->set_txpower(ah, chan,
3877                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3878                                  channel->max_antenna_gain * 2,
3879                                  channel->max_power * 2,
3880                                  min((u32) MAX_RATE_POWER,
3881                                  (u32) ah->regulatory.power_limit));
3882 }
3883
3884 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3885 {
3886         memcpy(ah->macaddr, mac, ETH_ALEN);
3887 }
3888
3889 void ath9k_hw_setopmode(struct ath_hw *ah)
3890 {
3891         ath9k_hw_set_operating_mode(ah, ah->opmode);
3892 }
3893
3894 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3895 {
3896         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3897         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3898 }
3899
3900 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3901 {
3902         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3903         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3904 }
3905
3906 void ath9k_hw_write_associd(struct ath_softc *sc)
3907 {
3908         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3909         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3910                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3911 }
3912
3913 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3914 {
3915         u64 tsf;
3916
3917         tsf = REG_READ(ah, AR_TSF_U32);
3918         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3919
3920         return tsf;
3921 }
3922
3923 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3924 {
3925         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3926         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3927 }
3928
3929 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3930 {
3931         ath9k_ps_wakeup(ah->ah_sc);
3932         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3933                            AH_TSF_WRITE_TIMEOUT))
3934                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3935                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3936
3937         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3938         ath9k_ps_restore(ah->ah_sc);
3939 }
3940
3941 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3942 {
3943         if (setting)
3944                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3945         else
3946                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3947
3948         return true;
3949 }
3950
3951 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3952 {
3953         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3954                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3955                 ah->slottime = (u32) -1;
3956                 return false;
3957         } else {
3958                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3959                 ah->slottime = us;
3960                 return true;
3961         }
3962 }
3963
3964 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3965 {
3966         u32 macmode;
3967
3968         if (mode == ATH9K_HT_MACMODE_2040 &&
3969             !ah->config.cwm_ignore_extcca)
3970                 macmode = AR_2040_JOINED_RX_CLEAR;
3971         else
3972                 macmode = 0;
3973
3974         REG_WRITE(ah, AR_2040_MODE, macmode);
3975 }
3976
3977 /***************************/
3978 /*  Bluetooth Coexistence  */
3979 /***************************/
3980
3981 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3982 {
3983         /* connect bt_active to baseband */
3984         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3985                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3986                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3987
3988         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3989                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3990
3991         /* Set input mux for bt_active to gpio pin */
3992         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3993                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3994                         ah->btactive_gpio);
3995
3996         /* Configure the desired gpio port for input */
3997         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3998
3999         /* Configure the desired GPIO port for TX_FRAME output */
4000         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
4001                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
4002 }