drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 /*
  88  * Read and write, they both share the same lock. We do this to serialize
  89  * reads and writes on Atheros 802.11n PCI devices only. This is required
  90  * as the FIFO on these devices can only accept sanely 2 requests. After
  91  * that the device goes bananas. Serializing the reads/writes prevents this
  92  * from happening.
  93  */
  94
  95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  96 {
  97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  98                 unsigned long flags;
  99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 102         } else
 103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 104 }
 105
 106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 107 {
 108         u32 val;
 109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 110                 unsigned long flags;
 111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 112                 val = ioread32(ah->ah_sc->mem + reg_offset);
 113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 114         } else
 115                 val = ioread32(ah->ah_sc->mem + reg_offset);
 116         return val;
 117 }
 118
 119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 120 {
 121         int i;
 122
 123         BUG_ON(timeout < AH_TIME_QUANTUM);
 124
 125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 126                 if ((REG_READ(ah, reg) & mask) == val)
 127                         return true;
 128
 129                 udelay(AH_TIME_QUANTUM);
 130         }
 131
 132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 134                 timeout, reg, REG_READ(ah, reg), mask, val);
 135
 136         return false;
 137 }
 138
 139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 140 {
 141         u32 retval;
 142         int i;
 143
 144         for (i = 0, retval = 0; i < n; i++) {
 145                 retval = (retval << 1) | (val & 1);
 146                 val >>= 1;
 147         }
 148         return retval;
 149 }
 150
 151 bool ath9k_get_channel_edges(struct ath_hw *ah,
 152                              u16 flags, u16 *low,
 153                              u16 *high)
 154 {
 155         struct ath9k_hw_capabilities *pCap = &ah->caps;
 156
 157         if (flags & CHANNEL_5GHZ) {
 158                 *low = pCap->low_5ghz_chan;
 159                 *high = pCap->high_5ghz_chan;
 160                 return true;
 161         }
 162         if ((flags & CHANNEL_2GHZ)) {
 163                 *low = pCap->low_2ghz_chan;
 164                 *high = pCap->high_2ghz_chan;
 165                 return true;
 166         }
 167         return false;
 168 }
 169
 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 171                            const struct ath_rate_table *rates,
 172                            u32 frameLen, u16 rateix,
 173                            bool shortPreamble)
 174 {
 175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 176         u32 kbps;
 177
 178         kbps = rates->info[rateix].ratekbps;
 179
 180         if (kbps == 0)
 181                 return 0;
 182
 183         switch (rates->info[rateix].phy) {
 184         case WLAN_RC_PHY_CCK:
 185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 186                 if (shortPreamble && rates->info[rateix].short_preamble)
 187                         phyTime >>= 1;
 188                 numBits = frameLen << 3;
 189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 190                 break;
 191         case WLAN_RC_PHY_OFDM:
 192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME_QUARTER
 197                                 + OFDM_PREAMBLE_TIME_QUARTER
 198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 199                 } else if (ah->curchan &&
 200                            IS_CHAN_HALF_RATE(ah->curchan)) {
 201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 204                         txTime = OFDM_SIFS_TIME_HALF +
 205                                 OFDM_PREAMBLE_TIME_HALF
 206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 207                 } else {
 208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 212                                 + (numSymbols * OFDM_SYMBOL_TIME);
 213                 }
 214                 break;
 215         default:
 216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 217                         "Unknown phy %u (rate ix %u)\n",
 218                         rates->info[rateix].phy, rateix);
 219                 txTime = 0;
 220                 break;
 221         }
 222
 223         return txTime;
 224 }
 225
 226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 227                                   struct ath9k_channel *chan,
 228                                   struct chan_centers *centers)
 229 {
 230         int8_t extoff;
 231
 232         if (!IS_CHAN_HT40(chan)) {
 233                 centers->ctl_center = centers->ext_center =
 234                         centers->synth_center = chan->channel;
 235                 return;
 236         }
 237
 238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 240                 centers->synth_center =
 241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 242                 extoff = 1;
 243         } else {
 244                 centers->synth_center =
 245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 246                 extoff = -1;
 247         }
 248
 249         centers->ctl_center =
 250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 251         centers->ext_center =
 252                 centers->synth_center + (extoff *
 253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 254                           HT40_CHANNEL_CENTER_SHIFT : 15));
 255 }
 256
 257 /******************/
 258 /* Chip Revisions */
 259 /******************/
 260
 261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 262 {
 263         u32 val;
 264
 265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 266
 267         if (val == 0xFF) {
 268                 val = REG_READ(ah, AR_SREV);
 269                 ah->hw_version.macVersion =
 270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 273         } else {
 274                 if (!AR_SREV_9100(ah))
 275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 276
 277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 278
 279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 280                         ah->is_pciexpress = true;
 281         }
 282 }
 283
 284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 285 {
 286         u32 val;
 287         int i;
 288
 289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 290
 291         for (i = 0; i < 8; i++)
 292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 295
 296         return ath9k_hw_reverse_bits(val, 8);
 297 }
 298
 299 /************************************/
 300 /* HW Attach, Detach, Init Routines */
 301 /************************************/
 302
 303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 304 {
 305         if (AR_SREV_9100(ah))
 306                 return;
 307
 308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 317
 318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 319 }
 320
 321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 322 {
 323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 324         u32 regHold[2];
 325         u32 patternData[4] = { 0x55555555,
 326                                0xaaaaaaaa,
 327                                0x66666666,
 328                                0x99999999 };
 329         int i, j;
 330
 331         for (i = 0; i < 2; i++) {
 332                 u32 addr = regAddr[i];
 333                 u32 wrData, rdData;
 334
 335                 regHold[i] = REG_READ(ah, addr);
 336                 for (j = 0; j < 0x100; j++) {
 337                         wrData = (j << 16) | j;
 338                         REG_WRITE(ah, addr, wrData);
 339                         rdData = REG_READ(ah, addr);
 340                         if (rdData != wrData) {
 341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 342                                         "address test failed "
 343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 344                                         addr, wrData, rdData);
 345                                 return false;
 346                         }
 347                 }
 348                 for (j = 0; j < 4; j++) {
 349                         wrData = patternData[j];
 350                         REG_WRITE(ah, addr, wrData);
 351                         rdData = REG_READ(ah, addr);
 352                         if (wrData != rdData) {
 353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 354                                         "address test failed "
 355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 356                                         addr, wrData, rdData);
 357                                 return false;
 358                         }
 359                 }
 360                 REG_WRITE(ah, regAddr[i], regHold[i]);
 361         }
 362         udelay(100);
 363
 364         return true;
 365 }
 366
 367 static const char *ath9k_hw_devname(u16 devid)
 368 {
 369         switch (devid) {
 370         case AR5416_DEVID_PCI:
 371                 return "Atheros 5416";
 372         case AR5416_DEVID_PCIE:
 373                 return "Atheros 5418";
 374         case AR9160_DEVID_PCI:
 375                 return "Atheros 9160";
 376         case AR5416_AR9100_DEVID:
 377                 return "Atheros 9100";
 378         case AR9280_DEVID_PCI:
 379         case AR9280_DEVID_PCIE:
 380                 return "Atheros 9280";
 381         case AR9285_DEVID_PCIE:
 382                 return "Atheros 9285";
 383         case AR5416_DEVID_AR9287_PCI:
 384         case AR5416_DEVID_AR9287_PCIE:
 385                 return "Atheros 9287";
 386         }
 387
 388         return NULL;
 389 }
 390
 391 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 392 {
 393         int i;
 394
 395         ah->config.dma_beacon_response_time = 2;
 396         ah->config.sw_beacon_response_time = 10;
 397         ah->config.additional_swba_backoff = 0;
 398         ah->config.ack_6mb = 0x0;
 399         ah->config.cwm_ignore_extcca = 0;
 400         ah->config.pcie_powersave_enable = 0;
 401         ah->config.pcie_clock_req = 0;
 402         ah->config.pcie_waen = 0;
 403         ah->config.analog_shiftreg = 1;
 404         ah->config.ht_enable = 1;
 405         ah->config.ofdm_trig_low = 200;
 406         ah->config.ofdm_trig_high = 500;
 407         ah->config.cck_trig_high = 200;
 408         ah->config.cck_trig_low = 100;
 409         ah->config.enable_ani = 1;
 410         ah->config.diversity_control = 0;
 411         ah->config.antenna_switch_swap = 0;
 412
 413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 416         }
 417
 418         ah->config.intr_mitigation = true;
 419
 420         /*
 421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 423          * This means we use it for all AR5416 devices, and the few
 424          * minor PCI AR9280 devices out there.
 425          *
 426          * Serialization is required because these devices do not handle
 427          * well the case of two concurrent reads/writes due to the latency
 428          * involved. During one read/write another read/write can be issued
 429          * on another CPU while the previous read/write may still be working
 430          * on our hardware, if we hit this case the hardware poops in a loop.
 431          * We prevent this by serializing reads and writes.
 432          *
 433          * This issue is not present on PCI-Express devices or pre-AR5416
 434          * devices (legacy, 802.11abg).
 435          */
 436         if (num_possible_cpus() > 1)
 437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 438 }
 439
 440 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 441                                         int *status)
 442 {
 443         struct ath_hw *ah;
 444
 445         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 446         if (ah == NULL) {
 447                 DPRINTF(sc, ATH_DBG_FATAL,
 448                         "Cannot allocate memory for state block\n");
 449                 *status = -ENOMEM;
 450                 return NULL;
 451         }
 452
 453         ah->ah_sc = sc;
 454         ah->hw_version.magic = AR5416_MAGIC;
 455         ah->regulatory.country_code = CTRY_DEFAULT;
 456         ah->hw_version.devid = devid;
 457         ah->hw_version.subvendorid = 0;
 458
 459         ah->ah_flags = 0;
 460         if ((devid == AR5416_AR9100_DEVID))
 461                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 462         if (!AR_SREV_9100(ah))
 463                 ah->ah_flags = AH_USE_EEPROM;
 464
 465         ah->regulatory.power_limit = MAX_RATE_POWER;
 466         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 467         ah->atim_window = 0;
 468         ah->diversity_control = ah->config.diversity_control;
 469         ah->antenna_switch_swap =
 470                 ah->config.antenna_switch_swap;
 471         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 472         ah->beacon_interval = 100;
 473         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 474         ah->slottime = (u32) -1;
 475         ah->acktimeout = (u32) -1;
 476         ah->ctstimeout = (u32) -1;
 477         ah->globaltxtimeout = (u32) -1;
 478
 479         ah->gbeacon_rate = 0;
 480
 481         ah->power_mode = ATH9K_PM_UNDEFINED;
 482
 483         return ah;
 484 }
 485
 486 static int ath9k_hw_rfattach(struct ath_hw *ah)
 487 {
 488         bool rfStatus = false;
 489         int ecode = 0;
 490
 491         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 492         if (!rfStatus) {
 493                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 494                         "RF setup failed, status: %u\n", ecode);
 495                 return ecode;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 502 {
 503         u32 val;
 504
 505         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 506
 507         val = ath9k_hw_get_radiorev(ah);
 508         switch (val & AR_RADIO_SREV_MAJOR) {
 509         case 0:
 510                 val = AR_RAD5133_SREV_MAJOR;
 511                 break;
 512         case AR_RAD5133_SREV_MAJOR:
 513         case AR_RAD5122_SREV_MAJOR:
 514         case AR_RAD2133_SREV_MAJOR:
 515         case AR_RAD2122_SREV_MAJOR:
 516                 break;
 517         default:
 518                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 519                         "Radio Chip Rev 0x%02X not supported\n",
 520                         val & AR_RADIO_SREV_MAJOR);
 521                 return -EOPNOTSUPP;
 522         }
 523
 524         ah->hw_version.analog5GhzRev = val;
 525
 526         return 0;
 527 }
 528
 529 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 530 {
 531         u32 sum;
 532         int i;
 533         u16 eeval;
 534
 535         sum = 0;
 536         for (i = 0; i < 3; i++) {
 537                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 538                 sum += eeval;
 539                 ah->macaddr[2 * i] = eeval >> 8;
 540                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 541         }
 542         if (sum == 0 || sum == 0xffff * 3)
 543                 return -EADDRNOTAVAIL;
 544
 545         return 0;
 546 }
 547
 548 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 549 {
 550         u32 rxgain_type;
 551
 552         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 553                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 554
 555                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 556                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 557                         ar9280Modes_backoff_13db_rxgain_9280_2,
 558                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 559                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 560                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 561                         ar9280Modes_backoff_23db_rxgain_9280_2,
 562                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 563                 else
 564                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 565                         ar9280Modes_original_rxgain_9280_2,
 566                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 567         } else {
 568                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 569                         ar9280Modes_original_rxgain_9280_2,
 570                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 571         }
 572 }
 573
 574 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 575 {
 576         u32 txgain_type;
 577
 578         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 579                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 580
 581                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 582                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 583                         ar9280Modes_high_power_tx_gain_9280_2,
 584                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 585                 else
 586                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 587                         ar9280Modes_original_tx_gain_9280_2,
 588                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 589         } else {
 590                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 591                 ar9280Modes_original_tx_gain_9280_2,
 592                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 593         }
 594 }
 595
 596 static int ath9k_hw_post_attach(struct ath_hw *ah)
 597 {
 598         int ecode;
 599
 600         if (!ath9k_hw_chip_test(ah))
 601                 return -ENODEV;
 602
 603         ecode = ath9k_hw_rf_claim(ah);
 604         if (ecode != 0)
 605                 return ecode;
 606
 607         ecode = ath9k_hw_eeprom_attach(ah);
 608         if (ecode != 0)
 609                 return ecode;
 610
 611         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 612                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 613
 614         ecode = ath9k_hw_rfattach(ah);
 615         if (ecode != 0)
 616                 return ecode;
 617
 618         if (!AR_SREV_9100(ah)) {
 619                 ath9k_hw_ani_setup(ah);
 620                 ath9k_hw_ani_attach(ah);
 621         }
 622
 623         return 0;
 624 }
 625
 626 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 627                                          int *status)
 628 {
 629         struct ath_hw *ah;
 630         int ecode;
 631         u32 i, j;
 632
 633         ah = ath9k_hw_newstate(devid, sc, status);
 634         if (ah == NULL)
 635                 return NULL;
 636
 637         ath9k_hw_set_defaults(ah);
 638
 639         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 640                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 641                 ecode = -EIO;
 642                 goto bad;
 643         }
 644
 645         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 646                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 647                 ecode = -EIO;
 648                 goto bad;
 649         }
 650
 651         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 652                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 653                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 654                         ah->config.serialize_regmode =
 655                                 SER_REG_MODE_ON;
 656                 } else {
 657                         ah->config.serialize_regmode =
 658                                 SER_REG_MODE_OFF;
 659                 }
 660         }
 661
 662         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 663                 ah->config.serialize_regmode);
 664
 665         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 666             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 667             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 668             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) &&
 669             (!AR_SREV_9285(ah)) && (!AR_SREV_9287(ah))) {
 670                 DPRINTF(sc, ATH_DBG_FATAL,
 671                         "Mac Chip Rev 0x%02x.%x is not supported by "
 672                         "this driver\n", ah->hw_version.macVersion,
 673                         ah->hw_version.macRev);
 674                 ecode = -EOPNOTSUPP;
 675                 goto bad;
 676         }
 677
 678         if (AR_SREV_9100(ah)) {
 679                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 680                 ah->supp_cals = IQ_MISMATCH_CAL;
 681                 ah->is_pciexpress = false;
 682         }
 683         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 684
 685         if (AR_SREV_9160_10_OR_LATER(ah)) {
 686                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 687                         ah->iq_caldata.calData = &iq_cal_single_sample;
 688                         ah->adcgain_caldata.calData =
 689                                 &adc_gain_cal_single_sample;
 690                         ah->adcdc_caldata.calData =
 691                                 &adc_dc_cal_single_sample;
 692                         ah->adcdc_calinitdata.calData =
 693                                 &adc_init_dc_cal;
 694                 } else {
 695                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 696                         ah->adcgain_caldata.calData =
 697                                 &adc_gain_cal_multi_sample;
 698                         ah->adcdc_caldata.calData =
 699                                 &adc_dc_cal_multi_sample;
 700                         ah->adcdc_calinitdata.calData =
 701                                 &adc_init_dc_cal;
 702                 }
 703                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 704         }
 705
 706         ah->ani_function = ATH9K_ANI_ALL;
 707         if (AR_SREV_9280_10_OR_LATER(ah))
 708                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 709         if (AR_SREV_9287_11_OR_LATER(ah)) {
 710                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 711                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 712                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 713                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 714                 if (ah->config.pcie_clock_req)
 715                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 716                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 717                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 718                 else
 719                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 720                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 721                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 722                                         2);
 723         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 724                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 725                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 726                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 727                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 728
 729                 if (ah->config.pcie_clock_req)
 730                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 731                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 732                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 733                 else
 734                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 735                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 736                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 737                                   2);
 738         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 739
 740
 741                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 742                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 743                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 744                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 745
 746                 if (ah->config.pcie_clock_req) {
 747                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 748                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 749                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 750                 } else {
 751                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 752                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 753                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 754                                   2);
 755                 }
 756         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 757                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 758                                ARRAY_SIZE(ar9285Modes_9285), 6);
 759                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 760                                ARRAY_SIZE(ar9285Common_9285), 2);
 761
 762                 if (ah->config.pcie_clock_req) {
 763                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 764                         ar9285PciePhy_clkreq_off_L1_9285,
 765                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 766                 } else {
 767                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 768                         ar9285PciePhy_clkreq_always_on_L1_9285,
 769                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 770                 }
 771         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 772                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 773                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 774                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 775                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 776
 777                 if (ah->config.pcie_clock_req) {
 778                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 779                                ar9280PciePhy_clkreq_off_L1_9280,
 780                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 781                 } else {
 782                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 783                                ar9280PciePhy_clkreq_always_on_L1_9280,
 784                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 785                 }
 786                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 787                                ar9280Modes_fast_clock_9280_2,
 788                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 789         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 790                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 791                                ARRAY_SIZE(ar9280Modes_9280), 6);
 792                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 793                                ARRAY_SIZE(ar9280Common_9280), 2);
 794         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 795                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 796                                ARRAY_SIZE(ar5416Modes_9160), 6);
 797                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 798                                ARRAY_SIZE(ar5416Common_9160), 2);
 799                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 800                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 801                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 802                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 803                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 804                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 805                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 806                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 807                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 808                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 809                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 810                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 811                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 812                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 813                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 814                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 815                 if (AR_SREV_9160_11(ah)) {
 816                         INIT_INI_ARRAY(&ah->iniAddac,
 817                                        ar5416Addac_91601_1,
 818                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 819                 } else {
 820                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 821                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 822                 }
 823         } else if (AR_SREV_9100_OR_LATER(ah)) {
 824                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 825                                ARRAY_SIZE(ar5416Modes_9100), 6);
 826                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 827                                ARRAY_SIZE(ar5416Common_9100), 2);
 828                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 829                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 830                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 831                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 832                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 833                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 834                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 835                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 836                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 837                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 838                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 839                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 840                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 841                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 842                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 843                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 844                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 845                                ARRAY_SIZE(ar5416Addac_9100), 2);
 846         } else {
 847                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 848                                ARRAY_SIZE(ar5416Modes), 6);
 849                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 850                                ARRAY_SIZE(ar5416Common), 2);
 851                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 852                                ARRAY_SIZE(ar5416Bank0), 2);
 853                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 854                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 855                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 856                                ARRAY_SIZE(ar5416Bank1), 2);
 857                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 858                                ARRAY_SIZE(ar5416Bank2), 2);
 859                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 860                                ARRAY_SIZE(ar5416Bank3), 3);
 861                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 862                                ARRAY_SIZE(ar5416Bank6), 3);
 863                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 864                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 865                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 866                                ARRAY_SIZE(ar5416Bank7), 2);
 867                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 868                                ARRAY_SIZE(ar5416Addac), 2);
 869         }
 870
 871         if (ah->is_pciexpress)
 872                 ath9k_hw_configpcipowersave(ah, 0);
 873         else
 874                 ath9k_hw_disablepcie(ah);
 875
 876         ecode = ath9k_hw_post_attach(ah);
 877         if (ecode != 0)
 878                 goto bad;
 879
 880         if (AR_SREV_9287_11(ah))
 881                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 882                 ar9287Modes_rx_gain_9287_1_1,
 883                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 884         else if (AR_SREV_9287_10(ah))
 885                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 886                 ar9287Modes_rx_gain_9287_1_0,
 887                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 888         else if (AR_SREV_9280_20(ah))
 889                 ath9k_hw_init_rxgain_ini(ah);
 890
 891         if (AR_SREV_9287_11(ah)) {
 892                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 893                 ar9287Modes_tx_gain_9287_1_1,
 894                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 895         } else if (AR_SREV_9287_10(ah)) {
 896                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 897                 ar9287Modes_tx_gain_9287_1_0,
 898                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 899         } else if (AR_SREV_9280_20(ah)) {
 900                 ath9k_hw_init_txgain_ini(ah);
 901         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 902                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 903
 904                 /* txgain table */
 905                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 906                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 907                         ar9285Modes_high_power_tx_gain_9285_1_2,
 908                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 909                 } else {
 910                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 911                         ar9285Modes_original_tx_gain_9285_1_2,
 912                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 913                 }
 914
 915         }
 916
 917         ath9k_hw_fill_cap_info(ah);
 918
 919         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 920             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 921
 922                 /* EEPROM Fixup */
 923                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 924                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 925
 926                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 927                                 u32 val = INI_RA(&ah->iniModes, i, j);
 928
 929                                 INI_RA(&ah->iniModes, i, j) =
 930                                         ath9k_hw_ini_fixup(ah,
 931                                                            &ah->eeprom.def,
 932                                                            reg, val);
 933                         }
 934                 }
 935         }
 936
 937         ecode = ath9k_hw_init_macaddr(ah);
 938         if (ecode != 0) {
 939                 DPRINTF(sc, ATH_DBG_FATAL,
 940                         "Failed to initialize MAC address\n");
 941                 goto bad;
 942         }
 943
 944         if (AR_SREV_9285(ah))
 945                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 946         else
 947                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 948
 949         ath9k_init_nfcal_hist_buffer(ah);
 950
 951         return ah;
 952 bad:
 953         if (ah)
 954                 ath9k_hw_detach(ah);
 955         if (status)
 956                 *status = ecode;
 957
 958         return NULL;
 959 }
 960
 961 static void ath9k_hw_init_bb(struct ath_hw *ah,
 962                              struct ath9k_channel *chan)
 963 {
 964         u32 synthDelay;
 965
 966         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 967         if (IS_CHAN_B(chan))
 968                 synthDelay = (4 * synthDelay) / 22;
 969         else
 970                 synthDelay /= 10;
 971
 972         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 973
 974         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 975 }
 976
 977 static void ath9k_hw_init_qos(struct ath_hw *ah)
 978 {
 979         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 980         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 981
 982         REG_WRITE(ah, AR_QOS_NO_ACK,
 983                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 984                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 985                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 986
 987         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 988         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 989         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 990         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 991         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 992 }
 993
 994 static void ath9k_hw_init_pll(struct ath_hw *ah,
 995                               struct ath9k_channel *chan)
 996 {
 997         u32 pll;
 998
 999         if (AR_SREV_9100(ah)) {
1000                 if (chan && IS_CHAN_5GHZ(chan))
1001                         pll = 0x1450;
1002                 else
1003                         pll = 0x1458;
1004         } else {
1005                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1006                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1007
1008                         if (chan && IS_CHAN_HALF_RATE(chan))
1009                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1010                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1011                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1012
1013                         if (chan && IS_CHAN_5GHZ(chan)) {
1014                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1015
1016
1017                                 if (AR_SREV_9280_20(ah)) {
1018                                         if (((chan->channel % 20) == 0)
1019                                             || ((chan->channel % 10) == 0))
1020                                                 pll = 0x2850;
1021                                         else
1022                                                 pll = 0x142c;
1023                                 }
1024                         } else {
1025                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1026                         }
1027
1028                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1029
1030                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1031
1032                         if (chan && IS_CHAN_HALF_RATE(chan))
1033                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1034                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1035                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1036
1037                         if (chan && IS_CHAN_5GHZ(chan))
1038                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1039                         else
1040                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1041                 } else {
1042                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1043
1044                         if (chan && IS_CHAN_HALF_RATE(chan))
1045                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1046                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1047                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1048
1049                         if (chan && IS_CHAN_5GHZ(chan))
1050                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1051                         else
1052                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1053                 }
1054         }
1055         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1056
1057         udelay(RTC_PLL_SETTLE_DELAY);
1058
1059         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1060 }
1061
1062 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1063 {
1064         int rx_chainmask, tx_chainmask;
1065
1066         rx_chainmask = ah->rxchainmask;
1067         tx_chainmask = ah->txchainmask;
1068
1069         switch (rx_chainmask) {
1070         case 0x5:
1071                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1072                             AR_PHY_SWAP_ALT_CHAIN);
1073         case 0x3:
1074                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1075                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1076                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1077                         break;
1078                 }
1079         case 0x1:
1080         case 0x2:
1081         case 0x7:
1082                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1083                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1084                 break;
1085         default:
1086                 break;
1087         }
1088
1089         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1090         if (tx_chainmask == 0x5) {
1091                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1092                             AR_PHY_SWAP_ALT_CHAIN);
1093         }
1094         if (AR_SREV_9100(ah))
1095                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1096                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1097 }
1098
1099 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1100                                           enum nl80211_iftype opmode)
1101 {
1102         ah->mask_reg = AR_IMR_TXERR |
1103                 AR_IMR_TXURN |
1104                 AR_IMR_RXERR |
1105                 AR_IMR_RXORN |
1106                 AR_IMR_BCNMISC;
1107
1108         if (ah->config.intr_mitigation)
1109                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1110         else
1111                 ah->mask_reg |= AR_IMR_RXOK;
1112
1113         ah->mask_reg |= AR_IMR_TXOK;
1114
1115         if (opmode == NL80211_IFTYPE_AP)
1116                 ah->mask_reg |= AR_IMR_MIB;
1117
1118         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1119         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1120
1121         if (!AR_SREV_9100(ah)) {
1122                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1123                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1124                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1125         }
1126 }
1127
1128 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1129 {
1130         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1131                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1132                 ah->acktimeout = (u32) -1;
1133                 return false;
1134         } else {
1135                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1136                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1137                 ah->acktimeout = us;
1138                 return true;
1139         }
1140 }
1141
1142 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1143 {
1144         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1145                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1146                 ah->ctstimeout = (u32) -1;
1147                 return false;
1148         } else {
1149                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1150                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1151                 ah->ctstimeout = us;
1152                 return true;
1153         }
1154 }
1155
1156 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1157 {
1158         if (tu > 0xFFFF) {
1159                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1160                         "bad global tx timeout %u\n", tu);
1161                 ah->globaltxtimeout = (u32) -1;
1162                 return false;
1163         } else {
1164                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1165                 ah->globaltxtimeout = tu;
1166                 return true;
1167         }
1168 }
1169
1170 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1171 {
1172         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1173                 ah->misc_mode);
1174
1175         if (ah->misc_mode != 0)
1176                 REG_WRITE(ah, AR_PCU_MISC,
1177                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1178         if (ah->slottime != (u32) -1)
1179                 ath9k_hw_setslottime(ah, ah->slottime);
1180         if (ah->acktimeout != (u32) -1)
1181                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1182         if (ah->ctstimeout != (u32) -1)
1183                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1184         if (ah->globaltxtimeout != (u32) -1)
1185                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1186 }
1187
1188 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1189 {
1190         return vendorid == ATHEROS_VENDOR_ID ?
1191                 ath9k_hw_devname(devid) : NULL;
1192 }
1193
1194 void ath9k_hw_detach(struct ath_hw *ah)
1195 {
1196         if (!AR_SREV_9100(ah))
1197                 ath9k_hw_ani_detach(ah);
1198
1199         ath9k_hw_rfdetach(ah);
1200         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1201         kfree(ah);
1202 }
1203
1204 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1205 {
1206         struct ath_hw *ah = NULL;
1207
1208         switch (devid) {
1209         case AR5416_DEVID_PCI:
1210         case AR5416_DEVID_PCIE:
1211         case AR5416_AR9100_DEVID:
1212         case AR9160_DEVID_PCI:
1213         case AR9280_DEVID_PCI:
1214         case AR9280_DEVID_PCIE:
1215         case AR9285_DEVID_PCIE:
1216         case AR5416_DEVID_AR9287_PCI:
1217         case AR5416_DEVID_AR9287_PCIE:
1218                 ah = ath9k_hw_do_attach(devid, sc, error);
1219                 break;
1220         default:
1221                 *error = -ENXIO;
1222                 break;
1223         }
1224
1225         return ah;
1226 }
1227
1228 /*******/
1229 /* INI */
1230 /*******/
1231
1232 static void ath9k_hw_override_ini(struct ath_hw *ah,
1233                                   struct ath9k_channel *chan)
1234 {
1235         /*
1236          * Set the RX_ABORT and RX_DIS and clear if off only after
1237          * RXE is set for MAC. This prevents frames with corrupted
1238          * descriptor status.
1239          */
1240         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1241
1242
1243         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1244             AR_SREV_9280_10_OR_LATER(ah))
1245                 return;
1246
1247         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1248 }
1249
1250 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1251                               struct ar5416_eeprom_def *pEepData,
1252                               u32 reg, u32 value)
1253 {
1254         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1255
1256         switch (ah->hw_version.devid) {
1257         case AR9280_DEVID_PCI:
1258                 if (reg == 0x7894) {
1259                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1260                                 "ini VAL: %x  EEPROM: %x\n", value,
1261                                 (pBase->version & 0xff));
1262
1263                         if ((pBase->version & 0xff) > 0x0a) {
1264                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1265                                         "PWDCLKIND: %d\n",
1266                                         pBase->pwdclkind);
1267                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1268                                 value |= AR_AN_TOP2_PWDCLKIND &
1269                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1270                         } else {
1271                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1272                                         "PWDCLKIND Earlier Rev\n");
1273                         }
1274
1275                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1276                                 "final ini VAL: %x\n", value);
1277                 }
1278                 break;
1279         }
1280
1281         return value;
1282 }
1283
1284 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1285                               struct ar5416_eeprom_def *pEepData,
1286                               u32 reg, u32 value)
1287 {
1288         if (ah->eep_map == EEP_MAP_4KBITS)
1289                 return value;
1290         else
1291                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1292 }
1293
1294 static void ath9k_olc_init(struct ath_hw *ah)
1295 {
1296         u32 i;
1297
1298         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1299                 ah->originalGain[i] =
1300                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1301                                         AR_PHY_TX_GAIN);
1302         ah->PDADCdelta = 0;
1303 }
1304
1305 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1306                               struct ath9k_channel *chan)
1307 {
1308         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1309
1310         if (IS_CHAN_B(chan))
1311                 ctl |= CTL_11B;
1312         else if (IS_CHAN_G(chan))
1313                 ctl |= CTL_11G;
1314         else
1315                 ctl |= CTL_11A;
1316
1317         return ctl;
1318 }
1319
1320 static int ath9k_hw_process_ini(struct ath_hw *ah,
1321                                 struct ath9k_channel *chan,
1322                                 enum ath9k_ht_macmode macmode)
1323 {
1324         int i, regWrites = 0;
1325         struct ieee80211_channel *channel = chan->chan;
1326         u32 modesIndex, freqIndex;
1327
1328         switch (chan->chanmode) {
1329         case CHANNEL_A:
1330         case CHANNEL_A_HT20:
1331                 modesIndex = 1;
1332                 freqIndex = 1;
1333                 break;
1334         case CHANNEL_A_HT40PLUS:
1335         case CHANNEL_A_HT40MINUS:
1336                 modesIndex = 2;
1337                 freqIndex = 1;
1338                 break;
1339         case CHANNEL_G:
1340         case CHANNEL_G_HT20:
1341         case CHANNEL_B:
1342                 modesIndex = 4;
1343                 freqIndex = 2;
1344                 break;
1345         case CHANNEL_G_HT40PLUS:
1346         case CHANNEL_G_HT40MINUS:
1347                 modesIndex = 3;
1348                 freqIndex = 2;
1349                 break;
1350
1351         default:
1352                 return -EINVAL;
1353         }
1354
1355         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1356         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1357         ah->eep_ops->set_addac(ah, chan);
1358
1359         if (AR_SREV_5416_22_OR_LATER(ah)) {
1360                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1361         } else {
1362                 struct ar5416IniArray temp;
1363                 u32 addacSize =
1364                         sizeof(u32) * ah->iniAddac.ia_rows *
1365                         ah->iniAddac.ia_columns;
1366
1367                 memcpy(ah->addac5416_21,
1368                        ah->iniAddac.ia_array, addacSize);
1369
1370                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1371
1372                 temp.ia_array = ah->addac5416_21;
1373                 temp.ia_columns = ah->iniAddac.ia_columns;
1374                 temp.ia_rows = ah->iniAddac.ia_rows;
1375                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1376         }
1377
1378         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1379
1380         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1381                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1382                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1383
1384                 REG_WRITE(ah, reg, val);
1385
1386                 if (reg >= 0x7800 && reg < 0x78a0
1387                     && ah->config.analog_shiftreg) {
1388                         udelay(100);
1389                 }
1390
1391                 DO_DELAY(regWrites);
1392         }
1393
1394         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1395                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1396
1397         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1398             AR_SREV_9287_10_OR_LATER(ah))
1399                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1400
1401         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1402                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1403                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1404
1405                 REG_WRITE(ah, reg, val);
1406
1407                 if (reg >= 0x7800 && reg < 0x78a0
1408                     && ah->config.analog_shiftreg) {
1409                         udelay(100);
1410                 }
1411
1412                 DO_DELAY(regWrites);
1413         }
1414
1415         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1416
1417         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1418                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1419                                 regWrites);
1420         }
1421
1422         ath9k_hw_override_ini(ah, chan);
1423         ath9k_hw_set_regs(ah, chan, macmode);
1424         ath9k_hw_init_chain_masks(ah);
1425
1426         if (OLC_FOR_AR9280_20_LATER)
1427                 ath9k_olc_init(ah);
1428
1429         ah->eep_ops->set_txpower(ah, chan,
1430                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1431                                  channel->max_antenna_gain * 2,
1432                                  channel->max_power * 2,
1433                                  min((u32) MAX_RATE_POWER,
1434                                  (u32) ah->regulatory.power_limit));
1435
1436         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1437                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1438                         "ar5416SetRfRegs failed\n");
1439                 return -EIO;
1440         }
1441
1442         return 0;
1443 }
1444
1445 /****************************************/
1446 /* Reset and Channel Switching Routines */
1447 /****************************************/
1448
1449 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1450 {
1451         u32 rfMode = 0;
1452
1453         if (chan == NULL)
1454                 return;
1455
1456         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1457                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1458
1459         if (!AR_SREV_9280_10_OR_LATER(ah))
1460                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1461                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1462
1463         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1464                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1465
1466         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1467 }
1468
1469 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1470 {
1471         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1472 }
1473
1474 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1475 {
1476         u32 regval;
1477
1478         regval = REG_READ(ah, AR_AHB_MODE);
1479         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1480
1481         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1482         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1483
1484         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1485
1486         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1487         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1488
1489         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1490
1491         if (AR_SREV_9285(ah)) {
1492                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1493                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1494         } else {
1495                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1496                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1497         }
1498 }
1499
1500 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1501 {
1502         u32 val;
1503
1504         val = REG_READ(ah, AR_STA_ID1);
1505         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1506         switch (opmode) {
1507         case NL80211_IFTYPE_AP:
1508                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1509                           | AR_STA_ID1_KSRCH_MODE);
1510                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1511                 break;
1512         case NL80211_IFTYPE_ADHOC:
1513         case NL80211_IFTYPE_MESH_POINT:
1514                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1515                           | AR_STA_ID1_KSRCH_MODE);
1516                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1517                 break;
1518         case NL80211_IFTYPE_STATION:
1519         case NL80211_IFTYPE_MONITOR:
1520                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1521                 break;
1522         }
1523 }
1524
1525 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1526                                                  u32 coef_scaled,
1527                                                  u32 *coef_mantissa,
1528                                                  u32 *coef_exponent)
1529 {
1530         u32 coef_exp, coef_man;
1531
1532         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1533                 if ((coef_scaled >> coef_exp) & 0x1)
1534                         break;
1535
1536         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1537
1538         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1539
1540         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1541         *coef_exponent = coef_exp - 16;
1542 }
1543
1544 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1545                                      struct ath9k_channel *chan)
1546 {
1547         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1548         u32 clockMhzScaled = 0x64000000;
1549         struct chan_centers centers;
1550
1551         if (IS_CHAN_HALF_RATE(chan))
1552                 clockMhzScaled = clockMhzScaled >> 1;
1553         else if (IS_CHAN_QUARTER_RATE(chan))
1554                 clockMhzScaled = clockMhzScaled >> 2;
1555
1556         ath9k_hw_get_channel_centers(ah, chan, &centers);
1557         coef_scaled = clockMhzScaled / centers.synth_center;
1558
1559         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1560                                       &ds_coef_exp);
1561
1562         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1563                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1564         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1565                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1566
1567         coef_scaled = (9 * coef_scaled) / 10;
1568
1569         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1570                                       &ds_coef_exp);
1571
1572         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1573                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1574         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1575                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1576 }
1577
1578 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1579 {
1580         u32 rst_flags;
1581         u32 tmpReg;
1582
1583         if (AR_SREV_9100(ah)) {
1584                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1585                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1586                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1587                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1588                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1589         }
1590
1591         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1592                   AR_RTC_FORCE_WAKE_ON_INT);
1593
1594         if (AR_SREV_9100(ah)) {
1595                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1596                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1597         } else {
1598                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1599                 if (tmpReg &
1600                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1601                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1602                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1603                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1604                 } else {
1605                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1606                 }
1607
1608                 rst_flags = AR_RTC_RC_MAC_WARM;
1609                 if (type == ATH9K_RESET_COLD)
1610                         rst_flags |= AR_RTC_RC_MAC_COLD;
1611         }
1612
1613         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1614         udelay(50);
1615
1616         REG_WRITE(ah, AR_RTC_RC, 0);
1617         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1618                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1619                         "RTC stuck in MAC reset\n");
1620                 return false;
1621         }
1622
1623         if (!AR_SREV_9100(ah))
1624                 REG_WRITE(ah, AR_RC, 0);
1625
1626         ath9k_hw_init_pll(ah, NULL);
1627
1628         if (AR_SREV_9100(ah))
1629                 udelay(50);
1630
1631         return true;
1632 }
1633
1634 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1635 {
1636         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1637                   AR_RTC_FORCE_WAKE_ON_INT);
1638
1639         REG_WRITE(ah, AR_RTC_RESET, 0);
1640         udelay(2);
1641         REG_WRITE(ah, AR_RTC_RESET, 1);
1642
1643         if (!ath9k_hw_wait(ah,
1644                            AR_RTC_STATUS,
1645                            AR_RTC_STATUS_M,
1646                            AR_RTC_STATUS_ON,
1647                            AH_WAIT_TIMEOUT)) {
1648                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1649                 return false;
1650         }
1651
1652         ath9k_hw_read_revisions(ah);
1653
1654         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1655 }
1656
1657 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1658 {
1659         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1660                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1661
1662         switch (type) {
1663         case ATH9K_RESET_POWER_ON:
1664                 return ath9k_hw_set_reset_power_on(ah);
1665         case ATH9K_RESET_WARM:
1666         case ATH9K_RESET_COLD:
1667                 return ath9k_hw_set_reset(ah, type);
1668         default:
1669                 return false;
1670         }
1671 }
1672
1673 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1674                               enum ath9k_ht_macmode macmode)
1675 {
1676         u32 phymode;
1677         u32 enableDacFifo = 0;
1678
1679         if (AR_SREV_9285_10_OR_LATER(ah))
1680                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1681                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1682
1683         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1684                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1685
1686         if (IS_CHAN_HT40(chan)) {
1687                 phymode |= AR_PHY_FC_DYN2040_EN;
1688
1689                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1690                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1691                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1692
1693                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1694                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1695         }
1696         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1697
1698         ath9k_hw_set11nmac2040(ah, macmode);
1699
1700         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1701         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1702 }
1703
1704 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1705                                 struct ath9k_channel *chan)
1706 {
1707         if (OLC_FOR_AR9280_20_LATER) {
1708                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1709                         return false;
1710         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1711                 return false;
1712
1713         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1714                 return false;
1715
1716         ah->chip_fullsleep = false;
1717         ath9k_hw_init_pll(ah, chan);
1718         ath9k_hw_set_rfmode(ah, chan);
1719
1720         return true;
1721 }
1722
1723 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1724                                     struct ath9k_channel *chan,
1725                                     enum ath9k_ht_macmode macmode)
1726 {
1727         struct ieee80211_channel *channel = chan->chan;
1728         u32 synthDelay, qnum;
1729
1730         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1731                 if (ath9k_hw_numtxpending(ah, qnum)) {
1732                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1733                                 "Transmit frames pending on queue %d\n", qnum);
1734                         return false;
1735                 }
1736         }
1737
1738         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1739         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1740                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1741                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1742                         "Could not kill baseband RX\n");
1743                 return false;
1744         }
1745
1746         ath9k_hw_set_regs(ah, chan, macmode);
1747
1748         if (AR_SREV_9280_10_OR_LATER(ah)) {
1749                 ath9k_hw_ar9280_set_channel(ah, chan);
1750         } else {
1751                 if (!(ath9k_hw_set_channel(ah, chan))) {
1752                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1753                                 "Failed to set channel\n");
1754                         return false;
1755                 }
1756         }
1757
1758         ah->eep_ops->set_txpower(ah, chan,
1759                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1760                              channel->max_antenna_gain * 2,
1761                              channel->max_power * 2,
1762                              min((u32) MAX_RATE_POWER,
1763                              (u32) ah->regulatory.power_limit));
1764
1765         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1766         if (IS_CHAN_B(chan))
1767                 synthDelay = (4 * synthDelay) / 22;
1768         else
1769                 synthDelay /= 10;
1770
1771         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1772
1773         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1774
1775         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1776                 ath9k_hw_set_delta_slope(ah, chan);
1777
1778         if (AR_SREV_9280_10_OR_LATER(ah))
1779                 ath9k_hw_9280_spur_mitigate(ah, chan);
1780         else
1781                 ath9k_hw_spur_mitigate(ah, chan);
1782
1783         if (!chan->oneTimeCalsDone)
1784                 chan->oneTimeCalsDone = true;
1785
1786         return true;
1787 }
1788
1789 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1790 {
1791         int bb_spur = AR_NO_SPUR;
1792         int freq;
1793         int bin, cur_bin;
1794         int bb_spur_off, spur_subchannel_sd;
1795         int spur_freq_sd;
1796         int spur_delta_phase;
1797         int denominator;
1798         int upper, lower, cur_vit_mask;
1799         int tmp, newVal;
1800         int i;
1801         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1802                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1803         };
1804         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1805                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1806         };
1807         int inc[4] = { 0, 100, 0, 0 };
1808         struct chan_centers centers;
1809
1810         int8_t mask_m[123];
1811         int8_t mask_p[123];
1812         int8_t mask_amt;
1813         int tmp_mask;
1814         int cur_bb_spur;
1815         bool is2GHz = IS_CHAN_2GHZ(chan);
1816
1817         memset(&mask_m, 0, sizeof(int8_t) * 123);
1818         memset(&mask_p, 0, sizeof(int8_t) * 123);
1819
1820         ath9k_hw_get_channel_centers(ah, chan, &centers);
1821         freq = centers.synth_center;
1822
1823         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1824         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1825                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1826
1827                 if (is2GHz)
1828                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1829                 else
1830                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1831
1832                 if (AR_NO_SPUR == cur_bb_spur)
1833                         break;
1834                 cur_bb_spur = cur_bb_spur - freq;
1835
1836                 if (IS_CHAN_HT40(chan)) {
1837                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1838                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1839                                 bb_spur = cur_bb_spur;
1840                                 break;
1841                         }
1842                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1843                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1844                         bb_spur = cur_bb_spur;
1845                         break;
1846                 }
1847         }
1848
1849         if (AR_NO_SPUR == bb_spur) {
1850                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1851                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1852                 return;
1853         } else {
1854                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1855                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1856         }
1857
1858         bin = bb_spur * 320;
1859
1860         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1861
1862         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1863                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1864                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1865                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1866         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1867
1868         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1869                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1870                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1871                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1872                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1873         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1874
1875         if (IS_CHAN_HT40(chan)) {
1876                 if (bb_spur < 0) {
1877                         spur_subchannel_sd = 1;
1878                         bb_spur_off = bb_spur + 10;
1879                 } else {
1880                         spur_subchannel_sd = 0;
1881                         bb_spur_off = bb_spur - 10;
1882                 }
1883         } else {
1884                 spur_subchannel_sd = 0;
1885                 bb_spur_off = bb_spur;
1886         }
1887
1888         if (IS_CHAN_HT40(chan))
1889                 spur_delta_phase =
1890                         ((bb_spur * 262144) /
1891                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1892         else
1893                 spur_delta_phase =
1894                         ((bb_spur * 524288) /
1895                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1896
1897         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1898         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1899
1900         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1901                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1902                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1903         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1904
1905         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1906         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1907
1908         cur_bin = -6000;
1909         upper = bin + 100;
1910         lower = bin - 100;
1911
1912         for (i = 0; i < 4; i++) {
1913                 int pilot_mask = 0;
1914                 int chan_mask = 0;
1915                 int bp = 0;
1916                 for (bp = 0; bp < 30; bp++) {
1917                         if ((cur_bin > lower) && (cur_bin < upper)) {
1918                                 pilot_mask = pilot_mask | 0x1 << bp;
1919                                 chan_mask = chan_mask | 0x1 << bp;
1920                         }
1921                         cur_bin += 100;
1922                 }
1923                 cur_bin += inc[i];
1924                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1925                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1926         }
1927
1928         cur_vit_mask = 6100;
1929         upper = bin + 120;
1930         lower = bin - 120;
1931
1932         for (i = 0; i < 123; i++) {
1933                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1934
1935                         /* workaround for gcc bug #37014 */
1936                         volatile int tmp_v = abs(cur_vit_mask - bin);
1937
1938                         if (tmp_v < 75)
1939                                 mask_amt = 1;
1940                         else
1941                                 mask_amt = 0;
1942                         if (cur_vit_mask < 0)
1943                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1944                         else
1945                                 mask_p[cur_vit_mask / 100] = mask_amt;
1946                 }
1947                 cur_vit_mask -= 100;
1948         }
1949
1950         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1951                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1952                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1953                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1954                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1955                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1956                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1957                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1958         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1959         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1960
1961         tmp_mask = (mask_m[31] << 28)
1962                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1963                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1964                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1965                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1966                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1967                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1968                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1969         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1970         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1971
1972         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1973                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1974                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1975                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1976                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1977                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1978                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1979                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1980         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1981         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1982
1983         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1984                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1985                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1986                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1987                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1988                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1989                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1990                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1991         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1992         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1993
1994         tmp_mask = (mask_p[15] << 28)
1995                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1996                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1997                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1998                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1999                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2000                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2001                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2002         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2003         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2004
2005         tmp_mask = (mask_p[30] << 28)
2006                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2007                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2008                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2009                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2010                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2011                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2012                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2013         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2014         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2015
2016         tmp_mask = (mask_p[45] << 28)
2017                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2018                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2019                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2020                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2021                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2022                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2023                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2024         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2025         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2026
2027         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2028                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2029                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2030                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2031                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2032                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2033                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2034                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2035         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2036         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2037 }
2038
2039 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2040 {
2041         int bb_spur = AR_NO_SPUR;
2042         int bin, cur_bin;
2043         int spur_freq_sd;
2044         int spur_delta_phase;
2045         int denominator;
2046         int upper, lower, cur_vit_mask;
2047         int tmp, new;
2048         int i;
2049         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2050                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2051         };
2052         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2053                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2054         };
2055         int inc[4] = { 0, 100, 0, 0 };
2056
2057         int8_t mask_m[123];
2058         int8_t mask_p[123];
2059         int8_t mask_amt;
2060         int tmp_mask;
2061         int cur_bb_spur;
2062         bool is2GHz = IS_CHAN_2GHZ(chan);
2063
2064         memset(&mask_m, 0, sizeof(int8_t) * 123);
2065         memset(&mask_p, 0, sizeof(int8_t) * 123);
2066
2067         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2068                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2069                 if (AR_NO_SPUR == cur_bb_spur)
2070                         break;
2071                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2072                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2073                         bb_spur = cur_bb_spur;
2074                         break;
2075                 }
2076         }
2077
2078         if (AR_NO_SPUR == bb_spur)
2079                 return;
2080
2081         bin = bb_spur * 32;
2082
2083         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2084         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2085                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2086                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2087                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2088
2089         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2090
2091         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2092                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2093                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2094                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2095                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2096         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2097
2098         spur_delta_phase = ((bb_spur * 524288) / 100) &
2099                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2100
2101         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2102         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2103
2104         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2105                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2106                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2107         REG_WRITE(ah, AR_PHY_TIMING11, new);
2108
2109         cur_bin = -6000;
2110         upper = bin + 100;
2111         lower = bin - 100;
2112
2113         for (i = 0; i < 4; i++) {
2114                 int pilot_mask = 0;
2115                 int chan_mask = 0;
2116                 int bp = 0;
2117                 for (bp = 0; bp < 30; bp++) {
2118                         if ((cur_bin > lower) && (cur_bin < upper)) {
2119                                 pilot_mask = pilot_mask | 0x1 << bp;
2120                                 chan_mask = chan_mask | 0x1 << bp;
2121                         }
2122                         cur_bin += 100;
2123                 }
2124                 cur_bin += inc[i];
2125                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2126                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2127         }
2128
2129         cur_vit_mask = 6100;
2130         upper = bin + 120;
2131         lower = bin - 120;
2132
2133         for (i = 0; i < 123; i++) {
2134                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2135
2136                         /* workaround for gcc bug #37014 */
2137                         volatile int tmp_v = abs(cur_vit_mask - bin);
2138
2139                         if (tmp_v < 75)
2140                                 mask_amt = 1;
2141                         else
2142                                 mask_amt = 0;
2143                         if (cur_vit_mask < 0)
2144                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2145                         else
2146                                 mask_p[cur_vit_mask / 100] = mask_amt;
2147                 }
2148                 cur_vit_mask -= 100;
2149         }
2150
2151         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2152                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2153                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2154                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2155                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2156                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2157                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2158                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2159         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2160         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2161
2162         tmp_mask = (mask_m[31] << 28)
2163                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2164                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2165                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2166                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2167                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2168                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2169                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2170         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2171         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2172
2173         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2174                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2175                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2176                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2177                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2178                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2179                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2180                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2181         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2182         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2183
2184         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2185                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2186                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2187                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2188                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2189                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2190                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2191                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2192         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2193         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2194
2195         tmp_mask = (mask_p[15] << 28)
2196                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2197                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2198                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2199                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2200                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2201                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2202                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2203         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2204         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2205
2206         tmp_mask = (mask_p[30] << 28)
2207                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2208                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2209                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2210                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2211                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2212                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2213                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2214         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2215         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2216
2217         tmp_mask = (mask_p[45] << 28)
2218                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2219                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2220                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2221                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2222                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2223                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2224                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2225         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2226         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2227
2228         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2229                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2230                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2231                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2232                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2233                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2234                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2235                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2236         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2237         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2238 }
2239
2240 static void ath9k_enable_rfkill(struct ath_hw *ah)
2241 {
2242         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2243                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2244
2245         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2246                     AR_GPIO_INPUT_MUX2_RFSILENT);
2247
2248         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2249         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2250 }
2251
2252 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2253                     bool bChannelChange)
2254 {
2255         u32 saveLedState;
2256         struct ath_softc *sc = ah->ah_sc;
2257         struct ath9k_channel *curchan = ah->curchan;
2258         u32 saveDefAntenna;
2259         u32 macStaId1;
2260         int i, rx_chainmask, r;
2261
2262         ah->extprotspacing = sc->ht_extprotspacing;
2263         ah->txchainmask = sc->tx_chainmask;
2264         ah->rxchainmask = sc->rx_chainmask;
2265
2266         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2267                 return -EIO;
2268
2269         if (curchan)
2270                 ath9k_hw_getnf(ah, curchan);
2271
2272         if (bChannelChange &&
2273             (ah->chip_fullsleep != true) &&
2274             (ah->curchan != NULL) &&
2275             (chan->channel != ah->curchan->channel) &&
2276             ((chan->channelFlags & CHANNEL_ALL) ==
2277              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2278             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2279                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2280
2281                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2282                         ath9k_hw_loadnf(ah, ah->curchan);
2283                         ath9k_hw_start_nfcal(ah);
2284                         return 0;
2285                 }
2286         }
2287
2288         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2289         if (saveDefAntenna == 0)
2290                 saveDefAntenna = 1;
2291
2292         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2293
2294         saveLedState = REG_READ(ah, AR_CFG_LED) &
2295                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2296                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2297
2298         ath9k_hw_mark_phy_inactive(ah);
2299
2300         if (!ath9k_hw_chip_reset(ah, chan)) {
2301                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2302                 return -EINVAL;
2303         }
2304
2305         if (AR_SREV_9280_10_OR_LATER(ah))
2306                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2307
2308         if (AR_SREV_9287_10_OR_LATER(ah)) {
2309                 /* Enable ASYNC FIFO */
2310                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2311                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2312                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2313                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2314                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2315                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2316                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2317         }
2318         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2319         if (r)
2320                 return r;
2321
2322         /* Setup MFP options for CCMP */
2323         if (AR_SREV_9280_20_OR_LATER(ah)) {
2324                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2325                  * frames when constructing CCMP AAD. */
2326                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2327                               0xc7ff);
2328                 ah->sw_mgmt_crypto = false;
2329         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2330                 /* Disable hardware crypto for management frames */
2331                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2332                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2333                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2334                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2335                 ah->sw_mgmt_crypto = true;
2336         } else
2337                 ah->sw_mgmt_crypto = true;
2338
2339         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2340                 ath9k_hw_set_delta_slope(ah, chan);
2341
2342         if (AR_SREV_9280_10_OR_LATER(ah))
2343                 ath9k_hw_9280_spur_mitigate(ah, chan);
2344         else
2345                 ath9k_hw_spur_mitigate(ah, chan);
2346
2347         ah->eep_ops->set_board_values(ah, chan);
2348
2349         ath9k_hw_decrease_chain_power(ah, chan);
2350
2351         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2352         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2353                   | macStaId1
2354                   | AR_STA_ID1_RTS_USE_DEF
2355                   | (ah->config.
2356                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2357                   | ah->sta_id1_defaults);
2358         ath9k_hw_set_operating_mode(ah, ah->opmode);
2359
2360         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2361         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2362
2363         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2364
2365         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2366         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2367                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2368
2369         REG_WRITE(ah, AR_ISR, ~0);
2370
2371         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2372
2373         if (AR_SREV_9280_10_OR_LATER(ah))
2374                 ath9k_hw_ar9280_set_channel(ah, chan);
2375         else
2376                 if (!(ath9k_hw_set_channel(ah, chan)))
2377                         return -EIO;
2378
2379         for (i = 0; i < AR_NUM_DCU; i++)
2380                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2381
2382         ah->intr_txqs = 0;
2383         for (i = 0; i < ah->caps.total_queues; i++)
2384                 ath9k_hw_resettxqueue(ah, i);
2385
2386         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2387         ath9k_hw_init_qos(ah);
2388
2389         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2390                 ath9k_enable_rfkill(ah);
2391
2392         ath9k_hw_init_user_settings(ah);
2393
2394         if (AR_SREV_9287_10_OR_LATER(ah)) {
2395                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2396                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2397                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2398                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2399                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2400                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2401
2402                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2403                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2404
2405                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2406                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2407                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2408                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2409         }
2410         if (AR_SREV_9287_10_OR_LATER(ah)) {
2411                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2412                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2413         }
2414
2415         REG_WRITE(ah, AR_STA_ID1,
2416                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2417
2418         ath9k_hw_set_dma(ah);
2419
2420         REG_WRITE(ah, AR_OBS, 8);
2421
2422         if (ah->config.intr_mitigation) {
2423                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2424                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2425         }
2426
2427         ath9k_hw_init_bb(ah, chan);
2428
2429         if (!ath9k_hw_init_cal(ah, chan))
2430                 return -EIO;
2431
2432         rx_chainmask = ah->rxchainmask;
2433         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2434                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2435                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2436         }
2437
2438         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2439
2440         if (AR_SREV_9100(ah)) {
2441                 u32 mask;
2442                 mask = REG_READ(ah, AR_CFG);
2443                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2444                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2445                                 "CFG Byte Swap Set 0x%x\n", mask);
2446                 } else {
2447                         mask =
2448                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2449                         REG_WRITE(ah, AR_CFG, mask);
2450                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2451                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2452                 }
2453         } else {
2454 #ifdef __BIG_ENDIAN
2455                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2456 #endif
2457         }
2458
2459         return 0;
2460 }
2461
2462 /************************/
2463 /* Key Cache Management */
2464 /************************/
2465
2466 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2467 {
2468         u32 keyType;
2469
2470         if (entry >= ah->caps.keycache_size) {
2471                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2472                         "keychache entry %u out of range\n", entry);
2473                 return false;
2474         }
2475
2476         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2477
2478         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2479         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2480         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2481         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2482         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2483         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2484         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2485         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2486
2487         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2488                 u16 micentry = entry + 64;
2489
2490                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2491                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2492                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2493                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2494
2495         }
2496
2497         if (ah->curchan == NULL)
2498                 return true;
2499
2500         return true;
2501 }
2502
2503 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2504 {
2505         u32 macHi, macLo;
2506
2507         if (entry >= ah->caps.keycache_size) {
2508                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2509                         "keychache entry %u out of range\n", entry);
2510                 return false;
2511         }
2512
2513         if (mac != NULL) {
2514                 macHi = (mac[5] << 8) | mac[4];
2515                 macLo = (mac[3] << 24) |
2516                         (mac[2] << 16) |
2517                         (mac[1] << 8) |
2518                         mac[0];
2519                 macLo >>= 1;
2520                 macLo |= (macHi & 1) << 31;
2521                 macHi >>= 1;
2522         } else {
2523                 macLo = macHi = 0;
2524         }
2525         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2526         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2527
2528         return true;
2529 }
2530
2531 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2532                                  const struct ath9k_keyval *k,
2533                                  const u8 *mac)
2534 {
2535         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2536         u32 key0, key1, key2, key3, key4;
2537         u32 keyType;
2538
2539         if (entry >= pCap->keycache_size) {
2540                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2541                         "keycache entry %u out of range\n", entry);
2542                 return false;
2543         }
2544
2545         switch (k->kv_type) {
2546         case ATH9K_CIPHER_AES_OCB:
2547                 keyType = AR_KEYTABLE_TYPE_AES;
2548                 break;
2549         case ATH9K_CIPHER_AES_CCM:
2550                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2551                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2552                                 "AES-CCM not supported by mac rev 0x%x\n",
2553                                 ah->hw_version.macRev);
2554                         return false;
2555                 }
2556                 keyType = AR_KEYTABLE_TYPE_CCM;
2557                 break;
2558         case ATH9K_CIPHER_TKIP:
2559                 keyType = AR_KEYTABLE_TYPE_TKIP;
2560                 if (ATH9K_IS_MIC_ENABLED(ah)
2561                     && entry + 64 >= pCap->keycache_size) {
2562                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2563                                 "entry %u inappropriate for TKIP\n", entry);
2564                         return false;
2565                 }
2566                 break;
2567         case ATH9K_CIPHER_WEP:
2568                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2569                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2570                                 "WEP key length %u too small\n", k->kv_len);
2571                         return false;
2572                 }
2573                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2574                         keyType = AR_KEYTABLE_TYPE_40;
2575                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2576                         keyType = AR_KEYTABLE_TYPE_104;
2577                 else
2578                         keyType = AR_KEYTABLE_TYPE_128;
2579                 break;
2580         case ATH9K_CIPHER_CLR:
2581                 keyType = AR_KEYTABLE_TYPE_CLR;
2582                 break;
2583         default:
2584                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2585                         "cipher %u not supported\n", k->kv_type);
2586                 return false;
2587         }
2588
2589         key0 = get_unaligned_le32(k->kv_val + 0);
2590         key1 = get_unaligned_le16(k->kv_val + 4);
2591         key2 = get_unaligned_le32(k->kv_val + 6);
2592         key3 = get_unaligned_le16(k->kv_val + 10);
2593         key4 = get_unaligned_le32(k->kv_val + 12);
2594         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2595                 key4 &= 0xff;
2596
2597         /*
2598          * Note: Key cache registers access special memory area that requires
2599          * two 32-bit writes to actually update the values in the internal
2600          * memory. Consequently, the exact order and pairs used here must be
2601          * maintained.
2602          */
2603
2604         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2605                 u16 micentry = entry + 64;
2606
2607                 /*
2608                  * Write inverted key[47:0] first to avoid Michael MIC errors
2609                  * on frames that could be sent or received at the same time.
2610                  * The correct key will be written in the end once everything
2611                  * else is ready.
2612                  */
2613                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2614                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2615
2616                 /* Write key[95:48] */
2617                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2618                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2619
2620                 /* Write key[127:96] and key type */
2621                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2622                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2623
2624                 /* Write MAC address for the entry */
2625                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2626
2627                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2628                         /*
2629                          * TKIP uses two key cache entries:
2630                          * Michael MIC TX/RX keys in the same key cache entry
2631                          * (idx = main index + 64):
2632                          * key0 [31:0] = RX key [31:0]
2633                          * key1 [15:0] = TX key [31:16]
2634                          * key1 [31:16] = reserved
2635                          * key2 [31:0] = RX key [63:32]
2636                          * key3 [15:0] = TX key [15:0]
2637                          * key3 [31:16] = reserved
2638                          * key4 [31:0] = TX key [63:32]
2639                          */
2640                         u32 mic0, mic1, mic2, mic3, mic4;
2641
2642                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2643                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2644                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2645                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2646                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2647
2648                         /* Write RX[31:0] and TX[31:16] */
2649                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2650                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2651
2652                         /* Write RX[63:32] and TX[15:0] */
2653                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2654                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2655
2656                         /* Write TX[63:32] and keyType(reserved) */
2657                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2658                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2659                                   AR_KEYTABLE_TYPE_CLR);
2660
2661                 } else {
2662                         /*
2663                          * TKIP uses four key cache entries (two for group
2664                          * keys):
2665                          * Michael MIC TX/RX keys are in different key cache
2666                          * entries (idx = main index + 64 for TX and
2667                          * main index + 32 + 96 for RX):
2668                          * key0 [31:0] = TX/RX MIC key [31:0]
2669                          * key1 [31:0] = reserved
2670                          * key2 [31:0] = TX/RX MIC key [63:32]
2671                          * key3 [31:0] = reserved
2672                          * key4 [31:0] = reserved
2673                          *
2674                          * Upper layer code will call this function separately
2675                          * for TX and RX keys when these registers offsets are
2676                          * used.
2677                          */
2678                         u32 mic0, mic2;
2679
2680                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2681                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2682
2683                         /* Write MIC key[31:0] */
2684                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2685                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2686
2687                         /* Write MIC key[63:32] */
2688                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2689                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2690
2691                         /* Write TX[63:32] and keyType(reserved) */
2692                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2693                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2694                                   AR_KEYTABLE_TYPE_CLR);
2695                 }
2696
2697                 /* MAC address registers are reserved for the MIC entry */
2698                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2699                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2700
2701                 /*
2702                  * Write the correct (un-inverted) key[47:0] last to enable
2703                  * TKIP now that all other registers are set with correct
2704                  * values.
2705                  */
2706                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2707                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2708         } else {
2709                 /* Write key[47:0] */
2710                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2711                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2712
2713                 /* Write key[95:48] */
2714                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2715                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2716
2717                 /* Write key[127:96] and key type */
2718                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2719                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2720
2721                 /* Write MAC address for the entry */
2722                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2723         }
2724
2725         return true;
2726 }
2727
2728 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2729 {
2730         if (entry < ah->caps.keycache_size) {
2731                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2732                 if (val & AR_KEYTABLE_VALID)
2733                         return true;
2734         }
2735         return false;
2736 }
2737
2738 /******************************/
2739 /* Power Management (Chipset) */
2740 /******************************/
2741
2742 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2743 {
2744         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2745         if (setChip) {
2746                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2747                             AR_RTC_FORCE_WAKE_EN);
2748                 if (!AR_SREV_9100(ah))
2749                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2750
2751                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2752                             AR_RTC_RESET_EN);
2753         }
2754 }
2755
2756 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2757 {
2758         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2759         if (setChip) {
2760                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2761
2762                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2763                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2764                                   AR_RTC_FORCE_WAKE_ON_INT);
2765                 } else {
2766                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2767                                     AR_RTC_FORCE_WAKE_EN);
2768                 }
2769         }
2770 }
2771
2772 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2773 {
2774         u32 val;
2775         int i;
2776
2777         if (setChip) {
2778                 if ((REG_READ(ah, AR_RTC_STATUS) &
2779                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2780                         if (ath9k_hw_set_reset_reg(ah,
2781                                            ATH9K_RESET_POWER_ON) != true) {
2782                                 return false;
2783                         }
2784                 }
2785                 if (AR_SREV_9100(ah))
2786                         REG_SET_BIT(ah, AR_RTC_RESET,
2787                                     AR_RTC_RESET_EN);
2788
2789                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2790                             AR_RTC_FORCE_WAKE_EN);
2791                 udelay(50);
2792
2793                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2794                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2795                         if (val == AR_RTC_STATUS_ON)
2796                                 break;
2797                         udelay(50);
2798                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2799                                     AR_RTC_FORCE_WAKE_EN);
2800                 }
2801                 if (i == 0) {
2802                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2803                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2804                         return false;
2805                 }
2806         }
2807
2808         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2809
2810         return true;
2811 }
2812
2813 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2814                                      enum ath9k_power_mode mode)
2815 {
2816         int status = true, setChip = true;
2817         static const char *modes[] = {
2818                 "AWAKE",
2819                 "FULL-SLEEP",
2820                 "NETWORK SLEEP",
2821                 "UNDEFINED"
2822         };
2823
2824         if (ah->power_mode == mode)
2825                 return status;
2826
2827         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2828                 modes[ah->power_mode], modes[mode]);
2829
2830         switch (mode) {
2831         case ATH9K_PM_AWAKE:
2832                 status = ath9k_hw_set_power_awake(ah, setChip);
2833                 break;
2834         case ATH9K_PM_FULL_SLEEP:
2835                 ath9k_set_power_sleep(ah, setChip);
2836                 ah->chip_fullsleep = true;
2837                 break;
2838         case ATH9K_PM_NETWORK_SLEEP:
2839                 ath9k_set_power_network_sleep(ah, setChip);
2840                 break;
2841         default:
2842                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2843                         "Unknown power mode %u\n", mode);
2844                 return false;
2845         }
2846         ah->power_mode = mode;
2847
2848         return status;
2849 }
2850
2851 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2852 {
2853         unsigned long flags;
2854         bool ret;
2855
2856         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2857         ret = ath9k_hw_setpower_nolock(ah, mode);
2858         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2859
2860         return ret;
2861 }
2862
2863 void ath9k_ps_wakeup(struct ath_softc *sc)
2864 {
2865         unsigned long flags;
2866
2867         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2868         if (++sc->ps_usecount != 1)
2869                 goto unlock;
2870
2871         ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2872
2873  unlock:
2874         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2875 }
2876
2877 void ath9k_ps_restore(struct ath_softc *sc)
2878 {
2879         unsigned long flags;
2880
2881         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2882         if (--sc->ps_usecount != 0)
2883                 goto unlock;
2884
2885         if (sc->ps_enabled &&
2886             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2887                               SC_OP_WAIT_FOR_CAB |
2888                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2889                               SC_OP_WAIT_FOR_TX_ACK)))
2890                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2891
2892  unlock:
2893         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2894 }
2895
2896 /*
2897  * Helper for ASPM support.
2898  *
2899  * Disable PLL when in L0s as well as receiver clock when in L1.
2900  * This power saving option must be enabled through the SerDes.
2901  *
2902  * Programming the SerDes must go through the same 288 bit serial shift
2903  * register as the other analog registers.  Hence the 9 writes.
2904  */
2905 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2906 {
2907         u8 i;
2908
2909         if (ah->is_pciexpress != true)
2910                 return;
2911
2912         /* Do not touch SerDes registers */
2913         if (ah->config.pcie_powersave_enable == 2)
2914                 return;
2915
2916         /* Nothing to do on restore for 11N */
2917         if (restore)
2918                 return;
2919
2920         if (AR_SREV_9280_20_OR_LATER(ah)) {
2921                 /*
2922                  * AR9280 2.0 or later chips use SerDes values from the
2923                  * initvals.h initialized depending on chipset during
2924                  * ath9k_hw_do_attach()
2925                  */
2926                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2927                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2928                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2929                 }
2930         } else if (AR_SREV_9280(ah) &&
2931                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2932                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2933                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2934
2935                 /* RX shut off when elecidle is asserted */
2936                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2937                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2938                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2939
2940                 /* Shut off CLKREQ active in L1 */
2941                 if (ah->config.pcie_clock_req)
2942                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2943                 else
2944                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2945
2946                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2947                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2948                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2949
2950                 /* Load the new settings */
2951                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2952
2953         } else {
2954                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2955                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2956
2957                 /* RX shut off when elecidle is asserted */
2958                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2959                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2960                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2961
2962                 /*
2963                  * Ignore ah->ah_config.pcie_clock_req setting for
2964                  * pre-AR9280 11n
2965                  */
2966                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2967
2968                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2969                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2970                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2971
2972                 /* Load the new settings */
2973                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2974         }
2975
2976         udelay(1000);
2977
2978         /* set bit 19 to allow forcing of pcie core into L1 state */
2979         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2980
2981         /* Several PCIe massages to ensure proper behaviour */
2982         if (ah->config.pcie_waen) {
2983                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2984         } else {
2985                 if (AR_SREV_9285(ah))
2986                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2987                 /*
2988                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2989                  * otherwise card may disappear.
2990                  */
2991                 else if (AR_SREV_9280(ah))
2992                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2993                 else
2994                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2995         }
2996 }
2997
2998 /**********************/
2999 /* Interrupt Handling */
3000 /**********************/
3001
3002 bool ath9k_hw_intrpend(struct ath_hw *ah)
3003 {
3004         u32 host_isr;
3005
3006         if (AR_SREV_9100(ah))
3007                 return true;
3008
3009         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3010         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3011                 return true;
3012
3013         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3014         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3015             && (host_isr != AR_INTR_SPURIOUS))
3016                 return true;
3017
3018         return false;
3019 }
3020
3021 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3022 {
3023         u32 isr = 0;
3024         u32 mask2 = 0;
3025         struct ath9k_hw_capabilities *pCap = &ah->caps;
3026         u32 sync_cause = 0;
3027         bool fatal_int = false;
3028
3029         if (!AR_SREV_9100(ah)) {
3030                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3031                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3032                             == AR_RTC_STATUS_ON) {
3033                                 isr = REG_READ(ah, AR_ISR);
3034                         }
3035                 }
3036
3037                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3038                         AR_INTR_SYNC_DEFAULT;
3039
3040                 *masked = 0;
3041
3042                 if (!isr && !sync_cause)
3043                         return false;
3044         } else {
3045                 *masked = 0;
3046                 isr = REG_READ(ah, AR_ISR);
3047         }
3048
3049         if (isr) {
3050                 if (isr & AR_ISR_BCNMISC) {
3051                         u32 isr2;
3052                         isr2 = REG_READ(ah, AR_ISR_S2);
3053                         if (isr2 & AR_ISR_S2_TIM)
3054                                 mask2 |= ATH9K_INT_TIM;
3055                         if (isr2 & AR_ISR_S2_DTIM)
3056                                 mask2 |= ATH9K_INT_DTIM;
3057                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3058                                 mask2 |= ATH9K_INT_DTIMSYNC;
3059                         if (isr2 & (AR_ISR_S2_CABEND))
3060                                 mask2 |= ATH9K_INT_CABEND;
3061                         if (isr2 & AR_ISR_S2_GTT)
3062                                 mask2 |= ATH9K_INT_GTT;
3063                         if (isr2 & AR_ISR_S2_CST)
3064                                 mask2 |= ATH9K_INT_CST;
3065                         if (isr2 & AR_ISR_S2_TSFOOR)
3066                                 mask2 |= ATH9K_INT_TSFOOR;
3067                 }
3068
3069                 isr = REG_READ(ah, AR_ISR_RAC);
3070                 if (isr == 0xffffffff) {
3071                         *masked = 0;
3072                         return false;
3073                 }
3074
3075                 *masked = isr & ATH9K_INT_COMMON;
3076
3077                 if (ah->config.intr_mitigation) {
3078                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3079                                 *masked |= ATH9K_INT_RX;
3080                 }
3081
3082                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3083                         *masked |= ATH9K_INT_RX;
3084                 if (isr &
3085                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3086                      AR_ISR_TXEOL)) {
3087                         u32 s0_s, s1_s;
3088
3089                         *masked |= ATH9K_INT_TX;
3090
3091                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3092                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3093                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3094
3095                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3096                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3097                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3098                 }
3099
3100                 if (isr & AR_ISR_RXORN) {
3101                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3102                                 "receive FIFO overrun interrupt\n");
3103                 }
3104
3105                 if (!AR_SREV_9100(ah)) {
3106                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3107                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3108                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3109                                         *masked |= ATH9K_INT_TIM_TIMER;
3110                         }
3111                 }
3112
3113                 *masked |= mask2;
3114         }
3115
3116         if (AR_SREV_9100(ah))
3117                 return true;
3118
3119         if (sync_cause) {
3120                 fatal_int =
3121                         (sync_cause &
3122                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3123                         ? true : false;
3124
3125                 if (fatal_int) {
3126                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3127                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3128                                         "received PCI FATAL interrupt\n");
3129                         }
3130                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3131                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3132                                         "received PCI PERR interrupt\n");
3133                         }
3134                         *masked |= ATH9K_INT_FATAL;
3135                 }
3136                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3137                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3138                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3139                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3140                         REG_WRITE(ah, AR_RC, 0);
3141                         *masked |= ATH9K_INT_FATAL;
3142                 }
3143                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3144                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3145                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3146                 }
3147
3148                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3149                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3150         }
3151
3152         return true;
3153 }
3154
3155 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3156 {
3157         u32 omask = ah->mask_reg;
3158         u32 mask, mask2;
3159         struct ath9k_hw_capabilities *pCap = &ah->caps;
3160
3161         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3162
3163         if (omask & ATH9K_INT_GLOBAL) {
3164                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3165                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3166                 (void) REG_READ(ah, AR_IER);
3167                 if (!AR_SREV_9100(ah)) {
3168                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3169                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3170
3171                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3172                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3173                 }
3174         }
3175
3176         mask = ints & ATH9K_INT_COMMON;
3177         mask2 = 0;
3178
3179         if (ints & ATH9K_INT_TX) {
3180                 if (ah->txok_interrupt_mask)
3181                         mask |= AR_IMR_TXOK;
3182                 if (ah->txdesc_interrupt_mask)
3183                         mask |= AR_IMR_TXDESC;
3184                 if (ah->txerr_interrupt_mask)
3185                         mask |= AR_IMR_TXERR;
3186                 if (ah->txeol_interrupt_mask)
3187                         mask |= AR_IMR_TXEOL;
3188         }
3189         if (ints & ATH9K_INT_RX) {
3190                 mask |= AR_IMR_RXERR;
3191                 if (ah->config.intr_mitigation)
3192                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3193                 else
3194                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3195                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3196                         mask |= AR_IMR_GENTMR;
3197         }
3198
3199         if (ints & (ATH9K_INT_BMISC)) {
3200                 mask |= AR_IMR_BCNMISC;
3201                 if (ints & ATH9K_INT_TIM)
3202                         mask2 |= AR_IMR_S2_TIM;
3203                 if (ints & ATH9K_INT_DTIM)
3204                         mask2 |= AR_IMR_S2_DTIM;
3205                 if (ints & ATH9K_INT_DTIMSYNC)
3206                         mask2 |= AR_IMR_S2_DTIMSYNC;
3207                 if (ints & ATH9K_INT_CABEND)
3208                         mask2 |= AR_IMR_S2_CABEND;
3209                 if (ints & ATH9K_INT_TSFOOR)
3210                         mask2 |= AR_IMR_S2_TSFOOR;
3211         }
3212
3213         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3214                 mask |= AR_IMR_BCNMISC;
3215                 if (ints & ATH9K_INT_GTT)
3216                         mask2 |= AR_IMR_S2_GTT;
3217                 if (ints & ATH9K_INT_CST)
3218                         mask2 |= AR_IMR_S2_CST;
3219         }
3220
3221         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3222         REG_WRITE(ah, AR_IMR, mask);
3223         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3224                                            AR_IMR_S2_DTIM |
3225                                            AR_IMR_S2_DTIMSYNC |
3226                                            AR_IMR_S2_CABEND |
3227                                            AR_IMR_S2_CABTO |
3228                                            AR_IMR_S2_TSFOOR |
3229                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3230         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3231         ah->mask_reg = ints;
3232
3233         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3234                 if (ints & ATH9K_INT_TIM_TIMER)
3235                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3236                 else
3237                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3238         }
3239
3240         if (ints & ATH9K_INT_GLOBAL) {
3241                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3242                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3243                 if (!AR_SREV_9100(ah)) {
3244                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3245                                   AR_INTR_MAC_IRQ);
3246                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3247
3248
3249                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3250                                   AR_INTR_SYNC_DEFAULT);
3251                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3252                                   AR_INTR_SYNC_DEFAULT);
3253                 }
3254                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3255                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3256         }
3257
3258         return omask;
3259 }
3260
3261 /*******************/
3262 /* Beacon Handling */
3263 /*******************/
3264
3265 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3266 {
3267         int flags = 0;
3268
3269         ah->beacon_interval = beacon_period;
3270
3271         switch (ah->opmode) {
3272         case NL80211_IFTYPE_STATION:
3273         case NL80211_IFTYPE_MONITOR:
3274                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3275                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3276                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3277                 flags |= AR_TBTT_TIMER_EN;
3278                 break;
3279         case NL80211_IFTYPE_ADHOC:
3280         case NL80211_IFTYPE_MESH_POINT:
3281                 REG_SET_BIT(ah, AR_TXCFG,
3282                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3283                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3284                           TU_TO_USEC(next_beacon +
3285                                      (ah->atim_window ? ah->
3286                                       atim_window : 1)));
3287                 flags |= AR_NDP_TIMER_EN;
3288         case NL80211_IFTYPE_AP:
3289                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3290                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3291                           TU_TO_USEC(next_beacon -
3292                                      ah->config.
3293                                      dma_beacon_response_time));
3294                 REG_WRITE(ah, AR_NEXT_SWBA,
3295                           TU_TO_USEC(next_beacon -
3296                                      ah->config.
3297                                      sw_beacon_response_time));
3298                 flags |=
3299                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3300                 break;
3301         default:
3302                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3303                         "%s: unsupported opmode: %d\n",
3304                         __func__, ah->opmode);
3305                 return;
3306                 break;
3307         }
3308
3309         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3310         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3311         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3312         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3313
3314         beacon_period &= ~ATH9K_BEACON_ENA;
3315         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3316                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3317                 ath9k_hw_reset_tsf(ah);
3318         }
3319
3320         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3321 }
3322
3323 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3324                                     const struct ath9k_beacon_state *bs)
3325 {
3326         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3327         struct ath9k_hw_capabilities *pCap = &ah->caps;
3328
3329         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3330
3331         REG_WRITE(ah, AR_BEACON_PERIOD,
3332                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3333         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3334                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3335
3336         REG_RMW_FIELD(ah, AR_RSSI_THR,
3337                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3338
3339         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3340
3341         if (bs->bs_sleepduration > beaconintval)
3342                 beaconintval = bs->bs_sleepduration;
3343
3344         dtimperiod = bs->bs_dtimperiod;
3345         if (bs->bs_sleepduration > dtimperiod)
3346                 dtimperiod = bs->bs_sleepduration;
3347
3348         if (beaconintval == dtimperiod)
3349                 nextTbtt = bs->bs_nextdtim;
3350         else
3351                 nextTbtt = bs->bs_nexttbtt;
3352
3353         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3354         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3355         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3356         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3357
3358         REG_WRITE(ah, AR_NEXT_DTIM,
3359                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3360         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3361
3362         REG_WRITE(ah, AR_SLEEP1,
3363                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3364                   | AR_SLEEP1_ASSUME_DTIM);
3365
3366         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3367                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3368         else
3369                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3370
3371         REG_WRITE(ah, AR_SLEEP2,
3372                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3373
3374         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3375         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3376
3377         REG_SET_BIT(ah, AR_TIMER_MODE,
3378                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3379                     AR_DTIM_TIMER_EN);
3380
3381         /* TSF Out of Range Threshold */
3382         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3383 }
3384
3385 /*******************/
3386 /* HW Capabilities */
3387 /*******************/
3388
3389 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3390 {
3391         struct ath9k_hw_capabilities *pCap = &ah->caps;
3392         u16 capField = 0, eeval;
3393
3394         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3395         ah->regulatory.current_rd = eeval;
3396
3397         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3398         if (AR_SREV_9285_10_OR_LATER(ah))
3399                 eeval |= AR9285_RDEXT_DEFAULT;
3400         ah->regulatory.current_rd_ext = eeval;
3401
3402         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3403
3404         if (ah->opmode != NL80211_IFTYPE_AP &&
3405             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3406                 if (ah->regulatory.current_rd == 0x64 ||
3407                     ah->regulatory.current_rd == 0x65)
3408                         ah->regulatory.current_rd += 5;
3409                 else if (ah->regulatory.current_rd == 0x41)
3410                         ah->regulatory.current_rd = 0x43;
3411                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3412                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3413         }
3414
3415         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3416         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3417
3418         if (eeval & AR5416_OPFLAGS_11A) {
3419                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3420                 if (ah->config.ht_enable) {
3421                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3422                                 set_bit(ATH9K_MODE_11NA_HT20,
3423                                         pCap->wireless_modes);
3424                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3425                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3426                                         pCap->wireless_modes);
3427                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3428                                         pCap->wireless_modes);
3429                         }
3430                 }
3431         }
3432
3433         if (eeval & AR5416_OPFLAGS_11G) {
3434                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3435                 if (ah->config.ht_enable) {
3436                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3437                                 set_bit(ATH9K_MODE_11NG_HT20,
3438                                         pCap->wireless_modes);
3439                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3440                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3441                                         pCap->wireless_modes);
3442                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3443                                         pCap->wireless_modes);
3444                         }
3445                 }
3446         }
3447
3448         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3449         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3450             !(eeval & AR5416_OPFLAGS_11A))
3451                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3452         else
3453                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3454
3455         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3456                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3457
3458         pCap->low_2ghz_chan = 2312;
3459         pCap->high_2ghz_chan = 2732;
3460
3461         pCap->low_5ghz_chan = 4920;
3462         pCap->high_5ghz_chan = 6100;
3463
3464         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3465         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3466         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3467
3468         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3469         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3470         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3471
3472         if (ah->config.ht_enable)
3473                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3474         else
3475                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3476
3477         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3478         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3479         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3480         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3481
3482         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3483                 pCap->total_queues =
3484                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3485         else
3486                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3487
3488         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3489                 pCap->keycache_size =
3490                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3491         else
3492                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3493
3494         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3495         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3496
3497         if (AR_SREV_9285_10_OR_LATER(ah))
3498                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3499         else if (AR_SREV_9280_10_OR_LATER(ah))
3500                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3501         else
3502                 pCap->num_gpio_pins = AR_NUM_GPIO;
3503
3504         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3505                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3506                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3507         } else {
3508                 pCap->rts_aggr_limit = (8 * 1024);
3509         }
3510
3511         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3512
3513 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3514         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3515         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3516                 ah->rfkill_gpio =
3517                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3518                 ah->rfkill_polarity =
3519                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3520
3521                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3522         }
3523 #endif
3524
3525         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3526             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3527             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3528             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3529             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3530             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3531                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3532         else
3533                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3534
3535         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3536                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3537         else
3538                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3539
3540         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3541                 pCap->reg_cap =
3542                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3543                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3544                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3545                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3546         } else {
3547                 pCap->reg_cap =
3548                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3549                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3550         }
3551
3552         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3553
3554         pCap->num_antcfg_5ghz =
3555                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3556         pCap->num_antcfg_2ghz =
3557                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3558
3559         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3560                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3561                 ah->btactive_gpio = 6;
3562                 ah->wlanactive_gpio = 5;
3563         }
3564 }
3565
3566 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3567                             u32 capability, u32 *result)
3568 {
3569         switch (type) {
3570         case ATH9K_CAP_CIPHER:
3571                 switch (capability) {
3572                 case ATH9K_CIPHER_AES_CCM:
3573                 case ATH9K_CIPHER_AES_OCB:
3574                 case ATH9K_CIPHER_TKIP:
3575                 case ATH9K_CIPHER_WEP:
3576                 case ATH9K_CIPHER_MIC:
3577                 case ATH9K_CIPHER_CLR:
3578                         return true;
3579                 default:
3580                         return false;
3581                 }
3582         case ATH9K_CAP_TKIP_MIC:
3583                 switch (capability) {
3584                 case 0:
3585                         return true;
3586                 case 1:
3587                         return (ah->sta_id1_defaults &
3588                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3589                         false;
3590                 }
3591         case ATH9K_CAP_TKIP_SPLIT:
3592                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3593                         false : true;
3594         case ATH9K_CAP_DIVERSITY:
3595                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3596                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3597                         true : false;
3598         case ATH9K_CAP_MCAST_KEYSRCH:
3599                 switch (capability) {
3600                 case 0:
3601                         return true;
3602                 case 1:
3603                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3604                                 return false;
3605                         } else {
3606                                 return (ah->sta_id1_defaults &
3607                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3608                                         false;
3609                         }
3610                 }
3611                 return false;
3612         case ATH9K_CAP_TXPOW:
3613                 switch (capability) {
3614                 case 0:
3615                         return 0;
3616                 case 1:
3617                         *result = ah->regulatory.power_limit;
3618                         return 0;
3619                 case 2:
3620                         *result = ah->regulatory.max_power_level;
3621                         return 0;
3622                 case 3:
3623                         *result = ah->regulatory.tp_scale;
3624                         return 0;
3625                 }
3626                 return false;
3627         case ATH9K_CAP_DS:
3628                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3629                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3630                         ? false : true;
3631         default:
3632                 return false;
3633         }
3634 }
3635
3636 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3637                             u32 capability, u32 setting, int *status)
3638 {
3639         u32 v;
3640
3641         switch (type) {
3642         case ATH9K_CAP_TKIP_MIC:
3643                 if (setting)
3644                         ah->sta_id1_defaults |=
3645                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3646                 else
3647                         ah->sta_id1_defaults &=
3648                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3649                 return true;
3650         case ATH9K_CAP_DIVERSITY:
3651                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3652                 if (setting)
3653                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3654                 else
3655                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3656                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3657                 return true;
3658         case ATH9K_CAP_MCAST_KEYSRCH:
3659                 if (setting)
3660                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3661                 else
3662                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3663                 return true;
3664         default:
3665                 return false;
3666         }
3667 }
3668
3669 /****************************/
3670 /* GPIO / RFKILL / Antennae */
3671 /****************************/
3672
3673 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3674                                          u32 gpio, u32 type)
3675 {
3676         int addr;
3677         u32 gpio_shift, tmp;
3678
3679         if (gpio > 11)
3680                 addr = AR_GPIO_OUTPUT_MUX3;
3681         else if (gpio > 5)
3682                 addr = AR_GPIO_OUTPUT_MUX2;
3683         else
3684                 addr = AR_GPIO_OUTPUT_MUX1;
3685
3686         gpio_shift = (gpio % 6) * 5;
3687
3688         if (AR_SREV_9280_20_OR_LATER(ah)
3689             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3690                 REG_RMW(ah, addr, (type << gpio_shift),
3691                         (0x1f << gpio_shift));
3692         } else {
3693                 tmp = REG_READ(ah, addr);
3694                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3695                 tmp &= ~(0x1f << gpio_shift);
3696                 tmp |= (type << gpio_shift);
3697                 REG_WRITE(ah, addr, tmp);
3698         }
3699 }
3700
3701 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3702 {
3703         u32 gpio_shift;
3704
3705         ASSERT(gpio < ah->caps.num_gpio_pins);
3706
3707         gpio_shift = gpio << 1;
3708
3709         REG_RMW(ah,
3710                 AR_GPIO_OE_OUT,
3711                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3712                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3713 }
3714
3715 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3716 {
3717 #define MS_REG_READ(x, y) \
3718         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3719
3720         if (gpio >= ah->caps.num_gpio_pins)
3721                 return 0xffffffff;
3722
3723         if (AR_SREV_9287_10_OR_LATER(ah))
3724                 return MS_REG_READ(AR9287, gpio) != 0;
3725         else if (AR_SREV_9285_10_OR_LATER(ah))
3726                 return MS_REG_READ(AR9285, gpio) != 0;
3727         else if (AR_SREV_9280_10_OR_LATER(ah))
3728                 return MS_REG_READ(AR928X, gpio) != 0;
3729         else
3730                 return MS_REG_READ(AR, gpio) != 0;
3731 }
3732
3733 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3734                          u32 ah_signal_type)
3735 {
3736         u32 gpio_shift;
3737
3738         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3739
3740         gpio_shift = 2 * gpio;
3741
3742         REG_RMW(ah,
3743                 AR_GPIO_OE_OUT,
3744                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3745                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3746 }
3747
3748 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3749 {
3750         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3751                 AR_GPIO_BIT(gpio));
3752 }
3753
3754 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3755 {
3756         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3757 }
3758
3759 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3760 {
3761         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3762 }
3763
3764 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3765                                enum ath9k_ant_setting settings,
3766                                struct ath9k_channel *chan,
3767                                u8 *tx_chainmask,
3768                                u8 *rx_chainmask,
3769                                u8 *antenna_cfgd)
3770 {
3771         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3772
3773         if (AR_SREV_9280(ah)) {
3774                 if (!tx_chainmask_cfg) {
3775
3776                         tx_chainmask_cfg = *tx_chainmask;
3777                         rx_chainmask_cfg = *rx_chainmask;
3778                 }
3779
3780                 switch (settings) {
3781                 case ATH9K_ANT_FIXED_A:
3782                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3783                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3784                         *antenna_cfgd = true;
3785                         break;
3786                 case ATH9K_ANT_FIXED_B:
3787                         if (ah->caps.tx_chainmask >
3788                             ATH9K_ANTENNA1_CHAINMASK) {
3789                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3790                         }
3791                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3792                         *antenna_cfgd = true;
3793                         break;
3794                 case ATH9K_ANT_VARIABLE:
3795                         *tx_chainmask = tx_chainmask_cfg;
3796                         *rx_chainmask = rx_chainmask_cfg;
3797                         *antenna_cfgd = true;
3798                         break;
3799                 default:
3800                         break;
3801                 }
3802         } else {
3803                 ah->diversity_control = settings;
3804         }
3805
3806         return true;
3807 }
3808
3809 /*********************/
3810 /* General Operation */
3811 /*********************/
3812
3813 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3814 {
3815         u32 bits = REG_READ(ah, AR_RX_FILTER);
3816         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3817
3818         if (phybits & AR_PHY_ERR_RADAR)
3819                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3820         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3821                 bits |= ATH9K_RX_FILTER_PHYERR;
3822
3823         return bits;
3824 }
3825
3826 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3827 {
3828         u32 phybits;
3829
3830         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3831         phybits = 0;
3832         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3833                 phybits |= AR_PHY_ERR_RADAR;
3834         if (bits & ATH9K_RX_FILTER_PHYERR)
3835                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3836         REG_WRITE(ah, AR_PHY_ERR, phybits);
3837
3838         if (phybits)
3839                 REG_WRITE(ah, AR_RXCFG,
3840                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3841         else
3842                 REG_WRITE(ah, AR_RXCFG,
3843                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3844 }
3845
3846 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3847 {
3848         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3849 }
3850
3851 bool ath9k_hw_disable(struct ath_hw *ah)
3852 {
3853         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3854                 return false;
3855
3856         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3857 }
3858
3859 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3860 {
3861         struct ath9k_channel *chan = ah->curchan;
3862         struct ieee80211_channel *channel = chan->chan;
3863
3864         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3865
3866         ah->eep_ops->set_txpower(ah, chan,
3867                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3868                                  channel->max_antenna_gain * 2,
3869                                  channel->max_power * 2,
3870                                  min((u32) MAX_RATE_POWER,
3871                                  (u32) ah->regulatory.power_limit));
3872 }
3873
3874 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3875 {
3876         memcpy(ah->macaddr, mac, ETH_ALEN);
3877 }
3878
3879 void ath9k_hw_setopmode(struct ath_hw *ah)
3880 {
3881         ath9k_hw_set_operating_mode(ah, ah->opmode);
3882 }
3883
3884 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3885 {
3886         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3887         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3888 }
3889
3890 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3891 {
3892         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3893         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3894 }
3895
3896 void ath9k_hw_write_associd(struct ath_softc *sc)
3897 {
3898         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3899         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3900                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3901 }
3902
3903 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3904 {
3905         u64 tsf;
3906
3907         tsf = REG_READ(ah, AR_TSF_U32);
3908         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3909
3910         return tsf;
3911 }
3912
3913 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3914 {
3915         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3916         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3917 }
3918
3919 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3920 {
3921         ath9k_ps_wakeup(ah->ah_sc);
3922         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3923                            AH_TSF_WRITE_TIMEOUT))
3924                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3925                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3926
3927         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3928         ath9k_ps_restore(ah->ah_sc);
3929 }
3930
3931 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3932 {
3933         if (setting)
3934                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3935         else
3936                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3937
3938         return true;
3939 }
3940
3941 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3942 {
3943         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3944                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3945                 ah->slottime = (u32) -1;
3946                 return false;
3947         } else {
3948                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3949                 ah->slottime = us;
3950                 return true;
3951         }
3952 }
3953
3954 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3955 {
3956         u32 macmode;
3957
3958         if (mode == ATH9K_HT_MACMODE_2040 &&
3959             !ah->config.cwm_ignore_extcca)
3960                 macmode = AR_2040_JOINED_RX_CLEAR;
3961         else
3962                 macmode = 0;
3963
3964         REG_WRITE(ah, AR_2040_MODE, macmode);
3965 }
3966
3967 /***************************/
3968 /*  Bluetooth Coexistence  */
3969 /***************************/
3970
3971 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3972 {
3973         /* connect bt_active to baseband */
3974         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3975                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3976                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3977
3978         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3979                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3980
3981         /* Set input mux for bt_active to gpio pin */
3982         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3983                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3984                         ah->btactive_gpio);
3985
3986         /* Configure the desired gpio port for input */
3987         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3988
3989         /* Configure the desired GPIO port for TX_FRAME output */
3990         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3991                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3992 }