drivers/net/wireless/ath/ath9k/htc_drv_init.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "htc.h"
  18
  19 MODULE_AUTHOR("Atheros Communications");
  20 MODULE_LICENSE("Dual BSD/GPL");
  21 MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  22
  23 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  24 module_param_named(debug, ath9k_debug, uint, 0);
  25 MODULE_PARM_DESC(debug, "Debugging mask");
  26
  27 int htc_modparam_nohwcrypt;
  28 module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  29 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  30
  31 #define CHAN2G(_freq, _idx)  { \
  32         .center_freq = (_freq), \
  33         .hw_value = (_idx), \
  34         .max_power = 20, \
  35 }
  36
  37 #define CHAN5G(_freq, _idx) { \
  38         .band = IEEE80211_BAND_5GHZ, \
  39         .center_freq = (_freq), \
  40         .hw_value = (_idx), \
  41         .max_power = 20, \
  42 }
  43
  44 #define ATH_HTC_BTCOEX_PRODUCT_ID "wb193"
  45
  46 static struct ieee80211_channel ath9k_2ghz_channels[] = {
  47         CHAN2G(2412, 0), /* Channel 1 */
  48         CHAN2G(2417, 1), /* Channel 2 */
  49         CHAN2G(2422, 2), /* Channel 3 */
  50         CHAN2G(2427, 3), /* Channel 4 */
  51         CHAN2G(2432, 4), /* Channel 5 */
  52         CHAN2G(2437, 5), /* Channel 6 */
  53         CHAN2G(2442, 6), /* Channel 7 */
  54         CHAN2G(2447, 7), /* Channel 8 */
  55         CHAN2G(2452, 8), /* Channel 9 */
  56         CHAN2G(2457, 9), /* Channel 10 */
  57         CHAN2G(2462, 10), /* Channel 11 */
  58         CHAN2G(2467, 11), /* Channel 12 */
  59         CHAN2G(2472, 12), /* Channel 13 */
  60         CHAN2G(2484, 13), /* Channel 14 */
  61 };
  62
  63 static struct ieee80211_channel ath9k_5ghz_channels[] = {
  64         /* _We_ call this UNII 1 */
  65         CHAN5G(5180, 14), /* Channel 36 */
  66         CHAN5G(5200, 15), /* Channel 40 */
  67         CHAN5G(5220, 16), /* Channel 44 */
  68         CHAN5G(5240, 17), /* Channel 48 */
  69         /* _We_ call this UNII 2 */
  70         CHAN5G(5260, 18), /* Channel 52 */
  71         CHAN5G(5280, 19), /* Channel 56 */
  72         CHAN5G(5300, 20), /* Channel 60 */
  73         CHAN5G(5320, 21), /* Channel 64 */
  74         /* _We_ call this "Middle band" */
  75         CHAN5G(5500, 22), /* Channel 100 */
  76         CHAN5G(5520, 23), /* Channel 104 */
  77         CHAN5G(5540, 24), /* Channel 108 */
  78         CHAN5G(5560, 25), /* Channel 112 */
  79         CHAN5G(5580, 26), /* Channel 116 */
  80         CHAN5G(5600, 27), /* Channel 120 */
  81         CHAN5G(5620, 28), /* Channel 124 */
  82         CHAN5G(5640, 29), /* Channel 128 */
  83         CHAN5G(5660, 30), /* Channel 132 */
  84         CHAN5G(5680, 31), /* Channel 136 */
  85         CHAN5G(5700, 32), /* Channel 140 */
  86         /* _We_ call this UNII 3 */
  87         CHAN5G(5745, 33), /* Channel 149 */
  88         CHAN5G(5765, 34), /* Channel 153 */
  89         CHAN5G(5785, 35), /* Channel 157 */
  90         CHAN5G(5805, 36), /* Channel 161 */
  91         CHAN5G(5825, 37), /* Channel 165 */
  92 };
  93
  94 /* Atheros hardware rate code addition for short premble */
  95 #define SHPCHECK(__hw_rate, __flags) \
  96         ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
  97
  98 #define RATE(_bitrate, _hw_rate, _flags) {              \
  99         .bitrate        = (_bitrate),                   \
 100         .flags          = (_flags),                     \
 101         .hw_value       = (_hw_rate),                   \
 102         .hw_value_short = (SHPCHECK(_hw_rate, _flags))  \
 103 }
 104
 105 static struct ieee80211_rate ath9k_legacy_rates[] = {
 106         RATE(10, 0x1b, 0),
 107         RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
 108         RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
 109         RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
 110         RATE(60, 0x0b, 0),
 111         RATE(90, 0x0f, 0),
 112         RATE(120, 0x0a, 0),
 113         RATE(180, 0x0e, 0),
 114         RATE(240, 0x09, 0),
 115         RATE(360, 0x0d, 0),
 116         RATE(480, 0x08, 0),
 117         RATE(540, 0x0c, 0),
 118 };
 119
 120 static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
 121 {
 122         int time_left;
 123
 124         if (atomic_read(&priv->htc->tgt_ready) > 0) {
 125                 atomic_dec(&priv->htc->tgt_ready);
 126                 return 0;
 127         }
 128
 129         /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
 130         time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
 131         if (!time_left) {
 132                 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
 133                 return -ETIMEDOUT;
 134         }
 135
 136         atomic_dec(&priv->htc->tgt_ready);
 137
 138         return 0;
 139 }
 140
 141 static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
 142 {
 143         ath9k_htc_exit_debug(priv->ah);
 144         ath9k_hw_deinit(priv->ah);
 145         tasklet_kill(&priv->swba_tasklet);
 146         tasklet_kill(&priv->rx_tasklet);
 147         tasklet_kill(&priv->tx_tasklet);
 148         kfree(priv->ah);
 149         priv->ah = NULL;
 150 }
 151
 152 static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
 153 {
 154         struct ieee80211_hw *hw = priv->hw;
 155
 156         wiphy_rfkill_stop_polling(hw->wiphy);
 157         ath9k_deinit_leds(priv);
 158         ieee80211_unregister_hw(hw);
 159         ath9k_rx_cleanup(priv);
 160         ath9k_tx_cleanup(priv);
 161         ath9k_deinit_priv(priv);
 162 }
 163
 164 static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
 165                                         u16 service_id,
 166                                         void (*tx) (void *,
 167                                                     struct sk_buff *,
 168                                                     enum htc_endpoint_id,
 169                                                     bool txok),
 170                                         enum htc_endpoint_id *ep_id)
 171 {
 172         struct htc_service_connreq req;
 173
 174         memset(&req, 0, sizeof(struct htc_service_connreq));
 175
 176         req.service_id = service_id;
 177         req.ep_callbacks.priv = priv;
 178         req.ep_callbacks.rx = ath9k_htc_rxep;
 179         req.ep_callbacks.tx = tx;
 180
 181         return htc_connect_service(priv->htc, &req, ep_id);
 182 }
 183
 184 static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
 185                                    u32 drv_info)
 186 {
 187         int ret;
 188
 189         /* WMI CMD*/
 190         ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
 191         if (ret)
 192                 goto err;
 193
 194         /* Beacon */
 195         ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
 196                                     &priv->beacon_ep);
 197         if (ret)
 198                 goto err;
 199
 200         /* CAB */
 201         ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
 202                                     &priv->cab_ep);
 203         if (ret)
 204                 goto err;
 205
 206
 207         /* UAPSD */
 208         ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
 209                                     &priv->uapsd_ep);
 210         if (ret)
 211                 goto err;
 212
 213         /* MGMT */
 214         ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
 215                                     &priv->mgmt_ep);
 216         if (ret)
 217                 goto err;
 218
 219         /* DATA BE */
 220         ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
 221                                     &priv->data_be_ep);
 222         if (ret)
 223                 goto err;
 224
 225         /* DATA BK */
 226         ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
 227                                     &priv->data_bk_ep);
 228         if (ret)
 229                 goto err;
 230
 231         /* DATA VI */
 232         ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
 233                                     &priv->data_vi_ep);
 234         if (ret)
 235                 goto err;
 236
 237         /* DATA VO */
 238         ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
 239                                     &priv->data_vo_ep);
 240         if (ret)
 241                 goto err;
 242
 243         /*
 244          * Setup required credits before initializing HTC.
 245          * This is a bit hacky, but, since queuing is done in
 246          * the HIF layer, shouldn't matter much.
 247          */
 248
 249         if (IS_AR7010_DEVICE(drv_info))
 250                 priv->htc->credits = 45;
 251         else
 252                 priv->htc->credits = 33;
 253
 254         ret = htc_init(priv->htc);
 255         if (ret)
 256                 goto err;
 257
 258         dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
 259                  priv->htc->credits);
 260
 261         return 0;
 262
 263 err:
 264         dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
 265         return ret;
 266 }
 267
 268 static int ath9k_reg_notifier(struct wiphy *wiphy,
 269                               struct regulatory_request *request)
 270 {
 271         struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
 272         struct ath9k_htc_priv *priv = hw->priv;
 273
 274         return ath_reg_notifier_apply(wiphy, request,
 275                                       ath9k_hw_regulatory(priv->ah));
 276 }
 277
 278 static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
 279 {
 280         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 281         struct ath_common *common = ath9k_hw_common(ah);
 282         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 283         __be32 val, reg = cpu_to_be32(reg_offset);
 284         int r;
 285
 286         r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
 287                           (u8 *) &reg, sizeof(reg),
 288                           (u8 *) &val, sizeof(val),
 289                           100);
 290         if (unlikely(r)) {
 291                 ath_dbg(common, ATH_DBG_WMI,
 292                         "REGISTER READ FAILED: (0x%04x, %d)\n",
 293                         reg_offset, r);
 294                 return -EIO;
 295         }
 296
 297         return be32_to_cpu(val);
 298 }
 299
 300 static void ath9k_multi_regread(void *hw_priv, u32 *addr,
 301                                 u32 *val, u16 count)
 302 {
 303         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 304         struct ath_common *common = ath9k_hw_common(ah);
 305         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 306         __be32 tmpaddr[8];
 307         __be32 tmpval[8];
 308         int i, ret;
 309
 310        for (i = 0; i < count; i++) {
 311                tmpaddr[i] = cpu_to_be32(addr[i]);
 312        }
 313
 314        ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
 315                            (u8 *)tmpaddr , sizeof(u32) * count,
 316                            (u8 *)tmpval, sizeof(u32) * count,
 317                            100);
 318         if (unlikely(ret)) {
 319                 ath_dbg(common, ATH_DBG_WMI,
 320                         "Multiple REGISTER READ FAILED (count: %d)\n", count);
 321         }
 322
 323        for (i = 0; i < count; i++) {
 324                val[i] = be32_to_cpu(tmpval[i]);
 325        }
 326 }
 327
 328 static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
 329 {
 330         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 331         struct ath_common *common = ath9k_hw_common(ah);
 332         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 333         const __be32 buf[2] = {
 334                 cpu_to_be32(reg_offset),
 335                 cpu_to_be32(val),
 336         };
 337         int r;
 338
 339         r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
 340                           (u8 *) &buf, sizeof(buf),
 341                           (u8 *) &val, sizeof(val),
 342                           100);
 343         if (unlikely(r)) {
 344                 ath_dbg(common, ATH_DBG_WMI,
 345                         "REGISTER WRITE FAILED:(0x%04x, %d)\n",
 346                         reg_offset, r);
 347         }
 348 }
 349
 350 static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
 351 {
 352         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 353         struct ath_common *common = ath9k_hw_common(ah);
 354         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 355         u32 rsp_status;
 356         int r;
 357
 358         mutex_lock(&priv->wmi->multi_write_mutex);
 359
 360         /* Store the register/value */
 361         priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
 362                 cpu_to_be32(reg_offset);
 363         priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
 364                 cpu_to_be32(val);
 365
 366         priv->wmi->multi_write_idx++;
 367
 368         /* If the buffer is full, send it out. */
 369         if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
 370                 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
 371                           (u8 *) &priv->wmi->multi_write,
 372                           sizeof(struct register_write) * priv->wmi->multi_write_idx,
 373                           (u8 *) &rsp_status, sizeof(rsp_status),
 374                           100);
 375                 if (unlikely(r)) {
 376                         ath_dbg(common, ATH_DBG_WMI,
 377                                 "REGISTER WRITE FAILED, multi len: %d\n",
 378                                 priv->wmi->multi_write_idx);
 379                 }
 380                 priv->wmi->multi_write_idx = 0;
 381         }
 382
 383         mutex_unlock(&priv->wmi->multi_write_mutex);
 384 }
 385
 386 static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
 387 {
 388         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 389         struct ath_common *common = ath9k_hw_common(ah);
 390         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 391
 392         if (atomic_read(&priv->wmi->mwrite_cnt))
 393                 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
 394         else
 395                 ath9k_regwrite_single(hw_priv, val, reg_offset);
 396 }
 397
 398 static void ath9k_enable_regwrite_buffer(void *hw_priv)
 399 {
 400         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 401         struct ath_common *common = ath9k_hw_common(ah);
 402         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 403
 404         atomic_inc(&priv->wmi->mwrite_cnt);
 405 }
 406
 407 static void ath9k_regwrite_flush(void *hw_priv)
 408 {
 409         struct ath_hw *ah = (struct ath_hw *) hw_priv;
 410         struct ath_common *common = ath9k_hw_common(ah);
 411         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
 412         u32 rsp_status;
 413         int r;
 414
 415         atomic_dec(&priv->wmi->mwrite_cnt);
 416
 417         mutex_lock(&priv->wmi->multi_write_mutex);
 418
 419         if (priv->wmi->multi_write_idx) {
 420                 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
 421                           (u8 *) &priv->wmi->multi_write,
 422                           sizeof(struct register_write) * priv->wmi->multi_write_idx,
 423                           (u8 *) &rsp_status, sizeof(rsp_status),
 424                           100);
 425                 if (unlikely(r)) {
 426                         ath_dbg(common, ATH_DBG_WMI,
 427                                 "REGISTER WRITE FAILED, multi len: %d\n",
 428                                 priv->wmi->multi_write_idx);
 429                 }
 430                 priv->wmi->multi_write_idx = 0;
 431         }
 432
 433         mutex_unlock(&priv->wmi->multi_write_mutex);
 434 }
 435
 436 static const struct ath_ops ath9k_common_ops = {
 437         .read = ath9k_regread,
 438         .multi_read = ath9k_multi_regread,
 439         .write = ath9k_regwrite,
 440         .enable_write_buffer = ath9k_enable_regwrite_buffer,
 441         .write_flush = ath9k_regwrite_flush,
 442 };
 443
 444 static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
 445 {
 446         *csz = L1_CACHE_BYTES >> 2;
 447 }
 448
 449 static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 450 {
 451         struct ath_hw *ah = (struct ath_hw *) common->ah;
 452
 453         (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
 454
 455         if (!ath9k_hw_wait(ah,
 456                            AR_EEPROM_STATUS_DATA,
 457                            AR_EEPROM_STATUS_DATA_BUSY |
 458                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
 459                            AH_WAIT_TIMEOUT))
 460                 return false;
 461
 462         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
 463                    AR_EEPROM_STATUS_DATA_VAL);
 464
 465         return true;
 466 }
 467
 468 static const struct ath_bus_ops ath9k_usb_bus_ops = {
 469         .ath_bus_type = ATH_USB,
 470         .read_cachesize = ath_usb_read_cachesize,
 471         .eeprom_read = ath_usb_eeprom_read,
 472 };
 473
 474 static void setup_ht_cap(struct ath9k_htc_priv *priv,
 475                          struct ieee80211_sta_ht_cap *ht_info)
 476 {
 477         struct ath_common *common = ath9k_hw_common(priv->ah);
 478         u8 tx_streams, rx_streams;
 479         int i;
 480
 481         ht_info->ht_supported = true;
 482         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 483                        IEEE80211_HT_CAP_SM_PS |
 484                        IEEE80211_HT_CAP_SGI_40 |
 485                        IEEE80211_HT_CAP_DSSSCCK40;
 486
 487         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
 488                 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
 489
 490         ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
 491
 492         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
 493         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 494
 495         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 496
 497         /* ath9k_htc supports only 1 or 2 stream devices */
 498         tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
 499         rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
 500
 501         ath_dbg(common, ATH_DBG_CONFIG,
 502                 "TX streams %d, RX streams: %d\n",
 503                 tx_streams, rx_streams);
 504
 505         if (tx_streams != rx_streams) {
 506                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
 507                 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
 508                                            IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 509         }
 510
 511         for (i = 0; i < rx_streams; i++)
 512                 ht_info->mcs.rx_mask[i] = 0xff;
 513
 514         ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
 515 }
 516
 517 static int ath9k_init_queues(struct ath9k_htc_priv *priv)
 518 {
 519         struct ath_common *common = ath9k_hw_common(priv->ah);
 520         int i;
 521
 522         for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
 523                 priv->hwq_map[i] = -1;
 524
 525         priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
 526         if (priv->beaconq == -1) {
 527                 ath_err(common, "Unable to setup BEACON xmit queue\n");
 528                 goto err;
 529         }
 530
 531         priv->cabq = ath9k_htc_cabq_setup(priv);
 532         if (priv->cabq == -1) {
 533                 ath_err(common, "Unable to setup CAB xmit queue\n");
 534                 goto err;
 535         }
 536
 537         if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
 538                 ath_err(common, "Unable to setup xmit queue for BE traffic\n");
 539                 goto err;
 540         }
 541
 542         if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
 543                 ath_err(common, "Unable to setup xmit queue for BK traffic\n");
 544                 goto err;
 545         }
 546         if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
 547                 ath_err(common, "Unable to setup xmit queue for VI traffic\n");
 548                 goto err;
 549         }
 550         if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
 551                 ath_err(common, "Unable to setup xmit queue for VO traffic\n");
 552                 goto err;
 553         }
 554
 555         return 0;
 556
 557 err:
 558         return -EINVAL;
 559 }
 560
 561 static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
 562 {
 563         struct ath_common *common = ath9k_hw_common(priv->ah);
 564         int i = 0;
 565
 566         /* Get the hardware key cache size. */
 567         common->keymax = priv->ah->caps.keycache_size;
 568         if (common->keymax > ATH_KEYMAX) {
 569                 ath_dbg(common, ATH_DBG_ANY,
 570                         "Warning, using only %u entries in %u key cache\n",
 571                         ATH_KEYMAX, common->keymax);
 572                 common->keymax = ATH_KEYMAX;
 573         }
 574
 575         if (priv->ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
 576                 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
 577
 578         /*
 579          * Reset the key cache since some parts do not
 580          * reset the contents on initial power up.
 581          */
 582         for (i = 0; i < common->keymax; i++)
 583                 ath_hw_keyreset(common, (u16) i);
 584 }
 585
 586 static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
 587 {
 588         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
 589                 priv->sbands[IEEE80211_BAND_2GHZ].channels =
 590                         ath9k_2ghz_channels;
 591                 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
 592                 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
 593                         ARRAY_SIZE(ath9k_2ghz_channels);
 594                 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
 595                 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
 596                         ARRAY_SIZE(ath9k_legacy_rates);
 597         }
 598
 599         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
 600                 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels;
 601                 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
 602                 priv->sbands[IEEE80211_BAND_5GHZ].n_channels =
 603                         ARRAY_SIZE(ath9k_5ghz_channels);
 604                 priv->sbands[IEEE80211_BAND_5GHZ].bitrates =
 605                         ath9k_legacy_rates + 4;
 606                 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
 607                         ARRAY_SIZE(ath9k_legacy_rates) - 4;
 608         }
 609 }
 610
 611 static void ath9k_init_misc(struct ath9k_htc_priv *priv)
 612 {
 613         struct ath_common *common = ath9k_hw_common(priv->ah);
 614
 615         common->tx_chainmask = priv->ah->caps.tx_chainmask;
 616         common->rx_chainmask = priv->ah->caps.rx_chainmask;
 617
 618         memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
 619
 620         priv->ah->opmode = NL80211_IFTYPE_STATION;
 621 }
 622
 623 static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
 624 {
 625         int qnum;
 626
 627         switch (priv->ah->btcoex_hw.scheme) {
 628         case ATH_BTCOEX_CFG_NONE:
 629                 break;
 630         case ATH_BTCOEX_CFG_3WIRE:
 631                 priv->ah->btcoex_hw.btactive_gpio = 7;
 632                 priv->ah->btcoex_hw.btpriority_gpio = 6;
 633                 priv->ah->btcoex_hw.wlanactive_gpio = 8;
 634                 priv->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
 635                 ath9k_hw_btcoex_init_3wire(priv->ah);
 636                 ath_htc_init_btcoex_work(priv);
 637                 qnum = priv->hwq_map[WME_AC_BE];
 638                 ath9k_hw_init_btcoex_hw(priv->ah, qnum);
 639                 break;
 640         default:
 641                 WARN_ON(1);
 642                 break;
 643         }
 644 }
 645
 646 static int ath9k_init_priv(struct ath9k_htc_priv *priv,
 647                            u16 devid, char *product,
 648                            u32 drv_info)
 649 {
 650         struct ath_hw *ah = NULL;
 651         struct ath_common *common;
 652         int ret = 0, csz = 0;
 653
 654         priv->op_flags |= OP_INVALID;
 655
 656         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 657         if (!ah)
 658                 return -ENOMEM;
 659
 660         ah->hw_version.devid = devid;
 661         ah->hw_version.subsysid = 0; /* FIXME */
 662         ah->hw_version.usbdev = drv_info;
 663         ah->ah_flags |= AH_USE_EEPROM;
 664         priv->ah = ah;
 665
 666         common = ath9k_hw_common(ah);
 667         common->ops = &ath9k_common_ops;
 668         common->bus_ops = &ath9k_usb_bus_ops;
 669         common->ah = ah;
 670         common->hw = priv->hw;
 671         common->priv = priv;
 672         common->debug_mask = ath9k_debug;
 673
 674         spin_lock_init(&priv->wmi->wmi_lock);
 675         spin_lock_init(&priv->beacon_lock);
 676         spin_lock_init(&priv->tx_lock);
 677         mutex_init(&priv->mutex);
 678         mutex_init(&priv->htc_pm_lock);
 679         tasklet_init(&priv->swba_tasklet, ath9k_swba_tasklet,
 680                      (unsigned long)priv);
 681         tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
 682                      (unsigned long)priv);
 683         tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet,
 684                      (unsigned long)priv);
 685         INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
 686         INIT_WORK(&priv->ps_work, ath9k_ps_work);
 687         INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
 688
 689         /*
 690          * Cache line size is used to size and align various
 691          * structures used to communicate with the hardware.
 692          */
 693         ath_read_cachesize(common, &csz);
 694         common->cachelsz = csz << 2; /* convert to bytes */
 695
 696         ret = ath9k_hw_init(ah);
 697         if (ret) {
 698                 ath_err(common,
 699                         "Unable to initialize hardware; initialization status: %d\n",
 700                         ret);
 701                 goto err_hw;
 702         }
 703
 704         ret = ath9k_htc_init_debug(ah);
 705         if (ret) {
 706                 ath_err(common, "Unable to create debugfs files\n");
 707                 goto err_debug;
 708         }
 709
 710         ret = ath9k_init_queues(priv);
 711         if (ret)
 712                 goto err_queues;
 713
 714         ath9k_init_crypto(priv);
 715         ath9k_init_channels_rates(priv);
 716         ath9k_init_misc(priv);
 717
 718         if (product && strncmp(product, ATH_HTC_BTCOEX_PRODUCT_ID, 5) == 0) {
 719                 ah->btcoex_hw.scheme = ATH_BTCOEX_CFG_3WIRE;
 720                 ath9k_init_btcoex(priv);
 721         }
 722
 723         return 0;
 724
 725 err_queues:
 726         ath9k_htc_exit_debug(ah);
 727 err_debug:
 728         ath9k_hw_deinit(ah);
 729 err_hw:
 730
 731         kfree(ah);
 732         priv->ah = NULL;
 733
 734         return ret;
 735 }
 736
 737 static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
 738                                struct ieee80211_hw *hw)
 739 {
 740         struct ath_common *common = ath9k_hw_common(priv->ah);
 741
 742         hw->flags = IEEE80211_HW_SIGNAL_DBM |
 743                 IEEE80211_HW_AMPDU_AGGREGATION |
 744                 IEEE80211_HW_SPECTRUM_MGMT |
 745                 IEEE80211_HW_HAS_RATE_CONTROL |
 746                 IEEE80211_HW_RX_INCLUDES_FCS |
 747                 IEEE80211_HW_SUPPORTS_PS |
 748                 IEEE80211_HW_PS_NULLFUNC_STACK;
 749
 750         hw->wiphy->interface_modes =
 751                 BIT(NL80211_IFTYPE_STATION) |
 752                 BIT(NL80211_IFTYPE_ADHOC);
 753
 754         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 755
 756         hw->queues = 4;
 757         hw->channel_change_time = 5000;
 758         hw->max_listen_interval = 10;
 759         hw->vif_data_size = sizeof(struct ath9k_htc_vif);
 760         hw->sta_data_size = sizeof(struct ath9k_htc_sta);
 761
 762         /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
 763         hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
 764                 sizeof(struct htc_frame_hdr) + 4;
 765
 766         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 767                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 768                         &priv->sbands[IEEE80211_BAND_2GHZ];
 769         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 770                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 771                         &priv->sbands[IEEE80211_BAND_5GHZ];
 772
 773         if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
 774                 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 775                         setup_ht_cap(priv,
 776                                      &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
 777                 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 778                         setup_ht_cap(priv,
 779                                      &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap);
 780         }
 781
 782         SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
 783 }
 784
 785 static int ath9k_init_device(struct ath9k_htc_priv *priv,
 786                              u16 devid, char *product, u32 drv_info)
 787 {
 788         struct ieee80211_hw *hw = priv->hw;
 789         struct ath_common *common;
 790         struct ath_hw *ah;
 791         int error = 0;
 792         struct ath_regulatory *reg;
 793
 794         /* Bring up device */
 795         error = ath9k_init_priv(priv, devid, product, drv_info);
 796         if (error != 0)
 797                 goto err_init;
 798
 799         ah = priv->ah;
 800         common = ath9k_hw_common(ah);
 801         ath9k_set_hw_capab(priv, hw);
 802
 803         /* Initialize regulatory */
 804         error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
 805                               ath9k_reg_notifier);
 806         if (error)
 807                 goto err_regd;
 808
 809         reg = &common->regulatory;
 810
 811         /* Setup TX */
 812         error = ath9k_tx_init(priv);
 813         if (error != 0)
 814                 goto err_tx;
 815
 816         /* Setup RX */
 817         error = ath9k_rx_init(priv);
 818         if (error != 0)
 819                 goto err_rx;
 820
 821         /* Register with mac80211 */
 822         error = ieee80211_register_hw(hw);
 823         if (error)
 824                 goto err_register;
 825
 826         /* Handle world regulatory */
 827         if (!ath_is_world_regd(reg)) {
 828                 error = regulatory_hint(hw->wiphy, reg->alpha2);
 829                 if (error)
 830                         goto err_world;
 831         }
 832
 833         ath9k_init_leds(priv);
 834         ath9k_start_rfkill_poll(priv);
 835
 836         return 0;
 837
 838 err_world:
 839         ieee80211_unregister_hw(hw);
 840 err_register:
 841         ath9k_rx_cleanup(priv);
 842 err_rx:
 843         ath9k_tx_cleanup(priv);
 844 err_tx:
 845         /* Nothing */
 846 err_regd:
 847         ath9k_deinit_priv(priv);
 848 err_init:
 849         return error;
 850 }
 851
 852 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
 853                            u16 devid, char *product, u32 drv_info)
 854 {
 855         struct ieee80211_hw *hw;
 856         struct ath9k_htc_priv *priv;
 857         int ret;
 858
 859         hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
 860         if (!hw)
 861                 return -ENOMEM;
 862
 863         priv = hw->priv;
 864         priv->hw = hw;
 865         priv->htc = htc_handle;
 866         priv->dev = dev;
 867         htc_handle->drv_priv = priv;
 868         SET_IEEE80211_DEV(hw, priv->dev);
 869
 870         ret = ath9k_htc_wait_for_target(priv);
 871         if (ret)
 872                 goto err_free;
 873
 874         priv->wmi = ath9k_init_wmi(priv);
 875         if (!priv->wmi) {
 876                 ret = -EINVAL;
 877                 goto err_free;
 878         }
 879
 880         ret = ath9k_init_htc_services(priv, devid, drv_info);
 881         if (ret)
 882                 goto err_init;
 883
 884         ret = ath9k_init_device(priv, devid, product, drv_info);
 885         if (ret)
 886                 goto err_init;
 887
 888         return 0;
 889
 890 err_init:
 891         ath9k_deinit_wmi(priv);
 892 err_free:
 893         ieee80211_free_hw(hw);
 894         return ret;
 895 }
 896
 897 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
 898 {
 899         if (htc_handle->drv_priv) {
 900
 901                 /* Check if the device has been yanked out. */
 902                 if (hotunplug)
 903                         htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
 904
 905                 ath9k_deinit_device(htc_handle->drv_priv);
 906                 ath9k_deinit_wmi(htc_handle->drv_priv);
 907                 ieee80211_free_hw(htc_handle->drv_priv->hw);
 908         }
 909 }
 910
 911 #ifdef CONFIG_PM
 912
 913 void ath9k_htc_suspend(struct htc_target *htc_handle)
 914 {
 915         ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
 916 }
 917
 918 int ath9k_htc_resume(struct htc_target *htc_handle)
 919 {
 920         struct ath9k_htc_priv *priv = htc_handle->drv_priv;
 921         int ret;
 922
 923         ret = ath9k_htc_wait_for_target(priv);
 924         if (ret)
 925                 return ret;
 926
 927         ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
 928                                       priv->ah->hw_version.usbdev);
 929         return ret;
 930 }
 931 #endif
 932
 933 static int __init ath9k_htc_init(void)
 934 {
 935         int error;
 936
 937         error = ath9k_htc_debug_create_root();
 938         if (error < 0) {
 939                 printk(KERN_ERR
 940                         "ath9k_htc: Unable to create debugfs root: %d\n",
 941                         error);
 942                 goto err_dbg;
 943         }
 944
 945         error = ath9k_hif_usb_init();
 946         if (error < 0) {
 947                 printk(KERN_ERR
 948                         "ath9k_htc: No USB devices found,"
 949                         " driver not installed.\n");
 950                 error = -ENODEV;
 951                 goto err_usb;
 952         }
 953
 954         return 0;
 955
 956 err_usb:
 957         ath9k_htc_debug_remove_root();
 958 err_dbg:
 959         return error;
 960 }
 961 module_init(ath9k_htc_init);
 962
 963 static void __exit ath9k_htc_exit(void)
 964 {
 965         ath9k_hif_usb_exit();
 966         ath9k_htc_debug_remove_root();
 967         printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
 968 }
 969 module_exit(ath9k_htc_exit);