drivers/net/wireless/ath/ath9k/eeprom_def.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9002_phy.h"
  19
  20 static void ath9k_get_txgain_index(struct ath_hw *ah,
  21                 struct ath9k_channel *chan,
  22                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
  23                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
  24 {
  25         u8 pcdac, i = 0;
  26         u16 idxL = 0, idxR = 0, numPiers;
  27         bool match;
  28         struct chan_centers centers;
  29
  30         ath9k_hw_get_channel_centers(ah, chan, &centers);
  31
  32         for (numPiers = 0; numPiers < availPiers; numPiers++)
  33                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
  34                         break;
  35
  36         match = ath9k_hw_get_lower_upper_index(
  37                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
  38                         calChans, numPiers, &idxL, &idxR);
  39         if (match) {
  40                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
  41                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
  42         } else {
  43                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
  44                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
  45                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
  46         }
  47
  48         while (pcdac > ah->originalGain[i] &&
  49                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
  50                 i++;
  51
  52         *pcdacIdx = i;
  53 }
  54
  55 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
  56                                 u32 initTxGain,
  57                                 int txPower,
  58                                 u8 *pPDADCValues)
  59 {
  60         u32 i;
  61         u32 offset;
  62
  63         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
  64                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  65         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
  66                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
  67
  68         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
  69                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
  70
  71         offset = txPower;
  72         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
  73                 if (i < offset)
  74                         pPDADCValues[i] = 0x0;
  75                 else
  76                         pPDADCValues[i] = 0xFF;
  77 }
  78
  79 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
  80 {
  81         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
  82 }
  83
  84 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
  85 {
  86         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
  87 }
  88
  89 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
  90 {
  91 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
  92         struct ath_common *common = ath9k_hw_common(ah);
  93         u16 *eep_data = (u16 *)&ah->eeprom.def;
  94         int addr, ar5416_eep_start_loc = 0x100;
  95
  96         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
  97                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
  98                                          eep_data)) {
  99                         ath_err(ath9k_hw_common(ah),
 100                                 "Unable to read eeprom region\n");
 101                         return false;
 102                 }
 103                 eep_data++;
 104         }
 105         return true;
 106 #undef SIZE_EEPROM_DEF
 107 }
 108
 109 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 110 {
 111         struct ar5416_eeprom_def *eep =
 112                 (struct ar5416_eeprom_def *) &ah->eeprom.def;
 113         struct ath_common *common = ath9k_hw_common(ah);
 114         u16 *eepdata, temp, magic, magic2;
 115         u32 sum = 0, el;
 116         bool need_swap = false;
 117         int i, addr, size;
 118
 119         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
 120                 ath_err(common, "Reading Magic # failed\n");
 121                 return false;
 122         }
 123
 124         if (!ath9k_hw_use_flash(ah)) {
 125                 ath_dbg(common, ATH_DBG_EEPROM,
 126                         "Read Magic = 0x%04X\n", magic);
 127
 128                 if (magic != AR5416_EEPROM_MAGIC) {
 129                         magic2 = swab16(magic);
 130
 131                         if (magic2 == AR5416_EEPROM_MAGIC) {
 132                                 size = sizeof(struct ar5416_eeprom_def);
 133                                 need_swap = true;
 134                                 eepdata = (u16 *) (&ah->eeprom);
 135
 136                                 for (addr = 0; addr < size / sizeof(u16); addr++) {
 137                                         temp = swab16(*eepdata);
 138                                         *eepdata = temp;
 139                                         eepdata++;
 140                                 }
 141                         } else {
 142                                 ath_err(common,
 143                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
 144                                 return -EINVAL;
 145                         }
 146                 }
 147         }
 148
 149         ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 150                 need_swap ? "True" : "False");
 151
 152         if (need_swap)
 153                 el = swab16(ah->eeprom.def.baseEepHeader.length);
 154         else
 155                 el = ah->eeprom.def.baseEepHeader.length;
 156
 157         if (el > sizeof(struct ar5416_eeprom_def))
 158                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
 159         else
 160                 el = el / sizeof(u16);
 161
 162         eepdata = (u16 *)(&ah->eeprom);
 163
 164         for (i = 0; i < el; i++)
 165                 sum ^= *eepdata++;
 166
 167         if (need_swap) {
 168                 u32 integer, j;
 169                 u16 word;
 170
 171                 ath_dbg(common, ATH_DBG_EEPROM,
 172                         "EEPROM Endianness is not native.. Changing.\n");
 173
 174                 word = swab16(eep->baseEepHeader.length);
 175                 eep->baseEepHeader.length = word;
 176
 177                 word = swab16(eep->baseEepHeader.checksum);
 178                 eep->baseEepHeader.checksum = word;
 179
 180                 word = swab16(eep->baseEepHeader.version);
 181                 eep->baseEepHeader.version = word;
 182
 183                 word = swab16(eep->baseEepHeader.regDmn[0]);
 184                 eep->baseEepHeader.regDmn[0] = word;
 185
 186                 word = swab16(eep->baseEepHeader.regDmn[1]);
 187                 eep->baseEepHeader.regDmn[1] = word;
 188
 189                 word = swab16(eep->baseEepHeader.rfSilent);
 190                 eep->baseEepHeader.rfSilent = word;
 191
 192                 word = swab16(eep->baseEepHeader.blueToothOptions);
 193                 eep->baseEepHeader.blueToothOptions = word;
 194
 195                 word = swab16(eep->baseEepHeader.deviceCap);
 196                 eep->baseEepHeader.deviceCap = word;
 197
 198                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
 199                         struct modal_eep_header *pModal =
 200                                 &eep->modalHeader[j];
 201                         integer = swab32(pModal->antCtrlCommon);
 202                         pModal->antCtrlCommon = integer;
 203
 204                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 205                                 integer = swab32(pModal->antCtrlChain[i]);
 206                                 pModal->antCtrlChain[i] = integer;
 207                         }
 208
 209                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 210                                 word = swab16(pModal->spurChans[i].spurChan);
 211                                 pModal->spurChans[i].spurChan = word;
 212                         }
 213                 }
 214         }
 215
 216         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 217             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 218                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 219                         sum, ah->eep_ops->get_eeprom_ver(ah));
 220                 return -EINVAL;
 221         }
 222
 223         /* Enable fixup for AR_AN_TOP2 if necessary */
 224         if (AR_SREV_9280_20_OR_LATER(ah) &&
 225             (eep->baseEepHeader.version & 0xff) > 0x0a &&
 226             eep->baseEepHeader.pwdclkind == 0)
 227                 ah->need_an_top2_fixup = 1;
 228
 229         return 0;
 230 }
 231
 232 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
 233                                    enum eeprom_param param)
 234 {
 235         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 236         struct modal_eep_header *pModal = eep->modalHeader;
 237         struct base_eep_header *pBase = &eep->baseEepHeader;
 238
 239         switch (param) {
 240         case EEP_NFTHRESH_5:
 241                 return pModal[0].noiseFloorThreshCh[0];
 242         case EEP_NFTHRESH_2:
 243                 return pModal[1].noiseFloorThreshCh[0];
 244         case EEP_MAC_LSW:
 245                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 246         case EEP_MAC_MID:
 247                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 248         case EEP_MAC_MSW:
 249                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 250         case EEP_REG_0:
 251                 return pBase->regDmn[0];
 252         case EEP_REG_1:
 253                 return pBase->regDmn[1];
 254         case EEP_OP_CAP:
 255                 return pBase->deviceCap;
 256         case EEP_OP_MODE:
 257                 return pBase->opCapFlags;
 258         case EEP_RF_SILENT:
 259                 return pBase->rfSilent;
 260         case EEP_OB_5:
 261                 return pModal[0].ob;
 262         case EEP_DB_5:
 263                 return pModal[0].db;
 264         case EEP_OB_2:
 265                 return pModal[1].ob;
 266         case EEP_DB_2:
 267                 return pModal[1].db;
 268         case EEP_MINOR_REV:
 269                 return AR5416_VER_MASK;
 270         case EEP_TX_MASK:
 271                 return pBase->txMask;
 272         case EEP_RX_MASK:
 273                 return pBase->rxMask;
 274         case EEP_FSTCLK_5G:
 275                 return pBase->fastClk5g;
 276         case EEP_RXGAIN_TYPE:
 277                 return pBase->rxGainType;
 278         case EEP_TXGAIN_TYPE:
 279                 return pBase->txGainType;
 280         case EEP_OL_PWRCTRL:
 281                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 282                         return pBase->openLoopPwrCntl ? true : false;
 283                 else
 284                         return false;
 285         case EEP_RC_CHAIN_MASK:
 286                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 287                         return pBase->rcChainMask;
 288                 else
 289                         return 0;
 290         case EEP_DAC_HPWR_5G:
 291                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
 292                         return pBase->dacHiPwrMode_5G;
 293                 else
 294                         return 0;
 295         case EEP_FRAC_N_5G:
 296                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
 297                         return pBase->frac_n_5g;
 298                 else
 299                         return 0;
 300         case EEP_PWR_TABLE_OFFSET:
 301                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
 302                         return pBase->pwr_table_offset;
 303                 else
 304                         return AR5416_PWR_TABLE_OFFSET_DB;
 305         default:
 306                 return 0;
 307         }
 308 }
 309
 310 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
 311                                   struct modal_eep_header *pModal,
 312                                   struct ar5416_eeprom_def *eep,
 313                                   u8 txRxAttenLocal, int regChainOffset, int i)
 314 {
 315         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 316                 txRxAttenLocal = pModal->txRxAttenCh[i];
 317
 318                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 319                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 320                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 321                               pModal->bswMargin[i]);
 322                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 323                               AR_PHY_GAIN_2GHZ_XATTEN1_DB,
 324                               pModal->bswAtten[i]);
 325                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 326                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 327                               pModal->xatten2Margin[i]);
 328                         REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 329                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 330                               pModal->xatten2Db[i]);
 331                 } else {
 332                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 333                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 334                            ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
 335                           | SM(pModal-> bswMargin[i],
 336                                AR_PHY_GAIN_2GHZ_BSW_MARGIN));
 337                         REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
 338                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 339                            ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
 340                           | SM(pModal->bswAtten[i],
 341                                AR_PHY_GAIN_2GHZ_BSW_ATTEN));
 342                 }
 343         }
 344
 345         if (AR_SREV_9280_20_OR_LATER(ah)) {
 346                 REG_RMW_FIELD(ah,
 347                       AR_PHY_RXGAIN + regChainOffset,
 348                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 349                 REG_RMW_FIELD(ah,
 350                       AR_PHY_RXGAIN + regChainOffset,
 351                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
 352         } else {
 353                 REG_WRITE(ah,
 354                           AR_PHY_RXGAIN + regChainOffset,
 355                           (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
 356                            ~AR_PHY_RXGAIN_TXRX_ATTEN)
 357                           | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
 358                 REG_WRITE(ah,
 359                           AR_PHY_GAIN_2GHZ + regChainOffset,
 360                           (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
 361                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
 362                           SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
 363         }
 364 }
 365
 366 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
 367                                           struct ath9k_channel *chan)
 368 {
 369         struct modal_eep_header *pModal;
 370         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 371         int i, regChainOffset;
 372         u8 txRxAttenLocal;
 373
 374         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 375         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 376
 377         REG_WRITE(ah, AR_PHY_SWITCH_COM,
 378                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
 379
 380         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 381                 if (AR_SREV_9280(ah)) {
 382                         if (i >= 2)
 383                                 break;
 384                 }
 385
 386                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 387                     (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
 388                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 389                 else
 390                         regChainOffset = i * 0x1000;
 391
 392                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
 393                           pModal->antCtrlChain[i]);
 394
 395                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
 396                           (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
 397                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 398                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 399                           SM(pModal->iqCalICh[i],
 400                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 401                           SM(pModal->iqCalQCh[i],
 402                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 403
 404                 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
 405                         ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
 406                                               regChainOffset, i);
 407         }
 408
 409         if (AR_SREV_9280_20_OR_LATER(ah)) {
 410                 if (IS_CHAN_2GHZ(chan)) {
 411                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 412                                                   AR_AN_RF2G1_CH0_OB,
 413                                                   AR_AN_RF2G1_CH0_OB_S,
 414                                                   pModal->ob);
 415                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
 416                                                   AR_AN_RF2G1_CH0_DB,
 417                                                   AR_AN_RF2G1_CH0_DB_S,
 418                                                   pModal->db);
 419                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 420                                                   AR_AN_RF2G1_CH1_OB,
 421                                                   AR_AN_RF2G1_CH1_OB_S,
 422                                                   pModal->ob_ch1);
 423                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
 424                                                   AR_AN_RF2G1_CH1_DB,
 425                                                   AR_AN_RF2G1_CH1_DB_S,
 426                                                   pModal->db_ch1);
 427                 } else {
 428                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 429                                                   AR_AN_RF5G1_CH0_OB5,
 430                                                   AR_AN_RF5G1_CH0_OB5_S,
 431                                                   pModal->ob);
 432                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
 433                                                   AR_AN_RF5G1_CH0_DB5,
 434                                                   AR_AN_RF5G1_CH0_DB5_S,
 435                                                   pModal->db);
 436                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 437                                                   AR_AN_RF5G1_CH1_OB5,
 438                                                   AR_AN_RF5G1_CH1_OB5_S,
 439                                                   pModal->ob_ch1);
 440                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
 441                                                   AR_AN_RF5G1_CH1_DB5,
 442                                                   AR_AN_RF5G1_CH1_DB5_S,
 443                                                   pModal->db_ch1);
 444                 }
 445                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 446                                           AR_AN_TOP2_XPABIAS_LVL,
 447                                           AR_AN_TOP2_XPABIAS_LVL_S,
 448                                           pModal->xpaBiasLvl);
 449                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
 450                                           AR_AN_TOP2_LOCALBIAS,
 451                                           AR_AN_TOP2_LOCALBIAS_S,
 452                                           !!(pModal->lna_ctl &
 453                                              LNA_CTL_LOCAL_BIAS));
 454                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
 455                               !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
 456         }
 457
 458         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 459                       pModal->switchSettling);
 460         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 461                       pModal->adcDesiredSize);
 462
 463         if (!AR_SREV_9280_20_OR_LATER(ah))
 464                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 465                               AR_PHY_DESIRED_SZ_PGA,
 466                               pModal->pgaDesiredSize);
 467
 468         REG_WRITE(ah, AR_PHY_RF_CTL4,
 469                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
 470                   | SM(pModal->txEndToXpaOff,
 471                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
 472                   | SM(pModal->txFrameToXpaOn,
 473                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
 474                   | SM(pModal->txFrameToXpaOn,
 475                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 476
 477         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 478                       pModal->txEndToRxOn);
 479
 480         if (AR_SREV_9280_20_OR_LATER(ah)) {
 481                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 482                               pModal->thresh62);
 483                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
 484                               AR_PHY_EXT_CCA0_THRESH62,
 485                               pModal->thresh62);
 486         } else {
 487                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
 488                               pModal->thresh62);
 489                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
 490                               AR_PHY_EXT_CCA_THRESH62,
 491                               pModal->thresh62);
 492         }
 493
 494         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
 495                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
 496                               AR_PHY_TX_END_DATA_START,
 497                               pModal->txFrameToDataStart);
 498                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 499                               pModal->txFrameToPaOn);
 500         }
 501
 502         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
 503                 if (IS_CHAN_HT40(chan))
 504                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 505                                       AR_PHY_SETTLING_SWITCH,
 506                                       pModal->swSettleHt40);
 507         }
 508
 509         if (AR_SREV_9280_20_OR_LATER(ah) &&
 510             AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
 511                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
 512                               AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
 513                               pModal->miscBits);
 514
 515
 516         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
 517                 if (IS_CHAN_2GHZ(chan))
 518                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 519                                         eep->baseEepHeader.dacLpMode);
 520                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
 521                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
 522                 else
 523                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
 524                                       eep->baseEepHeader.dacLpMode);
 525
 526                 udelay(100);
 527
 528                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
 529                               pModal->miscBits >> 2);
 530
 531                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
 532                               AR_PHY_TX_DESIRED_SCALE_CCK,
 533                               eep->baseEepHeader.desiredScaleCCK);
 534         }
 535 }
 536
 537 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 538                                    struct ath9k_channel *chan)
 539 {
 540 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
 541         struct modal_eep_header *pModal;
 542         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
 543         u8 biaslevel;
 544
 545         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 546                 return;
 547
 548         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 549                 return;
 550
 551         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
 552
 553         if (pModal->xpaBiasLvl != 0xff) {
 554                 biaslevel = pModal->xpaBiasLvl;
 555         } else {
 556                 u16 resetFreqBin, freqBin, freqCount = 0;
 557                 struct chan_centers centers;
 558
 559                 ath9k_hw_get_channel_centers(ah, chan, &centers);
 560
 561                 resetFreqBin = FREQ2FBIN(centers.synth_center,
 562                                          IS_CHAN_2GHZ(chan));
 563                 freqBin = XPA_LVL_FREQ(0) & 0xff;
 564                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
 565
 566                 freqCount++;
 567
 568                 while (freqCount < 3) {
 569                         if (XPA_LVL_FREQ(freqCount) == 0x0)
 570                                 break;
 571
 572                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
 573                         if (resetFreqBin >= freqBin)
 574                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
 575                         else
 576                                 break;
 577                         freqCount++;
 578                 }
 579         }
 580
 581         if (IS_CHAN_2GHZ(chan)) {
 582                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
 583                                         7, 1) & (~0x18)) | biaslevel << 3;
 584         } else {
 585                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
 586                                         6, 1) & (~0xc0)) | biaslevel << 6;
 587         }
 588 #undef XPA_LVL_FREQ
 589 }
 590
 591 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
 592                                 struct ath9k_channel *chan,
 593                                 struct cal_data_per_freq *pRawDataSet,
 594                                 u8 *bChans, u16 availPiers,
 595                                 u16 tPdGainOverlap,
 596                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 597                                 u16 numXpdGains)
 598 {
 599         int i, j, k;
 600         int16_t ss;
 601         u16 idxL = 0, idxR = 0, numPiers;
 602         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
 603                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 604         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
 605                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 606         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
 607                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 608
 609         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
 610         u8 minPwrT4[AR5416_NUM_PD_GAINS];
 611         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
 612         int16_t vpdStep;
 613         int16_t tmpVal;
 614         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 615         bool match;
 616         int16_t minDelta = 0;
 617         struct chan_centers centers;
 618
 619         memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
 620         ath9k_hw_get_channel_centers(ah, chan, &centers);
 621
 622         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 623                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
 624                         break;
 625         }
 626
 627         match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
 628                                                              IS_CHAN_2GHZ(chan)),
 629                                                bChans, numPiers, &idxL, &idxR);
 630
 631         if (match) {
 632                 for (i = 0; i < numXpdGains; i++) {
 633                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
 634                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
 635                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 636                                         pRawDataSet[idxL].pwrPdg[i],
 637                                         pRawDataSet[idxL].vpdPdg[i],
 638                                         AR5416_PD_GAIN_ICEPTS,
 639                                         vpdTableI[i]);
 640                 }
 641         } else {
 642                 for (i = 0; i < numXpdGains; i++) {
 643                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
 644                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
 645                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
 646                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
 647
 648                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
 649
 650                         maxPwrT4[i] =
 651                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
 652                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
 653
 654
 655                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 656                                                 pPwrL, pVpdL,
 657                                                 AR5416_PD_GAIN_ICEPTS,
 658                                                 vpdTableL[i]);
 659                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 660                                                 pPwrR, pVpdR,
 661                                                 AR5416_PD_GAIN_ICEPTS,
 662                                                 vpdTableR[i]);
 663
 664                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 665                                 vpdTableI[i][j] =
 666                                         (u8)(ath9k_hw_interpolate((u16)
 667                                              FREQ2FBIN(centers.
 668                                                        synth_center,
 669                                                        IS_CHAN_2GHZ
 670                                                        (chan)),
 671                                              bChans[idxL], bChans[idxR],
 672                                              vpdTableL[i][j], vpdTableR[i][j]));
 673                         }
 674                 }
 675         }
 676
 677         k = 0;
 678
 679         for (i = 0; i < numXpdGains; i++) {
 680                 if (i == (numXpdGains - 1))
 681                         pPdGainBoundaries[i] =
 682                                 (u16)(maxPwrT4[i] / 2);
 683                 else
 684                         pPdGainBoundaries[i] =
 685                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
 686
 687                 pPdGainBoundaries[i] =
 688                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
 689
 690                 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
 691                         minDelta = pPdGainBoundaries[0] - 23;
 692                         pPdGainBoundaries[0] = 23;
 693                 } else {
 694                         minDelta = 0;
 695                 }
 696
 697                 if (i == 0) {
 698                         if (AR_SREV_9280_20_OR_LATER(ah))
 699                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
 700                         else
 701                                 ss = 0;
 702                 } else {
 703                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
 704                                         (minPwrT4[i] / 2)) -
 705                                        tPdGainOverlap + 1 + minDelta);
 706                 }
 707                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
 708                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 709
 710                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 711                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
 712                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
 713                         ss++;
 714                 }
 715
 716                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
 717                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
 718                                 (minPwrT4[i] / 2));
 719                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
 720                         tgtIndex : sizeCurrVpdTable;
 721
 722                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 723                         pPDADCValues[k++] = vpdTableI[i][ss++];
 724                 }
 725
 726                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
 727                                     vpdTableI[i][sizeCurrVpdTable - 2]);
 728                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 729
 730                 if (tgtIndex >= maxIndex) {
 731                         while ((ss <= tgtIndex) &&
 732                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 733                                 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
 734                                                     (ss - maxIndex + 1) * vpdStep));
 735                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
 736                                                          255 : tmpVal);
 737                                 ss++;
 738                         }
 739                 }
 740         }
 741
 742         while (i < AR5416_PD_GAINS_IN_MASK) {
 743                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
 744                 i++;
 745         }
 746
 747         while (k < AR5416_NUM_PDADC_VALUES) {
 748                 pPDADCValues[k] = pPDADCValues[k - 1];
 749                 k++;
 750         }
 751 }
 752
 753 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
 754                                 u16 *gb,
 755                                 u16 numXpdGain,
 756                                 u16 pdGainOverlap_t2,
 757                                 int8_t pwr_table_offset,
 758                                 int16_t *diff)
 759
 760 {
 761         u16 k;
 762
 763         /* Prior to writing the boundaries or the pdadc vs. power table
 764          * into the chip registers the default starting point on the pdadc
 765          * vs. power table needs to be checked and the curve boundaries
 766          * adjusted accordingly
 767          */
 768         if (AR_SREV_9280_20_OR_LATER(ah)) {
 769                 u16 gb_limit;
 770
 771                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 772                         /* get the difference in dB */
 773                         *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
 774                         /* get the number of half dB steps */
 775                         *diff *= 2;
 776                         /* change the original gain boundary settings
 777                          * by the number of half dB steps
 778                          */
 779                         for (k = 0; k < numXpdGain; k++)
 780                                 gb[k] = (u16)(gb[k] - *diff);
 781                 }
 782                 /* Because of a hardware limitation, ensure the gain boundary
 783                  * is not larger than (63 - overlap)
 784                  */
 785                 gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
 786
 787                 for (k = 0; k < numXpdGain; k++)
 788                         gb[k] = (u16)min(gb_limit, gb[k]);
 789         }
 790
 791         return *diff;
 792 }
 793
 794 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
 795                                       int8_t pwr_table_offset,
 796                                       int16_t diff,
 797                                       u8 *pdadcValues)
 798 {
 799 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
 800         u16 k;
 801
 802         /* If this is a board that has a pwrTableOffset that differs from
 803          * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
 804          * pdadc vs pwr table needs to be adjusted prior to writing to the
 805          * chip.
 806          */
 807         if (AR_SREV_9280_20_OR_LATER(ah)) {
 808                 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
 809                         /* shift the table to start at the new offset */
 810                         for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
 811                                 pdadcValues[k] = pdadcValues[k + diff];
 812                         }
 813
 814                         /* fill the back of the table */
 815                         for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
 816                                 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
 817                         }
 818                 }
 819         }
 820 #undef NUM_PDADC
 821 }
 822
 823 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
 824                                   struct ath9k_channel *chan,
 825                                   int16_t *pTxPowerIndexOffset)
 826 {
 827 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
 828 #define SM_PDGAIN_B(x, y) \
 829                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
 830         struct ath_common *common = ath9k_hw_common(ah);
 831         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
 832         struct cal_data_per_freq *pRawDataset;
 833         u8 *pCalBChans = NULL;
 834         u16 pdGainOverlap_t2;
 835         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 836         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 837         u16 numPiers, i, j;
 838         int16_t diff = 0;
 839         u16 numXpdGain, xpdMask;
 840         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
 841         u32 reg32, regOffset, regChainOffset;
 842         int16_t modalIdx;
 843         int8_t pwr_table_offset;
 844
 845         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
 846         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
 847
 848         pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
 849
 850         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 851             AR5416_EEP_MINOR_VER_2) {
 852                 pdGainOverlap_t2 =
 853                         pEepData->modalHeader[modalIdx].pdGainOverlap;
 854         } else {
 855                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 856                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 857         }
 858
 859         if (IS_CHAN_2GHZ(chan)) {
 860                 pCalBChans = pEepData->calFreqPier2G;
 861                 numPiers = AR5416_NUM_2G_CAL_PIERS;
 862         } else {
 863                 pCalBChans = pEepData->calFreqPier5G;
 864                 numPiers = AR5416_NUM_5G_CAL_PIERS;
 865         }
 866
 867         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
 868                 pRawDataset = pEepData->calPierData2G[0];
 869                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
 870                                  pRawDataset)->vpdPdg[0][0];
 871         }
 872
 873         numXpdGain = 0;
 874
 875         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 876                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 877                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
 878                                 break;
 879                         xpdGainValues[numXpdGain] =
 880                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 881                         numXpdGain++;
 882                 }
 883         }
 884
 885         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 886                       (numXpdGain - 1) & 0x3);
 887         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 888                       xpdGainValues[0]);
 889         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 890                       xpdGainValues[1]);
 891         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
 892                       xpdGainValues[2]);
 893
 894         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 895                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 896                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 897                     (i != 0)) {
 898                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 899                 } else
 900                         regChainOffset = i * 0x1000;
 901
 902                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 903                         if (IS_CHAN_2GHZ(chan))
 904                                 pRawDataset = pEepData->calPierData2G[i];
 905                         else
 906                                 pRawDataset = pEepData->calPierData5G[i];
 907
 908
 909                         if (OLC_FOR_AR9280_20_LATER) {
 910                                 u8 pcdacIdx;
 911                                 u8 txPower;
 912
 913                                 ath9k_get_txgain_index(ah, chan,
 914                                 (struct calDataPerFreqOpLoop *)pRawDataset,
 915                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
 916                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
 917                                                      txPower/2, pdadcValues);
 918                         } else {
 919                                 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
 920                                                         chan, pRawDataset,
 921                                                         pCalBChans, numPiers,
 922                                                         pdGainOverlap_t2,
 923                                                         gainBoundaries,
 924                                                         pdadcValues,
 925                                                         numXpdGain);
 926                         }
 927
 928                         diff = ath9k_change_gain_boundary_setting(ah,
 929                                                            gainBoundaries,
 930                                                            numXpdGain,
 931                                                            pdGainOverlap_t2,
 932                                                            pwr_table_offset,
 933                                                            &diff);
 934
 935                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 936                                 if (OLC_FOR_AR9280_20_LATER) {
 937                                         REG_WRITE(ah,
 938                                                 AR_PHY_TPCRG5 + regChainOffset,
 939                                                 SM(0x6,
 940                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
 941                                                 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
 942                                                 SM_PD_GAIN(3) | SM_PD_GAIN(4));
 943                                 } else {
 944                                         REG_WRITE(ah,
 945                                                 AR_PHY_TPCRG5 + regChainOffset,
 946                                                 SM(pdGainOverlap_t2,
 947                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
 948                                                 SM_PDGAIN_B(0, 1) |
 949                                                 SM_PDGAIN_B(1, 2) |
 950                                                 SM_PDGAIN_B(2, 3) |
 951                                                 SM_PDGAIN_B(3, 4));
 952                                 }
 953                         }
 954
 955
 956                         ath9k_adjust_pdadc_values(ah, pwr_table_offset,
 957                                                   diff, pdadcValues);
 958
 959                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 960                         for (j = 0; j < 32; j++) {
 961                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 962                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 963                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 964                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 965                                 REG_WRITE(ah, regOffset, reg32);
 966
 967                                 ath_dbg(common, ATH_DBG_EEPROM,
 968                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 969                                         i, regChainOffset, regOffset,
 970                                         reg32);
 971                                 ath_dbg(common, ATH_DBG_EEPROM,
 972                                         "PDADC: Chain %d | PDADC %3d "
 973                                         "Value %3d | PDADC %3d Value %3d | "
 974                                         "PDADC %3d Value %3d | PDADC %3d "
 975                                         "Value %3d |\n",
 976                                         i, 4 * j, pdadcValues[4 * j],
 977                                         4 * j + 1, pdadcValues[4 * j + 1],
 978                                         4 * j + 2, pdadcValues[4 * j + 2],
 979                                         4 * j + 3, pdadcValues[4 * j + 3]);
 980
 981                                 regOffset += 4;
 982                         }
 983                 }
 984         }
 985
 986         *pTxPowerIndexOffset = 0;
 987 #undef SM_PD_GAIN
 988 #undef SM_PDGAIN_B
 989 }
 990
 991 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 992                                                   struct ath9k_channel *chan,
 993                                                   int16_t *ratesArray,
 994                                                   u16 cfgCtl,
 995                                                   u16 AntennaReduction,
 996                                                   u16 twiceMaxRegulatoryPower,
 997                                                   u16 powerLimit)
 998 {
 999 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
1000 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9 /* 10*log10(3)*2 */
1001
1002         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1003         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1004         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1005         static const u16 tpScaleReductionTable[5] =
1006                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
1007
1008         int i;
1009         int16_t twiceLargestAntenna;
1010         struct cal_ctl_data *rep;
1011         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
1012                 0, { 0, 0, 0, 0}
1013         };
1014         struct cal_target_power_leg targetPowerOfdmExt = {
1015                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
1016                 0, { 0, 0, 0, 0 }
1017         };
1018         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
1019                 0, {0, 0, 0, 0}
1020         };
1021         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
1022         static const u16 ctlModesFor11a[] = {
1023                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
1024         };
1025         static const u16 ctlModesFor11g[] = {
1026                 CTL_11B, CTL_11G, CTL_2GHT20,
1027                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
1028         };
1029         u16 numCtlModes;
1030         const u16 *pCtlMode;
1031         u16 ctlMode, freq;
1032         struct chan_centers centers;
1033         int tx_chainmask;
1034         u16 twiceMinEdgePower;
1035
1036         tx_chainmask = ah->txchainmask;
1037
1038         ath9k_hw_get_channel_centers(ah, chan, &centers);
1039
1040         twiceLargestAntenna = max(
1041                 pEepData->modalHeader
1042                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
1043                 pEepData->modalHeader
1044                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
1045
1046         twiceLargestAntenna = max((u8)twiceLargestAntenna,
1047                                   pEepData->modalHeader
1048                                   [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
1049
1050         twiceLargestAntenna = (int16_t)min(AntennaReduction -
1051                                            twiceLargestAntenna, 0);
1052
1053         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
1054
1055         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
1056                 maxRegAllowedPower -=
1057                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
1058         }
1059
1060         scaledPower = min(powerLimit, maxRegAllowedPower);
1061
1062         switch (ar5416_get_ntxchains(tx_chainmask)) {
1063         case 1:
1064                 break;
1065         case 2:
1066                 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
1067                         scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
1068                 else
1069                         scaledPower = 0;
1070                 break;
1071         case 3:
1072                 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
1073                         scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
1074                 else
1075                         scaledPower = 0;
1076                 break;
1077         }
1078
1079         if (IS_CHAN_2GHZ(chan)) {
1080                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
1081                         SUB_NUM_CTL_MODES_AT_2G_40;
1082                 pCtlMode = ctlModesFor11g;
1083
1084                 ath9k_hw_get_legacy_target_powers(ah, chan,
1085                         pEepData->calTargetPowerCck,
1086                         AR5416_NUM_2G_CCK_TARGET_POWERS,
1087                         &targetPowerCck, 4, false);
1088                 ath9k_hw_get_legacy_target_powers(ah, chan,
1089                         pEepData->calTargetPower2G,
1090                         AR5416_NUM_2G_20_TARGET_POWERS,
1091                         &targetPowerOfdm, 4, false);
1092                 ath9k_hw_get_target_powers(ah, chan,
1093                         pEepData->calTargetPower2GHT20,
1094                         AR5416_NUM_2G_20_TARGET_POWERS,
1095                         &targetPowerHt20, 8, false);
1096
1097                 if (IS_CHAN_HT40(chan)) {
1098                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
1099                         ath9k_hw_get_target_powers(ah, chan,
1100                                 pEepData->calTargetPower2GHT40,
1101                                 AR5416_NUM_2G_40_TARGET_POWERS,
1102                                 &targetPowerHt40, 8, true);
1103                         ath9k_hw_get_legacy_target_powers(ah, chan,
1104                                 pEepData->calTargetPowerCck,
1105                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
1106                                 &targetPowerCckExt, 4, true);
1107                         ath9k_hw_get_legacy_target_powers(ah, chan,
1108                                 pEepData->calTargetPower2G,
1109                                 AR5416_NUM_2G_20_TARGET_POWERS,
1110                                 &targetPowerOfdmExt, 4, true);
1111                 }
1112         } else {
1113                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
1114                         SUB_NUM_CTL_MODES_AT_5G_40;
1115                 pCtlMode = ctlModesFor11a;
1116
1117                 ath9k_hw_get_legacy_target_powers(ah, chan,
1118                         pEepData->calTargetPower5G,
1119                         AR5416_NUM_5G_20_TARGET_POWERS,
1120                         &targetPowerOfdm, 4, false);
1121                 ath9k_hw_get_target_powers(ah, chan,
1122                         pEepData->calTargetPower5GHT20,
1123                         AR5416_NUM_5G_20_TARGET_POWERS,
1124                         &targetPowerHt20, 8, false);
1125
1126                 if (IS_CHAN_HT40(chan)) {
1127                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
1128                         ath9k_hw_get_target_powers(ah, chan,
1129                                 pEepData->calTargetPower5GHT40,
1130                                 AR5416_NUM_5G_40_TARGET_POWERS,
1131                                 &targetPowerHt40, 8, true);
1132                         ath9k_hw_get_legacy_target_powers(ah, chan,
1133                                 pEepData->calTargetPower5G,
1134                                 AR5416_NUM_5G_20_TARGET_POWERS,
1135                                 &targetPowerOfdmExt, 4, true);
1136                 }
1137         }
1138
1139         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1140                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1141                         (pCtlMode[ctlMode] == CTL_2GHT40);
1142                 if (isHt40CtlMode)
1143                         freq = centers.synth_center;
1144                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1145                         freq = centers.ext_center;
1146                 else
1147                         freq = centers.ctl_center;
1148
1149                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1150                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
1151                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
1152
1153                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1154                         if ((((cfgCtl & ~CTL_MODE_M) |
1155                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1156                              pEepData->ctlIndex[i]) ||
1157                             (((cfgCtl & ~CTL_MODE_M) |
1158                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1159                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1160                                 rep = &(pEepData->ctlData[i]);
1161
1162                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1163                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1164                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1165
1166                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1167                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
1168                                                                 twiceMinEdgePower);
1169                                 } else {
1170                                         twiceMaxEdgePower = twiceMinEdgePower;
1171                                         break;
1172                                 }
1173                         }
1174                 }
1175
1176                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1177
1178                 switch (pCtlMode[ctlMode]) {
1179                 case CTL_11B:
1180                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1181                                 targetPowerCck.tPow2x[i] =
1182                                         min((u16)targetPowerCck.tPow2x[i],
1183                                             minCtlPower);
1184                         }
1185                         break;
1186                 case CTL_11A:
1187                 case CTL_11G:
1188                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1189                                 targetPowerOfdm.tPow2x[i] =
1190                                         min((u16)targetPowerOfdm.tPow2x[i],
1191                                             minCtlPower);
1192                         }
1193                         break;
1194                 case CTL_5GHT20:
1195                 case CTL_2GHT20:
1196                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1197                                 targetPowerHt20.tPow2x[i] =
1198                                         min((u16)targetPowerHt20.tPow2x[i],
1199                                             minCtlPower);
1200                         }
1201                         break;
1202                 case CTL_11B_EXT:
1203                         targetPowerCckExt.tPow2x[0] = min((u16)
1204                                         targetPowerCckExt.tPow2x[0],
1205                                         minCtlPower);
1206                         break;
1207                 case CTL_11A_EXT:
1208                 case CTL_11G_EXT:
1209                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1210                                         targetPowerOfdmExt.tPow2x[0],
1211                                         minCtlPower);
1212                         break;
1213                 case CTL_5GHT40:
1214                 case CTL_2GHT40:
1215                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1216                                 targetPowerHt40.tPow2x[i] =
1217                                         min((u16)targetPowerHt40.tPow2x[i],
1218                                             minCtlPower);
1219                         }
1220                         break;
1221                 default:
1222                         break;
1223                 }
1224         }
1225
1226         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1227                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1228                 targetPowerOfdm.tPow2x[0];
1229         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1230         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1231         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1232         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1233
1234         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1235                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1236
1237         if (IS_CHAN_2GHZ(chan)) {
1238                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1239                 ratesArray[rate2s] = ratesArray[rate2l] =
1240                         targetPowerCck.tPow2x[1];
1241                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1242                         targetPowerCck.tPow2x[2];
1243                 ratesArray[rate11s] = ratesArray[rate11l] =
1244                         targetPowerCck.tPow2x[3];
1245         }
1246         if (IS_CHAN_HT40(chan)) {
1247                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1248                         ratesArray[rateHt40_0 + i] =
1249                                 targetPowerHt40.tPow2x[i];
1250                 }
1251                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1252                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1253                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1254                 if (IS_CHAN_2GHZ(chan)) {
1255                         ratesArray[rateExtCck] =
1256                                 targetPowerCckExt.tPow2x[0];
1257                 }
1258         }
1259 }
1260
1261 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1262                                     struct ath9k_channel *chan,
1263                                     u16 cfgCtl,
1264                                     u8 twiceAntennaReduction,
1265                                     u8 twiceMaxRegulatoryPower,
1266                                     u8 powerLimit, bool test)
1267 {
1268 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1269         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1270         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1271         struct modal_eep_header *pModal =
1272                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1273         int16_t ratesArray[Ar5416RateSize];
1274         int16_t txPowerIndexOffset = 0;
1275         u8 ht40PowerIncForPdadc = 2;
1276         int i, cck_ofdm_delta = 0;
1277
1278         memset(ratesArray, 0, sizeof(ratesArray));
1279
1280         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1281             AR5416_EEP_MINOR_VER_2) {
1282                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1283         }
1284
1285         ath9k_hw_set_def_power_per_rate_table(ah, chan,
1286                                                &ratesArray[0], cfgCtl,
1287                                                twiceAntennaReduction,
1288                                                twiceMaxRegulatoryPower,
1289                                                powerLimit);
1290
1291         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
1292
1293         regulatory->max_power_level = 0;
1294         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1295                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1296                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1297                         ratesArray[i] = AR5416_MAX_RATE_POWER;
1298                 if (ratesArray[i] > regulatory->max_power_level)
1299                         regulatory->max_power_level = ratesArray[i];
1300         }
1301
1302         if (!test) {
1303                 i = rate6mb;
1304
1305                 if (IS_CHAN_HT40(chan))
1306                         i = rateHt40_0;
1307                 else if (IS_CHAN_HT20(chan))
1308                         i = rateHt20_0;
1309
1310                 regulatory->max_power_level = ratesArray[i];
1311         }
1312
1313         switch(ar5416_get_ntxchains(ah->txchainmask)) {
1314         case 1:
1315                 break;
1316         case 2:
1317                 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1318                 break;
1319         case 3:
1320                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1321                 break;
1322         default:
1323                 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1324                         "Invalid chainmask configuration\n");
1325                 break;
1326         }
1327
1328         if (test)
1329                 return;
1330
1331         if (AR_SREV_9280_20_OR_LATER(ah)) {
1332                 for (i = 0; i < Ar5416RateSize; i++) {
1333                         int8_t pwr_table_offset;
1334
1335                         pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1336                                                         EEP_PWR_TABLE_OFFSET);
1337                         ratesArray[i] -= pwr_table_offset * 2;
1338                 }
1339         }
1340
1341         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1342                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1343                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1344                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1345                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1346         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1347                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1348                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1349                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1350                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1351
1352         if (IS_CHAN_2GHZ(chan)) {
1353                 if (OLC_FOR_AR9280_20_LATER) {
1354                         cck_ofdm_delta = 2;
1355                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1356                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1357                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1358                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1359                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1360                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1361                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1362                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1363                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1364                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1365                 } else {
1366                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1367                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
1368                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1369                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1370                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1371                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1372                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
1373                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1374                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1375                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1376                 }
1377         }
1378
1379         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1380                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1381                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1382                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1383                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1384         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1385                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1386                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1387                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1388                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1389
1390         if (IS_CHAN_HT40(chan)) {
1391                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1392                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1393                                        ht40PowerIncForPdadc, 24)
1394                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1395                                          ht40PowerIncForPdadc, 16)
1396                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1397                                          ht40PowerIncForPdadc, 8)
1398                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1399                                          ht40PowerIncForPdadc, 0));
1400                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1401                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1402                                        ht40PowerIncForPdadc, 24)
1403                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1404                                          ht40PowerIncForPdadc, 16)
1405                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1406                                          ht40PowerIncForPdadc, 8)
1407                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1408                                          ht40PowerIncForPdadc, 0));
1409                 if (OLC_FOR_AR9280_20_LATER) {
1410                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1411                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1412                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1413                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1414                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1415                 } else {
1416                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1417                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1418                                 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1419                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1420                                 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1421                 }
1422         }
1423
1424         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1425                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1426                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1427 }
1428
1429 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
1430                                           enum ath9k_hal_freq_band freq_band)
1431 {
1432         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1433         struct modal_eep_header *pModal =
1434                 &(eep->modalHeader[freq_band]);
1435         struct base_eep_header *pBase = &eep->baseEepHeader;
1436         u8 num_ant_config;
1437
1438         num_ant_config = 1;
1439
1440         if (pBase->version >= 0x0E0D &&
1441             (pModal->lna_ctl & LNA_CTL_USE_ANT1))
1442                 num_ant_config += 1;
1443
1444         return num_ant_config;
1445 }
1446
1447 static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
1448                                                struct ath9k_channel *chan)
1449 {
1450         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1451         struct modal_eep_header *pModal =
1452                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1453
1454         return pModal->antCtrlCommon;
1455 }
1456
1457 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1458 {
1459 #define EEP_DEF_SPURCHAN \
1460         (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1461         struct ath_common *common = ath9k_hw_common(ah);
1462
1463         u16 spur_val = AR_NO_SPUR;
1464
1465         ath_dbg(common, ATH_DBG_ANI,
1466                 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1467                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1468
1469         switch (ah->config.spurmode) {
1470         case SPUR_DISABLE:
1471                 break;
1472         case SPUR_ENABLE_IOCTL:
1473                 spur_val = ah->config.spurchans[i][is2GHz];
1474                 ath_dbg(common, ATH_DBG_ANI,
1475                         "Getting spur val from new loc. %d\n", spur_val);
1476                 break;
1477         case SPUR_ENABLE_EEPROM:
1478                 spur_val = EEP_DEF_SPURCHAN;
1479                 break;
1480         }
1481
1482         return spur_val;
1483
1484 #undef EEP_DEF_SPURCHAN
1485 }
1486
1487 const struct eeprom_ops eep_def_ops = {
1488         .check_eeprom           = ath9k_hw_def_check_eeprom,
1489         .get_eeprom             = ath9k_hw_def_get_eeprom,
1490         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
1491         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
1492         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
1493         .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
1494         .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
1495         .set_board_values       = ath9k_hw_def_set_board_values,
1496         .set_addac              = ath9k_hw_def_set_addac,
1497         .set_txpower            = ath9k_hw_def_set_txpower,
1498         .get_spur_channel       = ath9k_hw_def_get_spur_channel
1499 };