drivers/net/wireless/ath/ath9k/ar9003_eeprom.h

   1 #ifndef AR9003_EEPROM_H
   2 #define AR9003_EEPROM_H
   3
   4 #include <linux/types.h>
   5
   6 #define AR9300_EEP_VER               0xD000
   7 #define AR9300_EEP_VER_MINOR_MASK    0xFFF
   8 #define AR9300_EEP_MINOR_VER_1       0x1
   9 #define AR9300_EEP_MINOR_VER         AR9300_EEP_MINOR_VER_1
  10
  11 /* 16-bit offset location start of calibration struct */
  12 #define AR9300_EEP_START_LOC         256
  13 #define AR9300_NUM_5G_CAL_PIERS      8
  14 #define AR9300_NUM_2G_CAL_PIERS      3
  15 #define AR9300_NUM_5G_20_TARGET_POWERS  8
  16 #define AR9300_NUM_5G_40_TARGET_POWERS  8
  17 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
  18 #define AR9300_NUM_2G_20_TARGET_POWERS  3
  19 #define AR9300_NUM_2G_40_TARGET_POWERS  3
  20 /* #define AR9300_NUM_CTLS              21 */
  21 #define AR9300_NUM_CTLS_5G           9
  22 #define AR9300_NUM_CTLS_2G           12
  23 #define AR9300_CTL_MODE_M            0xF
  24 #define AR9300_NUM_BAND_EDGES_5G     8
  25 #define AR9300_NUM_BAND_EDGES_2G     4
  26 #define AR9300_NUM_PD_GAINS          4
  27 #define AR9300_PD_GAINS_IN_MASK      4
  28 #define AR9300_PD_GAIN_ICEPTS        5
  29 #define AR9300_EEPROM_MODAL_SPURS    5
  30 #define AR9300_MAX_RATE_POWER        63
  31 #define AR9300_NUM_PDADC_VALUES      128
  32 #define AR9300_NUM_RATES             16
  33 #define AR9300_BCHAN_UNUSED          0xFF
  34 #define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
  35 #define AR9300_OPFLAGS_11A           0x01
  36 #define AR9300_OPFLAGS_11G           0x02
  37 #define AR9300_OPFLAGS_5G_HT40       0x04
  38 #define AR9300_OPFLAGS_2G_HT40       0x08
  39 #define AR9300_OPFLAGS_5G_HT20       0x10
  40 #define AR9300_OPFLAGS_2G_HT20       0x20
  41 #define AR9300_EEPMISC_BIG_ENDIAN    0x01
  42 #define AR9300_EEPMISC_WOW           0x02
  43 #define AR9300_CUSTOMER_DATA_SIZE    20
  44
  45 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
  46 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
  47 #define AR9300_MAX_CHAINS            3
  48 #define AR9300_ANT_16S               25
  49 #define AR9300_FUTURE_MODAL_SZ       6
  50
  51 #define AR9300_NUM_ANT_CHAIN_FIELDS     7
  52 #define AR9300_NUM_ANT_COMMON_FIELDS    4
  53 #define AR9300_SIZE_ANT_CHAIN_FIELD     3
  54 #define AR9300_SIZE_ANT_COMMON_FIELD    4
  55 #define AR9300_ANT_CHAIN_MASK           0x7
  56 #define AR9300_ANT_COMMON_MASK          0xf
  57 #define AR9300_CHAIN_0_IDX              0
  58 #define AR9300_CHAIN_1_IDX              1
  59 #define AR9300_CHAIN_2_IDX              2
  60
  61 #define AR928X_NUM_ANT_CHAIN_FIELDS     6
  62 #define AR928X_SIZE_ANT_CHAIN_FIELD     2
  63 #define AR928X_ANT_CHAIN_MASK           0x3
  64
  65 /* Delta from which to start power to pdadc table */
  66 /* This offset is used in both open loop and closed loop power control
  67  * schemes. In open loop power control, it is not really needed, but for
  68  * the "sake of consistency" it was kept. For certain AP designs, this
  69  * value is overwritten by the value in the flag "pwrTableOffset" just
  70  * before writing the pdadc vs pwr into the chip registers.
  71  */
  72 #define AR9300_PWR_TABLE_OFFSET  0
  73
  74 /* enable flags for voltage and temp compensation */
  75 #define ENABLE_TEMP_COMPENSATION 0x01
  76 #define ENABLE_VOLT_COMPENSATION 0x02
  77 /* byte addressable */
  78 #define AR9300_EEPROM_SIZE (16*1024)
  79 #define FIXED_CCA_THRESHOLD 15
  80
  81 #define AR9300_BASE_ADDR 0x3ff
  82 #define AR9300_BASE_ADDR_512 0x1ff
  83
  84 #define AR9300_OTP_BASE                 0x14000
  85 #define AR9300_OTP_STATUS               0x15f18
  86 #define AR9300_OTP_STATUS_TYPE          0x7
  87 #define AR9300_OTP_STATUS_VALID         0x4
  88 #define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
  89 #define AR9300_OTP_STATUS_SM_BUSY       0x1
  90 #define AR9300_OTP_READ_DATA            0x15f1c
  91
  92 enum targetPowerHTRates {
  93         HT_TARGET_RATE_0_8_16,
  94         HT_TARGET_RATE_1_3_9_11_17_19,
  95         HT_TARGET_RATE_4,
  96         HT_TARGET_RATE_5,
  97         HT_TARGET_RATE_6,
  98         HT_TARGET_RATE_7,
  99         HT_TARGET_RATE_12,
 100         HT_TARGET_RATE_13,
 101         HT_TARGET_RATE_14,
 102         HT_TARGET_RATE_15,
 103         HT_TARGET_RATE_20,
 104         HT_TARGET_RATE_21,
 105         HT_TARGET_RATE_22,
 106         HT_TARGET_RATE_23
 107 };
 108
 109 enum targetPowerLegacyRates {
 110         LEGACY_TARGET_RATE_6_24,
 111         LEGACY_TARGET_RATE_36,
 112         LEGACY_TARGET_RATE_48,
 113         LEGACY_TARGET_RATE_54
 114 };
 115
 116 enum targetPowerCckRates {
 117         LEGACY_TARGET_RATE_1L_5L,
 118         LEGACY_TARGET_RATE_5S,
 119         LEGACY_TARGET_RATE_11L,
 120         LEGACY_TARGET_RATE_11S
 121 };
 122
 123 enum ar9300_Rates {
 124         ALL_TARGET_LEGACY_6_24,
 125         ALL_TARGET_LEGACY_36,
 126         ALL_TARGET_LEGACY_48,
 127         ALL_TARGET_LEGACY_54,
 128         ALL_TARGET_LEGACY_1L_5L,
 129         ALL_TARGET_LEGACY_5S,
 130         ALL_TARGET_LEGACY_11L,
 131         ALL_TARGET_LEGACY_11S,
 132         ALL_TARGET_HT20_0_8_16,
 133         ALL_TARGET_HT20_1_3_9_11_17_19,
 134         ALL_TARGET_HT20_4,
 135         ALL_TARGET_HT20_5,
 136         ALL_TARGET_HT20_6,
 137         ALL_TARGET_HT20_7,
 138         ALL_TARGET_HT20_12,
 139         ALL_TARGET_HT20_13,
 140         ALL_TARGET_HT20_14,
 141         ALL_TARGET_HT20_15,
 142         ALL_TARGET_HT20_20,
 143         ALL_TARGET_HT20_21,
 144         ALL_TARGET_HT20_22,
 145         ALL_TARGET_HT20_23,
 146         ALL_TARGET_HT40_0_8_16,
 147         ALL_TARGET_HT40_1_3_9_11_17_19,
 148         ALL_TARGET_HT40_4,
 149         ALL_TARGET_HT40_5,
 150         ALL_TARGET_HT40_6,
 151         ALL_TARGET_HT40_7,
 152         ALL_TARGET_HT40_12,
 153         ALL_TARGET_HT40_13,
 154         ALL_TARGET_HT40_14,
 155         ALL_TARGET_HT40_15,
 156         ALL_TARGET_HT40_20,
 157         ALL_TARGET_HT40_21,
 158         ALL_TARGET_HT40_22,
 159         ALL_TARGET_HT40_23,
 160         ar9300RateSize,
 161 };
 162
 163
 164 struct eepFlags {
 165         u8 opFlags;
 166         u8 eepMisc;
 167 } __packed;
 168
 169 enum CompressAlgorithm {
 170         _CompressNone = 0,
 171         _CompressLzma,
 172         _CompressPairs,
 173         _CompressBlock,
 174         _Compress4,
 175         _Compress5,
 176         _Compress6,
 177         _Compress7,
 178 };
 179
 180 struct ar9300_base_eep_hdr {
 181         __le16 regDmn[2];
 182         /* 4 bits tx and 4 bits rx */
 183         u8 txrxMask;
 184         struct eepFlags opCapFlags;
 185         u8 rfSilent;
 186         u8 blueToothOptions;
 187         u8 deviceCap;
 188         /* takes lower byte in eeprom location */
 189         u8 deviceType;
 190         /* offset in dB to be added to beginning
 191          * of pdadc table in calibration
 192          */
 193         int8_t pwrTableOffset;
 194         u8 params_for_tuning_caps[2];
 195         /*
 196          * bit0 - enable tx temp comp
 197          * bit1 - enable tx volt comp
 198          * bit2 - enable fastClock - default to 1
 199          * bit3 - enable doubling - default to 1
 200          * bit4 - enable internal regulator - default to 1
 201          */
 202         u8 featureEnable;
 203         /* misc flags: bit0 - turn down drivestrength */
 204         u8 miscConfiguration;
 205         u8 eepromWriteEnableGpio;
 206         u8 wlanDisableGpio;
 207         u8 wlanLedGpio;
 208         u8 rxBandSelectGpio;
 209         u8 txrxgain;
 210         /* SW controlled internal regulator fields */
 211         __le32 swreg;
 212 } __packed;
 213
 214 struct ar9300_modal_eep_header {
 215         /* 4 idle, t1, t2, b (4 bits per setting) */
 216         __le32 antCtrlCommon;
 217         /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 218         __le32 antCtrlCommon2;
 219         /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
 220         __le16 antCtrlChain[AR9300_MAX_CHAINS];
 221         /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 222         u8 xatten1DB[AR9300_MAX_CHAINS];
 223         /* 3  xatten1_margin for merlin (0xa20c/b20c 16:12 */
 224         u8 xatten1Margin[AR9300_MAX_CHAINS];
 225         int8_t tempSlope;
 226         int8_t voltSlope;
 227         /* spur channels in usual fbin coding format */
 228         u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
 229         /* 3  Check if the register is per chain */
 230         int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
 231         u8 ob[AR9300_MAX_CHAINS];
 232         u8 db_stage2[AR9300_MAX_CHAINS];
 233         u8 db_stage3[AR9300_MAX_CHAINS];
 234         u8 db_stage4[AR9300_MAX_CHAINS];
 235         u8 xpaBiasLvl;
 236         u8 txFrameToDataStart;
 237         u8 txFrameToPaOn;
 238         u8 txClip;
 239         int8_t antennaGain;
 240         u8 switchSettling;
 241         int8_t adcDesiredSize;
 242         u8 txEndToXpaOff;
 243         u8 txEndToRxOn;
 244         u8 txFrameToXpaOn;
 245         u8 thresh62;
 246         __le32 papdRateMaskHt20;
 247         __le32 papdRateMaskHt40;
 248         u8 futureModal[10];
 249 } __packed;
 250
 251 struct ar9300_cal_data_per_freq_op_loop {
 252         int8_t refPower;
 253         /* pdadc voltage at power measurement */
 254         u8 voltMeas;
 255         /* pcdac used for power measurement   */
 256         u8 tempMeas;
 257         /* range is -60 to -127 create a mapping equation 1db resolution */
 258         int8_t rxNoisefloorCal;
 259         /*range is same as noisefloor */
 260         int8_t rxNoisefloorPower;
 261         /* temp measured when noisefloor cal was performed */
 262         u8 rxTempMeas;
 263 } __packed;
 264
 265 struct cal_tgt_pow_legacy {
 266         u8 tPow2x[4];
 267 } __packed;
 268
 269 struct cal_tgt_pow_ht {
 270         u8 tPow2x[14];
 271 } __packed;
 272
 273 struct cal_ctl_edge_pwr {
 274         u8 tPower:6,
 275            flag:2;
 276 } __packed;
 277
 278 struct cal_ctl_data_2g {
 279         struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_2G];
 280 } __packed;
 281
 282 struct cal_ctl_data_5g {
 283         struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
 284 } __packed;
 285
 286 struct ar9300_BaseExtension_1 {
 287         u8 ant_div_control;
 288         u8 future[13];
 289 } __packed;
 290
 291 struct ar9300_BaseExtension_2 {
 292         int8_t    tempSlopeLow;
 293         int8_t    tempSlopeHigh;
 294         u8   xatten1DBLow[AR9300_MAX_CHAINS];
 295         u8   xatten1MarginLow[AR9300_MAX_CHAINS];
 296         u8   xatten1DBHigh[AR9300_MAX_CHAINS];
 297         u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
 298 } __packed;
 299
 300 struct ar9300_eeprom {
 301         u8 eepromVersion;
 302         u8 templateVersion;
 303         u8 macAddr[6];
 304         u8 custData[AR9300_CUSTOMER_DATA_SIZE];
 305
 306         struct ar9300_base_eep_hdr baseEepHeader;
 307
 308         struct ar9300_modal_eep_header modalHeader2G;
 309         struct ar9300_BaseExtension_1 base_ext1;
 310         u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
 311         struct ar9300_cal_data_per_freq_op_loop
 312          calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
 313         u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
 314         u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
 315         u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
 316         u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
 317         struct cal_tgt_pow_legacy
 318          calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
 319         struct cal_tgt_pow_legacy
 320          calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
 321         struct cal_tgt_pow_ht
 322          calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
 323         struct cal_tgt_pow_ht
 324          calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
 325         u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
 326         u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
 327         struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
 328         struct ar9300_modal_eep_header modalHeader5G;
 329         struct ar9300_BaseExtension_2 base_ext2;
 330         u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
 331         struct ar9300_cal_data_per_freq_op_loop
 332          calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
 333         u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
 334         u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
 335         u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
 336         struct cal_tgt_pow_legacy
 337          calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
 338         struct cal_tgt_pow_ht
 339          calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
 340         struct cal_tgt_pow_ht
 341          calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
 342         u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
 343         u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
 344         struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
 345 } __packed;
 346
 347 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
 348 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
 349
 350 #endif