drivers/net/wireless/ath/ath9k/ar9002_calib.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "hw-ops.h"
  19 #include "ar9002_phy.h"
  20
  21 #define AR9285_CLCAL_REDO_THRESH    1
  22
  23 enum ar9002_cal_types {
  24         ADC_GAIN_CAL = BIT(0),
  25         ADC_DC_CAL = BIT(1),
  26         IQ_MISMATCH_CAL = BIT(2),
  27 };
  28
  29 static bool ar9002_hw_is_cal_supported(struct ath_hw *ah,
  30                                 struct ath9k_channel *chan,
  31                                 enum ar9002_cal_types cal_type)
  32 {
  33         bool supported = false;
  34         switch (ah->supp_cals & cal_type) {
  35         case IQ_MISMATCH_CAL:
  36                 /* Run IQ Mismatch for non-CCK only */
  37                 if (!IS_CHAN_B(chan))
  38                         supported = true;
  39                 break;
  40         case ADC_GAIN_CAL:
  41         case ADC_DC_CAL:
  42                 /* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
  43                 if (!IS_CHAN_B(chan) &&
  44                     !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
  45                         supported = true;
  46                 break;
  47         }
  48         return supported;
  49 }
  50
  51 static void ar9002_hw_setup_calibration(struct ath_hw *ah,
  52                                         struct ath9k_cal_list *currCal)
  53 {
  54         struct ath_common *common = ath9k_hw_common(ah);
  55
  56         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
  57                       AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
  58                       currCal->calData->calCountMax);
  59
  60         switch (currCal->calData->calType) {
  61         case IQ_MISMATCH_CAL:
  62                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
  63                 ath_dbg(common, ATH_DBG_CALIBRATE,
  64                         "starting IQ Mismatch Calibration\n");
  65                 break;
  66         case ADC_GAIN_CAL:
  67                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
  68                 ath_dbg(common, ATH_DBG_CALIBRATE,
  69                         "starting ADC Gain Calibration\n");
  70                 break;
  71         case ADC_DC_CAL:
  72                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
  73                 ath_dbg(common, ATH_DBG_CALIBRATE,
  74                         "starting ADC DC Calibration\n");
  75                 break;
  76         }
  77
  78         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
  79                     AR_PHY_TIMING_CTRL4_DO_CAL);
  80 }
  81
  82 static bool ar9002_hw_per_calibration(struct ath_hw *ah,
  83                                       struct ath9k_channel *ichan,
  84                                       u8 rxchainmask,
  85                                       struct ath9k_cal_list *currCal)
  86 {
  87         struct ath9k_hw_cal_data *caldata = ah->caldata;
  88         bool iscaldone = false;
  89
  90         if (currCal->calState == CAL_RUNNING) {
  91                 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
  92                       AR_PHY_TIMING_CTRL4_DO_CAL)) {
  93
  94                         currCal->calData->calCollect(ah);
  95                         ah->cal_samples++;
  96
  97                         if (ah->cal_samples >=
  98                             currCal->calData->calNumSamples) {
  99                                 int i, numChains = 0;
 100                                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 101                                         if (rxchainmask & (1 << i))
 102                                                 numChains++;
 103                                 }
 104
 105                                 currCal->calData->calPostProc(ah, numChains);
 106                                 caldata->CalValid |= currCal->calData->calType;
 107                                 currCal->calState = CAL_DONE;
 108                                 iscaldone = true;
 109                         } else {
 110                                 ar9002_hw_setup_calibration(ah, currCal);
 111                         }
 112                 }
 113         } else if (!(caldata->CalValid & currCal->calData->calType)) {
 114                 ath9k_hw_reset_calibration(ah, currCal);
 115         }
 116
 117         return iscaldone;
 118 }
 119
 120 static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
 121 {
 122         int i;
 123
 124         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 125                 ah->totalPowerMeasI[i] +=
 126                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 127                 ah->totalPowerMeasQ[i] +=
 128                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 129                 ah->totalIqCorrMeas[i] +=
 130                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 131                 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 132                         "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
 133                         ah->cal_samples, i, ah->totalPowerMeasI[i],
 134                         ah->totalPowerMeasQ[i],
 135                         ah->totalIqCorrMeas[i]);
 136         }
 137 }
 138
 139 static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
 140 {
 141         int i;
 142
 143         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 144                 ah->totalAdcIOddPhase[i] +=
 145                         REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 146                 ah->totalAdcIEvenPhase[i] +=
 147                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 148                 ah->totalAdcQOddPhase[i] +=
 149                         REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 150                 ah->totalAdcQEvenPhase[i] +=
 151                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 152
 153                 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 154                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
 155                         ah->cal_samples, i,
 156                         ah->totalAdcIOddPhase[i],
 157                         ah->totalAdcIEvenPhase[i],
 158                         ah->totalAdcQOddPhase[i],
 159                         ah->totalAdcQEvenPhase[i]);
 160         }
 161 }
 162
 163 static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
 164 {
 165         int i;
 166
 167         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 168                 ah->totalAdcDcOffsetIOddPhase[i] +=
 169                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
 170                 ah->totalAdcDcOffsetIEvenPhase[i] +=
 171                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
 172                 ah->totalAdcDcOffsetQOddPhase[i] +=
 173                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
 174                 ah->totalAdcDcOffsetQEvenPhase[i] +=
 175                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 176
 177                 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
 178                         "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
 179                         ah->cal_samples, i,
 180                         ah->totalAdcDcOffsetIOddPhase[i],
 181                         ah->totalAdcDcOffsetIEvenPhase[i],
 182                         ah->totalAdcDcOffsetQOddPhase[i],
 183                         ah->totalAdcDcOffsetQEvenPhase[i]);
 184         }
 185 }
 186
 187 static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
 188 {
 189         struct ath_common *common = ath9k_hw_common(ah);
 190         u32 powerMeasQ, powerMeasI, iqCorrMeas;
 191         u32 qCoffDenom, iCoffDenom;
 192         int32_t qCoff, iCoff;
 193         int iqCorrNeg, i;
 194
 195         for (i = 0; i < numChains; i++) {
 196                 powerMeasI = ah->totalPowerMeasI[i];
 197                 powerMeasQ = ah->totalPowerMeasQ[i];
 198                 iqCorrMeas = ah->totalIqCorrMeas[i];
 199
 200                 ath_dbg(common, ATH_DBG_CALIBRATE,
 201                         "Starting IQ Cal and Correction for Chain %d\n",
 202                         i);
 203
 204                 ath_dbg(common, ATH_DBG_CALIBRATE,
 205                         "Orignal: Chn %diq_corr_meas = 0x%08x\n",
 206                         i, ah->totalIqCorrMeas[i]);
 207
 208                 iqCorrNeg = 0;
 209
 210                 if (iqCorrMeas > 0x80000000) {
 211                         iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
 212                         iqCorrNeg = 1;
 213                 }
 214
 215                 ath_dbg(common, ATH_DBG_CALIBRATE,
 216                         "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
 217                 ath_dbg(common, ATH_DBG_CALIBRATE,
 218                         "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
 219                 ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
 220                         iqCorrNeg);
 221
 222                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
 223                 qCoffDenom = powerMeasQ / 64;
 224
 225                 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
 226                     (qCoffDenom != 0)) {
 227                         iCoff = iqCorrMeas / iCoffDenom;
 228                         qCoff = powerMeasI / qCoffDenom - 64;
 229                         ath_dbg(common, ATH_DBG_CALIBRATE,
 230                                 "Chn %d iCoff = 0x%08x\n", i, iCoff);
 231                         ath_dbg(common, ATH_DBG_CALIBRATE,
 232                                 "Chn %d qCoff = 0x%08x\n", i, qCoff);
 233
 234                         iCoff = iCoff & 0x3f;
 235                         ath_dbg(common, ATH_DBG_CALIBRATE,
 236                                 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
 237                         if (iqCorrNeg == 0x0)
 238                                 iCoff = 0x40 - iCoff;
 239
 240                         if (qCoff > 15)
 241                                 qCoff = 15;
 242                         else if (qCoff <= -16)
 243                                 qCoff = -16;
 244
 245                         ath_dbg(common, ATH_DBG_CALIBRATE,
 246                                 "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
 247                                 i, iCoff, qCoff);
 248
 249                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
 250                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
 251                                       iCoff);
 252                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
 253                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
 254                                       qCoff);
 255                         ath_dbg(common, ATH_DBG_CALIBRATE,
 256                                 "IQ Cal and Correction done for Chain %d\n",
 257                                 i);
 258                 }
 259         }
 260
 261         REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
 262                     AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
 263 }
 264
 265 static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
 266 {
 267         struct ath_common *common = ath9k_hw_common(ah);
 268         u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
 269         u32 qGainMismatch, iGainMismatch, val, i;
 270
 271         for (i = 0; i < numChains; i++) {
 272                 iOddMeasOffset = ah->totalAdcIOddPhase[i];
 273                 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
 274                 qOddMeasOffset = ah->totalAdcQOddPhase[i];
 275                 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
 276
 277                 ath_dbg(common, ATH_DBG_CALIBRATE,
 278                         "Starting ADC Gain Cal for Chain %d\n", i);
 279
 280                 ath_dbg(common, ATH_DBG_CALIBRATE,
 281                         "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
 282                         iOddMeasOffset);
 283                 ath_dbg(common, ATH_DBG_CALIBRATE,
 284                         "Chn %d pwr_meas_even_i = 0x%08x\n", i,
 285                         iEvenMeasOffset);
 286                 ath_dbg(common, ATH_DBG_CALIBRATE,
 287                         "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
 288                         qOddMeasOffset);
 289                 ath_dbg(common, ATH_DBG_CALIBRATE,
 290                         "Chn %d pwr_meas_even_q = 0x%08x\n", i,
 291                         qEvenMeasOffset);
 292
 293                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
 294                         iGainMismatch =
 295                                 ((iEvenMeasOffset * 32) /
 296                                  iOddMeasOffset) & 0x3f;
 297                         qGainMismatch =
 298                                 ((qOddMeasOffset * 32) /
 299                                  qEvenMeasOffset) & 0x3f;
 300
 301                         ath_dbg(common, ATH_DBG_CALIBRATE,
 302                                 "Chn %d gain_mismatch_i = 0x%08x\n", i,
 303                                 iGainMismatch);
 304                         ath_dbg(common, ATH_DBG_CALIBRATE,
 305                                 "Chn %d gain_mismatch_q = 0x%08x\n", i,
 306                                 qGainMismatch);
 307
 308                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 309                         val &= 0xfffff000;
 310                         val |= (qGainMismatch) | (iGainMismatch << 6);
 311                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 312
 313                         ath_dbg(common, ATH_DBG_CALIBRATE,
 314                                 "ADC Gain Cal done for Chain %d\n", i);
 315                 }
 316         }
 317
 318         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 319                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
 320                   AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
 321 }
 322
 323 static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
 324 {
 325         struct ath_common *common = ath9k_hw_common(ah);
 326         u32 iOddMeasOffset, iEvenMeasOffset, val, i;
 327         int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
 328         const struct ath9k_percal_data *calData =
 329                 ah->cal_list_curr->calData;
 330         u32 numSamples =
 331                 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
 332
 333         for (i = 0; i < numChains; i++) {
 334                 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
 335                 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
 336                 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
 337                 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
 338
 339                 ath_dbg(common, ATH_DBG_CALIBRATE,
 340                         "Starting ADC DC Offset Cal for Chain %d\n", i);
 341
 342                 ath_dbg(common, ATH_DBG_CALIBRATE,
 343                         "Chn %d pwr_meas_odd_i = %d\n", i,
 344                         iOddMeasOffset);
 345                 ath_dbg(common, ATH_DBG_CALIBRATE,
 346                         "Chn %d pwr_meas_even_i = %d\n", i,
 347                         iEvenMeasOffset);
 348                 ath_dbg(common, ATH_DBG_CALIBRATE,
 349                         "Chn %d pwr_meas_odd_q = %d\n", i,
 350                         qOddMeasOffset);
 351                 ath_dbg(common, ATH_DBG_CALIBRATE,
 352                         "Chn %d pwr_meas_even_q = %d\n", i,
 353                         qEvenMeasOffset);
 354
 355                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
 356                                numSamples) & 0x1ff;
 357                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
 358                                numSamples) & 0x1ff;
 359
 360                 ath_dbg(common, ATH_DBG_CALIBRATE,
 361                         "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
 362                         iDcMismatch);
 363                 ath_dbg(common, ATH_DBG_CALIBRATE,
 364                         "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
 365                         qDcMismatch);
 366
 367                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
 368                 val &= 0xc0000fff;
 369                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
 370                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 371
 372                 ath_dbg(common, ATH_DBG_CALIBRATE,
 373                         "ADC DC Offset Cal done for Chain %d\n", i);
 374         }
 375
 376         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
 377                   REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
 378                   AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
 379 }
 380
 381 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
 382 {
 383         u32 rddata;
 384         int32_t delta, currPDADC, slope;
 385
 386         rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
 387         currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
 388
 389         if (ah->initPDADC == 0 || currPDADC == 0) {
 390                 /*
 391                  * Zero value indicates that no frames have been transmitted
 392                  * yet, can't do temperature compensation until frames are
 393                  * transmitted.
 394                  */
 395                 return;
 396         } else {
 397                 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
 398
 399                 if (slope == 0) { /* to avoid divide by zero case */
 400                         delta = 0;
 401                 } else {
 402                         delta = ((currPDADC - ah->initPDADC)*4) / slope;
 403                 }
 404                 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
 405                               AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
 406                 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
 407                               AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
 408         }
 409 }
 410
 411 static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
 412 {
 413         u32 rddata, i;
 414         int delta, currPDADC, regval;
 415
 416         rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
 417         currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
 418
 419         if (ah->initPDADC == 0 || currPDADC == 0)
 420                 return;
 421
 422         if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
 423                 delta = (currPDADC - ah->initPDADC + 4) / 8;
 424         else
 425                 delta = (currPDADC - ah->initPDADC + 5) / 10;
 426
 427         if (delta != ah->PDADCdelta) {
 428                 ah->PDADCdelta = delta;
 429                 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
 430                         regval = ah->originalGain[i] - delta;
 431                         if (regval < 0)
 432                                 regval = 0;
 433
 434                         REG_RMW_FIELD(ah,
 435                                       AR_PHY_TX_GAIN_TBL1 + i * 4,
 436                                       AR_PHY_TX_GAIN, regval);
 437                 }
 438         }
 439 }
 440
 441 static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
 442 {
 443         u32 regVal;
 444         unsigned int i;
 445         u32 regList[][2] = {
 446                 { 0x786c, 0 },
 447                 { 0x7854, 0 },
 448                 { 0x7820, 0 },
 449                 { 0x7824, 0 },
 450                 { 0x7868, 0 },
 451                 { 0x783c, 0 },
 452                 { 0x7838, 0 } ,
 453                 { 0x7828, 0 } ,
 454         };
 455
 456         for (i = 0; i < ARRAY_SIZE(regList); i++)
 457                 regList[i][1] = REG_READ(ah, regList[i][0]);
 458
 459         regVal = REG_READ(ah, 0x7834);
 460         regVal &= (~(0x1));
 461         REG_WRITE(ah, 0x7834, regVal);
 462         regVal = REG_READ(ah, 0x9808);
 463         regVal |= (0x1 << 27);
 464         REG_WRITE(ah, 0x9808, regVal);
 465
 466         /* 786c,b23,1, pwddac=1 */
 467         REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
 468         /* 7854, b5,1, pdrxtxbb=1 */
 469         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
 470         /* 7854, b7,1, pdv2i=1 */
 471         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
 472         /* 7854, b8,1, pddacinterface=1 */
 473         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
 474         /* 7824,b12,0, offcal=0 */
 475         REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
 476         /* 7838, b1,0, pwddb=0 */
 477         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
 478         /* 7820,b11,0, enpacal=0 */
 479         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
 480         /* 7820,b25,1, pdpadrv1=0 */
 481         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
 482         /* 7820,b24,0, pdpadrv2=0 */
 483         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
 484         /* 7820,b23,0, pdpaout=0 */
 485         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
 486         /* 783c,b14-16,7, padrvgn2tab_0=7 */
 487         REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
 488         /*
 489          * 7838,b29-31,0, padrvgn1tab_0=0
 490          * does not matter since we turn it off
 491          */
 492         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
 493
 494         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
 495
 496         /* Set:
 497          * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
 498          * txon=1,paon=1,oscon=1,synthon_force=1
 499          */
 500         REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
 501         udelay(30);
 502         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
 503
 504         /* find off_6_1; */
 505         for (i = 6; i > 0; i--) {
 506                 regVal = REG_READ(ah, 0x7834);
 507                 regVal |= (1 << (20 + i));
 508                 REG_WRITE(ah, 0x7834, regVal);
 509                 udelay(1);
 510                 /* regVal = REG_READ(ah, 0x7834); */
 511                 regVal &= (~(0x1 << (20 + i)));
 512                 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
 513                             << (20 + i));
 514                 REG_WRITE(ah, 0x7834, regVal);
 515         }
 516
 517         regVal = (regVal >> 20) & 0x7f;
 518
 519         /* Update PA cal info */
 520         if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
 521                 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
 522                         ah->pacal_info.max_skipcount =
 523                                 2 * ah->pacal_info.max_skipcount;
 524                 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
 525         } else {
 526                 ah->pacal_info.max_skipcount = 1;
 527                 ah->pacal_info.skipcount = 0;
 528                 ah->pacal_info.prev_offset = regVal;
 529         }
 530
 531         ENABLE_REGWRITE_BUFFER(ah);
 532
 533         regVal = REG_READ(ah, 0x7834);
 534         regVal |= 0x1;
 535         REG_WRITE(ah, 0x7834, regVal);
 536         regVal = REG_READ(ah, 0x9808);
 537         regVal &= (~(0x1 << 27));
 538         REG_WRITE(ah, 0x9808, regVal);
 539
 540         for (i = 0; i < ARRAY_SIZE(regList); i++)
 541                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 542
 543         REGWRITE_BUFFER_FLUSH(ah);
 544 }
 545
 546 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
 547 {
 548         struct ath_common *common = ath9k_hw_common(ah);
 549         u32 regVal;
 550         int i, offset, offs_6_1, offs_0;
 551         u32 ccomp_org, reg_field;
 552         u32 regList[][2] = {
 553                 { 0x786c, 0 },
 554                 { 0x7854, 0 },
 555                 { 0x7820, 0 },
 556                 { 0x7824, 0 },
 557                 { 0x7868, 0 },
 558                 { 0x783c, 0 },
 559                 { 0x7838, 0 },
 560         };
 561
 562         ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
 563
 564         /* PA CAL is not needed for high power solution */
 565         if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
 566             AR5416_EEP_TXGAIN_HIGH_POWER)
 567                 return;
 568
 569         for (i = 0; i < ARRAY_SIZE(regList); i++)
 570                 regList[i][1] = REG_READ(ah, regList[i][0]);
 571
 572         regVal = REG_READ(ah, 0x7834);
 573         regVal &= (~(0x1));
 574         REG_WRITE(ah, 0x7834, regVal);
 575         regVal = REG_READ(ah, 0x9808);
 576         regVal |= (0x1 << 27);
 577         REG_WRITE(ah, 0x9808, regVal);
 578
 579         REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
 580         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
 581         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
 582         REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
 583         REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
 584         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
 585         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
 586         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
 587         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
 588         REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
 589         REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
 590         REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
 591         ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
 592         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
 593
 594         REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
 595         udelay(30);
 596         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
 597         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
 598
 599         for (i = 6; i > 0; i--) {
 600                 regVal = REG_READ(ah, 0x7834);
 601                 regVal |= (1 << (19 + i));
 602                 REG_WRITE(ah, 0x7834, regVal);
 603                 udelay(1);
 604                 regVal = REG_READ(ah, 0x7834);
 605                 regVal &= (~(0x1 << (19 + i)));
 606                 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
 607                 regVal |= (reg_field << (19 + i));
 608                 REG_WRITE(ah, 0x7834, regVal);
 609         }
 610
 611         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
 612         udelay(1);
 613         reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
 614         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
 615         offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
 616         offs_0   = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
 617
 618         offset = (offs_6_1<<1) | offs_0;
 619         offset = offset - 0;
 620         offs_6_1 = offset>>1;
 621         offs_0 = offset & 1;
 622
 623         if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
 624                 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
 625                         ah->pacal_info.max_skipcount =
 626                                 2 * ah->pacal_info.max_skipcount;
 627                 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
 628         } else {
 629                 ah->pacal_info.max_skipcount = 1;
 630                 ah->pacal_info.skipcount = 0;
 631                 ah->pacal_info.prev_offset = offset;
 632         }
 633
 634         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
 635         REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
 636
 637         regVal = REG_READ(ah, 0x7834);
 638         regVal |= 0x1;
 639         REG_WRITE(ah, 0x7834, regVal);
 640         regVal = REG_READ(ah, 0x9808);
 641         regVal &= (~(0x1 << 27));
 642         REG_WRITE(ah, 0x9808, regVal);
 643
 644         for (i = 0; i < ARRAY_SIZE(regList); i++)
 645                 REG_WRITE(ah, regList[i][0], regList[i][1]);
 646
 647         REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
 648 }
 649
 650 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
 651 {
 652         if (AR_SREV_9271(ah)) {
 653                 if (is_reset || !ah->pacal_info.skipcount)
 654                         ar9271_hw_pa_cal(ah, is_reset);
 655                 else
 656                         ah->pacal_info.skipcount--;
 657         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 658                 if (is_reset || !ah->pacal_info.skipcount)
 659                         ar9285_hw_pa_cal(ah, is_reset);
 660                 else
 661                         ah->pacal_info.skipcount--;
 662         }
 663 }
 664
 665 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
 666 {
 667         if (OLC_FOR_AR9287_10_LATER)
 668                 ar9287_hw_olc_temp_compensation(ah);
 669         else if (OLC_FOR_AR9280_20_LATER)
 670                 ar9280_hw_olc_temp_compensation(ah);
 671 }
 672
 673 static bool ar9002_hw_calibrate(struct ath_hw *ah,
 674                                 struct ath9k_channel *chan,
 675                                 u8 rxchainmask,
 676                                 bool longcal)
 677 {
 678         bool iscaldone = true;
 679         struct ath9k_cal_list *currCal = ah->cal_list_curr;
 680         bool nfcal, nfcal_pending = false;
 681
 682         nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF);
 683         if (ah->caldata)
 684                 nfcal_pending = ah->caldata->nfcal_pending;
 685
 686         if (currCal && !nfcal &&
 687             (currCal->calState == CAL_RUNNING ||
 688              currCal->calState == CAL_WAITING)) {
 689                 iscaldone = ar9002_hw_per_calibration(ah, chan,
 690                                                       rxchainmask, currCal);
 691                 if (iscaldone) {
 692                         ah->cal_list_curr = currCal = currCal->calNext;
 693
 694                         if (currCal->calState == CAL_WAITING) {
 695                                 iscaldone = false;
 696                                 ath9k_hw_reset_calibration(ah, currCal);
 697                         }
 698                 }
 699         }
 700
 701         /* Do NF cal only at longer intervals */
 702         if (longcal || nfcal_pending) {
 703                 /*
 704                  * Get the value from the previous NF cal and update
 705                  * history buffer.
 706                  */
 707                 if (ath9k_hw_getnf(ah, chan)) {
 708                         /*
 709                          * Load the NF from history buffer of the current
 710                          * channel.
 711                          * NF is slow time-variant, so it is OK to use a
 712                          * historical value.
 713                          */
 714                         ath9k_hw_loadnf(ah, ah->curchan);
 715                 }
 716
 717                 if (longcal) {
 718                         ath9k_hw_start_nfcal(ah, false);
 719                         /* Do periodic PAOffset Cal */
 720                         ar9002_hw_pa_cal(ah, false);
 721                         ar9002_hw_olc_temp_compensation(ah);
 722                 }
 723         }
 724
 725         return iscaldone;
 726 }
 727
 728 /* Carrier leakage Calibration fix */
 729 static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
 730 {
 731         struct ath_common *common = ath9k_hw_common(ah);
 732
 733         REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 734         if (IS_CHAN_HT20(chan)) {
 735                 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
 736                 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
 737                 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 738                             AR_PHY_AGC_CONTROL_FLTR_CAL);
 739                 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
 740                 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
 741                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
 742                                   AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
 743                         ath_dbg(common, ATH_DBG_CALIBRATE,
 744                                 "offset calibration failed to complete in 1ms; noisy environment?\n");
 745                         return false;
 746                 }
 747                 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
 748                 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
 749                 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 750         }
 751         REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 752         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
 753         REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
 754         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
 755         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
 756                           0, AH_WAIT_TIMEOUT)) {
 757                 ath_dbg(common, ATH_DBG_CALIBRATE,
 758                         "offset calibration failed to complete in 1ms; noisy environment?\n");
 759                 return false;
 760         }
 761
 762         REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 763         REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 764         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
 765
 766         return true;
 767 }
 768
 769 static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
 770 {
 771         int i;
 772         u_int32_t txgain_max;
 773         u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
 774         u_int32_t reg_clc_I0, reg_clc_Q0;
 775         u_int32_t i0_num = 0;
 776         u_int32_t q0_num = 0;
 777         u_int32_t total_num = 0;
 778         u_int32_t reg_rf2g5_org;
 779         bool retv = true;
 780
 781         if (!(ar9285_hw_cl_cal(ah, chan)))
 782                 return false;
 783
 784         txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
 785                         AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
 786
 787         for (i = 0; i < (txgain_max+1); i++) {
 788                 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
 789                            AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
 790                 if (!(gain_mask & (1 << clc_gain))) {
 791                         gain_mask |= (1 << clc_gain);
 792                         clc_num++;
 793                 }
 794         }
 795
 796         for (i = 0; i < clc_num; i++) {
 797                 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
 798                               & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
 799                 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
 800                               & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
 801                 if (reg_clc_I0 == 0)
 802                         i0_num++;
 803
 804                 if (reg_clc_Q0 == 0)
 805                         q0_num++;
 806         }
 807         total_num = i0_num + q0_num;
 808         if (total_num > AR9285_CLCAL_REDO_THRESH) {
 809                 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
 810                 if (AR_SREV_9285E_20(ah)) {
 811                         REG_WRITE(ah, AR9285_RF2G5,
 812                                   (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
 813                                   AR9285_RF2G5_IC50TX_XE_SET);
 814                 } else {
 815                         REG_WRITE(ah, AR9285_RF2G5,
 816                                   (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
 817                                   AR9285_RF2G5_IC50TX_SET);
 818                 }
 819                 retv = ar9285_hw_cl_cal(ah, chan);
 820                 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
 821         }
 822         return retv;
 823 }
 824
 825 static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
 826 {
 827         struct ath_common *common = ath9k_hw_common(ah);
 828
 829         if (AR_SREV_9271(ah)) {
 830                 if (!ar9285_hw_cl_cal(ah, chan))
 831                         return false;
 832         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 833                 if (!ar9285_hw_clc(ah, chan))
 834                         return false;
 835         } else {
 836                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 837                         if (!AR_SREV_9287_11_OR_LATER(ah))
 838                                 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
 839                                             AR_PHY_ADC_CTL_OFF_PWDADC);
 840                         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
 841                                     AR_PHY_AGC_CONTROL_FLTR_CAL);
 842                 }
 843
 844                 /* Calibrate the AGC */
 845                 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
 846                           REG_READ(ah, AR_PHY_AGC_CONTROL) |
 847                           AR_PHY_AGC_CONTROL_CAL);
 848
 849                 /* Poll for offset calibration complete */
 850                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
 851                                    AR_PHY_AGC_CONTROL_CAL,
 852                                    0, AH_WAIT_TIMEOUT)) {
 853                         ath_dbg(common, ATH_DBG_CALIBRATE,
 854                                 "offset calibration failed to complete in 1ms; noisy environment?\n");
 855                         return false;
 856                 }
 857
 858                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 859                         if (!AR_SREV_9287_11_OR_LATER(ah))
 860                                 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
 861                                             AR_PHY_ADC_CTL_OFF_PWDADC);
 862                         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
 863                                     AR_PHY_AGC_CONTROL_FLTR_CAL);
 864                 }
 865         }
 866
 867         /* Do PA Calibration */
 868         ar9002_hw_pa_cal(ah, true);
 869
 870         /* Do NF Calibration after DC offset and other calibrations */
 871         ath9k_hw_start_nfcal(ah, true);
 872
 873         if (ah->caldata)
 874                 ah->caldata->nfcal_pending = true;
 875
 876         ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
 877
 878         /* Enable IQ, ADC Gain and ADC DC offset CALs */
 879         if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
 880                 ah->supp_cals = IQ_MISMATCH_CAL;
 881
 882                 if (AR_SREV_9160_10_OR_LATER(ah))
 883                         ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL;
 884
 885                 if (AR_SREV_9287(ah))
 886                         ah->supp_cals &= ~ADC_GAIN_CAL;
 887
 888                 if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) {
 889                         INIT_CAL(&ah->adcgain_caldata);
 890                         INSERT_CAL(ah, &ah->adcgain_caldata);
 891                         ath_dbg(common, ATH_DBG_CALIBRATE,
 892                                         "enabling ADC Gain Calibration.\n");
 893                 }
 894
 895                 if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) {
 896                         INIT_CAL(&ah->adcdc_caldata);
 897                         INSERT_CAL(ah, &ah->adcdc_caldata);
 898                         ath_dbg(common, ATH_DBG_CALIBRATE,
 899                                         "enabling ADC DC Calibration.\n");
 900                 }
 901
 902                 if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) {
 903                         INIT_CAL(&ah->iq_caldata);
 904                         INSERT_CAL(ah, &ah->iq_caldata);
 905                         ath_dbg(common, ATH_DBG_CALIBRATE,
 906                                         "enabling IQ Calibration.\n");
 907                 }
 908
 909                 ah->cal_list_curr = ah->cal_list;
 910
 911                 if (ah->cal_list_curr)
 912                         ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
 913         }
 914
 915         if (ah->caldata)
 916                 ah->caldata->CalValid = 0;
 917
 918         return true;
 919 }
 920
 921 static const struct ath9k_percal_data iq_cal_multi_sample = {
 922         IQ_MISMATCH_CAL,
 923         MAX_CAL_SAMPLES,
 924         PER_MIN_LOG_COUNT,
 925         ar9002_hw_iqcal_collect,
 926         ar9002_hw_iqcalibrate
 927 };
 928 static const struct ath9k_percal_data iq_cal_single_sample = {
 929         IQ_MISMATCH_CAL,
 930         MIN_CAL_SAMPLES,
 931         PER_MAX_LOG_COUNT,
 932         ar9002_hw_iqcal_collect,
 933         ar9002_hw_iqcalibrate
 934 };
 935 static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
 936         ADC_GAIN_CAL,
 937         MAX_CAL_SAMPLES,
 938         PER_MIN_LOG_COUNT,
 939         ar9002_hw_adc_gaincal_collect,
 940         ar9002_hw_adc_gaincal_calibrate
 941 };
 942 static const struct ath9k_percal_data adc_gain_cal_single_sample = {
 943         ADC_GAIN_CAL,
 944         MIN_CAL_SAMPLES,
 945         PER_MAX_LOG_COUNT,
 946         ar9002_hw_adc_gaincal_collect,
 947         ar9002_hw_adc_gaincal_calibrate
 948 };
 949 static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
 950         ADC_DC_CAL,
 951         MAX_CAL_SAMPLES,
 952         PER_MIN_LOG_COUNT,
 953         ar9002_hw_adc_dccal_collect,
 954         ar9002_hw_adc_dccal_calibrate
 955 };
 956 static const struct ath9k_percal_data adc_dc_cal_single_sample = {
 957         ADC_DC_CAL,
 958         MIN_CAL_SAMPLES,
 959         PER_MAX_LOG_COUNT,
 960         ar9002_hw_adc_dccal_collect,
 961         ar9002_hw_adc_dccal_calibrate
 962 };
 963
 964 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
 965 {
 966         if (AR_SREV_9100(ah)) {
 967                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 968                 ah->supp_cals = IQ_MISMATCH_CAL;
 969                 return;
 970         }
 971
 972         if (AR_SREV_9160_10_OR_LATER(ah)) {
 973                 if (AR_SREV_9280_20_OR_LATER(ah)) {
 974                         ah->iq_caldata.calData = &iq_cal_single_sample;
 975                         ah->adcgain_caldata.calData =
 976                                 &adc_gain_cal_single_sample;
 977                         ah->adcdc_caldata.calData =
 978                                 &adc_dc_cal_single_sample;
 979                 } else {
 980                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 981                         ah->adcgain_caldata.calData =
 982                                 &adc_gain_cal_multi_sample;
 983                         ah->adcdc_caldata.calData =
 984                                 &adc_dc_cal_multi_sample;
 985                 }
 986                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 987
 988                 if (AR_SREV_9287(ah))
 989                         ah->supp_cals &= ~ADC_GAIN_CAL;
 990         }
 991 }
 992
 993 void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
 994 {
 995         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 996         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 997
 998         priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
 999         priv_ops->init_cal = ar9002_hw_init_cal;
1000         priv_ops->setup_calibration = ar9002_hw_setup_calibration;
1001
1002         ops->calibrate = ar9002_hw_calibrate;
1003 }