drivers/net/wireless/ath/ath5k/reset.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
   5  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
   6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
   7  *
   8  * Permission to use, copy, modify, and distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  */
  21
  22 /*****************************\
  23   Reset functions and helpers
  24 \*****************************/
  25
  26 #include <asm/unaligned.h>
  27
  28 #include <linux/pci.h>          /* To determine if a card is pci-e */
  29 #include <linux/log2.h>
  30 #include <linux/platform_device.h>
  31 #include "ath5k.h"
  32 #include "reg.h"
  33 #include "base.h"
  34 #include "debug.h"
  35
  36
  37 /******************\
  38 * Helper functions *
  39 \******************/
  40
  41 /*
  42  * Check if a register write has been completed
  43  */
  44 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
  45                               bool is_set)
  46 {
  47         int i;
  48         u32 data;
  49
  50         for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
  51                 data = ath5k_hw_reg_read(ah, reg);
  52                 if (is_set && (data & flag))
  53                         break;
  54                 else if ((data & flag) == val)
  55                         break;
  56                 udelay(15);
  57         }
  58
  59         return (i <= 0) ? -EAGAIN : 0;
  60 }
  61
  62
  63 /*************************\
  64 * Clock related functions *
  65 \*************************/
  66
  67 /**
  68  * ath5k_hw_htoclock - Translate usec to hw clock units
  69  *
  70  * @ah: The &struct ath5k_hw
  71  * @usec: value in microseconds
  72  */
  73 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
  74 {
  75         struct ath_common *common = ath5k_hw_common(ah);
  76         return usec * common->clockrate;
  77 }
  78
  79 /**
  80  * ath5k_hw_clocktoh - Translate hw clock units to usec
  81  * @clock: value in hw clock units
  82  */
  83 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
  84 {
  85         struct ath_common *common = ath5k_hw_common(ah);
  86         return clock / common->clockrate;
  87 }
  88
  89 /**
  90  * ath5k_hw_init_core_clock - Initialize core clock
  91  *
  92  * @ah The &struct ath5k_hw
  93  *
  94  * Initialize core clock parameters (usec, usec32, latencies etc).
  95  */
  96 static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
  97 {
  98         struct ieee80211_channel *channel = ah->ah_current_channel;
  99         struct ath_common *common = ath5k_hw_common(ah);
 100         u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
 101
 102         /*
 103          * Set core clock frequency
 104          */
 105         if (channel->hw_value & CHANNEL_5GHZ)
 106                 clock = 40; /* 802.11a */
 107         else if (channel->hw_value & CHANNEL_CCK)
 108                 clock = 22; /* 802.11b */
 109         else
 110                 clock = 44; /* 802.11g */
 111
 112         /* Use clock multiplier for non-default
 113          * bwmode */
 114         switch (ah->ah_bwmode) {
 115         case AR5K_BWMODE_40MHZ:
 116                 clock *= 2;
 117                 break;
 118         case AR5K_BWMODE_10MHZ:
 119                 clock /= 2;
 120                 break;
 121         case AR5K_BWMODE_5MHZ:
 122                 clock /= 4;
 123                 break;
 124         default:
 125                 break;
 126         }
 127
 128         common->clockrate = clock;
 129
 130         /*
 131          * Set USEC parameters
 132          */
 133         /* Set USEC counter on PCU*/
 134         usec = clock - 1;
 135         usec = AR5K_REG_SM(usec, AR5K_USEC_1);
 136
 137         /* Set usec duration on DCU */
 138         if (ah->ah_version != AR5K_AR5210)
 139                 AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
 140                                         AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
 141                                         clock);
 142
 143         /* Set 32MHz USEC counter */
 144         if ((ah->ah_radio == AR5K_RF5112) ||
 145             (ah->ah_radio == AR5K_RF2413) ||
 146             (ah->ah_radio == AR5K_RF5413) ||
 147             (ah->ah_radio == AR5K_RF2316) ||
 148             (ah->ah_radio == AR5K_RF2317))
 149                 /* Remain on 40MHz clock ? */
 150                 sclock = 40 - 1;
 151         else
 152                 sclock = 32 - 1;
 153         sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
 154
 155         /*
 156          * Set tx/rx latencies
 157          */
 158         usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
 159         txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
 160         rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
 161
 162         /*
 163          * Set default Tx frame to Tx data start delay
 164          */
 165         txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
 166
 167         /*
 168          * 5210 initvals don't include usec settings
 169          * so we need to use magic values here for
 170          * tx/rx latencies
 171          */
 172         if (ah->ah_version == AR5K_AR5210) {
 173                 /* same for turbo */
 174                 txlat = AR5K_INIT_TX_LATENCY_5210;
 175                 rxlat = AR5K_INIT_RX_LATENCY_5210;
 176         }
 177
 178         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
 179                 /* 5311 has different tx/rx latency masks
 180                  * from 5211, since we deal 5311 the same
 181                  * as 5211 when setting initvals, shift
 182                  * values here to their proper locations
 183                  *
 184                  * Note: Initvals indicate tx/rx/ latencies
 185                  * are the same for turbo mode */
 186                 txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
 187                 rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
 188         } else
 189         switch (ah->ah_bwmode) {
 190         case AR5K_BWMODE_10MHZ:
 191                 txlat = AR5K_REG_SM(txlat * 2,
 192                                 AR5K_USEC_TX_LATENCY_5211);
 193                 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
 194                                 AR5K_USEC_RX_LATENCY_5211);
 195                 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
 196                 break;
 197         case AR5K_BWMODE_5MHZ:
 198                 txlat = AR5K_REG_SM(txlat * 4,
 199                                 AR5K_USEC_TX_LATENCY_5211);
 200                 rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
 201                                 AR5K_USEC_RX_LATENCY_5211);
 202                 txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
 203                 break;
 204         case AR5K_BWMODE_40MHZ:
 205                 txlat = AR5K_INIT_TX_LAT_MIN;
 206                 rxlat = AR5K_REG_SM(rxlat / 2,
 207                                 AR5K_USEC_RX_LATENCY_5211);
 208                 txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
 209                 break;
 210         default:
 211                 break;
 212         }
 213
 214         usec_reg = (usec | sclock | txlat | rxlat);
 215         ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
 216
 217         /* On 5112 set tx frame to tx data start delay */
 218         if (ah->ah_radio == AR5K_RF5112) {
 219                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
 220                                         AR5K_PHY_RF_CTL2_TXF2TXD_START,
 221                                         txf2txs);
 222         }
 223 }
 224
 225 /*
 226  * If there is an external 32KHz crystal available, use it
 227  * as ref. clock instead of 32/40MHz clock and baseband clocks
 228  * to save power during sleep or restore normal 32/40MHz
 229  * operation.
 230  *
 231  * XXX: When operating on 32KHz certain PHY registers (27 - 31,
 232  *      123 - 127) require delay on access.
 233  */
 234 static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
 235 {
 236         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 237         u32 scal, spending, sclock;
 238
 239         /* Only set 32KHz settings if we have an external
 240          * 32KHz crystal present */
 241         if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
 242         AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
 243         enable) {
 244
 245                 /* 1 usec/cycle */
 246                 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
 247                 /* Set up tsf increment on each cycle */
 248                 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
 249
 250                 /* Set baseband sleep control registers
 251                  * and sleep control rate */
 252                 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
 253
 254                 if ((ah->ah_radio == AR5K_RF5112) ||
 255                 (ah->ah_radio == AR5K_RF5413) ||
 256                 (ah->ah_radio == AR5K_RF2316) ||
 257                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
 258                         spending = 0x14;
 259                 else
 260                         spending = 0x18;
 261                 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
 262
 263                 if ((ah->ah_radio == AR5K_RF5112) ||
 264                 (ah->ah_radio == AR5K_RF5413) ||
 265                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
 266                         ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
 267                         ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
 268                         ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
 269                         ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
 270                         AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 271                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
 272                 } else {
 273                         ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
 274                         ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
 275                         ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
 276                         ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
 277                         AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 278                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
 279                 }
 280
 281                 /* Enable sleep clock operation */
 282                 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
 283                                 AR5K_PCICFG_SLEEP_CLOCK_EN);
 284
 285         } else {
 286
 287                 /* Disable sleep clock operation and
 288                  * restore default parameters */
 289                 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
 290                                 AR5K_PCICFG_SLEEP_CLOCK_EN);
 291
 292                 AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
 293                                 AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
 294
 295                 /* Set DAC/ADC delays */
 296                 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
 297                 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
 298
 299                 if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
 300                         scal = AR5K_PHY_SCAL_32MHZ_2417;
 301                 else if (ee->ee_is_hb63)
 302                         scal = AR5K_PHY_SCAL_32MHZ_HB63;
 303                 else
 304                         scal = AR5K_PHY_SCAL_32MHZ;
 305                 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
 306
 307                 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
 308                 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
 309
 310                 if ((ah->ah_radio == AR5K_RF5112) ||
 311                 (ah->ah_radio == AR5K_RF5413) ||
 312                 (ah->ah_radio == AR5K_RF2316) ||
 313                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
 314                         spending = 0x14;
 315                 else
 316                         spending = 0x18;
 317                 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
 318
 319                 /* Set up tsf increment on each cycle */
 320                 AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
 321
 322                 if ((ah->ah_radio == AR5K_RF5112) ||
 323                         (ah->ah_radio == AR5K_RF5413) ||
 324                         (ah->ah_radio == AR5K_RF2316) ||
 325                         (ah->ah_radio == AR5K_RF2317))
 326                         sclock = 40 - 1;
 327                 else
 328                         sclock = 32 - 1;
 329                 AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);
 330         }
 331 }
 332
 333
 334 /*********************\
 335 * Reset/Sleep control *
 336 \*********************/
 337
 338 /*
 339  * Reset chipset
 340  */
 341 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
 342 {
 343         int ret;
 344         u32 mask = val ? val : ~0U;
 345
 346         /* Read-and-clear RX Descriptor Pointer*/
 347         ath5k_hw_reg_read(ah, AR5K_RXDP);
 348
 349         /*
 350          * Reset the device and wait until success
 351          */
 352         ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
 353
 354         /* Wait at least 128 PCI clocks */
 355         udelay(15);
 356
 357         if (ah->ah_version == AR5K_AR5210) {
 358                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
 359                         | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
 360                 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
 361                         | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
 362         } else {
 363                 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
 364                 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
 365         }
 366
 367         ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
 368
 369         /*
 370          * Reset configuration register (for hw byte-swap). Note that this
 371          * is only set for big endian. We do the necessary magic in
 372          * AR5K_INIT_CFG.
 373          */
 374         if ((val & AR5K_RESET_CTL_PCU) == 0)
 375                 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
 376
 377         return ret;
 378 }
 379
 380 /*
 381  * Reset AHB chipset
 382  * AR5K_RESET_CTL_PCU flag resets WMAC
 383  * AR5K_RESET_CTL_BASEBAND flag resets WBB
 384  */
 385 static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
 386 {
 387         u32 mask = flags ? flags : ~0U;
 388         u32 __iomem *reg;
 389         u32 regval;
 390         u32 val = 0;
 391
 392         /* ah->ah_mac_srev is not available at this point yet */
 393         if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
 394                 reg = (u32 __iomem *) AR5K_AR2315_RESET;
 395                 if (mask & AR5K_RESET_CTL_PCU)
 396                         val |= AR5K_AR2315_RESET_WMAC;
 397                 if (mask & AR5K_RESET_CTL_BASEBAND)
 398                         val |= AR5K_AR2315_RESET_BB_WARM;
 399         } else {
 400                 reg = (u32 __iomem *) AR5K_AR5312_RESET;
 401                 if (to_platform_device(ah->ah_sc->dev)->id == 0) {
 402                         if (mask & AR5K_RESET_CTL_PCU)
 403                                 val |= AR5K_AR5312_RESET_WMAC0;
 404                         if (mask & AR5K_RESET_CTL_BASEBAND)
 405                                 val |= AR5K_AR5312_RESET_BB0_COLD |
 406                                        AR5K_AR5312_RESET_BB0_WARM;
 407                 } else {
 408                         if (mask & AR5K_RESET_CTL_PCU)
 409                                 val |= AR5K_AR5312_RESET_WMAC1;
 410                         if (mask & AR5K_RESET_CTL_BASEBAND)
 411                                 val |= AR5K_AR5312_RESET_BB1_COLD |
 412                                        AR5K_AR5312_RESET_BB1_WARM;
 413                 }
 414         }
 415
 416         /* Put BB/MAC into reset */
 417         regval = __raw_readl(reg);
 418         __raw_writel(regval | val, reg);
 419         regval = __raw_readl(reg);
 420         udelay(100);
 421
 422         /* Bring BB/MAC out of reset */
 423         __raw_writel(regval & ~val, reg);
 424         regval = __raw_readl(reg);
 425
 426         /*
 427          * Reset configuration register (for hw byte-swap). Note that this
 428          * is only set for big endian. We do the necessary magic in
 429          * AR5K_INIT_CFG.
 430          */
 431         if ((flags & AR5K_RESET_CTL_PCU) == 0)
 432                 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
 433
 434         return 0;
 435 }
 436
 437
 438 /*
 439  * Sleep control
 440  */
 441 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
 442                               bool set_chip, u16 sleep_duration)
 443 {
 444         unsigned int i;
 445         u32 staid, data;
 446
 447         staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
 448
 449         switch (mode) {
 450         case AR5K_PM_AUTO:
 451                 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
 452                 /* fallthrough */
 453         case AR5K_PM_NETWORK_SLEEP:
 454                 if (set_chip)
 455                         ath5k_hw_reg_write(ah,
 456                                 AR5K_SLEEP_CTL_SLE_ALLOW |
 457                                 sleep_duration,
 458                                 AR5K_SLEEP_CTL);
 459
 460                 staid |= AR5K_STA_ID1_PWR_SV;
 461                 break;
 462
 463         case AR5K_PM_FULL_SLEEP:
 464                 if (set_chip)
 465                         ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
 466                                 AR5K_SLEEP_CTL);
 467
 468                 staid |= AR5K_STA_ID1_PWR_SV;
 469                 break;
 470
 471         case AR5K_PM_AWAKE:
 472
 473                 staid &= ~AR5K_STA_ID1_PWR_SV;
 474
 475                 if (!set_chip)
 476                         goto commit;
 477
 478                 data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
 479
 480                 /* If card is down we 'll get 0xffff... so we
 481                  * need to clean this up before we write the register
 482                  */
 483                 if (data & 0xffc00000)
 484                         data = 0;
 485                 else
 486                         /* Preserve sleep duration etc */
 487                         data = data & ~AR5K_SLEEP_CTL_SLE;
 488
 489                 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
 490                                                         AR5K_SLEEP_CTL);
 491                 udelay(15);
 492
 493                 for (i = 200; i > 0; i--) {
 494                         /* Check if the chip did wake up */
 495                         if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
 496                                         AR5K_PCICFG_SPWR_DN) == 0)
 497                                 break;
 498
 499                         /* Wait a bit and retry */
 500                         udelay(50);
 501                         ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
 502                                                         AR5K_SLEEP_CTL);
 503                 }
 504
 505                 /* Fail if the chip didn't wake up */
 506                 if (i == 0)
 507                         return -EIO;
 508
 509                 break;
 510
 511         default:
 512                 return -EINVAL;
 513         }
 514
 515 commit:
 516         ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
 517
 518         return 0;
 519 }
 520
 521 /*
 522  * Put device on hold
 523  *
 524  * Put MAC and Baseband on warm reset and
 525  * keep that state (don't clean sleep control
 526  * register). After this MAC and Baseband are
 527  * disabled and a full reset is needed to come
 528  * back. This way we save as much power as possible
 529  * without putting the card on full sleep.
 530  */
 531 int ath5k_hw_on_hold(struct ath5k_hw *ah)
 532 {
 533         struct pci_dev *pdev = ah->ah_sc->pdev;
 534         u32 bus_flags;
 535         int ret;
 536
 537         if (ath5k_get_bus_type(ah) == ATH_AHB)
 538                 return 0;
 539
 540         /* Make sure device is awake */
 541         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 542         if (ret) {
 543                 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
 544                 return ret;
 545         }
 546
 547         /*
 548          * Put chipset on warm reset...
 549          *
 550          * Note: putting PCI core on warm reset on PCI-E cards
 551          * results card to hang and always return 0xffff... so
 552          * we ignore that flag for PCI-E cards. On PCI cards
 553          * this flag gets cleared after 64 PCI clocks.
 554          */
 555         bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
 556
 557         if (ah->ah_version == AR5K_AR5210) {
 558                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 559                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
 560                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
 561                         mdelay(2);
 562         } else {
 563                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 564                         AR5K_RESET_CTL_BASEBAND | bus_flags);
 565         }
 566
 567         if (ret) {
 568                 ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
 569                 return -EIO;
 570         }
 571
 572         /* ...wakeup again!*/
 573         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 574         if (ret) {
 575                 ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
 576                 return ret;
 577         }
 578
 579         return ret;
 580 }
 581
 582 /*
 583  * Bring up MAC + PHY Chips and program PLL
 584  */
 585 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
 586 {
 587         struct pci_dev *pdev = ah->ah_sc->pdev;
 588         u32 turbo, mode, clock, bus_flags;
 589         int ret;
 590
 591         turbo = 0;
 592         mode = 0;
 593         clock = 0;
 594
 595         if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
 596                 /* Wakeup the device */
 597                 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 598                 if (ret) {
 599                         ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
 600                         return ret;
 601                 }
 602         }
 603
 604         /*
 605          * Put chipset on warm reset...
 606          *
 607          * Note: putting PCI core on warm reset on PCI-E cards
 608          * results card to hang and always return 0xffff... so
 609          * we ignore that flag for PCI-E cards. On PCI cards
 610          * this flag gets cleared after 64 PCI clocks.
 611          */
 612         bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
 613
 614         if (ah->ah_version == AR5K_AR5210) {
 615                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 616                         AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
 617                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
 618                         mdelay(2);
 619         } else {
 620                 if (ath5k_get_bus_type(ah) == ATH_AHB)
 621                         ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
 622                                 AR5K_RESET_CTL_BASEBAND);
 623                 else
 624                         ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
 625                                 AR5K_RESET_CTL_BASEBAND | bus_flags);
 626         }
 627
 628         if (ret) {
 629                 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
 630                 return -EIO;
 631         }
 632
 633         /* ...wakeup again!...*/
 634         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
 635         if (ret) {
 636                 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
 637                 return ret;
 638         }
 639
 640         /* ...reset configuration register on Wisoc ...
 641          * ...clear reset control register and pull device out of
 642          * warm reset on others */
 643         if (ath5k_get_bus_type(ah) == ATH_AHB)
 644                 ret = ath5k_hw_wisoc_reset(ah, 0);
 645         else
 646                 ret = ath5k_hw_nic_reset(ah, 0);
 647
 648         if (ret) {
 649                 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
 650                 return -EIO;
 651         }
 652
 653         /* On initialization skip PLL programming since we don't have
 654          * a channel / mode set yet */
 655         if (initial)
 656                 return 0;
 657
 658         if (ah->ah_version != AR5K_AR5210) {
 659                 /*
 660                  * Get channel mode flags
 661                  */
 662
 663                 if (ah->ah_radio >= AR5K_RF5112) {
 664                         mode = AR5K_PHY_MODE_RAD_RF5112;
 665                         clock = AR5K_PHY_PLL_RF5112;
 666                 } else {
 667                         mode = AR5K_PHY_MODE_RAD_RF5111;        /*Zero*/
 668                         clock = AR5K_PHY_PLL_RF5111;            /*Zero*/
 669                 }
 670
 671                 if (flags & CHANNEL_2GHZ) {
 672                         mode |= AR5K_PHY_MODE_FREQ_2GHZ;
 673                         clock |= AR5K_PHY_PLL_44MHZ;
 674
 675                         if (flags & CHANNEL_CCK) {
 676                                 mode |= AR5K_PHY_MODE_MOD_CCK;
 677                         } else if (flags & CHANNEL_OFDM) {
 678                                 /* XXX Dynamic OFDM/CCK is not supported by the
 679                                  * AR5211 so we set MOD_OFDM for plain g (no
 680                                  * CCK headers) operation. We need to test
 681                                  * this, 5211 might support ofdm-only g after
 682                                  * all, there are also initial register values
 683                                  * in the code for g mode (see initvals.c).
 684                                  */
 685                                 if (ah->ah_version == AR5K_AR5211)
 686                                         mode |= AR5K_PHY_MODE_MOD_OFDM;
 687                                 else
 688                                         mode |= AR5K_PHY_MODE_MOD_DYN;
 689                         } else {
 690                                 ATH5K_ERR(ah->ah_sc,
 691                                         "invalid radio modulation mode\n");
 692                                 return -EINVAL;
 693                         }
 694                 } else if (flags & CHANNEL_5GHZ) {
 695                         mode |= AR5K_PHY_MODE_FREQ_5GHZ;
 696
 697                         /* Different PLL setting for 5413 */
 698                         if (ah->ah_radio == AR5K_RF5413)
 699                                 clock = AR5K_PHY_PLL_40MHZ_5413;
 700                         else
 701                                 clock |= AR5K_PHY_PLL_40MHZ;
 702
 703                         if (flags & CHANNEL_OFDM)
 704                                 mode |= AR5K_PHY_MODE_MOD_OFDM;
 705                         else {
 706                                 ATH5K_ERR(ah->ah_sc,
 707                                         "invalid radio modulation mode\n");
 708                                 return -EINVAL;
 709                         }
 710                 } else {
 711                         ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
 712                         return -EINVAL;
 713                 }
 714
 715                 /*XXX: Can bwmode be used with dynamic mode ?
 716                  * (I don't think it supports 44MHz) */
 717                 /* On 2425 initvals TURBO_SHORT is not present */
 718                 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
 719                         turbo = AR5K_PHY_TURBO_MODE |
 720                                 (ah->ah_radio == AR5K_RF2425) ? 0 :
 721                                 AR5K_PHY_TURBO_SHORT;
 722                 } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
 723                         if (ah->ah_radio == AR5K_RF5413) {
 724                                 mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
 725                                         AR5K_PHY_MODE_HALF_RATE :
 726                                         AR5K_PHY_MODE_QUARTER_RATE;
 727                         } else if (ah->ah_version == AR5K_AR5212) {
 728                                 clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
 729                                         AR5K_PHY_PLL_HALF_RATE :
 730                                         AR5K_PHY_PLL_QUARTER_RATE;
 731                         }
 732                 }
 733
 734         } else { /* Reset the device */
 735
 736                 /* ...enable Atheros turbo mode if requested */
 737                 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
 738                         ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
 739                                         AR5K_PHY_TURBO);
 740         }
 741
 742         if (ah->ah_version != AR5K_AR5210) {
 743
 744                 /* ...update PLL if needed */
 745                 if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {
 746                         ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
 747                         udelay(300);
 748                 }
 749
 750                 /* ...set the PHY operating mode */
 751                 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
 752                 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
 753         }
 754
 755         return 0;
 756 }
 757
 758
 759 /**************************************\
 760 * Post-initvals register modifications *
 761 \**************************************/
 762
 763 /* TODO: Half/Quarter rate */
 764 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
 765                                 struct ieee80211_channel *channel)
 766 {
 767         if (ah->ah_version == AR5K_AR5212 &&
 768             ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 769
 770                 /* Setup ADC control */
 771                 ath5k_hw_reg_write(ah,
 772                                 (AR5K_REG_SM(2,
 773                                 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF) |
 774                                 AR5K_REG_SM(2,
 775                                 AR5K_PHY_ADC_CTL_INBUFGAIN_ON) |
 776                                 AR5K_PHY_ADC_CTL_PWD_DAC_OFF |
 777                                 AR5K_PHY_ADC_CTL_PWD_ADC_OFF),
 778                                 AR5K_PHY_ADC_CTL);
 779
 780
 781
 782                 /* Disable barker RSSI threshold */
 783                 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
 784                                 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR);
 785
 786                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,
 787                         AR5K_PHY_DAG_CCK_CTL_RSSI_THR, 2);
 788
 789                 /* Set the mute mask */
 790                 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);
 791         }
 792
 793         /* Clear PHY_BLUETOOTH to allow RX_CLEAR line debug */
 794         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)
 795                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);
 796
 797         /* Enable DCU double buffering */
 798         if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)
 799                 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
 800                                 AR5K_TXCFG_DCU_DBL_BUF_DIS);
 801
 802         /* Set fast ADC */
 803         if ((ah->ah_radio == AR5K_RF5413) ||
 804                 (ah->ah_radio == AR5K_RF2317) ||
 805                 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
 806                 u32 fast_adc = true;
 807
 808                 if (channel->center_freq == 2462 ||
 809                 channel->center_freq == 2467)
 810                         fast_adc = 0;
 811
 812                 /* Only update if needed */
 813                 if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)
 814                                 ath5k_hw_reg_write(ah, fast_adc,
 815                                                 AR5K_PHY_FAST_ADC);
 816         }
 817
 818         /* Fix for first revision of the RF5112 RF chipset */
 819         if (ah->ah_radio == AR5K_RF5112 &&
 820                         ah->ah_radio_5ghz_revision <
 821                         AR5K_SREV_RAD_5112A) {
 822                 u32 data;
 823                 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
 824                                 AR5K_PHY_CCKTXCTL);
 825                 if (channel->hw_value & CHANNEL_5GHZ)
 826                         data = 0xffb81020;
 827                 else
 828                         data = 0xffb80d20;
 829                 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
 830         }
 831
 832         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
 833                 /* Clear QCU/DCU clock gating register */
 834                 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
 835                 /* Set DAC/ADC delays */
 836                 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
 837                                                 AR5K_PHY_SCAL);
 838                 /* Enable PCU FIFO corruption ECO */
 839                 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
 840                                         AR5K_DIAG_SW_ECO_ENABLE);
 841         }
 842
 843         if (ah->ah_bwmode) {
 844                 /* Increase PHY switch and AGC settling time
 845                  * on turbo mode (ath5k_hw_commit_eeprom_settings
 846                  * will override settling time if available) */
 847                 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
 848
 849                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 850                                                 AR5K_PHY_SETTLING_AGC,
 851                                                 AR5K_AGC_SETTLING_TURBO);
 852
 853                         /* XXX: Initvals indicate we only increase
 854                          * switch time on AR5212, 5211 and 5210
 855                          * only change agc time (bug?) */
 856                         if (ah->ah_version == AR5K_AR5212)
 857                                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 858                                                 AR5K_PHY_SETTLING_SWITCH,
 859                                                 AR5K_SWITCH_SETTLING_TURBO);
 860
 861                         if (ah->ah_version == AR5K_AR5210) {
 862                                 /* Set Frame Control Register */
 863                                 ath5k_hw_reg_write(ah,
 864                                         (AR5K_PHY_FRAME_CTL_INI |
 865                                         AR5K_PHY_TURBO_MODE |
 866                                         AR5K_PHY_TURBO_SHORT | 0x2020),
 867                                         AR5K_PHY_FRAME_CTL_5210);
 868                         }
 869                 /* On 5413 PHY force window length for half/quarter rate*/
 870                 } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
 871                 (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
 872                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
 873                                                 AR5K_PHY_FRAME_CTL_WIN_LEN,
 874                                                 3);
 875                 }
 876         } else if (ah->ah_version == AR5K_AR5210) {
 877                 /* Set Frame Control Register for normal operation */
 878                 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
 879                                                 AR5K_PHY_FRAME_CTL_5210);
 880         }
 881 }
 882
 883 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
 884                 struct ieee80211_channel *channel)
 885 {
 886         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 887         s16 cck_ofdm_pwr_delta;
 888         u8 ee_mode;
 889
 890         /* TODO: Add support for AR5210 EEPROM */
 891         if (ah->ah_version == AR5K_AR5210)
 892                 return;
 893
 894         ee_mode = ath5k_eeprom_mode_from_channel(channel);
 895
 896         /* Adjust power delta for channel 14 */
 897         if (channel->center_freq == 2484)
 898                 cck_ofdm_pwr_delta =
 899                         ((ee->ee_cck_ofdm_power_delta -
 900                         ee->ee_scaled_cck_delta) * 2) / 10;
 901         else
 902                 cck_ofdm_pwr_delta =
 903                         (ee->ee_cck_ofdm_power_delta * 2) / 10;
 904
 905         /* Set CCK to OFDM power delta on tx power
 906          * adjustment register */
 907         if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
 908                 if (channel->hw_value == CHANNEL_G)
 909                         ath5k_hw_reg_write(ah,
 910                         AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),
 911                                 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA) |
 912                         AR5K_REG_SM((cck_ofdm_pwr_delta * -1),
 913                                 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX),
 914                                 AR5K_PHY_TX_PWR_ADJ);
 915                 else
 916                         ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);
 917         } else {
 918                 /* For older revs we scale power on sw during tx power
 919                  * setup */
 920                 ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;
 921                 ah->ah_txpower.txp_cck_ofdm_gainf_delta =
 922                                                 ee->ee_cck_ofdm_gain_delta;
 923         }
 924
 925         /* XXX: necessary here? is called from ath5k_hw_set_antenna_mode()
 926          * too */
 927         ath5k_hw_set_antenna_switch(ah, ee_mode);
 928
 929         /* Noise floor threshold */
 930         ath5k_hw_reg_write(ah,
 931                 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
 932                 AR5K_PHY_NFTHRES);
 933
 934         if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
 935         (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
 936                 /* Switch settling time (Turbo) */
 937                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 938                                 AR5K_PHY_SETTLING_SWITCH,
 939                                 ee->ee_switch_settling_turbo[ee_mode]);
 940
 941                 /* Tx/Rx attenuation (Turbo) */
 942                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
 943                                 AR5K_PHY_GAIN_TXRX_ATTEN,
 944                                 ee->ee_atn_tx_rx_turbo[ee_mode]);
 945
 946                 /* ADC/PGA desired size (Turbo) */
 947                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 948                                 AR5K_PHY_DESIRED_SIZE_ADC,
 949                                 ee->ee_adc_desired_size_turbo[ee_mode]);
 950
 951                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 952                                 AR5K_PHY_DESIRED_SIZE_PGA,
 953                                 ee->ee_pga_desired_size_turbo[ee_mode]);
 954
 955                 /* Tx/Rx margin (Turbo) */
 956                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
 957                                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
 958                                 ee->ee_margin_tx_rx_turbo[ee_mode]);
 959
 960         } else {
 961                 /* Switch settling time */
 962                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
 963                                 AR5K_PHY_SETTLING_SWITCH,
 964                                 ee->ee_switch_settling[ee_mode]);
 965
 966                 /* Tx/Rx attenuation */
 967                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,
 968                                 AR5K_PHY_GAIN_TXRX_ATTEN,
 969                                 ee->ee_atn_tx_rx[ee_mode]);
 970
 971                 /* ADC/PGA desired size */
 972                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 973                                 AR5K_PHY_DESIRED_SIZE_ADC,
 974                                 ee->ee_adc_desired_size[ee_mode]);
 975
 976                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,
 977                                 AR5K_PHY_DESIRED_SIZE_PGA,
 978                                 ee->ee_pga_desired_size[ee_mode]);
 979
 980                 /* Tx/Rx margin */
 981                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 982                         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
 983                                 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
 984                                 ee->ee_margin_tx_rx[ee_mode]);
 985         }
 986
 987         /* XPA delays */
 988         ath5k_hw_reg_write(ah,
 989                 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
 990                 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
 991                 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
 992                 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);
 993
 994         /* XLNA delay */
 995         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,
 996                         AR5K_PHY_RF_CTL3_TXE2XLNA_ON,
 997                         ee->ee_tx_end2xlna_enable[ee_mode]);
 998
 999         /* Thresh64 (ANI) */
1000         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,
1001                         AR5K_PHY_NF_THRESH62,
1002                         ee->ee_thr_62[ee_mode]);
1003
1004         /* False detect backoff for channels
1005          * that have spur noise. Write the new
1006          * cyclic power RSSI threshold. */
1007         if (ath5k_hw_chan_has_spur_noise(ah, channel))
1008                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1009                                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1010                                 AR5K_INIT_CYCRSSI_THR1 +
1011                                 ee->ee_false_detect[ee_mode]);
1012         else
1013                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,
1014                                 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1,
1015                                 AR5K_INIT_CYCRSSI_THR1);
1016
1017         /* I/Q correction (set enable bit last to match HAL sources) */
1018         /* TODO: Per channel i/q infos ? */
1019         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1020                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,
1021                             ee->ee_i_cal[ee_mode]);
1022                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,
1023                             ee->ee_q_cal[ee_mode]);
1024                 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1025         }
1026
1027         /* Heavy clipping -disable for now */
1028         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)
1029                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
1030 }
1031
1032
1033 /*********************\
1034 * Main reset function *
1035 \*********************/
1036
1037 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1038                 struct ieee80211_channel *channel, bool fast, bool skip_pcu)
1039 {
1040         u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
1041         u8 mode;
1042         int i, ret;
1043
1044         tsf_up = 0;
1045         tsf_lo = 0;
1046         mode = 0;
1047
1048         /*
1049          * Sanity check for fast flag
1050          * Fast channel change only available
1051          * on AR2413/AR5413.
1052          */
1053         if (fast && (ah->ah_radio != AR5K_RF2413) &&
1054         (ah->ah_radio != AR5K_RF5413))
1055                 fast = 0;
1056
1057         /* Disable sleep clock operation
1058          * to avoid register access delay on certain
1059          * PHY registers */
1060         if (ah->ah_version == AR5K_AR5212)
1061                 ath5k_hw_set_sleep_clock(ah, false);
1062
1063         /*
1064          * Stop PCU
1065          */
1066         ath5k_hw_stop_rx_pcu(ah);
1067
1068         /*
1069          * Stop DMA
1070          *
1071          * Note: If DMA didn't stop continue
1072          * since only a reset will fix it.
1073          */
1074         ret = ath5k_hw_dma_stop(ah);
1075
1076         /* RF Bus grant won't work if we have pending
1077          * frames */
1078         if (ret && fast) {
1079                 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1080                         "DMA didn't stop, falling back to normal reset\n");
1081                 fast = 0;
1082                 /* Non fatal, just continue with
1083                  * normal reset */
1084                 ret = 0;
1085         }
1086
1087         switch (channel->hw_value & CHANNEL_MODES) {
1088         case CHANNEL_A:
1089                 mode = AR5K_MODE_11A;
1090                 break;
1091         case CHANNEL_G:
1092
1093                 if (ah->ah_version <= AR5K_AR5211) {
1094                         ATH5K_ERR(ah->ah_sc,
1095                                 "G mode not available on 5210/5211");
1096                         return -EINVAL;
1097                 }
1098
1099                 mode = AR5K_MODE_11G;
1100                 break;
1101         case CHANNEL_B:
1102
1103                 if (ah->ah_version < AR5K_AR5211) {
1104                         ATH5K_ERR(ah->ah_sc,
1105                                 "B mode not available on 5210");
1106                         return -EINVAL;
1107                 }
1108
1109                 mode = AR5K_MODE_11B;
1110                 break;
1111         case CHANNEL_XR:
1112                 if (ah->ah_version == AR5K_AR5211) {
1113                         ATH5K_ERR(ah->ah_sc,
1114                                 "XR mode not available on 5211");
1115                         return -EINVAL;
1116                 }
1117                 mode = AR5K_MODE_XR;
1118                 break;
1119         default:
1120                 ATH5K_ERR(ah->ah_sc,
1121                         "invalid channel: %d\n", channel->center_freq);
1122                 return -EINVAL;
1123         }
1124
1125         /*
1126          * If driver requested fast channel change and DMA has stopped
1127          * go on. If it fails continue with a normal reset.
1128          */
1129         if (fast) {
1130                 ret = ath5k_hw_phy_init(ah, channel, mode, true);
1131                 if (ret) {
1132                         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1133                                 "fast chan change failed, falling back to normal reset\n");
1134                         /* Non fatal, can happen eg.
1135                          * on mode change */
1136                         ret = 0;
1137                 } else {
1138                         ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
1139                                 "fast chan change successful\n");
1140                         return 0;
1141                 }
1142         }
1143
1144         /*
1145          * Save some registers before a reset
1146          */
1147         if (ah->ah_version != AR5K_AR5210) {
1148                 /*
1149                  * Save frame sequence count
1150                  * For revs. after Oahu, only save
1151                  * seq num for DCU 0 (Global seq num)
1152                  */
1153                 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1154
1155                         for (i = 0; i < 10; i++)
1156                                 s_seq[i] = ath5k_hw_reg_read(ah,
1157                                         AR5K_QUEUE_DCU_SEQNUM(i));
1158
1159                 } else {
1160                         s_seq[0] = ath5k_hw_reg_read(ah,
1161                                         AR5K_QUEUE_DCU_SEQNUM(0));
1162                 }
1163
1164                 /* TSF accelerates on AR5211 during reset
1165                  * As a workaround save it here and restore
1166                  * it later so that it's back in time after
1167                  * reset. This way it'll get re-synced on the
1168                  * next beacon without breaking ad-hoc.
1169                  *
1170                  * On AR5212 TSF is almost preserved across a
1171                  * reset so it stays back in time anyway and
1172                  * we don't have to save/restore it.
1173                  *
1174                  * XXX: Since this breaks power saving we have
1175                  * to disable power saving until we receive the
1176                  * next beacon, so we can resync beacon timers */
1177                 if (ah->ah_version == AR5K_AR5211) {
1178                         tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
1179                         tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
1180                 }
1181         }
1182
1183
1184         /*GPIOs*/
1185         s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1186                                         AR5K_PCICFG_LEDSTATE;
1187         s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
1188         s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
1189
1190
1191         /*
1192          * Since we are going to write rf buffer
1193          * check if we have any pending gain_F
1194          * optimization settings
1195          */
1196         if (ah->ah_version == AR5K_AR5212 &&
1197         (ah->ah_radio <= AR5K_RF5112)) {
1198                 if (!fast && ah->ah_rf_banks != NULL)
1199                                 ath5k_hw_gainf_calibrate(ah);
1200         }
1201
1202         /* Wakeup the device */
1203         ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
1204         if (ret)
1205                 return ret;
1206
1207         /* PHY access enable */
1208         if (ah->ah_mac_srev >= AR5K_SREV_AR5211)
1209                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1210         else
1211                 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,
1212                                                         AR5K_PHY(0));
1213
1214         /* Write initial settings */
1215         ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
1216         if (ret)
1217                 return ret;
1218
1219         /* Initialize core clock settings */
1220         ath5k_hw_init_core_clock(ah);
1221
1222         /*
1223          * Tweak initval settings for revised
1224          * chipsets and add some more config
1225          * bits
1226          */
1227         ath5k_hw_tweak_initval_settings(ah, channel);
1228
1229         /* Commit values from EEPROM */
1230         ath5k_hw_commit_eeprom_settings(ah, channel);
1231
1232
1233         /*
1234          * Restore saved values
1235          */
1236
1237         /* Seqnum, TSF */
1238         if (ah->ah_version != AR5K_AR5210) {
1239                 if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
1240                         for (i = 0; i < 10; i++)
1241                                 ath5k_hw_reg_write(ah, s_seq[i],
1242                                         AR5K_QUEUE_DCU_SEQNUM(i));
1243                 } else {
1244                         ath5k_hw_reg_write(ah, s_seq[0],
1245                                 AR5K_QUEUE_DCU_SEQNUM(0));
1246                 }
1247
1248                 if (ah->ah_version == AR5K_AR5211) {
1249                         ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
1250                         ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
1251                 }
1252         }
1253
1254         /* Ledstate */
1255         AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1256
1257         /* Gpio settings */
1258         ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1259         ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1260
1261         /*
1262          * Initialize PCU
1263          */
1264         ath5k_hw_pcu_init(ah, op_mode, mode);
1265
1266         /*
1267          * Initialize PHY
1268          */
1269         ret = ath5k_hw_phy_init(ah, channel, mode, false);
1270         if (ret) {
1271                 ATH5K_ERR(ah->ah_sc,
1272                         "failed to initialize PHY (%i) !\n", ret);
1273                 return ret;
1274         }
1275
1276         /*
1277          * Configure QCUs/DCUs
1278          */
1279         ret = ath5k_hw_init_queues(ah);
1280         if (ret)
1281                 return ret;
1282
1283
1284         /*
1285          * Initialize DMA/Interrupts
1286          */
1287         ath5k_hw_dma_init(ah);
1288
1289
1290         /*
1291          * Enable 32KHz clock function for AR5212+ chips
1292          * Set clocks to 32KHz operation and use an
1293          * external 32KHz crystal when sleeping if one
1294          * exists.
1295          * Disabled by default because it is also disabled in
1296          * other drivers and it is known to cause stability
1297          * issues on some devices
1298          */
1299         if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&
1300             op_mode != NL80211_IFTYPE_AP)
1301                 ath5k_hw_set_sleep_clock(ah, true);
1302
1303         /*
1304          * Disable beacons and reset the TSF
1305          */
1306         AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
1307         ath5k_hw_reset_tsf(ah);
1308         return 0;
1309 }