drivers/net/wireless/ath/ath5k/eeprom.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 /*************************************\
  21 * EEPROM access functions and helpers *
  22 \*************************************/
  23
  24 #include "ath5k.h"
  25 #include "reg.h"
  26 #include "debug.h"
  27 #include "base.h"
  28
  29 /*
  30  * Read from eeprom
  31  */
  32 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
  33 {
  34         u32 status, timeout;
  35
  36         ATH5K_TRACE(ah->ah_sc);
  37         /*
  38          * Initialize EEPROM access
  39          */
  40         if (ah->ah_version == AR5K_AR5210) {
  41                 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
  42                 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
  43         } else {
  44                 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
  45                 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
  46                                 AR5K_EEPROM_CMD_READ);
  47         }
  48
  49         for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
  50                 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
  51                 if (status & AR5K_EEPROM_STAT_RDDONE) {
  52                         if (status & AR5K_EEPROM_STAT_RDERR)
  53                                 return -EIO;
  54                         *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
  55                                         0xffff);
  56                         return 0;
  57                 }
  58                 udelay(15);
  59         }
  60
  61         return -ETIMEDOUT;
  62 }
  63
  64 /*
  65  * Translate binary channel representation in EEPROM to frequency
  66  */
  67 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
  68                                  unsigned int mode)
  69 {
  70         u16 val;
  71
  72         if (bin == AR5K_EEPROM_CHANNEL_DIS)
  73                 return bin;
  74
  75         if (mode == AR5K_EEPROM_MODE_11A) {
  76                 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
  77                         val = (5 * bin) + 4800;
  78                 else
  79                         val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
  80                                 (bin * 10) + 5100;
  81         } else {
  82                 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
  83                         val = bin + 2300;
  84                 else
  85                         val = bin + 2400;
  86         }
  87
  88         return val;
  89 }
  90
  91 /*
  92  * Initialize eeprom & capabilities structs
  93  */
  94 static int
  95 ath5k_eeprom_init_header(struct ath5k_hw *ah)
  96 {
  97         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  98         int ret;
  99         u16 val;
 100
 101         /*
 102          * Read values from EEPROM and store them in the capability structure
 103          */
 104         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
 105         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
 106         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
 107         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
 108         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
 109
 110         /* Return if we have an old EEPROM */
 111         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
 112                 return 0;
 113
 114 #ifdef notyet
 115         /*
 116          * Validate the checksum of the EEPROM date. There are some
 117          * devices with invalid EEPROMs.
 118          */
 119         for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
 120                 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
 121                 cksum ^= val;
 122         }
 123         if (cksum != AR5K_EEPROM_INFO_CKSUM) {
 124                 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
 125                 return -EIO;
 126         }
 127 #endif
 128
 129         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
 130             ee_ant_gain);
 131
 132         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
 133                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
 134                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
 135
 136                 /* XXX: Don't know which versions include these two */
 137                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
 138
 139                 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
 140                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
 141
 142                 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
 143                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
 144                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
 145                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
 146                 }
 147         }
 148
 149         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
 150                 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
 151                 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
 152                 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
 153
 154                 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
 155                 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
 156                 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
 157         }
 158
 159         AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
 160
 161         if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
 162                 ee->ee_is_hb63 = true;
 163         else
 164                 ee->ee_is_hb63 = false;
 165
 166         AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
 167         ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
 168         ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
 169
 170         /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
 171          * and enable serdes programming if needed.
 172          *
 173          * XXX: Serdes values seem to be fixed so
 174          * no need to read them here, we write them
 175          * during ath5k_hw_attach */
 176         AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
 177         ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
 178                                                         true : false;
 179
 180         return 0;
 181 }
 182
 183
 184 /*
 185  * Read antenna infos from eeprom
 186  */
 187 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
 188                 unsigned int mode)
 189 {
 190         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 191         u32 o = *offset;
 192         u16 val;
 193         int ret, i = 0;
 194
 195         AR5K_EEPROM_READ(o++, val);
 196         ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
 197         ee->ee_atn_tx_rx[mode]          = (val >> 2) & 0x3f;
 198         ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
 199
 200         AR5K_EEPROM_READ(o++, val);
 201         ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
 202         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
 203         ee->ee_ant_control[mode][i++]   = val & 0x3f;
 204
 205         AR5K_EEPROM_READ(o++, val);
 206         ee->ee_ant_control[mode][i++]   = (val >> 10) & 0x3f;
 207         ee->ee_ant_control[mode][i++]   = (val >> 4) & 0x3f;
 208         ee->ee_ant_control[mode][i]     = (val << 2) & 0x3f;
 209
 210         AR5K_EEPROM_READ(o++, val);
 211         ee->ee_ant_control[mode][i++]   |= (val >> 14) & 0x3;
 212         ee->ee_ant_control[mode][i++]   = (val >> 8) & 0x3f;
 213         ee->ee_ant_control[mode][i++]   = (val >> 2) & 0x3f;
 214         ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
 215
 216         AR5K_EEPROM_READ(o++, val);
 217         ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
 218         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
 219         ee->ee_ant_control[mode][i++]   = val & 0x3f;
 220
 221         /* Get antenna switch tables */
 222         ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
 223             (ee->ee_ant_control[mode][0] << 4);
 224         ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
 225              ee->ee_ant_control[mode][1]        |
 226             (ee->ee_ant_control[mode][2] << 6)  |
 227             (ee->ee_ant_control[mode][3] << 12) |
 228             (ee->ee_ant_control[mode][4] << 18) |
 229             (ee->ee_ant_control[mode][5] << 24);
 230         ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
 231              ee->ee_ant_control[mode][6]        |
 232             (ee->ee_ant_control[mode][7] << 6)  |
 233             (ee->ee_ant_control[mode][8] << 12) |
 234             (ee->ee_ant_control[mode][9] << 18) |
 235             (ee->ee_ant_control[mode][10] << 24);
 236
 237         /* return new offset */
 238         *offset = o;
 239
 240         return 0;
 241 }
 242
 243 /*
 244  * Read supported modes and some mode-specific calibration data
 245  * from eeprom
 246  */
 247 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
 248                 unsigned int mode)
 249 {
 250         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 251         u32 o = *offset;
 252         u16 val;
 253         int ret;
 254
 255         ee->ee_n_piers[mode] = 0;
 256         AR5K_EEPROM_READ(o++, val);
 257         ee->ee_adc_desired_size[mode]   = (s8)((val >> 8) & 0xff);
 258         switch(mode) {
 259         case AR5K_EEPROM_MODE_11A:
 260                 ee->ee_ob[mode][3]      = (val >> 5) & 0x7;
 261                 ee->ee_db[mode][3]      = (val >> 2) & 0x7;
 262                 ee->ee_ob[mode][2]      = (val << 1) & 0x7;
 263
 264                 AR5K_EEPROM_READ(o++, val);
 265                 ee->ee_ob[mode][2]      |= (val >> 15) & 0x1;
 266                 ee->ee_db[mode][2]      = (val >> 12) & 0x7;
 267                 ee->ee_ob[mode][1]      = (val >> 9) & 0x7;
 268                 ee->ee_db[mode][1]      = (val >> 6) & 0x7;
 269                 ee->ee_ob[mode][0]      = (val >> 3) & 0x7;
 270                 ee->ee_db[mode][0]      = val & 0x7;
 271                 break;
 272         case AR5K_EEPROM_MODE_11G:
 273         case AR5K_EEPROM_MODE_11B:
 274                 ee->ee_ob[mode][1]      = (val >> 4) & 0x7;
 275                 ee->ee_db[mode][1]      = val & 0x7;
 276                 break;
 277         }
 278
 279         AR5K_EEPROM_READ(o++, val);
 280         ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
 281         ee->ee_thr_62[mode]             = val & 0xff;
 282
 283         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
 284                 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
 285
 286         AR5K_EEPROM_READ(o++, val);
 287         ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
 288         ee->ee_tx_frm2xpa_enable[mode]  = val & 0xff;
 289
 290         AR5K_EEPROM_READ(o++, val);
 291         ee->ee_pga_desired_size[mode]   = (val >> 8) & 0xff;
 292
 293         if ((val & 0xff) & 0x80)
 294                 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
 295         else
 296                 ee->ee_noise_floor_thr[mode] = val & 0xff;
 297
 298         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
 299                 ee->ee_noise_floor_thr[mode] =
 300                     mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
 301
 302         AR5K_EEPROM_READ(o++, val);
 303         ee->ee_xlna_gain[mode]          = (val >> 5) & 0xff;
 304         ee->ee_x_gain[mode]             = (val >> 1) & 0xf;
 305         ee->ee_xpd[mode]                = val & 0x1;
 306
 307         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
 308                 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
 309
 310         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
 311                 AR5K_EEPROM_READ(o++, val);
 312                 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
 313
 314                 if (mode == AR5K_EEPROM_MODE_11A)
 315                         ee->ee_xr_power[mode] = val & 0x3f;
 316                 else {
 317                         ee->ee_ob[mode][0] = val & 0x7;
 318                         ee->ee_db[mode][0] = (val >> 3) & 0x7;
 319                 }
 320         }
 321
 322         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
 323                 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
 324                 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
 325         } else {
 326                 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
 327
 328                 AR5K_EEPROM_READ(o++, val);
 329                 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
 330
 331                 if (mode == AR5K_EEPROM_MODE_11G) {
 332                         ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
 333                         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
 334                                 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
 335                 }
 336         }
 337
 338         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
 339                         mode == AR5K_EEPROM_MODE_11A) {
 340                 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
 341                 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
 342         }
 343
 344         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
 345                 goto done;
 346
 347         /* Note: >= v5 have bg freq piers on another location
 348          * so these freq piers are ignored for >= v5 (should be 0xff
 349          * anyway) */
 350         switch(mode) {
 351         case AR5K_EEPROM_MODE_11A:
 352                 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
 353                         break;
 354
 355                 AR5K_EEPROM_READ(o++, val);
 356                 ee->ee_margin_tx_rx[mode] = val & 0x3f;
 357                 break;
 358         case AR5K_EEPROM_MODE_11B:
 359                 AR5K_EEPROM_READ(o++, val);
 360
 361                 ee->ee_pwr_cal_b[0].freq =
 362                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 363                 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
 364                         ee->ee_n_piers[mode]++;
 365
 366                 ee->ee_pwr_cal_b[1].freq =
 367                         ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
 368                 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
 369                         ee->ee_n_piers[mode]++;
 370
 371                 AR5K_EEPROM_READ(o++, val);
 372                 ee->ee_pwr_cal_b[2].freq =
 373                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 374                 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
 375                         ee->ee_n_piers[mode]++;
 376
 377                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 378                         ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 379                 break;
 380         case AR5K_EEPROM_MODE_11G:
 381                 AR5K_EEPROM_READ(o++, val);
 382
 383                 ee->ee_pwr_cal_g[0].freq =
 384                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 385                 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
 386                         ee->ee_n_piers[mode]++;
 387
 388                 ee->ee_pwr_cal_g[1].freq =
 389                         ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
 390                 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
 391                         ee->ee_n_piers[mode]++;
 392
 393                 AR5K_EEPROM_READ(o++, val);
 394                 ee->ee_turbo_max_power[mode] = val & 0x7f;
 395                 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
 396
 397                 AR5K_EEPROM_READ(o++, val);
 398                 ee->ee_pwr_cal_g[2].freq =
 399                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 400                 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
 401                         ee->ee_n_piers[mode]++;
 402
 403                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 404                         ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 405
 406                 AR5K_EEPROM_READ(o++, val);
 407                 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
 408                 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
 409
 410                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
 411                         AR5K_EEPROM_READ(o++, val);
 412                         ee->ee_cck_ofdm_gain_delta = val & 0xff;
 413                 }
 414                 break;
 415         }
 416
 417 done:
 418         /* return new offset */
 419         *offset = o;
 420
 421         return 0;
 422 }
 423
 424 /*
 425  * Read turbo mode information on newer EEPROM versions
 426  */
 427 static int
 428 ath5k_eeprom_read_turbo_modes(struct ath5k_hw *ah,
 429                               u32 *offset, unsigned int mode)
 430 {
 431         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 432         u32 o = *offset;
 433         u16 val;
 434         int ret;
 435
 436         if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
 437                 return 0;
 438
 439         switch (mode){
 440         case AR5K_EEPROM_MODE_11A:
 441                 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
 442
 443                 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
 444                 AR5K_EEPROM_READ(o++, val);
 445                 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
 446                 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
 447
 448                 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
 449                 AR5K_EEPROM_READ(o++, val);
 450                 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
 451                 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
 452
 453                 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
 454                         ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
 455                 break;
 456         case AR5K_EEPROM_MODE_11G:
 457                 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
 458
 459                 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
 460                 AR5K_EEPROM_READ(o++, val);
 461                 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
 462                 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
 463
 464                 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
 465                 AR5K_EEPROM_READ(o++, val);
 466                 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
 467                 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
 468                 break;
 469         }
 470
 471         /* return new offset */
 472         *offset = o;
 473
 474         return 0;
 475 }
 476
 477 /* Read mode-specific data (except power calibration data) */
 478 static int
 479 ath5k_eeprom_init_modes(struct ath5k_hw *ah)
 480 {
 481         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 482         u32 mode_offset[3];
 483         unsigned int mode;
 484         u32 offset;
 485         int ret;
 486
 487         /*
 488          * Get values for all modes
 489          */
 490         mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
 491         mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
 492         mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
 493
 494         ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
 495                 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
 496
 497         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
 498                 offset = mode_offset[mode];
 499
 500                 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
 501                 if (ret)
 502                         return ret;
 503
 504                 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
 505                 if (ret)
 506                         return ret;
 507
 508                 ret = ath5k_eeprom_read_turbo_modes(ah, &offset, mode);
 509                 if (ret)
 510                         return ret;
 511         }
 512
 513         /* override for older eeprom versions for better performance */
 514         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
 515                 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
 516                 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
 517                 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
 518         }
 519
 520         return 0;
 521 }
 522
 523 /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
 524  * frequency mask) */
 525 static inline int
 526 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
 527                         struct ath5k_chan_pcal_info *pc, unsigned int mode)
 528 {
 529         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 530         int o = *offset;
 531         int i = 0;
 532         u8 freq1, freq2;
 533         int ret;
 534         u16 val;
 535
 536         ee->ee_n_piers[mode] = 0;
 537         while(i < max) {
 538                 AR5K_EEPROM_READ(o++, val);
 539
 540                 freq1 = val & 0xff;
 541                 if (!freq1)
 542                         break;
 543
 544                 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
 545                                 freq1, mode);
 546                 ee->ee_n_piers[mode]++;
 547
 548                 freq2 = (val >> 8) & 0xff;
 549                 if (!freq2)
 550                         break;
 551
 552                 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
 553                                 freq2, mode);
 554                 ee->ee_n_piers[mode]++;
 555         }
 556
 557         /* return new offset */
 558         *offset = o;
 559
 560         return 0;
 561 }
 562
 563 /* Read frequency piers for 802.11a */
 564 static int
 565 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
 566 {
 567         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 568         struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
 569         int i, ret;
 570         u16 val;
 571         u8 mask;
 572
 573         if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
 574                 ath5k_eeprom_read_freq_list(ah, &offset,
 575                         AR5K_EEPROM_N_5GHZ_CHAN, pcal,
 576                         AR5K_EEPROM_MODE_11A);
 577         } else {
 578                 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
 579
 580                 AR5K_EEPROM_READ(offset++, val);
 581                 pcal[0].freq  = (val >> 9) & mask;
 582                 pcal[1].freq  = (val >> 2) & mask;
 583                 pcal[2].freq  = (val << 5) & mask;
 584
 585                 AR5K_EEPROM_READ(offset++, val);
 586                 pcal[2].freq |= (val >> 11) & 0x1f;
 587                 pcal[3].freq  = (val >> 4) & mask;
 588                 pcal[4].freq  = (val << 3) & mask;
 589
 590                 AR5K_EEPROM_READ(offset++, val);
 591                 pcal[4].freq |= (val >> 13) & 0x7;
 592                 pcal[5].freq  = (val >> 6) & mask;
 593                 pcal[6].freq  = (val << 1) & mask;
 594
 595                 AR5K_EEPROM_READ(offset++, val);
 596                 pcal[6].freq |= (val >> 15) & 0x1;
 597                 pcal[7].freq  = (val >> 8) & mask;
 598                 pcal[8].freq  = (val >> 1) & mask;
 599                 pcal[9].freq  = (val << 6) & mask;
 600
 601                 AR5K_EEPROM_READ(offset++, val);
 602                 pcal[9].freq |= (val >> 10) & 0x3f;
 603
 604                 /* Fixed number of piers */
 605                 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
 606
 607                 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
 608                         pcal[i].freq = ath5k_eeprom_bin2freq(ee,
 609                                 pcal[i].freq, AR5K_EEPROM_MODE_11A);
 610                 }
 611         }
 612
 613         return 0;
 614 }
 615
 616 /* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
 617 static inline int
 618 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
 619 {
 620         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 621         struct ath5k_chan_pcal_info *pcal;
 622
 623         switch(mode) {
 624         case AR5K_EEPROM_MODE_11B:
 625                 pcal = ee->ee_pwr_cal_b;
 626                 break;
 627         case AR5K_EEPROM_MODE_11G:
 628                 pcal = ee->ee_pwr_cal_g;
 629                 break;
 630         default:
 631                 return -EINVAL;
 632         }
 633
 634         ath5k_eeprom_read_freq_list(ah, &offset,
 635                 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
 636                 mode);
 637
 638         return 0;
 639 }
 640
 641 /*
 642  * Read power calibration for RF5111 chips
 643  *
 644  * For RF5111 we have an XPD -eXternal Power Detector- curve
 645  * for each calibrated channel. Each curve has 0,5dB Power steps
 646  * on x axis and PCDAC steps (offsets) on y axis and looks like an
 647  * exponential function. To recreate the curve we read 11 points
 648  * here and interpolate later.
 649  */
 650
 651 /* Used to match PCDAC steps with power values on RF5111 chips
 652  * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
 653  * steps that match with the power values we read from eeprom. On
 654  * older eeprom versions (< 3.2) these steps are equaly spaced at
 655  * 10% of the pcdac curve -until the curve reaches it's maximum-
 656  * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
 657  * these 11 steps are spaced in a different way. This function returns
 658  * the pcdac steps based on eeprom version and curve min/max so that we
 659  * can have pcdac/pwr points.
 660  */
 661 static inline void
 662 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
 663 {
 664         static const u16 intercepts3[] =
 665                 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
 666         static const u16 intercepts3_2[] =
 667                 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
 668         const u16 *ip;
 669         int i;
 670
 671         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
 672                 ip = intercepts3_2;
 673         else
 674                 ip = intercepts3;
 675
 676         for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
 677                 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
 678 }
 679
 680 /* Convert RF5111 specific data to generic raw data
 681  * used by interpolation code */
 682 static int
 683 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
 684                                 struct ath5k_chan_pcal_info *chinfo)
 685 {
 686         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 687         struct ath5k_chan_pcal_info_rf5111 *pcinfo;
 688         struct ath5k_pdgain_info *pd;
 689         u8 pier, point, idx;
 690         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
 691
 692         /* Fill raw data for each calibration pier */
 693         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
 694
 695                 pcinfo = &chinfo[pier].rf5111_info;
 696
 697                 /* Allocate pd_curves for this cal pier */
 698                 chinfo[pier].pd_curves =
 699                         kcalloc(AR5K_EEPROM_N_PD_CURVES,
 700                                 sizeof(struct ath5k_pdgain_info),
 701                                 GFP_KERNEL);
 702
 703                 if (!chinfo[pier].pd_curves)
 704                         return -ENOMEM;
 705
 706                 /* Only one curve for RF5111
 707                  * find out which one and place
 708                  * in in pd_curves.
 709                  * Note: ee_x_gain is reversed here */
 710                 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
 711
 712                         if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
 713                                 pdgain_idx[0] = idx;
 714                                 break;
 715                         }
 716                 }
 717
 718                 ee->ee_pd_gains[mode] = 1;
 719
 720                 pd = &chinfo[pier].pd_curves[idx];
 721
 722                 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
 723
 724                 /* Allocate pd points for this curve */
 725                 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
 726                                         sizeof(u8), GFP_KERNEL);
 727                 if (!pd->pd_step)
 728                         return -ENOMEM;
 729
 730                 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
 731                                         sizeof(s16), GFP_KERNEL);
 732                 if (!pd->pd_pwr)
 733                         return -ENOMEM;
 734
 735                 /* Fill raw dataset
 736                  * (convert power to 0.25dB units
 737                  * for RF5112 combatibility) */
 738                 for (point = 0; point < pd->pd_points; point++) {
 739
 740                         /* Absolute values */
 741                         pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
 742
 743                         /* Already sorted */
 744                         pd->pd_step[point] = pcinfo->pcdac[point];
 745                 }
 746
 747                 /* Set min/max pwr */
 748                 chinfo[pier].min_pwr = pd->pd_pwr[0];
 749                 chinfo[pier].max_pwr = pd->pd_pwr[10];
 750
 751         }
 752
 753         return 0;
 754 }
 755
 756 /* Parse EEPROM data */
 757 static int
 758 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
 759 {
 760         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 761         struct ath5k_chan_pcal_info *pcal;
 762         int offset, ret;
 763         int i;
 764         u16 val;
 765
 766         offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
 767         switch(mode) {
 768         case AR5K_EEPROM_MODE_11A:
 769                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
 770                         return 0;
 771
 772                 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
 773                         offset + AR5K_EEPROM_GROUP1_OFFSET);
 774                 if (ret < 0)
 775                         return ret;
 776
 777                 offset += AR5K_EEPROM_GROUP2_OFFSET;
 778                 pcal = ee->ee_pwr_cal_a;
 779                 break;
 780         case AR5K_EEPROM_MODE_11B:
 781                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
 782                     !AR5K_EEPROM_HDR_11G(ee->ee_header))
 783                         return 0;
 784
 785                 pcal = ee->ee_pwr_cal_b;
 786                 offset += AR5K_EEPROM_GROUP3_OFFSET;
 787
 788                 /* fixed piers */
 789                 pcal[0].freq = 2412;
 790                 pcal[1].freq = 2447;
 791                 pcal[2].freq = 2484;
 792                 ee->ee_n_piers[mode] = 3;
 793                 break;
 794         case AR5K_EEPROM_MODE_11G:
 795                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
 796                         return 0;
 797
 798                 pcal = ee->ee_pwr_cal_g;
 799                 offset += AR5K_EEPROM_GROUP4_OFFSET;
 800
 801                 /* fixed piers */
 802                 pcal[0].freq = 2312;
 803                 pcal[1].freq = 2412;
 804                 pcal[2].freq = 2484;
 805                 ee->ee_n_piers[mode] = 3;
 806                 break;
 807         default:
 808                 return -EINVAL;
 809         }
 810
 811         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
 812                 struct ath5k_chan_pcal_info_rf5111 *cdata =
 813                         &pcal[i].rf5111_info;
 814
 815                 AR5K_EEPROM_READ(offset++, val);
 816                 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
 817                 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
 818                 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
 819
 820                 AR5K_EEPROM_READ(offset++, val);
 821                 cdata->pwr[0] |= ((val >> 14) & 0x3);
 822                 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
 823                 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
 824                 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
 825
 826                 AR5K_EEPROM_READ(offset++, val);
 827                 cdata->pwr[3] |= ((val >> 12) & 0xf);
 828                 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
 829                 cdata->pwr[5] = (val  & AR5K_EEPROM_POWER_M);
 830
 831                 AR5K_EEPROM_READ(offset++, val);
 832                 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
 833                 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
 834                 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
 835
 836                 AR5K_EEPROM_READ(offset++, val);
 837                 cdata->pwr[8] |= ((val >> 14) & 0x3);
 838                 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
 839                 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
 840
 841                 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
 842                         cdata->pcdac_max, cdata->pcdac);
 843         }
 844
 845         return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
 846 }
 847
 848
 849 /*
 850  * Read power calibration for RF5112 chips
 851  *
 852  * For RF5112 we have 4 XPD -eXternal Power Detector- curves
 853  * for each calibrated channel on 0, -6, -12 and -18dbm but we only
 854  * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
 855  * power steps on x axis and PCDAC steps on y axis and looks like a
 856  * linear function. To recreate the curve and pass the power values
 857  * on hw, we read 4 points for xpd 0 (lower gain -> max power)
 858  * and 3 points for xpd 3 (higher gain -> lower power) here and
 859  * interpolate later.
 860  *
 861  * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
 862  */
 863
 864 /* Convert RF5112 specific data to generic raw data
 865  * used by interpolation code */
 866 static int
 867 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
 868                                 struct ath5k_chan_pcal_info *chinfo)
 869 {
 870         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 871         struct ath5k_chan_pcal_info_rf5112 *pcinfo;
 872         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
 873         unsigned int pier, pdg, point;
 874
 875         /* Fill raw data for each calibration pier */
 876         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
 877
 878                 pcinfo = &chinfo[pier].rf5112_info;
 879
 880                 /* Allocate pd_curves for this cal pier */
 881                 chinfo[pier].pd_curves =
 882                                 kcalloc(AR5K_EEPROM_N_PD_CURVES,
 883                                         sizeof(struct ath5k_pdgain_info),
 884                                         GFP_KERNEL);
 885
 886                 if (!chinfo[pier].pd_curves)
 887                         return -ENOMEM;
 888
 889                 /* Fill pd_curves */
 890                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
 891
 892                         u8 idx = pdgain_idx[pdg];
 893                         struct ath5k_pdgain_info *pd =
 894                                         &chinfo[pier].pd_curves[idx];
 895
 896                         /* Lowest gain curve (max power) */
 897                         if (pdg == 0) {
 898                                 /* One more point for better accuracy */
 899                                 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
 900
 901                                 /* Allocate pd points for this curve */
 902                                 pd->pd_step = kcalloc(pd->pd_points,
 903                                                 sizeof(u8), GFP_KERNEL);
 904
 905                                 if (!pd->pd_step)
 906                                         return -ENOMEM;
 907
 908                                 pd->pd_pwr = kcalloc(pd->pd_points,
 909                                                 sizeof(s16), GFP_KERNEL);
 910
 911                                 if (!pd->pd_pwr)
 912                                         return -ENOMEM;
 913
 914
 915                                 /* Fill raw dataset
 916                                  * (all power levels are in 0.25dB units) */
 917                                 pd->pd_step[0] = pcinfo->pcdac_x0[0];
 918                                 pd->pd_pwr[0] = pcinfo->pwr_x0[0];
 919
 920                                 for (point = 1; point < pd->pd_points;
 921                                 point++) {
 922                                         /* Absolute values */
 923                                         pd->pd_pwr[point] =
 924                                                 pcinfo->pwr_x0[point];
 925
 926                                         /* Deltas */
 927                                         pd->pd_step[point] =
 928                                                 pd->pd_step[point - 1] +
 929                                                 pcinfo->pcdac_x0[point];
 930                                 }
 931
 932                                 /* Set min power for this frequency */
 933                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
 934
 935                         /* Highest gain curve (min power) */
 936                         } else if (pdg == 1) {
 937
 938                                 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
 939
 940                                 /* Allocate pd points for this curve */
 941                                 pd->pd_step = kcalloc(pd->pd_points,
 942                                                 sizeof(u8), GFP_KERNEL);
 943
 944                                 if (!pd->pd_step)
 945                                         return -ENOMEM;
 946
 947                                 pd->pd_pwr = kcalloc(pd->pd_points,
 948                                                 sizeof(s16), GFP_KERNEL);
 949
 950                                 if (!pd->pd_pwr)
 951                                         return -ENOMEM;
 952
 953                                 /* Fill raw dataset
 954                                  * (all power levels are in 0.25dB units) */
 955                                 for (point = 0; point < pd->pd_points;
 956                                 point++) {
 957                                         /* Absolute values */
 958                                         pd->pd_pwr[point] =
 959                                                 pcinfo->pwr_x3[point];
 960
 961                                         /* Fixed points */
 962                                         pd->pd_step[point] =
 963                                                 pcinfo->pcdac_x3[point];
 964                                 }
 965
 966                                 /* Since we have a higher gain curve
 967                                  * override min power */
 968                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
 969                         }
 970                 }
 971         }
 972
 973         return 0;
 974 }
 975
 976 /* Parse EEPROM data */
 977 static int
 978 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
 979 {
 980         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 981         struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
 982         struct ath5k_chan_pcal_info *gen_chan_info;
 983         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
 984         u32 offset;
 985         u8 i, c;
 986         u16 val;
 987         int ret;
 988         u8 pd_gains = 0;
 989
 990         /* Count how many curves we have and
 991          * identify them (which one of the 4
 992          * available curves we have on each count).
 993          * Curves are stored from lower (x0) to
 994          * higher (x3) gain */
 995         for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
 996                 /* ee_x_gain[mode] is x gain mask */
 997                 if ((ee->ee_x_gain[mode] >> i) & 0x1)
 998                         pdgain_idx[pd_gains++] = i;
 999         }
1000         ee->ee_pd_gains[mode] = pd_gains;
1001
1002         if (pd_gains == 0 || pd_gains > 2)
1003                 return -EINVAL;
1004
1005         switch (mode) {
1006         case AR5K_EEPROM_MODE_11A:
1007                 /*
1008                  * Read 5GHz EEPROM channels
1009                  */
1010                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1011                 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1012
1013                 offset += AR5K_EEPROM_GROUP2_OFFSET;
1014                 gen_chan_info = ee->ee_pwr_cal_a;
1015                 break;
1016         case AR5K_EEPROM_MODE_11B:
1017                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1018                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1019                         offset += AR5K_EEPROM_GROUP3_OFFSET;
1020
1021                 /* NB: frequency piers parsed during mode init */
1022                 gen_chan_info = ee->ee_pwr_cal_b;
1023                 break;
1024         case AR5K_EEPROM_MODE_11G:
1025                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1026                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1027                         offset += AR5K_EEPROM_GROUP4_OFFSET;
1028                 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1029                         offset += AR5K_EEPROM_GROUP2_OFFSET;
1030
1031                 /* NB: frequency piers parsed during mode init */
1032                 gen_chan_info = ee->ee_pwr_cal_g;
1033                 break;
1034         default:
1035                 return -EINVAL;
1036         }
1037
1038         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1039                 chan_pcal_info = &gen_chan_info[i].rf5112_info;
1040
1041                 /* Power values in quarter dB
1042                  * for the lower xpd gain curve
1043                  * (0 dBm -> higher output power) */
1044                 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
1045                         AR5K_EEPROM_READ(offset++, val);
1046                         chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
1047                         chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
1048                 }
1049
1050                 /* PCDAC steps
1051                  * corresponding to the above power
1052                  * measurements */
1053                 AR5K_EEPROM_READ(offset++, val);
1054                 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
1055                 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
1056                 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
1057
1058                 /* Power values in quarter dB
1059                  * for the higher xpd gain curve
1060                  * (18 dBm -> lower output power) */
1061                 AR5K_EEPROM_READ(offset++, val);
1062                 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
1063                 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
1064
1065                 AR5K_EEPROM_READ(offset++, val);
1066                 chan_pcal_info->pwr_x3[2] = (val & 0xff);
1067
1068                 /* PCDAC steps
1069                  * corresponding to the above power
1070                  * measurements (fixed) */
1071                 chan_pcal_info->pcdac_x3[0] = 20;
1072                 chan_pcal_info->pcdac_x3[1] = 35;
1073                 chan_pcal_info->pcdac_x3[2] = 63;
1074
1075                 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
1076                         chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
1077
1078                         /* Last xpd0 power level is also channel maximum */
1079                         gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
1080                 } else {
1081                         chan_pcal_info->pcdac_x0[0] = 1;
1082                         gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
1083                 }
1084
1085         }
1086
1087         return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1088 }
1089
1090
1091 /*
1092  * Read power calibration for RF2413 chips
1093  *
1094  * For RF2413 we have a Power to PDDAC table (Power Detector)
1095  * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1096  * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
1097  * axis and looks like an exponential function like the RF5111 curve.
1098  *
1099  * To recreate the curves we read here the points and interpolate
1100  * later. Note that in most cases only 2 (higher and lower) curves are
1101  * used (like RF5112) but vendors have the oportunity to include all
1102  * 4 curves on eeprom. The final curve (higher power) has an extra
1103  * point for better accuracy like RF5112.
1104  */
1105
1106 /* For RF2413 power calibration data doesn't start on a fixed location and
1107  * if a mode is not supported, it's section is missing -not zeroed-.
1108  * So we need to calculate the starting offset for each section by using
1109  * these two functions */
1110
1111 /* Return the size of each section based on the mode and the number of pd
1112  * gains available (maximum 4). */
1113 static inline unsigned int
1114 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1115 {
1116         static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1117         unsigned int sz;
1118
1119         sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1120         sz *= ee->ee_n_piers[mode];
1121
1122         return sz;
1123 }
1124
1125 /* Return the starting offset for a section based on the modes supported
1126  * and each section's size. */
1127 static unsigned int
1128 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1129 {
1130         u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1131
1132         switch(mode) {
1133         case AR5K_EEPROM_MODE_11G:
1134                 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1135                         offset += ath5k_pdgains_size_2413(ee,
1136                                         AR5K_EEPROM_MODE_11B) +
1137                                         AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1138                 /* fall through */
1139         case AR5K_EEPROM_MODE_11B:
1140                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1141                         offset += ath5k_pdgains_size_2413(ee,
1142                                         AR5K_EEPROM_MODE_11A) +
1143                                         AR5K_EEPROM_N_5GHZ_CHAN / 2;
1144                 /* fall through */
1145         case AR5K_EEPROM_MODE_11A:
1146                 break;
1147         default:
1148                 break;
1149         }
1150
1151         return offset;
1152 }
1153
1154 /* Convert RF2413 specific data to generic raw data
1155  * used by interpolation code */
1156 static int
1157 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1158                                 struct ath5k_chan_pcal_info *chinfo)
1159 {
1160         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1161         struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1162         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1163         unsigned int pier, pdg, point;
1164
1165         /* Fill raw data for each calibration pier */
1166         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1167
1168                 pcinfo = &chinfo[pier].rf2413_info;
1169
1170                 /* Allocate pd_curves for this cal pier */
1171                 chinfo[pier].pd_curves =
1172                                 kcalloc(AR5K_EEPROM_N_PD_CURVES,
1173                                         sizeof(struct ath5k_pdgain_info),
1174                                         GFP_KERNEL);
1175
1176                 if (!chinfo[pier].pd_curves)
1177                         return -ENOMEM;
1178
1179                 /* Fill pd_curves */
1180                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1181
1182                         u8 idx = pdgain_idx[pdg];
1183                         struct ath5k_pdgain_info *pd =
1184                                         &chinfo[pier].pd_curves[idx];
1185
1186                         /* One more point for the highest power
1187                          * curve (lowest gain) */
1188                         if (pdg == ee->ee_pd_gains[mode] - 1)
1189                                 pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
1190                         else
1191                                 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
1192
1193                         /* Allocate pd points for this curve */
1194                         pd->pd_step = kcalloc(pd->pd_points,
1195                                         sizeof(u8), GFP_KERNEL);
1196
1197                         if (!pd->pd_step)
1198                                 return -ENOMEM;
1199
1200                         pd->pd_pwr = kcalloc(pd->pd_points,
1201                                         sizeof(s16), GFP_KERNEL);
1202
1203                         if (!pd->pd_pwr)
1204                                 return -ENOMEM;
1205
1206                         /* Fill raw dataset
1207                          * convert all pwr levels to
1208                          * quarter dB for RF5112 combatibility */
1209                         pd->pd_step[0] = pcinfo->pddac_i[pdg];
1210                         pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1211
1212                         for (point = 1; point < pd->pd_points; point++) {
1213
1214                                 pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
1215                                         2 * pcinfo->pwr[pdg][point - 1];
1216
1217                                 pd->pd_step[point] = pd->pd_step[point - 1] +
1218                                                 pcinfo->pddac[pdg][point - 1];
1219
1220                         }
1221
1222                         /* Highest gain curve -> min power */
1223                         if (pdg == 0)
1224                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
1225
1226                         /* Lowest gain curve -> max power */
1227                         if (pdg == ee->ee_pd_gains[mode] - 1)
1228                                 chinfo[pier].max_pwr =
1229                                         pd->pd_pwr[pd->pd_points - 1];
1230                 }
1231         }
1232
1233         return 0;
1234 }
1235
1236 /* Parse EEPROM data */
1237 static int
1238 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1239 {
1240         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1241         struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1242         struct ath5k_chan_pcal_info *chinfo;
1243         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1244         u32 offset;
1245         int idx, i, ret;
1246         u16 val;
1247         u8 pd_gains = 0;
1248
1249         /* Count how many curves we have and
1250          * identify them (which one of the 4
1251          * available curves we have on each count).
1252          * Curves are stored from higher to
1253          * lower gain so we go backwards */
1254         for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
1255                 /* ee_x_gain[mode] is x gain mask */
1256                 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1257                         pdgain_idx[pd_gains++] = idx;
1258
1259         }
1260         ee->ee_pd_gains[mode] = pd_gains;
1261
1262         if (pd_gains == 0)
1263                 return -EINVAL;
1264
1265         offset = ath5k_cal_data_offset_2413(ee, mode);
1266         switch (mode) {
1267         case AR5K_EEPROM_MODE_11A:
1268                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1269                         return 0;
1270
1271                 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1272                 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
1273                 chinfo = ee->ee_pwr_cal_a;
1274                 break;
1275         case AR5K_EEPROM_MODE_11B:
1276                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1277                         return 0;
1278
1279                 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1280                 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1281                 chinfo = ee->ee_pwr_cal_b;
1282                 break;
1283         case AR5K_EEPROM_MODE_11G:
1284                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1285                         return 0;
1286
1287                 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1288                 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1289                 chinfo = ee->ee_pwr_cal_g;
1290                 break;
1291         default:
1292                 return -EINVAL;
1293         }
1294
1295         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1296                 pcinfo = &chinfo[i].rf2413_info;
1297
1298                 /*
1299                  * Read pwr_i, pddac_i and the first
1300                  * 2 pd points (pwr, pddac)
1301                  */
1302                 AR5K_EEPROM_READ(offset++, val);
1303                 pcinfo->pwr_i[0] = val & 0x1f;
1304                 pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
1305                 pcinfo->pwr[0][0] = (val >> 12) & 0xf;
1306
1307                 AR5K_EEPROM_READ(offset++, val);
1308                 pcinfo->pddac[0][0] = val & 0x3f;
1309                 pcinfo->pwr[0][1] = (val >> 6) & 0xf;
1310                 pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
1311
1312                 AR5K_EEPROM_READ(offset++, val);
1313                 pcinfo->pwr[0][2] = val & 0xf;
1314                 pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
1315
1316                 pcinfo->pwr[0][3] = 0;
1317                 pcinfo->pddac[0][3] = 0;
1318
1319                 if (pd_gains > 1) {
1320                         /*
1321                          * Pd gain 0 is not the last pd gain
1322                          * so it only has 2 pd points.
1323                          * Continue wih pd gain 1.
1324                          */
1325                         pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
1326
1327                         pcinfo->pddac_i[1] = (val >> 15) & 0x1;
1328                         AR5K_EEPROM_READ(offset++, val);
1329                         pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
1330
1331                         pcinfo->pwr[1][0] = (val >> 6) & 0xf;
1332                         pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
1333
1334                         AR5K_EEPROM_READ(offset++, val);
1335                         pcinfo->pwr[1][1] = val & 0xf;
1336                         pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
1337                         pcinfo->pwr[1][2] = (val >> 10) & 0xf;
1338
1339                         pcinfo->pddac[1][2] = (val >> 14) & 0x3;
1340                         AR5K_EEPROM_READ(offset++, val);
1341                         pcinfo->pddac[1][2] |= (val & 0xF) << 2;
1342
1343                         pcinfo->pwr[1][3] = 0;
1344                         pcinfo->pddac[1][3] = 0;
1345                 } else if (pd_gains == 1) {
1346                         /*
1347                          * Pd gain 0 is the last one so
1348                          * read the extra point.
1349                          */
1350                         pcinfo->pwr[0][3] = (val >> 10) & 0xf;
1351
1352                         pcinfo->pddac[0][3] = (val >> 14) & 0x3;
1353                         AR5K_EEPROM_READ(offset++, val);
1354                         pcinfo->pddac[0][3] |= (val & 0xF) << 2;
1355                 }
1356
1357                 /*
1358                  * Proceed with the other pd_gains
1359                  * as above.
1360                  */
1361                 if (pd_gains > 2) {
1362                         pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
1363                         pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
1364
1365                         AR5K_EEPROM_READ(offset++, val);
1366                         pcinfo->pwr[2][0] = (val >> 0) & 0xf;
1367                         pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
1368                         pcinfo->pwr[2][1] = (val >> 10) & 0xf;
1369
1370                         pcinfo->pddac[2][1] = (val >> 14) & 0x3;
1371                         AR5K_EEPROM_READ(offset++, val);
1372                         pcinfo->pddac[2][1] |= (val & 0xF) << 2;
1373
1374                         pcinfo->pwr[2][2] = (val >> 4) & 0xf;
1375                         pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
1376
1377                         pcinfo->pwr[2][3] = 0;
1378                         pcinfo->pddac[2][3] = 0;
1379                 } else if (pd_gains == 2) {
1380                         pcinfo->pwr[1][3] = (val >> 4) & 0xf;
1381                         pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
1382                 }
1383
1384                 if (pd_gains > 3) {
1385                         pcinfo->pwr_i[3] = (val >> 14) & 0x3;
1386                         AR5K_EEPROM_READ(offset++, val);
1387                         pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1388
1389                         pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
1390                         pcinfo->pwr[3][0] = (val >> 10) & 0xf;
1391                         pcinfo->pddac[3][0] = (val >> 14) & 0x3;
1392
1393                         AR5K_EEPROM_READ(offset++, val);
1394                         pcinfo->pddac[3][0] |= (val & 0xF) << 2;
1395                         pcinfo->pwr[3][1] = (val >> 4) & 0xf;
1396                         pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
1397
1398                         pcinfo->pwr[3][2] = (val >> 14) & 0x3;
1399                         AR5K_EEPROM_READ(offset++, val);
1400                         pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
1401
1402                         pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
1403                         pcinfo->pwr[3][3] = (val >> 8) & 0xf;
1404
1405                         pcinfo->pddac[3][3] = (val >> 12) & 0xF;
1406                         AR5K_EEPROM_READ(offset++, val);
1407                         pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
1408                 } else if (pd_gains == 3) {
1409                         pcinfo->pwr[2][3] = (val >> 14) & 0x3;
1410                         AR5K_EEPROM_READ(offset++, val);
1411                         pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
1412
1413                         pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
1414                 }
1415         }
1416
1417         return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1418 }
1419
1420
1421 /*
1422  * Read per rate target power (this is the maximum tx power
1423  * supported by the card). This info is used when setting
1424  * tx power, no matter the channel.
1425  *
1426  * This also works for v5 EEPROMs.
1427  */
1428 static int
1429 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1430 {
1431         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1432         struct ath5k_rate_pcal_info *rate_pcal_info;
1433         u8 *rate_target_pwr_num;
1434         u32 offset;
1435         u16 val;
1436         int ret, i;
1437
1438         offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1439         rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1440         switch (mode) {
1441         case AR5K_EEPROM_MODE_11A:
1442                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1443                 rate_pcal_info = ee->ee_rate_tpwr_a;
1444                 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1445                 break;
1446         case AR5K_EEPROM_MODE_11B:
1447                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1448                 rate_pcal_info = ee->ee_rate_tpwr_b;
1449                 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1450                 break;
1451         case AR5K_EEPROM_MODE_11G:
1452                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1453                 rate_pcal_info = ee->ee_rate_tpwr_g;
1454                 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1455                 break;
1456         default:
1457                 return -EINVAL;
1458         }
1459
1460         /* Different freq mask for older eeproms (<= v3.2) */
1461         if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1462                 for (i = 0; i < (*rate_target_pwr_num); i++) {
1463                         AR5K_EEPROM_READ(offset++, val);
1464                         rate_pcal_info[i].freq =
1465                             ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1466
1467                         rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1468                         rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1469
1470                         AR5K_EEPROM_READ(offset++, val);
1471
1472                         if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1473                             val == 0) {
1474                                 (*rate_target_pwr_num) = i;
1475                                 break;
1476                         }
1477
1478                         rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1479                         rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1480                         rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1481                 }
1482         } else {
1483                 for (i = 0; i < (*rate_target_pwr_num); i++) {
1484                         AR5K_EEPROM_READ(offset++, val);
1485                         rate_pcal_info[i].freq =
1486                             ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1487
1488                         rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1489                         rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1490
1491                         AR5K_EEPROM_READ(offset++, val);
1492
1493                         if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1494                             val == 0) {
1495                                 (*rate_target_pwr_num) = i;
1496                                 break;
1497                         }
1498
1499                         rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1500                         rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1501                         rate_pcal_info[i].target_power_54 = (val & 0x3f);
1502                 }
1503         }
1504
1505         return 0;
1506 }
1507
1508 /*
1509  * Read per channel calibration info from EEPROM
1510  *
1511  * This info is used to calibrate the baseband power table. Imagine
1512  * that for each channel there is a power curve that's hw specific
1513  * (depends on amplifier etc) and we try to "correct" this curve using
1514  * offests we pass on to phy chip (baseband -> before amplifier) so that
1515  * it can use accurate power values when setting tx power (takes amplifier's
1516  * performance on each channel into account).
1517  *
1518  * EEPROM provides us with the offsets for some pre-calibrated channels
1519  * and we have to interpolate to create the full table for these channels and
1520  * also the table for any channel.
1521  */
1522 static int
1523 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1524 {
1525         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1526         int (*read_pcal)(struct ath5k_hw *hw, int mode);
1527         int mode;
1528         int err;
1529
1530         if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1531                         (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1532                 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1533         else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1534                         (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1535                 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1536         else
1537                 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1538
1539
1540         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1541         mode++) {
1542                 err = read_pcal(ah, mode);
1543                 if (err)
1544                         return err;
1545
1546                 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1547                 if (err < 0)
1548                         return err;
1549         }
1550
1551         return 0;
1552 }
1553
1554 static int
1555 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
1556 {
1557         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1558         struct ath5k_chan_pcal_info *chinfo;
1559         u8 pier, pdg;
1560
1561         switch (mode) {
1562         case AR5K_EEPROM_MODE_11A:
1563                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1564                         return 0;
1565                 chinfo = ee->ee_pwr_cal_a;
1566                 break;
1567         case AR5K_EEPROM_MODE_11B:
1568                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1569                         return 0;
1570                 chinfo = ee->ee_pwr_cal_b;
1571                 break;
1572         case AR5K_EEPROM_MODE_11G:
1573                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1574                         return 0;
1575                 chinfo = ee->ee_pwr_cal_g;
1576                 break;
1577         default:
1578                 return -EINVAL;
1579         }
1580
1581         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1582                 if (!chinfo[pier].pd_curves)
1583                         continue;
1584
1585                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1586                         struct ath5k_pdgain_info *pd =
1587                                         &chinfo[pier].pd_curves[pdg];
1588
1589                         if (pd != NULL) {
1590                                 kfree(pd->pd_step);
1591                                 kfree(pd->pd_pwr);
1592                         }
1593                 }
1594
1595                 kfree(chinfo[pier].pd_curves);
1596         }
1597
1598         return 0;
1599 }
1600
1601 void
1602 ath5k_eeprom_detach(struct ath5k_hw *ah)
1603 {
1604         u8 mode;
1605
1606         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1607                 ath5k_eeprom_free_pcal_info(ah, mode);
1608 }
1609
1610 /* Read conformance test limits used for regulatory control */
1611 static int
1612 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1613 {
1614         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1615         struct ath5k_edge_power *rep;
1616         unsigned int fmask, pmask;
1617         unsigned int ctl_mode;
1618         int ret, i, j;
1619         u32 offset;
1620         u16 val;
1621
1622         pmask = AR5K_EEPROM_POWER_M;
1623         fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1624         offset = AR5K_EEPROM_CTL(ee->ee_version);
1625         ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1626         for (i = 0; i < ee->ee_ctls; i += 2) {
1627                 AR5K_EEPROM_READ(offset++, val);
1628                 ee->ee_ctl[i] = (val >> 8) & 0xff;
1629                 ee->ee_ctl[i + 1] = val & 0xff;
1630         }
1631
1632         offset = AR5K_EEPROM_GROUP8_OFFSET;
1633         if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1634                 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1635                         AR5K_EEPROM_GROUP5_OFFSET;
1636         else
1637                 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1638
1639         rep = ee->ee_ctl_pwr;
1640         for(i = 0; i < ee->ee_ctls; i++) {
1641                 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1642                 case AR5K_CTL_11A:
1643                 case AR5K_CTL_TURBO:
1644                         ctl_mode = AR5K_EEPROM_MODE_11A;
1645                         break;
1646                 default:
1647                         ctl_mode = AR5K_EEPROM_MODE_11G;
1648                         break;
1649                 }
1650                 if (ee->ee_ctl[i] == 0) {
1651                         if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1652                                 offset += 8;
1653                         else
1654                                 offset += 7;
1655                         rep += AR5K_EEPROM_N_EDGES;
1656                         continue;
1657                 }
1658                 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1659                         for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1660                                 AR5K_EEPROM_READ(offset++, val);
1661                                 rep[j].freq = (val >> 8) & fmask;
1662                                 rep[j + 1].freq = val & fmask;
1663                         }
1664                         for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1665                                 AR5K_EEPROM_READ(offset++, val);
1666                                 rep[j].edge = (val >> 8) & pmask;
1667                                 rep[j].flag = (val >> 14) & 1;
1668                                 rep[j + 1].edge = val & pmask;
1669                                 rep[j + 1].flag = (val >> 6) & 1;
1670                         }
1671                 } else {
1672                         AR5K_EEPROM_READ(offset++, val);
1673                         rep[0].freq = (val >> 9) & fmask;
1674                         rep[1].freq = (val >> 2) & fmask;
1675                         rep[2].freq = (val << 5) & fmask;
1676
1677                         AR5K_EEPROM_READ(offset++, val);
1678                         rep[2].freq |= (val >> 11) & 0x1f;
1679                         rep[3].freq = (val >> 4) & fmask;
1680                         rep[4].freq = (val << 3) & fmask;
1681
1682                         AR5K_EEPROM_READ(offset++, val);
1683                         rep[4].freq |= (val >> 13) & 0x7;
1684                         rep[5].freq = (val >> 6) & fmask;
1685                         rep[6].freq = (val << 1) & fmask;
1686
1687                         AR5K_EEPROM_READ(offset++, val);
1688                         rep[6].freq |= (val >> 15) & 0x1;
1689                         rep[7].freq = (val >> 8) & fmask;
1690
1691                         rep[0].edge = (val >> 2) & pmask;
1692                         rep[1].edge = (val << 4) & pmask;
1693
1694                         AR5K_EEPROM_READ(offset++, val);
1695                         rep[1].edge |= (val >> 12) & 0xf;
1696                         rep[2].edge = (val >> 6) & pmask;
1697                         rep[3].edge = val & pmask;
1698
1699                         AR5K_EEPROM_READ(offset++, val);
1700                         rep[4].edge = (val >> 10) & pmask;
1701                         rep[5].edge = (val >> 4) & pmask;
1702                         rep[6].edge = (val << 2) & pmask;
1703
1704                         AR5K_EEPROM_READ(offset++, val);
1705                         rep[6].edge |= (val >> 14) & 0x3;
1706                         rep[7].edge = (val >> 8) & pmask;
1707                 }
1708                 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1709                         rep[j].freq = ath5k_eeprom_bin2freq(ee,
1710                                 rep[j].freq, ctl_mode);
1711                 }
1712                 rep += AR5K_EEPROM_N_EDGES;
1713         }
1714
1715         return 0;
1716 }
1717
1718 static int
1719 ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1720 {
1721         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1722         u32 offset;
1723         u16 val;
1724         int ret = 0, i;
1725
1726         offset = AR5K_EEPROM_CTL(ee->ee_version) +
1727                                 AR5K_EEPROM_N_CTLS(ee->ee_version);
1728
1729         if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1730                 /* No spur info for 5GHz */
1731                 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1732                 /* 2 channels for 2GHz (2464/2420) */
1733                 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1734                 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1735                 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1736         } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1737                 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1738                         AR5K_EEPROM_READ(offset, val);
1739                         ee->ee_spur_chans[i][0] = val;
1740                         AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
1741                                                                         val);
1742                         ee->ee_spur_chans[i][1] = val;
1743                         offset++;
1744                 }
1745         }
1746
1747         return ret;
1748 }
1749
1750 /*
1751  * Initialize eeprom data structure
1752  */
1753 int
1754 ath5k_eeprom_init(struct ath5k_hw *ah)
1755 {
1756         int err;
1757
1758         err = ath5k_eeprom_init_header(ah);
1759         if (err < 0)
1760                 return err;
1761
1762         err = ath5k_eeprom_init_modes(ah);
1763         if (err < 0)
1764                 return err;
1765
1766         err = ath5k_eeprom_read_pcal_info(ah);
1767         if (err < 0)
1768                 return err;
1769
1770         err = ath5k_eeprom_read_ctl_info(ah);
1771         if (err < 0)
1772                 return err;
1773
1774         err = ath5k_eeprom_read_spur_chans(ah);
1775         if (err < 0)
1776                 return err;
1777
1778         return 0;
1779 }
1780
1781 /*
1782  * Read the MAC address from eeprom
1783  */
1784 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
1785 {
1786         u8 mac_d[ETH_ALEN] = {};
1787         u32 total, offset;
1788         u16 data;
1789         int octet, ret;
1790
1791         ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
1792         if (ret)
1793                 return ret;
1794
1795         for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
1796                 ret = ath5k_hw_eeprom_read(ah, offset, &data);
1797                 if (ret)
1798                         return ret;
1799
1800                 total += data;
1801                 mac_d[octet + 1] = data & 0xff;
1802                 mac_d[octet] = data >> 8;
1803                 octet += 2;
1804         }
1805
1806         if (!total || total == 3 * 0xffff)
1807                 return -EINVAL;
1808
1809         memcpy(mac, mac_d, ETH_ALEN);
1810
1811         return 0;
1812 }