drivers/net/wireless/ath/ath5k/eeprom.c

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
   4  * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
   5  *
   6  * Permission to use, copy, modify, and distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 /*************************************\
  21 * EEPROM access functions and helpers *
  22 \*************************************/
  23
  24 #include <linux/slab.h>
  25
  26 #include "ath5k.h"
  27 #include "reg.h"
  28 #include "debug.h"
  29 #include "base.h"
  30
  31
  32 /******************\
  33 * Helper functions *
  34 \******************/
  35
  36 /*
  37  * Translate binary channel representation in EEPROM to frequency
  38  */
  39 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
  40                                                         unsigned int mode)
  41 {
  42         u16 val;
  43
  44         if (bin == AR5K_EEPROM_CHANNEL_DIS)
  45                 return bin;
  46
  47         if (mode == AR5K_EEPROM_MODE_11A) {
  48                 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
  49                         val = (5 * bin) + 4800;
  50                 else
  51                         val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
  52                                 (bin * 10) + 5100;
  53         } else {
  54                 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
  55                         val = bin + 2300;
  56                 else
  57                         val = bin + 2400;
  58         }
  59
  60         return val;
  61 }
  62
  63
  64 /*********\
  65 * Parsers *
  66 \*********/
  67
  68 /*
  69  * Initialize eeprom & capabilities structs
  70  */
  71 static int
  72 ath5k_eeprom_init_header(struct ath5k_hw *ah)
  73 {
  74         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  75         u16 val;
  76         u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
  77
  78         /*
  79          * Read values from EEPROM and store them in the capability structure
  80          */
  81         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
  82         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
  83         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
  84         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
  85         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
  86
  87         /* Return if we have an old EEPROM */
  88         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
  89                 return 0;
  90
  91         /*
  92          * Validate the checksum of the EEPROM date. There are some
  93          * devices with invalid EEPROMs.
  94          */
  95         AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
  96         if (val) {
  97                 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
  98                            AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
  99                 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
 100                 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
 101
 102                 /*
 103                  * Fail safe check to prevent stupid loops due
 104                  * to busted EEPROMs. XXX: This value is likely too
 105                  * big still, waiting on a better value.
 106                  */
 107                 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
 108                         ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
 109                                   "%d (0x%04x) max expected: %d (0x%04x)\n",
 110                                   eep_max, eep_max,
 111                                   3 * AR5K_EEPROM_INFO_MAX,
 112                                   3 * AR5K_EEPROM_INFO_MAX);
 113                         return -EIO;
 114                 }
 115         }
 116
 117         for (cksum = 0, offset = 0; offset < eep_max; offset++) {
 118                 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
 119                 cksum ^= val;
 120         }
 121         if (cksum != AR5K_EEPROM_INFO_CKSUM) {
 122                 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
 123                           "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
 124                           cksum, eep_max,
 125                           eep_max == AR5K_EEPROM_INFO_MAX ?
 126                                 "default size" : "custom size");
 127                 return -EIO;
 128         }
 129
 130         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
 131             ee_ant_gain);
 132
 133         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
 134                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
 135                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
 136
 137                 /* XXX: Don't know which versions include these two */
 138                 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
 139
 140                 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
 141                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
 142
 143                 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
 144                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
 145                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
 146                         AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
 147                 }
 148         }
 149
 150         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
 151                 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
 152                 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
 153                 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
 154
 155                 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
 156                 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
 157                 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
 158         }
 159
 160         AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
 161
 162         if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
 163                 ee->ee_is_hb63 = true;
 164         else
 165                 ee->ee_is_hb63 = false;
 166
 167         AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
 168         ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
 169         ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
 170
 171         /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
 172          * and enable serdes programming if needed.
 173          *
 174          * XXX: Serdes values seem to be fixed so
 175          * no need to read them here, we write them
 176          * during ath5k_hw_init */
 177         AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
 178         ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
 179                                                         true : false;
 180
 181         return 0;
 182 }
 183
 184
 185 /*
 186  * Read antenna infos from eeprom
 187  */
 188 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
 189                 unsigned int mode)
 190 {
 191         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 192         u32 o = *offset;
 193         u16 val;
 194         int i = 0;
 195
 196         AR5K_EEPROM_READ(o++, val);
 197         ee->ee_switch_settling[mode]    = (val >> 8) & 0x7f;
 198         ee->ee_atn_tx_rx[mode]          = (val >> 2) & 0x3f;
 199         ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
 200
 201         AR5K_EEPROM_READ(o++, val);
 202         ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
 203         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
 204         ee->ee_ant_control[mode][i++]   = val & 0x3f;
 205
 206         AR5K_EEPROM_READ(o++, val);
 207         ee->ee_ant_control[mode][i++]   = (val >> 10) & 0x3f;
 208         ee->ee_ant_control[mode][i++]   = (val >> 4) & 0x3f;
 209         ee->ee_ant_control[mode][i]     = (val << 2) & 0x3f;
 210
 211         AR5K_EEPROM_READ(o++, val);
 212         ee->ee_ant_control[mode][i++]   |= (val >> 14) & 0x3;
 213         ee->ee_ant_control[mode][i++]   = (val >> 8) & 0x3f;
 214         ee->ee_ant_control[mode][i++]   = (val >> 2) & 0x3f;
 215         ee->ee_ant_control[mode][i]     = (val << 4) & 0x3f;
 216
 217         AR5K_EEPROM_READ(o++, val);
 218         ee->ee_ant_control[mode][i++]   |= (val >> 12) & 0xf;
 219         ee->ee_ant_control[mode][i++]   = (val >> 6) & 0x3f;
 220         ee->ee_ant_control[mode][i++]   = val & 0x3f;
 221
 222         /* Get antenna switch tables */
 223         ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
 224             (ee->ee_ant_control[mode][0] << 4);
 225         ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
 226              ee->ee_ant_control[mode][1]        |
 227             (ee->ee_ant_control[mode][2] << 6)  |
 228             (ee->ee_ant_control[mode][3] << 12) |
 229             (ee->ee_ant_control[mode][4] << 18) |
 230             (ee->ee_ant_control[mode][5] << 24);
 231         ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
 232              ee->ee_ant_control[mode][6]        |
 233             (ee->ee_ant_control[mode][7] << 6)  |
 234             (ee->ee_ant_control[mode][8] << 12) |
 235             (ee->ee_ant_control[mode][9] << 18) |
 236             (ee->ee_ant_control[mode][10] << 24);
 237
 238         /* return new offset */
 239         *offset = o;
 240
 241         return 0;
 242 }
 243
 244 /*
 245  * Read supported modes and some mode-specific calibration data
 246  * from eeprom
 247  */
 248 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
 249                 unsigned int mode)
 250 {
 251         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 252         u32 o = *offset;
 253         u16 val;
 254
 255         ee->ee_n_piers[mode] = 0;
 256         AR5K_EEPROM_READ(o++, val);
 257         ee->ee_adc_desired_size[mode]   = (s8)((val >> 8) & 0xff);
 258         switch(mode) {
 259         case AR5K_EEPROM_MODE_11A:
 260                 ee->ee_ob[mode][3]      = (val >> 5) & 0x7;
 261                 ee->ee_db[mode][3]      = (val >> 2) & 0x7;
 262                 ee->ee_ob[mode][2]      = (val << 1) & 0x7;
 263
 264                 AR5K_EEPROM_READ(o++, val);
 265                 ee->ee_ob[mode][2]      |= (val >> 15) & 0x1;
 266                 ee->ee_db[mode][2]      = (val >> 12) & 0x7;
 267                 ee->ee_ob[mode][1]      = (val >> 9) & 0x7;
 268                 ee->ee_db[mode][1]      = (val >> 6) & 0x7;
 269                 ee->ee_ob[mode][0]      = (val >> 3) & 0x7;
 270                 ee->ee_db[mode][0]      = val & 0x7;
 271                 break;
 272         case AR5K_EEPROM_MODE_11G:
 273         case AR5K_EEPROM_MODE_11B:
 274                 ee->ee_ob[mode][1]      = (val >> 4) & 0x7;
 275                 ee->ee_db[mode][1]      = val & 0x7;
 276                 break;
 277         }
 278
 279         AR5K_EEPROM_READ(o++, val);
 280         ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
 281         ee->ee_thr_62[mode]             = val & 0xff;
 282
 283         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
 284                 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
 285
 286         AR5K_EEPROM_READ(o++, val);
 287         ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
 288         ee->ee_tx_frm2xpa_enable[mode]  = val & 0xff;
 289
 290         AR5K_EEPROM_READ(o++, val);
 291         ee->ee_pga_desired_size[mode]   = (val >> 8) & 0xff;
 292
 293         if ((val & 0xff) & 0x80)
 294                 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
 295         else
 296                 ee->ee_noise_floor_thr[mode] = val & 0xff;
 297
 298         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
 299                 ee->ee_noise_floor_thr[mode] =
 300                     mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
 301
 302         AR5K_EEPROM_READ(o++, val);
 303         ee->ee_xlna_gain[mode]          = (val >> 5) & 0xff;
 304         ee->ee_x_gain[mode]             = (val >> 1) & 0xf;
 305         ee->ee_xpd[mode]                = val & 0x1;
 306
 307         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
 308             mode != AR5K_EEPROM_MODE_11B)
 309                 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
 310
 311         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
 312                 AR5K_EEPROM_READ(o++, val);
 313                 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
 314
 315                 if (mode == AR5K_EEPROM_MODE_11A)
 316                         ee->ee_xr_power[mode] = val & 0x3f;
 317                 else {
 318                         /* b_DB_11[bg] and b_OB_11[bg] */
 319                         ee->ee_ob[mode][0] = val & 0x7;
 320                         ee->ee_db[mode][0] = (val >> 3) & 0x7;
 321                 }
 322         }
 323
 324         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
 325                 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
 326                 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
 327         } else {
 328                 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
 329
 330                 AR5K_EEPROM_READ(o++, val);
 331                 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
 332
 333                 if (mode == AR5K_EEPROM_MODE_11G) {
 334                         ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
 335                         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
 336                                 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
 337                 }
 338         }
 339
 340         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
 341                         mode == AR5K_EEPROM_MODE_11A) {
 342                 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
 343                 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
 344         }
 345
 346         if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
 347                 goto done;
 348
 349         /* Note: >= v5 have bg freq piers on another location
 350          * so these freq piers are ignored for >= v5 (should be 0xff
 351          * anyway) */
 352         switch(mode) {
 353         case AR5K_EEPROM_MODE_11A:
 354                 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
 355                         break;
 356
 357                 AR5K_EEPROM_READ(o++, val);
 358                 ee->ee_margin_tx_rx[mode] = val & 0x3f;
 359                 break;
 360         case AR5K_EEPROM_MODE_11B:
 361                 AR5K_EEPROM_READ(o++, val);
 362
 363                 ee->ee_pwr_cal_b[0].freq =
 364                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 365                 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
 366                         ee->ee_n_piers[mode]++;
 367
 368                 ee->ee_pwr_cal_b[1].freq =
 369                         ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
 370                 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
 371                         ee->ee_n_piers[mode]++;
 372
 373                 AR5K_EEPROM_READ(o++, val);
 374                 ee->ee_pwr_cal_b[2].freq =
 375                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 376                 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
 377                         ee->ee_n_piers[mode]++;
 378
 379                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 380                         ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 381                 break;
 382         case AR5K_EEPROM_MODE_11G:
 383                 AR5K_EEPROM_READ(o++, val);
 384
 385                 ee->ee_pwr_cal_g[0].freq =
 386                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 387                 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
 388                         ee->ee_n_piers[mode]++;
 389
 390                 ee->ee_pwr_cal_g[1].freq =
 391                         ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
 392                 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
 393                         ee->ee_n_piers[mode]++;
 394
 395                 AR5K_EEPROM_READ(o++, val);
 396                 ee->ee_turbo_max_power[mode] = val & 0x7f;
 397                 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
 398
 399                 AR5K_EEPROM_READ(o++, val);
 400                 ee->ee_pwr_cal_g[2].freq =
 401                         ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
 402                 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
 403                         ee->ee_n_piers[mode]++;
 404
 405                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
 406                         ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
 407
 408                 AR5K_EEPROM_READ(o++, val);
 409                 ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
 410                 ee->ee_q_cal[mode] = val & 0x1f;
 411
 412                 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
 413                         AR5K_EEPROM_READ(o++, val);
 414                         ee->ee_cck_ofdm_gain_delta = val & 0xff;
 415                 }
 416                 break;
 417         }
 418
 419         /*
 420          * Read turbo mode information on newer EEPROM versions
 421          */
 422         if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
 423                 goto done;
 424
 425         switch (mode){
 426         case AR5K_EEPROM_MODE_11A:
 427                 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
 428
 429                 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
 430                 AR5K_EEPROM_READ(o++, val);
 431                 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
 432                 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
 433
 434                 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
 435                 AR5K_EEPROM_READ(o++, val);
 436                 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
 437                 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
 438
 439                 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
 440                         ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
 441                 break;
 442         case AR5K_EEPROM_MODE_11G:
 443                 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
 444
 445                 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
 446                 AR5K_EEPROM_READ(o++, val);
 447                 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
 448                 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
 449
 450                 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
 451                 AR5K_EEPROM_READ(o++, val);
 452                 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
 453                 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
 454                 break;
 455         }
 456
 457 done:
 458         /* return new offset */
 459         *offset = o;
 460
 461         return 0;
 462 }
 463
 464 /* Read mode-specific data (except power calibration data) */
 465 static int
 466 ath5k_eeprom_init_modes(struct ath5k_hw *ah)
 467 {
 468         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 469         u32 mode_offset[3];
 470         unsigned int mode;
 471         u32 offset;
 472         int ret;
 473
 474         /*
 475          * Get values for all modes
 476          */
 477         mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
 478         mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
 479         mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
 480
 481         ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
 482                 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
 483
 484         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
 485                 offset = mode_offset[mode];
 486
 487                 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
 488                 if (ret)
 489                         return ret;
 490
 491                 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
 492                 if (ret)
 493                         return ret;
 494         }
 495
 496         /* override for older eeprom versions for better performance */
 497         if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
 498                 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
 499                 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
 500                 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
 501         }
 502
 503         return 0;
 504 }
 505
 506 /* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
 507  * frequency mask) */
 508 static inline int
 509 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
 510                         struct ath5k_chan_pcal_info *pc, unsigned int mode)
 511 {
 512         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 513         int o = *offset;
 514         int i = 0;
 515         u8 freq1, freq2;
 516         u16 val;
 517
 518         ee->ee_n_piers[mode] = 0;
 519         while(i < max) {
 520                 AR5K_EEPROM_READ(o++, val);
 521
 522                 freq1 = val & 0xff;
 523                 if (!freq1)
 524                         break;
 525
 526                 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
 527                                 freq1, mode);
 528                 ee->ee_n_piers[mode]++;
 529
 530                 freq2 = (val >> 8) & 0xff;
 531                 if (!freq2)
 532                         break;
 533
 534                 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
 535                                 freq2, mode);
 536                 ee->ee_n_piers[mode]++;
 537         }
 538
 539         /* return new offset */
 540         *offset = o;
 541
 542         return 0;
 543 }
 544
 545 /* Read frequency piers for 802.11a */
 546 static int
 547 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
 548 {
 549         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 550         struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
 551         int i;
 552         u16 val;
 553         u8 mask;
 554
 555         if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
 556                 ath5k_eeprom_read_freq_list(ah, &offset,
 557                         AR5K_EEPROM_N_5GHZ_CHAN, pcal,
 558                         AR5K_EEPROM_MODE_11A);
 559         } else {
 560                 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
 561
 562                 AR5K_EEPROM_READ(offset++, val);
 563                 pcal[0].freq  = (val >> 9) & mask;
 564                 pcal[1].freq  = (val >> 2) & mask;
 565                 pcal[2].freq  = (val << 5) & mask;
 566
 567                 AR5K_EEPROM_READ(offset++, val);
 568                 pcal[2].freq |= (val >> 11) & 0x1f;
 569                 pcal[3].freq  = (val >> 4) & mask;
 570                 pcal[4].freq  = (val << 3) & mask;
 571
 572                 AR5K_EEPROM_READ(offset++, val);
 573                 pcal[4].freq |= (val >> 13) & 0x7;
 574                 pcal[5].freq  = (val >> 6) & mask;
 575                 pcal[6].freq  = (val << 1) & mask;
 576
 577                 AR5K_EEPROM_READ(offset++, val);
 578                 pcal[6].freq |= (val >> 15) & 0x1;
 579                 pcal[7].freq  = (val >> 8) & mask;
 580                 pcal[8].freq  = (val >> 1) & mask;
 581                 pcal[9].freq  = (val << 6) & mask;
 582
 583                 AR5K_EEPROM_READ(offset++, val);
 584                 pcal[9].freq |= (val >> 10) & 0x3f;
 585
 586                 /* Fixed number of piers */
 587                 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
 588
 589                 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
 590                         pcal[i].freq = ath5k_eeprom_bin2freq(ee,
 591                                 pcal[i].freq, AR5K_EEPROM_MODE_11A);
 592                 }
 593         }
 594
 595         return 0;
 596 }
 597
 598 /* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
 599 static inline int
 600 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
 601 {
 602         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 603         struct ath5k_chan_pcal_info *pcal;
 604
 605         switch(mode) {
 606         case AR5K_EEPROM_MODE_11B:
 607                 pcal = ee->ee_pwr_cal_b;
 608                 break;
 609         case AR5K_EEPROM_MODE_11G:
 610                 pcal = ee->ee_pwr_cal_g;
 611                 break;
 612         default:
 613                 return -EINVAL;
 614         }
 615
 616         ath5k_eeprom_read_freq_list(ah, &offset,
 617                 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
 618                 mode);
 619
 620         return 0;
 621 }
 622
 623
 624 /*
 625  * Read power calibration for RF5111 chips
 626  *
 627  * For RF5111 we have an XPD -eXternal Power Detector- curve
 628  * for each calibrated channel. Each curve has 0,5dB Power steps
 629  * on x axis and PCDAC steps (offsets) on y axis and looks like an
 630  * exponential function. To recreate the curve we read 11 points
 631  * here and interpolate later.
 632  */
 633
 634 /* Used to match PCDAC steps with power values on RF5111 chips
 635  * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
 636  * steps that match with the power values we read from eeprom. On
 637  * older eeprom versions (< 3.2) these steps are equaly spaced at
 638  * 10% of the pcdac curve -until the curve reaches its maximum-
 639  * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
 640  * these 11 steps are spaced in a different way. This function returns
 641  * the pcdac steps based on eeprom version and curve min/max so that we
 642  * can have pcdac/pwr points.
 643  */
 644 static inline void
 645 ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
 646 {
 647         static const u16 intercepts3[] =
 648                 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
 649         static const u16 intercepts3_2[] =
 650                 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
 651         const u16 *ip;
 652         int i;
 653
 654         if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
 655                 ip = intercepts3_2;
 656         else
 657                 ip = intercepts3;
 658
 659         for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
 660                 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
 661 }
 662
 663 static int
 664 ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
 665 {
 666         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 667         struct ath5k_chan_pcal_info *chinfo;
 668         u8 pier, pdg;
 669
 670         switch (mode) {
 671         case AR5K_EEPROM_MODE_11A:
 672                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
 673                         return 0;
 674                 chinfo = ee->ee_pwr_cal_a;
 675                 break;
 676         case AR5K_EEPROM_MODE_11B:
 677                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
 678                         return 0;
 679                 chinfo = ee->ee_pwr_cal_b;
 680                 break;
 681         case AR5K_EEPROM_MODE_11G:
 682                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
 683                         return 0;
 684                 chinfo = ee->ee_pwr_cal_g;
 685                 break;
 686         default:
 687                 return -EINVAL;
 688         }
 689
 690         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
 691                 if (!chinfo[pier].pd_curves)
 692                         continue;
 693
 694                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
 695                         struct ath5k_pdgain_info *pd =
 696                                         &chinfo[pier].pd_curves[pdg];
 697
 698                         if (pd != NULL) {
 699                                 kfree(pd->pd_step);
 700                                 kfree(pd->pd_pwr);
 701                         }
 702                 }
 703
 704                 kfree(chinfo[pier].pd_curves);
 705         }
 706
 707         return 0;
 708 }
 709
 710 /* Convert RF5111 specific data to generic raw data
 711  * used by interpolation code */
 712 static int
 713 ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
 714                                 struct ath5k_chan_pcal_info *chinfo)
 715 {
 716         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 717         struct ath5k_chan_pcal_info_rf5111 *pcinfo;
 718         struct ath5k_pdgain_info *pd;
 719         u8 pier, point, idx;
 720         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
 721
 722         /* Fill raw data for each calibration pier */
 723         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
 724
 725                 pcinfo = &chinfo[pier].rf5111_info;
 726
 727                 /* Allocate pd_curves for this cal pier */
 728                 chinfo[pier].pd_curves =
 729                         kcalloc(AR5K_EEPROM_N_PD_CURVES,
 730                                 sizeof(struct ath5k_pdgain_info),
 731                                 GFP_KERNEL);
 732
 733                 if (!chinfo[pier].pd_curves)
 734                         goto err_out;
 735
 736                 /* Only one curve for RF5111
 737                  * find out which one and place
 738                  * in pd_curves.
 739                  * Note: ee_x_gain is reversed here */
 740                 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
 741
 742                         if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
 743                                 pdgain_idx[0] = idx;
 744                                 break;
 745                         }
 746                 }
 747
 748                 ee->ee_pd_gains[mode] = 1;
 749
 750                 pd = &chinfo[pier].pd_curves[idx];
 751
 752                 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
 753
 754                 /* Allocate pd points for this curve */
 755                 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
 756                                         sizeof(u8), GFP_KERNEL);
 757                 if (!pd->pd_step)
 758                         goto err_out;
 759
 760                 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
 761                                         sizeof(s16), GFP_KERNEL);
 762                 if (!pd->pd_pwr)
 763                         goto err_out;
 764
 765                 /* Fill raw dataset
 766                  * (convert power to 0.25dB units
 767                  * for RF5112 combatibility) */
 768                 for (point = 0; point < pd->pd_points; point++) {
 769
 770                         /* Absolute values */
 771                         pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
 772
 773                         /* Already sorted */
 774                         pd->pd_step[point] = pcinfo->pcdac[point];
 775                 }
 776
 777                 /* Set min/max pwr */
 778                 chinfo[pier].min_pwr = pd->pd_pwr[0];
 779                 chinfo[pier].max_pwr = pd->pd_pwr[10];
 780
 781         }
 782
 783         return 0;
 784
 785 err_out:
 786         ath5k_eeprom_free_pcal_info(ah, mode);
 787         return -ENOMEM;
 788 }
 789
 790 /* Parse EEPROM data */
 791 static int
 792 ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
 793 {
 794         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 795         struct ath5k_chan_pcal_info *pcal;
 796         int offset, ret;
 797         int i;
 798         u16 val;
 799
 800         offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
 801         switch(mode) {
 802         case AR5K_EEPROM_MODE_11A:
 803                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
 804                         return 0;
 805
 806                 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
 807                         offset + AR5K_EEPROM_GROUP1_OFFSET);
 808                 if (ret < 0)
 809                         return ret;
 810
 811                 offset += AR5K_EEPROM_GROUP2_OFFSET;
 812                 pcal = ee->ee_pwr_cal_a;
 813                 break;
 814         case AR5K_EEPROM_MODE_11B:
 815                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
 816                     !AR5K_EEPROM_HDR_11G(ee->ee_header))
 817                         return 0;
 818
 819                 pcal = ee->ee_pwr_cal_b;
 820                 offset += AR5K_EEPROM_GROUP3_OFFSET;
 821
 822                 /* fixed piers */
 823                 pcal[0].freq = 2412;
 824                 pcal[1].freq = 2447;
 825                 pcal[2].freq = 2484;
 826                 ee->ee_n_piers[mode] = 3;
 827                 break;
 828         case AR5K_EEPROM_MODE_11G:
 829                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
 830                         return 0;
 831
 832                 pcal = ee->ee_pwr_cal_g;
 833                 offset += AR5K_EEPROM_GROUP4_OFFSET;
 834
 835                 /* fixed piers */
 836                 pcal[0].freq = 2312;
 837                 pcal[1].freq = 2412;
 838                 pcal[2].freq = 2484;
 839                 ee->ee_n_piers[mode] = 3;
 840                 break;
 841         default:
 842                 return -EINVAL;
 843         }
 844
 845         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
 846                 struct ath5k_chan_pcal_info_rf5111 *cdata =
 847                         &pcal[i].rf5111_info;
 848
 849                 AR5K_EEPROM_READ(offset++, val);
 850                 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
 851                 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
 852                 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
 853
 854                 AR5K_EEPROM_READ(offset++, val);
 855                 cdata->pwr[0] |= ((val >> 14) & 0x3);
 856                 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
 857                 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
 858                 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
 859
 860                 AR5K_EEPROM_READ(offset++, val);
 861                 cdata->pwr[3] |= ((val >> 12) & 0xf);
 862                 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
 863                 cdata->pwr[5] = (val  & AR5K_EEPROM_POWER_M);
 864
 865                 AR5K_EEPROM_READ(offset++, val);
 866                 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
 867                 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
 868                 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
 869
 870                 AR5K_EEPROM_READ(offset++, val);
 871                 cdata->pwr[8] |= ((val >> 14) & 0x3);
 872                 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
 873                 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
 874
 875                 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
 876                         cdata->pcdac_max, cdata->pcdac);
 877         }
 878
 879         return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
 880 }
 881
 882
 883 /*
 884  * Read power calibration for RF5112 chips
 885  *
 886  * For RF5112 we have 4 XPD -eXternal Power Detector- curves
 887  * for each calibrated channel on 0, -6, -12 and -18dbm but we only
 888  * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
 889  * power steps on x axis and PCDAC steps on y axis and looks like a
 890  * linear function. To recreate the curve and pass the power values
 891  * on hw, we read 4 points for xpd 0 (lower gain -> max power)
 892  * and 3 points for xpd 3 (higher gain -> lower power) here and
 893  * interpolate later.
 894  *
 895  * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
 896  */
 897
 898 /* Convert RF5112 specific data to generic raw data
 899  * used by interpolation code */
 900 static int
 901 ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
 902                                 struct ath5k_chan_pcal_info *chinfo)
 903 {
 904         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
 905         struct ath5k_chan_pcal_info_rf5112 *pcinfo;
 906         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
 907         unsigned int pier, pdg, point;
 908
 909         /* Fill raw data for each calibration pier */
 910         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
 911
 912                 pcinfo = &chinfo[pier].rf5112_info;
 913
 914                 /* Allocate pd_curves for this cal pier */
 915                 chinfo[pier].pd_curves =
 916                                 kcalloc(AR5K_EEPROM_N_PD_CURVES,
 917                                         sizeof(struct ath5k_pdgain_info),
 918                                         GFP_KERNEL);
 919
 920                 if (!chinfo[pier].pd_curves)
 921                         goto err_out;
 922
 923                 /* Fill pd_curves */
 924                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
 925
 926                         u8 idx = pdgain_idx[pdg];
 927                         struct ath5k_pdgain_info *pd =
 928                                         &chinfo[pier].pd_curves[idx];
 929
 930                         /* Lowest gain curve (max power) */
 931                         if (pdg == 0) {
 932                                 /* One more point for better accuracy */
 933                                 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
 934
 935                                 /* Allocate pd points for this curve */
 936                                 pd->pd_step = kcalloc(pd->pd_points,
 937                                                 sizeof(u8), GFP_KERNEL);
 938
 939                                 if (!pd->pd_step)
 940                                         goto err_out;
 941
 942                                 pd->pd_pwr = kcalloc(pd->pd_points,
 943                                                 sizeof(s16), GFP_KERNEL);
 944
 945                                 if (!pd->pd_pwr)
 946                                         goto err_out;
 947
 948                                 /* Fill raw dataset
 949                                  * (all power levels are in 0.25dB units) */
 950                                 pd->pd_step[0] = pcinfo->pcdac_x0[0];
 951                                 pd->pd_pwr[0] = pcinfo->pwr_x0[0];
 952
 953                                 for (point = 1; point < pd->pd_points;
 954                                 point++) {
 955                                         /* Absolute values */
 956                                         pd->pd_pwr[point] =
 957                                                 pcinfo->pwr_x0[point];
 958
 959                                         /* Deltas */
 960                                         pd->pd_step[point] =
 961                                                 pd->pd_step[point - 1] +
 962                                                 pcinfo->pcdac_x0[point];
 963                                 }
 964
 965                                 /* Set min power for this frequency */
 966                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
 967
 968                         /* Highest gain curve (min power) */
 969                         } else if (pdg == 1) {
 970
 971                                 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
 972
 973                                 /* Allocate pd points for this curve */
 974                                 pd->pd_step = kcalloc(pd->pd_points,
 975                                                 sizeof(u8), GFP_KERNEL);
 976
 977                                 if (!pd->pd_step)
 978                                         goto err_out;
 979
 980                                 pd->pd_pwr = kcalloc(pd->pd_points,
 981                                                 sizeof(s16), GFP_KERNEL);
 982
 983                                 if (!pd->pd_pwr)
 984                                         goto err_out;
 985
 986                                 /* Fill raw dataset
 987                                  * (all power levels are in 0.25dB units) */
 988                                 for (point = 0; point < pd->pd_points;
 989                                 point++) {
 990                                         /* Absolute values */
 991                                         pd->pd_pwr[point] =
 992                                                 pcinfo->pwr_x3[point];
 993
 994                                         /* Fixed points */
 995                                         pd->pd_step[point] =
 996                                                 pcinfo->pcdac_x3[point];
 997                                 }
 998
 999                                 /* Since we have a higher gain curve
1000                                  * override min power */
1001                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
1002                         }
1003                 }
1004         }
1005
1006         return 0;
1007
1008 err_out:
1009         ath5k_eeprom_free_pcal_info(ah, mode);
1010         return -ENOMEM;
1011 }
1012
1013 /* Parse EEPROM data */
1014 static int
1015 ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
1016 {
1017         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1018         struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
1019         struct ath5k_chan_pcal_info *gen_chan_info;
1020         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1021         u32 offset;
1022         u8 i, c;
1023         u16 val;
1024         u8 pd_gains = 0;
1025
1026         /* Count how many curves we have and
1027          * identify them (which one of the 4
1028          * available curves we have on each count).
1029          * Curves are stored from lower (x0) to
1030          * higher (x3) gain */
1031         for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
1032                 /* ee_x_gain[mode] is x gain mask */
1033                 if ((ee->ee_x_gain[mode] >> i) & 0x1)
1034                         pdgain_idx[pd_gains++] = i;
1035         }
1036         ee->ee_pd_gains[mode] = pd_gains;
1037
1038         if (pd_gains == 0 || pd_gains > 2)
1039                 return -EINVAL;
1040
1041         switch (mode) {
1042         case AR5K_EEPROM_MODE_11A:
1043                 /*
1044                  * Read 5GHz EEPROM channels
1045                  */
1046                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1047                 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1048
1049                 offset += AR5K_EEPROM_GROUP2_OFFSET;
1050                 gen_chan_info = ee->ee_pwr_cal_a;
1051                 break;
1052         case AR5K_EEPROM_MODE_11B:
1053                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1054                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1055                         offset += AR5K_EEPROM_GROUP3_OFFSET;
1056
1057                 /* NB: frequency piers parsed during mode init */
1058                 gen_chan_info = ee->ee_pwr_cal_b;
1059                 break;
1060         case AR5K_EEPROM_MODE_11G:
1061                 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1062                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1063                         offset += AR5K_EEPROM_GROUP4_OFFSET;
1064                 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1065                         offset += AR5K_EEPROM_GROUP2_OFFSET;
1066
1067                 /* NB: frequency piers parsed during mode init */
1068                 gen_chan_info = ee->ee_pwr_cal_g;
1069                 break;
1070         default:
1071                 return -EINVAL;
1072         }
1073
1074         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1075                 chan_pcal_info = &gen_chan_info[i].rf5112_info;
1076
1077                 /* Power values in quarter dB
1078                  * for the lower xpd gain curve
1079                  * (0 dBm -> higher output power) */
1080                 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
1081                         AR5K_EEPROM_READ(offset++, val);
1082                         chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
1083                         chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
1084                 }
1085
1086                 /* PCDAC steps
1087                  * corresponding to the above power
1088                  * measurements */
1089                 AR5K_EEPROM_READ(offset++, val);
1090                 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
1091                 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
1092                 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
1093
1094                 /* Power values in quarter dB
1095                  * for the higher xpd gain curve
1096                  * (18 dBm -> lower output power) */
1097                 AR5K_EEPROM_READ(offset++, val);
1098                 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
1099                 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
1100
1101                 AR5K_EEPROM_READ(offset++, val);
1102                 chan_pcal_info->pwr_x3[2] = (val & 0xff);
1103
1104                 /* PCDAC steps
1105                  * corresponding to the above power
1106                  * measurements (fixed) */
1107                 chan_pcal_info->pcdac_x3[0] = 20;
1108                 chan_pcal_info->pcdac_x3[1] = 35;
1109                 chan_pcal_info->pcdac_x3[2] = 63;
1110
1111                 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
1112                         chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
1113
1114                         /* Last xpd0 power level is also channel maximum */
1115                         gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
1116                 } else {
1117                         chan_pcal_info->pcdac_x0[0] = 1;
1118                         gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
1119                 }
1120
1121         }
1122
1123         return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1124 }
1125
1126
1127 /*
1128  * Read power calibration for RF2413 chips
1129  *
1130  * For RF2413 we have a Power to PDDAC table (Power Detector)
1131  * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1132  * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
1133  * axis and looks like an exponential function like the RF5111 curve.
1134  *
1135  * To recreate the curves we read here the points and interpolate
1136  * later. Note that in most cases only 2 (higher and lower) curves are
1137  * used (like RF5112) but vendors have the opportunity to include all
1138  * 4 curves on eeprom. The final curve (higher power) has an extra
1139  * point for better accuracy like RF5112.
1140  */
1141
1142 /* For RF2413 power calibration data doesn't start on a fixed location and
1143  * if a mode is not supported, its section is missing -not zeroed-.
1144  * So we need to calculate the starting offset for each section by using
1145  * these two functions */
1146
1147 /* Return the size of each section based on the mode and the number of pd
1148  * gains available (maximum 4). */
1149 static inline unsigned int
1150 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1151 {
1152         static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1153         unsigned int sz;
1154
1155         sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1156         sz *= ee->ee_n_piers[mode];
1157
1158         return sz;
1159 }
1160
1161 /* Return the starting offset for a section based on the modes supported
1162  * and each section's size. */
1163 static unsigned int
1164 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1165 {
1166         u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1167
1168         switch(mode) {
1169         case AR5K_EEPROM_MODE_11G:
1170                 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1171                         offset += ath5k_pdgains_size_2413(ee,
1172                                         AR5K_EEPROM_MODE_11B) +
1173                                         AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1174                 /* fall through */
1175         case AR5K_EEPROM_MODE_11B:
1176                 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1177                         offset += ath5k_pdgains_size_2413(ee,
1178                                         AR5K_EEPROM_MODE_11A) +
1179                                         AR5K_EEPROM_N_5GHZ_CHAN / 2;
1180                 /* fall through */
1181         case AR5K_EEPROM_MODE_11A:
1182                 break;
1183         default:
1184                 break;
1185         }
1186
1187         return offset;
1188 }
1189
1190 /* Convert RF2413 specific data to generic raw data
1191  * used by interpolation code */
1192 static int
1193 ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1194                                 struct ath5k_chan_pcal_info *chinfo)
1195 {
1196         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1197         struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1198         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1199         unsigned int pier, pdg, point;
1200
1201         /* Fill raw data for each calibration pier */
1202         for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1203
1204                 pcinfo = &chinfo[pier].rf2413_info;
1205
1206                 /* Allocate pd_curves for this cal pier */
1207                 chinfo[pier].pd_curves =
1208                                 kcalloc(AR5K_EEPROM_N_PD_CURVES,
1209                                         sizeof(struct ath5k_pdgain_info),
1210                                         GFP_KERNEL);
1211
1212                 if (!chinfo[pier].pd_curves)
1213                         goto err_out;
1214
1215                 /* Fill pd_curves */
1216                 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1217
1218                         u8 idx = pdgain_idx[pdg];
1219                         struct ath5k_pdgain_info *pd =
1220                                         &chinfo[pier].pd_curves[idx];
1221
1222                         /* One more point for the highest power
1223                          * curve (lowest gain) */
1224                         if (pdg == ee->ee_pd_gains[mode] - 1)
1225                                 pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
1226                         else
1227                                 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
1228
1229                         /* Allocate pd points for this curve */
1230                         pd->pd_step = kcalloc(pd->pd_points,
1231                                         sizeof(u8), GFP_KERNEL);
1232
1233                         if (!pd->pd_step)
1234                                 goto err_out;
1235
1236                         pd->pd_pwr = kcalloc(pd->pd_points,
1237                                         sizeof(s16), GFP_KERNEL);
1238
1239                         if (!pd->pd_pwr)
1240                                 goto err_out;
1241
1242                         /* Fill raw dataset
1243                          * convert all pwr levels to
1244                          * quarter dB for RF5112 combatibility */
1245                         pd->pd_step[0] = pcinfo->pddac_i[pdg];
1246                         pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1247
1248                         for (point = 1; point < pd->pd_points; point++) {
1249
1250                                 pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
1251                                         2 * pcinfo->pwr[pdg][point - 1];
1252
1253                                 pd->pd_step[point] = pd->pd_step[point - 1] +
1254                                                 pcinfo->pddac[pdg][point - 1];
1255
1256                         }
1257
1258                         /* Highest gain curve -> min power */
1259                         if (pdg == 0)
1260                                 chinfo[pier].min_pwr = pd->pd_pwr[0];
1261
1262                         /* Lowest gain curve -> max power */
1263                         if (pdg == ee->ee_pd_gains[mode] - 1)
1264                                 chinfo[pier].max_pwr =
1265                                         pd->pd_pwr[pd->pd_points - 1];
1266                 }
1267         }
1268
1269         return 0;
1270
1271 err_out:
1272         ath5k_eeprom_free_pcal_info(ah, mode);
1273         return -ENOMEM;
1274 }
1275
1276 /* Parse EEPROM data */
1277 static int
1278 ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1279 {
1280         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1281         struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1282         struct ath5k_chan_pcal_info *chinfo;
1283         u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1284         u32 offset;
1285         int idx, i;
1286         u16 val;
1287         u8 pd_gains = 0;
1288
1289         /* Count how many curves we have and
1290          * identify them (which one of the 4
1291          * available curves we have on each count).
1292          * Curves are stored from higher to
1293          * lower gain so we go backwards */
1294         for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
1295                 /* ee_x_gain[mode] is x gain mask */
1296                 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1297                         pdgain_idx[pd_gains++] = idx;
1298
1299         }
1300         ee->ee_pd_gains[mode] = pd_gains;
1301
1302         if (pd_gains == 0)
1303                 return -EINVAL;
1304
1305         offset = ath5k_cal_data_offset_2413(ee, mode);
1306         switch (mode) {
1307         case AR5K_EEPROM_MODE_11A:
1308                 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1309                         return 0;
1310
1311                 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1312                 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
1313                 chinfo = ee->ee_pwr_cal_a;
1314                 break;
1315         case AR5K_EEPROM_MODE_11B:
1316                 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1317                         return 0;
1318
1319                 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1320                 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1321                 chinfo = ee->ee_pwr_cal_b;
1322                 break;
1323         case AR5K_EEPROM_MODE_11G:
1324                 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1325                         return 0;
1326
1327                 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1328                 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1329                 chinfo = ee->ee_pwr_cal_g;
1330                 break;
1331         default:
1332                 return -EINVAL;
1333         }
1334
1335         for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1336                 pcinfo = &chinfo[i].rf2413_info;
1337
1338                 /*
1339                  * Read pwr_i, pddac_i and the first
1340                  * 2 pd points (pwr, pddac)
1341                  */
1342                 AR5K_EEPROM_READ(offset++, val);
1343                 pcinfo->pwr_i[0] = val & 0x1f;
1344                 pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
1345                 pcinfo->pwr[0][0] = (val >> 12) & 0xf;
1346
1347                 AR5K_EEPROM_READ(offset++, val);
1348                 pcinfo->pddac[0][0] = val & 0x3f;
1349                 pcinfo->pwr[0][1] = (val >> 6) & 0xf;
1350                 pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
1351
1352                 AR5K_EEPROM_READ(offset++, val);
1353                 pcinfo->pwr[0][2] = val & 0xf;
1354                 pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
1355
1356                 pcinfo->pwr[0][3] = 0;
1357                 pcinfo->pddac[0][3] = 0;
1358
1359                 if (pd_gains > 1) {
1360                         /*
1361                          * Pd gain 0 is not the last pd gain
1362                          * so it only has 2 pd points.
1363                          * Continue with pd gain 1.
1364                          */
1365                         pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
1366
1367                         pcinfo->pddac_i[1] = (val >> 15) & 0x1;
1368                         AR5K_EEPROM_READ(offset++, val);
1369                         pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
1370
1371                         pcinfo->pwr[1][0] = (val >> 6) & 0xf;
1372                         pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
1373
1374                         AR5K_EEPROM_READ(offset++, val);
1375                         pcinfo->pwr[1][1] = val & 0xf;
1376                         pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
1377                         pcinfo->pwr[1][2] = (val >> 10) & 0xf;
1378
1379                         pcinfo->pddac[1][2] = (val >> 14) & 0x3;
1380                         AR5K_EEPROM_READ(offset++, val);
1381                         pcinfo->pddac[1][2] |= (val & 0xF) << 2;
1382
1383                         pcinfo->pwr[1][3] = 0;
1384                         pcinfo->pddac[1][3] = 0;
1385                 } else if (pd_gains == 1) {
1386                         /*
1387                          * Pd gain 0 is the last one so
1388                          * read the extra point.
1389                          */
1390                         pcinfo->pwr[0][3] = (val >> 10) & 0xf;
1391
1392                         pcinfo->pddac[0][3] = (val >> 14) & 0x3;
1393                         AR5K_EEPROM_READ(offset++, val);
1394                         pcinfo->pddac[0][3] |= (val & 0xF) << 2;
1395                 }
1396
1397                 /*
1398                  * Proceed with the other pd_gains
1399                  * as above.
1400                  */
1401                 if (pd_gains > 2) {
1402                         pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
1403                         pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
1404
1405                         AR5K_EEPROM_READ(offset++, val);
1406                         pcinfo->pwr[2][0] = (val >> 0) & 0xf;
1407                         pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
1408                         pcinfo->pwr[2][1] = (val >> 10) & 0xf;
1409
1410                         pcinfo->pddac[2][1] = (val >> 14) & 0x3;
1411                         AR5K_EEPROM_READ(offset++, val);
1412                         pcinfo->pddac[2][1] |= (val & 0xF) << 2;
1413
1414                         pcinfo->pwr[2][2] = (val >> 4) & 0xf;
1415                         pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
1416
1417                         pcinfo->pwr[2][3] = 0;
1418                         pcinfo->pddac[2][3] = 0;
1419                 } else if (pd_gains == 2) {
1420                         pcinfo->pwr[1][3] = (val >> 4) & 0xf;
1421                         pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
1422                 }
1423
1424                 if (pd_gains > 3) {
1425                         pcinfo->pwr_i[3] = (val >> 14) & 0x3;
1426                         AR5K_EEPROM_READ(offset++, val);
1427                         pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1428
1429                         pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
1430                         pcinfo->pwr[3][0] = (val >> 10) & 0xf;
1431                         pcinfo->pddac[3][0] = (val >> 14) & 0x3;
1432
1433                         AR5K_EEPROM_READ(offset++, val);
1434                         pcinfo->pddac[3][0] |= (val & 0xF) << 2;
1435                         pcinfo->pwr[3][1] = (val >> 4) & 0xf;
1436                         pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
1437
1438                         pcinfo->pwr[3][2] = (val >> 14) & 0x3;
1439                         AR5K_EEPROM_READ(offset++, val);
1440                         pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
1441
1442                         pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
1443                         pcinfo->pwr[3][3] = (val >> 8) & 0xf;
1444
1445                         pcinfo->pddac[3][3] = (val >> 12) & 0xF;
1446                         AR5K_EEPROM_READ(offset++, val);
1447                         pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
1448                 } else if (pd_gains == 3) {
1449                         pcinfo->pwr[2][3] = (val >> 14) & 0x3;
1450                         AR5K_EEPROM_READ(offset++, val);
1451                         pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
1452
1453                         pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
1454                 }
1455         }
1456
1457         return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1458 }
1459
1460
1461 /*
1462  * Read per rate target power (this is the maximum tx power
1463  * supported by the card). This info is used when setting
1464  * tx power, no matter the channel.
1465  *
1466  * This also works for v5 EEPROMs.
1467  */
1468 static int
1469 ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1470 {
1471         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1472         struct ath5k_rate_pcal_info *rate_pcal_info;
1473         u8 *rate_target_pwr_num;
1474         u32 offset;
1475         u16 val;
1476         int i;
1477
1478         offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1479         rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1480         switch (mode) {
1481         case AR5K_EEPROM_MODE_11A:
1482                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1483                 rate_pcal_info = ee->ee_rate_tpwr_a;
1484                 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1485                 break;
1486         case AR5K_EEPROM_MODE_11B:
1487                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1488                 rate_pcal_info = ee->ee_rate_tpwr_b;
1489                 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1490                 break;
1491         case AR5K_EEPROM_MODE_11G:
1492                 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1493                 rate_pcal_info = ee->ee_rate_tpwr_g;
1494                 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1495                 break;
1496         default:
1497                 return -EINVAL;
1498         }
1499
1500         /* Different freq mask for older eeproms (<= v3.2) */
1501         if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1502                 for (i = 0; i < (*rate_target_pwr_num); i++) {
1503                         AR5K_EEPROM_READ(offset++, val);
1504                         rate_pcal_info[i].freq =
1505                             ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1506
1507                         rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1508                         rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1509
1510                         AR5K_EEPROM_READ(offset++, val);
1511
1512                         if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1513                             val == 0) {
1514                                 (*rate_target_pwr_num) = i;
1515                                 break;
1516                         }
1517
1518                         rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1519                         rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1520                         rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1521                 }
1522         } else {
1523                 for (i = 0; i < (*rate_target_pwr_num); i++) {
1524                         AR5K_EEPROM_READ(offset++, val);
1525                         rate_pcal_info[i].freq =
1526                             ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1527
1528                         rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1529                         rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1530
1531                         AR5K_EEPROM_READ(offset++, val);
1532
1533                         if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1534                             val == 0) {
1535                                 (*rate_target_pwr_num) = i;
1536                                 break;
1537                         }
1538
1539                         rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1540                         rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1541                         rate_pcal_info[i].target_power_54 = (val & 0x3f);
1542                 }
1543         }
1544
1545         return 0;
1546 }
1547
1548
1549 /*
1550  * Read per channel calibration info from EEPROM
1551  *
1552  * This info is used to calibrate the baseband power table. Imagine
1553  * that for each channel there is a power curve that's hw specific
1554  * (depends on amplifier etc) and we try to "correct" this curve using
1555  * offsets we pass on to phy chip (baseband -> before amplifier) so that
1556  * it can use accurate power values when setting tx power (takes amplifier's
1557  * performance on each channel into account).
1558  *
1559  * EEPROM provides us with the offsets for some pre-calibrated channels
1560  * and we have to interpolate to create the full table for these channels and
1561  * also the table for any channel.
1562  */
1563 static int
1564 ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1565 {
1566         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1567         int (*read_pcal)(struct ath5k_hw *hw, int mode);
1568         int mode;
1569         int err;
1570
1571         if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1572                         (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1573                 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1574         else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1575                         (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1576                 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1577         else
1578                 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1579
1580
1581         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1582         mode++) {
1583                 err = read_pcal(ah, mode);
1584                 if (err)
1585                         return err;
1586
1587                 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1588                 if (err < 0)
1589                         return err;
1590         }
1591
1592         return 0;
1593 }
1594
1595 /* Read conformance test limits used for regulatory control */
1596 static int
1597 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1598 {
1599         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1600         struct ath5k_edge_power *rep;
1601         unsigned int fmask, pmask;
1602         unsigned int ctl_mode;
1603         int i, j;
1604         u32 offset;
1605         u16 val;
1606
1607         pmask = AR5K_EEPROM_POWER_M;
1608         fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1609         offset = AR5K_EEPROM_CTL(ee->ee_version);
1610         ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1611         for (i = 0; i < ee->ee_ctls; i += 2) {
1612                 AR5K_EEPROM_READ(offset++, val);
1613                 ee->ee_ctl[i] = (val >> 8) & 0xff;
1614                 ee->ee_ctl[i + 1] = val & 0xff;
1615         }
1616
1617         offset = AR5K_EEPROM_GROUP8_OFFSET;
1618         if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1619                 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1620                         AR5K_EEPROM_GROUP5_OFFSET;
1621         else
1622                 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1623
1624         rep = ee->ee_ctl_pwr;
1625         for(i = 0; i < ee->ee_ctls; i++) {
1626                 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1627                 case AR5K_CTL_11A:
1628                 case AR5K_CTL_TURBO:
1629                         ctl_mode = AR5K_EEPROM_MODE_11A;
1630                         break;
1631                 default:
1632                         ctl_mode = AR5K_EEPROM_MODE_11G;
1633                         break;
1634                 }
1635                 if (ee->ee_ctl[i] == 0) {
1636                         if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1637                                 offset += 8;
1638                         else
1639                                 offset += 7;
1640                         rep += AR5K_EEPROM_N_EDGES;
1641                         continue;
1642                 }
1643                 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1644                         for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1645                                 AR5K_EEPROM_READ(offset++, val);
1646                                 rep[j].freq = (val >> 8) & fmask;
1647                                 rep[j + 1].freq = val & fmask;
1648                         }
1649                         for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1650                                 AR5K_EEPROM_READ(offset++, val);
1651                                 rep[j].edge = (val >> 8) & pmask;
1652                                 rep[j].flag = (val >> 14) & 1;
1653                                 rep[j + 1].edge = val & pmask;
1654                                 rep[j + 1].flag = (val >> 6) & 1;
1655                         }
1656                 } else {
1657                         AR5K_EEPROM_READ(offset++, val);
1658                         rep[0].freq = (val >> 9) & fmask;
1659                         rep[1].freq = (val >> 2) & fmask;
1660                         rep[2].freq = (val << 5) & fmask;
1661
1662                         AR5K_EEPROM_READ(offset++, val);
1663                         rep[2].freq |= (val >> 11) & 0x1f;
1664                         rep[3].freq = (val >> 4) & fmask;
1665                         rep[4].freq = (val << 3) & fmask;
1666
1667                         AR5K_EEPROM_READ(offset++, val);
1668                         rep[4].freq |= (val >> 13) & 0x7;
1669                         rep[5].freq = (val >> 6) & fmask;
1670                         rep[6].freq = (val << 1) & fmask;
1671
1672                         AR5K_EEPROM_READ(offset++, val);
1673                         rep[6].freq |= (val >> 15) & 0x1;
1674                         rep[7].freq = (val >> 8) & fmask;
1675
1676                         rep[0].edge = (val >> 2) & pmask;
1677                         rep[1].edge = (val << 4) & pmask;
1678
1679                         AR5K_EEPROM_READ(offset++, val);
1680                         rep[1].edge |= (val >> 12) & 0xf;
1681                         rep[2].edge = (val >> 6) & pmask;
1682                         rep[3].edge = val & pmask;
1683
1684                         AR5K_EEPROM_READ(offset++, val);
1685                         rep[4].edge = (val >> 10) & pmask;
1686                         rep[5].edge = (val >> 4) & pmask;
1687                         rep[6].edge = (val << 2) & pmask;
1688
1689                         AR5K_EEPROM_READ(offset++, val);
1690                         rep[6].edge |= (val >> 14) & 0x3;
1691                         rep[7].edge = (val >> 8) & pmask;
1692                 }
1693                 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1694                         rep[j].freq = ath5k_eeprom_bin2freq(ee,
1695                                 rep[j].freq, ctl_mode);
1696                 }
1697                 rep += AR5K_EEPROM_N_EDGES;
1698         }
1699
1700         return 0;
1701 }
1702
1703 static int
1704 ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1705 {
1706         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1707         u32 offset;
1708         u16 val;
1709         int ret = 0, i;
1710
1711         offset = AR5K_EEPROM_CTL(ee->ee_version) +
1712                                 AR5K_EEPROM_N_CTLS(ee->ee_version);
1713
1714         if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1715                 /* No spur info for 5GHz */
1716                 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1717                 /* 2 channels for 2GHz (2464/2420) */
1718                 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1719                 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1720                 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1721         } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1722                 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1723                         AR5K_EEPROM_READ(offset, val);
1724                         ee->ee_spur_chans[i][0] = val;
1725                         AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
1726                                                                         val);
1727                         ee->ee_spur_chans[i][1] = val;
1728                         offset++;
1729                 }
1730         }
1731
1732         return ret;
1733 }
1734
1735
1736 /***********************\
1737 * Init/Detach functions *
1738 \***********************/
1739
1740 /*
1741  * Initialize eeprom data structure
1742  */
1743 int
1744 ath5k_eeprom_init(struct ath5k_hw *ah)
1745 {
1746         int err;
1747
1748         err = ath5k_eeprom_init_header(ah);
1749         if (err < 0)
1750                 return err;
1751
1752         err = ath5k_eeprom_init_modes(ah);
1753         if (err < 0)
1754                 return err;
1755
1756         err = ath5k_eeprom_read_pcal_info(ah);
1757         if (err < 0)
1758                 return err;
1759
1760         err = ath5k_eeprom_read_ctl_info(ah);
1761         if (err < 0)
1762                 return err;
1763
1764         err = ath5k_eeprom_read_spur_chans(ah);
1765         if (err < 0)
1766                 return err;
1767
1768         return 0;
1769 }
1770
1771 void
1772 ath5k_eeprom_detach(struct ath5k_hw *ah)
1773 {
1774         u8 mode;
1775
1776         for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1777                 ath5k_eeprom_free_pcal_info(ah, mode);
1778 }
1779
1780 int
1781 ath5k_eeprom_mode_from_channel(struct ieee80211_channel *channel)
1782 {
1783         switch (channel->hw_value & CHANNEL_MODES) {
1784         case CHANNEL_A:
1785         case CHANNEL_XR:
1786                 return AR5K_EEPROM_MODE_11A;
1787         case CHANNEL_G:
1788                 return AR5K_EEPROM_MODE_11G;
1789         case CHANNEL_B:
1790                 return AR5K_EEPROM_MODE_11B;
1791         default:
1792                 return -1;
1793         }
1794 }