drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     113
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "August 2, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 282         {}
 283 };
 284
 285 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 286
 287 static const struct {
 288         const char string[ETH_GSTRING_LEN];
 289 } ethtool_stats_keys[TG3_NUM_STATS] = {
 290         { "rx_octets" },
 291         { "rx_fragments" },
 292         { "rx_ucast_packets" },
 293         { "rx_mcast_packets" },
 294         { "rx_bcast_packets" },
 295         { "rx_fcs_errors" },
 296         { "rx_align_errors" },
 297         { "rx_xon_pause_rcvd" },
 298         { "rx_xoff_pause_rcvd" },
 299         { "rx_mac_ctrl_rcvd" },
 300         { "rx_xoff_entered" },
 301         { "rx_frame_too_long_errors" },
 302         { "rx_jabbers" },
 303         { "rx_undersize_packets" },
 304         { "rx_in_length_errors" },
 305         { "rx_out_length_errors" },
 306         { "rx_64_or_less_octet_packets" },
 307         { "rx_65_to_127_octet_packets" },
 308         { "rx_128_to_255_octet_packets" },
 309         { "rx_256_to_511_octet_packets" },
 310         { "rx_512_to_1023_octet_packets" },
 311         { "rx_1024_to_1522_octet_packets" },
 312         { "rx_1523_to_2047_octet_packets" },
 313         { "rx_2048_to_4095_octet_packets" },
 314         { "rx_4096_to_8191_octet_packets" },
 315         { "rx_8192_to_9022_octet_packets" },
 316
 317         { "tx_octets" },
 318         { "tx_collisions" },
 319
 320         { "tx_xon_sent" },
 321         { "tx_xoff_sent" },
 322         { "tx_flow_control" },
 323         { "tx_mac_errors" },
 324         { "tx_single_collisions" },
 325         { "tx_mult_collisions" },
 326         { "tx_deferred" },
 327         { "tx_excessive_collisions" },
 328         { "tx_late_collisions" },
 329         { "tx_collide_2times" },
 330         { "tx_collide_3times" },
 331         { "tx_collide_4times" },
 332         { "tx_collide_5times" },
 333         { "tx_collide_6times" },
 334         { "tx_collide_7times" },
 335         { "tx_collide_8times" },
 336         { "tx_collide_9times" },
 337         { "tx_collide_10times" },
 338         { "tx_collide_11times" },
 339         { "tx_collide_12times" },
 340         { "tx_collide_13times" },
 341         { "tx_collide_14times" },
 342         { "tx_collide_15times" },
 343         { "tx_ucast_packets" },
 344         { "tx_mcast_packets" },
 345         { "tx_bcast_packets" },
 346         { "tx_carrier_sense_errors" },
 347         { "tx_discards" },
 348         { "tx_errors" },
 349
 350         { "dma_writeq_full" },
 351         { "dma_write_prioq_full" },
 352         { "rxbds_empty" },
 353         { "rx_discards" },
 354         { "rx_errors" },
 355         { "rx_threshold_hit" },
 356
 357         { "dma_readq_full" },
 358         { "dma_read_prioq_full" },
 359         { "tx_comp_queue_full" },
 360
 361         { "ring_set_send_prod_index" },
 362         { "ring_status_update" },
 363         { "nic_irqs" },
 364         { "nic_avoided_irqs" },
 365         { "nic_tx_threshold_hit" }
 366 };
 367
 368 static const struct {
 369         const char string[ETH_GSTRING_LEN];
 370 } ethtool_test_keys[TG3_NUM_TEST] = {
 371         { "nvram test     (online) " },
 372         { "link test      (online) " },
 373         { "register test  (offline)" },
 374         { "memory test    (offline)" },
 375         { "loopback test  (offline)" },
 376         { "interrupt test (offline)" },
 377 };
 378
 379 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 380 {
 381         writel(val, tp->regs + off);
 382 }
 383
 384 static u32 tg3_read32(struct tg3 *tp, u32 off)
 385 {
 386         return readl(tp->regs + off);
 387 }
 388
 389 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 390 {
 391         writel(val, tp->aperegs + off);
 392 }
 393
 394 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 395 {
 396         return readl(tp->aperegs + off);
 397 }
 398
 399 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&tp->indirect_lock, flags);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 405         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 406         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 407 }
 408
 409 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 410 {
 411         writel(val, tp->regs + off);
 412         readl(tp->regs + off);
 413 }
 414
 415 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 416 {
 417         unsigned long flags;
 418         u32 val;
 419
 420         spin_lock_irqsave(&tp->indirect_lock, flags);
 421         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 422         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 423         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 424         return val;
 425 }
 426
 427 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 428 {
 429         unsigned long flags;
 430
 431         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 432                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 433                                        TG3_64BIT_REG_LOW, val);
 434                 return;
 435         }
 436         if (off == TG3_RX_STD_PROD_IDX_REG) {
 437                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 438                                        TG3_64BIT_REG_LOW, val);
 439                 return;
 440         }
 441
 442         spin_lock_irqsave(&tp->indirect_lock, flags);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 444         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 445         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 446
 447         /* In indirect mode when disabling interrupts, we also need
 448          * to clear the interrupt bit in the GRC local ctrl register.
 449          */
 450         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 451             (val == 0x1)) {
 452                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 453                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 454         }
 455 }
 456
 457 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 458 {
 459         unsigned long flags;
 460         u32 val;
 461
 462         spin_lock_irqsave(&tp->indirect_lock, flags);
 463         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 464         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 465         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 466         return val;
 467 }
 468
 469 /* usec_wait specifies the wait time in usec when writing to certain registers
 470  * where it is unsafe to read back the register without some delay.
 471  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 472  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 473  */
 474 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 475 {
 476         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 477             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 478                 /* Non-posted methods */
 479                 tp->write32(tp, off, val);
 480         else {
 481                 /* Posted method */
 482                 tg3_write32(tp, off, val);
 483                 if (usec_wait)
 484                         udelay(usec_wait);
 485                 tp->read32(tp, off);
 486         }
 487         /* Wait again after the read for the posted method to guarantee that
 488          * the wait time is met.
 489          */
 490         if (usec_wait)
 491                 udelay(usec_wait);
 492 }
 493
 494 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 495 {
 496         tp->write32_mbox(tp, off, val);
 497         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 498             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 499                 tp->read32_mbox(tp, off);
 500 }
 501
 502 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 503 {
 504         void __iomem *mbox = tp->regs + off;
 505         writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 507                 writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 509                 readl(mbox);
 510 }
 511
 512 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 513 {
 514         return readl(tp->regs + off + GRCMBOX_BASE);
 515 }
 516
 517 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 518 {
 519         writel(val, tp->regs + off + GRCMBOX_BASE);
 520 }
 521
 522 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 523 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 524 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 525 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 526 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 527
 528 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 529 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 530 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 531 #define tr32(reg)                       tp->read32(tp, reg)
 532
 533 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 534 {
 535         unsigned long flags;
 536
 537         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 538             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 539                 return;
 540
 541         spin_lock_irqsave(&tp->indirect_lock, flags);
 542         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 544                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 545
 546                 /* Always leave this as zero. */
 547                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 548         } else {
 549                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 550                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 551
 552                 /* Always leave this as zero. */
 553                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 554         }
 555         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 556 }
 557
 558 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 559 {
 560         unsigned long flags;
 561
 562         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 563             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 564                 *val = 0;
 565                 return;
 566         }
 567
 568         spin_lock_irqsave(&tp->indirect_lock, flags);
 569         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 570                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 571                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 572
 573                 /* Always leave this as zero. */
 574                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 575         } else {
 576                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 577                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 578
 579                 /* Always leave this as zero. */
 580                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 581         }
 582         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 583 }
 584
 585 static void tg3_ape_lock_init(struct tg3 *tp)
 586 {
 587         int i;
 588         u32 regbase;
 589
 590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 591                 regbase = TG3_APE_LOCK_GRANT;
 592         else
 593                 regbase = TG3_APE_PER_LOCK_GRANT;
 594
 595         /* Make sure the driver hasn't any stale locks. */
 596         for (i = 0; i < 8; i++)
 597                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 598 }
 599
 600 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 601 {
 602         int i, off;
 603         int ret = 0;
 604         u32 status, req, gnt;
 605
 606         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 607                 return 0;
 608
 609         switch (locknum) {
 610         case TG3_APE_LOCK_GRC:
 611         case TG3_APE_LOCK_MEM:
 612                 break;
 613         default:
 614                 return -EINVAL;
 615         }
 616
 617         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 618                 req = TG3_APE_LOCK_REQ;
 619                 gnt = TG3_APE_LOCK_GRANT;
 620         } else {
 621                 req = TG3_APE_PER_LOCK_REQ;
 622                 gnt = TG3_APE_PER_LOCK_GRANT;
 623         }
 624
 625         off = 4 * locknum;
 626
 627         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 628
 629         /* Wait for up to 1 millisecond to acquire lock. */
 630         for (i = 0; i < 100; i++) {
 631                 status = tg3_ape_read32(tp, gnt + off);
 632                 if (status == APE_LOCK_GRANT_DRIVER)
 633                         break;
 634                 udelay(10);
 635         }
 636
 637         if (status != APE_LOCK_GRANT_DRIVER) {
 638                 /* Revoke the lock request. */
 639                 tg3_ape_write32(tp, gnt + off,
 640                                 APE_LOCK_GRANT_DRIVER);
 641
 642                 ret = -EBUSY;
 643         }
 644
 645         return ret;
 646 }
 647
 648 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 649 {
 650         u32 gnt;
 651
 652         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 653                 return;
 654
 655         switch (locknum) {
 656         case TG3_APE_LOCK_GRC:
 657         case TG3_APE_LOCK_MEM:
 658                 break;
 659         default:
 660                 return;
 661         }
 662
 663         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 664                 gnt = TG3_APE_LOCK_GRANT;
 665         else
 666                 gnt = TG3_APE_PER_LOCK_GRANT;
 667
 668         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 669 }
 670
 671 static void tg3_disable_ints(struct tg3 *tp)
 672 {
 673         int i;
 674
 675         tw32(TG3PCI_MISC_HOST_CTRL,
 676              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 677         for (i = 0; i < tp->irq_max; i++)
 678                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 679 }
 680
 681 static void tg3_enable_ints(struct tg3 *tp)
 682 {
 683         int i;
 684
 685         tp->irq_sync = 0;
 686         wmb();
 687
 688         tw32(TG3PCI_MISC_HOST_CTRL,
 689              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 690
 691         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 692         for (i = 0; i < tp->irq_cnt; i++) {
 693                 struct tg3_napi *tnapi = &tp->napi[i];
 694
 695                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 697                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698
 699                 tp->coal_now |= tnapi->coal_now;
 700         }
 701
 702         /* Force an initial interrupt */
 703         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 704             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 705                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 706         else
 707                 tw32(HOSTCC_MODE, tp->coal_now);
 708
 709         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 710 }
 711
 712 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 713 {
 714         struct tg3 *tp = tnapi->tp;
 715         struct tg3_hw_status *sblk = tnapi->hw_status;
 716         unsigned int work_exists = 0;
 717
 718         /* check for phy events */
 719         if (!(tp->tg3_flags &
 720               (TG3_FLAG_USE_LINKCHG_REG |
 721                TG3_FLAG_POLL_SERDES))) {
 722                 if (sblk->status & SD_STATUS_LINK_CHG)
 723                         work_exists = 1;
 724         }
 725         /* check for RX/TX work to do */
 726         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 727             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 728                 work_exists = 1;
 729
 730         return work_exists;
 731 }
 732
 733 /* tg3_int_reenable
 734  *  similar to tg3_enable_ints, but it accurately determines whether there
 735  *  is new work pending and can return without flushing the PIO write
 736  *  which reenables interrupts
 737  */
 738 static void tg3_int_reenable(struct tg3_napi *tnapi)
 739 {
 740         struct tg3 *tp = tnapi->tp;
 741
 742         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 743         mmiowb();
 744
 745         /* When doing tagged status, this work check is unnecessary.
 746          * The last_tag we write above tells the chip which piece of
 747          * work we've completed.
 748          */
 749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 750             tg3_has_work(tnapi))
 751                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 752                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 753 }
 754
 755 static void tg3_napi_disable(struct tg3 *tp)
 756 {
 757         int i;
 758
 759         for (i = tp->irq_cnt - 1; i >= 0; i--)
 760                 napi_disable(&tp->napi[i].napi);
 761 }
 762
 763 static void tg3_napi_enable(struct tg3 *tp)
 764 {
 765         int i;
 766
 767         for (i = 0; i < tp->irq_cnt; i++)
 768                 napi_enable(&tp->napi[i].napi);
 769 }
 770
 771 static inline void tg3_netif_stop(struct tg3 *tp)
 772 {
 773         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 774         tg3_napi_disable(tp);
 775         netif_tx_disable(tp->dev);
 776 }
 777
 778 static inline void tg3_netif_start(struct tg3 *tp)
 779 {
 780         /* NOTE: unconditional netif_tx_wake_all_queues is only
 781          * appropriate so long as all callers are assured to
 782          * have free tx slots (such as after tg3_init_hw)
 783          */
 784         netif_tx_wake_all_queues(tp->dev);
 785
 786         tg3_napi_enable(tp);
 787         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 788         tg3_enable_ints(tp);
 789 }
 790
 791 static void tg3_switch_clocks(struct tg3 *tp)
 792 {
 793         u32 clock_ctrl;
 794         u32 orig_clock_ctrl;
 795
 796         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 797             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 798                 return;
 799
 800         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 801
 802         orig_clock_ctrl = clock_ctrl;
 803         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 804                        CLOCK_CTRL_CLKRUN_OENABLE |
 805                        0x1f);
 806         tp->pci_clock_ctrl = clock_ctrl;
 807
 808         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 809                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 810                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 811                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 812                 }
 813         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 814                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 815                             clock_ctrl |
 816                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 817                             40);
 818                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 819                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 820                             40);
 821         }
 822         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 823 }
 824
 825 #define PHY_BUSY_LOOPS  5000
 826
 827 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 828 {
 829         u32 frame_val;
 830         unsigned int loops;
 831         int ret;
 832
 833         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 834                 tw32_f(MAC_MI_MODE,
 835                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 836                 udelay(80);
 837         }
 838
 839         *val = 0x0;
 840
 841         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 842                       MI_COM_PHY_ADDR_MASK);
 843         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 844                       MI_COM_REG_ADDR_MASK);
 845         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 846
 847         tw32_f(MAC_MI_COM, frame_val);
 848
 849         loops = PHY_BUSY_LOOPS;
 850         while (loops != 0) {
 851                 udelay(10);
 852                 frame_val = tr32(MAC_MI_COM);
 853
 854                 if ((frame_val & MI_COM_BUSY) == 0) {
 855                         udelay(5);
 856                         frame_val = tr32(MAC_MI_COM);
 857                         break;
 858                 }
 859                 loops -= 1;
 860         }
 861
 862         ret = -EBUSY;
 863         if (loops != 0) {
 864                 *val = frame_val & MI_COM_DATA_MASK;
 865                 ret = 0;
 866         }
 867
 868         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 869                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 870                 udelay(80);
 871         }
 872
 873         return ret;
 874 }
 875
 876 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 877 {
 878         u32 frame_val;
 879         unsigned int loops;
 880         int ret;
 881
 882         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 883             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 884                 return 0;
 885
 886         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 887                 tw32_f(MAC_MI_MODE,
 888                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 889                 udelay(80);
 890         }
 891
 892         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 893                       MI_COM_PHY_ADDR_MASK);
 894         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 895                       MI_COM_REG_ADDR_MASK);
 896         frame_val |= (val & MI_COM_DATA_MASK);
 897         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 898
 899         tw32_f(MAC_MI_COM, frame_val);
 900
 901         loops = PHY_BUSY_LOOPS;
 902         while (loops != 0) {
 903                 udelay(10);
 904                 frame_val = tr32(MAC_MI_COM);
 905                 if ((frame_val & MI_COM_BUSY) == 0) {
 906                         udelay(5);
 907                         frame_val = tr32(MAC_MI_COM);
 908                         break;
 909                 }
 910                 loops -= 1;
 911         }
 912
 913         ret = -EBUSY;
 914         if (loops != 0)
 915                 ret = 0;
 916
 917         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 918                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 919                 udelay(80);
 920         }
 921
 922         return ret;
 923 }
 924
 925 static int tg3_bmcr_reset(struct tg3 *tp)
 926 {
 927         u32 phy_control;
 928         int limit, err;
 929
 930         /* OK, reset it, and poll the BMCR_RESET bit until it
 931          * clears or we time out.
 932          */
 933         phy_control = BMCR_RESET;
 934         err = tg3_writephy(tp, MII_BMCR, phy_control);
 935         if (err != 0)
 936                 return -EBUSY;
 937
 938         limit = 5000;
 939         while (limit--) {
 940                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 941                 if (err != 0)
 942                         return -EBUSY;
 943
 944                 if ((phy_control & BMCR_RESET) == 0) {
 945                         udelay(40);
 946                         break;
 947                 }
 948                 udelay(10);
 949         }
 950         if (limit < 0)
 951                 return -EBUSY;
 952
 953         return 0;
 954 }
 955
 956 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 957 {
 958         struct tg3 *tp = bp->priv;
 959         u32 val;
 960
 961         spin_lock_bh(&tp->lock);
 962
 963         if (tg3_readphy(tp, reg, &val))
 964                 val = -EIO;
 965
 966         spin_unlock_bh(&tp->lock);
 967
 968         return val;
 969 }
 970
 971 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 972 {
 973         struct tg3 *tp = bp->priv;
 974         u32 ret = 0;
 975
 976         spin_lock_bh(&tp->lock);
 977
 978         if (tg3_writephy(tp, reg, val))
 979                 ret = -EIO;
 980
 981         spin_unlock_bh(&tp->lock);
 982
 983         return ret;
 984 }
 985
 986 static int tg3_mdio_reset(struct mii_bus *bp)
 987 {
 988         return 0;
 989 }
 990
 991 static void tg3_mdio_config_5785(struct tg3 *tp)
 992 {
 993         u32 val;
 994         struct phy_device *phydev;
 995
 996         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 997         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 998         case PHY_ID_BCM50610:
 999         case PHY_ID_BCM50610M:
1000                 val = MAC_PHYCFG2_50610_LED_MODES;
1001                 break;
1002         case PHY_ID_BCMAC131:
1003                 val = MAC_PHYCFG2_AC131_LED_MODES;
1004                 break;
1005         case PHY_ID_RTL8211C:
1006                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1007                 break;
1008         case PHY_ID_RTL8201E:
1009                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1010                 break;
1011         default:
1012                 return;
1013         }
1014
1015         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1016                 tw32(MAC_PHYCFG2, val);
1017
1018                 val = tr32(MAC_PHYCFG1);
1019                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1020                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1021                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1022                 tw32(MAC_PHYCFG1, val);
1023
1024                 return;
1025         }
1026
1027         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1028                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1029                        MAC_PHYCFG2_FMODE_MASK_MASK |
1030                        MAC_PHYCFG2_GMODE_MASK_MASK |
1031                        MAC_PHYCFG2_ACT_MASK_MASK   |
1032                        MAC_PHYCFG2_QUAL_MASK_MASK |
1033                        MAC_PHYCFG2_INBAND_ENABLE;
1034
1035         tw32(MAC_PHYCFG2, val);
1036
1037         val = tr32(MAC_PHYCFG1);
1038         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1039                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1040         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1043                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1044                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1045         }
1046         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1047                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1048         tw32(MAC_PHYCFG1, val);
1049
1050         val = tr32(MAC_EXT_RGMII_MODE);
1051         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1052                  MAC_RGMII_MODE_RX_QUALITY |
1053                  MAC_RGMII_MODE_RX_ACTIVITY |
1054                  MAC_RGMII_MODE_RX_ENG_DET |
1055                  MAC_RGMII_MODE_TX_ENABLE |
1056                  MAC_RGMII_MODE_TX_LOWPWR |
1057                  MAC_RGMII_MODE_TX_RESET);
1058         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1059                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1060                         val |= MAC_RGMII_MODE_RX_INT_B |
1061                                MAC_RGMII_MODE_RX_QUALITY |
1062                                MAC_RGMII_MODE_RX_ACTIVITY |
1063                                MAC_RGMII_MODE_RX_ENG_DET;
1064                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1065                         val |= MAC_RGMII_MODE_TX_ENABLE |
1066                                MAC_RGMII_MODE_TX_LOWPWR |
1067                                MAC_RGMII_MODE_TX_RESET;
1068         }
1069         tw32(MAC_EXT_RGMII_MODE, val);
1070 }
1071
1072 static void tg3_mdio_start(struct tg3 *tp)
1073 {
1074         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1075         tw32_f(MAC_MI_MODE, tp->mi_mode);
1076         udelay(80);
1077
1078         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1079             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1080                 tg3_mdio_config_5785(tp);
1081 }
1082
1083 static int tg3_mdio_init(struct tg3 *tp)
1084 {
1085         int i;
1086         u32 reg;
1087         struct phy_device *phydev;
1088
1089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1090             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1091                 u32 is_serdes;
1092
1093                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1094
1095                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1096                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1097                 else
1098                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1099                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1100                 if (is_serdes)
1101                         tp->phy_addr += 7;
1102         } else
1103                 tp->phy_addr = TG3_PHY_MII_ADDR;
1104
1105         tg3_mdio_start(tp);
1106
1107         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1108             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1109                 return 0;
1110
1111         tp->mdio_bus = mdiobus_alloc();
1112         if (tp->mdio_bus == NULL)
1113                 return -ENOMEM;
1114
1115         tp->mdio_bus->name     = "tg3 mdio bus";
1116         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1117                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1118         tp->mdio_bus->priv     = tp;
1119         tp->mdio_bus->parent   = &tp->pdev->dev;
1120         tp->mdio_bus->read     = &tg3_mdio_read;
1121         tp->mdio_bus->write    = &tg3_mdio_write;
1122         tp->mdio_bus->reset    = &tg3_mdio_reset;
1123         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1124         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1125
1126         for (i = 0; i < PHY_MAX_ADDR; i++)
1127                 tp->mdio_bus->irq[i] = PHY_POLL;
1128
1129         /* The bus registration will look for all the PHYs on the mdio bus.
1130          * Unfortunately, it does not ensure the PHY is powered up before
1131          * accessing the PHY ID registers.  A chip reset is the
1132          * quickest way to bring the device back to an operational state..
1133          */
1134         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1135                 tg3_bmcr_reset(tp);
1136
1137         i = mdiobus_register(tp->mdio_bus);
1138         if (i) {
1139                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1140                 mdiobus_free(tp->mdio_bus);
1141                 return i;
1142         }
1143
1144         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1145
1146         if (!phydev || !phydev->drv) {
1147                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1148                 mdiobus_unregister(tp->mdio_bus);
1149                 mdiobus_free(tp->mdio_bus);
1150                 return -ENODEV;
1151         }
1152
1153         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1154         case PHY_ID_BCM57780:
1155                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1156                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1157                 break;
1158         case PHY_ID_BCM50610:
1159         case PHY_ID_BCM50610M:
1160                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1161                                      PHY_BRCM_RX_REFCLK_UNUSED |
1162                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1163                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1164                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1165                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1166                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1167                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1168                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1169                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1170                 /* fallthru */
1171         case PHY_ID_RTL8211C:
1172                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1173                 break;
1174         case PHY_ID_RTL8201E:
1175         case PHY_ID_BCMAC131:
1176                 phydev->interface = PHY_INTERFACE_MODE_MII;
1177                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1178                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1179                 break;
1180         }
1181
1182         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1183
1184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1185                 tg3_mdio_config_5785(tp);
1186
1187         return 0;
1188 }
1189
1190 static void tg3_mdio_fini(struct tg3 *tp)
1191 {
1192         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1193                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1194                 mdiobus_unregister(tp->mdio_bus);
1195                 mdiobus_free(tp->mdio_bus);
1196         }
1197 }
1198
1199 /* tp->lock is held. */
1200 static inline void tg3_generate_fw_event(struct tg3 *tp)
1201 {
1202         u32 val;
1203
1204         val = tr32(GRC_RX_CPU_EVENT);
1205         val |= GRC_RX_CPU_DRIVER_EVENT;
1206         tw32_f(GRC_RX_CPU_EVENT, val);
1207
1208         tp->last_event_jiffies = jiffies;
1209 }
1210
1211 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1212
1213 /* tp->lock is held. */
1214 static void tg3_wait_for_event_ack(struct tg3 *tp)
1215 {
1216         int i;
1217         unsigned int delay_cnt;
1218         long time_remain;
1219
1220         /* If enough time has passed, no wait is necessary. */
1221         time_remain = (long)(tp->last_event_jiffies + 1 +
1222                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1223                       (long)jiffies;
1224         if (time_remain < 0)
1225                 return;
1226
1227         /* Check if we can shorten the wait time. */
1228         delay_cnt = jiffies_to_usecs(time_remain);
1229         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1230                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1231         delay_cnt = (delay_cnt >> 3) + 1;
1232
1233         for (i = 0; i < delay_cnt; i++) {
1234                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1235                         break;
1236                 udelay(8);
1237         }
1238 }
1239
1240 /* tp->lock is held. */
1241 static void tg3_ump_link_report(struct tg3 *tp)
1242 {
1243         u32 reg;
1244         u32 val;
1245
1246         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1247             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1248                 return;
1249
1250         tg3_wait_for_event_ack(tp);
1251
1252         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1253
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1255
1256         val = 0;
1257         if (!tg3_readphy(tp, MII_BMCR, &reg))
1258                 val = reg << 16;
1259         if (!tg3_readphy(tp, MII_BMSR, &reg))
1260                 val |= (reg & 0xffff);
1261         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1262
1263         val = 0;
1264         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1265                 val = reg << 16;
1266         if (!tg3_readphy(tp, MII_LPA, &reg))
1267                 val |= (reg & 0xffff);
1268         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1269
1270         val = 0;
1271         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1272                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1273                         val = reg << 16;
1274                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1275                         val |= (reg & 0xffff);
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1278
1279         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1280                 val = reg << 16;
1281         else
1282                 val = 0;
1283         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1284
1285         tg3_generate_fw_event(tp);
1286 }
1287
1288 static void tg3_link_report(struct tg3 *tp)
1289 {
1290         if (!netif_carrier_ok(tp->dev)) {
1291                 netif_info(tp, link, tp->dev, "Link is down\n");
1292                 tg3_ump_link_report(tp);
1293         } else if (netif_msg_link(tp)) {
1294                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1295                             (tp->link_config.active_speed == SPEED_1000 ?
1296                              1000 :
1297                              (tp->link_config.active_speed == SPEED_100 ?
1298                               100 : 10)),
1299                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1300                              "full" : "half"));
1301
1302                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1303                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1304                             "on" : "off",
1305                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1306                             "on" : "off");
1307                 tg3_ump_link_report(tp);
1308         }
1309 }
1310
1311 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1312 {
1313         u16 miireg;
1314
1315         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1316                 miireg = ADVERTISE_PAUSE_CAP;
1317         else if (flow_ctrl & FLOW_CTRL_TX)
1318                 miireg = ADVERTISE_PAUSE_ASYM;
1319         else if (flow_ctrl & FLOW_CTRL_RX)
1320                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1321         else
1322                 miireg = 0;
1323
1324         return miireg;
1325 }
1326
1327 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1328 {
1329         u16 miireg;
1330
1331         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1332                 miireg = ADVERTISE_1000XPAUSE;
1333         else if (flow_ctrl & FLOW_CTRL_TX)
1334                 miireg = ADVERTISE_1000XPSE_ASYM;
1335         else if (flow_ctrl & FLOW_CTRL_RX)
1336                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1337         else
1338                 miireg = 0;
1339
1340         return miireg;
1341 }
1342
1343 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1344 {
1345         u8 cap = 0;
1346
1347         if (lcladv & ADVERTISE_1000XPAUSE) {
1348                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1349                         if (rmtadv & LPA_1000XPAUSE)
1350                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1351                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1352                                 cap = FLOW_CTRL_RX;
1353                 } else {
1354                         if (rmtadv & LPA_1000XPAUSE)
1355                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1356                 }
1357         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1358                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1359                         cap = FLOW_CTRL_TX;
1360         }
1361
1362         return cap;
1363 }
1364
1365 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1366 {
1367         u8 autoneg;
1368         u8 flowctrl = 0;
1369         u32 old_rx_mode = tp->rx_mode;
1370         u32 old_tx_mode = tp->tx_mode;
1371
1372         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1373                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1374         else
1375                 autoneg = tp->link_config.autoneg;
1376
1377         if (autoneg == AUTONEG_ENABLE &&
1378             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1379                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1380                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1381                 else
1382                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1383         } else
1384                 flowctrl = tp->link_config.flowctrl;
1385
1386         tp->link_config.active_flowctrl = flowctrl;
1387
1388         if (flowctrl & FLOW_CTRL_RX)
1389                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1390         else
1391                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1392
1393         if (old_rx_mode != tp->rx_mode)
1394                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1395
1396         if (flowctrl & FLOW_CTRL_TX)
1397                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1398         else
1399                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1400
1401         if (old_tx_mode != tp->tx_mode)
1402                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1403 }
1404
1405 static void tg3_adjust_link(struct net_device *dev)
1406 {
1407         u8 oldflowctrl, linkmesg = 0;
1408         u32 mac_mode, lcl_adv, rmt_adv;
1409         struct tg3 *tp = netdev_priv(dev);
1410         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1411
1412         spin_lock_bh(&tp->lock);
1413
1414         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1415                                     MAC_MODE_HALF_DUPLEX);
1416
1417         oldflowctrl = tp->link_config.active_flowctrl;
1418
1419         if (phydev->link) {
1420                 lcl_adv = 0;
1421                 rmt_adv = 0;
1422
1423                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1424                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1425                 else if (phydev->speed == SPEED_1000 ||
1426                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1427                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1428                 else
1429                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1430
1431                 if (phydev->duplex == DUPLEX_HALF)
1432                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1433                 else {
1434                         lcl_adv = tg3_advert_flowctrl_1000T(
1435                                   tp->link_config.flowctrl);
1436
1437                         if (phydev->pause)
1438                                 rmt_adv = LPA_PAUSE_CAP;
1439                         if (phydev->asym_pause)
1440                                 rmt_adv |= LPA_PAUSE_ASYM;
1441                 }
1442
1443                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1444         } else
1445                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1446
1447         if (mac_mode != tp->mac_mode) {
1448                 tp->mac_mode = mac_mode;
1449                 tw32_f(MAC_MODE, tp->mac_mode);
1450                 udelay(40);
1451         }
1452
1453         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1454                 if (phydev->speed == SPEED_10)
1455                         tw32(MAC_MI_STAT,
1456                              MAC_MI_STAT_10MBPS_MODE |
1457                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1458                 else
1459                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1460         }
1461
1462         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1463                 tw32(MAC_TX_LENGTHS,
1464                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1465                       (6 << TX_LENGTHS_IPG_SHIFT) |
1466                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1467         else
1468                 tw32(MAC_TX_LENGTHS,
1469                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1470                       (6 << TX_LENGTHS_IPG_SHIFT) |
1471                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1472
1473         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1474             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1475             phydev->speed != tp->link_config.active_speed ||
1476             phydev->duplex != tp->link_config.active_duplex ||
1477             oldflowctrl != tp->link_config.active_flowctrl)
1478                 linkmesg = 1;
1479
1480         tp->link_config.active_speed = phydev->speed;
1481         tp->link_config.active_duplex = phydev->duplex;
1482
1483         spin_unlock_bh(&tp->lock);
1484
1485         if (linkmesg)
1486                 tg3_link_report(tp);
1487 }
1488
1489 static int tg3_phy_init(struct tg3 *tp)
1490 {
1491         struct phy_device *phydev;
1492
1493         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1494                 return 0;
1495
1496         /* Bring the PHY back to a known state. */
1497         tg3_bmcr_reset(tp);
1498
1499         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1500
1501         /* Attach the MAC to the PHY. */
1502         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1503                              phydev->dev_flags, phydev->interface);
1504         if (IS_ERR(phydev)) {
1505                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1506                 return PTR_ERR(phydev);
1507         }
1508
1509         /* Mask with MAC supported features. */
1510         switch (phydev->interface) {
1511         case PHY_INTERFACE_MODE_GMII:
1512         case PHY_INTERFACE_MODE_RGMII:
1513                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1514                         phydev->supported &= (PHY_GBIT_FEATURES |
1515                                               SUPPORTED_Pause |
1516                                               SUPPORTED_Asym_Pause);
1517                         break;
1518                 }
1519                 /* fallthru */
1520         case PHY_INTERFACE_MODE_MII:
1521                 phydev->supported &= (PHY_BASIC_FEATURES |
1522                                       SUPPORTED_Pause |
1523                                       SUPPORTED_Asym_Pause);
1524                 break;
1525         default:
1526                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1527                 return -EINVAL;
1528         }
1529
1530         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1531
1532         phydev->advertising = phydev->supported;
1533
1534         return 0;
1535 }
1536
1537 static void tg3_phy_start(struct tg3 *tp)
1538 {
1539         struct phy_device *phydev;
1540
1541         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1542                 return;
1543
1544         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1545
1546         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1547                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1548                 phydev->speed = tp->link_config.orig_speed;
1549                 phydev->duplex = tp->link_config.orig_duplex;
1550                 phydev->autoneg = tp->link_config.orig_autoneg;
1551                 phydev->advertising = tp->link_config.orig_advertising;
1552         }
1553
1554         phy_start(phydev);
1555
1556         phy_start_aneg(phydev);
1557 }
1558
1559 static void tg3_phy_stop(struct tg3 *tp)
1560 {
1561         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1562                 return;
1563
1564         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1565 }
1566
1567 static void tg3_phy_fini(struct tg3 *tp)
1568 {
1569         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1570                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1571                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1572         }
1573 }
1574
1575 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1576 {
1577         int err;
1578
1579         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1580         if (!err)
1581                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1582
1583         return err;
1584 }
1585
1586 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1587 {
1588         u32 phytest;
1589
1590         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1591                 u32 phy;
1592
1593                 tg3_writephy(tp, MII_TG3_FET_TEST,
1594                              phytest | MII_TG3_FET_SHADOW_EN);
1595                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1596                         if (enable)
1597                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1598                         else
1599                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1600                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1601                 }
1602                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1603         }
1604 }
1605
1606 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1607 {
1608         u32 reg;
1609
1610         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1611             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1612               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1613              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1614                 return;
1615
1616         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1617                 tg3_phy_fet_toggle_apd(tp, enable);
1618                 return;
1619         }
1620
1621         reg = MII_TG3_MISC_SHDW_WREN |
1622               MII_TG3_MISC_SHDW_SCR5_SEL |
1623               MII_TG3_MISC_SHDW_SCR5_LPED |
1624               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1625               MII_TG3_MISC_SHDW_SCR5_SDTL |
1626               MII_TG3_MISC_SHDW_SCR5_C125OE;
1627         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1628                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1629
1630         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1631
1632
1633         reg = MII_TG3_MISC_SHDW_WREN |
1634               MII_TG3_MISC_SHDW_APD_SEL |
1635               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1636         if (enable)
1637                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1638
1639         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1640 }
1641
1642 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1643 {
1644         u32 phy;
1645
1646         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1647             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1648                 return;
1649
1650         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1651                 u32 ephy;
1652
1653                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1654                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1655
1656                         tg3_writephy(tp, MII_TG3_FET_TEST,
1657                                      ephy | MII_TG3_FET_SHADOW_EN);
1658                         if (!tg3_readphy(tp, reg, &phy)) {
1659                                 if (enable)
1660                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1661                                 else
1662                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1663                                 tg3_writephy(tp, reg, phy);
1664                         }
1665                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1666                 }
1667         } else {
1668                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1669                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1670                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1671                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1672                         if (enable)
1673                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1674                         else
1675                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1676                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1677                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1678                 }
1679         }
1680 }
1681
1682 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1683 {
1684         u32 val;
1685
1686         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1687                 return;
1688
1689         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1690             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1691                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1692                              (val | (1 << 15) | (1 << 4)));
1693 }
1694
1695 static void tg3_phy_apply_otp(struct tg3 *tp)
1696 {
1697         u32 otp, phy;
1698
1699         if (!tp->phy_otp)
1700                 return;
1701
1702         otp = tp->phy_otp;
1703
1704         /* Enable SM_DSP clock and tx 6dB coding. */
1705         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1706               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1707               MII_TG3_AUXCTL_ACTL_TX_6DB;
1708         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1709
1710         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1711         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1712         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1713
1714         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1715               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1716         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1717
1718         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1719         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1720         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1721
1722         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1723         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1724
1725         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1726         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1727
1728         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1729               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1730         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1731
1732         /* Turn off SM_DSP clock. */
1733         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1734               MII_TG3_AUXCTL_ACTL_TX_6DB;
1735         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1736 }
1737
1738 static int tg3_wait_macro_done(struct tg3 *tp)
1739 {
1740         int limit = 100;
1741
1742         while (limit--) {
1743                 u32 tmp32;
1744
1745                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1746                         if ((tmp32 & 0x1000) == 0)
1747                                 break;
1748                 }
1749         }
1750         if (limit < 0)
1751                 return -EBUSY;
1752
1753         return 0;
1754 }
1755
1756 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1757 {
1758         static const u32 test_pat[4][6] = {
1759         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1760         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1761         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1762         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1763         };
1764         int chan;
1765
1766         for (chan = 0; chan < 4; chan++) {
1767                 int i;
1768
1769                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1770                              (chan * 0x2000) | 0x0200);
1771                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1772
1773                 for (i = 0; i < 6; i++)
1774                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1775                                      test_pat[chan][i]);
1776
1777                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1778                 if (tg3_wait_macro_done(tp)) {
1779                         *resetp = 1;
1780                         return -EBUSY;
1781                 }
1782
1783                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1784                              (chan * 0x2000) | 0x0200);
1785                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1786                 if (tg3_wait_macro_done(tp)) {
1787                         *resetp = 1;
1788                         return -EBUSY;
1789                 }
1790
1791                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1792                 if (tg3_wait_macro_done(tp)) {
1793                         *resetp = 1;
1794                         return -EBUSY;
1795                 }
1796
1797                 for (i = 0; i < 6; i += 2) {
1798                         u32 low, high;
1799
1800                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1801                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1802                             tg3_wait_macro_done(tp)) {
1803                                 *resetp = 1;
1804                                 return -EBUSY;
1805                         }
1806                         low &= 0x7fff;
1807                         high &= 0x000f;
1808                         if (low != test_pat[chan][i] ||
1809                             high != test_pat[chan][i+1]) {
1810                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1811                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1812                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1813
1814                                 return -EBUSY;
1815                         }
1816                 }
1817         }
1818
1819         return 0;
1820 }
1821
1822 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1823 {
1824         int chan;
1825
1826         for (chan = 0; chan < 4; chan++) {
1827                 int i;
1828
1829                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1830                              (chan * 0x2000) | 0x0200);
1831                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1834                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1835                 if (tg3_wait_macro_done(tp))
1836                         return -EBUSY;
1837         }
1838
1839         return 0;
1840 }
1841
1842 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1843 {
1844         u32 reg32, phy9_orig;
1845         int retries, do_phy_reset, err;
1846
1847         retries = 10;
1848         do_phy_reset = 1;
1849         do {
1850                 if (do_phy_reset) {
1851                         err = tg3_bmcr_reset(tp);
1852                         if (err)
1853                                 return err;
1854                         do_phy_reset = 0;
1855                 }
1856
1857                 /* Disable transmitter and interrupt.  */
1858                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1859                         continue;
1860
1861                 reg32 |= 0x3000;
1862                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1863
1864                 /* Set full-duplex, 1000 mbps.  */
1865                 tg3_writephy(tp, MII_BMCR,
1866                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1867
1868                 /* Set to master mode.  */
1869                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1870                         continue;
1871
1872                 tg3_writephy(tp, MII_TG3_CTRL,
1873                              (MII_TG3_CTRL_AS_MASTER |
1874                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1875
1876                 /* Enable SM_DSP_CLOCK and 6dB.  */
1877                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1878
1879                 /* Block the PHY control access.  */
1880                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1881
1882                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1883                 if (!err)
1884                         break;
1885         } while (--retries);
1886
1887         err = tg3_phy_reset_chanpat(tp);
1888         if (err)
1889                 return err;
1890
1891         tg3_phydsp_write(tp, 0x8005, 0x0000);
1892
1893         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1894         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1895
1896         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1898                 /* Set Extended packet length bit for jumbo frames */
1899                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1900         } else {
1901                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1902         }
1903
1904         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1905
1906         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1907                 reg32 &= ~0x3000;
1908                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1909         } else if (!err)
1910                 err = -EBUSY;
1911
1912         return err;
1913 }
1914
1915 /* This will reset the tigon3 PHY if there is no valid
1916  * link unless the FORCE argument is non-zero.
1917  */
1918 static int tg3_phy_reset(struct tg3 *tp)
1919 {
1920         u32 cpmuctrl;
1921         u32 phy_status;
1922         int err;
1923
1924         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1925                 u32 val;
1926
1927                 val = tr32(GRC_MISC_CFG);
1928                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1929                 udelay(40);
1930         }
1931         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1932         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1933         if (err != 0)
1934                 return -EBUSY;
1935
1936         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1937                 netif_carrier_off(tp->dev);
1938                 tg3_link_report(tp);
1939         }
1940
1941         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1942             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1943             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1944                 err = tg3_phy_reset_5703_4_5(tp);
1945                 if (err)
1946                         return err;
1947                 goto out;
1948         }
1949
1950         cpmuctrl = 0;
1951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1952             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1953                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1954                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1955                         tw32(TG3_CPMU_CTRL,
1956                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1957         }
1958
1959         err = tg3_bmcr_reset(tp);
1960         if (err)
1961                 return err;
1962
1963         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1964                 u32 phy;
1965
1966                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1967                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1968
1969                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1970         }
1971
1972         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1973             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1974                 u32 val;
1975
1976                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1977                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1978                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1979                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1980                         udelay(40);
1981                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1982                 }
1983         }
1984
1985         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1986              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1987             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1988                 return 0;
1989
1990         tg3_phy_apply_otp(tp);
1991
1992         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1993                 tg3_phy_toggle_apd(tp, true);
1994         else
1995                 tg3_phy_toggle_apd(tp, false);
1996
1997 out:
1998         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2000                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2001                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2003         }
2004         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2005                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2006                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2007         }
2008         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2010                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2011                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2012                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2013                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2014         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2015                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2016                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2017                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2018                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2019                         tg3_writephy(tp, MII_TG3_TEST1,
2020                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2021                 } else
2022                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2023                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2024         }
2025         /* Set Extended packet length bit (bit 14) on all chips that */
2026         /* support jumbo frames */
2027         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2028                 /* Cannot do read-modify-write on 5401 */
2029                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2030         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2031                 u32 phy_reg;
2032
2033                 /* Set bit 14 with read-modify-write to preserve other bits */
2034                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2035                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2036                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2037         }
2038
2039         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2040          * jumbo frames transmission.
2041          */
2042         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2043                 u32 phy_reg;
2044
2045                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2046                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2047                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2048         }
2049
2050         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2051                 /* adjust output voltage */
2052                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2053         }
2054
2055         tg3_phy_toggle_automdix(tp, 1);
2056         tg3_phy_set_wirespeed(tp);
2057         return 0;
2058 }
2059
2060 static void tg3_frob_aux_power(struct tg3 *tp)
2061 {
2062         struct tg3 *tp_peer = tp;
2063
2064         /* The GPIOs do something completely different on 57765. */
2065         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2066             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2068                 return;
2069
2070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2073                 struct net_device *dev_peer;
2074
2075                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2076                 /* remove_one() may have been run on the peer. */
2077                 if (!dev_peer)
2078                         tp_peer = tp;
2079                 else
2080                         tp_peer = netdev_priv(dev_peer);
2081         }
2082
2083         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2084             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2085             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2087                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2088                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2089                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090                                     (GRC_LCLCTRL_GPIO_OE0 |
2091                                      GRC_LCLCTRL_GPIO_OE1 |
2092                                      GRC_LCLCTRL_GPIO_OE2 |
2093                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2095                                     100);
2096                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2097                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2098                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2100                                              GRC_LCLCTRL_GPIO_OE1 |
2101                                              GRC_LCLCTRL_GPIO_OE2 |
2102                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2104                                              tp->grc_local_ctrl;
2105                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2106
2107                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2108                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2109
2110                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2111                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2112                 } else {
2113                         u32 no_gpio2;
2114                         u32 grc_local_ctrl = 0;
2115
2116                         if (tp_peer != tp &&
2117                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2118                                 return;
2119
2120                         /* Workaround to prevent overdrawing Amps. */
2121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2122                             ASIC_REV_5714) {
2123                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2124                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125                                             grc_local_ctrl, 100);
2126                         }
2127
2128                         /* On 5753 and variants, GPIO2 cannot be used. */
2129                         no_gpio2 = tp->nic_sram_data_cfg &
2130                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2131
2132                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2133                                          GRC_LCLCTRL_GPIO_OE1 |
2134                                          GRC_LCLCTRL_GPIO_OE2 |
2135                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2137                         if (no_gpio2) {
2138                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2139                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2140                         }
2141                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2142                                                     grc_local_ctrl, 100);
2143
2144                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2145
2146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147                                                     grc_local_ctrl, 100);
2148
2149                         if (!no_gpio2) {
2150                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2151                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                             grc_local_ctrl, 100);
2153                         }
2154                 }
2155         } else {
2156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2157                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2158                         if (tp_peer != tp &&
2159                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2160                                 return;
2161
2162                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163                                     (GRC_LCLCTRL_GPIO_OE1 |
2164                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2165
2166                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2167                                     GRC_LCLCTRL_GPIO_OE1, 100);
2168
2169                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2170                                     (GRC_LCLCTRL_GPIO_OE1 |
2171                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2172                 }
2173         }
2174 }
2175
2176 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2177 {
2178         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2179                 return 1;
2180         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2181                 if (speed != SPEED_10)
2182                         return 1;
2183         } else if (speed == SPEED_10)
2184                 return 1;
2185
2186         return 0;
2187 }
2188
2189 static int tg3_setup_phy(struct tg3 *, int);
2190
2191 #define RESET_KIND_SHUTDOWN     0
2192 #define RESET_KIND_INIT         1
2193 #define RESET_KIND_SUSPEND      2
2194
2195 static void tg3_write_sig_post_reset(struct tg3 *, int);
2196 static int tg3_halt_cpu(struct tg3 *, u32);
2197
2198 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2199 {
2200         u32 val;
2201
2202         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2204                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2205                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2206
2207                         sg_dig_ctrl |=
2208                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2209                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2210                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2211                 }
2212                 return;
2213         }
2214
2215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2216                 tg3_bmcr_reset(tp);
2217                 val = tr32(GRC_MISC_CFG);
2218                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2219                 udelay(40);
2220                 return;
2221         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2222                 u32 phytest;
2223                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2224                         u32 phy;
2225
2226                         tg3_writephy(tp, MII_ADVERTISE, 0);
2227                         tg3_writephy(tp, MII_BMCR,
2228                                      BMCR_ANENABLE | BMCR_ANRESTART);
2229
2230                         tg3_writephy(tp, MII_TG3_FET_TEST,
2231                                      phytest | MII_TG3_FET_SHADOW_EN);
2232                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2233                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2234                                 tg3_writephy(tp,
2235                                              MII_TG3_FET_SHDW_AUXMODE4,
2236                                              phy);
2237                         }
2238                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2239                 }
2240                 return;
2241         } else if (do_low_power) {
2242                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2243                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2244
2245                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2246                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2247                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2248                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2249                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2250         }
2251
2252         /* The PHY should not be powered down on some chips because
2253          * of bugs.
2254          */
2255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2256             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2257             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2258              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2259                 return;
2260
2261         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2262             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2263                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2264                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2265                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2266                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2267         }
2268
2269         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2270 }
2271
2272 /* tp->lock is held. */
2273 static int tg3_nvram_lock(struct tg3 *tp)
2274 {
2275         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2276                 int i;
2277
2278                 if (tp->nvram_lock_cnt == 0) {
2279                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2280                         for (i = 0; i < 8000; i++) {
2281                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2282                                         break;
2283                                 udelay(20);
2284                         }
2285                         if (i == 8000) {
2286                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2287                                 return -ENODEV;
2288                         }
2289                 }
2290                 tp->nvram_lock_cnt++;
2291         }
2292         return 0;
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_nvram_unlock(struct tg3 *tp)
2297 {
2298         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2299                 if (tp->nvram_lock_cnt > 0)
2300                         tp->nvram_lock_cnt--;
2301                 if (tp->nvram_lock_cnt == 0)
2302                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_enable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2314         }
2315 }
2316
2317 /* tp->lock is held. */
2318 static void tg3_disable_nvram_access(struct tg3 *tp)
2319 {
2320         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2321             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2322                 u32 nvaccess = tr32(NVRAM_ACCESS);
2323
2324                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2325         }
2326 }
2327
2328 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2329                                         u32 offset, u32 *val)
2330 {
2331         u32 tmp;
2332         int i;
2333
2334         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2335                 return -EINVAL;
2336
2337         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338                                         EEPROM_ADDR_DEVID_MASK |
2339                                         EEPROM_ADDR_READ);
2340         tw32(GRC_EEPROM_ADDR,
2341              tmp |
2342              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344               EEPROM_ADDR_ADDR_MASK) |
2345              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2346
2347         for (i = 0; i < 1000; i++) {
2348                 tmp = tr32(GRC_EEPROM_ADDR);
2349
2350                 if (tmp & EEPROM_ADDR_COMPLETE)
2351                         break;
2352                 msleep(1);
2353         }
2354         if (!(tmp & EEPROM_ADDR_COMPLETE))
2355                 return -EBUSY;
2356
2357         tmp = tr32(GRC_EEPROM_DATA);
2358
2359         /*
2360          * The data will always be opposite the native endian
2361          * format.  Perform a blind byteswap to compensate.
2362          */
2363         *val = swab32(tmp);
2364
2365         return 0;
2366 }
2367
2368 #define NVRAM_CMD_TIMEOUT 10000
2369
2370 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2371 {
2372         int i;
2373
2374         tw32(NVRAM_CMD, nvram_cmd);
2375         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2376                 udelay(10);
2377                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2378                         udelay(10);
2379                         break;
2380                 }
2381         }
2382
2383         if (i == NVRAM_CMD_TIMEOUT)
2384                 return -EBUSY;
2385
2386         return 0;
2387 }
2388
2389 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2390 {
2391         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2392             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2393             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2394            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2395             (tp->nvram_jedecnum == JEDEC_ATMEL))
2396
2397                 addr = ((addr / tp->nvram_pagesize) <<
2398                         ATMEL_AT45DB0X1B_PAGE_POS) +
2399                        (addr % tp->nvram_pagesize);
2400
2401         return addr;
2402 }
2403
2404 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2405 {
2406         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2407             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2408             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2409            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2410             (tp->nvram_jedecnum == JEDEC_ATMEL))
2411
2412                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2413                         tp->nvram_pagesize) +
2414                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2415
2416         return addr;
2417 }
2418
2419 /* NOTE: Data read in from NVRAM is byteswapped according to
2420  * the byteswapping settings for all other register accesses.
2421  * tg3 devices are BE devices, so on a BE machine, the data
2422  * returned will be exactly as it is seen in NVRAM.  On a LE
2423  * machine, the 32-bit value will be byteswapped.
2424  */
2425 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2426 {
2427         int ret;
2428
2429         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2430                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2431
2432         offset = tg3_nvram_phys_addr(tp, offset);
2433
2434         if (offset > NVRAM_ADDR_MSK)
2435                 return -EINVAL;
2436
2437         ret = tg3_nvram_lock(tp);
2438         if (ret)
2439                 return ret;
2440
2441         tg3_enable_nvram_access(tp);
2442
2443         tw32(NVRAM_ADDR, offset);
2444         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2445                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2446
2447         if (ret == 0)
2448                 *val = tr32(NVRAM_RDDATA);
2449
2450         tg3_disable_nvram_access(tp);
2451
2452         tg3_nvram_unlock(tp);
2453
2454         return ret;
2455 }
2456
2457 /* Ensures NVRAM data is in bytestream format. */
2458 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2459 {
2460         u32 v;
2461         int res = tg3_nvram_read(tp, offset, &v);
2462         if (!res)
2463                 *val = cpu_to_be32(v);
2464         return res;
2465 }
2466
2467 /* tp->lock is held. */
2468 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2469 {
2470         u32 addr_high, addr_low;
2471         int i;
2472
2473         addr_high = ((tp->dev->dev_addr[0] << 8) |
2474                      tp->dev->dev_addr[1]);
2475         addr_low = ((tp->dev->dev_addr[2] << 24) |
2476                     (tp->dev->dev_addr[3] << 16) |
2477                     (tp->dev->dev_addr[4] <<  8) |
2478                     (tp->dev->dev_addr[5] <<  0));
2479         for (i = 0; i < 4; i++) {
2480                 if (i == 1 && skip_mac_1)
2481                         continue;
2482                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2483                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2484         }
2485
2486         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2488                 for (i = 0; i < 12; i++) {
2489                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2490                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2491                 }
2492         }
2493
2494         addr_high = (tp->dev->dev_addr[0] +
2495                      tp->dev->dev_addr[1] +
2496                      tp->dev->dev_addr[2] +
2497                      tp->dev->dev_addr[3] +
2498                      tp->dev->dev_addr[4] +
2499                      tp->dev->dev_addr[5]) &
2500                 TX_BACKOFF_SEED_MASK;
2501         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2502 }
2503
2504 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2505 {
2506         u32 misc_host_ctrl;
2507         bool device_should_wake, do_low_power;
2508
2509         /* Make sure register accesses (indirect or otherwise)
2510          * will function correctly.
2511          */
2512         pci_write_config_dword(tp->pdev,
2513                                TG3PCI_MISC_HOST_CTRL,
2514                                tp->misc_host_ctrl);
2515
2516         switch (state) {
2517         case PCI_D0:
2518                 pci_enable_wake(tp->pdev, state, false);
2519                 pci_set_power_state(tp->pdev, PCI_D0);
2520
2521                 /* Switch out of Vaux if it is a NIC */
2522                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2523                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2524
2525                 return 0;
2526
2527         case PCI_D1:
2528         case PCI_D2:
2529         case PCI_D3hot:
2530                 break;
2531
2532         default:
2533                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2534                            state);
2535                 return -EINVAL;
2536         }
2537
2538         /* Restore the CLKREQ setting. */
2539         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2540                 u16 lnkctl;
2541
2542                 pci_read_config_word(tp->pdev,
2543                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2544                                      &lnkctl);
2545                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2546                 pci_write_config_word(tp->pdev,
2547                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2548                                       lnkctl);
2549         }
2550
2551         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2552         tw32(TG3PCI_MISC_HOST_CTRL,
2553              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2554
2555         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2556                              device_may_wakeup(&tp->pdev->dev) &&
2557                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2558
2559         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2560                 do_low_power = false;
2561                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2562                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2563                         struct phy_device *phydev;
2564                         u32 phyid, advertising;
2565
2566                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2567
2568                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2569
2570                         tp->link_config.orig_speed = phydev->speed;
2571                         tp->link_config.orig_duplex = phydev->duplex;
2572                         tp->link_config.orig_autoneg = phydev->autoneg;
2573                         tp->link_config.orig_advertising = phydev->advertising;
2574
2575                         advertising = ADVERTISED_TP |
2576                                       ADVERTISED_Pause |
2577                                       ADVERTISED_Autoneg |
2578                                       ADVERTISED_10baseT_Half;
2579
2580                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2581                             device_should_wake) {
2582                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2583                                         advertising |=
2584                                                 ADVERTISED_100baseT_Half |
2585                                                 ADVERTISED_100baseT_Full |
2586                                                 ADVERTISED_10baseT_Full;
2587                                 else
2588                                         advertising |= ADVERTISED_10baseT_Full;
2589                         }
2590
2591                         phydev->advertising = advertising;
2592
2593                         phy_start_aneg(phydev);
2594
2595                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2596                         if (phyid != PHY_ID_BCMAC131) {
2597                                 phyid &= PHY_BCM_OUI_MASK;
2598                                 if (phyid == PHY_BCM_OUI_1 ||
2599                                     phyid == PHY_BCM_OUI_2 ||
2600                                     phyid == PHY_BCM_OUI_3)
2601                                         do_low_power = true;
2602                         }
2603                 }
2604         } else {
2605                 do_low_power = true;
2606
2607                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2608                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2609                         tp->link_config.orig_speed = tp->link_config.speed;
2610                         tp->link_config.orig_duplex = tp->link_config.duplex;
2611                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2612                 }
2613
2614                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2615                         tp->link_config.speed = SPEED_10;
2616                         tp->link_config.duplex = DUPLEX_HALF;
2617                         tp->link_config.autoneg = AUTONEG_ENABLE;
2618                         tg3_setup_phy(tp, 0);
2619                 }
2620         }
2621
2622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2623                 u32 val;
2624
2625                 val = tr32(GRC_VCPU_EXT_CTRL);
2626                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2627         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2628                 int i;
2629                 u32 val;
2630
2631                 for (i = 0; i < 200; i++) {
2632                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2633                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2634                                 break;
2635                         msleep(1);
2636                 }
2637         }
2638         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2639                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2640                                                      WOL_DRV_STATE_SHUTDOWN |
2641                                                      WOL_DRV_WOL |
2642                                                      WOL_SET_MAGIC_PKT);
2643
2644         if (device_should_wake) {
2645                 u32 mac_mode;
2646
2647                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2648                         if (do_low_power) {
2649                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2650                                 udelay(40);
2651                         }
2652
2653                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2654                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2655                         else
2656                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2657
2658                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2659                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2660                             ASIC_REV_5700) {
2661                                 u32 speed = (tp->tg3_flags &
2662                                              TG3_FLAG_WOL_SPEED_100MB) ?
2663                                              SPEED_100 : SPEED_10;
2664                                 if (tg3_5700_link_polarity(tp, speed))
2665                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2666                                 else
2667                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668                         }
2669                 } else {
2670                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2671                 }
2672
2673                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2674                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2675
2676                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2677                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2678                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2679                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2680                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2681                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2682
2683                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2684                         mac_mode |= tp->mac_mode &
2685                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2686                         if (mac_mode & MAC_MODE_APE_TX_EN)
2687                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2688                 }
2689
2690                 tw32_f(MAC_MODE, mac_mode);
2691                 udelay(100);
2692
2693                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2694                 udelay(10);
2695         }
2696
2697         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2698             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2700                 u32 base_val;
2701
2702                 base_val = tp->pci_clock_ctrl;
2703                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2704                              CLOCK_CTRL_TXCLK_DISABLE);
2705
2706                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2707                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2708         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2709                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2710                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2711                 /* do nothing */
2712         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2713                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2714                 u32 newbits1, newbits2;
2715
2716                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2717                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2718                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2719                                     CLOCK_CTRL_TXCLK_DISABLE |
2720                                     CLOCK_CTRL_ALTCLK);
2721                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2722                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2723                         newbits1 = CLOCK_CTRL_625_CORE;
2724                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2725                 } else {
2726                         newbits1 = CLOCK_CTRL_ALTCLK;
2727                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2728                 }
2729
2730                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2731                             40);
2732
2733                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2734                             40);
2735
2736                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2737                         u32 newbits3;
2738
2739                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2741                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2742                                             CLOCK_CTRL_TXCLK_DISABLE |
2743                                             CLOCK_CTRL_44MHZ_CORE);
2744                         } else {
2745                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2746                         }
2747
2748                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2749                                     tp->pci_clock_ctrl | newbits3, 40);
2750                 }
2751         }
2752
2753         if (!(device_should_wake) &&
2754             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2755                 tg3_power_down_phy(tp, do_low_power);
2756
2757         tg3_frob_aux_power(tp);
2758
2759         /* Workaround for unstable PLL clock */
2760         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2761             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2762                 u32 val = tr32(0x7d00);
2763
2764                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2765                 tw32(0x7d00, val);
2766                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2767                         int err;
2768
2769                         err = tg3_nvram_lock(tp);
2770                         tg3_halt_cpu(tp, RX_CPU_BASE);
2771                         if (!err)
2772                                 tg3_nvram_unlock(tp);
2773                 }
2774         }
2775
2776         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2777
2778         if (device_should_wake)
2779                 pci_enable_wake(tp->pdev, state, true);
2780
2781         /* Finally, set the new power state. */
2782         pci_set_power_state(tp->pdev, state);
2783
2784         return 0;
2785 }
2786
2787 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2788 {
2789         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2790         case MII_TG3_AUX_STAT_10HALF:
2791                 *speed = SPEED_10;
2792                 *duplex = DUPLEX_HALF;
2793                 break;
2794
2795         case MII_TG3_AUX_STAT_10FULL:
2796                 *speed = SPEED_10;
2797                 *duplex = DUPLEX_FULL;
2798                 break;
2799
2800         case MII_TG3_AUX_STAT_100HALF:
2801                 *speed = SPEED_100;
2802                 *duplex = DUPLEX_HALF;
2803                 break;
2804
2805         case MII_TG3_AUX_STAT_100FULL:
2806                 *speed = SPEED_100;
2807                 *duplex = DUPLEX_FULL;
2808                 break;
2809
2810         case MII_TG3_AUX_STAT_1000HALF:
2811                 *speed = SPEED_1000;
2812                 *duplex = DUPLEX_HALF;
2813                 break;
2814
2815         case MII_TG3_AUX_STAT_1000FULL:
2816                 *speed = SPEED_1000;
2817                 *duplex = DUPLEX_FULL;
2818                 break;
2819
2820         default:
2821                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2822                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2823                                  SPEED_10;
2824                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2825                                   DUPLEX_HALF;
2826                         break;
2827                 }
2828                 *speed = SPEED_INVALID;
2829                 *duplex = DUPLEX_INVALID;
2830                 break;
2831         }
2832 }
2833
2834 static void tg3_phy_copper_begin(struct tg3 *tp)
2835 {
2836         u32 new_adv;
2837         int i;
2838
2839         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2840                 /* Entering low power mode.  Disable gigabit and
2841                  * 100baseT advertisements.
2842                  */
2843                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2844
2845                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2846                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2847                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2848                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2849
2850                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851         } else if (tp->link_config.speed == SPEED_INVALID) {
2852                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2853                         tp->link_config.advertising &=
2854                                 ~(ADVERTISED_1000baseT_Half |
2855                                   ADVERTISED_1000baseT_Full);
2856
2857                 new_adv = ADVERTISE_CSMA;
2858                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2859                         new_adv |= ADVERTISE_10HALF;
2860                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2861                         new_adv |= ADVERTISE_10FULL;
2862                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2863                         new_adv |= ADVERTISE_100HALF;
2864                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2865                         new_adv |= ADVERTISE_100FULL;
2866
2867                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2868
2869                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2870
2871                 if (tp->link_config.advertising &
2872                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2873                         new_adv = 0;
2874                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2875                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2876                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2877                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2878                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2879                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2880                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2881                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2882                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2883                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884                 } else {
2885                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2886                 }
2887         } else {
2888                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2889                 new_adv |= ADVERTISE_CSMA;
2890
2891                 /* Asking for a specific link mode. */
2892                 if (tp->link_config.speed == SPEED_1000) {
2893                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2894
2895                         if (tp->link_config.duplex == DUPLEX_FULL)
2896                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2897                         else
2898                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2899                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2900                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2901                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2902                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2903                 } else {
2904                         if (tp->link_config.speed == SPEED_100) {
2905                                 if (tp->link_config.duplex == DUPLEX_FULL)
2906                                         new_adv |= ADVERTISE_100FULL;
2907                                 else
2908                                         new_adv |= ADVERTISE_100HALF;
2909                         } else {
2910                                 if (tp->link_config.duplex == DUPLEX_FULL)
2911                                         new_adv |= ADVERTISE_10FULL;
2912                                 else
2913                                         new_adv |= ADVERTISE_10HALF;
2914                         }
2915                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2916
2917                         new_adv = 0;
2918                 }
2919
2920                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2921         }
2922
2923         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2924             tp->link_config.speed != SPEED_INVALID) {
2925                 u32 bmcr, orig_bmcr;
2926
2927                 tp->link_config.active_speed = tp->link_config.speed;
2928                 tp->link_config.active_duplex = tp->link_config.duplex;
2929
2930                 bmcr = 0;
2931                 switch (tp->link_config.speed) {
2932                 default:
2933                 case SPEED_10:
2934                         break;
2935
2936                 case SPEED_100:
2937                         bmcr |= BMCR_SPEED100;
2938                         break;
2939
2940                 case SPEED_1000:
2941                         bmcr |= TG3_BMCR_SPEED1000;
2942                         break;
2943                 }
2944
2945                 if (tp->link_config.duplex == DUPLEX_FULL)
2946                         bmcr |= BMCR_FULLDPLX;
2947
2948                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2949                     (bmcr != orig_bmcr)) {
2950                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2951                         for (i = 0; i < 1500; i++) {
2952                                 u32 tmp;
2953
2954                                 udelay(10);
2955                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2956                                     tg3_readphy(tp, MII_BMSR, &tmp))
2957                                         continue;
2958                                 if (!(tmp & BMSR_LSTATUS)) {
2959                                         udelay(40);
2960                                         break;
2961                                 }
2962                         }
2963                         tg3_writephy(tp, MII_BMCR, bmcr);
2964                         udelay(40);
2965                 }
2966         } else {
2967                 tg3_writephy(tp, MII_BMCR,
2968                              BMCR_ANENABLE | BMCR_ANRESTART);
2969         }
2970 }
2971
2972 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2973 {
2974         int err;
2975
2976         /* Turn off tap power management. */
2977         /* Set Extended packet length bit */
2978         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2979
2980         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2981         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2982         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2983         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2984         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2985
2986         udelay(40);
2987
2988         return err;
2989 }
2990
2991 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2992 {
2993         u32 adv_reg, all_mask = 0;
2994
2995         if (mask & ADVERTISED_10baseT_Half)
2996                 all_mask |= ADVERTISE_10HALF;
2997         if (mask & ADVERTISED_10baseT_Full)
2998                 all_mask |= ADVERTISE_10FULL;
2999         if (mask & ADVERTISED_100baseT_Half)
3000                 all_mask |= ADVERTISE_100HALF;
3001         if (mask & ADVERTISED_100baseT_Full)
3002                 all_mask |= ADVERTISE_100FULL;
3003
3004         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3005                 return 0;
3006
3007         if ((adv_reg & all_mask) != all_mask)
3008                 return 0;
3009         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3010                 u32 tg3_ctrl;
3011
3012                 all_mask = 0;
3013                 if (mask & ADVERTISED_1000baseT_Half)
3014                         all_mask |= ADVERTISE_1000HALF;
3015                 if (mask & ADVERTISED_1000baseT_Full)
3016                         all_mask |= ADVERTISE_1000FULL;
3017
3018                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3019                         return 0;
3020
3021                 if ((tg3_ctrl & all_mask) != all_mask)
3022                         return 0;
3023         }
3024         return 1;
3025 }
3026
3027 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3028 {
3029         u32 curadv, reqadv;
3030
3031         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3032                 return 1;
3033
3034         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3035         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3036
3037         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3038                 if (curadv != reqadv)
3039                         return 0;
3040
3041                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3042                         tg3_readphy(tp, MII_LPA, rmtadv);
3043         } else {
3044                 /* Reprogram the advertisement register, even if it
3045                  * does not affect the current link.  If the link
3046                  * gets renegotiated in the future, we can save an
3047                  * additional renegotiation cycle by advertising
3048                  * it correctly in the first place.
3049                  */
3050                 if (curadv != reqadv) {
3051                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3052                                      ADVERTISE_PAUSE_ASYM);
3053                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3054                 }
3055         }
3056
3057         return 1;
3058 }
3059
3060 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3061 {
3062         int current_link_up;
3063         u32 bmsr, dummy;
3064         u32 lcl_adv, rmt_adv;
3065         u16 current_speed;
3066         u8 current_duplex;
3067         int i, err;
3068
3069         tw32(MAC_EVENT, 0);
3070
3071         tw32_f(MAC_STATUS,
3072              (MAC_STATUS_SYNC_CHANGED |
3073               MAC_STATUS_CFG_CHANGED |
3074               MAC_STATUS_MI_COMPLETION |
3075               MAC_STATUS_LNKSTATE_CHANGED));
3076         udelay(40);
3077
3078         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3079                 tw32_f(MAC_MI_MODE,
3080                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3081                 udelay(80);
3082         }
3083
3084         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3085
3086         /* Some third-party PHYs need to be reset on link going
3087          * down.
3088          */
3089         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3090              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3091              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3092             netif_carrier_ok(tp->dev)) {
3093                 tg3_readphy(tp, MII_BMSR, &bmsr);
3094                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3095                     !(bmsr & BMSR_LSTATUS))
3096                         force_reset = 1;
3097         }
3098         if (force_reset)
3099                 tg3_phy_reset(tp);
3100
3101         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3102                 tg3_readphy(tp, MII_BMSR, &bmsr);
3103                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3104                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3105                         bmsr = 0;
3106
3107                 if (!(bmsr & BMSR_LSTATUS)) {
3108                         err = tg3_init_5401phy_dsp(tp);
3109                         if (err)
3110                                 return err;
3111
3112                         tg3_readphy(tp, MII_BMSR, &bmsr);
3113                         for (i = 0; i < 1000; i++) {
3114                                 udelay(10);
3115                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3116                                     (bmsr & BMSR_LSTATUS)) {
3117                                         udelay(40);
3118                                         break;
3119                                 }
3120                         }
3121
3122                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3123                             TG3_PHY_REV_BCM5401_B0 &&
3124                             !(bmsr & BMSR_LSTATUS) &&
3125                             tp->link_config.active_speed == SPEED_1000) {
3126                                 err = tg3_phy_reset(tp);
3127                                 if (!err)
3128                                         err = tg3_init_5401phy_dsp(tp);
3129                                 if (err)
3130                                         return err;
3131                         }
3132                 }
3133         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3134                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3135                 /* 5701 {A0,B0} CRC bug workaround */
3136                 tg3_writephy(tp, 0x15, 0x0a75);
3137                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3138                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3139                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3140         }
3141
3142         /* Clear pending interrupts... */
3143         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3144         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3145
3146         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3147                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3148         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3149                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3150
3151         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3152             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3153                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3154                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3155                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3156                 else
3157                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3158         }
3159
3160         current_link_up = 0;
3161         current_speed = SPEED_INVALID;
3162         current_duplex = DUPLEX_INVALID;
3163
3164         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3165                 u32 val;
3166
3167                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3168                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3169                 if (!(val & (1 << 10))) {
3170                         val |= (1 << 10);
3171                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3172                         goto relink;
3173                 }
3174         }
3175
3176         bmsr = 0;
3177         for (i = 0; i < 100; i++) {
3178                 tg3_readphy(tp, MII_BMSR, &bmsr);
3179                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3180                     (bmsr & BMSR_LSTATUS))
3181                         break;
3182                 udelay(40);
3183         }
3184
3185         if (bmsr & BMSR_LSTATUS) {
3186                 u32 aux_stat, bmcr;
3187
3188                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3189                 for (i = 0; i < 2000; i++) {
3190                         udelay(10);
3191                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3192                             aux_stat)
3193                                 break;
3194                 }
3195
3196                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3197                                              &current_speed,
3198                                              &current_duplex);
3199
3200                 bmcr = 0;
3201                 for (i = 0; i < 200; i++) {
3202                         tg3_readphy(tp, MII_BMCR, &bmcr);
3203                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3204                                 continue;
3205                         if (bmcr && bmcr != 0x7fff)
3206                                 break;
3207                         udelay(10);
3208                 }
3209
3210                 lcl_adv = 0;
3211                 rmt_adv = 0;
3212
3213                 tp->link_config.active_speed = current_speed;
3214                 tp->link_config.active_duplex = current_duplex;
3215
3216                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3217                         if ((bmcr & BMCR_ANENABLE) &&
3218                             tg3_copper_is_advertising_all(tp,
3219                                                 tp->link_config.advertising)) {
3220                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3221                                                                   &rmt_adv))
3222                                         current_link_up = 1;
3223                         }
3224                 } else {
3225                         if (!(bmcr & BMCR_ANENABLE) &&
3226                             tp->link_config.speed == current_speed &&
3227                             tp->link_config.duplex == current_duplex &&
3228                             tp->link_config.flowctrl ==
3229                             tp->link_config.active_flowctrl) {
3230                                 current_link_up = 1;
3231                         }
3232                 }
3233
3234                 if (current_link_up == 1 &&
3235                     tp->link_config.active_duplex == DUPLEX_FULL)
3236                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3237         }
3238
3239 relink:
3240         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3241                 u32 tmp;
3242
3243                 tg3_phy_copper_begin(tp);
3244
3245                 tg3_readphy(tp, MII_BMSR, &tmp);
3246                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3247                     (tmp & BMSR_LSTATUS))
3248                         current_link_up = 1;
3249         }
3250
3251         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3252         if (current_link_up == 1) {
3253                 if (tp->link_config.active_speed == SPEED_100 ||
3254                     tp->link_config.active_speed == SPEED_10)
3255                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3256                 else
3257                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3258         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3259                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3260         else
3261                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3262
3263         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3264         if (tp->link_config.active_duplex == DUPLEX_HALF)
3265                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3266
3267         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3268                 if (current_link_up == 1 &&
3269                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3270                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3271                 else
3272                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3273         }
3274
3275         /* ??? Without this setting Netgear GA302T PHY does not
3276          * ??? send/receive packets...
3277          */
3278         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3279             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3280                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3281                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3282                 udelay(80);
3283         }
3284
3285         tw32_f(MAC_MODE, tp->mac_mode);
3286         udelay(40);
3287
3288         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3289                 /* Polled via timer. */
3290                 tw32_f(MAC_EVENT, 0);
3291         } else {
3292                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3293         }
3294         udelay(40);
3295
3296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3297             current_link_up == 1 &&
3298             tp->link_config.active_speed == SPEED_1000 &&
3299             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3300              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3301                 udelay(120);
3302                 tw32_f(MAC_STATUS,
3303                      (MAC_STATUS_SYNC_CHANGED |
3304                       MAC_STATUS_CFG_CHANGED));
3305                 udelay(40);
3306                 tg3_write_mem(tp,
3307                               NIC_SRAM_FIRMWARE_MBOX,
3308                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3309         }
3310
3311         /* Prevent send BD corruption. */
3312         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3313                 u16 oldlnkctl, newlnkctl;
3314
3315                 pci_read_config_word(tp->pdev,
3316                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3317                                      &oldlnkctl);
3318                 if (tp->link_config.active_speed == SPEED_100 ||
3319                     tp->link_config.active_speed == SPEED_10)
3320                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3321                 else
3322                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3323                 if (newlnkctl != oldlnkctl)
3324                         pci_write_config_word(tp->pdev,
3325                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3326                                               newlnkctl);
3327         }
3328
3329         if (current_link_up != netif_carrier_ok(tp->dev)) {
3330                 if (current_link_up)
3331                         netif_carrier_on(tp->dev);
3332                 else
3333                         netif_carrier_off(tp->dev);
3334                 tg3_link_report(tp);
3335         }
3336
3337         return 0;
3338 }
3339
3340 struct tg3_fiber_aneginfo {
3341         int state;
3342 #define ANEG_STATE_UNKNOWN              0
3343 #define ANEG_STATE_AN_ENABLE            1
3344 #define ANEG_STATE_RESTART_INIT         2
3345 #define ANEG_STATE_RESTART              3
3346 #define ANEG_STATE_DISABLE_LINK_OK      4
3347 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3348 #define ANEG_STATE_ABILITY_DETECT       6
3349 #define ANEG_STATE_ACK_DETECT_INIT      7
3350 #define ANEG_STATE_ACK_DETECT           8
3351 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3352 #define ANEG_STATE_COMPLETE_ACK         10
3353 #define ANEG_STATE_IDLE_DETECT_INIT     11
3354 #define ANEG_STATE_IDLE_DETECT          12
3355 #define ANEG_STATE_LINK_OK              13
3356 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3357 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3358
3359         u32 flags;
3360 #define MR_AN_ENABLE            0x00000001
3361 #define MR_RESTART_AN           0x00000002
3362 #define MR_AN_COMPLETE          0x00000004
3363 #define MR_PAGE_RX              0x00000008
3364 #define MR_NP_LOADED            0x00000010
3365 #define MR_TOGGLE_TX            0x00000020
3366 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3367 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3368 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3369 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3370 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3371 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3372 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3373 #define MR_TOGGLE_RX            0x00002000
3374 #define MR_NP_RX                0x00004000
3375
3376 #define MR_LINK_OK              0x80000000
3377
3378         unsigned long link_time, cur_time;
3379
3380         u32 ability_match_cfg;
3381         int ability_match_count;
3382
3383         char ability_match, idle_match, ack_match;
3384
3385         u32 txconfig, rxconfig;
3386 #define ANEG_CFG_NP             0x00000080
3387 #define ANEG_CFG_ACK            0x00000040
3388 #define ANEG_CFG_RF2            0x00000020
3389 #define ANEG_CFG_RF1            0x00000010
3390 #define ANEG_CFG_PS2            0x00000001
3391 #define ANEG_CFG_PS1            0x00008000
3392 #define ANEG_CFG_HD             0x00004000
3393 #define ANEG_CFG_FD             0x00002000
3394 #define ANEG_CFG_INVAL          0x00001f06
3395
3396 };
3397 #define ANEG_OK         0
3398 #define ANEG_DONE       1
3399 #define ANEG_TIMER_ENAB 2
3400 #define ANEG_FAILED     -1
3401
3402 #define ANEG_STATE_SETTLE_TIME  10000
3403
3404 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3405                                    struct tg3_fiber_aneginfo *ap)
3406 {
3407         u16 flowctrl;
3408         unsigned long delta;
3409         u32 rx_cfg_reg;
3410         int ret;
3411
3412         if (ap->state == ANEG_STATE_UNKNOWN) {
3413                 ap->rxconfig = 0;
3414                 ap->link_time = 0;
3415                 ap->cur_time = 0;
3416                 ap->ability_match_cfg = 0;
3417                 ap->ability_match_count = 0;
3418                 ap->ability_match = 0;
3419                 ap->idle_match = 0;
3420                 ap->ack_match = 0;
3421         }
3422         ap->cur_time++;
3423
3424         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3425                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3426
3427                 if (rx_cfg_reg != ap->ability_match_cfg) {
3428                         ap->ability_match_cfg = rx_cfg_reg;
3429                         ap->ability_match = 0;
3430                         ap->ability_match_count = 0;
3431                 } else {
3432                         if (++ap->ability_match_count > 1) {
3433                                 ap->ability_match = 1;
3434                                 ap->ability_match_cfg = rx_cfg_reg;
3435                         }
3436                 }
3437                 if (rx_cfg_reg & ANEG_CFG_ACK)
3438                         ap->ack_match = 1;
3439                 else
3440                         ap->ack_match = 0;
3441
3442                 ap->idle_match = 0;
3443         } else {
3444                 ap->idle_match = 1;
3445                 ap->ability_match_cfg = 0;
3446                 ap->ability_match_count = 0;
3447                 ap->ability_match = 0;
3448                 ap->ack_match = 0;
3449
3450                 rx_cfg_reg = 0;
3451         }
3452
3453         ap->rxconfig = rx_cfg_reg;
3454         ret = ANEG_OK;
3455
3456         switch (ap->state) {
3457         case ANEG_STATE_UNKNOWN:
3458                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3459                         ap->state = ANEG_STATE_AN_ENABLE;
3460
3461                 /* fallthru */
3462         case ANEG_STATE_AN_ENABLE:
3463                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3464                 if (ap->flags & MR_AN_ENABLE) {
3465                         ap->link_time = 0;
3466                         ap->cur_time = 0;
3467                         ap->ability_match_cfg = 0;
3468                         ap->ability_match_count = 0;
3469                         ap->ability_match = 0;
3470                         ap->idle_match = 0;
3471                         ap->ack_match = 0;
3472
3473                         ap->state = ANEG_STATE_RESTART_INIT;
3474                 } else {
3475                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3476                 }
3477                 break;
3478
3479         case ANEG_STATE_RESTART_INIT:
3480                 ap->link_time = ap->cur_time;
3481                 ap->flags &= ~(MR_NP_LOADED);
3482                 ap->txconfig = 0;
3483                 tw32(MAC_TX_AUTO_NEG, 0);
3484                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3485                 tw32_f(MAC_MODE, tp->mac_mode);
3486                 udelay(40);
3487
3488                 ret = ANEG_TIMER_ENAB;
3489                 ap->state = ANEG_STATE_RESTART;
3490
3491                 /* fallthru */
3492         case ANEG_STATE_RESTART:
3493                 delta = ap->cur_time - ap->link_time;
3494                 if (delta > ANEG_STATE_SETTLE_TIME)
3495                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3496                 else
3497                         ret = ANEG_TIMER_ENAB;
3498                 break;
3499
3500         case ANEG_STATE_DISABLE_LINK_OK:
3501                 ret = ANEG_DONE;
3502                 break;
3503
3504         case ANEG_STATE_ABILITY_DETECT_INIT:
3505                 ap->flags &= ~(MR_TOGGLE_TX);
3506                 ap->txconfig = ANEG_CFG_FD;
3507                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3508                 if (flowctrl & ADVERTISE_1000XPAUSE)
3509                         ap->txconfig |= ANEG_CFG_PS1;
3510                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3511                         ap->txconfig |= ANEG_CFG_PS2;
3512                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3513                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3514                 tw32_f(MAC_MODE, tp->mac_mode);
3515                 udelay(40);
3516
3517                 ap->state = ANEG_STATE_ABILITY_DETECT;
3518                 break;
3519
3520         case ANEG_STATE_ABILITY_DETECT:
3521                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3522                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3523                 break;
3524
3525         case ANEG_STATE_ACK_DETECT_INIT:
3526                 ap->txconfig |= ANEG_CFG_ACK;
3527                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3528                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3529                 tw32_f(MAC_MODE, tp->mac_mode);
3530                 udelay(40);
3531
3532                 ap->state = ANEG_STATE_ACK_DETECT;
3533
3534                 /* fallthru */
3535         case ANEG_STATE_ACK_DETECT:
3536                 if (ap->ack_match != 0) {
3537                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3538                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3539                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3540                         } else {
3541                                 ap->state = ANEG_STATE_AN_ENABLE;
3542                         }
3543                 } else if (ap->ability_match != 0 &&
3544                            ap->rxconfig == 0) {
3545                         ap->state = ANEG_STATE_AN_ENABLE;
3546                 }
3547                 break;
3548
3549         case ANEG_STATE_COMPLETE_ACK_INIT:
3550                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3551                         ret = ANEG_FAILED;
3552                         break;
3553                 }
3554                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3555                                MR_LP_ADV_HALF_DUPLEX |
3556                                MR_LP_ADV_SYM_PAUSE |
3557                                MR_LP_ADV_ASYM_PAUSE |
3558                                MR_LP_ADV_REMOTE_FAULT1 |
3559                                MR_LP_ADV_REMOTE_FAULT2 |
3560                                MR_LP_ADV_NEXT_PAGE |
3561                                MR_TOGGLE_RX |
3562                                MR_NP_RX);
3563                 if (ap->rxconfig & ANEG_CFG_FD)
3564                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3565                 if (ap->rxconfig & ANEG_CFG_HD)
3566                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3567                 if (ap->rxconfig & ANEG_CFG_PS1)
3568                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3569                 if (ap->rxconfig & ANEG_CFG_PS2)
3570                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3571                 if (ap->rxconfig & ANEG_CFG_RF1)
3572                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3573                 if (ap->rxconfig & ANEG_CFG_RF2)
3574                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3575                 if (ap->rxconfig & ANEG_CFG_NP)
3576                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3577
3578                 ap->link_time = ap->cur_time;
3579
3580                 ap->flags ^= (MR_TOGGLE_TX);
3581                 if (ap->rxconfig & 0x0008)
3582                         ap->flags |= MR_TOGGLE_RX;
3583                 if (ap->rxconfig & ANEG_CFG_NP)
3584                         ap->flags |= MR_NP_RX;
3585                 ap->flags |= MR_PAGE_RX;
3586
3587                 ap->state = ANEG_STATE_COMPLETE_ACK;
3588                 ret = ANEG_TIMER_ENAB;
3589                 break;
3590
3591         case ANEG_STATE_COMPLETE_ACK:
3592                 if (ap->ability_match != 0 &&
3593                     ap->rxconfig == 0) {
3594                         ap->state = ANEG_STATE_AN_ENABLE;
3595                         break;
3596                 }
3597                 delta = ap->cur_time - ap->link_time;
3598                 if (delta > ANEG_STATE_SETTLE_TIME) {
3599                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3600                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3601                         } else {
3602                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3603                                     !(ap->flags & MR_NP_RX)) {
3604                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3605                                 } else {
3606                                         ret = ANEG_FAILED;
3607                                 }
3608                         }
3609                 }
3610                 break;
3611
3612         case ANEG_STATE_IDLE_DETECT_INIT:
3613                 ap->link_time = ap->cur_time;
3614                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3615                 tw32_f(MAC_MODE, tp->mac_mode);
3616                 udelay(40);
3617
3618                 ap->state = ANEG_STATE_IDLE_DETECT;
3619                 ret = ANEG_TIMER_ENAB;
3620                 break;
3621
3622         case ANEG_STATE_IDLE_DETECT:
3623                 if (ap->ability_match != 0 &&
3624                     ap->rxconfig == 0) {
3625                         ap->state = ANEG_STATE_AN_ENABLE;
3626                         break;
3627                 }
3628                 delta = ap->cur_time - ap->link_time;
3629                 if (delta > ANEG_STATE_SETTLE_TIME) {
3630                         /* XXX another gem from the Broadcom driver :( */
3631                         ap->state = ANEG_STATE_LINK_OK;
3632                 }
3633                 break;
3634
3635         case ANEG_STATE_LINK_OK:
3636                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3637                 ret = ANEG_DONE;
3638                 break;
3639
3640         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3641                 /* ??? unimplemented */
3642                 break;
3643
3644         case ANEG_STATE_NEXT_PAGE_WAIT:
3645                 /* ??? unimplemented */
3646                 break;
3647
3648         default:
3649                 ret = ANEG_FAILED;
3650                 break;
3651         }
3652
3653         return ret;
3654 }
3655
3656 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3657 {
3658         int res = 0;
3659         struct tg3_fiber_aneginfo aninfo;
3660         int status = ANEG_FAILED;
3661         unsigned int tick;
3662         u32 tmp;
3663
3664         tw32_f(MAC_TX_AUTO_NEG, 0);
3665
3666         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3667         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3668         udelay(40);
3669
3670         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3671         udelay(40);
3672
3673         memset(&aninfo, 0, sizeof(aninfo));
3674         aninfo.flags |= MR_AN_ENABLE;
3675         aninfo.state = ANEG_STATE_UNKNOWN;
3676         aninfo.cur_time = 0;
3677         tick = 0;
3678         while (++tick < 195000) {
3679                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3680                 if (status == ANEG_DONE || status == ANEG_FAILED)
3681                         break;
3682
3683                 udelay(1);
3684         }
3685
3686         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3687         tw32_f(MAC_MODE, tp->mac_mode);
3688         udelay(40);
3689
3690         *txflags = aninfo.txconfig;
3691         *rxflags = aninfo.flags;
3692
3693         if (status == ANEG_DONE &&
3694             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3695                              MR_LP_ADV_FULL_DUPLEX)))
3696                 res = 1;
3697
3698         return res;
3699 }
3700
3701 static void tg3_init_bcm8002(struct tg3 *tp)
3702 {
3703         u32 mac_status = tr32(MAC_STATUS);
3704         int i;
3705
3706         /* Reset when initting first time or we have a link. */
3707         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3708             !(mac_status & MAC_STATUS_PCS_SYNCED))
3709                 return;
3710
3711         /* Set PLL lock range. */
3712         tg3_writephy(tp, 0x16, 0x8007);
3713
3714         /* SW reset */
3715         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3716
3717         /* Wait for reset to complete. */
3718         /* XXX schedule_timeout() ... */
3719         for (i = 0; i < 500; i++)
3720                 udelay(10);
3721
3722         /* Config mode; select PMA/Ch 1 regs. */
3723         tg3_writephy(tp, 0x10, 0x8411);
3724
3725         /* Enable auto-lock and comdet, select txclk for tx. */
3726         tg3_writephy(tp, 0x11, 0x0a10);
3727
3728         tg3_writephy(tp, 0x18, 0x00a0);
3729         tg3_writephy(tp, 0x16, 0x41ff);
3730
3731         /* Assert and deassert POR. */
3732         tg3_writephy(tp, 0x13, 0x0400);
3733         udelay(40);
3734         tg3_writephy(tp, 0x13, 0x0000);
3735
3736         tg3_writephy(tp, 0x11, 0x0a50);
3737         udelay(40);
3738         tg3_writephy(tp, 0x11, 0x0a10);
3739
3740         /* Wait for signal to stabilize */
3741         /* XXX schedule_timeout() ... */
3742         for (i = 0; i < 15000; i++)
3743                 udelay(10);
3744
3745         /* Deselect the channel register so we can read the PHYID
3746          * later.
3747          */
3748         tg3_writephy(tp, 0x10, 0x8011);
3749 }
3750
3751 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3752 {
3753         u16 flowctrl;
3754         u32 sg_dig_ctrl, sg_dig_status;
3755         u32 serdes_cfg, expected_sg_dig_ctrl;
3756         int workaround, port_a;
3757         int current_link_up;
3758
3759         serdes_cfg = 0;
3760         expected_sg_dig_ctrl = 0;
3761         workaround = 0;
3762         port_a = 1;
3763         current_link_up = 0;
3764
3765         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3766             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3767                 workaround = 1;
3768                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3769                         port_a = 0;
3770
3771                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3772                 /* preserve bits 20-23 for voltage regulator */
3773                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3774         }
3775
3776         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3777
3778         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3779                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3780                         if (workaround) {
3781                                 u32 val = serdes_cfg;
3782
3783                                 if (port_a)
3784                                         val |= 0xc010000;
3785                                 else
3786                                         val |= 0x4010000;
3787                                 tw32_f(MAC_SERDES_CFG, val);
3788                         }
3789
3790                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3791                 }
3792                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3793                         tg3_setup_flow_control(tp, 0, 0);
3794                         current_link_up = 1;
3795                 }
3796                 goto out;
3797         }
3798
3799         /* Want auto-negotiation.  */
3800         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3801
3802         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3803         if (flowctrl & ADVERTISE_1000XPAUSE)
3804                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3805         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3806                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3807
3808         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3809                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3810                     tp->serdes_counter &&
3811                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3812                                     MAC_STATUS_RCVD_CFG)) ==
3813                      MAC_STATUS_PCS_SYNCED)) {
3814                         tp->serdes_counter--;
3815                         current_link_up = 1;
3816                         goto out;
3817                 }
3818 restart_autoneg:
3819                 if (workaround)
3820                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3821                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3822                 udelay(5);
3823                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3824
3825                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3826                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3827         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3828                                  MAC_STATUS_SIGNAL_DET)) {
3829                 sg_dig_status = tr32(SG_DIG_STATUS);
3830                 mac_status = tr32(MAC_STATUS);
3831
3832                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3833                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3834                         u32 local_adv = 0, remote_adv = 0;
3835
3836                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3837                                 local_adv |= ADVERTISE_1000XPAUSE;
3838                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3839                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3840
3841                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3842                                 remote_adv |= LPA_1000XPAUSE;
3843                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3844                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3845
3846                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3847                         current_link_up = 1;
3848                         tp->serdes_counter = 0;
3849                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3850                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3851                         if (tp->serdes_counter)
3852                                 tp->serdes_counter--;
3853                         else {
3854                                 if (workaround) {
3855                                         u32 val = serdes_cfg;
3856
3857                                         if (port_a)
3858                                                 val |= 0xc010000;
3859                                         else
3860                                                 val |= 0x4010000;
3861
3862                                         tw32_f(MAC_SERDES_CFG, val);
3863                                 }
3864
3865                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3866                                 udelay(40);
3867
3868                                 /* Link parallel detection - link is up */
3869                                 /* only if we have PCS_SYNC and not */
3870                                 /* receiving config code words */
3871                                 mac_status = tr32(MAC_STATUS);
3872                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3873                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3874                                         tg3_setup_flow_control(tp, 0, 0);
3875                                         current_link_up = 1;
3876                                         tp->phy_flags |=
3877                                                 TG3_PHYFLG_PARALLEL_DETECT;
3878                                         tp->serdes_counter =
3879                                                 SERDES_PARALLEL_DET_TIMEOUT;
3880                                 } else
3881                                         goto restart_autoneg;
3882                         }
3883                 }
3884         } else {
3885                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3886                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3887         }
3888
3889 out:
3890         return current_link_up;
3891 }
3892
3893 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3894 {
3895         int current_link_up = 0;
3896
3897         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3898                 goto out;
3899
3900         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3901                 u32 txflags, rxflags;
3902                 int i;
3903
3904                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3905                         u32 local_adv = 0, remote_adv = 0;
3906
3907                         if (txflags & ANEG_CFG_PS1)
3908                                 local_adv |= ADVERTISE_1000XPAUSE;
3909                         if (txflags & ANEG_CFG_PS2)
3910                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3911
3912                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3913                                 remote_adv |= LPA_1000XPAUSE;
3914                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3915                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3916
3917                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3918
3919                         current_link_up = 1;
3920                 }
3921                 for (i = 0; i < 30; i++) {
3922                         udelay(20);
3923                         tw32_f(MAC_STATUS,
3924                                (MAC_STATUS_SYNC_CHANGED |
3925                                 MAC_STATUS_CFG_CHANGED));
3926                         udelay(40);
3927                         if ((tr32(MAC_STATUS) &
3928                              (MAC_STATUS_SYNC_CHANGED |
3929                               MAC_STATUS_CFG_CHANGED)) == 0)
3930                                 break;
3931                 }
3932
3933                 mac_status = tr32(MAC_STATUS);
3934                 if (current_link_up == 0 &&
3935                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3936                     !(mac_status & MAC_STATUS_RCVD_CFG))
3937                         current_link_up = 1;
3938         } else {
3939                 tg3_setup_flow_control(tp, 0, 0);
3940
3941                 /* Forcing 1000FD link up. */
3942                 current_link_up = 1;
3943
3944                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3945                 udelay(40);
3946
3947                 tw32_f(MAC_MODE, tp->mac_mode);
3948                 udelay(40);
3949         }
3950
3951 out:
3952         return current_link_up;
3953 }
3954
3955 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3956 {
3957         u32 orig_pause_cfg;
3958         u16 orig_active_speed;
3959         u8 orig_active_duplex;
3960         u32 mac_status;
3961         int current_link_up;
3962         int i;
3963
3964         orig_pause_cfg = tp->link_config.active_flowctrl;
3965         orig_active_speed = tp->link_config.active_speed;
3966         orig_active_duplex = tp->link_config.active_duplex;
3967
3968         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3969             netif_carrier_ok(tp->dev) &&
3970             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3971                 mac_status = tr32(MAC_STATUS);
3972                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3973                                MAC_STATUS_SIGNAL_DET |
3974                                MAC_STATUS_CFG_CHANGED |
3975                                MAC_STATUS_RCVD_CFG);
3976                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3977                                    MAC_STATUS_SIGNAL_DET)) {
3978                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979                                             MAC_STATUS_CFG_CHANGED));
3980                         return 0;
3981                 }
3982         }
3983
3984         tw32_f(MAC_TX_AUTO_NEG, 0);
3985
3986         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3987         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3988         tw32_f(MAC_MODE, tp->mac_mode);
3989         udelay(40);
3990
3991         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3992                 tg3_init_bcm8002(tp);
3993
3994         /* Enable link change event even when serdes polling.  */
3995         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3996         udelay(40);
3997
3998         current_link_up = 0;
3999         mac_status = tr32(MAC_STATUS);
4000
4001         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4002                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4003         else
4004                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4005
4006         tp->napi[0].hw_status->status =
4007                 (SD_STATUS_UPDATED |
4008                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4009
4010         for (i = 0; i < 100; i++) {
4011                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4012                                     MAC_STATUS_CFG_CHANGED));
4013                 udelay(5);
4014                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4015                                          MAC_STATUS_CFG_CHANGED |
4016                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4017                         break;
4018         }
4019
4020         mac_status = tr32(MAC_STATUS);
4021         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4022                 current_link_up = 0;
4023                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4024                     tp->serdes_counter == 0) {
4025                         tw32_f(MAC_MODE, (tp->mac_mode |
4026                                           MAC_MODE_SEND_CONFIGS));
4027                         udelay(1);
4028                         tw32_f(MAC_MODE, tp->mac_mode);
4029                 }
4030         }
4031
4032         if (current_link_up == 1) {
4033                 tp->link_config.active_speed = SPEED_1000;
4034                 tp->link_config.active_duplex = DUPLEX_FULL;
4035                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4036                                     LED_CTRL_LNKLED_OVERRIDE |
4037                                     LED_CTRL_1000MBPS_ON));
4038         } else {
4039                 tp->link_config.active_speed = SPEED_INVALID;
4040                 tp->link_config.active_duplex = DUPLEX_INVALID;
4041                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4042                                     LED_CTRL_LNKLED_OVERRIDE |
4043                                     LED_CTRL_TRAFFIC_OVERRIDE));
4044         }
4045
4046         if (current_link_up != netif_carrier_ok(tp->dev)) {
4047                 if (current_link_up)
4048                         netif_carrier_on(tp->dev);
4049                 else
4050                         netif_carrier_off(tp->dev);
4051                 tg3_link_report(tp);
4052         } else {
4053                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4054                 if (orig_pause_cfg != now_pause_cfg ||
4055                     orig_active_speed != tp->link_config.active_speed ||
4056                     orig_active_duplex != tp->link_config.active_duplex)
4057                         tg3_link_report(tp);
4058         }
4059
4060         return 0;
4061 }
4062
4063 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4064 {
4065         int current_link_up, err = 0;
4066         u32 bmsr, bmcr;
4067         u16 current_speed;
4068         u8 current_duplex;
4069         u32 local_adv, remote_adv;
4070
4071         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4072         tw32_f(MAC_MODE, tp->mac_mode);
4073         udelay(40);
4074
4075         tw32(MAC_EVENT, 0);
4076
4077         tw32_f(MAC_STATUS,
4078              (MAC_STATUS_SYNC_CHANGED |
4079               MAC_STATUS_CFG_CHANGED |
4080               MAC_STATUS_MI_COMPLETION |
4081               MAC_STATUS_LNKSTATE_CHANGED));
4082         udelay(40);
4083
4084         if (force_reset)
4085                 tg3_phy_reset(tp);
4086
4087         current_link_up = 0;
4088         current_speed = SPEED_INVALID;
4089         current_duplex = DUPLEX_INVALID;
4090
4091         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4092         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4093         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4094                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4095                         bmsr |= BMSR_LSTATUS;
4096                 else
4097                         bmsr &= ~BMSR_LSTATUS;
4098         }
4099
4100         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4101
4102         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4103             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4104                 /* do nothing, just check for link up at the end */
4105         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4106                 u32 adv, new_adv;
4107
4108                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4109                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4110                                   ADVERTISE_1000XPAUSE |
4111                                   ADVERTISE_1000XPSE_ASYM |
4112                                   ADVERTISE_SLCT);
4113
4114                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4115
4116                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4117                         new_adv |= ADVERTISE_1000XHALF;
4118                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4119                         new_adv |= ADVERTISE_1000XFULL;
4120
4121                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4122                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4123                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4124                         tg3_writephy(tp, MII_BMCR, bmcr);
4125
4126                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4127                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4128                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4129
4130                         return err;
4131                 }
4132         } else {
4133                 u32 new_bmcr;
4134
4135                 bmcr &= ~BMCR_SPEED1000;
4136                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4137
4138                 if (tp->link_config.duplex == DUPLEX_FULL)
4139                         new_bmcr |= BMCR_FULLDPLX;
4140
4141                 if (new_bmcr != bmcr) {
4142                         /* BMCR_SPEED1000 is a reserved bit that needs
4143                          * to be set on write.
4144                          */
4145                         new_bmcr |= BMCR_SPEED1000;
4146
4147                         /* Force a linkdown */
4148                         if (netif_carrier_ok(tp->dev)) {
4149                                 u32 adv;
4150
4151                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4152                                 adv &= ~(ADVERTISE_1000XFULL |
4153                                          ADVERTISE_1000XHALF |
4154                                          ADVERTISE_SLCT);
4155                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4156                                 tg3_writephy(tp, MII_BMCR, bmcr |
4157                                                            BMCR_ANRESTART |
4158                                                            BMCR_ANENABLE);
4159                                 udelay(10);
4160                                 netif_carrier_off(tp->dev);
4161                         }
4162                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4163                         bmcr = new_bmcr;
4164                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4165                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4166                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4167                             ASIC_REV_5714) {
4168                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4169                                         bmsr |= BMSR_LSTATUS;
4170                                 else
4171                                         bmsr &= ~BMSR_LSTATUS;
4172                         }
4173                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4174                 }
4175         }
4176
4177         if (bmsr & BMSR_LSTATUS) {
4178                 current_speed = SPEED_1000;
4179                 current_link_up = 1;
4180                 if (bmcr & BMCR_FULLDPLX)
4181                         current_duplex = DUPLEX_FULL;
4182                 else
4183                         current_duplex = DUPLEX_HALF;
4184
4185                 local_adv = 0;
4186                 remote_adv = 0;
4187
4188                 if (bmcr & BMCR_ANENABLE) {
4189                         u32 common;
4190
4191                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4192                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4193                         common = local_adv & remote_adv;
4194                         if (common & (ADVERTISE_1000XHALF |
4195                                       ADVERTISE_1000XFULL)) {
4196                                 if (common & ADVERTISE_1000XFULL)
4197                                         current_duplex = DUPLEX_FULL;
4198                                 else
4199                                         current_duplex = DUPLEX_HALF;
4200                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4201                                 /* Link is up via parallel detect */
4202                         } else {
4203                                 current_link_up = 0;
4204                         }
4205                 }
4206         }
4207
4208         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4209                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4210
4211         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4212         if (tp->link_config.active_duplex == DUPLEX_HALF)
4213                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4214
4215         tw32_f(MAC_MODE, tp->mac_mode);
4216         udelay(40);
4217
4218         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4219
4220         tp->link_config.active_speed = current_speed;
4221         tp->link_config.active_duplex = current_duplex;
4222
4223         if (current_link_up != netif_carrier_ok(tp->dev)) {
4224                 if (current_link_up)
4225                         netif_carrier_on(tp->dev);
4226                 else {
4227                         netif_carrier_off(tp->dev);
4228                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4229                 }
4230                 tg3_link_report(tp);
4231         }
4232         return err;
4233 }
4234
4235 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4236 {
4237         if (tp->serdes_counter) {
4238                 /* Give autoneg time to complete. */
4239                 tp->serdes_counter--;
4240                 return;
4241         }
4242
4243         if (!netif_carrier_ok(tp->dev) &&
4244             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4245                 u32 bmcr;
4246
4247                 tg3_readphy(tp, MII_BMCR, &bmcr);
4248                 if (bmcr & BMCR_ANENABLE) {
4249                         u32 phy1, phy2;
4250
4251                         /* Select shadow register 0x1f */
4252                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4253                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4254
4255                         /* Select expansion interrupt status register */
4256                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4257                                          MII_TG3_DSP_EXP1_INT_STAT);
4258                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4259                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4260
4261                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4262                                 /* We have signal detect and not receiving
4263                                  * config code words, link is up by parallel
4264                                  * detection.
4265                                  */
4266
4267                                 bmcr &= ~BMCR_ANENABLE;
4268                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4269                                 tg3_writephy(tp, MII_BMCR, bmcr);
4270                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4271                         }
4272                 }
4273         } else if (netif_carrier_ok(tp->dev) &&
4274                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4275                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4276                 u32 phy2;
4277
4278                 /* Select expansion interrupt status register */
4279                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4280                                  MII_TG3_DSP_EXP1_INT_STAT);
4281                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4282                 if (phy2 & 0x20) {
4283                         u32 bmcr;
4284
4285                         /* Config code words received, turn on autoneg. */
4286                         tg3_readphy(tp, MII_BMCR, &bmcr);
4287                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4288
4289                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4290
4291                 }
4292         }
4293 }
4294
4295 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4296 {
4297         int err;
4298
4299         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4300                 err = tg3_setup_fiber_phy(tp, force_reset);
4301         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4302                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4303         else
4304                 err = tg3_setup_copper_phy(tp, force_reset);
4305
4306         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4307                 u32 val, scale;
4308
4309                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4310                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4311                         scale = 65;
4312                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4313                         scale = 6;
4314                 else
4315                         scale = 12;
4316
4317                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4318                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4319                 tw32(GRC_MISC_CFG, val);
4320         }
4321
4322         if (tp->link_config.active_speed == SPEED_1000 &&
4323             tp->link_config.active_duplex == DUPLEX_HALF)
4324                 tw32(MAC_TX_LENGTHS,
4325                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4326                       (6 << TX_LENGTHS_IPG_SHIFT) |
4327                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4328         else
4329                 tw32(MAC_TX_LENGTHS,
4330                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4331                       (6 << TX_LENGTHS_IPG_SHIFT) |
4332                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4333
4334         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4335                 if (netif_carrier_ok(tp->dev)) {
4336                         tw32(HOSTCC_STAT_COAL_TICKS,
4337                              tp->coal.stats_block_coalesce_usecs);
4338                 } else {
4339                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4340                 }
4341         }
4342
4343         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4344                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4345                 if (!netif_carrier_ok(tp->dev))
4346                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4347                               tp->pwrmgmt_thresh;
4348                 else
4349                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4350                 tw32(PCIE_PWR_MGMT_THRESH, val);
4351         }
4352
4353         return err;
4354 }
4355
4356 /* This is called whenever we suspect that the system chipset is re-
4357  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4358  * is bogus tx completions. We try to recover by setting the
4359  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4360  * in the workqueue.
4361  */
4362 static void tg3_tx_recover(struct tg3 *tp)
4363 {
4364         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4365                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4366
4367         netdev_warn(tp->dev,
4368                     "The system may be re-ordering memory-mapped I/O "
4369                     "cycles to the network device, attempting to recover. "
4370                     "Please report the problem to the driver maintainer "
4371                     "and include system chipset information.\n");
4372
4373         spin_lock(&tp->lock);
4374         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4375         spin_unlock(&tp->lock);
4376 }
4377
4378 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4379 {
4380         /* Tell compiler to fetch tx indices from memory. */
4381         barrier();
4382         return tnapi->tx_pending -
4383                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4384 }
4385
4386 /* Tigon3 never reports partial packet sends.  So we do not
4387  * need special logic to handle SKBs that have not had all
4388  * of their frags sent yet, like SunGEM does.
4389  */
4390 static void tg3_tx(struct tg3_napi *tnapi)
4391 {
4392         struct tg3 *tp = tnapi->tp;
4393         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4394         u32 sw_idx = tnapi->tx_cons;
4395         struct netdev_queue *txq;
4396         int index = tnapi - tp->napi;
4397
4398         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4399                 index--;
4400
4401         txq = netdev_get_tx_queue(tp->dev, index);
4402
4403         while (sw_idx != hw_idx) {
4404                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4405                 struct sk_buff *skb = ri->skb;
4406                 int i, tx_bug = 0;
4407
4408                 if (unlikely(skb == NULL)) {
4409                         tg3_tx_recover(tp);
4410                         return;
4411                 }
4412
4413                 pci_unmap_single(tp->pdev,
4414                                  dma_unmap_addr(ri, mapping),
4415                                  skb_headlen(skb),
4416                                  PCI_DMA_TODEVICE);
4417
4418                 ri->skb = NULL;
4419
4420                 sw_idx = NEXT_TX(sw_idx);
4421
4422                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4423                         ri = &tnapi->tx_buffers[sw_idx];
4424                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4425                                 tx_bug = 1;
4426
4427                         pci_unmap_page(tp->pdev,
4428                                        dma_unmap_addr(ri, mapping),
4429                                        skb_shinfo(skb)->frags[i].size,
4430                                        PCI_DMA_TODEVICE);
4431                         sw_idx = NEXT_TX(sw_idx);
4432                 }
4433
4434                 dev_kfree_skb(skb);
4435
4436                 if (unlikely(tx_bug)) {
4437                         tg3_tx_recover(tp);
4438                         return;
4439                 }
4440         }
4441
4442         tnapi->tx_cons = sw_idx;
4443
4444         /* Need to make the tx_cons update visible to tg3_start_xmit()
4445          * before checking for netif_queue_stopped().  Without the
4446          * memory barrier, there is a small possibility that tg3_start_xmit()
4447          * will miss it and cause the queue to be stopped forever.
4448          */
4449         smp_mb();
4450
4451         if (unlikely(netif_tx_queue_stopped(txq) &&
4452                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4453                 __netif_tx_lock(txq, smp_processor_id());
4454                 if (netif_tx_queue_stopped(txq) &&
4455                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4456                         netif_tx_wake_queue(txq);
4457                 __netif_tx_unlock(txq);
4458         }
4459 }
4460
4461 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4462 {
4463         if (!ri->skb)
4464                 return;
4465
4466         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4467                          map_sz, PCI_DMA_FROMDEVICE);
4468         dev_kfree_skb_any(ri->skb);
4469         ri->skb = NULL;
4470 }
4471
4472 /* Returns size of skb allocated or < 0 on error.
4473  *
4474  * We only need to fill in the address because the other members
4475  * of the RX descriptor are invariant, see tg3_init_rings.
4476  *
4477  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4478  * posting buffers we only dirty the first cache line of the RX
4479  * descriptor (containing the address).  Whereas for the RX status
4480  * buffers the cpu only reads the last cacheline of the RX descriptor
4481  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4482  */
4483 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4484                             u32 opaque_key, u32 dest_idx_unmasked)
4485 {
4486         struct tg3_rx_buffer_desc *desc;
4487         struct ring_info *map, *src_map;
4488         struct sk_buff *skb;
4489         dma_addr_t mapping;
4490         int skb_size, dest_idx;
4491
4492         src_map = NULL;
4493         switch (opaque_key) {
4494         case RXD_OPAQUE_RING_STD:
4495                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4496                 desc = &tpr->rx_std[dest_idx];
4497                 map = &tpr->rx_std_buffers[dest_idx];
4498                 skb_size = tp->rx_pkt_map_sz;
4499                 break;
4500
4501         case RXD_OPAQUE_RING_JUMBO:
4502                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4503                 desc = &tpr->rx_jmb[dest_idx].std;
4504                 map = &tpr->rx_jmb_buffers[dest_idx];
4505                 skb_size = TG3_RX_JMB_MAP_SZ;
4506                 break;
4507
4508         default:
4509                 return -EINVAL;
4510         }
4511
4512         /* Do not overwrite any of the map or rp information
4513          * until we are sure we can commit to a new buffer.
4514          *
4515          * Callers depend upon this behavior and assume that
4516          * we leave everything unchanged if we fail.
4517          */
4518         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4519         if (skb == NULL)
4520                 return -ENOMEM;
4521
4522         skb_reserve(skb, tp->rx_offset);
4523
4524         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4525                                  PCI_DMA_FROMDEVICE);
4526         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4527                 dev_kfree_skb(skb);
4528                 return -EIO;
4529         }
4530
4531         map->skb = skb;
4532         dma_unmap_addr_set(map, mapping, mapping);
4533
4534         desc->addr_hi = ((u64)mapping >> 32);
4535         desc->addr_lo = ((u64)mapping & 0xffffffff);
4536
4537         return skb_size;
4538 }
4539
4540 /* We only need to move over in the address because the other
4541  * members of the RX descriptor are invariant.  See notes above
4542  * tg3_alloc_rx_skb for full details.
4543  */
4544 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4545                            struct tg3_rx_prodring_set *dpr,
4546                            u32 opaque_key, int src_idx,
4547                            u32 dest_idx_unmasked)
4548 {
4549         struct tg3 *tp = tnapi->tp;
4550         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4551         struct ring_info *src_map, *dest_map;
4552         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4553         int dest_idx;
4554
4555         switch (opaque_key) {
4556         case RXD_OPAQUE_RING_STD:
4557                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4558                 dest_desc = &dpr->rx_std[dest_idx];
4559                 dest_map = &dpr->rx_std_buffers[dest_idx];
4560                 src_desc = &spr->rx_std[src_idx];
4561                 src_map = &spr->rx_std_buffers[src_idx];
4562                 break;
4563
4564         case RXD_OPAQUE_RING_JUMBO:
4565                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4566                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4567                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4568                 src_desc = &spr->rx_jmb[src_idx].std;
4569                 src_map = &spr->rx_jmb_buffers[src_idx];
4570                 break;
4571
4572         default:
4573                 return;
4574         }
4575
4576         dest_map->skb = src_map->skb;
4577         dma_unmap_addr_set(dest_map, mapping,
4578                            dma_unmap_addr(src_map, mapping));
4579         dest_desc->addr_hi = src_desc->addr_hi;
4580         dest_desc->addr_lo = src_desc->addr_lo;
4581
4582         /* Ensure that the update to the skb happens after the physical
4583          * addresses have been transferred to the new BD location.
4584          */
4585         smp_wmb();
4586
4587         src_map->skb = NULL;
4588 }
4589
4590 /* The RX ring scheme is composed of multiple rings which post fresh
4591  * buffers to the chip, and one special ring the chip uses to report
4592  * status back to the host.
4593  *
4594  * The special ring reports the status of received packets to the
4595  * host.  The chip does not write into the original descriptor the
4596  * RX buffer was obtained from.  The chip simply takes the original
4597  * descriptor as provided by the host, updates the status and length
4598  * field, then writes this into the next status ring entry.
4599  *
4600  * Each ring the host uses to post buffers to the chip is described
4601  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4602  * it is first placed into the on-chip ram.  When the packet's length
4603  * is known, it walks down the TG3_BDINFO entries to select the ring.
4604  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4605  * which is within the range of the new packet's length is chosen.
4606  *
4607  * The "separate ring for rx status" scheme may sound queer, but it makes
4608  * sense from a cache coherency perspective.  If only the host writes
4609  * to the buffer post rings, and only the chip writes to the rx status
4610  * rings, then cache lines never move beyond shared-modified state.
4611  * If both the host and chip were to write into the same ring, cache line
4612  * eviction could occur since both entities want it in an exclusive state.
4613  */
4614 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4615 {
4616         struct tg3 *tp = tnapi->tp;
4617         u32 work_mask, rx_std_posted = 0;
4618         u32 std_prod_idx, jmb_prod_idx;
4619         u32 sw_idx = tnapi->rx_rcb_ptr;
4620         u16 hw_idx;
4621         int received;
4622         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4623
4624         hw_idx = *(tnapi->rx_rcb_prod_idx);
4625         /*
4626          * We need to order the read of hw_idx and the read of
4627          * the opaque cookie.
4628          */
4629         rmb();
4630         work_mask = 0;
4631         received = 0;
4632         std_prod_idx = tpr->rx_std_prod_idx;
4633         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4634         while (sw_idx != hw_idx && budget > 0) {
4635                 struct ring_info *ri;
4636                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4637                 unsigned int len;
4638                 struct sk_buff *skb;
4639                 dma_addr_t dma_addr;
4640                 u32 opaque_key, desc_idx, *post_ptr;
4641                 bool hw_vlan __maybe_unused = false;
4642                 u16 vtag __maybe_unused = 0;
4643
4644                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4645                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4646                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4647                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4648                         dma_addr = dma_unmap_addr(ri, mapping);
4649                         skb = ri->skb;
4650                         post_ptr = &std_prod_idx;
4651                         rx_std_posted++;
4652                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4653                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4654                         dma_addr = dma_unmap_addr(ri, mapping);
4655                         skb = ri->skb;
4656                         post_ptr = &jmb_prod_idx;
4657                 } else
4658                         goto next_pkt_nopost;
4659
4660                 work_mask |= opaque_key;
4661
4662                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4663                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4664                 drop_it:
4665                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4666                                        desc_idx, *post_ptr);
4667                 drop_it_no_recycle:
4668                         /* Other statistics kept track of by card. */
4669                         tp->rx_dropped++;
4670                         goto next_pkt;
4671                 }
4672
4673                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4674                       ETH_FCS_LEN;
4675
4676                 if (len > TG3_RX_COPY_THRESH(tp)) {
4677                         int skb_size;
4678
4679                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4680                                                     *post_ptr);
4681                         if (skb_size < 0)
4682                                 goto drop_it;
4683
4684                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4685                                          PCI_DMA_FROMDEVICE);
4686
4687                         /* Ensure that the update to the skb happens
4688                          * after the usage of the old DMA mapping.
4689                          */
4690                         smp_wmb();
4691
4692                         ri->skb = NULL;
4693
4694                         skb_put(skb, len);
4695                 } else {
4696                         struct sk_buff *copy_skb;
4697
4698                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4699                                        desc_idx, *post_ptr);
4700
4701                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4702                                                     TG3_RAW_IP_ALIGN);
4703                         if (copy_skb == NULL)
4704                                 goto drop_it_no_recycle;
4705
4706                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4707                         skb_put(copy_skb, len);
4708                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4709                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4710                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4711
4712                         /* We'll reuse the original ring buffer. */
4713                         skb = copy_skb;
4714                 }
4715
4716                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4717                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4718                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4719                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4720                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4721                 else
4722                         skb->ip_summed = CHECKSUM_NONE;
4723
4724                 skb->protocol = eth_type_trans(skb, tp->dev);
4725
4726                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4727                     skb->protocol != htons(ETH_P_8021Q)) {
4728                         dev_kfree_skb(skb);
4729                         goto drop_it_no_recycle;
4730                 }
4731
4732                 if (desc->type_flags & RXD_FLAG_VLAN &&
4733                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4734                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4735 #if TG3_VLAN_TAG_USED
4736                         if (tp->vlgrp)
4737                                 hw_vlan = true;
4738                         else
4739 #endif
4740                         {
4741                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4742                                                     __skb_push(skb, VLAN_HLEN);
4743
4744                                 memmove(ve, skb->data + VLAN_HLEN,
4745                                         ETH_ALEN * 2);
4746                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4747                                 ve->h_vlan_TCI = htons(vtag);
4748                         }
4749                 }
4750
4751 #if TG3_VLAN_TAG_USED
4752                 if (hw_vlan)
4753                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4754                 else
4755 #endif
4756                         napi_gro_receive(&tnapi->napi, skb);
4757
4758                 received++;
4759                 budget--;
4760
4761 next_pkt:
4762                 (*post_ptr)++;
4763
4764                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4765                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4766                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4767                                      tpr->rx_std_prod_idx);
4768                         work_mask &= ~RXD_OPAQUE_RING_STD;
4769                         rx_std_posted = 0;
4770                 }
4771 next_pkt_nopost:
4772                 sw_idx++;
4773                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4774
4775                 /* Refresh hw_idx to see if there is new work */
4776                 if (sw_idx == hw_idx) {
4777                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4778                         rmb();
4779                 }
4780         }
4781
4782         /* ACK the status ring. */
4783         tnapi->rx_rcb_ptr = sw_idx;
4784         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4785
4786         /* Refill RX ring(s). */
4787         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4788                 if (work_mask & RXD_OPAQUE_RING_STD) {
4789                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4790                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4791                                      tpr->rx_std_prod_idx);
4792                 }
4793                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4794                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4795                                                TG3_RX_JUMBO_RING_SIZE;
4796                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4797                                      tpr->rx_jmb_prod_idx);
4798                 }
4799                 mmiowb();
4800         } else if (work_mask) {
4801                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4802                  * updated before the producer indices can be updated.
4803                  */
4804                 smp_wmb();
4805
4806                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4807                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4808
4809                 if (tnapi != &tp->napi[1])
4810                         napi_schedule(&tp->napi[1].napi);
4811         }
4812
4813         return received;
4814 }
4815
4816 static void tg3_poll_link(struct tg3 *tp)
4817 {
4818         /* handle link change and other phy events */
4819         if (!(tp->tg3_flags &
4820               (TG3_FLAG_USE_LINKCHG_REG |
4821                TG3_FLAG_POLL_SERDES))) {
4822                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4823
4824                 if (sblk->status & SD_STATUS_LINK_CHG) {
4825                         sblk->status = SD_STATUS_UPDATED |
4826                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4827                         spin_lock(&tp->lock);
4828                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4829                                 tw32_f(MAC_STATUS,
4830                                      (MAC_STATUS_SYNC_CHANGED |
4831                                       MAC_STATUS_CFG_CHANGED |
4832                                       MAC_STATUS_MI_COMPLETION |
4833                                       MAC_STATUS_LNKSTATE_CHANGED));
4834                                 udelay(40);
4835                         } else
4836                                 tg3_setup_phy(tp, 0);
4837                         spin_unlock(&tp->lock);
4838                 }
4839         }
4840 }
4841
4842 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4843                                 struct tg3_rx_prodring_set *dpr,
4844                                 struct tg3_rx_prodring_set *spr)
4845 {
4846         u32 si, di, cpycnt, src_prod_idx;
4847         int i, err = 0;
4848
4849         while (1) {
4850                 src_prod_idx = spr->rx_std_prod_idx;
4851
4852                 /* Make sure updates to the rx_std_buffers[] entries and the
4853                  * standard producer index are seen in the correct order.
4854                  */
4855                 smp_rmb();
4856
4857                 if (spr->rx_std_cons_idx == src_prod_idx)
4858                         break;
4859
4860                 if (spr->rx_std_cons_idx < src_prod_idx)
4861                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4862                 else
4863                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4864
4865                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4866
4867                 si = spr->rx_std_cons_idx;
4868                 di = dpr->rx_std_prod_idx;
4869
4870                 for (i = di; i < di + cpycnt; i++) {
4871                         if (dpr->rx_std_buffers[i].skb) {
4872                                 cpycnt = i - di;
4873                                 err = -ENOSPC;
4874                                 break;
4875                         }
4876                 }
4877
4878                 if (!cpycnt)
4879                         break;
4880
4881                 /* Ensure that updates to the rx_std_buffers ring and the
4882                  * shadowed hardware producer ring from tg3_recycle_skb() are
4883                  * ordered correctly WRT the skb check above.
4884                  */
4885                 smp_rmb();
4886
4887                 memcpy(&dpr->rx_std_buffers[di],
4888                        &spr->rx_std_buffers[si],
4889                        cpycnt * sizeof(struct ring_info));
4890
4891                 for (i = 0; i < cpycnt; i++, di++, si++) {
4892                         struct tg3_rx_buffer_desc *sbd, *dbd;
4893                         sbd = &spr->rx_std[si];
4894                         dbd = &dpr->rx_std[di];
4895                         dbd->addr_hi = sbd->addr_hi;
4896                         dbd->addr_lo = sbd->addr_lo;
4897                 }
4898
4899                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4900                                        TG3_RX_RING_SIZE;
4901                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4902                                        TG3_RX_RING_SIZE;
4903         }
4904
4905         while (1) {
4906                 src_prod_idx = spr->rx_jmb_prod_idx;
4907
4908                 /* Make sure updates to the rx_jmb_buffers[] entries and
4909                  * the jumbo producer index are seen in the correct order.
4910                  */
4911                 smp_rmb();
4912
4913                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4914                         break;
4915
4916                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4917                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4918                 else
4919                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4920
4921                 cpycnt = min(cpycnt,
4922                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4923
4924                 si = spr->rx_jmb_cons_idx;
4925                 di = dpr->rx_jmb_prod_idx;
4926
4927                 for (i = di; i < di + cpycnt; i++) {
4928                         if (dpr->rx_jmb_buffers[i].skb) {
4929                                 cpycnt = i - di;
4930                                 err = -ENOSPC;
4931                                 break;
4932                         }
4933                 }
4934
4935                 if (!cpycnt)
4936                         break;
4937
4938                 /* Ensure that updates to the rx_jmb_buffers ring and the
4939                  * shadowed hardware producer ring from tg3_recycle_skb() are
4940                  * ordered correctly WRT the skb check above.
4941                  */
4942                 smp_rmb();
4943
4944                 memcpy(&dpr->rx_jmb_buffers[di],
4945                        &spr->rx_jmb_buffers[si],
4946                        cpycnt * sizeof(struct ring_info));
4947
4948                 for (i = 0; i < cpycnt; i++, di++, si++) {
4949                         struct tg3_rx_buffer_desc *sbd, *dbd;
4950                         sbd = &spr->rx_jmb[si].std;
4951                         dbd = &dpr->rx_jmb[di].std;
4952                         dbd->addr_hi = sbd->addr_hi;
4953                         dbd->addr_lo = sbd->addr_lo;
4954                 }
4955
4956                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4957                                        TG3_RX_JUMBO_RING_SIZE;
4958                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4959                                        TG3_RX_JUMBO_RING_SIZE;
4960         }
4961
4962         return err;
4963 }
4964
4965 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4966 {
4967         struct tg3 *tp = tnapi->tp;
4968
4969         /* run TX completion thread */
4970         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4971                 tg3_tx(tnapi);
4972                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4973                         return work_done;
4974         }
4975
4976         /* run RX thread, within the bounds set by NAPI.
4977          * All RX "locking" is done by ensuring outside
4978          * code synchronizes with tg3->napi.poll()
4979          */
4980         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4981                 work_done += tg3_rx(tnapi, budget - work_done);
4982
4983         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4984                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4985                 int i, err = 0;
4986                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4987                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4988
4989                 for (i = 1; i < tp->irq_cnt; i++)
4990                         err |= tg3_rx_prodring_xfer(tp, dpr,
4991                                                     tp->napi[i].prodring);
4992
4993                 wmb();
4994
4995                 if (std_prod_idx != dpr->rx_std_prod_idx)
4996                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4997                                      dpr->rx_std_prod_idx);
4998
4999                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5000                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5001                                      dpr->rx_jmb_prod_idx);
5002
5003                 mmiowb();
5004
5005                 if (err)
5006                         tw32_f(HOSTCC_MODE, tp->coal_now);
5007         }
5008
5009         return work_done;
5010 }
5011
5012 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5013 {
5014         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5015         struct tg3 *tp = tnapi->tp;
5016         int work_done = 0;
5017         struct tg3_hw_status *sblk = tnapi->hw_status;
5018
5019         while (1) {
5020                 work_done = tg3_poll_work(tnapi, work_done, budget);
5021
5022                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5023                         goto tx_recovery;
5024
5025                 if (unlikely(work_done >= budget))
5026                         break;
5027
5028                 /* tp->last_tag is used in tg3_int_reenable() below
5029                  * to tell the hw how much work has been processed,
5030                  * so we must read it before checking for more work.
5031                  */
5032                 tnapi->last_tag = sblk->status_tag;
5033                 tnapi->last_irq_tag = tnapi->last_tag;
5034                 rmb();
5035
5036                 /* check for RX/TX work to do */
5037                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5038                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5039                         napi_complete(napi);
5040                         /* Reenable interrupts. */
5041                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5042                         mmiowb();
5043                         break;
5044                 }
5045         }
5046
5047         return work_done;
5048
5049 tx_recovery:
5050         /* work_done is guaranteed to be less than budget. */
5051         napi_complete(napi);
5052         schedule_work(&tp->reset_task);
5053         return work_done;
5054 }
5055
5056 static int tg3_poll(struct napi_struct *napi, int budget)
5057 {
5058         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5059         struct tg3 *tp = tnapi->tp;
5060         int work_done = 0;
5061         struct tg3_hw_status *sblk = tnapi->hw_status;
5062
5063         while (1) {
5064                 tg3_poll_link(tp);
5065
5066                 work_done = tg3_poll_work(tnapi, work_done, budget);
5067
5068                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5069                         goto tx_recovery;
5070
5071                 if (unlikely(work_done >= budget))
5072                         break;
5073
5074                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5075                         /* tp->last_tag is used in tg3_int_reenable() below
5076                          * to tell the hw how much work has been processed,
5077                          * so we must read it before checking for more work.
5078                          */
5079                         tnapi->last_tag = sblk->status_tag;
5080                         tnapi->last_irq_tag = tnapi->last_tag;
5081                         rmb();
5082                 } else
5083                         sblk->status &= ~SD_STATUS_UPDATED;
5084
5085                 if (likely(!tg3_has_work(tnapi))) {
5086                         napi_complete(napi);
5087                         tg3_int_reenable(tnapi);
5088                         break;
5089                 }
5090         }
5091
5092         return work_done;
5093
5094 tx_recovery:
5095         /* work_done is guaranteed to be less than budget. */
5096         napi_complete(napi);
5097         schedule_work(&tp->reset_task);
5098         return work_done;
5099 }
5100
5101 static void tg3_irq_quiesce(struct tg3 *tp)
5102 {
5103         int i;
5104
5105         BUG_ON(tp->irq_sync);
5106
5107         tp->irq_sync = 1;
5108         smp_mb();
5109
5110         for (i = 0; i < tp->irq_cnt; i++)
5111                 synchronize_irq(tp->napi[i].irq_vec);
5112 }
5113
5114 static inline int tg3_irq_sync(struct tg3 *tp)
5115 {
5116         return tp->irq_sync;
5117 }
5118
5119 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5120  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5121  * with as well.  Most of the time, this is not necessary except when
5122  * shutting down the device.
5123  */
5124 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5125 {
5126         spin_lock_bh(&tp->lock);
5127         if (irq_sync)
5128                 tg3_irq_quiesce(tp);
5129 }
5130
5131 static inline void tg3_full_unlock(struct tg3 *tp)
5132 {
5133         spin_unlock_bh(&tp->lock);
5134 }
5135
5136 /* One-shot MSI handler - Chip automatically disables interrupt
5137  * after sending MSI so driver doesn't have to do it.
5138  */
5139 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5140 {
5141         struct tg3_napi *tnapi = dev_id;
5142         struct tg3 *tp = tnapi->tp;
5143
5144         prefetch(tnapi->hw_status);
5145         if (tnapi->rx_rcb)
5146                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5147
5148         if (likely(!tg3_irq_sync(tp)))
5149                 napi_schedule(&tnapi->napi);
5150
5151         return IRQ_HANDLED;
5152 }
5153
5154 /* MSI ISR - No need to check for interrupt sharing and no need to
5155  * flush status block and interrupt mailbox. PCI ordering rules
5156  * guarantee that MSI will arrive after the status block.
5157  */
5158 static irqreturn_t tg3_msi(int irq, void *dev_id)
5159 {
5160         struct tg3_napi *tnapi = dev_id;
5161         struct tg3 *tp = tnapi->tp;
5162
5163         prefetch(tnapi->hw_status);
5164         if (tnapi->rx_rcb)
5165                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5166         /*
5167          * Writing any value to intr-mbox-0 clears PCI INTA# and
5168          * chip-internal interrupt pending events.
5169          * Writing non-zero to intr-mbox-0 additional tells the
5170          * NIC to stop sending us irqs, engaging "in-intr-handler"
5171          * event coalescing.
5172          */
5173         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5174         if (likely(!tg3_irq_sync(tp)))
5175                 napi_schedule(&tnapi->napi);
5176
5177         return IRQ_RETVAL(1);
5178 }
5179
5180 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5181 {
5182         struct tg3_napi *tnapi = dev_id;
5183         struct tg3 *tp = tnapi->tp;
5184         struct tg3_hw_status *sblk = tnapi->hw_status;
5185         unsigned int handled = 1;
5186
5187         /* In INTx mode, it is possible for the interrupt to arrive at
5188          * the CPU before the status block posted prior to the interrupt.
5189          * Reading the PCI State register will confirm whether the
5190          * interrupt is ours and will flush the status block.
5191          */
5192         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5193                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5194                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5195                         handled = 0;
5196                         goto out;
5197                 }
5198         }
5199
5200         /*
5201          * Writing any value to intr-mbox-0 clears PCI INTA# and
5202          * chip-internal interrupt pending events.
5203          * Writing non-zero to intr-mbox-0 additional tells the
5204          * NIC to stop sending us irqs, engaging "in-intr-handler"
5205          * event coalescing.
5206          *
5207          * Flush the mailbox to de-assert the IRQ immediately to prevent
5208          * spurious interrupts.  The flush impacts performance but
5209          * excessive spurious interrupts can be worse in some cases.
5210          */
5211         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5212         if (tg3_irq_sync(tp))
5213                 goto out;
5214         sblk->status &= ~SD_STATUS_UPDATED;
5215         if (likely(tg3_has_work(tnapi))) {
5216                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5217                 napi_schedule(&tnapi->napi);
5218         } else {
5219                 /* No work, shared interrupt perhaps?  re-enable
5220                  * interrupts, and flush that PCI write
5221                  */
5222                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5223                                0x00000000);
5224         }
5225 out:
5226         return IRQ_RETVAL(handled);
5227 }
5228
5229 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5230 {
5231         struct tg3_napi *tnapi = dev_id;
5232         struct tg3 *tp = tnapi->tp;
5233         struct tg3_hw_status *sblk = tnapi->hw_status;
5234         unsigned int handled = 1;
5235
5236         /* In INTx mode, it is possible for the interrupt to arrive at
5237          * the CPU before the status block posted prior to the interrupt.
5238          * Reading the PCI State register will confirm whether the
5239          * interrupt is ours and will flush the status block.
5240          */
5241         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5242                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5243                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5244                         handled = 0;
5245                         goto out;
5246                 }
5247         }
5248
5249         /*
5250          * writing any value to intr-mbox-0 clears PCI INTA# and
5251          * chip-internal interrupt pending events.
5252          * writing non-zero to intr-mbox-0 additional tells the
5253          * NIC to stop sending us irqs, engaging "in-intr-handler"
5254          * event coalescing.
5255          *
5256          * Flush the mailbox to de-assert the IRQ immediately to prevent
5257          * spurious interrupts.  The flush impacts performance but
5258          * excessive spurious interrupts can be worse in some cases.
5259          */
5260         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5261
5262         /*
5263          * In a shared interrupt configuration, sometimes other devices'
5264          * interrupts will scream.  We record the current status tag here
5265          * so that the above check can report that the screaming interrupts
5266          * are unhandled.  Eventually they will be silenced.
5267          */
5268         tnapi->last_irq_tag = sblk->status_tag;
5269
5270         if (tg3_irq_sync(tp))
5271                 goto out;
5272
5273         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5274
5275         napi_schedule(&tnapi->napi);
5276
5277 out:
5278         return IRQ_RETVAL(handled);
5279 }
5280
5281 /* ISR for interrupt test */
5282 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5283 {
5284         struct tg3_napi *tnapi = dev_id;
5285         struct tg3 *tp = tnapi->tp;
5286         struct tg3_hw_status *sblk = tnapi->hw_status;
5287
5288         if ((sblk->status & SD_STATUS_UPDATED) ||
5289             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5290                 tg3_disable_ints(tp);
5291                 return IRQ_RETVAL(1);
5292         }
5293         return IRQ_RETVAL(0);
5294 }
5295
5296 static int tg3_init_hw(struct tg3 *, int);
5297 static int tg3_halt(struct tg3 *, int, int);
5298
5299 /* Restart hardware after configuration changes, self-test, etc.
5300  * Invoked with tp->lock held.
5301  */
5302 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5303         __releases(tp->lock)
5304         __acquires(tp->lock)
5305 {
5306         int err;
5307
5308         err = tg3_init_hw(tp, reset_phy);
5309         if (err) {
5310                 netdev_err(tp->dev,
5311                            "Failed to re-initialize device, aborting\n");
5312                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5313                 tg3_full_unlock(tp);
5314                 del_timer_sync(&tp->timer);
5315                 tp->irq_sync = 0;
5316                 tg3_napi_enable(tp);
5317                 dev_close(tp->dev);
5318                 tg3_full_lock(tp, 0);
5319         }
5320         return err;
5321 }
5322
5323 #ifdef CONFIG_NET_POLL_CONTROLLER
5324 static void tg3_poll_controller(struct net_device *dev)
5325 {
5326         int i;
5327         struct tg3 *tp = netdev_priv(dev);
5328
5329         for (i = 0; i < tp->irq_cnt; i++)
5330                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5331 }
5332 #endif
5333
5334 static void tg3_reset_task(struct work_struct *work)
5335 {
5336         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5337         int err;
5338         unsigned int restart_timer;
5339
5340         tg3_full_lock(tp, 0);
5341
5342         if (!netif_running(tp->dev)) {
5343                 tg3_full_unlock(tp);
5344                 return;
5345         }
5346
5347         tg3_full_unlock(tp);
5348
5349         tg3_phy_stop(tp);
5350
5351         tg3_netif_stop(tp);
5352
5353         tg3_full_lock(tp, 1);
5354
5355         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5356         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5357
5358         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5359                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5360                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5361                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5362                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5363         }
5364
5365         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5366         err = tg3_init_hw(tp, 1);
5367         if (err)
5368                 goto out;
5369
5370         tg3_netif_start(tp);
5371
5372         if (restart_timer)
5373                 mod_timer(&tp->timer, jiffies + 1);
5374
5375 out:
5376         tg3_full_unlock(tp);
5377
5378         if (!err)
5379                 tg3_phy_start(tp);
5380 }
5381
5382 static void tg3_dump_short_state(struct tg3 *tp)
5383 {
5384         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5385                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5386         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5387                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5388 }
5389
5390 static void tg3_tx_timeout(struct net_device *dev)
5391 {
5392         struct tg3 *tp = netdev_priv(dev);
5393
5394         if (netif_msg_tx_err(tp)) {
5395                 netdev_err(dev, "transmit timed out, resetting\n");
5396                 tg3_dump_short_state(tp);
5397         }
5398
5399         schedule_work(&tp->reset_task);
5400 }
5401
5402 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5403 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5404 {
5405         u32 base = (u32) mapping & 0xffffffff;
5406
5407         return ((base > 0xffffdcc0) &&
5408                 (base + len + 8 < base));
5409 }
5410
5411 /* Test for DMA addresses > 40-bit */
5412 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5413                                           int len)
5414 {
5415 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5416         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5417                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5418         return 0;
5419 #else
5420         return 0;
5421 #endif
5422 }
5423
5424 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5425
5426 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5427 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5428                                        struct sk_buff *skb, u32 last_plus_one,
5429                                        u32 *start, u32 base_flags, u32 mss)
5430 {
5431         struct tg3 *tp = tnapi->tp;
5432         struct sk_buff *new_skb;
5433         dma_addr_t new_addr = 0;
5434         u32 entry = *start;
5435         int i, ret = 0;
5436
5437         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5438                 new_skb = skb_copy(skb, GFP_ATOMIC);
5439         else {
5440                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5441
5442                 new_skb = skb_copy_expand(skb,
5443                                           skb_headroom(skb) + more_headroom,
5444                                           skb_tailroom(skb), GFP_ATOMIC);
5445         }
5446
5447         if (!new_skb) {
5448                 ret = -1;
5449         } else {
5450                 /* New SKB is guaranteed to be linear. */
5451                 entry = *start;
5452                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5453                                           PCI_DMA_TODEVICE);
5454                 /* Make sure the mapping succeeded */
5455                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5456                         ret = -1;
5457                         dev_kfree_skb(new_skb);
5458                         new_skb = NULL;
5459
5460                 /* Make sure new skb does not cross any 4G boundaries.
5461                  * Drop the packet if it does.
5462                  */
5463                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5464                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5465                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5466                                          PCI_DMA_TODEVICE);
5467                         ret = -1;
5468                         dev_kfree_skb(new_skb);
5469                         new_skb = NULL;
5470                 } else {
5471                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5472                                     base_flags, 1 | (mss << 1));
5473                         *start = NEXT_TX(entry);
5474                 }
5475         }
5476
5477         /* Now clean up the sw ring entries. */
5478         i = 0;
5479         while (entry != last_plus_one) {
5480                 int len;
5481
5482                 if (i == 0)
5483                         len = skb_headlen(skb);
5484                 else
5485                         len = skb_shinfo(skb)->frags[i-1].size;
5486
5487                 pci_unmap_single(tp->pdev,
5488                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5489                                                 mapping),
5490                                  len, PCI_DMA_TODEVICE);
5491                 if (i == 0) {
5492                         tnapi->tx_buffers[entry].skb = new_skb;
5493                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5494                                            new_addr);
5495                 } else {
5496                         tnapi->tx_buffers[entry].skb = NULL;
5497                 }
5498                 entry = NEXT_TX(entry);
5499                 i++;
5500         }
5501
5502         dev_kfree_skb(skb);
5503
5504         return ret;
5505 }
5506
5507 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5508                         dma_addr_t mapping, int len, u32 flags,
5509                         u32 mss_and_is_end)
5510 {
5511         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5512         int is_end = (mss_and_is_end & 0x1);
5513         u32 mss = (mss_and_is_end >> 1);
5514         u32 vlan_tag = 0;
5515
5516         if (is_end)
5517                 flags |= TXD_FLAG_END;
5518         if (flags & TXD_FLAG_VLAN) {
5519                 vlan_tag = flags >> 16;
5520                 flags &= 0xffff;
5521         }
5522         vlan_tag |= (mss << TXD_MSS_SHIFT);
5523
5524         txd->addr_hi = ((u64) mapping >> 32);
5525         txd->addr_lo = ((u64) mapping & 0xffffffff);
5526         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5527         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5528 }
5529
5530 /* hard_start_xmit for devices that don't have any bugs and
5531  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5532  */
5533 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5534                                   struct net_device *dev)
5535 {
5536         struct tg3 *tp = netdev_priv(dev);
5537         u32 len, entry, base_flags, mss;
5538         dma_addr_t mapping;
5539         struct tg3_napi *tnapi;
5540         struct netdev_queue *txq;
5541         unsigned int i, last;
5542
5543         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5544         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5545         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5546                 tnapi++;
5547
5548         /* We are running in BH disabled context with netif_tx_lock
5549          * and TX reclaim runs via tp->napi.poll inside of a software
5550          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5551          * no IRQ context deadlocks to worry about either.  Rejoice!
5552          */
5553         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5554                 if (!netif_tx_queue_stopped(txq)) {
5555                         netif_tx_stop_queue(txq);
5556
5557                         /* This is a hard error, log it. */
5558                         netdev_err(dev,
5559                                    "BUG! Tx Ring full when queue awake!\n");
5560                 }
5561                 return NETDEV_TX_BUSY;
5562         }
5563
5564         entry = tnapi->tx_prod;
5565         base_flags = 0;
5566         mss = skb_shinfo(skb)->gso_size;
5567         if (mss) {
5568                 int tcp_opt_len, ip_tcp_len;
5569                 u32 hdrlen;
5570
5571                 if (skb_header_cloned(skb) &&
5572                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5573                         dev_kfree_skb(skb);
5574                         goto out_unlock;
5575                 }
5576
5577                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5578                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5579                 else {
5580                         struct iphdr *iph = ip_hdr(skb);
5581
5582                         tcp_opt_len = tcp_optlen(skb);
5583                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5584
5585                         iph->check = 0;
5586                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5587                         hdrlen = ip_tcp_len + tcp_opt_len;
5588                 }
5589
5590                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5591                         mss |= (hdrlen & 0xc) << 12;
5592                         if (hdrlen & 0x10)
5593                                 base_flags |= 0x00000010;
5594                         base_flags |= (hdrlen & 0x3e0) << 5;
5595                 } else
5596                         mss |= hdrlen << 9;
5597
5598                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5599                                TXD_FLAG_CPU_POST_DMA);
5600
5601                 tcp_hdr(skb)->check = 0;
5602
5603         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5604                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5605         }
5606
5607 #if TG3_VLAN_TAG_USED
5608         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5609                 base_flags |= (TXD_FLAG_VLAN |
5610                                (vlan_tx_tag_get(skb) << 16));
5611 #endif
5612
5613         len = skb_headlen(skb);
5614
5615         /* Queue skb data, a.k.a. the main skb fragment. */
5616         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5617         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5618                 dev_kfree_skb(skb);
5619                 goto out_unlock;
5620         }
5621
5622         tnapi->tx_buffers[entry].skb = skb;
5623         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5624
5625         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5626             !mss && skb->len > ETH_DATA_LEN)
5627                 base_flags |= TXD_FLAG_JMB_PKT;
5628
5629         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5630                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5631
5632         entry = NEXT_TX(entry);
5633
5634         /* Now loop through additional data fragments, and queue them. */
5635         if (skb_shinfo(skb)->nr_frags > 0) {
5636                 last = skb_shinfo(skb)->nr_frags - 1;
5637                 for (i = 0; i <= last; i++) {
5638                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5639
5640                         len = frag->size;
5641                         mapping = pci_map_page(tp->pdev,
5642                                                frag->page,
5643                                                frag->page_offset,
5644                                                len, PCI_DMA_TODEVICE);
5645                         if (pci_dma_mapping_error(tp->pdev, mapping))
5646                                 goto dma_error;
5647
5648                         tnapi->tx_buffers[entry].skb = NULL;
5649                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5650                                            mapping);
5651
5652                         tg3_set_txd(tnapi, entry, mapping, len,
5653                                     base_flags, (i == last) | (mss << 1));
5654
5655                         entry = NEXT_TX(entry);
5656                 }
5657         }
5658
5659         /* Packets are ready, update Tx producer idx local and on card. */
5660         tw32_tx_mbox(tnapi->prodmbox, entry);
5661
5662         tnapi->tx_prod = entry;
5663         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5664                 netif_tx_stop_queue(txq);
5665
5666                 /* netif_tx_stop_queue() must be done before checking
5667                  * checking tx index in tg3_tx_avail() below, because in
5668                  * tg3_tx(), we update tx index before checking for
5669                  * netif_tx_queue_stopped().
5670                  */
5671                 smp_mb();
5672                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5673                         netif_tx_wake_queue(txq);
5674         }
5675
5676 out_unlock:
5677         mmiowb();
5678
5679         return NETDEV_TX_OK;
5680
5681 dma_error:
5682         last = i;
5683         entry = tnapi->tx_prod;
5684         tnapi->tx_buffers[entry].skb = NULL;
5685         pci_unmap_single(tp->pdev,
5686                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5687                          skb_headlen(skb),
5688                          PCI_DMA_TODEVICE);
5689         for (i = 0; i <= last; i++) {
5690                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691                 entry = NEXT_TX(entry);
5692
5693                 pci_unmap_page(tp->pdev,
5694                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5695                                               mapping),
5696                                frag->size, PCI_DMA_TODEVICE);
5697         }
5698
5699         dev_kfree_skb(skb);
5700         return NETDEV_TX_OK;
5701 }
5702
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704                                           struct net_device *);
5705
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707  * TSO header is greater than 80 bytes.
5708  */
5709 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5710 {
5711         struct sk_buff *segs, *nskb;
5712         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5713
5714         /* Estimate the number of fragments in the worst case */
5715         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5716                 netif_stop_queue(tp->dev);
5717
5718                 /* netif_tx_stop_queue() must be done before checking
5719                  * checking tx index in tg3_tx_avail() below, because in
5720                  * tg3_tx(), we update tx index before checking for
5721                  * netif_tx_queue_stopped().
5722                  */
5723                 smp_mb();
5724                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5725                         return NETDEV_TX_BUSY;
5726
5727                 netif_wake_queue(tp->dev);
5728         }
5729
5730         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5731         if (IS_ERR(segs))
5732                 goto tg3_tso_bug_end;
5733
5734         do {
5735                 nskb = segs;
5736                 segs = segs->next;
5737                 nskb->next = NULL;
5738                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5739         } while (segs);
5740
5741 tg3_tso_bug_end:
5742         dev_kfree_skb(skb);
5743
5744         return NETDEV_TX_OK;
5745 }
5746
5747 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5748  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5749  */
5750 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5751                                           struct net_device *dev)
5752 {
5753         struct tg3 *tp = netdev_priv(dev);
5754         u32 len, entry, base_flags, mss;
5755         int would_hit_hwbug;
5756         dma_addr_t mapping;
5757         struct tg3_napi *tnapi;
5758         struct netdev_queue *txq;
5759         unsigned int i, last;
5760
5761         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5762         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5763         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5764                 tnapi++;
5765
5766         /* We are running in BH disabled context with netif_tx_lock
5767          * and TX reclaim runs via tp->napi.poll inside of a software
5768          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5769          * no IRQ context deadlocks to worry about either.  Rejoice!
5770          */
5771         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5772                 if (!netif_tx_queue_stopped(txq)) {
5773                         netif_tx_stop_queue(txq);
5774
5775                         /* This is a hard error, log it. */
5776                         netdev_err(dev,
5777                                    "BUG! Tx Ring full when queue awake!\n");
5778                 }
5779                 return NETDEV_TX_BUSY;
5780         }
5781
5782         entry = tnapi->tx_prod;
5783         base_flags = 0;
5784         if (skb->ip_summed == CHECKSUM_PARTIAL)
5785                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5786
5787         mss = skb_shinfo(skb)->gso_size;
5788         if (mss) {
5789                 struct iphdr *iph;
5790                 u32 tcp_opt_len, hdr_len;
5791
5792                 if (skb_header_cloned(skb) &&
5793                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5794                         dev_kfree_skb(skb);
5795                         goto out_unlock;
5796                 }
5797
5798                 iph = ip_hdr(skb);
5799                 tcp_opt_len = tcp_optlen(skb);
5800
5801                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5802                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5803                 } else {
5804                         u32 ip_tcp_len;
5805
5806                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5807                         hdr_len = ip_tcp_len + tcp_opt_len;
5808
5809                         iph->check = 0;
5810                         iph->tot_len = htons(mss + hdr_len);
5811                 }
5812
5813                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5814                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5815                         return tg3_tso_bug(tp, skb);
5816
5817                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5818                                TXD_FLAG_CPU_POST_DMA);
5819
5820                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5821                         tcp_hdr(skb)->check = 0;
5822                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5823                 } else
5824                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5825                                                                  iph->daddr, 0,
5826                                                                  IPPROTO_TCP,
5827                                                                  0);
5828
5829                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5830                         mss |= (hdr_len & 0xc) << 12;
5831                         if (hdr_len & 0x10)
5832                                 base_flags |= 0x00000010;
5833                         base_flags |= (hdr_len & 0x3e0) << 5;
5834                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5835                         mss |= hdr_len << 9;
5836                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5837                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5838                         if (tcp_opt_len || iph->ihl > 5) {
5839                                 int tsflags;
5840
5841                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5842                                 mss |= (tsflags << 11);
5843                         }
5844                 } else {
5845                         if (tcp_opt_len || iph->ihl > 5) {
5846                                 int tsflags;
5847
5848                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5849                                 base_flags |= tsflags << 12;
5850                         }
5851                 }
5852         }
5853 #if TG3_VLAN_TAG_USED
5854         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5855                 base_flags |= (TXD_FLAG_VLAN |
5856                                (vlan_tx_tag_get(skb) << 16));
5857 #endif
5858
5859         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5860             !mss && skb->len > ETH_DATA_LEN)
5861                 base_flags |= TXD_FLAG_JMB_PKT;
5862
5863         len = skb_headlen(skb);
5864
5865         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5866         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5867                 dev_kfree_skb(skb);
5868                 goto out_unlock;
5869         }
5870
5871         tnapi->tx_buffers[entry].skb = skb;
5872         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5873
5874         would_hit_hwbug = 0;
5875
5876         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5877                 would_hit_hwbug = 1;
5878
5879         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5880             tg3_4g_overflow_test(mapping, len))
5881                 would_hit_hwbug = 1;
5882
5883         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5884             tg3_40bit_overflow_test(tp, mapping, len))
5885                 would_hit_hwbug = 1;
5886
5887         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5888                 would_hit_hwbug = 1;
5889
5890         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5891                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5892
5893         entry = NEXT_TX(entry);
5894
5895         /* Now loop through additional data fragments, and queue them. */
5896         if (skb_shinfo(skb)->nr_frags > 0) {
5897                 last = skb_shinfo(skb)->nr_frags - 1;
5898                 for (i = 0; i <= last; i++) {
5899                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5900
5901                         len = frag->size;
5902                         mapping = pci_map_page(tp->pdev,
5903                                                frag->page,
5904                                                frag->page_offset,
5905                                                len, PCI_DMA_TODEVICE);
5906
5907                         tnapi->tx_buffers[entry].skb = NULL;
5908                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5909                                            mapping);
5910                         if (pci_dma_mapping_error(tp->pdev, mapping))
5911                                 goto dma_error;
5912
5913                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5914                             len <= 8)
5915                                 would_hit_hwbug = 1;
5916
5917                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5918                             tg3_4g_overflow_test(mapping, len))
5919                                 would_hit_hwbug = 1;
5920
5921                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5922                             tg3_40bit_overflow_test(tp, mapping, len))
5923                                 would_hit_hwbug = 1;
5924
5925                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5926                                 tg3_set_txd(tnapi, entry, mapping, len,
5927                                             base_flags, (i == last)|(mss << 1));
5928                         else
5929                                 tg3_set_txd(tnapi, entry, mapping, len,
5930                                             base_flags, (i == last));
5931
5932                         entry = NEXT_TX(entry);
5933                 }
5934         }
5935
5936         if (would_hit_hwbug) {
5937                 u32 last_plus_one = entry;
5938                 u32 start;
5939
5940                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5941                 start &= (TG3_TX_RING_SIZE - 1);
5942
5943                 /* If the workaround fails due to memory/mapping
5944                  * failure, silently drop this packet.
5945                  */
5946                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5947                                                 &start, base_flags, mss))
5948                         goto out_unlock;
5949
5950                 entry = start;
5951         }
5952
5953         /* Packets are ready, update Tx producer idx local and on card. */
5954         tw32_tx_mbox(tnapi->prodmbox, entry);
5955
5956         tnapi->tx_prod = entry;
5957         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5958                 netif_tx_stop_queue(txq);
5959
5960                 /* netif_tx_stop_queue() must be done before checking
5961                  * checking tx index in tg3_tx_avail() below, because in
5962                  * tg3_tx(), we update tx index before checking for
5963                  * netif_tx_queue_stopped().
5964                  */
5965                 smp_mb();
5966                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5967                         netif_tx_wake_queue(txq);
5968         }
5969
5970 out_unlock:
5971         mmiowb();
5972
5973         return NETDEV_TX_OK;
5974
5975 dma_error:
5976         last = i;
5977         entry = tnapi->tx_prod;
5978         tnapi->tx_buffers[entry].skb = NULL;
5979         pci_unmap_single(tp->pdev,
5980                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5981                          skb_headlen(skb),
5982                          PCI_DMA_TODEVICE);
5983         for (i = 0; i <= last; i++) {
5984                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5985                 entry = NEXT_TX(entry);
5986
5987                 pci_unmap_page(tp->pdev,
5988                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5989                                               mapping),
5990                                frag->size, PCI_DMA_TODEVICE);
5991         }
5992
5993         dev_kfree_skb(skb);
5994         return NETDEV_TX_OK;
5995 }
5996
5997 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5998                                int new_mtu)
5999 {
6000         dev->mtu = new_mtu;
6001
6002         if (new_mtu > ETH_DATA_LEN) {
6003                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6004                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6005                         ethtool_op_set_tso(dev, 0);
6006                 } else {
6007                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6008                 }
6009         } else {
6010                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6011                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6012                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6013         }
6014 }
6015
6016 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6017 {
6018         struct tg3 *tp = netdev_priv(dev);
6019         int err;
6020
6021         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6022                 return -EINVAL;
6023
6024         if (!netif_running(dev)) {
6025                 /* We'll just catch it later when the
6026                  * device is up'd.
6027                  */
6028                 tg3_set_mtu(dev, tp, new_mtu);
6029                 return 0;
6030         }
6031
6032         tg3_phy_stop(tp);
6033
6034         tg3_netif_stop(tp);
6035
6036         tg3_full_lock(tp, 1);
6037
6038         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6039
6040         tg3_set_mtu(dev, tp, new_mtu);
6041
6042         err = tg3_restart_hw(tp, 0);
6043
6044         if (!err)
6045                 tg3_netif_start(tp);
6046
6047         tg3_full_unlock(tp);
6048
6049         if (!err)
6050                 tg3_phy_start(tp);
6051
6052         return err;
6053 }
6054
6055 static void tg3_rx_prodring_free(struct tg3 *tp,
6056                                  struct tg3_rx_prodring_set *tpr)
6057 {
6058         int i;
6059
6060         if (tpr != &tp->prodring[0]) {
6061                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6062                      i = (i + 1) % TG3_RX_RING_SIZE)
6063                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6064                                         tp->rx_pkt_map_sz);
6065
6066                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6067                         for (i = tpr->rx_jmb_cons_idx;
6068                              i != tpr->rx_jmb_prod_idx;
6069                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6070                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6071                                                 TG3_RX_JMB_MAP_SZ);
6072                         }
6073                 }
6074
6075                 return;
6076         }
6077
6078         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6079                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6080                                 tp->rx_pkt_map_sz);
6081
6082         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6083                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6084                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6085                                         TG3_RX_JMB_MAP_SZ);
6086         }
6087 }
6088
6089 /* Initialize rx rings for packet processing.
6090  *
6091  * The chip has been shut down and the driver detached from
6092  * the networking, so no interrupts or new tx packets will
6093  * end up in the driver.  tp->{tx,}lock are held and thus
6094  * we may not sleep.
6095  */
6096 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6097                                  struct tg3_rx_prodring_set *tpr)
6098 {
6099         u32 i, rx_pkt_dma_sz;
6100
6101         tpr->rx_std_cons_idx = 0;
6102         tpr->rx_std_prod_idx = 0;
6103         tpr->rx_jmb_cons_idx = 0;
6104         tpr->rx_jmb_prod_idx = 0;
6105
6106         if (tpr != &tp->prodring[0]) {
6107                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6108                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6109                         memset(&tpr->rx_jmb_buffers[0], 0,
6110                                TG3_RX_JMB_BUFF_RING_SIZE);
6111                 goto done;
6112         }
6113
6114         /* Zero out all descriptors. */
6115         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6116
6117         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6118         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6119             tp->dev->mtu > ETH_DATA_LEN)
6120                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6121         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6122
6123         /* Initialize invariants of the rings, we only set this
6124          * stuff once.  This works because the card does not
6125          * write into the rx buffer posting rings.
6126          */
6127         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6128                 struct tg3_rx_buffer_desc *rxd;
6129
6130                 rxd = &tpr->rx_std[i];
6131                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6132                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6133                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6134                                (i << RXD_OPAQUE_INDEX_SHIFT));
6135         }
6136
6137         /* Now allocate fresh SKBs for each rx ring. */
6138         for (i = 0; i < tp->rx_pending; i++) {
6139                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6140                         netdev_warn(tp->dev,
6141                                     "Using a smaller RX standard ring. Only "
6142                                     "%d out of %d buffers were allocated "
6143                                     "successfully\n", i, tp->rx_pending);
6144                         if (i == 0)
6145                                 goto initfail;
6146                         tp->rx_pending = i;
6147                         break;
6148                 }
6149         }
6150
6151         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6152                 goto done;
6153
6154         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6155
6156         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6157                 goto done;
6158
6159         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6160                 struct tg3_rx_buffer_desc *rxd;
6161
6162                 rxd = &tpr->rx_jmb[i].std;
6163                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6164                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6165                                   RXD_FLAG_JUMBO;
6166                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6167                        (i << RXD_OPAQUE_INDEX_SHIFT));
6168         }
6169
6170         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6171                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6172                         netdev_warn(tp->dev,
6173                                     "Using a smaller RX jumbo ring. Only %d "
6174                                     "out of %d buffers were allocated "
6175                                     "successfully\n", i, tp->rx_jumbo_pending);
6176                         if (i == 0)
6177                                 goto initfail;
6178                         tp->rx_jumbo_pending = i;
6179                         break;
6180                 }
6181         }
6182
6183 done:
6184         return 0;
6185
6186 initfail:
6187         tg3_rx_prodring_free(tp, tpr);
6188         return -ENOMEM;
6189 }
6190
6191 static void tg3_rx_prodring_fini(struct tg3 *tp,
6192                                  struct tg3_rx_prodring_set *tpr)
6193 {
6194         kfree(tpr->rx_std_buffers);
6195         tpr->rx_std_buffers = NULL;
6196         kfree(tpr->rx_jmb_buffers);
6197         tpr->rx_jmb_buffers = NULL;
6198         if (tpr->rx_std) {
6199                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6200                                     tpr->rx_std, tpr->rx_std_mapping);
6201                 tpr->rx_std = NULL;
6202         }
6203         if (tpr->rx_jmb) {
6204                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6205                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6206                 tpr->rx_jmb = NULL;
6207         }
6208 }
6209
6210 static int tg3_rx_prodring_init(struct tg3 *tp,
6211                                 struct tg3_rx_prodring_set *tpr)
6212 {
6213         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6214         if (!tpr->rx_std_buffers)
6215                 return -ENOMEM;
6216
6217         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6218                                            &tpr->rx_std_mapping);
6219         if (!tpr->rx_std)
6220                 goto err_out;
6221
6222         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6223                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6224                                               GFP_KERNEL);
6225                 if (!tpr->rx_jmb_buffers)
6226                         goto err_out;
6227
6228                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6229                                                    TG3_RX_JUMBO_RING_BYTES,
6230                                                    &tpr->rx_jmb_mapping);
6231                 if (!tpr->rx_jmb)
6232                         goto err_out;
6233         }
6234
6235         return 0;
6236
6237 err_out:
6238         tg3_rx_prodring_fini(tp, tpr);
6239         return -ENOMEM;
6240 }
6241
6242 /* Free up pending packets in all rx/tx rings.
6243  *
6244  * The chip has been shut down and the driver detached from
6245  * the networking, so no interrupts or new tx packets will
6246  * end up in the driver.  tp->{tx,}lock is not held and we are not
6247  * in an interrupt context and thus may sleep.
6248  */
6249 static void tg3_free_rings(struct tg3 *tp)
6250 {
6251         int i, j;
6252
6253         for (j = 0; j < tp->irq_cnt; j++) {
6254                 struct tg3_napi *tnapi = &tp->napi[j];
6255
6256                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6257
6258                 if (!tnapi->tx_buffers)
6259                         continue;
6260
6261                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6262                         struct ring_info *txp;
6263                         struct sk_buff *skb;
6264                         unsigned int k;
6265
6266                         txp = &tnapi->tx_buffers[i];
6267                         skb = txp->skb;
6268
6269                         if (skb == NULL) {
6270                                 i++;
6271                                 continue;
6272                         }
6273
6274                         pci_unmap_single(tp->pdev,
6275                                          dma_unmap_addr(txp, mapping),
6276                                          skb_headlen(skb),
6277                                          PCI_DMA_TODEVICE);
6278                         txp->skb = NULL;
6279
6280                         i++;
6281
6282                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6283                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6284                                 pci_unmap_page(tp->pdev,
6285                                                dma_unmap_addr(txp, mapping),
6286                                                skb_shinfo(skb)->frags[k].size,
6287                                                PCI_DMA_TODEVICE);
6288                                 i++;
6289                         }
6290
6291                         dev_kfree_skb_any(skb);
6292                 }
6293         }
6294 }
6295
6296 /* Initialize tx/rx rings for packet processing.
6297  *
6298  * The chip has been shut down and the driver detached from
6299  * the networking, so no interrupts or new tx packets will
6300  * end up in the driver.  tp->{tx,}lock are held and thus
6301  * we may not sleep.
6302  */
6303 static int tg3_init_rings(struct tg3 *tp)
6304 {
6305         int i;
6306
6307         /* Free up all the SKBs. */
6308         tg3_free_rings(tp);
6309
6310         for (i = 0; i < tp->irq_cnt; i++) {
6311                 struct tg3_napi *tnapi = &tp->napi[i];
6312
6313                 tnapi->last_tag = 0;
6314                 tnapi->last_irq_tag = 0;
6315                 tnapi->hw_status->status = 0;
6316                 tnapi->hw_status->status_tag = 0;
6317                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6318
6319                 tnapi->tx_prod = 0;
6320                 tnapi->tx_cons = 0;
6321                 if (tnapi->tx_ring)
6322                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6323
6324                 tnapi->rx_rcb_ptr = 0;
6325                 if (tnapi->rx_rcb)
6326                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6327
6328                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6329                         tg3_free_rings(tp);
6330                         return -ENOMEM;
6331                 }
6332         }
6333
6334         return 0;
6335 }
6336
6337 /*
6338  * Must not be invoked with interrupt sources disabled and
6339  * the hardware shutdown down.
6340  */
6341 static void tg3_free_consistent(struct tg3 *tp)
6342 {
6343         int i;
6344
6345         for (i = 0; i < tp->irq_cnt; i++) {
6346                 struct tg3_napi *tnapi = &tp->napi[i];
6347
6348                 if (tnapi->tx_ring) {
6349                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6350                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6351                         tnapi->tx_ring = NULL;
6352                 }
6353
6354                 kfree(tnapi->tx_buffers);
6355                 tnapi->tx_buffers = NULL;
6356
6357                 if (tnapi->rx_rcb) {
6358                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6359                                             tnapi->rx_rcb,
6360                                             tnapi->rx_rcb_mapping);
6361                         tnapi->rx_rcb = NULL;
6362                 }
6363
6364                 if (tnapi->hw_status) {
6365                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6366                                             tnapi->hw_status,
6367                                             tnapi->status_mapping);
6368                         tnapi->hw_status = NULL;
6369                 }
6370         }
6371
6372         if (tp->hw_stats) {
6373                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6374                                     tp->hw_stats, tp->stats_mapping);
6375                 tp->hw_stats = NULL;
6376         }
6377
6378         for (i = 0; i < tp->irq_cnt; i++)
6379                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6380 }
6381
6382 /*
6383  * Must not be invoked with interrupt sources disabled and
6384  * the hardware shutdown down.  Can sleep.
6385  */
6386 static int tg3_alloc_consistent(struct tg3 *tp)
6387 {
6388         int i;
6389
6390         for (i = 0; i < tp->irq_cnt; i++) {
6391                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6392                         goto err_out;
6393         }
6394
6395         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6396                                             sizeof(struct tg3_hw_stats),
6397                                             &tp->stats_mapping);
6398         if (!tp->hw_stats)
6399                 goto err_out;
6400
6401         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6402
6403         for (i = 0; i < tp->irq_cnt; i++) {
6404                 struct tg3_napi *tnapi = &tp->napi[i];
6405                 struct tg3_hw_status *sblk;
6406
6407                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6408                                                         TG3_HW_STATUS_SIZE,
6409                                                         &tnapi->status_mapping);
6410                 if (!tnapi->hw_status)
6411                         goto err_out;
6412
6413                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6414                 sblk = tnapi->hw_status;
6415
6416                 /* If multivector TSS is enabled, vector 0 does not handle
6417                  * tx interrupts.  Don't allocate any resources for it.
6418                  */
6419                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6420                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6421                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6422                                                     TG3_TX_RING_SIZE,
6423                                                     GFP_KERNEL);
6424                         if (!tnapi->tx_buffers)
6425                                 goto err_out;
6426
6427                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6428                                                               TG3_TX_RING_BYTES,
6429                                                        &tnapi->tx_desc_mapping);
6430                         if (!tnapi->tx_ring)
6431                                 goto err_out;
6432                 }
6433
6434                 /*
6435                  * When RSS is enabled, the status block format changes
6436                  * slightly.  The "rx_jumbo_consumer", "reserved",
6437                  * and "rx_mini_consumer" members get mapped to the
6438                  * other three rx return ring producer indexes.
6439                  */
6440                 switch (i) {
6441                 default:
6442                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6443                         break;
6444                 case 2:
6445                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6446                         break;
6447                 case 3:
6448                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6449                         break;
6450                 case 4:
6451                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6452                         break;
6453                 }
6454
6455                 tnapi->prodring = &tp->prodring[i];
6456
6457                 /*
6458                  * If multivector RSS is enabled, vector 0 does not handle
6459                  * rx or tx interrupts.  Don't allocate any resources for it.
6460                  */
6461                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6462                         continue;
6463
6464                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6465                                                      TG3_RX_RCB_RING_BYTES(tp),
6466                                                      &tnapi->rx_rcb_mapping);
6467                 if (!tnapi->rx_rcb)
6468                         goto err_out;
6469
6470                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6471         }
6472
6473         return 0;
6474
6475 err_out:
6476         tg3_free_consistent(tp);
6477         return -ENOMEM;
6478 }
6479
6480 #define MAX_WAIT_CNT 1000
6481
6482 /* To stop a block, clear the enable bit and poll till it
6483  * clears.  tp->lock is held.
6484  */
6485 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6486 {
6487         unsigned int i;
6488         u32 val;
6489
6490         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6491                 switch (ofs) {
6492                 case RCVLSC_MODE:
6493                 case DMAC_MODE:
6494                 case MBFREE_MODE:
6495                 case BUFMGR_MODE:
6496                 case MEMARB_MODE:
6497                         /* We can't enable/disable these bits of the
6498                          * 5705/5750, just say success.
6499                          */
6500                         return 0;
6501
6502                 default:
6503                         break;
6504                 }
6505         }
6506
6507         val = tr32(ofs);
6508         val &= ~enable_bit;
6509         tw32_f(ofs, val);
6510
6511         for (i = 0; i < MAX_WAIT_CNT; i++) {
6512                 udelay(100);
6513                 val = tr32(ofs);
6514                 if ((val & enable_bit) == 0)
6515                         break;
6516         }
6517
6518         if (i == MAX_WAIT_CNT && !silent) {
6519                 dev_err(&tp->pdev->dev,
6520                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6521                         ofs, enable_bit);
6522                 return -ENODEV;
6523         }
6524
6525         return 0;
6526 }
6527
6528 /* tp->lock is held. */
6529 static int tg3_abort_hw(struct tg3 *tp, int silent)
6530 {
6531         int i, err;
6532
6533         tg3_disable_ints(tp);
6534
6535         tp->rx_mode &= ~RX_MODE_ENABLE;
6536         tw32_f(MAC_RX_MODE, tp->rx_mode);
6537         udelay(10);
6538
6539         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6540         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6541         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6542         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6543         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6544         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6545
6546         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6547         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6548         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6549         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6550         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6551         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6552         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6553
6554         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6555         tw32_f(MAC_MODE, tp->mac_mode);
6556         udelay(40);
6557
6558         tp->tx_mode &= ~TX_MODE_ENABLE;
6559         tw32_f(MAC_TX_MODE, tp->tx_mode);
6560
6561         for (i = 0; i < MAX_WAIT_CNT; i++) {
6562                 udelay(100);
6563                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6564                         break;
6565         }
6566         if (i >= MAX_WAIT_CNT) {
6567                 dev_err(&tp->pdev->dev,
6568                         "%s timed out, TX_MODE_ENABLE will not clear "
6569                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6570                 err |= -ENODEV;
6571         }
6572
6573         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6574         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6575         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6576
6577         tw32(FTQ_RESET, 0xffffffff);
6578         tw32(FTQ_RESET, 0x00000000);
6579
6580         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6581         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6582
6583         for (i = 0; i < tp->irq_cnt; i++) {
6584                 struct tg3_napi *tnapi = &tp->napi[i];
6585                 if (tnapi->hw_status)
6586                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6587         }
6588         if (tp->hw_stats)
6589                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6590
6591         return err;
6592 }
6593
6594 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6595 {
6596         int i;
6597         u32 apedata;
6598
6599         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6600         if (apedata != APE_SEG_SIG_MAGIC)
6601                 return;
6602
6603         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6604         if (!(apedata & APE_FW_STATUS_READY))
6605                 return;
6606
6607         /* Wait for up to 1 millisecond for APE to service previous event. */
6608         for (i = 0; i < 10; i++) {
6609                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6610                         return;
6611
6612                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6613
6614                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6615                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6616                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6617
6618                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6619
6620                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6621                         break;
6622
6623                 udelay(100);
6624         }
6625
6626         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6627                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6628 }
6629
6630 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6631 {
6632         u32 event;
6633         u32 apedata;
6634
6635         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6636                 return;
6637
6638         switch (kind) {
6639         case RESET_KIND_INIT:
6640                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6641                                 APE_HOST_SEG_SIG_MAGIC);
6642                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6643                                 APE_HOST_SEG_LEN_MAGIC);
6644                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6645                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6646                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6647                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6648                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6649                                 APE_HOST_BEHAV_NO_PHYLOCK);
6650
6651                 event = APE_EVENT_STATUS_STATE_START;
6652                 break;
6653         case RESET_KIND_SHUTDOWN:
6654                 /* With the interface we are currently using,
6655                  * APE does not track driver state.  Wiping
6656                  * out the HOST SEGMENT SIGNATURE forces
6657                  * the APE to assume OS absent status.
6658                  */
6659                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6660
6661                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6662                 break;
6663         case RESET_KIND_SUSPEND:
6664                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6665                 break;
6666         default:
6667                 return;
6668         }
6669
6670         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6671
6672         tg3_ape_send_event(tp, event);
6673 }
6674
6675 /* tp->lock is held. */
6676 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6677 {
6678         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6679                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6680
6681         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6682                 switch (kind) {
6683                 case RESET_KIND_INIT:
6684                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6685                                       DRV_STATE_START);
6686                         break;
6687
6688                 case RESET_KIND_SHUTDOWN:
6689                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6690                                       DRV_STATE_UNLOAD);
6691                         break;
6692
6693                 case RESET_KIND_SUSPEND:
6694                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6695                                       DRV_STATE_SUSPEND);
6696                         break;
6697
6698                 default:
6699                         break;
6700                 }
6701         }
6702
6703         if (kind == RESET_KIND_INIT ||
6704             kind == RESET_KIND_SUSPEND)
6705                 tg3_ape_driver_state_change(tp, kind);
6706 }
6707
6708 /* tp->lock is held. */
6709 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6710 {
6711         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6712                 switch (kind) {
6713                 case RESET_KIND_INIT:
6714                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6715                                       DRV_STATE_START_DONE);
6716                         break;
6717
6718                 case RESET_KIND_SHUTDOWN:
6719                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6720                                       DRV_STATE_UNLOAD_DONE);
6721                         break;
6722
6723                 default:
6724                         break;
6725                 }
6726         }
6727
6728         if (kind == RESET_KIND_SHUTDOWN)
6729                 tg3_ape_driver_state_change(tp, kind);
6730 }
6731
6732 /* tp->lock is held. */
6733 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6734 {
6735         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6736                 switch (kind) {
6737                 case RESET_KIND_INIT:
6738                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6739                                       DRV_STATE_START);
6740                         break;
6741
6742                 case RESET_KIND_SHUTDOWN:
6743                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6744                                       DRV_STATE_UNLOAD);
6745                         break;
6746
6747                 case RESET_KIND_SUSPEND:
6748                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6749                                       DRV_STATE_SUSPEND);
6750                         break;
6751
6752                 default:
6753                         break;
6754                 }
6755         }
6756 }
6757
6758 static int tg3_poll_fw(struct tg3 *tp)
6759 {
6760         int i;
6761         u32 val;
6762
6763         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6764                 /* Wait up to 20ms for init done. */
6765                 for (i = 0; i < 200; i++) {
6766                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6767                                 return 0;
6768                         udelay(100);
6769                 }
6770                 return -ENODEV;
6771         }
6772
6773         /* Wait for firmware initialization to complete. */
6774         for (i = 0; i < 100000; i++) {
6775                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6776                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6777                         break;
6778                 udelay(10);
6779         }
6780
6781         /* Chip might not be fitted with firmware.  Some Sun onboard
6782          * parts are configured like that.  So don't signal the timeout
6783          * of the above loop as an error, but do report the lack of
6784          * running firmware once.
6785          */
6786         if (i >= 100000 &&
6787             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6788                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6789
6790                 netdev_info(tp->dev, "No firmware running\n");
6791         }
6792
6793         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6794                 /* The 57765 A0 needs a little more
6795                  * time to do some important work.
6796                  */
6797                 mdelay(10);
6798         }
6799
6800         return 0;
6801 }
6802
6803 /* Save PCI command register before chip reset */
6804 static void tg3_save_pci_state(struct tg3 *tp)
6805 {
6806         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6807 }
6808
6809 /* Restore PCI state after chip reset */
6810 static void tg3_restore_pci_state(struct tg3 *tp)
6811 {
6812         u32 val;
6813
6814         /* Re-enable indirect register accesses. */
6815         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6816                                tp->misc_host_ctrl);
6817
6818         /* Set MAX PCI retry to zero. */
6819         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6820         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6821             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6822                 val |= PCISTATE_RETRY_SAME_DMA;
6823         /* Allow reads and writes to the APE register and memory space. */
6824         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6825                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6826                        PCISTATE_ALLOW_APE_SHMEM_WR |
6827                        PCISTATE_ALLOW_APE_PSPACE_WR;
6828         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6829
6830         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6831
6832         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6833                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6834                         pcie_set_readrq(tp->pdev, 4096);
6835                 else {
6836                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6837                                               tp->pci_cacheline_sz);
6838                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6839                                               tp->pci_lat_timer);
6840                 }
6841         }
6842
6843         /* Make sure PCI-X relaxed ordering bit is clear. */
6844         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6845                 u16 pcix_cmd;
6846
6847                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6848                                      &pcix_cmd);
6849                 pcix_cmd &= ~PCI_X_CMD_ERO;
6850                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6851                                       pcix_cmd);
6852         }
6853
6854         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6855
6856                 /* Chip reset on 5780 will reset MSI enable bit,
6857                  * so need to restore it.
6858                  */
6859                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6860                         u16 ctrl;
6861
6862                         pci_read_config_word(tp->pdev,
6863                                              tp->msi_cap + PCI_MSI_FLAGS,
6864                                              &ctrl);
6865                         pci_write_config_word(tp->pdev,
6866                                               tp->msi_cap + PCI_MSI_FLAGS,
6867                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6868                         val = tr32(MSGINT_MODE);
6869                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6870                 }
6871         }
6872 }
6873
6874 static void tg3_stop_fw(struct tg3 *);
6875
6876 /* tp->lock is held. */
6877 static int tg3_chip_reset(struct tg3 *tp)
6878 {
6879         u32 val;
6880         void (*write_op)(struct tg3 *, u32, u32);
6881         int i, err;
6882
6883         tg3_nvram_lock(tp);
6884
6885         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6886
6887         /* No matching tg3_nvram_unlock() after this because
6888          * chip reset below will undo the nvram lock.
6889          */
6890         tp->nvram_lock_cnt = 0;
6891
6892         /* GRC_MISC_CFG core clock reset will clear the memory
6893          * enable bit in PCI register 4 and the MSI enable bit
6894          * on some chips, so we save relevant registers here.
6895          */
6896         tg3_save_pci_state(tp);
6897
6898         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6899             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6900                 tw32(GRC_FASTBOOT_PC, 0);
6901
6902         /*
6903          * We must avoid the readl() that normally takes place.
6904          * It locks machines, causes machine checks, and other
6905          * fun things.  So, temporarily disable the 5701
6906          * hardware workaround, while we do the reset.
6907          */
6908         write_op = tp->write32;
6909         if (write_op == tg3_write_flush_reg32)
6910                 tp->write32 = tg3_write32;
6911
6912         /* Prevent the irq handler from reading or writing PCI registers
6913          * during chip reset when the memory enable bit in the PCI command
6914          * register may be cleared.  The chip does not generate interrupt
6915          * at this time, but the irq handler may still be called due to irq
6916          * sharing or irqpoll.
6917          */
6918         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6919         for (i = 0; i < tp->irq_cnt; i++) {
6920                 struct tg3_napi *tnapi = &tp->napi[i];
6921                 if (tnapi->hw_status) {
6922                         tnapi->hw_status->status = 0;
6923                         tnapi->hw_status->status_tag = 0;
6924                 }
6925                 tnapi->last_tag = 0;
6926                 tnapi->last_irq_tag = 0;
6927         }
6928         smp_mb();
6929
6930         for (i = 0; i < tp->irq_cnt; i++)
6931                 synchronize_irq(tp->napi[i].irq_vec);
6932
6933         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6934                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6935                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6936         }
6937
6938         /* do the reset */
6939         val = GRC_MISC_CFG_CORECLK_RESET;
6940
6941         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6942                 /* Force PCIe 1.0a mode */
6943                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6944                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6945                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6946                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6947                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6948
6949                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6950                         tw32(GRC_MISC_CFG, (1 << 29));
6951                         val |= (1 << 29);
6952                 }
6953         }
6954
6955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6956                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6957                 tw32(GRC_VCPU_EXT_CTRL,
6958                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6959         }
6960
6961         /* Manage gphy power for all CPMU absent PCIe devices. */
6962         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6963             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6964                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6965
6966         tw32(GRC_MISC_CFG, val);
6967
6968         /* restore 5701 hardware bug workaround write method */
6969         tp->write32 = write_op;
6970
6971         /* Unfortunately, we have to delay before the PCI read back.
6972          * Some 575X chips even will not respond to a PCI cfg access
6973          * when the reset command is given to the chip.
6974          *
6975          * How do these hardware designers expect things to work
6976          * properly if the PCI write is posted for a long period
6977          * of time?  It is always necessary to have some method by
6978          * which a register read back can occur to push the write
6979          * out which does the reset.
6980          *
6981          * For most tg3 variants the trick below was working.
6982          * Ho hum...
6983          */
6984         udelay(120);
6985
6986         /* Flush PCI posted writes.  The normal MMIO registers
6987          * are inaccessible at this time so this is the only
6988          * way to make this reliably (actually, this is no longer
6989          * the case, see above).  I tried to use indirect
6990          * register read/write but this upset some 5701 variants.
6991          */
6992         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6993
6994         udelay(120);
6995
6996         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6997                 u16 val16;
6998
6999                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7000                         int i;
7001                         u32 cfg_val;
7002
7003                         /* Wait for link training to complete.  */
7004                         for (i = 0; i < 5000; i++)
7005                                 udelay(100);
7006
7007                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7008                         pci_write_config_dword(tp->pdev, 0xc4,
7009                                                cfg_val | (1 << 15));
7010                 }
7011
7012                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7013                 pci_read_config_word(tp->pdev,
7014                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7015                                      &val16);
7016                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7017                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7018                 /*
7019                  * Older PCIe devices only support the 128 byte
7020                  * MPS setting.  Enforce the restriction.
7021                  */
7022                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7023                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7024                 pci_write_config_word(tp->pdev,
7025                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7026                                       val16);
7027
7028                 pcie_set_readrq(tp->pdev, 4096);
7029
7030                 /* Clear error status */
7031                 pci_write_config_word(tp->pdev,
7032                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7033                                       PCI_EXP_DEVSTA_CED |
7034                                       PCI_EXP_DEVSTA_NFED |
7035                                       PCI_EXP_DEVSTA_FED |
7036                                       PCI_EXP_DEVSTA_URD);
7037         }
7038
7039         tg3_restore_pci_state(tp);
7040
7041         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7042
7043         val = 0;
7044         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7045                 val = tr32(MEMARB_MODE);
7046         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7047
7048         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7049                 tg3_stop_fw(tp);
7050                 tw32(0x5000, 0x400);
7051         }
7052
7053         tw32(GRC_MODE, tp->grc_mode);
7054
7055         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7056                 val = tr32(0xc4);
7057
7058                 tw32(0xc4, val | (1 << 15));
7059         }
7060
7061         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7062             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7063                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7064                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7065                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7066                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7067         }
7068
7069         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7070                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7071                 tw32_f(MAC_MODE, tp->mac_mode);
7072         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7073                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7074                 tw32_f(MAC_MODE, tp->mac_mode);
7075         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7076                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7077                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7078                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7079                 tw32_f(MAC_MODE, tp->mac_mode);
7080         } else
7081                 tw32_f(MAC_MODE, 0);
7082         udelay(40);
7083
7084         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7085
7086         err = tg3_poll_fw(tp);
7087         if (err)
7088                 return err;
7089
7090         tg3_mdio_start(tp);
7091
7092         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7093             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7094             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7095             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7096                 val = tr32(0x7c00);
7097
7098                 tw32(0x7c00, val | (1 << 25));
7099         }
7100
7101         /* Reprobe ASF enable state.  */
7102         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7103         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7104         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7105         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7106                 u32 nic_cfg;
7107
7108                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7109                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7110                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7111                         tp->last_event_jiffies = jiffies;
7112                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7113                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7114                 }
7115         }
7116
7117         return 0;
7118 }
7119
7120 /* tp->lock is held. */
7121 static void tg3_stop_fw(struct tg3 *tp)
7122 {
7123         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7124            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7125                 /* Wait for RX cpu to ACK the previous event. */
7126                 tg3_wait_for_event_ack(tp);
7127
7128                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7129
7130                 tg3_generate_fw_event(tp);
7131
7132                 /* Wait for RX cpu to ACK this event. */
7133                 tg3_wait_for_event_ack(tp);
7134         }
7135 }
7136
7137 /* tp->lock is held. */
7138 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7139 {
7140         int err;
7141
7142         tg3_stop_fw(tp);
7143
7144         tg3_write_sig_pre_reset(tp, kind);
7145
7146         tg3_abort_hw(tp, silent);
7147         err = tg3_chip_reset(tp);
7148
7149         __tg3_set_mac_addr(tp, 0);
7150
7151         tg3_write_sig_legacy(tp, kind);
7152         tg3_write_sig_post_reset(tp, kind);
7153
7154         if (err)
7155                 return err;
7156
7157         return 0;
7158 }
7159
7160 #define RX_CPU_SCRATCH_BASE     0x30000
7161 #define RX_CPU_SCRATCH_SIZE     0x04000
7162 #define TX_CPU_SCRATCH_BASE     0x34000
7163 #define TX_CPU_SCRATCH_SIZE     0x04000
7164
7165 /* tp->lock is held. */
7166 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7167 {
7168         int i;
7169
7170         BUG_ON(offset == TX_CPU_BASE &&
7171             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7172
7173         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7174                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7175
7176                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7177                 return 0;
7178         }
7179         if (offset == RX_CPU_BASE) {
7180                 for (i = 0; i < 10000; i++) {
7181                         tw32(offset + CPU_STATE, 0xffffffff);
7182                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7183                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7184                                 break;
7185                 }
7186
7187                 tw32(offset + CPU_STATE, 0xffffffff);
7188                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7189                 udelay(10);
7190         } else {
7191                 for (i = 0; i < 10000; i++) {
7192                         tw32(offset + CPU_STATE, 0xffffffff);
7193                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7194                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7195                                 break;
7196                 }
7197         }
7198
7199         if (i >= 10000) {
7200                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7201                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7202                 return -ENODEV;
7203         }
7204
7205         /* Clear firmware's nvram arbitration. */
7206         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7207                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7208         return 0;
7209 }
7210
7211 struct fw_info {
7212         unsigned int fw_base;
7213         unsigned int fw_len;
7214         const __be32 *fw_data;
7215 };
7216
7217 /* tp->lock is held. */
7218 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7219                                  int cpu_scratch_size, struct fw_info *info)
7220 {
7221         int err, lock_err, i;
7222         void (*write_op)(struct tg3 *, u32, u32);
7223
7224         if (cpu_base == TX_CPU_BASE &&
7225             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7226                 netdev_err(tp->dev,
7227                            "%s: Trying to load TX cpu firmware which is 5705\n",
7228                            __func__);
7229                 return -EINVAL;
7230         }
7231
7232         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7233                 write_op = tg3_write_mem;
7234         else
7235                 write_op = tg3_write_indirect_reg32;
7236
7237         /* It is possible that bootcode is still loading at this point.
7238          * Get the nvram lock first before halting the cpu.
7239          */
7240         lock_err = tg3_nvram_lock(tp);
7241         err = tg3_halt_cpu(tp, cpu_base);
7242         if (!lock_err)
7243                 tg3_nvram_unlock(tp);
7244         if (err)
7245                 goto out;
7246
7247         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7248                 write_op(tp, cpu_scratch_base + i, 0);
7249         tw32(cpu_base + CPU_STATE, 0xffffffff);
7250         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7251         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7252                 write_op(tp, (cpu_scratch_base +
7253                               (info->fw_base & 0xffff) +
7254                               (i * sizeof(u32))),
7255                               be32_to_cpu(info->fw_data[i]));
7256
7257         err = 0;
7258
7259 out:
7260         return err;
7261 }
7262
7263 /* tp->lock is held. */
7264 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7265 {
7266         struct fw_info info;
7267         const __be32 *fw_data;
7268         int err, i;
7269
7270         fw_data = (void *)tp->fw->data;
7271
7272         /* Firmware blob starts with version numbers, followed by
7273            start address and length. We are setting complete length.
7274            length = end_address_of_bss - start_address_of_text.
7275            Remainder is the blob to be loaded contiguously
7276            from start address. */
7277
7278         info.fw_base = be32_to_cpu(fw_data[1]);
7279         info.fw_len = tp->fw->size - 12;
7280         info.fw_data = &fw_data[3];
7281
7282         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7283                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7284                                     &info);
7285         if (err)
7286                 return err;
7287
7288         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7289                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7290                                     &info);
7291         if (err)
7292                 return err;
7293
7294         /* Now startup only the RX cpu. */
7295         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7296         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7297
7298         for (i = 0; i < 5; i++) {
7299                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7300                         break;
7301                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7302                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7303                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7304                 udelay(1000);
7305         }
7306         if (i >= 5) {
7307                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7308                            "should be %08x\n", __func__,
7309                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7310                 return -ENODEV;
7311         }
7312         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7313         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7314
7315         return 0;
7316 }
7317
7318 /* 5705 needs a special version of the TSO firmware.  */
7319
7320 /* tp->lock is held. */
7321 static int tg3_load_tso_firmware(struct tg3 *tp)
7322 {
7323         struct fw_info info;
7324         const __be32 *fw_data;
7325         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7326         int err, i;
7327
7328         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7329                 return 0;
7330
7331         fw_data = (void *)tp->fw->data;
7332
7333         /* Firmware blob starts with version numbers, followed by
7334            start address and length. We are setting complete length.
7335            length = end_address_of_bss - start_address_of_text.
7336            Remainder is the blob to be loaded contiguously
7337            from start address. */
7338
7339         info.fw_base = be32_to_cpu(fw_data[1]);
7340         cpu_scratch_size = tp->fw_len;
7341         info.fw_len = tp->fw->size - 12;
7342         info.fw_data = &fw_data[3];
7343
7344         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7345                 cpu_base = RX_CPU_BASE;
7346                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7347         } else {
7348                 cpu_base = TX_CPU_BASE;
7349                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7350                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7351         }
7352
7353         err = tg3_load_firmware_cpu(tp, cpu_base,
7354                                     cpu_scratch_base, cpu_scratch_size,
7355                                     &info);
7356         if (err)
7357                 return err;
7358
7359         /* Now startup the cpu. */
7360         tw32(cpu_base + CPU_STATE, 0xffffffff);
7361         tw32_f(cpu_base + CPU_PC, info.fw_base);
7362
7363         for (i = 0; i < 5; i++) {
7364                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7365                         break;
7366                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7367                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7368                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7369                 udelay(1000);
7370         }
7371         if (i >= 5) {
7372                 netdev_err(tp->dev,
7373                            "%s fails to set CPU PC, is %08x should be %08x\n",
7374                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7375                 return -ENODEV;
7376         }
7377         tw32(cpu_base + CPU_STATE, 0xffffffff);
7378         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7379         return 0;
7380 }
7381
7382
7383 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7384 {
7385         struct tg3 *tp = netdev_priv(dev);
7386         struct sockaddr *addr = p;
7387         int err = 0, skip_mac_1 = 0;
7388
7389         if (!is_valid_ether_addr(addr->sa_data))
7390                 return -EINVAL;
7391
7392         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7393
7394         if (!netif_running(dev))
7395                 return 0;
7396
7397         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7398                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7399
7400                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7401                 addr0_low = tr32(MAC_ADDR_0_LOW);
7402                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7403                 addr1_low = tr32(MAC_ADDR_1_LOW);
7404
7405                 /* Skip MAC addr 1 if ASF is using it. */
7406                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7407                     !(addr1_high == 0 && addr1_low == 0))
7408                         skip_mac_1 = 1;
7409         }
7410         spin_lock_bh(&tp->lock);
7411         __tg3_set_mac_addr(tp, skip_mac_1);
7412         spin_unlock_bh(&tp->lock);
7413
7414         return err;
7415 }
7416
7417 /* tp->lock is held. */
7418 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7419                            dma_addr_t mapping, u32 maxlen_flags,
7420                            u32 nic_addr)
7421 {
7422         tg3_write_mem(tp,
7423                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7424                       ((u64) mapping >> 32));
7425         tg3_write_mem(tp,
7426                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7427                       ((u64) mapping & 0xffffffff));
7428         tg3_write_mem(tp,
7429                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7430                        maxlen_flags);
7431
7432         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7433                 tg3_write_mem(tp,
7434                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7435                               nic_addr);
7436 }
7437
7438 static void __tg3_set_rx_mode(struct net_device *);
7439 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7440 {
7441         int i;
7442
7443         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7444                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7445                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7446                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7447         } else {
7448                 tw32(HOSTCC_TXCOL_TICKS, 0);
7449                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7450                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7451         }
7452
7453         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7454                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7455                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7456                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7457         } else {
7458                 tw32(HOSTCC_RXCOL_TICKS, 0);
7459                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7460                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7461         }
7462
7463         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7464                 u32 val = ec->stats_block_coalesce_usecs;
7465
7466                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7467                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7468
7469                 if (!netif_carrier_ok(tp->dev))
7470                         val = 0;
7471
7472                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7473         }
7474
7475         for (i = 0; i < tp->irq_cnt - 1; i++) {
7476                 u32 reg;
7477
7478                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7479                 tw32(reg, ec->rx_coalesce_usecs);
7480                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7481                 tw32(reg, ec->rx_max_coalesced_frames);
7482                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7483                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7484
7485                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7486                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7487                         tw32(reg, ec->tx_coalesce_usecs);
7488                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7489                         tw32(reg, ec->tx_max_coalesced_frames);
7490                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7491                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7492                 }
7493         }
7494
7495         for (; i < tp->irq_max - 1; i++) {
7496                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7497                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7498                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7499
7500                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7501                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7502                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7503                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7504                 }
7505         }
7506 }
7507
7508 /* tp->lock is held. */
7509 static void tg3_rings_reset(struct tg3 *tp)
7510 {
7511         int i;
7512         u32 stblk, txrcb, rxrcb, limit;
7513         struct tg3_napi *tnapi = &tp->napi[0];
7514
7515         /* Disable all transmit rings but the first. */
7516         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7517                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7518         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7519                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7520         else
7521                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7522
7523         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7524              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7525                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7526                               BDINFO_FLAGS_DISABLED);
7527
7528
7529         /* Disable all receive return rings but the first. */
7530         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7531             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7532                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7533         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7534                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7535         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7536                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7537                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7538         else
7539                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7540
7541         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7542              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7543                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7544                               BDINFO_FLAGS_DISABLED);
7545
7546         /* Disable interrupts */
7547         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7548
7549         /* Zero mailbox registers. */
7550         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7551                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7552                         tp->napi[i].tx_prod = 0;
7553                         tp->napi[i].tx_cons = 0;
7554                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7555                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7556                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7557                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7558                 }
7559                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7560                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7561         } else {
7562                 tp->napi[0].tx_prod = 0;
7563                 tp->napi[0].tx_cons = 0;
7564                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7565                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7566         }
7567
7568         /* Make sure the NIC-based send BD rings are disabled. */
7569         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7570                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7571                 for (i = 0; i < 16; i++)
7572                         tw32_tx_mbox(mbox + i * 8, 0);
7573         }
7574
7575         txrcb = NIC_SRAM_SEND_RCB;
7576         rxrcb = NIC_SRAM_RCV_RET_RCB;
7577
7578         /* Clear status block in ram. */
7579         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7580
7581         /* Set status block DMA address */
7582         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7583              ((u64) tnapi->status_mapping >> 32));
7584         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7585              ((u64) tnapi->status_mapping & 0xffffffff));
7586
7587         if (tnapi->tx_ring) {
7588                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7589                                (TG3_TX_RING_SIZE <<
7590                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7591                                NIC_SRAM_TX_BUFFER_DESC);
7592                 txrcb += TG3_BDINFO_SIZE;
7593         }
7594
7595         if (tnapi->rx_rcb) {
7596                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7597                                (TG3_RX_RCB_RING_SIZE(tp) <<
7598                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7599                 rxrcb += TG3_BDINFO_SIZE;
7600         }
7601
7602         stblk = HOSTCC_STATBLCK_RING1;
7603
7604         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7605                 u64 mapping = (u64)tnapi->status_mapping;
7606                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7607                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7608
7609                 /* Clear status block in ram. */
7610                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7611
7612                 if (tnapi->tx_ring) {
7613                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7614                                        (TG3_TX_RING_SIZE <<
7615                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7616                                        NIC_SRAM_TX_BUFFER_DESC);
7617                         txrcb += TG3_BDINFO_SIZE;
7618                 }
7619
7620                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7621                                (TG3_RX_RCB_RING_SIZE(tp) <<
7622                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7623
7624                 stblk += 8;
7625                 rxrcb += TG3_BDINFO_SIZE;
7626         }
7627 }
7628
7629 /* tp->lock is held. */
7630 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7631 {
7632         u32 val, rdmac_mode;
7633         int i, err, limit;
7634         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7635
7636         tg3_disable_ints(tp);
7637
7638         tg3_stop_fw(tp);
7639
7640         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7641
7642         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7643                 tg3_abort_hw(tp, 1);
7644
7645         if (reset_phy)
7646                 tg3_phy_reset(tp);
7647
7648         err = tg3_chip_reset(tp);
7649         if (err)
7650                 return err;
7651
7652         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7653
7654         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7655                 val = tr32(TG3_CPMU_CTRL);
7656                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7657                 tw32(TG3_CPMU_CTRL, val);
7658
7659                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7660                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7661                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7662                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7663
7664                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7665                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7666                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7667                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7668
7669                 val = tr32(TG3_CPMU_HST_ACC);
7670                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7671                 val |= CPMU_HST_ACC_MACCLK_6_25;
7672                 tw32(TG3_CPMU_HST_ACC, val);
7673         }
7674
7675         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7676                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7677                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7678                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7679                 tw32(PCIE_PWR_MGMT_THRESH, val);
7680
7681                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7682                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7683
7684                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7685
7686                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7687                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7688         }
7689
7690         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7691                 u32 grc_mode = tr32(GRC_MODE);
7692
7693                 /* Access the lower 1K of PL PCIE block registers. */
7694                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7695                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7696
7697                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7698                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7699                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7700
7701                 tw32(GRC_MODE, grc_mode);
7702         }
7703
7704         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7705                 u32 grc_mode = tr32(GRC_MODE);
7706
7707                 /* Access the lower 1K of PL PCIE block registers. */
7708                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7709                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7710
7711                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7712                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7713                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7714
7715                 tw32(GRC_MODE, grc_mode);
7716
7717                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7718                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7719                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7720                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7721         }
7722
7723         /* This works around an issue with Athlon chipsets on
7724          * B3 tigon3 silicon.  This bit has no effect on any
7725          * other revision.  But do not set this on PCI Express
7726          * chips and don't even touch the clocks if the CPMU is present.
7727          */
7728         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7729                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7730                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7731                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7732         }
7733
7734         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7735             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7736                 val = tr32(TG3PCI_PCISTATE);
7737                 val |= PCISTATE_RETRY_SAME_DMA;
7738                 tw32(TG3PCI_PCISTATE, val);
7739         }
7740
7741         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7742                 /* Allow reads and writes to the
7743                  * APE register and memory space.
7744                  */
7745                 val = tr32(TG3PCI_PCISTATE);
7746                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7747                        PCISTATE_ALLOW_APE_SHMEM_WR |
7748                        PCISTATE_ALLOW_APE_PSPACE_WR;
7749                 tw32(TG3PCI_PCISTATE, val);
7750         }
7751
7752         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7753                 /* Enable some hw fixes.  */
7754                 val = tr32(TG3PCI_MSI_DATA);
7755                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7756                 tw32(TG3PCI_MSI_DATA, val);
7757         }
7758
7759         /* Descriptor ring init may make accesses to the
7760          * NIC SRAM area to setup the TX descriptors, so we
7761          * can only do this after the hardware has been
7762          * successfully reset.
7763          */
7764         err = tg3_init_rings(tp);
7765         if (err)
7766                 return err;
7767
7768         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7769                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7770                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7771                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7772                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7773                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7774         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7775                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7776                 /* This value is determined during the probe time DMA
7777                  * engine test, tg3_test_dma.
7778                  */
7779                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7780         }
7781
7782         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7783                           GRC_MODE_4X_NIC_SEND_RINGS |
7784                           GRC_MODE_NO_TX_PHDR_CSUM |
7785                           GRC_MODE_NO_RX_PHDR_CSUM);
7786         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7787
7788         /* Pseudo-header checksum is done by hardware logic and not
7789          * the offload processers, so make the chip do the pseudo-
7790          * header checksums on receive.  For transmit it is more
7791          * convenient to do the pseudo-header checksum in software
7792          * as Linux does that on transmit for us in all cases.
7793          */
7794         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7795
7796         tw32(GRC_MODE,
7797              tp->grc_mode |
7798              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7799
7800         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7801         val = tr32(GRC_MISC_CFG);
7802         val &= ~0xff;
7803         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7804         tw32(GRC_MISC_CFG, val);
7805
7806         /* Initialize MBUF/DESC pool. */
7807         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7808                 /* Do nothing.  */
7809         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7810                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7811                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7812                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7813                 else
7814                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7815                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7816                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7817         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7818                 int fw_len;
7819
7820                 fw_len = tp->fw_len;
7821                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7822                 tw32(BUFMGR_MB_POOL_ADDR,
7823                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7824                 tw32(BUFMGR_MB_POOL_SIZE,
7825                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7826         }
7827
7828         if (tp->dev->mtu <= ETH_DATA_LEN) {
7829                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7830                      tp->bufmgr_config.mbuf_read_dma_low_water);
7831                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7832                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7833                 tw32(BUFMGR_MB_HIGH_WATER,
7834                      tp->bufmgr_config.mbuf_high_water);
7835         } else {
7836                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7837                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7838                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7839                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7840                 tw32(BUFMGR_MB_HIGH_WATER,
7841                      tp->bufmgr_config.mbuf_high_water_jumbo);
7842         }
7843         tw32(BUFMGR_DMA_LOW_WATER,
7844              tp->bufmgr_config.dma_low_water);
7845         tw32(BUFMGR_DMA_HIGH_WATER,
7846              tp->bufmgr_config.dma_high_water);
7847
7848         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7849         for (i = 0; i < 2000; i++) {
7850                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7851                         break;
7852                 udelay(10);
7853         }
7854         if (i >= 2000) {
7855                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7856                 return -ENODEV;
7857         }
7858
7859         /* Setup replenish threshold. */
7860         val = tp->rx_pending / 8;
7861         if (val == 0)
7862                 val = 1;
7863         else if (val > tp->rx_std_max_post)
7864                 val = tp->rx_std_max_post;
7865         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7866                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7867                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7868
7869                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7870                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7871         }
7872
7873         tw32(RCVBDI_STD_THRESH, val);
7874
7875         /* Initialize TG3_BDINFO's at:
7876          *  RCVDBDI_STD_BD:     standard eth size rx ring
7877          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7878          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7879          *
7880          * like so:
7881          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7882          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7883          *                              ring attribute flags
7884          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7885          *
7886          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7887          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7888          *
7889          * The size of each ring is fixed in the firmware, but the location is
7890          * configurable.
7891          */
7892         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7893              ((u64) tpr->rx_std_mapping >> 32));
7894         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7895              ((u64) tpr->rx_std_mapping & 0xffffffff));
7896         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7897             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7898                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7899                      NIC_SRAM_RX_BUFFER_DESC);
7900
7901         /* Disable the mini ring */
7902         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7903                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7904                      BDINFO_FLAGS_DISABLED);
7905
7906         /* Program the jumbo buffer descriptor ring control
7907          * blocks on those devices that have them.
7908          */
7909         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7910             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7911                 /* Setup replenish threshold. */
7912                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7913
7914                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7915                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7916                              ((u64) tpr->rx_jmb_mapping >> 32));
7917                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7918                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7919                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7920                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7921                              BDINFO_FLAGS_USE_EXT_RECV);
7922                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7923                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7924                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7925                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7926                 } else {
7927                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7928                              BDINFO_FLAGS_DISABLED);
7929                 }
7930
7931                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7932                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7933                               (TG3_RX_STD_DMA_SZ << 2);
7934                 else
7935                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7936         } else
7937                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7938
7939         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7940
7941         tpr->rx_std_prod_idx = tp->rx_pending;
7942         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7943
7944         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7945                           tp->rx_jumbo_pending : 0;
7946         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7947
7948         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7949                 tw32(STD_REPLENISH_LWM, 32);
7950                 tw32(JMB_REPLENISH_LWM, 16);
7951         }
7952
7953         tg3_rings_reset(tp);
7954
7955         /* Initialize MAC address and backoff seed. */
7956         __tg3_set_mac_addr(tp, 0);
7957
7958         /* MTU + ethernet header + FCS + optional VLAN tag */
7959         tw32(MAC_RX_MTU_SIZE,
7960              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7961
7962         /* The slot time is changed by tg3_setup_phy if we
7963          * run at gigabit with half duplex.
7964          */
7965         tw32(MAC_TX_LENGTHS,
7966              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7967              (6 << TX_LENGTHS_IPG_SHIFT) |
7968              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7969
7970         /* Receive rules. */
7971         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7972         tw32(RCVLPC_CONFIG, 0x0181);
7973
7974         /* Calculate RDMAC_MODE setting early, we need it to determine
7975          * the RCVLPC_STATE_ENABLE mask.
7976          */
7977         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7978                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7979                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7980                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7981                       RDMAC_MODE_LNGREAD_ENAB);
7982
7983         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7985                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7986
7987         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7988             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7989             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7990                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7991                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7992                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7993
7994         /* If statement applies to 5705 and 5750 PCI devices only */
7995         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7996              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7997             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7998                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7999                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8000                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8001                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8002                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8003                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8004                 }
8005         }
8006
8007         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8008                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8009
8010         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8011                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8012
8013         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8015             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8016                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8017
8018         /* Receive/send statistics. */
8019         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8020                 val = tr32(RCVLPC_STATS_ENABLE);
8021                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8022                 tw32(RCVLPC_STATS_ENABLE, val);
8023         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8024                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8025                 val = tr32(RCVLPC_STATS_ENABLE);
8026                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8027                 tw32(RCVLPC_STATS_ENABLE, val);
8028         } else {
8029                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8030         }
8031         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8032         tw32(SNDDATAI_STATSENAB, 0xffffff);
8033         tw32(SNDDATAI_STATSCTRL,
8034              (SNDDATAI_SCTRL_ENABLE |
8035               SNDDATAI_SCTRL_FASTUPD));
8036
8037         /* Setup host coalescing engine. */
8038         tw32(HOSTCC_MODE, 0);
8039         for (i = 0; i < 2000; i++) {
8040                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8041                         break;
8042                 udelay(10);
8043         }
8044
8045         __tg3_set_coalesce(tp, &tp->coal);
8046
8047         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8048                 /* Status/statistics block address.  See tg3_timer,
8049                  * the tg3_periodic_fetch_stats call there, and
8050                  * tg3_get_stats to see how this works for 5705/5750 chips.
8051                  */
8052                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8053                      ((u64) tp->stats_mapping >> 32));
8054                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8055                      ((u64) tp->stats_mapping & 0xffffffff));
8056                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8057
8058                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8059
8060                 /* Clear statistics and status block memory areas */
8061                 for (i = NIC_SRAM_STATS_BLK;
8062                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8063                      i += sizeof(u32)) {
8064                         tg3_write_mem(tp, i, 0);
8065                         udelay(40);
8066                 }
8067         }
8068
8069         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8070
8071         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8072         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8073         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8074                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8075
8076         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8077                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8078                 /* reset to prevent losing 1st rx packet intermittently */
8079                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8080                 udelay(10);
8081         }
8082
8083         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8084                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8085         else
8086                 tp->mac_mode = 0;
8087         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8088                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8089         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8090             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8091             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8092                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8093         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8094         udelay(40);
8095
8096         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8097          * If TG3_FLG2_IS_NIC is zero, we should read the
8098          * register to preserve the GPIO settings for LOMs. The GPIOs,
8099          * whether used as inputs or outputs, are set by boot code after
8100          * reset.
8101          */
8102         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8103                 u32 gpio_mask;
8104
8105                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8106                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8107                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8108
8109                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8110                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8111                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8112
8113                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8114                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8115
8116                 tp->grc_local_ctrl &= ~gpio_mask;
8117                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8118
8119                 /* GPIO1 must be driven high for eeprom write protect */
8120                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8121                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8122                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8123         }
8124         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8125         udelay(100);
8126
8127         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8128                 val = tr32(MSGINT_MODE);
8129                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8130                 tw32(MSGINT_MODE, val);
8131         }
8132
8133         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8134                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8135                 udelay(40);
8136         }
8137
8138         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8139                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8140                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8141                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8142                WDMAC_MODE_LNGREAD_ENAB);
8143
8144         /* If statement applies to 5705 and 5750 PCI devices only */
8145         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8146              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8147             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8148                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8149                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8150                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8151                         /* nothing */
8152                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8153                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8154                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8155                         val |= WDMAC_MODE_RX_ACCEL;
8156                 }
8157         }
8158
8159         /* Enable host coalescing bug fix */
8160         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8161                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8162
8163         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8164                 val |= WDMAC_MODE_BURST_ALL_DATA;
8165
8166         tw32_f(WDMAC_MODE, val);
8167         udelay(40);
8168
8169         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8170                 u16 pcix_cmd;
8171
8172                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8173                                      &pcix_cmd);
8174                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8175                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8176                         pcix_cmd |= PCI_X_CMD_READ_2K;
8177                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8178                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8179                         pcix_cmd |= PCI_X_CMD_READ_2K;
8180                 }
8181                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8182                                       pcix_cmd);
8183         }
8184
8185         tw32_f(RDMAC_MODE, rdmac_mode);
8186         udelay(40);
8187
8188         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8189         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8190                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8191
8192         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8193                 tw32(SNDDATAC_MODE,
8194                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8195         else
8196                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8197
8198         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8199         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8200         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8201         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8202         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8203                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8204         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8205         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8206                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8207         tw32(SNDBDI_MODE, val);
8208         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8209
8210         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8211                 err = tg3_load_5701_a0_firmware_fix(tp);
8212                 if (err)
8213                         return err;
8214         }
8215
8216         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8217                 err = tg3_load_tso_firmware(tp);
8218                 if (err)
8219                         return err;
8220         }
8221
8222         tp->tx_mode = TX_MODE_ENABLE;
8223         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8224             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8225                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8226         tw32_f(MAC_TX_MODE, tp->tx_mode);
8227         udelay(100);
8228
8229         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8230                 u32 reg = MAC_RSS_INDIR_TBL_0;
8231                 u8 *ent = (u8 *)&val;
8232
8233                 /* Setup the indirection table */
8234                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8235                         int idx = i % sizeof(val);
8236
8237                         ent[idx] = i % (tp->irq_cnt - 1);
8238                         if (idx == sizeof(val) - 1) {
8239                                 tw32(reg, val);
8240                                 reg += 4;
8241                         }
8242                 }
8243
8244                 /* Setup the "secret" hash key. */
8245                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8246                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8247                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8248                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8249                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8250                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8251                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8252                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8253                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8254                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8255         }
8256
8257         tp->rx_mode = RX_MODE_ENABLE;
8258         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8259                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8260
8261         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8262                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8263                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8264                                RX_MODE_RSS_IPV6_HASH_EN |
8265                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8266                                RX_MODE_RSS_IPV4_HASH_EN |
8267                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8268
8269         tw32_f(MAC_RX_MODE, tp->rx_mode);
8270         udelay(10);
8271
8272         tw32(MAC_LED_CTRL, tp->led_ctrl);
8273
8274         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8275         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8276                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8277                 udelay(10);
8278         }
8279         tw32_f(MAC_RX_MODE, tp->rx_mode);
8280         udelay(10);
8281
8282         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8283                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8284                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8285                         /* Set drive transmission level to 1.2V  */
8286                         /* only if the signal pre-emphasis bit is not set  */
8287                         val = tr32(MAC_SERDES_CFG);
8288                         val &= 0xfffff000;
8289                         val |= 0x880;
8290                         tw32(MAC_SERDES_CFG, val);
8291                 }
8292                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8293                         tw32(MAC_SERDES_CFG, 0x616000);
8294         }
8295
8296         /* Prevent chip from dropping frames when flow control
8297          * is enabled.
8298          */
8299         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8300                 val = 1;
8301         else
8302                 val = 2;
8303         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8304
8305         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8306             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8307                 /* Use hardware link auto-negotiation */
8308                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8309         }
8310
8311         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8312             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8313                 u32 tmp;
8314
8315                 tmp = tr32(SERDES_RX_CTRL);
8316                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8317                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8318                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8319                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8320         }
8321
8322         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8323                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8324                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8325                         tp->link_config.speed = tp->link_config.orig_speed;
8326                         tp->link_config.duplex = tp->link_config.orig_duplex;
8327                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8328                 }
8329
8330                 err = tg3_setup_phy(tp, 0);
8331                 if (err)
8332                         return err;
8333
8334                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8335                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8336                         u32 tmp;
8337
8338                         /* Clear CRC stats. */
8339                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8340                                 tg3_writephy(tp, MII_TG3_TEST1,
8341                                              tmp | MII_TG3_TEST1_CRC_EN);
8342                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8343                         }
8344                 }
8345         }
8346
8347         __tg3_set_rx_mode(tp->dev);
8348
8349         /* Initialize receive rules. */
8350         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8351         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8352         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8353         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8354
8355         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8356             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8357                 limit = 8;
8358         else
8359                 limit = 16;
8360         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8361                 limit -= 4;
8362         switch (limit) {
8363         case 16:
8364                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8365         case 15:
8366                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8367         case 14:
8368                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8369         case 13:
8370                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8371         case 12:
8372                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8373         case 11:
8374                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8375         case 10:
8376                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8377         case 9:
8378                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8379         case 8:
8380                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8381         case 7:
8382                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8383         case 6:
8384                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8385         case 5:
8386                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8387         case 4:
8388                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8389         case 3:
8390                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8391         case 2:
8392         case 1:
8393
8394         default:
8395                 break;
8396         }
8397
8398         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8399                 /* Write our heartbeat update interval to APE. */
8400                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8401                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8402
8403         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8404
8405         return 0;
8406 }
8407
8408 /* Called at device open time to get the chip ready for
8409  * packet processing.  Invoked with tp->lock held.
8410  */
8411 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8412 {
8413         tg3_switch_clocks(tp);
8414
8415         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8416
8417         return tg3_reset_hw(tp, reset_phy);
8418 }
8419
8420 #define TG3_STAT_ADD32(PSTAT, REG) \
8421 do {    u32 __val = tr32(REG); \
8422         (PSTAT)->low += __val; \
8423         if ((PSTAT)->low < __val) \
8424                 (PSTAT)->high += 1; \
8425 } while (0)
8426
8427 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8428 {
8429         struct tg3_hw_stats *sp = tp->hw_stats;
8430
8431         if (!netif_carrier_ok(tp->dev))
8432                 return;
8433
8434         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8435         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8436         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8437         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8438         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8439         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8440         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8441         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8442         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8443         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8444         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8445         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8446         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8447
8448         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8449         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8450         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8451         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8452         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8453         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8454         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8455         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8456         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8457         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8458         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8459         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8460         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8461         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8462
8463         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8464         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8465         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8466 }
8467
8468 static void tg3_timer(unsigned long __opaque)
8469 {
8470         struct tg3 *tp = (struct tg3 *) __opaque;
8471
8472         if (tp->irq_sync)
8473                 goto restart_timer;
8474
8475         spin_lock(&tp->lock);
8476
8477         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8478                 /* All of this garbage is because when using non-tagged
8479                  * IRQ status the mailbox/status_block protocol the chip
8480                  * uses with the cpu is race prone.
8481                  */
8482                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8483                         tw32(GRC_LOCAL_CTRL,
8484                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8485                 } else {
8486                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8487                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8488                 }
8489
8490                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8491                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8492                         spin_unlock(&tp->lock);
8493                         schedule_work(&tp->reset_task);
8494                         return;
8495                 }
8496         }
8497
8498         /* This part only runs once per second. */
8499         if (!--tp->timer_counter) {
8500                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8501                         tg3_periodic_fetch_stats(tp);
8502
8503                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8504                         u32 mac_stat;
8505                         int phy_event;
8506
8507                         mac_stat = tr32(MAC_STATUS);
8508
8509                         phy_event = 0;
8510                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8511                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8512                                         phy_event = 1;
8513                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8514                                 phy_event = 1;
8515
8516                         if (phy_event)
8517                                 tg3_setup_phy(tp, 0);
8518                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8519                         u32 mac_stat = tr32(MAC_STATUS);
8520                         int need_setup = 0;
8521
8522                         if (netif_carrier_ok(tp->dev) &&
8523                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8524                                 need_setup = 1;
8525                         }
8526                         if (!netif_carrier_ok(tp->dev) &&
8527                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8528                                          MAC_STATUS_SIGNAL_DET))) {
8529                                 need_setup = 1;
8530                         }
8531                         if (need_setup) {
8532                                 if (!tp->serdes_counter) {
8533                                         tw32_f(MAC_MODE,
8534                                              (tp->mac_mode &
8535                                               ~MAC_MODE_PORT_MODE_MASK));
8536                                         udelay(40);
8537                                         tw32_f(MAC_MODE, tp->mac_mode);
8538                                         udelay(40);
8539                                 }
8540                                 tg3_setup_phy(tp, 0);
8541                         }
8542                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8543                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8544                         tg3_serdes_parallel_detect(tp);
8545                 }
8546
8547                 tp->timer_counter = tp->timer_multiplier;
8548         }
8549
8550         /* Heartbeat is only sent once every 2 seconds.
8551          *
8552          * The heartbeat is to tell the ASF firmware that the host
8553          * driver is still alive.  In the event that the OS crashes,
8554          * ASF needs to reset the hardware to free up the FIFO space
8555          * that may be filled with rx packets destined for the host.
8556          * If the FIFO is full, ASF will no longer function properly.
8557          *
8558          * Unintended resets have been reported on real time kernels
8559          * where the timer doesn't run on time.  Netpoll will also have
8560          * same problem.
8561          *
8562          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8563          * to check the ring condition when the heartbeat is expiring
8564          * before doing the reset.  This will prevent most unintended
8565          * resets.
8566          */
8567         if (!--tp->asf_counter) {
8568                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8569                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8570                         tg3_wait_for_event_ack(tp);
8571
8572                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8573                                       FWCMD_NICDRV_ALIVE3);
8574                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8575                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8576                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8577
8578                         tg3_generate_fw_event(tp);
8579                 }
8580                 tp->asf_counter = tp->asf_multiplier;
8581         }
8582
8583         spin_unlock(&tp->lock);
8584
8585 restart_timer:
8586         tp->timer.expires = jiffies + tp->timer_offset;
8587         add_timer(&tp->timer);
8588 }
8589
8590 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8591 {
8592         irq_handler_t fn;
8593         unsigned long flags;
8594         char *name;
8595         struct tg3_napi *tnapi = &tp->napi[irq_num];
8596
8597         if (tp->irq_cnt == 1)
8598                 name = tp->dev->name;
8599         else {
8600                 name = &tnapi->irq_lbl[0];
8601                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8602                 name[IFNAMSIZ-1] = 0;
8603         }
8604
8605         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8606                 fn = tg3_msi;
8607                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8608                         fn = tg3_msi_1shot;
8609                 flags = IRQF_SAMPLE_RANDOM;
8610         } else {
8611                 fn = tg3_interrupt;
8612                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8613                         fn = tg3_interrupt_tagged;
8614                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8615         }
8616
8617         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8618 }
8619
8620 static int tg3_test_interrupt(struct tg3 *tp)
8621 {
8622         struct tg3_napi *tnapi = &tp->napi[0];
8623         struct net_device *dev = tp->dev;
8624         int err, i, intr_ok = 0;
8625         u32 val;
8626
8627         if (!netif_running(dev))
8628                 return -ENODEV;
8629
8630         tg3_disable_ints(tp);
8631
8632         free_irq(tnapi->irq_vec, tnapi);
8633
8634         /*
8635          * Turn off MSI one shot mode.  Otherwise this test has no
8636          * observable way to know whether the interrupt was delivered.
8637          */
8638         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8639             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8640                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8641                 tw32(MSGINT_MODE, val);
8642         }
8643
8644         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8645                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8646         if (err)
8647                 return err;
8648
8649         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8650         tg3_enable_ints(tp);
8651
8652         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8653                tnapi->coal_now);
8654
8655         for (i = 0; i < 5; i++) {
8656                 u32 int_mbox, misc_host_ctrl;
8657
8658                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8659                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8660
8661                 if ((int_mbox != 0) ||
8662                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8663                         intr_ok = 1;
8664                         break;
8665                 }
8666
8667                 msleep(10);
8668         }
8669
8670         tg3_disable_ints(tp);
8671
8672         free_irq(tnapi->irq_vec, tnapi);
8673
8674         err = tg3_request_irq(tp, 0);
8675
8676         if (err)
8677                 return err;
8678
8679         if (intr_ok) {
8680                 /* Reenable MSI one shot mode. */
8681                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8682                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8683                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8684                         tw32(MSGINT_MODE, val);
8685                 }
8686                 return 0;
8687         }
8688
8689         return -EIO;
8690 }
8691
8692 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8693  * successfully restored
8694  */
8695 static int tg3_test_msi(struct tg3 *tp)
8696 {
8697         int err;
8698         u16 pci_cmd;
8699
8700         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8701                 return 0;
8702
8703         /* Turn off SERR reporting in case MSI terminates with Master
8704          * Abort.
8705          */
8706         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8707         pci_write_config_word(tp->pdev, PCI_COMMAND,
8708                               pci_cmd & ~PCI_COMMAND_SERR);
8709
8710         err = tg3_test_interrupt(tp);
8711
8712         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8713
8714         if (!err)
8715                 return 0;
8716
8717         /* other failures */
8718         if (err != -EIO)
8719                 return err;
8720
8721         /* MSI test failed, go back to INTx mode */
8722         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8723                     "to INTx mode. Please report this failure to the PCI "
8724                     "maintainer and include system chipset information\n");
8725
8726         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8727
8728         pci_disable_msi(tp->pdev);
8729
8730         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8731         tp->napi[0].irq_vec = tp->pdev->irq;
8732
8733         err = tg3_request_irq(tp, 0);
8734         if (err)
8735                 return err;
8736
8737         /* Need to reset the chip because the MSI cycle may have terminated
8738          * with Master Abort.
8739          */
8740         tg3_full_lock(tp, 1);
8741
8742         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8743         err = tg3_init_hw(tp, 1);
8744
8745         tg3_full_unlock(tp);
8746
8747         if (err)
8748                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8749
8750         return err;
8751 }
8752
8753 static int tg3_request_firmware(struct tg3 *tp)
8754 {
8755         const __be32 *fw_data;
8756
8757         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8758                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8759                            tp->fw_needed);
8760                 return -ENOENT;
8761         }
8762
8763         fw_data = (void *)tp->fw->data;
8764
8765         /* Firmware blob starts with version numbers, followed by
8766          * start address and _full_ length including BSS sections
8767          * (which must be longer than the actual data, of course
8768          */
8769
8770         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8771         if (tp->fw_len < (tp->fw->size - 12)) {
8772                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8773                            tp->fw_len, tp->fw_needed);
8774                 release_firmware(tp->fw);
8775                 tp->fw = NULL;
8776                 return -EINVAL;
8777         }
8778
8779         /* We no longer need firmware; we have it. */
8780         tp->fw_needed = NULL;
8781         return 0;
8782 }
8783
8784 static bool tg3_enable_msix(struct tg3 *tp)
8785 {
8786         int i, rc, cpus = num_online_cpus();
8787         struct msix_entry msix_ent[tp->irq_max];
8788
8789         if (cpus == 1)
8790                 /* Just fallback to the simpler MSI mode. */
8791                 return false;
8792
8793         /*
8794          * We want as many rx rings enabled as there are cpus.
8795          * The first MSIX vector only deals with link interrupts, etc,
8796          * so we add one to the number of vectors we are requesting.
8797          */
8798         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8799
8800         for (i = 0; i < tp->irq_max; i++) {
8801                 msix_ent[i].entry  = i;
8802                 msix_ent[i].vector = 0;
8803         }
8804
8805         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8806         if (rc < 0) {
8807                 return false;
8808         } else if (rc != 0) {
8809                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8810                         return false;
8811                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8812                               tp->irq_cnt, rc);
8813                 tp->irq_cnt = rc;
8814         }
8815
8816         for (i = 0; i < tp->irq_max; i++)
8817                 tp->napi[i].irq_vec = msix_ent[i].vector;
8818
8819         tp->dev->real_num_tx_queues = 1;
8820         if (tp->irq_cnt > 1) {
8821                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8822
8823                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8824                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8825                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8826                         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8827                 }
8828         }
8829
8830         return true;
8831 }
8832
8833 static void tg3_ints_init(struct tg3 *tp)
8834 {
8835         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8836             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8837                 /* All MSI supporting chips should support tagged
8838                  * status.  Assert that this is the case.
8839                  */
8840                 netdev_warn(tp->dev,
8841                             "MSI without TAGGED_STATUS? Not using MSI\n");
8842                 goto defcfg;
8843         }
8844
8845         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8846                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8847         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8848                  pci_enable_msi(tp->pdev) == 0)
8849                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8850
8851         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8852                 u32 msi_mode = tr32(MSGINT_MODE);
8853                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8854                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8855                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8856         }
8857 defcfg:
8858         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8859                 tp->irq_cnt = 1;
8860                 tp->napi[0].irq_vec = tp->pdev->irq;
8861                 tp->dev->real_num_tx_queues = 1;
8862         }
8863 }
8864
8865 static void tg3_ints_fini(struct tg3 *tp)
8866 {
8867         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8868                 pci_disable_msix(tp->pdev);
8869         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8870                 pci_disable_msi(tp->pdev);
8871         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8872         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8873 }
8874
8875 static int tg3_open(struct net_device *dev)
8876 {
8877         struct tg3 *tp = netdev_priv(dev);
8878         int i, err;
8879
8880         if (tp->fw_needed) {
8881                 err = tg3_request_firmware(tp);
8882                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8883                         if (err)
8884                                 return err;
8885                 } else if (err) {
8886                         netdev_warn(tp->dev, "TSO capability disabled\n");
8887                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8888                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8889                         netdev_notice(tp->dev, "TSO capability restored\n");
8890                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8891                 }
8892         }
8893
8894         netif_carrier_off(tp->dev);
8895
8896         err = tg3_set_power_state(tp, PCI_D0);
8897         if (err)
8898                 return err;
8899
8900         tg3_full_lock(tp, 0);
8901
8902         tg3_disable_ints(tp);
8903         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8904
8905         tg3_full_unlock(tp);
8906
8907         /*
8908          * Setup interrupts first so we know how
8909          * many NAPI resources to allocate
8910          */
8911         tg3_ints_init(tp);
8912
8913         /* The placement of this call is tied
8914          * to the setup and use of Host TX descriptors.
8915          */
8916         err = tg3_alloc_consistent(tp);
8917         if (err)
8918                 goto err_out1;
8919
8920         tg3_napi_enable(tp);
8921
8922         for (i = 0; i < tp->irq_cnt; i++) {
8923                 struct tg3_napi *tnapi = &tp->napi[i];
8924                 err = tg3_request_irq(tp, i);
8925                 if (err) {
8926                         for (i--; i >= 0; i--)
8927                                 free_irq(tnapi->irq_vec, tnapi);
8928                         break;
8929                 }
8930         }
8931
8932         if (err)
8933                 goto err_out2;
8934
8935         tg3_full_lock(tp, 0);
8936
8937         err = tg3_init_hw(tp, 1);
8938         if (err) {
8939                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8940                 tg3_free_rings(tp);
8941         } else {
8942                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8943                         tp->timer_offset = HZ;
8944                 else
8945                         tp->timer_offset = HZ / 10;
8946
8947                 BUG_ON(tp->timer_offset > HZ);
8948                 tp->timer_counter = tp->timer_multiplier =
8949                         (HZ / tp->timer_offset);
8950                 tp->asf_counter = tp->asf_multiplier =
8951                         ((HZ / tp->timer_offset) * 2);
8952
8953                 init_timer(&tp->timer);
8954                 tp->timer.expires = jiffies + tp->timer_offset;
8955                 tp->timer.data = (unsigned long) tp;
8956                 tp->timer.function = tg3_timer;
8957         }
8958
8959         tg3_full_unlock(tp);
8960
8961         if (err)
8962                 goto err_out3;
8963
8964         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8965                 err = tg3_test_msi(tp);
8966
8967                 if (err) {
8968                         tg3_full_lock(tp, 0);
8969                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8970                         tg3_free_rings(tp);
8971                         tg3_full_unlock(tp);
8972
8973                         goto err_out2;
8974                 }
8975
8976                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8977                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8978                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8979
8980                         tw32(PCIE_TRANSACTION_CFG,
8981                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8982                 }
8983         }
8984
8985         tg3_phy_start(tp);
8986
8987         tg3_full_lock(tp, 0);
8988
8989         add_timer(&tp->timer);
8990         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8991         tg3_enable_ints(tp);
8992
8993         tg3_full_unlock(tp);
8994
8995         netif_tx_start_all_queues(dev);
8996
8997         return 0;
8998
8999 err_out3:
9000         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9001                 struct tg3_napi *tnapi = &tp->napi[i];
9002                 free_irq(tnapi->irq_vec, tnapi);
9003         }
9004
9005 err_out2:
9006         tg3_napi_disable(tp);
9007         tg3_free_consistent(tp);
9008
9009 err_out1:
9010         tg3_ints_fini(tp);
9011         return err;
9012 }
9013
9014 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9015                                                  struct rtnl_link_stats64 *);
9016 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9017
9018 static int tg3_close(struct net_device *dev)
9019 {
9020         int i;
9021         struct tg3 *tp = netdev_priv(dev);
9022
9023         tg3_napi_disable(tp);
9024         cancel_work_sync(&tp->reset_task);
9025
9026         netif_tx_stop_all_queues(dev);
9027
9028         del_timer_sync(&tp->timer);
9029
9030         tg3_phy_stop(tp);
9031
9032         tg3_full_lock(tp, 1);
9033
9034         tg3_disable_ints(tp);
9035
9036         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9037         tg3_free_rings(tp);
9038         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9039
9040         tg3_full_unlock(tp);
9041
9042         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9043                 struct tg3_napi *tnapi = &tp->napi[i];
9044                 free_irq(tnapi->irq_vec, tnapi);
9045         }
9046
9047         tg3_ints_fini(tp);
9048
9049         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9050
9051         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9052                sizeof(tp->estats_prev));
9053
9054         tg3_free_consistent(tp);
9055
9056         tg3_set_power_state(tp, PCI_D3hot);
9057
9058         netif_carrier_off(tp->dev);
9059
9060         return 0;
9061 }
9062
9063 static inline u64 get_stat64(tg3_stat64_t *val)
9064 {
9065        return ((u64)val->high << 32) | ((u64)val->low);
9066 }
9067
9068 static u64 calc_crc_errors(struct tg3 *tp)
9069 {
9070         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9071
9072         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9073             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9074              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9075                 u32 val;
9076
9077                 spin_lock_bh(&tp->lock);
9078                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9079                         tg3_writephy(tp, MII_TG3_TEST1,
9080                                      val | MII_TG3_TEST1_CRC_EN);
9081                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9082                 } else
9083                         val = 0;
9084                 spin_unlock_bh(&tp->lock);
9085
9086                 tp->phy_crc_errors += val;
9087
9088                 return tp->phy_crc_errors;
9089         }
9090
9091         return get_stat64(&hw_stats->rx_fcs_errors);
9092 }
9093
9094 #define ESTAT_ADD(member) \
9095         estats->member =        old_estats->member + \
9096                                 get_stat64(&hw_stats->member)
9097
9098 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9099 {
9100         struct tg3_ethtool_stats *estats = &tp->estats;
9101         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9102         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9103
9104         if (!hw_stats)
9105                 return old_estats;
9106
9107         ESTAT_ADD(rx_octets);
9108         ESTAT_ADD(rx_fragments);
9109         ESTAT_ADD(rx_ucast_packets);
9110         ESTAT_ADD(rx_mcast_packets);
9111         ESTAT_ADD(rx_bcast_packets);
9112         ESTAT_ADD(rx_fcs_errors);
9113         ESTAT_ADD(rx_align_errors);
9114         ESTAT_ADD(rx_xon_pause_rcvd);
9115         ESTAT_ADD(rx_xoff_pause_rcvd);
9116         ESTAT_ADD(rx_mac_ctrl_rcvd);
9117         ESTAT_ADD(rx_xoff_entered);
9118         ESTAT_ADD(rx_frame_too_long_errors);
9119         ESTAT_ADD(rx_jabbers);
9120         ESTAT_ADD(rx_undersize_packets);
9121         ESTAT_ADD(rx_in_length_errors);
9122         ESTAT_ADD(rx_out_length_errors);
9123         ESTAT_ADD(rx_64_or_less_octet_packets);
9124         ESTAT_ADD(rx_65_to_127_octet_packets);
9125         ESTAT_ADD(rx_128_to_255_octet_packets);
9126         ESTAT_ADD(rx_256_to_511_octet_packets);
9127         ESTAT_ADD(rx_512_to_1023_octet_packets);
9128         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9129         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9130         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9131         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9132         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9133
9134         ESTAT_ADD(tx_octets);
9135         ESTAT_ADD(tx_collisions);
9136         ESTAT_ADD(tx_xon_sent);
9137         ESTAT_ADD(tx_xoff_sent);
9138         ESTAT_ADD(tx_flow_control);
9139         ESTAT_ADD(tx_mac_errors);
9140         ESTAT_ADD(tx_single_collisions);
9141         ESTAT_ADD(tx_mult_collisions);
9142         ESTAT_ADD(tx_deferred);
9143         ESTAT_ADD(tx_excessive_collisions);
9144         ESTAT_ADD(tx_late_collisions);
9145         ESTAT_ADD(tx_collide_2times);
9146         ESTAT_ADD(tx_collide_3times);
9147         ESTAT_ADD(tx_collide_4times);
9148         ESTAT_ADD(tx_collide_5times);
9149         ESTAT_ADD(tx_collide_6times);
9150         ESTAT_ADD(tx_collide_7times);
9151         ESTAT_ADD(tx_collide_8times);
9152         ESTAT_ADD(tx_collide_9times);
9153         ESTAT_ADD(tx_collide_10times);
9154         ESTAT_ADD(tx_collide_11times);
9155         ESTAT_ADD(tx_collide_12times);
9156         ESTAT_ADD(tx_collide_13times);
9157         ESTAT_ADD(tx_collide_14times);
9158         ESTAT_ADD(tx_collide_15times);
9159         ESTAT_ADD(tx_ucast_packets);
9160         ESTAT_ADD(tx_mcast_packets);
9161         ESTAT_ADD(tx_bcast_packets);
9162         ESTAT_ADD(tx_carrier_sense_errors);
9163         ESTAT_ADD(tx_discards);
9164         ESTAT_ADD(tx_errors);
9165
9166         ESTAT_ADD(dma_writeq_full);
9167         ESTAT_ADD(dma_write_prioq_full);
9168         ESTAT_ADD(rxbds_empty);
9169         ESTAT_ADD(rx_discards);
9170         ESTAT_ADD(rx_errors);
9171         ESTAT_ADD(rx_threshold_hit);
9172
9173         ESTAT_ADD(dma_readq_full);
9174         ESTAT_ADD(dma_read_prioq_full);
9175         ESTAT_ADD(tx_comp_queue_full);
9176
9177         ESTAT_ADD(ring_set_send_prod_index);
9178         ESTAT_ADD(ring_status_update);
9179         ESTAT_ADD(nic_irqs);
9180         ESTAT_ADD(nic_avoided_irqs);
9181         ESTAT_ADD(nic_tx_threshold_hit);
9182
9183         return estats;
9184 }
9185
9186 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9187                                                  struct rtnl_link_stats64 *stats)
9188 {
9189         struct tg3 *tp = netdev_priv(dev);
9190         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9191         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9192
9193         if (!hw_stats)
9194                 return old_stats;
9195
9196         stats->rx_packets = old_stats->rx_packets +
9197                 get_stat64(&hw_stats->rx_ucast_packets) +
9198                 get_stat64(&hw_stats->rx_mcast_packets) +
9199                 get_stat64(&hw_stats->rx_bcast_packets);
9200
9201         stats->tx_packets = old_stats->tx_packets +
9202                 get_stat64(&hw_stats->tx_ucast_packets) +
9203                 get_stat64(&hw_stats->tx_mcast_packets) +
9204                 get_stat64(&hw_stats->tx_bcast_packets);
9205
9206         stats->rx_bytes = old_stats->rx_bytes +
9207                 get_stat64(&hw_stats->rx_octets);
9208         stats->tx_bytes = old_stats->tx_bytes +
9209                 get_stat64(&hw_stats->tx_octets);
9210
9211         stats->rx_errors = old_stats->rx_errors +
9212                 get_stat64(&hw_stats->rx_errors);
9213         stats->tx_errors = old_stats->tx_errors +
9214                 get_stat64(&hw_stats->tx_errors) +
9215                 get_stat64(&hw_stats->tx_mac_errors) +
9216                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9217                 get_stat64(&hw_stats->tx_discards);
9218
9219         stats->multicast = old_stats->multicast +
9220                 get_stat64(&hw_stats->rx_mcast_packets);
9221         stats->collisions = old_stats->collisions +
9222                 get_stat64(&hw_stats->tx_collisions);
9223
9224         stats->rx_length_errors = old_stats->rx_length_errors +
9225                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9226                 get_stat64(&hw_stats->rx_undersize_packets);
9227
9228         stats->rx_over_errors = old_stats->rx_over_errors +
9229                 get_stat64(&hw_stats->rxbds_empty);
9230         stats->rx_frame_errors = old_stats->rx_frame_errors +
9231                 get_stat64(&hw_stats->rx_align_errors);
9232         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9233                 get_stat64(&hw_stats->tx_discards);
9234         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9235                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9236
9237         stats->rx_crc_errors = old_stats->rx_crc_errors +
9238                 calc_crc_errors(tp);
9239
9240         stats->rx_missed_errors = old_stats->rx_missed_errors +
9241                 get_stat64(&hw_stats->rx_discards);
9242
9243         stats->rx_dropped = tp->rx_dropped;
9244
9245         return stats;
9246 }
9247
9248 static inline u32 calc_crc(unsigned char *buf, int len)
9249 {
9250         u32 reg;
9251         u32 tmp;
9252         int j, k;
9253
9254         reg = 0xffffffff;
9255
9256         for (j = 0; j < len; j++) {
9257                 reg ^= buf[j];
9258
9259                 for (k = 0; k < 8; k++) {
9260                         tmp = reg & 0x01;
9261
9262                         reg >>= 1;
9263
9264                         if (tmp)
9265                                 reg ^= 0xedb88320;
9266                 }
9267         }
9268
9269         return ~reg;
9270 }
9271
9272 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9273 {
9274         /* accept or reject all multicast frames */
9275         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9276         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9277         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9278         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9279 }
9280
9281 static void __tg3_set_rx_mode(struct net_device *dev)
9282 {
9283         struct tg3 *tp = netdev_priv(dev);
9284         u32 rx_mode;
9285
9286         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9287                                   RX_MODE_KEEP_VLAN_TAG);
9288
9289         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9290          * flag clear.
9291          */
9292 #if TG3_VLAN_TAG_USED
9293         if (!tp->vlgrp &&
9294             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9295                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9296 #else
9297         /* By definition, VLAN is disabled always in this
9298          * case.
9299          */
9300         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9301                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9302 #endif
9303
9304         if (dev->flags & IFF_PROMISC) {
9305                 /* Promiscuous mode. */
9306                 rx_mode |= RX_MODE_PROMISC;
9307         } else if (dev->flags & IFF_ALLMULTI) {
9308                 /* Accept all multicast. */
9309                 tg3_set_multi(tp, 1);
9310         } else if (netdev_mc_empty(dev)) {
9311                 /* Reject all multicast. */
9312                 tg3_set_multi(tp, 0);
9313         } else {
9314                 /* Accept one or more multicast(s). */
9315                 struct netdev_hw_addr *ha;
9316                 u32 mc_filter[4] = { 0, };
9317                 u32 regidx;
9318                 u32 bit;
9319                 u32 crc;
9320
9321                 netdev_for_each_mc_addr(ha, dev) {
9322                         crc = calc_crc(ha->addr, ETH_ALEN);
9323                         bit = ~crc & 0x7f;
9324                         regidx = (bit & 0x60) >> 5;
9325                         bit &= 0x1f;
9326                         mc_filter[regidx] |= (1 << bit);
9327                 }
9328
9329                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9330                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9331                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9332                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9333         }
9334
9335         if (rx_mode != tp->rx_mode) {
9336                 tp->rx_mode = rx_mode;
9337                 tw32_f(MAC_RX_MODE, rx_mode);
9338                 udelay(10);
9339         }
9340 }
9341
9342 static void tg3_set_rx_mode(struct net_device *dev)
9343 {
9344         struct tg3 *tp = netdev_priv(dev);
9345
9346         if (!netif_running(dev))
9347                 return;
9348
9349         tg3_full_lock(tp, 0);
9350         __tg3_set_rx_mode(dev);
9351         tg3_full_unlock(tp);
9352 }
9353
9354 #define TG3_REGDUMP_LEN         (32 * 1024)
9355
9356 static int tg3_get_regs_len(struct net_device *dev)
9357 {
9358         return TG3_REGDUMP_LEN;
9359 }
9360
9361 static void tg3_get_regs(struct net_device *dev,
9362                 struct ethtool_regs *regs, void *_p)
9363 {
9364         u32 *p = _p;
9365         struct tg3 *tp = netdev_priv(dev);
9366         u8 *orig_p = _p;
9367         int i;
9368
9369         regs->version = 0;
9370
9371         memset(p, 0, TG3_REGDUMP_LEN);
9372
9373         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9374                 return;
9375
9376         tg3_full_lock(tp, 0);
9377
9378 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9379 #define GET_REG32_LOOP(base, len)               \
9380 do {    p = (u32 *)(orig_p + (base));           \
9381         for (i = 0; i < len; i += 4)            \
9382                 __GET_REG32((base) + i);        \
9383 } while (0)
9384 #define GET_REG32_1(reg)                        \
9385 do {    p = (u32 *)(orig_p + (reg));            \
9386         __GET_REG32((reg));                     \
9387 } while (0)
9388
9389         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9390         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9391         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9392         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9393         GET_REG32_1(SNDDATAC_MODE);
9394         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9395         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9396         GET_REG32_1(SNDBDC_MODE);
9397         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9398         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9399         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9400         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9401         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9402         GET_REG32_1(RCVDCC_MODE);
9403         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9404         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9405         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9406         GET_REG32_1(MBFREE_MODE);
9407         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9408         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9409         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9410         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9411         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9412         GET_REG32_1(RX_CPU_MODE);
9413         GET_REG32_1(RX_CPU_STATE);
9414         GET_REG32_1(RX_CPU_PGMCTR);
9415         GET_REG32_1(RX_CPU_HWBKPT);
9416         GET_REG32_1(TX_CPU_MODE);
9417         GET_REG32_1(TX_CPU_STATE);
9418         GET_REG32_1(TX_CPU_PGMCTR);
9419         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9420         GET_REG32_LOOP(FTQ_RESET, 0x120);
9421         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9422         GET_REG32_1(DMAC_MODE);
9423         GET_REG32_LOOP(GRC_MODE, 0x4c);
9424         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9425                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9426
9427 #undef __GET_REG32
9428 #undef GET_REG32_LOOP
9429 #undef GET_REG32_1
9430
9431         tg3_full_unlock(tp);
9432 }
9433
9434 static int tg3_get_eeprom_len(struct net_device *dev)
9435 {
9436         struct tg3 *tp = netdev_priv(dev);
9437
9438         return tp->nvram_size;
9439 }
9440
9441 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9442 {
9443         struct tg3 *tp = netdev_priv(dev);
9444         int ret;
9445         u8  *pd;
9446         u32 i, offset, len, b_offset, b_count;
9447         __be32 val;
9448
9449         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9450                 return -EINVAL;
9451
9452         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9453                 return -EAGAIN;
9454
9455         offset = eeprom->offset;
9456         len = eeprom->len;
9457         eeprom->len = 0;
9458
9459         eeprom->magic = TG3_EEPROM_MAGIC;
9460
9461         if (offset & 3) {
9462                 /* adjustments to start on required 4 byte boundary */
9463                 b_offset = offset & 3;
9464                 b_count = 4 - b_offset;
9465                 if (b_count > len) {
9466                         /* i.e. offset=1 len=2 */
9467                         b_count = len;
9468                 }
9469                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9470                 if (ret)
9471                         return ret;
9472                 memcpy(data, ((char *)&val) + b_offset, b_count);
9473                 len -= b_count;
9474                 offset += b_count;
9475                 eeprom->len += b_count;
9476         }
9477
9478         /* read bytes upto the last 4 byte boundary */
9479         pd = &data[eeprom->len];
9480         for (i = 0; i < (len - (len & 3)); i += 4) {
9481                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9482                 if (ret) {
9483                         eeprom->len += i;
9484                         return ret;
9485                 }
9486                 memcpy(pd + i, &val, 4);
9487         }
9488         eeprom->len += i;
9489
9490         if (len & 3) {
9491                 /* read last bytes not ending on 4 byte boundary */
9492                 pd = &data[eeprom->len];
9493                 b_count = len & 3;
9494                 b_offset = offset + len - b_count;
9495                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9496                 if (ret)
9497                         return ret;
9498                 memcpy(pd, &val, b_count);
9499                 eeprom->len += b_count;
9500         }
9501         return 0;
9502 }
9503
9504 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9505
9506 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9507 {
9508         struct tg3 *tp = netdev_priv(dev);
9509         int ret;
9510         u32 offset, len, b_offset, odd_len;
9511         u8 *buf;
9512         __be32 start, end;
9513
9514         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9515                 return -EAGAIN;
9516
9517         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9518             eeprom->magic != TG3_EEPROM_MAGIC)
9519                 return -EINVAL;
9520
9521         offset = eeprom->offset;
9522         len = eeprom->len;
9523
9524         if ((b_offset = (offset & 3))) {
9525                 /* adjustments to start on required 4 byte boundary */
9526                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9527                 if (ret)
9528                         return ret;
9529                 len += b_offset;
9530                 offset &= ~3;
9531                 if (len < 4)
9532                         len = 4;
9533         }
9534
9535         odd_len = 0;
9536         if (len & 3) {
9537                 /* adjustments to end on required 4 byte boundary */
9538                 odd_len = 1;
9539                 len = (len + 3) & ~3;
9540                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9541                 if (ret)
9542                         return ret;
9543         }
9544
9545         buf = data;
9546         if (b_offset || odd_len) {
9547                 buf = kmalloc(len, GFP_KERNEL);
9548                 if (!buf)
9549                         return -ENOMEM;
9550                 if (b_offset)
9551                         memcpy(buf, &start, 4);
9552                 if (odd_len)
9553                         memcpy(buf+len-4, &end, 4);
9554                 memcpy(buf + b_offset, data, eeprom->len);
9555         }
9556
9557         ret = tg3_nvram_write_block(tp, offset, len, buf);
9558
9559         if (buf != data)
9560                 kfree(buf);
9561
9562         return ret;
9563 }
9564
9565 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9566 {
9567         struct tg3 *tp = netdev_priv(dev);
9568
9569         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9570                 struct phy_device *phydev;
9571                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9572                         return -EAGAIN;
9573                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9574                 return phy_ethtool_gset(phydev, cmd);
9575         }
9576
9577         cmd->supported = (SUPPORTED_Autoneg);
9578
9579         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9580                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9581                                    SUPPORTED_1000baseT_Full);
9582
9583         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9584                 cmd->supported |= (SUPPORTED_100baseT_Half |
9585                                   SUPPORTED_100baseT_Full |
9586                                   SUPPORTED_10baseT_Half |
9587                                   SUPPORTED_10baseT_Full |
9588                                   SUPPORTED_TP);
9589                 cmd->port = PORT_TP;
9590         } else {
9591                 cmd->supported |= SUPPORTED_FIBRE;
9592                 cmd->port = PORT_FIBRE;
9593         }
9594
9595         cmd->advertising = tp->link_config.advertising;
9596         if (netif_running(dev)) {
9597                 cmd->speed = tp->link_config.active_speed;
9598                 cmd->duplex = tp->link_config.active_duplex;
9599         }
9600         cmd->phy_address = tp->phy_addr;
9601         cmd->transceiver = XCVR_INTERNAL;
9602         cmd->autoneg = tp->link_config.autoneg;
9603         cmd->maxtxpkt = 0;
9604         cmd->maxrxpkt = 0;
9605         return 0;
9606 }
9607
9608 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9609 {
9610         struct tg3 *tp = netdev_priv(dev);
9611
9612         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9613                 struct phy_device *phydev;
9614                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9615                         return -EAGAIN;
9616                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9617                 return phy_ethtool_sset(phydev, cmd);
9618         }
9619
9620         if (cmd->autoneg != AUTONEG_ENABLE &&
9621             cmd->autoneg != AUTONEG_DISABLE)
9622                 return -EINVAL;
9623
9624         if (cmd->autoneg == AUTONEG_DISABLE &&
9625             cmd->duplex != DUPLEX_FULL &&
9626             cmd->duplex != DUPLEX_HALF)
9627                 return -EINVAL;
9628
9629         if (cmd->autoneg == AUTONEG_ENABLE) {
9630                 u32 mask = ADVERTISED_Autoneg |
9631                            ADVERTISED_Pause |
9632                            ADVERTISED_Asym_Pause;
9633
9634                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9635                         mask |= ADVERTISED_1000baseT_Half |
9636                                 ADVERTISED_1000baseT_Full;
9637
9638                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9639                         mask |= ADVERTISED_100baseT_Half |
9640                                 ADVERTISED_100baseT_Full |
9641                                 ADVERTISED_10baseT_Half |
9642                                 ADVERTISED_10baseT_Full |
9643                                 ADVERTISED_TP;
9644                 else
9645                         mask |= ADVERTISED_FIBRE;
9646
9647                 if (cmd->advertising & ~mask)
9648                         return -EINVAL;
9649
9650                 mask &= (ADVERTISED_1000baseT_Half |
9651                          ADVERTISED_1000baseT_Full |
9652                          ADVERTISED_100baseT_Half |
9653                          ADVERTISED_100baseT_Full |
9654                          ADVERTISED_10baseT_Half |
9655                          ADVERTISED_10baseT_Full);
9656
9657                 cmd->advertising &= mask;
9658         } else {
9659                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9660                         if (cmd->speed != SPEED_1000)
9661                                 return -EINVAL;
9662
9663                         if (cmd->duplex != DUPLEX_FULL)
9664                                 return -EINVAL;
9665                 } else {
9666                         if (cmd->speed != SPEED_100 &&
9667                             cmd->speed != SPEED_10)
9668                                 return -EINVAL;
9669                 }
9670         }
9671
9672         tg3_full_lock(tp, 0);
9673
9674         tp->link_config.autoneg = cmd->autoneg;
9675         if (cmd->autoneg == AUTONEG_ENABLE) {
9676                 tp->link_config.advertising = (cmd->advertising |
9677                                               ADVERTISED_Autoneg);
9678                 tp->link_config.speed = SPEED_INVALID;
9679                 tp->link_config.duplex = DUPLEX_INVALID;
9680         } else {
9681                 tp->link_config.advertising = 0;
9682                 tp->link_config.speed = cmd->speed;
9683                 tp->link_config.duplex = cmd->duplex;
9684         }
9685
9686         tp->link_config.orig_speed = tp->link_config.speed;
9687         tp->link_config.orig_duplex = tp->link_config.duplex;
9688         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9689
9690         if (netif_running(dev))
9691                 tg3_setup_phy(tp, 1);
9692
9693         tg3_full_unlock(tp);
9694
9695         return 0;
9696 }
9697
9698 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9699 {
9700         struct tg3 *tp = netdev_priv(dev);
9701
9702         strcpy(info->driver, DRV_MODULE_NAME);
9703         strcpy(info->version, DRV_MODULE_VERSION);
9704         strcpy(info->fw_version, tp->fw_ver);
9705         strcpy(info->bus_info, pci_name(tp->pdev));
9706 }
9707
9708 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9709 {
9710         struct tg3 *tp = netdev_priv(dev);
9711
9712         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9713             device_can_wakeup(&tp->pdev->dev))
9714                 wol->supported = WAKE_MAGIC;
9715         else
9716                 wol->supported = 0;
9717         wol->wolopts = 0;
9718         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9719             device_can_wakeup(&tp->pdev->dev))
9720                 wol->wolopts = WAKE_MAGIC;
9721         memset(&wol->sopass, 0, sizeof(wol->sopass));
9722 }
9723
9724 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9725 {
9726         struct tg3 *tp = netdev_priv(dev);
9727         struct device *dp = &tp->pdev->dev;
9728
9729         if (wol->wolopts & ~WAKE_MAGIC)
9730                 return -EINVAL;
9731         if ((wol->wolopts & WAKE_MAGIC) &&
9732             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9733                 return -EINVAL;
9734
9735         spin_lock_bh(&tp->lock);
9736         if (wol->wolopts & WAKE_MAGIC) {
9737                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9738                 device_set_wakeup_enable(dp, true);
9739         } else {
9740                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9741                 device_set_wakeup_enable(dp, false);
9742         }
9743         spin_unlock_bh(&tp->lock);
9744
9745         return 0;
9746 }
9747
9748 static u32 tg3_get_msglevel(struct net_device *dev)
9749 {
9750         struct tg3 *tp = netdev_priv(dev);
9751         return tp->msg_enable;
9752 }
9753
9754 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9755 {
9756         struct tg3 *tp = netdev_priv(dev);
9757         tp->msg_enable = value;
9758 }
9759
9760 static int tg3_set_tso(struct net_device *dev, u32 value)
9761 {
9762         struct tg3 *tp = netdev_priv(dev);
9763
9764         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9765                 if (value)
9766                         return -EINVAL;
9767                 return 0;
9768         }
9769         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9770             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9771              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9772                 if (value) {
9773                         dev->features |= NETIF_F_TSO6;
9774                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9775                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9776                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9777                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9778                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9779                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9780                                 dev->features |= NETIF_F_TSO_ECN;
9781                 } else
9782                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9783         }
9784         return ethtool_op_set_tso(dev, value);
9785 }
9786
9787 static int tg3_nway_reset(struct net_device *dev)
9788 {
9789         struct tg3 *tp = netdev_priv(dev);
9790         int r;
9791
9792         if (!netif_running(dev))
9793                 return -EAGAIN;
9794
9795         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9796                 return -EINVAL;
9797
9798         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9799                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9800                         return -EAGAIN;
9801                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9802         } else {
9803                 u32 bmcr;
9804
9805                 spin_lock_bh(&tp->lock);
9806                 r = -EINVAL;
9807                 tg3_readphy(tp, MII_BMCR, &bmcr);
9808                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9809                     ((bmcr & BMCR_ANENABLE) ||
9810                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9811                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9812                                                    BMCR_ANENABLE);
9813                         r = 0;
9814                 }
9815                 spin_unlock_bh(&tp->lock);
9816         }
9817
9818         return r;
9819 }
9820
9821 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9822 {
9823         struct tg3 *tp = netdev_priv(dev);
9824
9825         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9826         ering->rx_mini_max_pending = 0;
9827         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9828                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9829         else
9830                 ering->rx_jumbo_max_pending = 0;
9831
9832         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9833
9834         ering->rx_pending = tp->rx_pending;
9835         ering->rx_mini_pending = 0;
9836         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9837                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9838         else
9839                 ering->rx_jumbo_pending = 0;
9840
9841         ering->tx_pending = tp->napi[0].tx_pending;
9842 }
9843
9844 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9845 {
9846         struct tg3 *tp = netdev_priv(dev);
9847         int i, irq_sync = 0, err = 0;
9848
9849         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9850             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9851             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9852             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9853             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9854              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9855                 return -EINVAL;
9856
9857         if (netif_running(dev)) {
9858                 tg3_phy_stop(tp);
9859                 tg3_netif_stop(tp);
9860                 irq_sync = 1;
9861         }
9862
9863         tg3_full_lock(tp, irq_sync);
9864
9865         tp->rx_pending = ering->rx_pending;
9866
9867         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9868             tp->rx_pending > 63)
9869                 tp->rx_pending = 63;
9870         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9871
9872         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9873                 tp->napi[i].tx_pending = ering->tx_pending;
9874
9875         if (netif_running(dev)) {
9876                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9877                 err = tg3_restart_hw(tp, 1);
9878                 if (!err)
9879                         tg3_netif_start(tp);
9880         }
9881
9882         tg3_full_unlock(tp);
9883
9884         if (irq_sync && !err)
9885                 tg3_phy_start(tp);
9886
9887         return err;
9888 }
9889
9890 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9891 {
9892         struct tg3 *tp = netdev_priv(dev);
9893
9894         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9895
9896         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9897                 epause->rx_pause = 1;
9898         else
9899                 epause->rx_pause = 0;
9900
9901         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9902                 epause->tx_pause = 1;
9903         else
9904                 epause->tx_pause = 0;
9905 }
9906
9907 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9908 {
9909         struct tg3 *tp = netdev_priv(dev);
9910         int err = 0;
9911
9912         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9913                 u32 newadv;
9914                 struct phy_device *phydev;
9915
9916                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9917
9918                 if (!(phydev->supported & SUPPORTED_Pause) ||
9919                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9920                      ((epause->rx_pause && !epause->tx_pause) ||
9921                       (!epause->rx_pause && epause->tx_pause))))
9922                         return -EINVAL;
9923
9924                 tp->link_config.flowctrl = 0;
9925                 if (epause->rx_pause) {
9926                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9927
9928                         if (epause->tx_pause) {
9929                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9930                                 newadv = ADVERTISED_Pause;
9931                         } else
9932                                 newadv = ADVERTISED_Pause |
9933                                          ADVERTISED_Asym_Pause;
9934                 } else if (epause->tx_pause) {
9935                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9936                         newadv = ADVERTISED_Asym_Pause;
9937                 } else
9938                         newadv = 0;
9939
9940                 if (epause->autoneg)
9941                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9942                 else
9943                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9944
9945                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9946                         u32 oldadv = phydev->advertising &
9947                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9948                         if (oldadv != newadv) {
9949                                 phydev->advertising &=
9950                                         ~(ADVERTISED_Pause |
9951                                           ADVERTISED_Asym_Pause);
9952                                 phydev->advertising |= newadv;
9953                                 if (phydev->autoneg) {
9954                                         /*
9955                                          * Always renegotiate the link to
9956                                          * inform our link partner of our
9957                                          * flow control settings, even if the
9958                                          * flow control is forced.  Let
9959                                          * tg3_adjust_link() do the final
9960                                          * flow control setup.
9961                                          */
9962                                         return phy_start_aneg(phydev);
9963                                 }
9964                         }
9965
9966                         if (!epause->autoneg)
9967                                 tg3_setup_flow_control(tp, 0, 0);
9968                 } else {
9969                         tp->link_config.orig_advertising &=
9970                                         ~(ADVERTISED_Pause |
9971                                           ADVERTISED_Asym_Pause);
9972                         tp->link_config.orig_advertising |= newadv;
9973                 }
9974         } else {
9975                 int irq_sync = 0;
9976
9977                 if (netif_running(dev)) {
9978                         tg3_netif_stop(tp);
9979                         irq_sync = 1;
9980                 }
9981
9982                 tg3_full_lock(tp, irq_sync);
9983
9984                 if (epause->autoneg)
9985                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9986                 else
9987                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9988                 if (epause->rx_pause)
9989                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9990                 else
9991                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9992                 if (epause->tx_pause)
9993                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9994                 else
9995                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9996
9997                 if (netif_running(dev)) {
9998                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9999                         err = tg3_restart_hw(tp, 1);
10000                         if (!err)
10001                                 tg3_netif_start(tp);
10002                 }
10003
10004                 tg3_full_unlock(tp);
10005         }
10006
10007         return err;
10008 }
10009
10010 static u32 tg3_get_rx_csum(struct net_device *dev)
10011 {
10012         struct tg3 *tp = netdev_priv(dev);
10013         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10014 }
10015
10016 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10017 {
10018         struct tg3 *tp = netdev_priv(dev);
10019
10020         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10021                 if (data != 0)
10022                         return -EINVAL;
10023                 return 0;
10024         }
10025
10026         spin_lock_bh(&tp->lock);
10027         if (data)
10028                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10029         else
10030                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10031         spin_unlock_bh(&tp->lock);
10032
10033         return 0;
10034 }
10035
10036 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10037 {
10038         struct tg3 *tp = netdev_priv(dev);
10039
10040         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10041                 if (data != 0)
10042                         return -EINVAL;
10043                 return 0;
10044         }
10045
10046         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10047                 ethtool_op_set_tx_ipv6_csum(dev, data);
10048         else
10049                 ethtool_op_set_tx_csum(dev, data);
10050
10051         return 0;
10052 }
10053
10054 static int tg3_get_sset_count(struct net_device *dev, int sset)
10055 {
10056         switch (sset) {
10057         case ETH_SS_TEST:
10058                 return TG3_NUM_TEST;
10059         case ETH_SS_STATS:
10060                 return TG3_NUM_STATS;
10061         default:
10062                 return -EOPNOTSUPP;
10063         }
10064 }
10065
10066 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10067 {
10068         switch (stringset) {
10069         case ETH_SS_STATS:
10070                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10071                 break;
10072         case ETH_SS_TEST:
10073                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10074                 break;
10075         default:
10076                 WARN_ON(1);     /* we need a WARN() */
10077                 break;
10078         }
10079 }
10080
10081 static int tg3_phys_id(struct net_device *dev, u32 data)
10082 {
10083         struct tg3 *tp = netdev_priv(dev);
10084         int i;
10085
10086         if (!netif_running(tp->dev))
10087                 return -EAGAIN;
10088
10089         if (data == 0)
10090                 data = UINT_MAX / 2;
10091
10092         for (i = 0; i < (data * 2); i++) {
10093                 if ((i % 2) == 0)
10094                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10095                                            LED_CTRL_1000MBPS_ON |
10096                                            LED_CTRL_100MBPS_ON |
10097                                            LED_CTRL_10MBPS_ON |
10098                                            LED_CTRL_TRAFFIC_OVERRIDE |
10099                                            LED_CTRL_TRAFFIC_BLINK |
10100                                            LED_CTRL_TRAFFIC_LED);
10101
10102                 else
10103                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10104                                            LED_CTRL_TRAFFIC_OVERRIDE);
10105
10106                 if (msleep_interruptible(500))
10107                         break;
10108         }
10109         tw32(MAC_LED_CTRL, tp->led_ctrl);
10110         return 0;
10111 }
10112
10113 static void tg3_get_ethtool_stats(struct net_device *dev,
10114                                    struct ethtool_stats *estats, u64 *tmp_stats)
10115 {
10116         struct tg3 *tp = netdev_priv(dev);
10117         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10118 }
10119
10120 #define NVRAM_TEST_SIZE 0x100
10121 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10122 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10123 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10124 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10125 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10126
10127 static int tg3_test_nvram(struct tg3 *tp)
10128 {
10129         u32 csum, magic;
10130         __be32 *buf;
10131         int i, j, k, err = 0, size;
10132
10133         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10134                 return 0;
10135
10136         if (tg3_nvram_read(tp, 0, &magic) != 0)
10137                 return -EIO;
10138
10139         if (magic == TG3_EEPROM_MAGIC)
10140                 size = NVRAM_TEST_SIZE;
10141         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10142                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10143                     TG3_EEPROM_SB_FORMAT_1) {
10144                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10145                         case TG3_EEPROM_SB_REVISION_0:
10146                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10147                                 break;
10148                         case TG3_EEPROM_SB_REVISION_2:
10149                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10150                                 break;
10151                         case TG3_EEPROM_SB_REVISION_3:
10152                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10153                                 break;
10154                         default:
10155                                 return 0;
10156                         }
10157                 } else
10158                         return 0;
10159         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10160                 size = NVRAM_SELFBOOT_HW_SIZE;
10161         else
10162                 return -EIO;
10163
10164         buf = kmalloc(size, GFP_KERNEL);
10165         if (buf == NULL)
10166                 return -ENOMEM;
10167
10168         err = -EIO;
10169         for (i = 0, j = 0; i < size; i += 4, j++) {
10170                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10171                 if (err)
10172                         break;
10173         }
10174         if (i < size)
10175                 goto out;
10176
10177         /* Selfboot format */
10178         magic = be32_to_cpu(buf[0]);
10179         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10180             TG3_EEPROM_MAGIC_FW) {
10181                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10182
10183                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10184                     TG3_EEPROM_SB_REVISION_2) {
10185                         /* For rev 2, the csum doesn't include the MBA. */
10186                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10187                                 csum8 += buf8[i];
10188                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10189                                 csum8 += buf8[i];
10190                 } else {
10191                         for (i = 0; i < size; i++)
10192                                 csum8 += buf8[i];
10193                 }
10194
10195                 if (csum8 == 0) {
10196                         err = 0;
10197                         goto out;
10198                 }
10199
10200                 err = -EIO;
10201                 goto out;
10202         }
10203
10204         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10205             TG3_EEPROM_MAGIC_HW) {
10206                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10207                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10208                 u8 *buf8 = (u8 *) buf;
10209
10210                 /* Separate the parity bits and the data bytes.  */
10211                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10212                         if ((i == 0) || (i == 8)) {
10213                                 int l;
10214                                 u8 msk;
10215
10216                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10217                                         parity[k++] = buf8[i] & msk;
10218                                 i++;
10219                         } else if (i == 16) {
10220                                 int l;
10221                                 u8 msk;
10222
10223                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10224                                         parity[k++] = buf8[i] & msk;
10225                                 i++;
10226
10227                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10228                                         parity[k++] = buf8[i] & msk;
10229                                 i++;
10230                         }
10231                         data[j++] = buf8[i];
10232                 }
10233
10234                 err = -EIO;
10235                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10236                         u8 hw8 = hweight8(data[i]);
10237
10238                         if ((hw8 & 0x1) && parity[i])
10239                                 goto out;
10240                         else if (!(hw8 & 0x1) && !parity[i])
10241                                 goto out;
10242                 }
10243                 err = 0;
10244                 goto out;
10245         }
10246
10247         /* Bootstrap checksum at offset 0x10 */
10248         csum = calc_crc((unsigned char *) buf, 0x10);
10249         if (csum != be32_to_cpu(buf[0x10/4]))
10250                 goto out;
10251
10252         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10253         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10254         if (csum != be32_to_cpu(buf[0xfc/4]))
10255                 goto out;
10256
10257         err = 0;
10258
10259 out:
10260         kfree(buf);
10261         return err;
10262 }
10263
10264 #define TG3_SERDES_TIMEOUT_SEC  2
10265 #define TG3_COPPER_TIMEOUT_SEC  6
10266
10267 static int tg3_test_link(struct tg3 *tp)
10268 {
10269         int i, max;
10270
10271         if (!netif_running(tp->dev))
10272                 return -ENODEV;
10273
10274         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10275                 max = TG3_SERDES_TIMEOUT_SEC;
10276         else
10277                 max = TG3_COPPER_TIMEOUT_SEC;
10278
10279         for (i = 0; i < max; i++) {
10280                 if (netif_carrier_ok(tp->dev))
10281                         return 0;
10282
10283                 if (msleep_interruptible(1000))
10284                         break;
10285         }
10286
10287         return -EIO;
10288 }
10289
10290 /* Only test the commonly used registers */
10291 static int tg3_test_registers(struct tg3 *tp)
10292 {
10293         int i, is_5705, is_5750;
10294         u32 offset, read_mask, write_mask, val, save_val, read_val;
10295         static struct {
10296                 u16 offset;
10297                 u16 flags;
10298 #define TG3_FL_5705     0x1
10299 #define TG3_FL_NOT_5705 0x2
10300 #define TG3_FL_NOT_5788 0x4
10301 #define TG3_FL_NOT_5750 0x8
10302                 u32 read_mask;
10303                 u32 write_mask;
10304         } reg_tbl[] = {
10305                 /* MAC Control Registers */
10306                 { MAC_MODE, TG3_FL_NOT_5705,
10307                         0x00000000, 0x00ef6f8c },
10308                 { MAC_MODE, TG3_FL_5705,
10309                         0x00000000, 0x01ef6b8c },
10310                 { MAC_STATUS, TG3_FL_NOT_5705,
10311                         0x03800107, 0x00000000 },
10312                 { MAC_STATUS, TG3_FL_5705,
10313                         0x03800100, 0x00000000 },
10314                 { MAC_ADDR_0_HIGH, 0x0000,
10315                         0x00000000, 0x0000ffff },
10316                 { MAC_ADDR_0_LOW, 0x0000,
10317                         0x00000000, 0xffffffff },
10318                 { MAC_RX_MTU_SIZE, 0x0000,
10319                         0x00000000, 0x0000ffff },
10320                 { MAC_TX_MODE, 0x0000,
10321                         0x00000000, 0x00000070 },
10322                 { MAC_TX_LENGTHS, 0x0000,
10323                         0x00000000, 0x00003fff },
10324                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10325                         0x00000000, 0x000007fc },
10326                 { MAC_RX_MODE, TG3_FL_5705,
10327                         0x00000000, 0x000007dc },
10328                 { MAC_HASH_REG_0, 0x0000,
10329                         0x00000000, 0xffffffff },
10330                 { MAC_HASH_REG_1, 0x0000,
10331                         0x00000000, 0xffffffff },
10332                 { MAC_HASH_REG_2, 0x0000,
10333                         0x00000000, 0xffffffff },
10334                 { MAC_HASH_REG_3, 0x0000,
10335                         0x00000000, 0xffffffff },
10336
10337                 /* Receive Data and Receive BD Initiator Control Registers. */
10338                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10339                         0x00000000, 0xffffffff },
10340                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10341                         0x00000000, 0xffffffff },
10342                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10343                         0x00000000, 0x00000003 },
10344                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10345                         0x00000000, 0xffffffff },
10346                 { RCVDBDI_STD_BD+0, 0x0000,
10347                         0x00000000, 0xffffffff },
10348                 { RCVDBDI_STD_BD+4, 0x0000,
10349                         0x00000000, 0xffffffff },
10350                 { RCVDBDI_STD_BD+8, 0x0000,
10351                         0x00000000, 0xffff0002 },
10352                 { RCVDBDI_STD_BD+0xc, 0x0000,
10353                         0x00000000, 0xffffffff },
10354
10355                 /* Receive BD Initiator Control Registers. */
10356                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10357                         0x00000000, 0xffffffff },
10358                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10359                         0x00000000, 0x000003ff },
10360                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10361                         0x00000000, 0xffffffff },
10362
10363                 /* Host Coalescing Control Registers. */
10364                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10365                         0x00000000, 0x00000004 },
10366                 { HOSTCC_MODE, TG3_FL_5705,
10367                         0x00000000, 0x000000f6 },
10368                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10369                         0x00000000, 0xffffffff },
10370                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10371                         0x00000000, 0x000003ff },
10372                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10373                         0x00000000, 0xffffffff },
10374                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10375                         0x00000000, 0x000003ff },
10376                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10377                         0x00000000, 0xffffffff },
10378                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10379                         0x00000000, 0x000000ff },
10380                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10381                         0x00000000, 0xffffffff },
10382                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10383                         0x00000000, 0x000000ff },
10384                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10385                         0x00000000, 0xffffffff },
10386                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10387                         0x00000000, 0xffffffff },
10388                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10389                         0x00000000, 0xffffffff },
10390                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10391                         0x00000000, 0x000000ff },
10392                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10393                         0x00000000, 0xffffffff },
10394                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10395                         0x00000000, 0x000000ff },
10396                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10397                         0x00000000, 0xffffffff },
10398                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10399                         0x00000000, 0xffffffff },
10400                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10401                         0x00000000, 0xffffffff },
10402                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10403                         0x00000000, 0xffffffff },
10404                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10405                         0x00000000, 0xffffffff },
10406                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10407                         0xffffffff, 0x00000000 },
10408                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10409                         0xffffffff, 0x00000000 },
10410
10411                 /* Buffer Manager Control Registers. */
10412                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10413                         0x00000000, 0x007fff80 },
10414                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10415                         0x00000000, 0x007fffff },
10416                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10417                         0x00000000, 0x0000003f },
10418                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10419                         0x00000000, 0x000001ff },
10420                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10421                         0x00000000, 0x000001ff },
10422                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10423                         0xffffffff, 0x00000000 },
10424                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10425                         0xffffffff, 0x00000000 },
10426
10427                 /* Mailbox Registers */
10428                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10429                         0x00000000, 0x000001ff },
10430                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10431                         0x00000000, 0x000001ff },
10432                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10433                         0x00000000, 0x000007ff },
10434                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10435                         0x00000000, 0x000001ff },
10436
10437                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10438         };
10439
10440         is_5705 = is_5750 = 0;
10441         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10442                 is_5705 = 1;
10443                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10444                         is_5750 = 1;
10445         }
10446
10447         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10448                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10449                         continue;
10450
10451                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10452                         continue;
10453
10454                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10455                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10456                         continue;
10457
10458                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10459                         continue;
10460
10461                 offset = (u32) reg_tbl[i].offset;
10462                 read_mask = reg_tbl[i].read_mask;
10463                 write_mask = reg_tbl[i].write_mask;
10464
10465                 /* Save the original register content */
10466                 save_val = tr32(offset);
10467
10468                 /* Determine the read-only value. */
10469                 read_val = save_val & read_mask;
10470
10471                 /* Write zero to the register, then make sure the read-only bits
10472                  * are not changed and the read/write bits are all zeros.
10473                  */
10474                 tw32(offset, 0);
10475
10476                 val = tr32(offset);
10477
10478                 /* Test the read-only and read/write bits. */
10479                 if (((val & read_mask) != read_val) || (val & write_mask))
10480                         goto out;
10481
10482                 /* Write ones to all the bits defined by RdMask and WrMask, then
10483                  * make sure the read-only bits are not changed and the
10484                  * read/write bits are all ones.
10485                  */
10486                 tw32(offset, read_mask | write_mask);
10487
10488                 val = tr32(offset);
10489
10490                 /* Test the read-only bits. */
10491                 if ((val & read_mask) != read_val)
10492                         goto out;
10493
10494                 /* Test the read/write bits. */
10495                 if ((val & write_mask) != write_mask)
10496                         goto out;
10497
10498                 tw32(offset, save_val);
10499         }
10500
10501         return 0;
10502
10503 out:
10504         if (netif_msg_hw(tp))
10505                 netdev_err(tp->dev,
10506                            "Register test failed at offset %x\n", offset);
10507         tw32(offset, save_val);
10508         return -EIO;
10509 }
10510
10511 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10512 {
10513         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10514         int i;
10515         u32 j;
10516
10517         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10518                 for (j = 0; j < len; j += 4) {
10519                         u32 val;
10520
10521                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10522                         tg3_read_mem(tp, offset + j, &val);
10523                         if (val != test_pattern[i])
10524                                 return -EIO;
10525                 }
10526         }
10527         return 0;
10528 }
10529
10530 static int tg3_test_memory(struct tg3 *tp)
10531 {
10532         static struct mem_entry {
10533                 u32 offset;
10534                 u32 len;
10535         } mem_tbl_570x[] = {
10536                 { 0x00000000, 0x00b50},
10537                 { 0x00002000, 0x1c000},
10538                 { 0xffffffff, 0x00000}
10539         }, mem_tbl_5705[] = {
10540                 { 0x00000100, 0x0000c},
10541                 { 0x00000200, 0x00008},
10542                 { 0x00004000, 0x00800},
10543                 { 0x00006000, 0x01000},
10544                 { 0x00008000, 0x02000},
10545                 { 0x00010000, 0x0e000},
10546                 { 0xffffffff, 0x00000}
10547         }, mem_tbl_5755[] = {
10548                 { 0x00000200, 0x00008},
10549                 { 0x00004000, 0x00800},
10550                 { 0x00006000, 0x00800},
10551                 { 0x00008000, 0x02000},
10552                 { 0x00010000, 0x0c000},
10553                 { 0xffffffff, 0x00000}
10554         }, mem_tbl_5906[] = {
10555                 { 0x00000200, 0x00008},
10556                 { 0x00004000, 0x00400},
10557                 { 0x00006000, 0x00400},
10558                 { 0x00008000, 0x01000},
10559                 { 0x00010000, 0x01000},
10560                 { 0xffffffff, 0x00000}
10561         }, mem_tbl_5717[] = {
10562                 { 0x00000200, 0x00008},
10563                 { 0x00010000, 0x0a000},
10564                 { 0x00020000, 0x13c00},
10565                 { 0xffffffff, 0x00000}
10566         }, mem_tbl_57765[] = {
10567                 { 0x00000200, 0x00008},
10568                 { 0x00004000, 0x00800},
10569                 { 0x00006000, 0x09800},
10570                 { 0x00010000, 0x0a000},
10571                 { 0xffffffff, 0x00000}
10572         };
10573         struct mem_entry *mem_tbl;
10574         int err = 0;
10575         int i;
10576
10577         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10578             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10579                 mem_tbl = mem_tbl_5717;
10580         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10581                 mem_tbl = mem_tbl_57765;
10582         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10583                 mem_tbl = mem_tbl_5755;
10584         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10585                 mem_tbl = mem_tbl_5906;
10586         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10587                 mem_tbl = mem_tbl_5705;
10588         else
10589                 mem_tbl = mem_tbl_570x;
10590
10591         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10592                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10593                 if (err)
10594                         break;
10595         }
10596
10597         return err;
10598 }
10599
10600 #define TG3_MAC_LOOPBACK        0
10601 #define TG3_PHY_LOOPBACK        1
10602
10603 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10604 {
10605         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10606         u32 desc_idx, coal_now;
10607         struct sk_buff *skb, *rx_skb;
10608         u8 *tx_data;
10609         dma_addr_t map;
10610         int num_pkts, tx_len, rx_len, i, err;
10611         struct tg3_rx_buffer_desc *desc;
10612         struct tg3_napi *tnapi, *rnapi;
10613         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10614
10615         tnapi = &tp->napi[0];
10616         rnapi = &tp->napi[0];
10617         if (tp->irq_cnt > 1) {
10618                 rnapi = &tp->napi[1];
10619                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10620                         tnapi = &tp->napi[1];
10621         }
10622         coal_now = tnapi->coal_now | rnapi->coal_now;
10623
10624         if (loopback_mode == TG3_MAC_LOOPBACK) {
10625                 /* HW errata - mac loopback fails in some cases on 5780.
10626                  * Normal traffic and PHY loopback are not affected by
10627                  * errata.
10628                  */
10629                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10630                         return 0;
10631
10632                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10633                            MAC_MODE_PORT_INT_LPBACK;
10634                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10635                         mac_mode |= MAC_MODE_LINK_POLARITY;
10636                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10637                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10638                 else
10639                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10640                 tw32(MAC_MODE, mac_mode);
10641         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10642                 u32 val;
10643
10644                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10645                         tg3_phy_fet_toggle_apd(tp, false);
10646                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10647                 } else
10648                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10649
10650                 tg3_phy_toggle_automdix(tp, 0);
10651
10652                 tg3_writephy(tp, MII_BMCR, val);
10653                 udelay(40);
10654
10655                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10656                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10657                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10658                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10659                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10660                         /* The write needs to be flushed for the AC131 */
10661                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10662                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10663                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10664                 } else
10665                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10666
10667                 /* reset to prevent losing 1st rx packet intermittently */
10668                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10669                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10670                         udelay(10);
10671                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10672                 }
10673                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10674                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10675                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10676                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10677                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10678                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10679                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10680                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10681                 }
10682                 tw32(MAC_MODE, mac_mode);
10683         } else {
10684                 return -EINVAL;
10685         }
10686
10687         err = -EIO;
10688
10689         tx_len = 1514;
10690         skb = netdev_alloc_skb(tp->dev, tx_len);
10691         if (!skb)
10692                 return -ENOMEM;
10693
10694         tx_data = skb_put(skb, tx_len);
10695         memcpy(tx_data, tp->dev->dev_addr, 6);
10696         memset(tx_data + 6, 0x0, 8);
10697
10698         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10699
10700         for (i = 14; i < tx_len; i++)
10701                 tx_data[i] = (u8) (i & 0xff);
10702
10703         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10704         if (pci_dma_mapping_error(tp->pdev, map)) {
10705                 dev_kfree_skb(skb);
10706                 return -EIO;
10707         }
10708
10709         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10710                rnapi->coal_now);
10711
10712         udelay(10);
10713
10714         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10715
10716         num_pkts = 0;
10717
10718         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10719
10720         tnapi->tx_prod++;
10721         num_pkts++;
10722
10723         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10724         tr32_mailbox(tnapi->prodmbox);
10725
10726         udelay(10);
10727
10728         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10729         for (i = 0; i < 35; i++) {
10730                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10731                        coal_now);
10732
10733                 udelay(10);
10734
10735                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10736                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10737                 if ((tx_idx == tnapi->tx_prod) &&
10738                     (rx_idx == (rx_start_idx + num_pkts)))
10739                         break;
10740         }
10741
10742         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10743         dev_kfree_skb(skb);
10744
10745         if (tx_idx != tnapi->tx_prod)
10746                 goto out;
10747
10748         if (rx_idx != rx_start_idx + num_pkts)
10749                 goto out;
10750
10751         desc = &rnapi->rx_rcb[rx_start_idx];
10752         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10753         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10754         if (opaque_key != RXD_OPAQUE_RING_STD)
10755                 goto out;
10756
10757         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10758             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10759                 goto out;
10760
10761         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10762         if (rx_len != tx_len)
10763                 goto out;
10764
10765         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10766
10767         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10768         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10769
10770         for (i = 14; i < tx_len; i++) {
10771                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10772                         goto out;
10773         }
10774         err = 0;
10775
10776         /* tg3_free_rings will unmap and free the rx_skb */
10777 out:
10778         return err;
10779 }
10780
10781 #define TG3_MAC_LOOPBACK_FAILED         1
10782 #define TG3_PHY_LOOPBACK_FAILED         2
10783 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10784                                          TG3_PHY_LOOPBACK_FAILED)
10785
10786 static int tg3_test_loopback(struct tg3 *tp)
10787 {
10788         int err = 0;
10789         u32 cpmuctrl = 0;
10790
10791         if (!netif_running(tp->dev))
10792                 return TG3_LOOPBACK_FAILED;
10793
10794         err = tg3_reset_hw(tp, 1);
10795         if (err)
10796                 return TG3_LOOPBACK_FAILED;
10797
10798         /* Turn off gphy autopowerdown. */
10799         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10800                 tg3_phy_toggle_apd(tp, false);
10801
10802         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10803                 int i;
10804                 u32 status;
10805
10806                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10807
10808                 /* Wait for up to 40 microseconds to acquire lock. */
10809                 for (i = 0; i < 4; i++) {
10810                         status = tr32(TG3_CPMU_MUTEX_GNT);
10811                         if (status == CPMU_MUTEX_GNT_DRIVER)
10812                                 break;
10813                         udelay(10);
10814                 }
10815
10816                 if (status != CPMU_MUTEX_GNT_DRIVER)
10817                         return TG3_LOOPBACK_FAILED;
10818
10819                 /* Turn off link-based power management. */
10820                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10821                 tw32(TG3_CPMU_CTRL,
10822                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10823                                   CPMU_CTRL_LINK_AWARE_MODE));
10824         }
10825
10826         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10827                 err |= TG3_MAC_LOOPBACK_FAILED;
10828
10829         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10830                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10831
10832                 /* Release the mutex */
10833                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10834         }
10835
10836         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10837             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10838                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10839                         err |= TG3_PHY_LOOPBACK_FAILED;
10840         }
10841
10842         /* Re-enable gphy autopowerdown. */
10843         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10844                 tg3_phy_toggle_apd(tp, true);
10845
10846         return err;
10847 }
10848
10849 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10850                           u64 *data)
10851 {
10852         struct tg3 *tp = netdev_priv(dev);
10853
10854         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10855                 tg3_set_power_state(tp, PCI_D0);
10856
10857         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10858
10859         if (tg3_test_nvram(tp) != 0) {
10860                 etest->flags |= ETH_TEST_FL_FAILED;
10861                 data[0] = 1;
10862         }
10863         if (tg3_test_link(tp) != 0) {
10864                 etest->flags |= ETH_TEST_FL_FAILED;
10865                 data[1] = 1;
10866         }
10867         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10868                 int err, err2 = 0, irq_sync = 0;
10869
10870                 if (netif_running(dev)) {
10871                         tg3_phy_stop(tp);
10872                         tg3_netif_stop(tp);
10873                         irq_sync = 1;
10874                 }
10875
10876                 tg3_full_lock(tp, irq_sync);
10877
10878                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10879                 err = tg3_nvram_lock(tp);
10880                 tg3_halt_cpu(tp, RX_CPU_BASE);
10881                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10882                         tg3_halt_cpu(tp, TX_CPU_BASE);
10883                 if (!err)
10884                         tg3_nvram_unlock(tp);
10885
10886                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10887                         tg3_phy_reset(tp);
10888
10889                 if (tg3_test_registers(tp) != 0) {
10890                         etest->flags |= ETH_TEST_FL_FAILED;
10891                         data[2] = 1;
10892                 }
10893                 if (tg3_test_memory(tp) != 0) {
10894                         etest->flags |= ETH_TEST_FL_FAILED;
10895                         data[3] = 1;
10896                 }
10897                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10898                         etest->flags |= ETH_TEST_FL_FAILED;
10899
10900                 tg3_full_unlock(tp);
10901
10902                 if (tg3_test_interrupt(tp) != 0) {
10903                         etest->flags |= ETH_TEST_FL_FAILED;
10904                         data[5] = 1;
10905                 }
10906
10907                 tg3_full_lock(tp, 0);
10908
10909                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10910                 if (netif_running(dev)) {
10911                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10912                         err2 = tg3_restart_hw(tp, 1);
10913                         if (!err2)
10914                                 tg3_netif_start(tp);
10915                 }
10916
10917                 tg3_full_unlock(tp);
10918
10919                 if (irq_sync && !err2)
10920                         tg3_phy_start(tp);
10921         }
10922         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10923                 tg3_set_power_state(tp, PCI_D3hot);
10924
10925 }
10926
10927 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10928 {
10929         struct mii_ioctl_data *data = if_mii(ifr);
10930         struct tg3 *tp = netdev_priv(dev);
10931         int err;
10932
10933         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10934                 struct phy_device *phydev;
10935                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10936                         return -EAGAIN;
10937                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10938                 return phy_mii_ioctl(phydev, ifr, cmd);
10939         }
10940
10941         switch (cmd) {
10942         case SIOCGMIIPHY:
10943                 data->phy_id = tp->phy_addr;
10944
10945                 /* fallthru */
10946         case SIOCGMIIREG: {
10947                 u32 mii_regval;
10948
10949                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10950                         break;                  /* We have no PHY */
10951
10952                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10953                         return -EAGAIN;
10954
10955                 spin_lock_bh(&tp->lock);
10956                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10957                 spin_unlock_bh(&tp->lock);
10958
10959                 data->val_out = mii_regval;
10960
10961                 return err;
10962         }
10963
10964         case SIOCSMIIREG:
10965                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10966                         break;                  /* We have no PHY */
10967
10968                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10969                         return -EAGAIN;
10970
10971                 spin_lock_bh(&tp->lock);
10972                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10973                 spin_unlock_bh(&tp->lock);
10974
10975                 return err;
10976
10977         default:
10978                 /* do nothing */
10979                 break;
10980         }
10981         return -EOPNOTSUPP;
10982 }
10983
10984 #if TG3_VLAN_TAG_USED
10985 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10986 {
10987         struct tg3 *tp = netdev_priv(dev);
10988
10989         if (!netif_running(dev)) {
10990                 tp->vlgrp = grp;
10991                 return;
10992         }
10993
10994         tg3_netif_stop(tp);
10995
10996         tg3_full_lock(tp, 0);
10997
10998         tp->vlgrp = grp;
10999
11000         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11001         __tg3_set_rx_mode(dev);
11002
11003         tg3_netif_start(tp);
11004
11005         tg3_full_unlock(tp);
11006 }
11007 #endif
11008
11009 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11010 {
11011         struct tg3 *tp = netdev_priv(dev);
11012
11013         memcpy(ec, &tp->coal, sizeof(*ec));
11014         return 0;
11015 }
11016
11017 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11018 {
11019         struct tg3 *tp = netdev_priv(dev);
11020         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11021         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11022
11023         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11024                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11025                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11026                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11027                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11028         }
11029
11030         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11031             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11032             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11033             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11034             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11035             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11036             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11037             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11038             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11039             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11040                 return -EINVAL;
11041
11042         /* No rx interrupts will be generated if both are zero */
11043         if ((ec->rx_coalesce_usecs == 0) &&
11044             (ec->rx_max_coalesced_frames == 0))
11045                 return -EINVAL;
11046
11047         /* No tx interrupts will be generated if both are zero */
11048         if ((ec->tx_coalesce_usecs == 0) &&
11049             (ec->tx_max_coalesced_frames == 0))
11050                 return -EINVAL;
11051
11052         /* Only copy relevant parameters, ignore all others. */
11053         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11054         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11055         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11056         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11057         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11058         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11059         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11060         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11061         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11062
11063         if (netif_running(dev)) {
11064                 tg3_full_lock(tp, 0);
11065                 __tg3_set_coalesce(tp, &tp->coal);
11066                 tg3_full_unlock(tp);
11067         }
11068         return 0;
11069 }
11070
11071 static const struct ethtool_ops tg3_ethtool_ops = {
11072         .get_settings           = tg3_get_settings,
11073         .set_settings           = tg3_set_settings,
11074         .get_drvinfo            = tg3_get_drvinfo,
11075         .get_regs_len           = tg3_get_regs_len,
11076         .get_regs               = tg3_get_regs,
11077         .get_wol                = tg3_get_wol,
11078         .set_wol                = tg3_set_wol,
11079         .get_msglevel           = tg3_get_msglevel,
11080         .set_msglevel           = tg3_set_msglevel,
11081         .nway_reset             = tg3_nway_reset,
11082         .get_link               = ethtool_op_get_link,
11083         .get_eeprom_len         = tg3_get_eeprom_len,
11084         .get_eeprom             = tg3_get_eeprom,
11085         .set_eeprom             = tg3_set_eeprom,
11086         .get_ringparam          = tg3_get_ringparam,
11087         .set_ringparam          = tg3_set_ringparam,
11088         .get_pauseparam         = tg3_get_pauseparam,
11089         .set_pauseparam         = tg3_set_pauseparam,
11090         .get_rx_csum            = tg3_get_rx_csum,
11091         .set_rx_csum            = tg3_set_rx_csum,
11092         .set_tx_csum            = tg3_set_tx_csum,
11093         .set_sg                 = ethtool_op_set_sg,
11094         .set_tso                = tg3_set_tso,
11095         .self_test              = tg3_self_test,
11096         .get_strings            = tg3_get_strings,
11097         .phys_id                = tg3_phys_id,
11098         .get_ethtool_stats      = tg3_get_ethtool_stats,
11099         .get_coalesce           = tg3_get_coalesce,
11100         .set_coalesce           = tg3_set_coalesce,
11101         .get_sset_count         = tg3_get_sset_count,
11102 };
11103
11104 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11105 {
11106         u32 cursize, val, magic;
11107
11108         tp->nvram_size = EEPROM_CHIP_SIZE;
11109
11110         if (tg3_nvram_read(tp, 0, &magic) != 0)
11111                 return;
11112
11113         if ((magic != TG3_EEPROM_MAGIC) &&
11114             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11115             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11116                 return;
11117
11118         /*
11119          * Size the chip by reading offsets at increasing powers of two.
11120          * When we encounter our validation signature, we know the addressing
11121          * has wrapped around, and thus have our chip size.
11122          */
11123         cursize = 0x10;
11124
11125         while (cursize < tp->nvram_size) {
11126                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11127                         return;
11128
11129                 if (val == magic)
11130                         break;
11131
11132                 cursize <<= 1;
11133         }
11134
11135         tp->nvram_size = cursize;
11136 }
11137
11138 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11139 {
11140         u32 val;
11141
11142         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11143             tg3_nvram_read(tp, 0, &val) != 0)
11144                 return;
11145
11146         /* Selfboot format */
11147         if (val != TG3_EEPROM_MAGIC) {
11148                 tg3_get_eeprom_size(tp);
11149                 return;
11150         }
11151
11152         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11153                 if (val != 0) {
11154                         /* This is confusing.  We want to operate on the
11155                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11156                          * call will read from NVRAM and byteswap the data
11157                          * according to the byteswapping settings for all
11158                          * other register accesses.  This ensures the data we
11159                          * want will always reside in the lower 16-bits.
11160                          * However, the data in NVRAM is in LE format, which
11161                          * means the data from the NVRAM read will always be
11162                          * opposite the endianness of the CPU.  The 16-bit
11163                          * byteswap then brings the data to CPU endianness.
11164                          */
11165                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11166                         return;
11167                 }
11168         }
11169         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11170 }
11171
11172 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11173 {
11174         u32 nvcfg1;
11175
11176         nvcfg1 = tr32(NVRAM_CFG1);
11177         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11178                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11179         } else {
11180                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11181                 tw32(NVRAM_CFG1, nvcfg1);
11182         }
11183
11184         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11185             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11186                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11187                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11188                         tp->nvram_jedecnum = JEDEC_ATMEL;
11189                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11190                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11191                         break;
11192                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11193                         tp->nvram_jedecnum = JEDEC_ATMEL;
11194                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11195                         break;
11196                 case FLASH_VENDOR_ATMEL_EEPROM:
11197                         tp->nvram_jedecnum = JEDEC_ATMEL;
11198                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11199                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11200                         break;
11201                 case FLASH_VENDOR_ST:
11202                         tp->nvram_jedecnum = JEDEC_ST;
11203                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11204                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11205                         break;
11206                 case FLASH_VENDOR_SAIFUN:
11207                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11208                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11209                         break;
11210                 case FLASH_VENDOR_SST_SMALL:
11211                 case FLASH_VENDOR_SST_LARGE:
11212                         tp->nvram_jedecnum = JEDEC_SST;
11213                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11214                         break;
11215                 }
11216         } else {
11217                 tp->nvram_jedecnum = JEDEC_ATMEL;
11218                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11219                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11220         }
11221 }
11222
11223 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11224 {
11225         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11226         case FLASH_5752PAGE_SIZE_256:
11227                 tp->nvram_pagesize = 256;
11228                 break;
11229         case FLASH_5752PAGE_SIZE_512:
11230                 tp->nvram_pagesize = 512;
11231                 break;
11232         case FLASH_5752PAGE_SIZE_1K:
11233                 tp->nvram_pagesize = 1024;
11234                 break;
11235         case FLASH_5752PAGE_SIZE_2K:
11236                 tp->nvram_pagesize = 2048;
11237                 break;
11238         case FLASH_5752PAGE_SIZE_4K:
11239                 tp->nvram_pagesize = 4096;
11240                 break;
11241         case FLASH_5752PAGE_SIZE_264:
11242                 tp->nvram_pagesize = 264;
11243                 break;
11244         case FLASH_5752PAGE_SIZE_528:
11245                 tp->nvram_pagesize = 528;
11246                 break;
11247         }
11248 }
11249
11250 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11251 {
11252         u32 nvcfg1;
11253
11254         nvcfg1 = tr32(NVRAM_CFG1);
11255
11256         /* NVRAM protection for TPM */
11257         if (nvcfg1 & (1 << 27))
11258                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11259
11260         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11261         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11262         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11263                 tp->nvram_jedecnum = JEDEC_ATMEL;
11264                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11265                 break;
11266         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11267                 tp->nvram_jedecnum = JEDEC_ATMEL;
11268                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11269                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11270                 break;
11271         case FLASH_5752VENDOR_ST_M45PE10:
11272         case FLASH_5752VENDOR_ST_M45PE20:
11273         case FLASH_5752VENDOR_ST_M45PE40:
11274                 tp->nvram_jedecnum = JEDEC_ST;
11275                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11276                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11277                 break;
11278         }
11279
11280         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11281                 tg3_nvram_get_pagesize(tp, nvcfg1);
11282         } else {
11283                 /* For eeprom, set pagesize to maximum eeprom size */
11284                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11285
11286                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11287                 tw32(NVRAM_CFG1, nvcfg1);
11288         }
11289 }
11290
11291 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11292 {
11293         u32 nvcfg1, protect = 0;
11294
11295         nvcfg1 = tr32(NVRAM_CFG1);
11296
11297         /* NVRAM protection for TPM */
11298         if (nvcfg1 & (1 << 27)) {
11299                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11300                 protect = 1;
11301         }
11302
11303         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11304         switch (nvcfg1) {
11305         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11306         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11307         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11308         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11309                 tp->nvram_jedecnum = JEDEC_ATMEL;
11310                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11311                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11312                 tp->nvram_pagesize = 264;
11313                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11314                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11315                         tp->nvram_size = (protect ? 0x3e200 :
11316                                           TG3_NVRAM_SIZE_512KB);
11317                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11318                         tp->nvram_size = (protect ? 0x1f200 :
11319                                           TG3_NVRAM_SIZE_256KB);
11320                 else
11321                         tp->nvram_size = (protect ? 0x1f200 :
11322                                           TG3_NVRAM_SIZE_128KB);
11323                 break;
11324         case FLASH_5752VENDOR_ST_M45PE10:
11325         case FLASH_5752VENDOR_ST_M45PE20:
11326         case FLASH_5752VENDOR_ST_M45PE40:
11327                 tp->nvram_jedecnum = JEDEC_ST;
11328                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11329                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11330                 tp->nvram_pagesize = 256;
11331                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11332                         tp->nvram_size = (protect ?
11333                                           TG3_NVRAM_SIZE_64KB :
11334                                           TG3_NVRAM_SIZE_128KB);
11335                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11336                         tp->nvram_size = (protect ?
11337                                           TG3_NVRAM_SIZE_64KB :
11338                                           TG3_NVRAM_SIZE_256KB);
11339                 else
11340                         tp->nvram_size = (protect ?
11341                                           TG3_NVRAM_SIZE_128KB :
11342                                           TG3_NVRAM_SIZE_512KB);
11343                 break;
11344         }
11345 }
11346
11347 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11348 {
11349         u32 nvcfg1;
11350
11351         nvcfg1 = tr32(NVRAM_CFG1);
11352
11353         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11354         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11355         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11356         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11357         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11358                 tp->nvram_jedecnum = JEDEC_ATMEL;
11359                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11360                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11361
11362                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11363                 tw32(NVRAM_CFG1, nvcfg1);
11364                 break;
11365         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11366         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11367         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11368         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11369                 tp->nvram_jedecnum = JEDEC_ATMEL;
11370                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11371                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11372                 tp->nvram_pagesize = 264;
11373                 break;
11374         case FLASH_5752VENDOR_ST_M45PE10:
11375         case FLASH_5752VENDOR_ST_M45PE20:
11376         case FLASH_5752VENDOR_ST_M45PE40:
11377                 tp->nvram_jedecnum = JEDEC_ST;
11378                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11379                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11380                 tp->nvram_pagesize = 256;
11381                 break;
11382         }
11383 }
11384
11385 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11386 {
11387         u32 nvcfg1, protect = 0;
11388
11389         nvcfg1 = tr32(NVRAM_CFG1);
11390
11391         /* NVRAM protection for TPM */
11392         if (nvcfg1 & (1 << 27)) {
11393                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11394                 protect = 1;
11395         }
11396
11397         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11398         switch (nvcfg1) {
11399         case FLASH_5761VENDOR_ATMEL_ADB021D:
11400         case FLASH_5761VENDOR_ATMEL_ADB041D:
11401         case FLASH_5761VENDOR_ATMEL_ADB081D:
11402         case FLASH_5761VENDOR_ATMEL_ADB161D:
11403         case FLASH_5761VENDOR_ATMEL_MDB021D:
11404         case FLASH_5761VENDOR_ATMEL_MDB041D:
11405         case FLASH_5761VENDOR_ATMEL_MDB081D:
11406         case FLASH_5761VENDOR_ATMEL_MDB161D:
11407                 tp->nvram_jedecnum = JEDEC_ATMEL;
11408                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11409                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11410                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11411                 tp->nvram_pagesize = 256;
11412                 break;
11413         case FLASH_5761VENDOR_ST_A_M45PE20:
11414         case FLASH_5761VENDOR_ST_A_M45PE40:
11415         case FLASH_5761VENDOR_ST_A_M45PE80:
11416         case FLASH_5761VENDOR_ST_A_M45PE16:
11417         case FLASH_5761VENDOR_ST_M_M45PE20:
11418         case FLASH_5761VENDOR_ST_M_M45PE40:
11419         case FLASH_5761VENDOR_ST_M_M45PE80:
11420         case FLASH_5761VENDOR_ST_M_M45PE16:
11421                 tp->nvram_jedecnum = JEDEC_ST;
11422                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11423                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11424                 tp->nvram_pagesize = 256;
11425                 break;
11426         }
11427
11428         if (protect) {
11429                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11430         } else {
11431                 switch (nvcfg1) {
11432                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11433                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11434                 case FLASH_5761VENDOR_ST_A_M45PE16:
11435                 case FLASH_5761VENDOR_ST_M_M45PE16:
11436                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11437                         break;
11438                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11439                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11440                 case FLASH_5761VENDOR_ST_A_M45PE80:
11441                 case FLASH_5761VENDOR_ST_M_M45PE80:
11442                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11443                         break;
11444                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11445                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11446                 case FLASH_5761VENDOR_ST_A_M45PE40:
11447                 case FLASH_5761VENDOR_ST_M_M45PE40:
11448                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11449                         break;
11450                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11451                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11452                 case FLASH_5761VENDOR_ST_A_M45PE20:
11453                 case FLASH_5761VENDOR_ST_M_M45PE20:
11454                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11455                         break;
11456                 }
11457         }
11458 }
11459
11460 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11461 {
11462         tp->nvram_jedecnum = JEDEC_ATMEL;
11463         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11464         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11465 }
11466
11467 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11468 {
11469         u32 nvcfg1;
11470
11471         nvcfg1 = tr32(NVRAM_CFG1);
11472
11473         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11474         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11475         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11476                 tp->nvram_jedecnum = JEDEC_ATMEL;
11477                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11478                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11479
11480                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11481                 tw32(NVRAM_CFG1, nvcfg1);
11482                 return;
11483         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11484         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11485         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11486         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11487         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11488         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11489         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11490                 tp->nvram_jedecnum = JEDEC_ATMEL;
11491                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11492                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11493
11494                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11495                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11496                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11497                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11498                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11499                         break;
11500                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11501                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11502                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11503                         break;
11504                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11505                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11506                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11507                         break;
11508                 }
11509                 break;
11510         case FLASH_5752VENDOR_ST_M45PE10:
11511         case FLASH_5752VENDOR_ST_M45PE20:
11512         case FLASH_5752VENDOR_ST_M45PE40:
11513                 tp->nvram_jedecnum = JEDEC_ST;
11514                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11515                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11516
11517                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11518                 case FLASH_5752VENDOR_ST_M45PE10:
11519                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11520                         break;
11521                 case FLASH_5752VENDOR_ST_M45PE20:
11522                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11523                         break;
11524                 case FLASH_5752VENDOR_ST_M45PE40:
11525                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11526                         break;
11527                 }
11528                 break;
11529         default:
11530                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11531                 return;
11532         }
11533
11534         tg3_nvram_get_pagesize(tp, nvcfg1);
11535         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11536                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11537 }
11538
11539
11540 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11541 {
11542         u32 nvcfg1;
11543
11544         nvcfg1 = tr32(NVRAM_CFG1);
11545
11546         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11547         case FLASH_5717VENDOR_ATMEL_EEPROM:
11548         case FLASH_5717VENDOR_MICRO_EEPROM:
11549                 tp->nvram_jedecnum = JEDEC_ATMEL;
11550                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11551                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11552
11553                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11554                 tw32(NVRAM_CFG1, nvcfg1);
11555                 return;
11556         case FLASH_5717VENDOR_ATMEL_MDB011D:
11557         case FLASH_5717VENDOR_ATMEL_ADB011B:
11558         case FLASH_5717VENDOR_ATMEL_ADB011D:
11559         case FLASH_5717VENDOR_ATMEL_MDB021D:
11560         case FLASH_5717VENDOR_ATMEL_ADB021B:
11561         case FLASH_5717VENDOR_ATMEL_ADB021D:
11562         case FLASH_5717VENDOR_ATMEL_45USPT:
11563                 tp->nvram_jedecnum = JEDEC_ATMEL;
11564                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11565                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11566
11567                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11568                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11569                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11570                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11571                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11572                         break;
11573                 default:
11574                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11575                         break;
11576                 }
11577                 break;
11578         case FLASH_5717VENDOR_ST_M_M25PE10:
11579         case FLASH_5717VENDOR_ST_A_M25PE10:
11580         case FLASH_5717VENDOR_ST_M_M45PE10:
11581         case FLASH_5717VENDOR_ST_A_M45PE10:
11582         case FLASH_5717VENDOR_ST_M_M25PE20:
11583         case FLASH_5717VENDOR_ST_A_M25PE20:
11584         case FLASH_5717VENDOR_ST_M_M45PE20:
11585         case FLASH_5717VENDOR_ST_A_M45PE20:
11586         case FLASH_5717VENDOR_ST_25USPT:
11587         case FLASH_5717VENDOR_ST_45USPT:
11588                 tp->nvram_jedecnum = JEDEC_ST;
11589                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11590                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11591
11592                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11593                 case FLASH_5717VENDOR_ST_M_M25PE20:
11594                 case FLASH_5717VENDOR_ST_A_M25PE20:
11595                 case FLASH_5717VENDOR_ST_M_M45PE20:
11596                 case FLASH_5717VENDOR_ST_A_M45PE20:
11597                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11598                         break;
11599                 default:
11600                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11601                         break;
11602                 }
11603                 break;
11604         default:
11605                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11606                 return;
11607         }
11608
11609         tg3_nvram_get_pagesize(tp, nvcfg1);
11610         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11611                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11612 }
11613
11614 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11615 static void __devinit tg3_nvram_init(struct tg3 *tp)
11616 {
11617         tw32_f(GRC_EEPROM_ADDR,
11618              (EEPROM_ADDR_FSM_RESET |
11619               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11620                EEPROM_ADDR_CLKPERD_SHIFT)));
11621
11622         msleep(1);
11623
11624         /* Enable seeprom accesses. */
11625         tw32_f(GRC_LOCAL_CTRL,
11626              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11627         udelay(100);
11628
11629         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11630             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11631                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11632
11633                 if (tg3_nvram_lock(tp)) {
11634                         netdev_warn(tp->dev,
11635                                     "Cannot get nvram lock, %s failed\n",
11636                                     __func__);
11637                         return;
11638                 }
11639                 tg3_enable_nvram_access(tp);
11640
11641                 tp->nvram_size = 0;
11642
11643                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11644                         tg3_get_5752_nvram_info(tp);
11645                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11646                         tg3_get_5755_nvram_info(tp);
11647                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11648                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11649                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11650                         tg3_get_5787_nvram_info(tp);
11651                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11652                         tg3_get_5761_nvram_info(tp);
11653                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11654                         tg3_get_5906_nvram_info(tp);
11655                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11656                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11657                         tg3_get_57780_nvram_info(tp);
11658                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11659                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11660                         tg3_get_5717_nvram_info(tp);
11661                 else
11662                         tg3_get_nvram_info(tp);
11663
11664                 if (tp->nvram_size == 0)
11665                         tg3_get_nvram_size(tp);
11666
11667                 tg3_disable_nvram_access(tp);
11668                 tg3_nvram_unlock(tp);
11669
11670         } else {
11671                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11672
11673                 tg3_get_eeprom_size(tp);
11674         }
11675 }
11676
11677 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11678                                     u32 offset, u32 len, u8 *buf)
11679 {
11680         int i, j, rc = 0;
11681         u32 val;
11682
11683         for (i = 0; i < len; i += 4) {
11684                 u32 addr;
11685                 __be32 data;
11686
11687                 addr = offset + i;
11688
11689                 memcpy(&data, buf + i, 4);
11690
11691                 /*
11692                  * The SEEPROM interface expects the data to always be opposite
11693                  * the native endian format.  We accomplish this by reversing
11694                  * all the operations that would have been performed on the
11695                  * data from a call to tg3_nvram_read_be32().
11696                  */
11697                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11698
11699                 val = tr32(GRC_EEPROM_ADDR);
11700                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11701
11702                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11703                         EEPROM_ADDR_READ);
11704                 tw32(GRC_EEPROM_ADDR, val |
11705                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11706                         (addr & EEPROM_ADDR_ADDR_MASK) |
11707                         EEPROM_ADDR_START |
11708                         EEPROM_ADDR_WRITE);
11709
11710                 for (j = 0; j < 1000; j++) {
11711                         val = tr32(GRC_EEPROM_ADDR);
11712
11713                         if (val & EEPROM_ADDR_COMPLETE)
11714                                 break;
11715                         msleep(1);
11716                 }
11717                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11718                         rc = -EBUSY;
11719                         break;
11720                 }
11721         }
11722
11723         return rc;
11724 }
11725
11726 /* offset and length are dword aligned */
11727 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11728                 u8 *buf)
11729 {
11730         int ret = 0;
11731         u32 pagesize = tp->nvram_pagesize;
11732         u32 pagemask = pagesize - 1;
11733         u32 nvram_cmd;
11734         u8 *tmp;
11735
11736         tmp = kmalloc(pagesize, GFP_KERNEL);
11737         if (tmp == NULL)
11738                 return -ENOMEM;
11739
11740         while (len) {
11741                 int j;
11742                 u32 phy_addr, page_off, size;
11743
11744                 phy_addr = offset & ~pagemask;
11745
11746                 for (j = 0; j < pagesize; j += 4) {
11747                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11748                                                   (__be32 *) (tmp + j));
11749                         if (ret)
11750                                 break;
11751                 }
11752                 if (ret)
11753                         break;
11754
11755                 page_off = offset & pagemask;
11756                 size = pagesize;
11757                 if (len < size)
11758                         size = len;
11759
11760                 len -= size;
11761
11762                 memcpy(tmp + page_off, buf, size);
11763
11764                 offset = offset + (pagesize - page_off);
11765
11766                 tg3_enable_nvram_access(tp);
11767
11768                 /*
11769                  * Before we can erase the flash page, we need
11770                  * to issue a special "write enable" command.
11771                  */
11772                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11773
11774                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11775                         break;
11776
11777                 /* Erase the target page */
11778                 tw32(NVRAM_ADDR, phy_addr);
11779
11780                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11781                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11782
11783                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11784                         break;
11785
11786                 /* Issue another write enable to start the write. */
11787                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11788
11789                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11790                         break;
11791
11792                 for (j = 0; j < pagesize; j += 4) {
11793                         __be32 data;
11794
11795                         data = *((__be32 *) (tmp + j));
11796
11797                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11798
11799                         tw32(NVRAM_ADDR, phy_addr + j);
11800
11801                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11802                                 NVRAM_CMD_WR;
11803
11804                         if (j == 0)
11805                                 nvram_cmd |= NVRAM_CMD_FIRST;
11806                         else if (j == (pagesize - 4))
11807                                 nvram_cmd |= NVRAM_CMD_LAST;
11808
11809                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11810                                 break;
11811                 }
11812                 if (ret)
11813                         break;
11814         }
11815
11816         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11817         tg3_nvram_exec_cmd(tp, nvram_cmd);
11818
11819         kfree(tmp);
11820
11821         return ret;
11822 }
11823
11824 /* offset and length are dword aligned */
11825 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11826                 u8 *buf)
11827 {
11828         int i, ret = 0;
11829
11830         for (i = 0; i < len; i += 4, offset += 4) {
11831                 u32 page_off, phy_addr, nvram_cmd;
11832                 __be32 data;
11833
11834                 memcpy(&data, buf + i, 4);
11835                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11836
11837                 page_off = offset % tp->nvram_pagesize;
11838
11839                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11840
11841                 tw32(NVRAM_ADDR, phy_addr);
11842
11843                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11844
11845                 if (page_off == 0 || i == 0)
11846                         nvram_cmd |= NVRAM_CMD_FIRST;
11847                 if (page_off == (tp->nvram_pagesize - 4))
11848                         nvram_cmd |= NVRAM_CMD_LAST;
11849
11850                 if (i == (len - 4))
11851                         nvram_cmd |= NVRAM_CMD_LAST;
11852
11853                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11854                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11855                     (tp->nvram_jedecnum == JEDEC_ST) &&
11856                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11857
11858                         if ((ret = tg3_nvram_exec_cmd(tp,
11859                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11860                                 NVRAM_CMD_DONE)))
11861
11862                                 break;
11863                 }
11864                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11865                         /* We always do complete word writes to eeprom. */
11866                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11867                 }
11868
11869                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11870                         break;
11871         }
11872         return ret;
11873 }
11874
11875 /* offset and length are dword aligned */
11876 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11877 {
11878         int ret;
11879
11880         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11881                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11882                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11883                 udelay(40);
11884         }
11885
11886         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11887                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11888         } else {
11889                 u32 grc_mode;
11890
11891                 ret = tg3_nvram_lock(tp);
11892                 if (ret)
11893                         return ret;
11894
11895                 tg3_enable_nvram_access(tp);
11896                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11897                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11898                         tw32(NVRAM_WRITE1, 0x406);
11899
11900                 grc_mode = tr32(GRC_MODE);
11901                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11902
11903                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11904                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11905
11906                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11907                                 buf);
11908                 } else {
11909                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11910                                 buf);
11911                 }
11912
11913                 grc_mode = tr32(GRC_MODE);
11914                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11915
11916                 tg3_disable_nvram_access(tp);
11917                 tg3_nvram_unlock(tp);
11918         }
11919
11920         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11921                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11922                 udelay(40);
11923         }
11924
11925         return ret;
11926 }
11927
11928 struct subsys_tbl_ent {
11929         u16 subsys_vendor, subsys_devid;
11930         u32 phy_id;
11931 };
11932
11933 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11934         /* Broadcom boards. */
11935         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11936           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11937         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11938           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11939         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11940           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11941         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11942           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11943         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11944           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11945         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11946           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11947         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11948           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11949         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11950           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11951         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11952           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11953         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11954           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11955         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11956           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11957
11958         /* 3com boards. */
11959         { TG3PCI_SUBVENDOR_ID_3COM,
11960           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11961         { TG3PCI_SUBVENDOR_ID_3COM,
11962           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11963         { TG3PCI_SUBVENDOR_ID_3COM,
11964           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11965         { TG3PCI_SUBVENDOR_ID_3COM,
11966           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11967         { TG3PCI_SUBVENDOR_ID_3COM,
11968           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11969
11970         /* DELL boards. */
11971         { TG3PCI_SUBVENDOR_ID_DELL,
11972           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11973         { TG3PCI_SUBVENDOR_ID_DELL,
11974           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11975         { TG3PCI_SUBVENDOR_ID_DELL,
11976           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11977         { TG3PCI_SUBVENDOR_ID_DELL,
11978           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11979
11980         /* Compaq boards. */
11981         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11982           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11983         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11984           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11985         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11986           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11987         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11988           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11989         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11990           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11991
11992         /* IBM boards. */
11993         { TG3PCI_SUBVENDOR_ID_IBM,
11994           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11995 };
11996
11997 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
11998 {
11999         int i;
12000
12001         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12002                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12003                      tp->pdev->subsystem_vendor) &&
12004                     (subsys_id_to_phy_id[i].subsys_devid ==
12005                      tp->pdev->subsystem_device))
12006                         return &subsys_id_to_phy_id[i];
12007         }
12008         return NULL;
12009 }
12010
12011 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12012 {
12013         u32 val;
12014         u16 pmcsr;
12015
12016         /* On some early chips the SRAM cannot be accessed in D3hot state,
12017          * so need make sure we're in D0.
12018          */
12019         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12020         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12021         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12022         msleep(1);
12023
12024         /* Make sure register accesses (indirect or otherwise)
12025          * will function correctly.
12026          */
12027         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12028                                tp->misc_host_ctrl);
12029
12030         /* The memory arbiter has to be enabled in order for SRAM accesses
12031          * to succeed.  Normally on powerup the tg3 chip firmware will make
12032          * sure it is enabled, but other entities such as system netboot
12033          * code might disable it.
12034          */
12035         val = tr32(MEMARB_MODE);
12036         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12037
12038         tp->phy_id = TG3_PHY_ID_INVALID;
12039         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12040
12041         /* Assume an onboard device and WOL capable by default.  */
12042         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12043
12044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12045                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12046                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12047                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12048                 }
12049                 val = tr32(VCPU_CFGSHDW);
12050                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12051                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12052                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12053                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12054                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12055                 goto done;
12056         }
12057
12058         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12059         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12060                 u32 nic_cfg, led_cfg;
12061                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12062                 int eeprom_phy_serdes = 0;
12063
12064                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12065                 tp->nic_sram_data_cfg = nic_cfg;
12066
12067                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12068                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12069                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12070                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12071                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12072                     (ver > 0) && (ver < 0x100))
12073                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12074
12075                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12076                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12077
12078                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12079                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12080                         eeprom_phy_serdes = 1;
12081
12082                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12083                 if (nic_phy_id != 0) {
12084                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12085                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12086
12087                         eeprom_phy_id  = (id1 >> 16) << 10;
12088                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12089                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12090                 } else
12091                         eeprom_phy_id = 0;
12092
12093                 tp->phy_id = eeprom_phy_id;
12094                 if (eeprom_phy_serdes) {
12095                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12096                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12097                         else
12098                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12099                 }
12100
12101                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12102                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12103                                     SHASTA_EXT_LED_MODE_MASK);
12104                 else
12105                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12106
12107                 switch (led_cfg) {
12108                 default:
12109                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12110                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12111                         break;
12112
12113                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12114                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12115                         break;
12116
12117                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12118                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12119
12120                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12121                          * read on some older 5700/5701 bootcode.
12122                          */
12123                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12124                             ASIC_REV_5700 ||
12125                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12126                             ASIC_REV_5701)
12127                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12128
12129                         break;
12130
12131                 case SHASTA_EXT_LED_SHARED:
12132                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12133                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12134                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12135                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12136                                                  LED_CTRL_MODE_PHY_2);
12137                         break;
12138
12139                 case SHASTA_EXT_LED_MAC:
12140                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12141                         break;
12142
12143                 case SHASTA_EXT_LED_COMBO:
12144                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12145                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12146                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12147                                                  LED_CTRL_MODE_PHY_2);
12148                         break;
12149
12150                 }
12151
12152                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12153                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12154                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12155                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12156
12157                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12158                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12159
12160                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12161                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12162                         if ((tp->pdev->subsystem_vendor ==
12163                              PCI_VENDOR_ID_ARIMA) &&
12164                             (tp->pdev->subsystem_device == 0x205a ||
12165                              tp->pdev->subsystem_device == 0x2063))
12166                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12167                 } else {
12168                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12169                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12170                 }
12171
12172                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12173                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12174                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12175                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12176                 }
12177
12178                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12179                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12180                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12181
12182                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12183                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12184                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12185
12186                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12187                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12188                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12189
12190                 if (cfg2 & (1 << 17))
12191                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12192
12193                 /* serdes signal pre-emphasis in register 0x590 set by */
12194                 /* bootcode if bit 18 is set */
12195                 if (cfg2 & (1 << 18))
12196                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12197
12198                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12199                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12200                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12201                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12202
12203                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12204                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12205                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12206                         u32 cfg3;
12207
12208                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12209                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12210                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12211                 }
12212
12213                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12214                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12215                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12216                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12217                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12218                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12219         }
12220 done:
12221         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12222         device_set_wakeup_enable(&tp->pdev->dev,
12223                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12224 }
12225
12226 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12227 {
12228         int i;
12229         u32 val;
12230
12231         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12232         tw32(OTP_CTRL, cmd);
12233
12234         /* Wait for up to 1 ms for command to execute. */
12235         for (i = 0; i < 100; i++) {
12236                 val = tr32(OTP_STATUS);
12237                 if (val & OTP_STATUS_CMD_DONE)
12238                         break;
12239                 udelay(10);
12240         }
12241
12242         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12243 }
12244
12245 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12246  * configuration is a 32-bit value that straddles the alignment boundary.
12247  * We do two 32-bit reads and then shift and merge the results.
12248  */
12249 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12250 {
12251         u32 bhalf_otp, thalf_otp;
12252
12253         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12254
12255         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12256                 return 0;
12257
12258         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12259
12260         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12261                 return 0;
12262
12263         thalf_otp = tr32(OTP_READ_DATA);
12264
12265         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12266
12267         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12268                 return 0;
12269
12270         bhalf_otp = tr32(OTP_READ_DATA);
12271
12272         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12273 }
12274
12275 static int __devinit tg3_phy_probe(struct tg3 *tp)
12276 {
12277         u32 hw_phy_id_1, hw_phy_id_2;
12278         u32 hw_phy_id, hw_phy_id_masked;
12279         int err;
12280
12281         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12282                 return tg3_phy_init(tp);
12283
12284         /* Reading the PHY ID register can conflict with ASF
12285          * firmware access to the PHY hardware.
12286          */
12287         err = 0;
12288         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12289             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12290                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12291         } else {
12292                 /* Now read the physical PHY_ID from the chip and verify
12293                  * that it is sane.  If it doesn't look good, we fall back
12294                  * to either the hard-coded table based PHY_ID and failing
12295                  * that the value found in the eeprom area.
12296                  */
12297                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12298                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12299
12300                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12301                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12302                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12303
12304                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12305         }
12306
12307         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12308                 tp->phy_id = hw_phy_id;
12309                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12310                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12311                 else
12312                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12313         } else {
12314                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12315                         /* Do nothing, phy ID already set up in
12316                          * tg3_get_eeprom_hw_cfg().
12317                          */
12318                 } else {
12319                         struct subsys_tbl_ent *p;
12320
12321                         /* No eeprom signature?  Try the hardcoded
12322                          * subsys device table.
12323                          */
12324                         p = tg3_lookup_by_subsys(tp);
12325                         if (!p)
12326                                 return -ENODEV;
12327
12328                         tp->phy_id = p->phy_id;
12329                         if (!tp->phy_id ||
12330                             tp->phy_id == TG3_PHY_ID_BCM8002)
12331                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12332                 }
12333         }
12334
12335         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12336             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12337             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12338                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12339
12340                 tg3_readphy(tp, MII_BMSR, &bmsr);
12341                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12342                     (bmsr & BMSR_LSTATUS))
12343                         goto skip_phy_reset;
12344
12345                 err = tg3_phy_reset(tp);
12346                 if (err)
12347                         return err;
12348
12349                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12350                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12351                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12352                 tg3_ctrl = 0;
12353                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12354                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12355                                     MII_TG3_CTRL_ADV_1000_FULL);
12356                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12357                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12358                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12359                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12360                 }
12361
12362                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12363                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12364                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12365                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12366                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12367
12368                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12369                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12370
12371                         tg3_writephy(tp, MII_BMCR,
12372                                      BMCR_ANENABLE | BMCR_ANRESTART);
12373                 }
12374                 tg3_phy_set_wirespeed(tp);
12375
12376                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12377                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12378                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12379         }
12380
12381 skip_phy_reset:
12382         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12383                 err = tg3_init_5401phy_dsp(tp);
12384                 if (err)
12385                         return err;
12386
12387                 err = tg3_init_5401phy_dsp(tp);
12388         }
12389
12390         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12391                 tp->link_config.advertising =
12392                         (ADVERTISED_1000baseT_Half |
12393                          ADVERTISED_1000baseT_Full |
12394                          ADVERTISED_Autoneg |
12395                          ADVERTISED_FIBRE);
12396         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12397                 tp->link_config.advertising &=
12398                         ~(ADVERTISED_1000baseT_Half |
12399                           ADVERTISED_1000baseT_Full);
12400
12401         return err;
12402 }
12403
12404 static void __devinit tg3_read_vpd(struct tg3 *tp)
12405 {
12406         u8 vpd_data[TG3_NVM_VPD_LEN];
12407         unsigned int block_end, rosize, len;
12408         int j, i = 0;
12409         u32 magic;
12410
12411         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12412             tg3_nvram_read(tp, 0x0, &magic))
12413                 goto out_not_found;
12414
12415         if (magic == TG3_EEPROM_MAGIC) {
12416                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12417                         u32 tmp;
12418
12419                         /* The data is in little-endian format in NVRAM.
12420                          * Use the big-endian read routines to preserve
12421                          * the byte order as it exists in NVRAM.
12422                          */
12423                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12424                                 goto out_not_found;
12425
12426                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12427                 }
12428         } else {
12429                 ssize_t cnt;
12430                 unsigned int pos = 0;
12431
12432                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12433                         cnt = pci_read_vpd(tp->pdev, pos,
12434                                            TG3_NVM_VPD_LEN - pos,
12435                                            &vpd_data[pos]);
12436                         if (cnt == -ETIMEDOUT || -EINTR)
12437                                 cnt = 0;
12438                         else if (cnt < 0)
12439                                 goto out_not_found;
12440                 }
12441                 if (pos != TG3_NVM_VPD_LEN)
12442                         goto out_not_found;
12443         }
12444
12445         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12446                              PCI_VPD_LRDT_RO_DATA);
12447         if (i < 0)
12448                 goto out_not_found;
12449
12450         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12451         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12452         i += PCI_VPD_LRDT_TAG_SIZE;
12453
12454         if (block_end > TG3_NVM_VPD_LEN)
12455                 goto out_not_found;
12456
12457         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12458                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12459         if (j > 0) {
12460                 len = pci_vpd_info_field_size(&vpd_data[j]);
12461
12462                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12463                 if (j + len > block_end || len != 4 ||
12464                     memcmp(&vpd_data[j], "1028", 4))
12465                         goto partno;
12466
12467                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12468                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12469                 if (j < 0)
12470                         goto partno;
12471
12472                 len = pci_vpd_info_field_size(&vpd_data[j]);
12473
12474                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12475                 if (j + len > block_end)
12476                         goto partno;
12477
12478                 memcpy(tp->fw_ver, &vpd_data[j], len);
12479                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12480         }
12481
12482 partno:
12483         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12484                                       PCI_VPD_RO_KEYWORD_PARTNO);
12485         if (i < 0)
12486                 goto out_not_found;
12487
12488         len = pci_vpd_info_field_size(&vpd_data[i]);
12489
12490         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12491         if (len > TG3_BPN_SIZE ||
12492             (len + i) > TG3_NVM_VPD_LEN)
12493                 goto out_not_found;
12494
12495         memcpy(tp->board_part_number, &vpd_data[i], len);
12496
12497         return;
12498
12499 out_not_found:
12500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12501                 strcpy(tp->board_part_number, "BCM95906");
12502         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12503                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12504                 strcpy(tp->board_part_number, "BCM57780");
12505         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12506                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12507                 strcpy(tp->board_part_number, "BCM57760");
12508         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12509                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12510                 strcpy(tp->board_part_number, "BCM57790");
12511         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12512                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12513                 strcpy(tp->board_part_number, "BCM57788");
12514         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12515                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12516                 strcpy(tp->board_part_number, "BCM57761");
12517         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12518                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12519                 strcpy(tp->board_part_number, "BCM57765");
12520         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12521                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12522                 strcpy(tp->board_part_number, "BCM57781");
12523         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12524                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12525                 strcpy(tp->board_part_number, "BCM57785");
12526         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12527                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12528                 strcpy(tp->board_part_number, "BCM57791");
12529         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12530                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12531                 strcpy(tp->board_part_number, "BCM57795");
12532         else
12533                 strcpy(tp->board_part_number, "none");
12534 }
12535
12536 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12537 {
12538         u32 val;
12539
12540         if (tg3_nvram_read(tp, offset, &val) ||
12541             (val & 0xfc000000) != 0x0c000000 ||
12542             tg3_nvram_read(tp, offset + 4, &val) ||
12543             val != 0)
12544                 return 0;
12545
12546         return 1;
12547 }
12548
12549 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12550 {
12551         u32 val, offset, start, ver_offset;
12552         int i, dst_off;
12553         bool newver = false;
12554
12555         if (tg3_nvram_read(tp, 0xc, &offset) ||
12556             tg3_nvram_read(tp, 0x4, &start))
12557                 return;
12558
12559         offset = tg3_nvram_logical_addr(tp, offset);
12560
12561         if (tg3_nvram_read(tp, offset, &val))
12562                 return;
12563
12564         if ((val & 0xfc000000) == 0x0c000000) {
12565                 if (tg3_nvram_read(tp, offset + 4, &val))
12566                         return;
12567
12568                 if (val == 0)
12569                         newver = true;
12570         }
12571
12572         dst_off = strlen(tp->fw_ver);
12573
12574         if (newver) {
12575                 if (TG3_VER_SIZE - dst_off < 16 ||
12576                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12577                         return;
12578
12579                 offset = offset + ver_offset - start;
12580                 for (i = 0; i < 16; i += 4) {
12581                         __be32 v;
12582                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12583                                 return;
12584
12585                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12586                 }
12587         } else {
12588                 u32 major, minor;
12589
12590                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12591                         return;
12592
12593                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12594                         TG3_NVM_BCVER_MAJSFT;
12595                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12596                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12597                          "v%d.%02d", major, minor);
12598         }
12599 }
12600
12601 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12602 {
12603         u32 val, major, minor;
12604
12605         /* Use native endian representation */
12606         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12607                 return;
12608
12609         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12610                 TG3_NVM_HWSB_CFG1_MAJSFT;
12611         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12612                 TG3_NVM_HWSB_CFG1_MINSFT;
12613
12614         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12615 }
12616
12617 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12618 {
12619         u32 offset, major, minor, build;
12620
12621         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12622
12623         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12624                 return;
12625
12626         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12627         case TG3_EEPROM_SB_REVISION_0:
12628                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12629                 break;
12630         case TG3_EEPROM_SB_REVISION_2:
12631                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12632                 break;
12633         case TG3_EEPROM_SB_REVISION_3:
12634                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12635                 break;
12636         case TG3_EEPROM_SB_REVISION_4:
12637                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12638                 break;
12639         case TG3_EEPROM_SB_REVISION_5:
12640                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12641                 break;
12642         default:
12643                 return;
12644         }
12645
12646         if (tg3_nvram_read(tp, offset, &val))
12647                 return;
12648
12649         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12650                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12651         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12652                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12653         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12654
12655         if (minor > 99 || build > 26)
12656                 return;
12657
12658         offset = strlen(tp->fw_ver);
12659         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12660                  " v%d.%02d", major, minor);
12661
12662         if (build > 0) {
12663                 offset = strlen(tp->fw_ver);
12664                 if (offset < TG3_VER_SIZE - 1)
12665                         tp->fw_ver[offset] = 'a' + build - 1;
12666         }
12667 }
12668
12669 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12670 {
12671         u32 val, offset, start;
12672         int i, vlen;
12673
12674         for (offset = TG3_NVM_DIR_START;
12675              offset < TG3_NVM_DIR_END;
12676              offset += TG3_NVM_DIRENT_SIZE) {
12677                 if (tg3_nvram_read(tp, offset, &val))
12678                         return;
12679
12680                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12681                         break;
12682         }
12683
12684         if (offset == TG3_NVM_DIR_END)
12685                 return;
12686
12687         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12688                 start = 0x08000000;
12689         else if (tg3_nvram_read(tp, offset - 4, &start))
12690                 return;
12691
12692         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12693             !tg3_fw_img_is_valid(tp, offset) ||
12694             tg3_nvram_read(tp, offset + 8, &val))
12695                 return;
12696
12697         offset += val - start;
12698
12699         vlen = strlen(tp->fw_ver);
12700
12701         tp->fw_ver[vlen++] = ',';
12702         tp->fw_ver[vlen++] = ' ';
12703
12704         for (i = 0; i < 4; i++) {
12705                 __be32 v;
12706                 if (tg3_nvram_read_be32(tp, offset, &v))
12707                         return;
12708
12709                 offset += sizeof(v);
12710
12711                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12712                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12713                         break;
12714                 }
12715
12716                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12717                 vlen += sizeof(v);
12718         }
12719 }
12720
12721 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12722 {
12723         int vlen;
12724         u32 apedata;
12725         char *fwtype;
12726
12727         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12728             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12729                 return;
12730
12731         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12732         if (apedata != APE_SEG_SIG_MAGIC)
12733                 return;
12734
12735         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12736         if (!(apedata & APE_FW_STATUS_READY))
12737                 return;
12738
12739         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12740
12741         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
12742                 fwtype = "NCSI";
12743         else
12744                 fwtype = "DASH";
12745
12746         vlen = strlen(tp->fw_ver);
12747
12748         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12749                  fwtype,
12750                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12751                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12752                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12753                  (apedata & APE_FW_VERSION_BLDMSK));
12754 }
12755
12756 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12757 {
12758         u32 val;
12759         bool vpd_vers = false;
12760
12761         if (tp->fw_ver[0] != 0)
12762                 vpd_vers = true;
12763
12764         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12765                 strcat(tp->fw_ver, "sb");
12766                 return;
12767         }
12768
12769         if (tg3_nvram_read(tp, 0, &val))
12770                 return;
12771
12772         if (val == TG3_EEPROM_MAGIC)
12773                 tg3_read_bc_ver(tp);
12774         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12775                 tg3_read_sb_ver(tp, val);
12776         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12777                 tg3_read_hwsb_ver(tp);
12778         else
12779                 return;
12780
12781         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12782              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12783                 goto done;
12784
12785         tg3_read_mgmtfw_ver(tp);
12786
12787 done:
12788         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12789 }
12790
12791 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12792
12793 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12794 {
12795 #if TG3_VLAN_TAG_USED
12796         dev->vlan_features |= flags;
12797 #endif
12798 }
12799
12800 static int __devinit tg3_get_invariants(struct tg3 *tp)
12801 {
12802         static struct pci_device_id write_reorder_chipsets[] = {
12803                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12804                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12805                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12806                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12807                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12808                              PCI_DEVICE_ID_VIA_8385_0) },
12809                 { },
12810         };
12811         u32 misc_ctrl_reg;
12812         u32 pci_state_reg, grc_misc_cfg;
12813         u32 val;
12814         u16 pci_cmd;
12815         int err;
12816
12817         /* Force memory write invalidate off.  If we leave it on,
12818          * then on 5700_BX chips we have to enable a workaround.
12819          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12820          * to match the cacheline size.  The Broadcom driver have this
12821          * workaround but turns MWI off all the times so never uses
12822          * it.  This seems to suggest that the workaround is insufficient.
12823          */
12824         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12825         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12826         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12827
12828         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12829          * has the register indirect write enable bit set before
12830          * we try to access any of the MMIO registers.  It is also
12831          * critical that the PCI-X hw workaround situation is decided
12832          * before that as well.
12833          */
12834         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12835                               &misc_ctrl_reg);
12836
12837         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12838                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12839         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12840                 u32 prod_id_asic_rev;
12841
12842                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12843                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12844                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724 ||
12845                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12846                         pci_read_config_dword(tp->pdev,
12847                                               TG3PCI_GEN2_PRODID_ASICREV,
12848                                               &prod_id_asic_rev);
12849                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12850                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12851                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12852                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12853                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12854                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12855                         pci_read_config_dword(tp->pdev,
12856                                               TG3PCI_GEN15_PRODID_ASICREV,
12857                                               &prod_id_asic_rev);
12858                 else
12859                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12860                                               &prod_id_asic_rev);
12861
12862                 tp->pci_chip_rev_id = prod_id_asic_rev;
12863         }
12864
12865         /* Wrong chip ID in 5752 A0. This code can be removed later
12866          * as A0 is not in production.
12867          */
12868         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12869                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12870
12871         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12872          * we need to disable memory and use config. cycles
12873          * only to access all registers. The 5702/03 chips
12874          * can mistakenly decode the special cycles from the
12875          * ICH chipsets as memory write cycles, causing corruption
12876          * of register and memory space. Only certain ICH bridges
12877          * will drive special cycles with non-zero data during the
12878          * address phase which can fall within the 5703's address
12879          * range. This is not an ICH bug as the PCI spec allows
12880          * non-zero address during special cycles. However, only
12881          * these ICH bridges are known to drive non-zero addresses
12882          * during special cycles.
12883          *
12884          * Since special cycles do not cross PCI bridges, we only
12885          * enable this workaround if the 5703 is on the secondary
12886          * bus of these ICH bridges.
12887          */
12888         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12889             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12890                 static struct tg3_dev_id {
12891                         u32     vendor;
12892                         u32     device;
12893                         u32     rev;
12894                 } ich_chipsets[] = {
12895                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12896                           PCI_ANY_ID },
12897                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12898                           PCI_ANY_ID },
12899                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12900                           0xa },
12901                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12902                           PCI_ANY_ID },
12903                         { },
12904                 };
12905                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12906                 struct pci_dev *bridge = NULL;
12907
12908                 while (pci_id->vendor != 0) {
12909                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12910                                                 bridge);
12911                         if (!bridge) {
12912                                 pci_id++;
12913                                 continue;
12914                         }
12915                         if (pci_id->rev != PCI_ANY_ID) {
12916                                 if (bridge->revision > pci_id->rev)
12917                                         continue;
12918                         }
12919                         if (bridge->subordinate &&
12920                             (bridge->subordinate->number ==
12921                              tp->pdev->bus->number)) {
12922
12923                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12924                                 pci_dev_put(bridge);
12925                                 break;
12926                         }
12927                 }
12928         }
12929
12930         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12931                 static struct tg3_dev_id {
12932                         u32     vendor;
12933                         u32     device;
12934                 } bridge_chipsets[] = {
12935                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12936                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12937                         { },
12938                 };
12939                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12940                 struct pci_dev *bridge = NULL;
12941
12942                 while (pci_id->vendor != 0) {
12943                         bridge = pci_get_device(pci_id->vendor,
12944                                                 pci_id->device,
12945                                                 bridge);
12946                         if (!bridge) {
12947                                 pci_id++;
12948                                 continue;
12949                         }
12950                         if (bridge->subordinate &&
12951                             (bridge->subordinate->number <=
12952                              tp->pdev->bus->number) &&
12953                             (bridge->subordinate->subordinate >=
12954                              tp->pdev->bus->number)) {
12955                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12956                                 pci_dev_put(bridge);
12957                                 break;
12958                         }
12959                 }
12960         }
12961
12962         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12963          * DMA addresses > 40-bit. This bridge may have other additional
12964          * 57xx devices behind it in some 4-port NIC designs for example.
12965          * Any tg3 device found behind the bridge will also need the 40-bit
12966          * DMA workaround.
12967          */
12968         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12969             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12970                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12971                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12972                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12973         } else {
12974                 struct pci_dev *bridge = NULL;
12975
12976                 do {
12977                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12978                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12979                                                 bridge);
12980                         if (bridge && bridge->subordinate &&
12981                             (bridge->subordinate->number <=
12982                              tp->pdev->bus->number) &&
12983                             (bridge->subordinate->subordinate >=
12984                              tp->pdev->bus->number)) {
12985                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12986                                 pci_dev_put(bridge);
12987                                 break;
12988                         }
12989                 } while (bridge);
12990         }
12991
12992         /* Initialize misc host control in PCI block. */
12993         tp->misc_host_ctrl |= (misc_ctrl_reg &
12994                                MISC_HOST_CTRL_CHIPREV);
12995         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12996                                tp->misc_host_ctrl);
12997
12998         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13001                 tp->pdev_peer = tg3_find_peer(tp);
13002
13003         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13006                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13007
13008         /* Intentionally exclude ASIC_REV_5906 */
13009         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13010             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13012             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13013             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13015             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13016                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13017
13018         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13020             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13021             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13022             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13023                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13024
13025         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13026             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13027                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13028
13029         /* 5700 B0 chips do not support checksumming correctly due
13030          * to hardware bugs.
13031          */
13032         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13033                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13034         else {
13035                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13036
13037                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13038                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13039                         features |= NETIF_F_IPV6_CSUM;
13040                 tp->dev->features |= features;
13041                 vlan_features_add(tp->dev, features);
13042         }
13043
13044         /* Determine TSO capabilities */
13045         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13046                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13047         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13048                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13049                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13050         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13051                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13052                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13053                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13054                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13055         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13056                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13057                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13058                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13059                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13060                         tp->fw_needed = FIRMWARE_TG3TSO5;
13061                 else
13062                         tp->fw_needed = FIRMWARE_TG3TSO;
13063         }
13064
13065         tp->irq_max = 1;
13066
13067         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13068                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13069                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13070                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13071                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13072                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13073                      tp->pdev_peer == tp->pdev))
13074                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13075
13076                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13077                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13078                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13079                 }
13080
13081                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13082                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13083                         tp->irq_max = TG3_IRQ_MAX_VECS;
13084                 }
13085         }
13086
13087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13088             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13089             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13090                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13091         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13092                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13093                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13094         }
13095
13096         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13097                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13098
13099         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13100             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13101             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13102                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13103
13104         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13105                               &pci_state_reg);
13106
13107         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13108         if (tp->pcie_cap != 0) {
13109                 u16 lnkctl;
13110
13111                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13112
13113                 pcie_set_readrq(tp->pdev, 4096);
13114
13115                 pci_read_config_word(tp->pdev,
13116                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13117                                      &lnkctl);
13118                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13119                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13120                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13122                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13123                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13124                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13125                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13126                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13127                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13128                 }
13129         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13130                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13131         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13132                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13133                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13134                 if (!tp->pcix_cap) {
13135                         dev_err(&tp->pdev->dev,
13136                                 "Cannot find PCI-X capability, aborting\n");
13137                         return -EIO;
13138                 }
13139
13140                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13141                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13142         }
13143
13144         /* If we have an AMD 762 or VIA K8T800 chipset, write
13145          * reordering to the mailbox registers done by the host
13146          * controller can cause major troubles.  We read back from
13147          * every mailbox register write to force the writes to be
13148          * posted to the chip in order.
13149          */
13150         if (pci_dev_present(write_reorder_chipsets) &&
13151             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13152                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13153
13154         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13155                              &tp->pci_cacheline_sz);
13156         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13157                              &tp->pci_lat_timer);
13158         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13159             tp->pci_lat_timer < 64) {
13160                 tp->pci_lat_timer = 64;
13161                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13162                                       tp->pci_lat_timer);
13163         }
13164
13165         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13166                 /* 5700 BX chips need to have their TX producer index
13167                  * mailboxes written twice to workaround a bug.
13168                  */
13169                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13170
13171                 /* If we are in PCI-X mode, enable register write workaround.
13172                  *
13173                  * The workaround is to use indirect register accesses
13174                  * for all chip writes not to mailbox registers.
13175                  */
13176                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13177                         u32 pm_reg;
13178
13179                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13180
13181                         /* The chip can have it's power management PCI config
13182                          * space registers clobbered due to this bug.
13183                          * So explicitly force the chip into D0 here.
13184                          */
13185                         pci_read_config_dword(tp->pdev,
13186                                               tp->pm_cap + PCI_PM_CTRL,
13187                                               &pm_reg);
13188                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13189                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13190                         pci_write_config_dword(tp->pdev,
13191                                                tp->pm_cap + PCI_PM_CTRL,
13192                                                pm_reg);
13193
13194                         /* Also, force SERR#/PERR# in PCI command. */
13195                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13196                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13197                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13198                 }
13199         }
13200
13201         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13202                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13203         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13204                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13205
13206         /* Chip-specific fixup from Broadcom driver */
13207         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13208             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13209                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13210                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13211         }
13212
13213         /* Default fast path register access methods */
13214         tp->read32 = tg3_read32;
13215         tp->write32 = tg3_write32;
13216         tp->read32_mbox = tg3_read32;
13217         tp->write32_mbox = tg3_write32;
13218         tp->write32_tx_mbox = tg3_write32;
13219         tp->write32_rx_mbox = tg3_write32;
13220
13221         /* Various workaround register access methods */
13222         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13223                 tp->write32 = tg3_write_indirect_reg32;
13224         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13225                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13226                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13227                 /*
13228                  * Back to back register writes can cause problems on these
13229                  * chips, the workaround is to read back all reg writes
13230                  * except those to mailbox regs.
13231                  *
13232                  * See tg3_write_indirect_reg32().
13233                  */
13234                 tp->write32 = tg3_write_flush_reg32;
13235         }
13236
13237         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13238             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13239                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13240                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13241                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13242         }
13243
13244         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13245                 tp->read32 = tg3_read_indirect_reg32;
13246                 tp->write32 = tg3_write_indirect_reg32;
13247                 tp->read32_mbox = tg3_read_indirect_mbox;
13248                 tp->write32_mbox = tg3_write_indirect_mbox;
13249                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13250                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13251
13252                 iounmap(tp->regs);
13253                 tp->regs = NULL;
13254
13255                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13256                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13257                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13258         }
13259         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13260                 tp->read32_mbox = tg3_read32_mbox_5906;
13261                 tp->write32_mbox = tg3_write32_mbox_5906;
13262                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13263                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13264         }
13265
13266         if (tp->write32 == tg3_write_indirect_reg32 ||
13267             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13268              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13269               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13270                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13271
13272         /* Get eeprom hw config before calling tg3_set_power_state().
13273          * In particular, the TG3_FLG2_IS_NIC flag must be
13274          * determined before calling tg3_set_power_state() so that
13275          * we know whether or not to switch out of Vaux power.
13276          * When the flag is set, it means that GPIO1 is used for eeprom
13277          * write protect and also implies that it is a LOM where GPIOs
13278          * are not used to switch power.
13279          */
13280         tg3_get_eeprom_hw_cfg(tp);
13281
13282         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13283                 /* Allow reads and writes to the
13284                  * APE register and memory space.
13285                  */
13286                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13287                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13288                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13289                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13290                                        pci_state_reg);
13291         }
13292
13293         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13294             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13295             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13296             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13297             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13298                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13299
13300         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13301          * GPIO1 driven high will bring 5700's external PHY out of reset.
13302          * It is also used as eeprom write protect on LOMs.
13303          */
13304         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13305         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13306             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13307                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13308                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13309         /* Unused GPIO3 must be driven as output on 5752 because there
13310          * are no pull-up resistors on unused GPIO pins.
13311          */
13312         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13313                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13314
13315         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13316             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13317             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13318                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13319
13320         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13321             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13322                 /* Turn off the debug UART. */
13323                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13324                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13325                         /* Keep VMain power. */
13326                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13327                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13328         }
13329
13330         /* Force the chip into D0. */
13331         err = tg3_set_power_state(tp, PCI_D0);
13332         if (err) {
13333                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13334                 return err;
13335         }
13336
13337         /* Derive initial jumbo mode from MTU assigned in
13338          * ether_setup() via the alloc_etherdev() call
13339          */
13340         if (tp->dev->mtu > ETH_DATA_LEN &&
13341             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13342                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13343
13344         /* Determine WakeOnLan speed to use. */
13345         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13346             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13347             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13348             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13349                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13350         } else {
13351                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13352         }
13353
13354         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13355                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13356
13357         /* A few boards don't want Ethernet@WireSpeed phy feature */
13358         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13359             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13360              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13361              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13362             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13363             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13364                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13365
13366         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13367             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13368                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13369         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13370                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13371
13372         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13373             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13374             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13375             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13376             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13377                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13378                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13379                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13380                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13381                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13382                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13383                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13384                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13385                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13386                 } else
13387                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13388         }
13389
13390         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13391             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13392                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13393                 if (tp->phy_otp == 0)
13394                         tp->phy_otp = TG3_OTP_DEFAULT;
13395         }
13396
13397         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13398                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13399         else
13400                 tp->mi_mode = MAC_MI_MODE_BASE;
13401
13402         tp->coalesce_mode = 0;
13403         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13404             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13405                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13406
13407         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13408             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13409                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13410
13411         err = tg3_mdio_init(tp);
13412         if (err)
13413                 return err;
13414
13415         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13416             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
13417                 return -ENOTSUPP;
13418
13419         /* Initialize data/descriptor byte/word swapping. */
13420         val = tr32(GRC_MODE);
13421         val &= GRC_MODE_HOST_STACKUP;
13422         tw32(GRC_MODE, val | tp->grc_mode);
13423
13424         tg3_switch_clocks(tp);
13425
13426         /* Clear this out for sanity. */
13427         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13428
13429         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13430                               &pci_state_reg);
13431         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13432             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13433                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13434
13435                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13436                     chiprevid == CHIPREV_ID_5701_B0 ||
13437                     chiprevid == CHIPREV_ID_5701_B2 ||
13438                     chiprevid == CHIPREV_ID_5701_B5) {
13439                         void __iomem *sram_base;
13440
13441                         /* Write some dummy words into the SRAM status block
13442                          * area, see if it reads back correctly.  If the return
13443                          * value is bad, force enable the PCIX workaround.
13444                          */
13445                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13446
13447                         writel(0x00000000, sram_base);
13448                         writel(0x00000000, sram_base + 4);
13449                         writel(0xffffffff, sram_base + 4);
13450                         if (readl(sram_base) != 0x00000000)
13451                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13452                 }
13453         }
13454
13455         udelay(50);
13456         tg3_nvram_init(tp);
13457
13458         grc_misc_cfg = tr32(GRC_MISC_CFG);
13459         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13460
13461         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13462             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13463              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13464                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13465
13466         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13467             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13468                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13469         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13470                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13471                                       HOSTCC_MODE_CLRTICK_TXBD);
13472
13473                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13474                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13475                                        tp->misc_host_ctrl);
13476         }
13477
13478         /* Preserve the APE MAC_MODE bits */
13479         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13480                 tp->mac_mode = tr32(MAC_MODE) |
13481                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13482         else
13483                 tp->mac_mode = TG3_DEF_MAC_MODE;
13484
13485         /* these are limited to 10/100 only */
13486         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13487              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13488             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13489              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13490              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13491               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13492               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13493             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13494              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13495               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13496               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13497             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13498             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13499             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13500             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13501                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13502
13503         err = tg3_phy_probe(tp);
13504         if (err) {
13505                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13506                 /* ... but do not return immediately ... */
13507                 tg3_mdio_fini(tp);
13508         }
13509
13510         tg3_read_vpd(tp);
13511         tg3_read_fw_ver(tp);
13512
13513         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13514                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13515         } else {
13516                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13517                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13518                 else
13519                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13520         }
13521
13522         /* 5700 {AX,BX} chips have a broken status block link
13523          * change bit implementation, so we must use the
13524          * status register in those cases.
13525          */
13526         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13527                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13528         else
13529                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13530
13531         /* The led_ctrl is set during tg3_phy_probe, here we might
13532          * have to force the link status polling mechanism based
13533          * upon subsystem IDs.
13534          */
13535         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13536             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13537             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13538                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13539                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13540         }
13541
13542         /* For all SERDES we poll the MAC status register. */
13543         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13544                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13545         else
13546                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13547
13548         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13549         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13550         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13551             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13552                 tp->rx_offset -= NET_IP_ALIGN;
13553 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13554                 tp->rx_copy_thresh = ~(u16)0;
13555 #endif
13556         }
13557
13558         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13559
13560         /* Increment the rx prod index on the rx std ring by at most
13561          * 8 for these chips to workaround hw errata.
13562          */
13563         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13564             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13565             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13566                 tp->rx_std_max_post = 8;
13567
13568         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13569                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13570                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13571
13572         return err;
13573 }
13574
13575 #ifdef CONFIG_SPARC
13576 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13577 {
13578         struct net_device *dev = tp->dev;
13579         struct pci_dev *pdev = tp->pdev;
13580         struct device_node *dp = pci_device_to_OF_node(pdev);
13581         const unsigned char *addr;
13582         int len;
13583
13584         addr = of_get_property(dp, "local-mac-address", &len);
13585         if (addr && len == 6) {
13586                 memcpy(dev->dev_addr, addr, 6);
13587                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13588                 return 0;
13589         }
13590         return -ENODEV;
13591 }
13592
13593 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13594 {
13595         struct net_device *dev = tp->dev;
13596
13597         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13598         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13599         return 0;
13600 }
13601 #endif
13602
13603 static int __devinit tg3_get_device_address(struct tg3 *tp)
13604 {
13605         struct net_device *dev = tp->dev;
13606         u32 hi, lo, mac_offset;
13607         int addr_ok = 0;
13608
13609 #ifdef CONFIG_SPARC
13610         if (!tg3_get_macaddr_sparc(tp))
13611                 return 0;
13612 #endif
13613
13614         mac_offset = 0x7c;
13615         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13616             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13617                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13618                         mac_offset = 0xcc;
13619                 if (tg3_nvram_lock(tp))
13620                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13621                 else
13622                         tg3_nvram_unlock(tp);
13623         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13624                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13625                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13626                         mac_offset = 0xcc;
13627                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13628                         mac_offset += 0x18c;
13629         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13630                 mac_offset = 0x10;
13631
13632         /* First try to get it from MAC address mailbox. */
13633         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13634         if ((hi >> 16) == 0x484b) {
13635                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13636                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13637
13638                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13639                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13640                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13641                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13642                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13643
13644                 /* Some old bootcode may report a 0 MAC address in SRAM */
13645                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13646         }
13647         if (!addr_ok) {
13648                 /* Next, try NVRAM. */
13649                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13650                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13651                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13652                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13653                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13654                 }
13655                 /* Finally just fetch it out of the MAC control regs. */
13656                 else {
13657                         hi = tr32(MAC_ADDR_0_HIGH);
13658                         lo = tr32(MAC_ADDR_0_LOW);
13659
13660                         dev->dev_addr[5] = lo & 0xff;
13661                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13662                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13663                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13664                         dev->dev_addr[1] = hi & 0xff;
13665                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13666                 }
13667         }
13668
13669         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13670 #ifdef CONFIG_SPARC
13671                 if (!tg3_get_default_macaddr_sparc(tp))
13672                         return 0;
13673 #endif
13674                 return -EINVAL;
13675         }
13676         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13677         return 0;
13678 }
13679
13680 #define BOUNDARY_SINGLE_CACHELINE       1
13681 #define BOUNDARY_MULTI_CACHELINE        2
13682
13683 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13684 {
13685         int cacheline_size;
13686         u8 byte;
13687         int goal;
13688
13689         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13690         if (byte == 0)
13691                 cacheline_size = 1024;
13692         else
13693                 cacheline_size = (int) byte * 4;
13694
13695         /* On 5703 and later chips, the boundary bits have no
13696          * effect.
13697          */
13698         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13699             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13700             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13701                 goto out;
13702
13703 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13704         goal = BOUNDARY_MULTI_CACHELINE;
13705 #else
13706 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13707         goal = BOUNDARY_SINGLE_CACHELINE;
13708 #else
13709         goal = 0;
13710 #endif
13711 #endif
13712
13713         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13714                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13715                 goto out;
13716         }
13717
13718         if (!goal)
13719                 goto out;
13720
13721         /* PCI controllers on most RISC systems tend to disconnect
13722          * when a device tries to burst across a cache-line boundary.
13723          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13724          *
13725          * Unfortunately, for PCI-E there are only limited
13726          * write-side controls for this, and thus for reads
13727          * we will still get the disconnects.  We'll also waste
13728          * these PCI cycles for both read and write for chips
13729          * other than 5700 and 5701 which do not implement the
13730          * boundary bits.
13731          */
13732         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13733             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13734                 switch (cacheline_size) {
13735                 case 16:
13736                 case 32:
13737                 case 64:
13738                 case 128:
13739                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13740                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13741                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13742                         } else {
13743                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13744                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13745                         }
13746                         break;
13747
13748                 case 256:
13749                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13750                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13751                         break;
13752
13753                 default:
13754                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13755                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13756                         break;
13757                 }
13758         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13759                 switch (cacheline_size) {
13760                 case 16:
13761                 case 32:
13762                 case 64:
13763                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13764                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13765                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13766                                 break;
13767                         }
13768                         /* fallthrough */
13769                 case 128:
13770                 default:
13771                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13772                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13773                         break;
13774                 }
13775         } else {
13776                 switch (cacheline_size) {
13777                 case 16:
13778                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13779                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13780                                         DMA_RWCTRL_WRITE_BNDRY_16);
13781                                 break;
13782                         }
13783                         /* fallthrough */
13784                 case 32:
13785                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13786                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13787                                         DMA_RWCTRL_WRITE_BNDRY_32);
13788                                 break;
13789                         }
13790                         /* fallthrough */
13791                 case 64:
13792                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13793                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13794                                         DMA_RWCTRL_WRITE_BNDRY_64);
13795                                 break;
13796                         }
13797                         /* fallthrough */
13798                 case 128:
13799                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13800                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13801                                         DMA_RWCTRL_WRITE_BNDRY_128);
13802                                 break;
13803                         }
13804                         /* fallthrough */
13805                 case 256:
13806                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13807                                 DMA_RWCTRL_WRITE_BNDRY_256);
13808                         break;
13809                 case 512:
13810                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13811                                 DMA_RWCTRL_WRITE_BNDRY_512);
13812                         break;
13813                 case 1024:
13814                 default:
13815                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13816                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13817                         break;
13818                 }
13819         }
13820
13821 out:
13822         return val;
13823 }
13824
13825 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13826 {
13827         struct tg3_internal_buffer_desc test_desc;
13828         u32 sram_dma_descs;
13829         int i, ret;
13830
13831         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13832
13833         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13834         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13835         tw32(RDMAC_STATUS, 0);
13836         tw32(WDMAC_STATUS, 0);
13837
13838         tw32(BUFMGR_MODE, 0);
13839         tw32(FTQ_RESET, 0);
13840
13841         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13842         test_desc.addr_lo = buf_dma & 0xffffffff;
13843         test_desc.nic_mbuf = 0x00002100;
13844         test_desc.len = size;
13845
13846         /*
13847          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13848          * the *second* time the tg3 driver was getting loaded after an
13849          * initial scan.
13850          *
13851          * Broadcom tells me:
13852          *   ...the DMA engine is connected to the GRC block and a DMA
13853          *   reset may affect the GRC block in some unpredictable way...
13854          *   The behavior of resets to individual blocks has not been tested.
13855          *
13856          * Broadcom noted the GRC reset will also reset all sub-components.
13857          */
13858         if (to_device) {
13859                 test_desc.cqid_sqid = (13 << 8) | 2;
13860
13861                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13862                 udelay(40);
13863         } else {
13864                 test_desc.cqid_sqid = (16 << 8) | 7;
13865
13866                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13867                 udelay(40);
13868         }
13869         test_desc.flags = 0x00000005;
13870
13871         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13872                 u32 val;
13873
13874                 val = *(((u32 *)&test_desc) + i);
13875                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13876                                        sram_dma_descs + (i * sizeof(u32)));
13877                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13878         }
13879         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13880
13881         if (to_device)
13882                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13883         else
13884                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13885
13886         ret = -ENODEV;
13887         for (i = 0; i < 40; i++) {
13888                 u32 val;
13889
13890                 if (to_device)
13891                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13892                 else
13893                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13894                 if ((val & 0xffff) == sram_dma_descs) {
13895                         ret = 0;
13896                         break;
13897                 }
13898
13899                 udelay(100);
13900         }
13901
13902         return ret;
13903 }
13904
13905 #define TEST_BUFFER_SIZE        0x2000
13906
13907 static int __devinit tg3_test_dma(struct tg3 *tp)
13908 {
13909         dma_addr_t buf_dma;
13910         u32 *buf, saved_dma_rwctrl;
13911         int ret = 0;
13912
13913         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13914         if (!buf) {
13915                 ret = -ENOMEM;
13916                 goto out_nofree;
13917         }
13918
13919         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13920                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13921
13922         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13923
13924         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13925                 goto out;
13926
13927         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13928                 /* DMA read watermark not used on PCIE */
13929                 tp->dma_rwctrl |= 0x00180000;
13930         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13931                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13932                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13933                         tp->dma_rwctrl |= 0x003f0000;
13934                 else
13935                         tp->dma_rwctrl |= 0x003f000f;
13936         } else {
13937                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13938                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13939                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13940                         u32 read_water = 0x7;
13941
13942                         /* If the 5704 is behind the EPB bridge, we can
13943                          * do the less restrictive ONE_DMA workaround for
13944                          * better performance.
13945                          */
13946                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13947                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13948                                 tp->dma_rwctrl |= 0x8000;
13949                         else if (ccval == 0x6 || ccval == 0x7)
13950                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13951
13952                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13953                                 read_water = 4;
13954                         /* Set bit 23 to enable PCIX hw bug fix */
13955                         tp->dma_rwctrl |=
13956                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13957                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13958                                 (1 << 23);
13959                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13960                         /* 5780 always in PCIX mode */
13961                         tp->dma_rwctrl |= 0x00144000;
13962                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13963                         /* 5714 always in PCIX mode */
13964                         tp->dma_rwctrl |= 0x00148000;
13965                 } else {
13966                         tp->dma_rwctrl |= 0x001b000f;
13967                 }
13968         }
13969
13970         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13971             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13972                 tp->dma_rwctrl &= 0xfffffff0;
13973
13974         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13975             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13976                 /* Remove this if it causes problems for some boards. */
13977                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13978
13979                 /* On 5700/5701 chips, we need to set this bit.
13980                  * Otherwise the chip will issue cacheline transactions
13981                  * to streamable DMA memory with not all the byte
13982                  * enables turned on.  This is an error on several
13983                  * RISC PCI controllers, in particular sparc64.
13984                  *
13985                  * On 5703/5704 chips, this bit has been reassigned
13986                  * a different meaning.  In particular, it is used
13987                  * on those chips to enable a PCI-X workaround.
13988                  */
13989                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13990         }
13991
13992         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13993
13994 #if 0
13995         /* Unneeded, already done by tg3_get_invariants.  */
13996         tg3_switch_clocks(tp);
13997 #endif
13998
13999         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14000             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14001                 goto out;
14002
14003         /* It is best to perform DMA test with maximum write burst size
14004          * to expose the 5700/5701 write DMA bug.
14005          */
14006         saved_dma_rwctrl = tp->dma_rwctrl;
14007         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14008         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14009
14010         while (1) {
14011                 u32 *p = buf, i;
14012
14013                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14014                         p[i] = i;
14015
14016                 /* Send the buffer to the chip. */
14017                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14018                 if (ret) {
14019                         dev_err(&tp->pdev->dev,
14020                                 "%s: Buffer write failed. err = %d\n",
14021                                 __func__, ret);
14022                         break;
14023                 }
14024
14025 #if 0
14026                 /* validate data reached card RAM correctly. */
14027                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14028                         u32 val;
14029                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14030                         if (le32_to_cpu(val) != p[i]) {
14031                                 dev_err(&tp->pdev->dev,
14032                                         "%s: Buffer corrupted on device! "
14033                                         "(%d != %d)\n", __func__, val, i);
14034                                 /* ret = -ENODEV here? */
14035                         }
14036                         p[i] = 0;
14037                 }
14038 #endif
14039                 /* Now read it back. */
14040                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14041                 if (ret) {
14042                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14043                                 "err = %d\n", __func__, ret);
14044                         break;
14045                 }
14046
14047                 /* Verify it. */
14048                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14049                         if (p[i] == i)
14050                                 continue;
14051
14052                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14053                             DMA_RWCTRL_WRITE_BNDRY_16) {
14054                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14055                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14056                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14057                                 break;
14058                         } else {
14059                                 dev_err(&tp->pdev->dev,
14060                                         "%s: Buffer corrupted on read back! "
14061                                         "(%d != %d)\n", __func__, p[i], i);
14062                                 ret = -ENODEV;
14063                                 goto out;
14064                         }
14065                 }
14066
14067                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14068                         /* Success. */
14069                         ret = 0;
14070                         break;
14071                 }
14072         }
14073         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14074             DMA_RWCTRL_WRITE_BNDRY_16) {
14075                 static struct pci_device_id dma_wait_state_chipsets[] = {
14076                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14077                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14078                         { },
14079                 };
14080
14081                 /* DMA test passed without adjusting DMA boundary,
14082                  * now look for chipsets that are known to expose the
14083                  * DMA bug without failing the test.
14084                  */
14085                 if (pci_dev_present(dma_wait_state_chipsets)) {
14086                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14087                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14088                 } else {
14089                         /* Safe to use the calculated DMA boundary. */
14090                         tp->dma_rwctrl = saved_dma_rwctrl;
14091                 }
14092
14093                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14094         }
14095
14096 out:
14097         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14098 out_nofree:
14099         return ret;
14100 }
14101
14102 static void __devinit tg3_init_link_config(struct tg3 *tp)
14103 {
14104         tp->link_config.advertising =
14105                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14106                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14107                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14108                  ADVERTISED_Autoneg | ADVERTISED_MII);
14109         tp->link_config.speed = SPEED_INVALID;
14110         tp->link_config.duplex = DUPLEX_INVALID;
14111         tp->link_config.autoneg = AUTONEG_ENABLE;
14112         tp->link_config.active_speed = SPEED_INVALID;
14113         tp->link_config.active_duplex = DUPLEX_INVALID;
14114         tp->link_config.orig_speed = SPEED_INVALID;
14115         tp->link_config.orig_duplex = DUPLEX_INVALID;
14116         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14117 }
14118
14119 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14120 {
14121         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14122                 tp->bufmgr_config.mbuf_read_dma_low_water =
14123                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14124                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14125                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14126                 tp->bufmgr_config.mbuf_high_water =
14127                         DEFAULT_MB_HIGH_WATER_57765;
14128
14129                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14130                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14131                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14132                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14133                 tp->bufmgr_config.mbuf_high_water_jumbo =
14134                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14135         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14136                 tp->bufmgr_config.mbuf_read_dma_low_water =
14137                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14138                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14139                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14140                 tp->bufmgr_config.mbuf_high_water =
14141                         DEFAULT_MB_HIGH_WATER_5705;
14142                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14143                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14144                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14145                         tp->bufmgr_config.mbuf_high_water =
14146                                 DEFAULT_MB_HIGH_WATER_5906;
14147                 }
14148
14149                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14150                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14151                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14152                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14153                 tp->bufmgr_config.mbuf_high_water_jumbo =
14154                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14155         } else {
14156                 tp->bufmgr_config.mbuf_read_dma_low_water =
14157                         DEFAULT_MB_RDMA_LOW_WATER;
14158                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14159                         DEFAULT_MB_MACRX_LOW_WATER;
14160                 tp->bufmgr_config.mbuf_high_water =
14161                         DEFAULT_MB_HIGH_WATER;
14162
14163                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14164                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14165                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14166                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14167                 tp->bufmgr_config.mbuf_high_water_jumbo =
14168                         DEFAULT_MB_HIGH_WATER_JUMBO;
14169         }
14170
14171         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14172         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14173 }
14174
14175 static char * __devinit tg3_phy_string(struct tg3 *tp)
14176 {
14177         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14178         case TG3_PHY_ID_BCM5400:        return "5400";
14179         case TG3_PHY_ID_BCM5401:        return "5401";
14180         case TG3_PHY_ID_BCM5411:        return "5411";
14181         case TG3_PHY_ID_BCM5701:        return "5701";
14182         case TG3_PHY_ID_BCM5703:        return "5703";
14183         case TG3_PHY_ID_BCM5704:        return "5704";
14184         case TG3_PHY_ID_BCM5705:        return "5705";
14185         case TG3_PHY_ID_BCM5750:        return "5750";
14186         case TG3_PHY_ID_BCM5752:        return "5752";
14187         case TG3_PHY_ID_BCM5714:        return "5714";
14188         case TG3_PHY_ID_BCM5780:        return "5780";
14189         case TG3_PHY_ID_BCM5755:        return "5755";
14190         case TG3_PHY_ID_BCM5787:        return "5787";
14191         case TG3_PHY_ID_BCM5784:        return "5784";
14192         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14193         case TG3_PHY_ID_BCM5906:        return "5906";
14194         case TG3_PHY_ID_BCM5761:        return "5761";
14195         case TG3_PHY_ID_BCM5718C:       return "5718C";
14196         case TG3_PHY_ID_BCM5718S:       return "5718S";
14197         case TG3_PHY_ID_BCM57765:       return "57765";
14198         case TG3_PHY_ID_BCM5719C:       return "5719C";
14199         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14200         case 0:                 return "serdes";
14201         default:                return "unknown";
14202         }
14203 }
14204
14205 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14206 {
14207         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14208                 strcpy(str, "PCI Express");
14209                 return str;
14210         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14211                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14212
14213                 strcpy(str, "PCIX:");
14214
14215                 if ((clock_ctrl == 7) ||
14216                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14217                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14218                         strcat(str, "133MHz");
14219                 else if (clock_ctrl == 0)
14220                         strcat(str, "33MHz");
14221                 else if (clock_ctrl == 2)
14222                         strcat(str, "50MHz");
14223                 else if (clock_ctrl == 4)
14224                         strcat(str, "66MHz");
14225                 else if (clock_ctrl == 6)
14226                         strcat(str, "100MHz");
14227         } else {
14228                 strcpy(str, "PCI:");
14229                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14230                         strcat(str, "66MHz");
14231                 else
14232                         strcat(str, "33MHz");
14233         }
14234         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14235                 strcat(str, ":32-bit");
14236         else
14237                 strcat(str, ":64-bit");
14238         return str;
14239 }
14240
14241 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14242 {
14243         struct pci_dev *peer;
14244         unsigned int func, devnr = tp->pdev->devfn & ~7;
14245
14246         for (func = 0; func < 8; func++) {
14247                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14248                 if (peer && peer != tp->pdev)
14249                         break;
14250                 pci_dev_put(peer);
14251         }
14252         /* 5704 can be configured in single-port mode, set peer to
14253          * tp->pdev in that case.
14254          */
14255         if (!peer) {
14256                 peer = tp->pdev;
14257                 return peer;
14258         }
14259
14260         /*
14261          * We don't need to keep the refcount elevated; there's no way
14262          * to remove one half of this device without removing the other
14263          */
14264         pci_dev_put(peer);
14265
14266         return peer;
14267 }
14268
14269 static void __devinit tg3_init_coal(struct tg3 *tp)
14270 {
14271         struct ethtool_coalesce *ec = &tp->coal;
14272
14273         memset(ec, 0, sizeof(*ec));
14274         ec->cmd = ETHTOOL_GCOALESCE;
14275         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14276         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14277         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14278         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14279         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14280         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14281         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14282         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14283         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14284
14285         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14286                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14287                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14288                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14289                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14290                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14291         }
14292
14293         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14294                 ec->rx_coalesce_usecs_irq = 0;
14295                 ec->tx_coalesce_usecs_irq = 0;
14296                 ec->stats_block_coalesce_usecs = 0;
14297         }
14298 }
14299
14300 static const struct net_device_ops tg3_netdev_ops = {
14301         .ndo_open               = tg3_open,
14302         .ndo_stop               = tg3_close,
14303         .ndo_start_xmit         = tg3_start_xmit,
14304         .ndo_get_stats64        = tg3_get_stats64,
14305         .ndo_validate_addr      = eth_validate_addr,
14306         .ndo_set_multicast_list = tg3_set_rx_mode,
14307         .ndo_set_mac_address    = tg3_set_mac_addr,
14308         .ndo_do_ioctl           = tg3_ioctl,
14309         .ndo_tx_timeout         = tg3_tx_timeout,
14310         .ndo_change_mtu         = tg3_change_mtu,
14311 #if TG3_VLAN_TAG_USED
14312         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14313 #endif
14314 #ifdef CONFIG_NET_POLL_CONTROLLER
14315         .ndo_poll_controller    = tg3_poll_controller,
14316 #endif
14317 };
14318
14319 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14320         .ndo_open               = tg3_open,
14321         .ndo_stop               = tg3_close,
14322         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14323         .ndo_get_stats64        = tg3_get_stats64,
14324         .ndo_validate_addr      = eth_validate_addr,
14325         .ndo_set_multicast_list = tg3_set_rx_mode,
14326         .ndo_set_mac_address    = tg3_set_mac_addr,
14327         .ndo_do_ioctl           = tg3_ioctl,
14328         .ndo_tx_timeout         = tg3_tx_timeout,
14329         .ndo_change_mtu         = tg3_change_mtu,
14330 #if TG3_VLAN_TAG_USED
14331         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14332 #endif
14333 #ifdef CONFIG_NET_POLL_CONTROLLER
14334         .ndo_poll_controller    = tg3_poll_controller,
14335 #endif
14336 };
14337
14338 static int __devinit tg3_init_one(struct pci_dev *pdev,
14339                                   const struct pci_device_id *ent)
14340 {
14341         struct net_device *dev;
14342         struct tg3 *tp;
14343         int i, err, pm_cap;
14344         u32 sndmbx, rcvmbx, intmbx;
14345         char str[40];
14346         u64 dma_mask, persist_dma_mask;
14347
14348         printk_once(KERN_INFO "%s\n", version);
14349
14350         err = pci_enable_device(pdev);
14351         if (err) {
14352                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14353                 return err;
14354         }
14355
14356         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14357         if (err) {
14358                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14359                 goto err_out_disable_pdev;
14360         }
14361
14362         pci_set_master(pdev);
14363
14364         /* Find power-management capability. */
14365         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14366         if (pm_cap == 0) {
14367                 dev_err(&pdev->dev,
14368                         "Cannot find Power Management capability, aborting\n");
14369                 err = -EIO;
14370                 goto err_out_free_res;
14371         }
14372
14373         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14374         if (!dev) {
14375                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14376                 err = -ENOMEM;
14377                 goto err_out_free_res;
14378         }
14379
14380         SET_NETDEV_DEV(dev, &pdev->dev);
14381
14382 #if TG3_VLAN_TAG_USED
14383         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14384 #endif
14385
14386         tp = netdev_priv(dev);
14387         tp->pdev = pdev;
14388         tp->dev = dev;
14389         tp->pm_cap = pm_cap;
14390         tp->rx_mode = TG3_DEF_RX_MODE;
14391         tp->tx_mode = TG3_DEF_TX_MODE;
14392
14393         if (tg3_debug > 0)
14394                 tp->msg_enable = tg3_debug;
14395         else
14396                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14397
14398         /* The word/byte swap controls here control register access byte
14399          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14400          * setting below.
14401          */
14402         tp->misc_host_ctrl =
14403                 MISC_HOST_CTRL_MASK_PCI_INT |
14404                 MISC_HOST_CTRL_WORD_SWAP |
14405                 MISC_HOST_CTRL_INDIR_ACCESS |
14406                 MISC_HOST_CTRL_PCISTATE_RW;
14407
14408         /* The NONFRM (non-frame) byte/word swap controls take effect
14409          * on descriptor entries, anything which isn't packet data.
14410          *
14411          * The StrongARM chips on the board (one for tx, one for rx)
14412          * are running in big-endian mode.
14413          */
14414         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14415                         GRC_MODE_WSWAP_NONFRM_DATA);
14416 #ifdef __BIG_ENDIAN
14417         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14418 #endif
14419         spin_lock_init(&tp->lock);
14420         spin_lock_init(&tp->indirect_lock);
14421         INIT_WORK(&tp->reset_task, tg3_reset_task);
14422
14423         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14424         if (!tp->regs) {
14425                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14426                 err = -ENOMEM;
14427                 goto err_out_free_dev;
14428         }
14429
14430         tg3_init_link_config(tp);
14431
14432         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14433         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14434
14435         dev->ethtool_ops = &tg3_ethtool_ops;
14436         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14437         dev->irq = pdev->irq;
14438
14439         err = tg3_get_invariants(tp);
14440         if (err) {
14441                 dev_err(&pdev->dev,
14442                         "Problem fetching invariants of chip, aborting\n");
14443                 goto err_out_iounmap;
14444         }
14445
14446         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14447             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 &&
14448             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14449                 dev->netdev_ops = &tg3_netdev_ops;
14450         else
14451                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14452
14453
14454         /* The EPB bridge inside 5714, 5715, and 5780 and any
14455          * device behind the EPB cannot support DMA addresses > 40-bit.
14456          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14457          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14458          * do DMA address check in tg3_start_xmit().
14459          */
14460         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14461                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14462         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14463                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14464 #ifdef CONFIG_HIGHMEM
14465                 dma_mask = DMA_BIT_MASK(64);
14466 #endif
14467         } else
14468                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14469
14470         /* Configure DMA attributes. */
14471         if (dma_mask > DMA_BIT_MASK(32)) {
14472                 err = pci_set_dma_mask(pdev, dma_mask);
14473                 if (!err) {
14474                         dev->features |= NETIF_F_HIGHDMA;
14475                         err = pci_set_consistent_dma_mask(pdev,
14476                                                           persist_dma_mask);
14477                         if (err < 0) {
14478                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14479                                         "DMA for consistent allocations\n");
14480                                 goto err_out_iounmap;
14481                         }
14482                 }
14483         }
14484         if (err || dma_mask == DMA_BIT_MASK(32)) {
14485                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14486                 if (err) {
14487                         dev_err(&pdev->dev,
14488                                 "No usable DMA configuration, aborting\n");
14489                         goto err_out_iounmap;
14490                 }
14491         }
14492
14493         tg3_init_bufmgr_config(tp);
14494
14495         /* Selectively allow TSO based on operating conditions */
14496         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14497             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14498                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14499         else {
14500                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14501                 tp->fw_needed = NULL;
14502         }
14503
14504         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14505                 tp->fw_needed = FIRMWARE_TG3;
14506
14507         /* TSO is on by default on chips that support hardware TSO.
14508          * Firmware TSO on older chips gives lower performance, so it
14509          * is off by default, but can be enabled using ethtool.
14510          */
14511         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14512             (dev->features & NETIF_F_IP_CSUM)) {
14513                 dev->features |= NETIF_F_TSO;
14514                 vlan_features_add(dev, NETIF_F_TSO);
14515         }
14516         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14517             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14518                 if (dev->features & NETIF_F_IPV6_CSUM) {
14519                         dev->features |= NETIF_F_TSO6;
14520                         vlan_features_add(dev, NETIF_F_TSO6);
14521                 }
14522                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14523                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14524                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14525                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14526                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14527                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14528                         dev->features |= NETIF_F_TSO_ECN;
14529                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14530                 }
14531         }
14532
14533         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14534             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14535             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14536                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14537                 tp->rx_pending = 63;
14538         }
14539
14540         err = tg3_get_device_address(tp);
14541         if (err) {
14542                 dev_err(&pdev->dev,
14543                         "Could not obtain valid ethernet address, aborting\n");
14544                 goto err_out_iounmap;
14545         }
14546
14547         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14548                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14549                 if (!tp->aperegs) {
14550                         dev_err(&pdev->dev,
14551                                 "Cannot map APE registers, aborting\n");
14552                         err = -ENOMEM;
14553                         goto err_out_iounmap;
14554                 }
14555
14556                 tg3_ape_lock_init(tp);
14557
14558                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14559                         tg3_read_dash_ver(tp);
14560         }
14561
14562         /*
14563          * Reset chip in case UNDI or EFI driver did not shutdown
14564          * DMA self test will enable WDMAC and we'll see (spurious)
14565          * pending DMA on the PCI bus at that point.
14566          */
14567         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14568             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14569                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14570                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14571         }
14572
14573         err = tg3_test_dma(tp);
14574         if (err) {
14575                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14576                 goto err_out_apeunmap;
14577         }
14578
14579         /* flow control autonegotiation is default behavior */
14580         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14581         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14582
14583         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14584         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14585         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14586         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14587                 struct tg3_napi *tnapi = &tp->napi[i];
14588
14589                 tnapi->tp = tp;
14590                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14591
14592                 tnapi->int_mbox = intmbx;
14593                 if (i < 4)
14594                         intmbx += 0x8;
14595                 else
14596                         intmbx += 0x4;
14597
14598                 tnapi->consmbox = rcvmbx;
14599                 tnapi->prodmbox = sndmbx;
14600
14601                 if (i) {
14602                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14603                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14604                 } else {
14605                         tnapi->coal_now = HOSTCC_MODE_NOW;
14606                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14607                 }
14608
14609                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14610                         break;
14611
14612                 /*
14613                  * If we support MSIX, we'll be using RSS.  If we're using
14614                  * RSS, the first vector only handles link interrupts and the
14615                  * remaining vectors handle rx and tx interrupts.  Reuse the
14616                  * mailbox values for the next iteration.  The values we setup
14617                  * above are still useful for the single vectored mode.
14618                  */
14619                 if (!i)
14620                         continue;
14621
14622                 rcvmbx += 0x8;
14623
14624                 if (sndmbx & 0x4)
14625                         sndmbx -= 0x4;
14626                 else
14627                         sndmbx += 0xc;
14628         }
14629
14630         tg3_init_coal(tp);
14631
14632         pci_set_drvdata(pdev, dev);
14633
14634         err = register_netdev(dev);
14635         if (err) {
14636                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14637                 goto err_out_apeunmap;
14638         }
14639
14640         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14641                     tp->board_part_number,
14642                     tp->pci_chip_rev_id,
14643                     tg3_bus_string(tp, str),
14644                     dev->dev_addr);
14645
14646         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14647                 struct phy_device *phydev;
14648                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14649                 netdev_info(dev,
14650                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14651                             phydev->drv->name, dev_name(&phydev->dev));
14652         } else {
14653                 char *ethtype;
14654
14655                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14656                         ethtype = "10/100Base-TX";
14657                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14658                         ethtype = "1000Base-SX";
14659                 else
14660                         ethtype = "10/100/1000Base-T";
14661
14662                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14663                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14664                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14665         }
14666
14667         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14668                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14669                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14670                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14671                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14672                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14673         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14674                     tp->dma_rwctrl,
14675                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14676                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14677
14678         return 0;
14679
14680 err_out_apeunmap:
14681         if (tp->aperegs) {
14682                 iounmap(tp->aperegs);
14683                 tp->aperegs = NULL;
14684         }
14685
14686 err_out_iounmap:
14687         if (tp->regs) {
14688                 iounmap(tp->regs);
14689                 tp->regs = NULL;
14690         }
14691
14692 err_out_free_dev:
14693         free_netdev(dev);
14694
14695 err_out_free_res:
14696         pci_release_regions(pdev);
14697
14698 err_out_disable_pdev:
14699         pci_disable_device(pdev);
14700         pci_set_drvdata(pdev, NULL);
14701         return err;
14702 }
14703
14704 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14705 {
14706         struct net_device *dev = pci_get_drvdata(pdev);
14707
14708         if (dev) {
14709                 struct tg3 *tp = netdev_priv(dev);
14710
14711                 if (tp->fw)
14712                         release_firmware(tp->fw);
14713
14714                 flush_scheduled_work();
14715
14716                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14717                         tg3_phy_fini(tp);
14718                         tg3_mdio_fini(tp);
14719                 }
14720
14721                 unregister_netdev(dev);
14722                 if (tp->aperegs) {
14723                         iounmap(tp->aperegs);
14724                         tp->aperegs = NULL;
14725                 }
14726                 if (tp->regs) {
14727                         iounmap(tp->regs);
14728                         tp->regs = NULL;
14729                 }
14730                 free_netdev(dev);
14731                 pci_release_regions(pdev);
14732                 pci_disable_device(pdev);
14733                 pci_set_drvdata(pdev, NULL);
14734         }
14735 }
14736
14737 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14738 {
14739         struct net_device *dev = pci_get_drvdata(pdev);
14740         struct tg3 *tp = netdev_priv(dev);
14741         pci_power_t target_state;
14742         int err;
14743
14744         /* PCI register 4 needs to be saved whether netif_running() or not.
14745          * MSI address and data need to be saved if using MSI and
14746          * netif_running().
14747          */
14748         pci_save_state(pdev);
14749
14750         if (!netif_running(dev))
14751                 return 0;
14752
14753         flush_scheduled_work();
14754         tg3_phy_stop(tp);
14755         tg3_netif_stop(tp);
14756
14757         del_timer_sync(&tp->timer);
14758
14759         tg3_full_lock(tp, 1);
14760         tg3_disable_ints(tp);
14761         tg3_full_unlock(tp);
14762
14763         netif_device_detach(dev);
14764
14765         tg3_full_lock(tp, 0);
14766         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14767         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14768         tg3_full_unlock(tp);
14769
14770         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14771
14772         err = tg3_set_power_state(tp, target_state);
14773         if (err) {
14774                 int err2;
14775
14776                 tg3_full_lock(tp, 0);
14777
14778                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14779                 err2 = tg3_restart_hw(tp, 1);
14780                 if (err2)
14781                         goto out;
14782
14783                 tp->timer.expires = jiffies + tp->timer_offset;
14784                 add_timer(&tp->timer);
14785
14786                 netif_device_attach(dev);
14787                 tg3_netif_start(tp);
14788
14789 out:
14790                 tg3_full_unlock(tp);
14791
14792                 if (!err2)
14793                         tg3_phy_start(tp);
14794         }
14795
14796         return err;
14797 }
14798
14799 static int tg3_resume(struct pci_dev *pdev)
14800 {
14801         struct net_device *dev = pci_get_drvdata(pdev);
14802         struct tg3 *tp = netdev_priv(dev);
14803         int err;
14804
14805         pci_restore_state(tp->pdev);
14806
14807         if (!netif_running(dev))
14808                 return 0;
14809
14810         err = tg3_set_power_state(tp, PCI_D0);
14811         if (err)
14812                 return err;
14813
14814         netif_device_attach(dev);
14815
14816         tg3_full_lock(tp, 0);
14817
14818         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14819         err = tg3_restart_hw(tp, 1);
14820         if (err)
14821                 goto out;
14822
14823         tp->timer.expires = jiffies + tp->timer_offset;
14824         add_timer(&tp->timer);
14825
14826         tg3_netif_start(tp);
14827
14828 out:
14829         tg3_full_unlock(tp);
14830
14831         if (!err)
14832                 tg3_phy_start(tp);
14833
14834         return err;
14835 }
14836
14837 static struct pci_driver tg3_driver = {
14838         .name           = DRV_MODULE_NAME,
14839         .id_table       = tg3_pci_tbl,
14840         .probe          = tg3_init_one,
14841         .remove         = __devexit_p(tg3_remove_one),
14842         .suspend        = tg3_suspend,
14843         .resume         = tg3_resume
14844 };
14845
14846 static int __init tg3_init(void)
14847 {
14848         return pci_register_driver(&tg3_driver);
14849 }
14850
14851 static void __exit tg3_cleanup(void)
14852 {
14853         pci_unregister_driver(&tg3_driver);
14854 }
14855
14856 module_init(tg3_init);
14857 module_exit(tg3_cleanup);