drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43 #include <net/ip.h>
  44
  45 #include <asm/system.h>
  46 #include <asm/io.h>
  47 #include <asm/byteorder.h>
  48 #include <asm/uaccess.h>
  49
  50 #ifdef CONFIG_SPARC
  51 #include <asm/idprom.h>
  52 #include <asm/prom.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #define TG3_TSO_SUPPORT 1
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define PFX DRV_MODULE_NAME     ": "
  67 #define DRV_MODULE_VERSION      "3.81"
  68 #define DRV_MODULE_RELDATE      "September 5, 2007"
  69
  70 #define TG3_DEF_MAC_MODE        0
  71 #define TG3_DEF_RX_MODE         0
  72 #define TG3_DEF_TX_MODE         0
  73 #define TG3_DEF_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_IFDOWN       | \
  79          NETIF_MSG_IFUP         | \
  80          NETIF_MSG_RX_ERR       | \
  81          NETIF_MSG_TX_ERR)
  82
  83 /* length of time before we decide the hardware is borked,
  84  * and dev->tx_timeout() should be called to fix the problem
  85  */
  86 #define TG3_TX_TIMEOUT                  (5 * HZ)
  87
  88 /* hardware minimum and maximum for a single frame's data payload */
  89 #define TG3_MIN_MTU                     60
  90 #define TG3_MAX_MTU(tp) \
  91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  92
  93 /* These numbers seem to be hard coded in the NIC firmware somehow.
  94  * You can't change the ring sizes, but you can change where you place
  95  * them in the NIC onboard memory.
  96  */
  97 #define TG3_RX_RING_SIZE                512
  98 #define TG3_DEF_RX_RING_PENDING         200
  99 #define TG3_RX_JUMBO_RING_SIZE          256
 100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 101
 102 /* Do not place this n-ring entries value into the tp struct itself,
 103  * we really want to expose these constants to GCC so that modulo et
 104  * al.  operations are done with shifts and masks instead of with
 105  * hw multiply/modulo instructions.  Another solution would be to
 106  * replace things like '% foo' with '& (foo - 1)'.
 107  */
 108 #define TG3_RX_RCB_RING_SIZE(tp)        \
 109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 110
 111 #define TG3_TX_RING_SIZE                512
 112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 113
 114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 115                                  TG3_RX_RING_SIZE)
 116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_JUMBO_RING_SIZE)
 118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 119                                    TG3_RX_RCB_RING_SIZE(tp))
 120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 121                                  TG3_TX_RING_SIZE)
 122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 123
 124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 126
 127 /* minimum number of free TX descriptors required to wake up TX process */
 128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 129
 130 /* number of ETHTOOL_GSTATS u64's */
 131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 132
 133 #define TG3_NUM_TEST            6
 134
 135 static char version[] __devinitdata =
 136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 137
 138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142
 143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 144 module_param(tg3_debug, int, 0);
 145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 146
 147 static struct pci_device_id tg3_pci_tbl[] = {
 148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 208         {}
 209 };
 210
 211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 212
 213 static const struct {
 214         const char string[ETH_GSTRING_LEN];
 215 } ethtool_stats_keys[TG3_NUM_STATS] = {
 216         { "rx_octets" },
 217         { "rx_fragments" },
 218         { "rx_ucast_packets" },
 219         { "rx_mcast_packets" },
 220         { "rx_bcast_packets" },
 221         { "rx_fcs_errors" },
 222         { "rx_align_errors" },
 223         { "rx_xon_pause_rcvd" },
 224         { "rx_xoff_pause_rcvd" },
 225         { "rx_mac_ctrl_rcvd" },
 226         { "rx_xoff_entered" },
 227         { "rx_frame_too_long_errors" },
 228         { "rx_jabbers" },
 229         { "rx_undersize_packets" },
 230         { "rx_in_length_errors" },
 231         { "rx_out_length_errors" },
 232         { "rx_64_or_less_octet_packets" },
 233         { "rx_65_to_127_octet_packets" },
 234         { "rx_128_to_255_octet_packets" },
 235         { "rx_256_to_511_octet_packets" },
 236         { "rx_512_to_1023_octet_packets" },
 237         { "rx_1024_to_1522_octet_packets" },
 238         { "rx_1523_to_2047_octet_packets" },
 239         { "rx_2048_to_4095_octet_packets" },
 240         { "rx_4096_to_8191_octet_packets" },
 241         { "rx_8192_to_9022_octet_packets" },
 242
 243         { "tx_octets" },
 244         { "tx_collisions" },
 245
 246         { "tx_xon_sent" },
 247         { "tx_xoff_sent" },
 248         { "tx_flow_control" },
 249         { "tx_mac_errors" },
 250         { "tx_single_collisions" },
 251         { "tx_mult_collisions" },
 252         { "tx_deferred" },
 253         { "tx_excessive_collisions" },
 254         { "tx_late_collisions" },
 255         { "tx_collide_2times" },
 256         { "tx_collide_3times" },
 257         { "tx_collide_4times" },
 258         { "tx_collide_5times" },
 259         { "tx_collide_6times" },
 260         { "tx_collide_7times" },
 261         { "tx_collide_8times" },
 262         { "tx_collide_9times" },
 263         { "tx_collide_10times" },
 264         { "tx_collide_11times" },
 265         { "tx_collide_12times" },
 266         { "tx_collide_13times" },
 267         { "tx_collide_14times" },
 268         { "tx_collide_15times" },
 269         { "tx_ucast_packets" },
 270         { "tx_mcast_packets" },
 271         { "tx_bcast_packets" },
 272         { "tx_carrier_sense_errors" },
 273         { "tx_discards" },
 274         { "tx_errors" },
 275
 276         { "dma_writeq_full" },
 277         { "dma_write_prioq_full" },
 278         { "rxbds_empty" },
 279         { "rx_discards" },
 280         { "rx_errors" },
 281         { "rx_threshold_hit" },
 282
 283         { "dma_readq_full" },
 284         { "dma_read_prioq_full" },
 285         { "tx_comp_queue_full" },
 286
 287         { "ring_set_send_prod_index" },
 288         { "ring_status_update" },
 289         { "nic_irqs" },
 290         { "nic_avoided_irqs" },
 291         { "nic_tx_threshold_hit" }
 292 };
 293
 294 static const struct {
 295         const char string[ETH_GSTRING_LEN];
 296 } ethtool_test_keys[TG3_NUM_TEST] = {
 297         { "nvram test     (online) " },
 298         { "link test      (online) " },
 299         { "register test  (offline)" },
 300         { "memory test    (offline)" },
 301         { "loopback test  (offline)" },
 302         { "interrupt test (offline)" },
 303 };
 304
 305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 306 {
 307         writel(val, tp->regs + off);
 308 }
 309
 310 static u32 tg3_read32(struct tg3 *tp, u32 off)
 311 {
 312         return (readl(tp->regs + off));
 313 }
 314
 315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 316 {
 317         unsigned long flags;
 318
 319         spin_lock_irqsave(&tp->indirect_lock, flags);
 320         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 321         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 322         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 323 }
 324
 325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 326 {
 327         writel(val, tp->regs + off);
 328         readl(tp->regs + off);
 329 }
 330
 331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 332 {
 333         unsigned long flags;
 334         u32 val;
 335
 336         spin_lock_irqsave(&tp->indirect_lock, flags);
 337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 338         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 340         return val;
 341 }
 342
 343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         unsigned long flags;
 346
 347         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 348                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 349                                        TG3_64BIT_REG_LOW, val);
 350                 return;
 351         }
 352         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 353                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 354                                        TG3_64BIT_REG_LOW, val);
 355                 return;
 356         }
 357
 358         spin_lock_irqsave(&tp->indirect_lock, flags);
 359         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 360         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 361         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 362
 363         /* In indirect mode when disabling interrupts, we also need
 364          * to clear the interrupt bit in the GRC local ctrl register.
 365          */
 366         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 367             (val == 0x1)) {
 368                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 369                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 370         }
 371 }
 372
 373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 374 {
 375         unsigned long flags;
 376         u32 val;
 377
 378         spin_lock_irqsave(&tp->indirect_lock, flags);
 379         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 380         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 381         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 382         return val;
 383 }
 384
 385 /* usec_wait specifies the wait time in usec when writing to certain registers
 386  * where it is unsafe to read back the register without some delay.
 387  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 388  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 389  */
 390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 391 {
 392         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 393             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 394                 /* Non-posted methods */
 395                 tp->write32(tp, off, val);
 396         else {
 397                 /* Posted method */
 398                 tg3_write32(tp, off, val);
 399                 if (usec_wait)
 400                         udelay(usec_wait);
 401                 tp->read32(tp, off);
 402         }
 403         /* Wait again after the read for the posted method to guarantee that
 404          * the wait time is met.
 405          */
 406         if (usec_wait)
 407                 udelay(usec_wait);
 408 }
 409
 410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 411 {
 412         tp->write32_mbox(tp, off, val);
 413         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 415                 tp->read32_mbox(tp, off);
 416 }
 417
 418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 419 {
 420         void __iomem *mbox = tp->regs + off;
 421         writel(val, mbox);
 422         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 423                 writel(val, mbox);
 424         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 425                 readl(mbox);
 426 }
 427
 428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 429 {
 430         return (readl(tp->regs + off + GRCMBOX_BASE));
 431 }
 432
 433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 434 {
 435         writel(val, tp->regs + off + GRCMBOX_BASE);
 436 }
 437
 438 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 439 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 440 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 441 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 442 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 443
 444 #define tw32(reg,val)           tp->write32(tp, reg, val)
 445 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 447 #define tr32(reg)               tp->read32(tp, reg)
 448
 449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 450 {
 451         unsigned long flags;
 452
 453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 454             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 455                 return;
 456
 457         spin_lock_irqsave(&tp->indirect_lock, flags);
 458         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 461
 462                 /* Always leave this as zero. */
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 464         } else {
 465                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 466                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 467
 468                 /* Always leave this as zero. */
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 470         }
 471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 472 }
 473
 474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 475 {
 476         unsigned long flags;
 477
 478         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 479             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 480                 *val = 0;
 481                 return;
 482         }
 483
 484         spin_lock_irqsave(&tp->indirect_lock, flags);
 485         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 486                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 487                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 488
 489                 /* Always leave this as zero. */
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 491         } else {
 492                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 493                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 494
 495                 /* Always leave this as zero. */
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 497         }
 498         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 499 }
 500
 501 static void tg3_disable_ints(struct tg3 *tp)
 502 {
 503         tw32(TG3PCI_MISC_HOST_CTRL,
 504              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 505         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 506 }
 507
 508 static inline void tg3_cond_int(struct tg3 *tp)
 509 {
 510         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 511             (tp->hw_status->status & SD_STATUS_UPDATED))
 512                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 513         else
 514                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 515                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 516 }
 517
 518 static void tg3_enable_ints(struct tg3 *tp)
 519 {
 520         tp->irq_sync = 0;
 521         wmb();
 522
 523         tw32(TG3PCI_MISC_HOST_CTRL,
 524              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 525         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 526                        (tp->last_tag << 24));
 527         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 528                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 529                                (tp->last_tag << 24));
 530         tg3_cond_int(tp);
 531 }
 532
 533 static inline unsigned int tg3_has_work(struct tg3 *tp)
 534 {
 535         struct tg3_hw_status *sblk = tp->hw_status;
 536         unsigned int work_exists = 0;
 537
 538         /* check for phy events */
 539         if (!(tp->tg3_flags &
 540               (TG3_FLAG_USE_LINKCHG_REG |
 541                TG3_FLAG_POLL_SERDES))) {
 542                 if (sblk->status & SD_STATUS_LINK_CHG)
 543                         work_exists = 1;
 544         }
 545         /* check for RX/TX work to do */
 546         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 547             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 548                 work_exists = 1;
 549
 550         return work_exists;
 551 }
 552
 553 /* tg3_restart_ints
 554  *  similar to tg3_enable_ints, but it accurately determines whether there
 555  *  is new work pending and can return without flushing the PIO write
 556  *  which reenables interrupts
 557  */
 558 static void tg3_restart_ints(struct tg3 *tp)
 559 {
 560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 561                      tp->last_tag << 24);
 562         mmiowb();
 563
 564         /* When doing tagged status, this work check is unnecessary.
 565          * The last_tag we write above tells the chip which piece of
 566          * work we've completed.
 567          */
 568         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 569             tg3_has_work(tp))
 570                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 571                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 572 }
 573
 574 static inline void tg3_netif_stop(struct tg3 *tp)
 575 {
 576         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 577         netif_poll_disable(tp->dev);
 578         netif_tx_disable(tp->dev);
 579 }
 580
 581 static inline void tg3_netif_start(struct tg3 *tp)
 582 {
 583         netif_wake_queue(tp->dev);
 584         /* NOTE: unconditional netif_wake_queue is only appropriate
 585          * so long as all callers are assured to have free tx slots
 586          * (such as after tg3_init_hw)
 587          */
 588         netif_poll_enable(tp->dev);
 589         tp->hw_status->status |= SD_STATUS_UPDATED;
 590         tg3_enable_ints(tp);
 591 }
 592
 593 static void tg3_switch_clocks(struct tg3 *tp)
 594 {
 595         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 596         u32 orig_clock_ctrl;
 597
 598         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 599                 return;
 600
 601         orig_clock_ctrl = clock_ctrl;
 602         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 603                        CLOCK_CTRL_CLKRUN_OENABLE |
 604                        0x1f);
 605         tp->pci_clock_ctrl = clock_ctrl;
 606
 607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 608                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 609                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 610                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 611                 }
 612         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 613                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                             clock_ctrl |
 615                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 616                             40);
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 619                             40);
 620         }
 621         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 622 }
 623
 624 #define PHY_BUSY_LOOPS  5000
 625
 626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 627 {
 628         u32 frame_val;
 629         unsigned int loops;
 630         int ret;
 631
 632         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 633                 tw32_f(MAC_MI_MODE,
 634                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 635                 udelay(80);
 636         }
 637
 638         *val = 0x0;
 639
 640         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 641                       MI_COM_PHY_ADDR_MASK);
 642         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 643                       MI_COM_REG_ADDR_MASK);
 644         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 645
 646         tw32_f(MAC_MI_COM, frame_val);
 647
 648         loops = PHY_BUSY_LOOPS;
 649         while (loops != 0) {
 650                 udelay(10);
 651                 frame_val = tr32(MAC_MI_COM);
 652
 653                 if ((frame_val & MI_COM_BUSY) == 0) {
 654                         udelay(5);
 655                         frame_val = tr32(MAC_MI_COM);
 656                         break;
 657                 }
 658                 loops -= 1;
 659         }
 660
 661         ret = -EBUSY;
 662         if (loops != 0) {
 663                 *val = frame_val & MI_COM_DATA_MASK;
 664                 ret = 0;
 665         }
 666
 667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 668                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 669                 udelay(80);
 670         }
 671
 672         return ret;
 673 }
 674
 675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 676 {
 677         u32 frame_val;
 678         unsigned int loops;
 679         int ret;
 680
 681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 682             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 683                 return 0;
 684
 685         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 686                 tw32_f(MAC_MI_MODE,
 687                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 688                 udelay(80);
 689         }
 690
 691         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 692                       MI_COM_PHY_ADDR_MASK);
 693         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 694                       MI_COM_REG_ADDR_MASK);
 695         frame_val |= (val & MI_COM_DATA_MASK);
 696         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 697
 698         tw32_f(MAC_MI_COM, frame_val);
 699
 700         loops = PHY_BUSY_LOOPS;
 701         while (loops != 0) {
 702                 udelay(10);
 703                 frame_val = tr32(MAC_MI_COM);
 704                 if ((frame_val & MI_COM_BUSY) == 0) {
 705                         udelay(5);
 706                         frame_val = tr32(MAC_MI_COM);
 707                         break;
 708                 }
 709                 loops -= 1;
 710         }
 711
 712         ret = -EBUSY;
 713         if (loops != 0)
 714                 ret = 0;
 715
 716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 717                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 718                 udelay(80);
 719         }
 720
 721         return ret;
 722 }
 723
 724 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
 725 {
 726         u32 phy;
 727
 728         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
 729             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
 730                 return;
 731
 732         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 733                 u32 ephy;
 734
 735                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
 736                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
 737                                      ephy | MII_TG3_EPHY_SHADOW_EN);
 738                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
 739                                 if (enable)
 740                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
 741                                 else
 742                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
 743                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
 744                         }
 745                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
 746                 }
 747         } else {
 748                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
 749                       MII_TG3_AUXCTL_SHDWSEL_MISC;
 750                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
 751                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
 752                         if (enable)
 753                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
 754                         else
 755                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
 756                         phy |= MII_TG3_AUXCTL_MISC_WREN;
 757                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
 758                 }
 759         }
 760 }
 761
 762 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 763 {
 764         u32 val;
 765
 766         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 767                 return;
 768
 769         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 770             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 771                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 772                              (val | (1 << 15) | (1 << 4)));
 773 }
 774
 775 static int tg3_bmcr_reset(struct tg3 *tp)
 776 {
 777         u32 phy_control;
 778         int limit, err;
 779
 780         /* OK, reset it, and poll the BMCR_RESET bit until it
 781          * clears or we time out.
 782          */
 783         phy_control = BMCR_RESET;
 784         err = tg3_writephy(tp, MII_BMCR, phy_control);
 785         if (err != 0)
 786                 return -EBUSY;
 787
 788         limit = 5000;
 789         while (limit--) {
 790                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 791                 if (err != 0)
 792                         return -EBUSY;
 793
 794                 if ((phy_control & BMCR_RESET) == 0) {
 795                         udelay(40);
 796                         break;
 797                 }
 798                 udelay(10);
 799         }
 800         if (limit <= 0)
 801                 return -EBUSY;
 802
 803         return 0;
 804 }
 805
 806 static int tg3_wait_macro_done(struct tg3 *tp)
 807 {
 808         int limit = 100;
 809
 810         while (limit--) {
 811                 u32 tmp32;
 812
 813                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 814                         if ((tmp32 & 0x1000) == 0)
 815                                 break;
 816                 }
 817         }
 818         if (limit <= 0)
 819                 return -EBUSY;
 820
 821         return 0;
 822 }
 823
 824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 825 {
 826         static const u32 test_pat[4][6] = {
 827         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 828         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 829         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 830         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 831         };
 832         int chan;
 833
 834         for (chan = 0; chan < 4; chan++) {
 835                 int i;
 836
 837                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 838                              (chan * 0x2000) | 0x0200);
 839                 tg3_writephy(tp, 0x16, 0x0002);
 840
 841                 for (i = 0; i < 6; i++)
 842                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 843                                      test_pat[chan][i]);
 844
 845                 tg3_writephy(tp, 0x16, 0x0202);
 846                 if (tg3_wait_macro_done(tp)) {
 847                         *resetp = 1;
 848                         return -EBUSY;
 849                 }
 850
 851                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 852                              (chan * 0x2000) | 0x0200);
 853                 tg3_writephy(tp, 0x16, 0x0082);
 854                 if (tg3_wait_macro_done(tp)) {
 855                         *resetp = 1;
 856                         return -EBUSY;
 857                 }
 858
 859                 tg3_writephy(tp, 0x16, 0x0802);
 860                 if (tg3_wait_macro_done(tp)) {
 861                         *resetp = 1;
 862                         return -EBUSY;
 863                 }
 864
 865                 for (i = 0; i < 6; i += 2) {
 866                         u32 low, high;
 867
 868                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 869                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 870                             tg3_wait_macro_done(tp)) {
 871                                 *resetp = 1;
 872                                 return -EBUSY;
 873                         }
 874                         low &= 0x7fff;
 875                         high &= 0x000f;
 876                         if (low != test_pat[chan][i] ||
 877                             high != test_pat[chan][i+1]) {
 878                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 879                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 880                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 881
 882                                 return -EBUSY;
 883                         }
 884                 }
 885         }
 886
 887         return 0;
 888 }
 889
 890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 891 {
 892         int chan;
 893
 894         for (chan = 0; chan < 4; chan++) {
 895                 int i;
 896
 897                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 898                              (chan * 0x2000) | 0x0200);
 899                 tg3_writephy(tp, 0x16, 0x0002);
 900                 for (i = 0; i < 6; i++)
 901                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 902                 tg3_writephy(tp, 0x16, 0x0202);
 903                 if (tg3_wait_macro_done(tp))
 904                         return -EBUSY;
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 911 {
 912         u32 reg32, phy9_orig;
 913         int retries, do_phy_reset, err;
 914
 915         retries = 10;
 916         do_phy_reset = 1;
 917         do {
 918                 if (do_phy_reset) {
 919                         err = tg3_bmcr_reset(tp);
 920                         if (err)
 921                                 return err;
 922                         do_phy_reset = 0;
 923                 }
 924
 925                 /* Disable transmitter and interrupt.  */
 926                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 927                         continue;
 928
 929                 reg32 |= 0x3000;
 930                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 931
 932                 /* Set full-duplex, 1000 mbps.  */
 933                 tg3_writephy(tp, MII_BMCR,
 934                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 935
 936                 /* Set to master mode.  */
 937                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 938                         continue;
 939
 940                 tg3_writephy(tp, MII_TG3_CTRL,
 941                              (MII_TG3_CTRL_AS_MASTER |
 942                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 943
 944                 /* Enable SM_DSP_CLOCK and 6dB.  */
 945                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 946
 947                 /* Block the PHY control access.  */
 948                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 949                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 950
 951                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 952                 if (!err)
 953                         break;
 954         } while (--retries);
 955
 956         err = tg3_phy_reset_chanpat(tp);
 957         if (err)
 958                 return err;
 959
 960         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 961         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 962
 963         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 964         tg3_writephy(tp, 0x16, 0x0000);
 965
 966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 968                 /* Set Extended packet length bit for jumbo frames */
 969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 970         }
 971         else {
 972                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 973         }
 974
 975         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 976
 977         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 978                 reg32 &= ~0x3000;
 979                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 980         } else if (!err)
 981                 err = -EBUSY;
 982
 983         return err;
 984 }
 985
 986 static void tg3_link_report(struct tg3 *);
 987
 988 /* This will reset the tigon3 PHY if there is no valid
 989  * link unless the FORCE argument is non-zero.
 990  */
 991 static int tg3_phy_reset(struct tg3 *tp)
 992 {
 993         u32 phy_status;
 994         int err;
 995
 996         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 997                 u32 val;
 998
 999                 val = tr32(GRC_MISC_CFG);
1000                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1001                 udelay(40);
1002         }
1003         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1004         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1005         if (err != 0)
1006                 return -EBUSY;
1007
1008         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1009                 netif_carrier_off(tp->dev);
1010                 tg3_link_report(tp);
1011         }
1012
1013         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1014             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1015             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1016                 err = tg3_phy_reset_5703_4_5(tp);
1017                 if (err)
1018                         return err;
1019                 goto out;
1020         }
1021
1022         err = tg3_bmcr_reset(tp);
1023         if (err)
1024                 return err;
1025
1026 out:
1027         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1028                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1030                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1031                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1032                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1033                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1034         }
1035         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1036                 tg3_writephy(tp, 0x1c, 0x8d68);
1037                 tg3_writephy(tp, 0x1c, 0x8d68);
1038         }
1039         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1040                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1041                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1042                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1043                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1044                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1045                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1046                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1047                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1048         }
1049         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1050                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1051                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1052                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1053                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1054                         tg3_writephy(tp, MII_TG3_TEST1,
1055                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1056                 } else
1057                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1058                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1059         }
1060         /* Set Extended packet length bit (bit 14) on all chips that */
1061         /* support jumbo frames */
1062         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1063                 /* Cannot do read-modify-write on 5401 */
1064                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1065         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1066                 u32 phy_reg;
1067
1068                 /* Set bit 14 with read-modify-write to preserve other bits */
1069                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1070                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1071                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1072         }
1073
1074         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1075          * jumbo frames transmission.
1076          */
1077         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1078                 u32 phy_reg;
1079
1080                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1081                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1082                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1083         }
1084
1085         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1086                 /* adjust output voltage */
1087                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1088         }
1089
1090         tg3_phy_toggle_automdix(tp, 1);
1091         tg3_phy_set_wirespeed(tp);
1092         return 0;
1093 }
1094
1095 static void tg3_frob_aux_power(struct tg3 *tp)
1096 {
1097         struct tg3 *tp_peer = tp;
1098
1099         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1100                 return;
1101
1102         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1103             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1104                 struct net_device *dev_peer;
1105
1106                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1107                 /* remove_one() may have been run on the peer. */
1108                 if (!dev_peer)
1109                         tp_peer = tp;
1110                 else
1111                         tp_peer = netdev_priv(dev_peer);
1112         }
1113
1114         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1115             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1116             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1117             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1118                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1119                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1120                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1121                                     (GRC_LCLCTRL_GPIO_OE0 |
1122                                      GRC_LCLCTRL_GPIO_OE1 |
1123                                      GRC_LCLCTRL_GPIO_OE2 |
1124                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1125                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1126                                     100);
1127                 } else {
1128                         u32 no_gpio2;
1129                         u32 grc_local_ctrl = 0;
1130
1131                         if (tp_peer != tp &&
1132                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1133                                 return;
1134
1135                         /* Workaround to prevent overdrawing Amps. */
1136                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1137                             ASIC_REV_5714) {
1138                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1139                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140                                             grc_local_ctrl, 100);
1141                         }
1142
1143                         /* On 5753 and variants, GPIO2 cannot be used. */
1144                         no_gpio2 = tp->nic_sram_data_cfg &
1145                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1146
1147                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1148                                          GRC_LCLCTRL_GPIO_OE1 |
1149                                          GRC_LCLCTRL_GPIO_OE2 |
1150                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1151                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1152                         if (no_gpio2) {
1153                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1154                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1155                         }
1156                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157                                                     grc_local_ctrl, 100);
1158
1159                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1160
1161                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1162                                                     grc_local_ctrl, 100);
1163
1164                         if (!no_gpio2) {
1165                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1166                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1167                                             grc_local_ctrl, 100);
1168                         }
1169                 }
1170         } else {
1171                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1172                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1173                         if (tp_peer != tp &&
1174                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1175                                 return;
1176
1177                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1178                                     (GRC_LCLCTRL_GPIO_OE1 |
1179                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1180
1181                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1182                                     GRC_LCLCTRL_GPIO_OE1, 100);
1183
1184                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1185                                     (GRC_LCLCTRL_GPIO_OE1 |
1186                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1187                 }
1188         }
1189 }
1190
1191 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1192 {
1193         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1194                 return 1;
1195         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1196                 if (speed != SPEED_10)
1197                         return 1;
1198         } else if (speed == SPEED_10)
1199                 return 1;
1200
1201         return 0;
1202 }
1203
1204 static int tg3_setup_phy(struct tg3 *, int);
1205
1206 #define RESET_KIND_SHUTDOWN     0
1207 #define RESET_KIND_INIT         1
1208 #define RESET_KIND_SUSPEND      2
1209
1210 static void tg3_write_sig_post_reset(struct tg3 *, int);
1211 static int tg3_halt_cpu(struct tg3 *, u32);
1212 static int tg3_nvram_lock(struct tg3 *);
1213 static void tg3_nvram_unlock(struct tg3 *);
1214
1215 static void tg3_power_down_phy(struct tg3 *tp)
1216 {
1217         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1218                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1219                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1220                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1221
1222                         sg_dig_ctrl |=
1223                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1224                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1225                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1226                 }
1227                 return;
1228         }
1229
1230         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1231                 u32 val;
1232
1233                 tg3_bmcr_reset(tp);
1234                 val = tr32(GRC_MISC_CFG);
1235                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1236                 udelay(40);
1237                 return;
1238         } else {
1239                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1240                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1241                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1242         }
1243
1244         /* The PHY should not be powered down on some chips because
1245          * of bugs.
1246          */
1247         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1248             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1249             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1250              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1251                 return;
1252         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1253 }
1254
1255 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1256 {
1257         u32 misc_host_ctrl;
1258         u16 power_control, power_caps;
1259         int pm = tp->pm_cap;
1260
1261         /* Make sure register accesses (indirect or otherwise)
1262          * will function correctly.
1263          */
1264         pci_write_config_dword(tp->pdev,
1265                                TG3PCI_MISC_HOST_CTRL,
1266                                tp->misc_host_ctrl);
1267
1268         pci_read_config_word(tp->pdev,
1269                              pm + PCI_PM_CTRL,
1270                              &power_control);
1271         power_control |= PCI_PM_CTRL_PME_STATUS;
1272         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1273         switch (state) {
1274         case PCI_D0:
1275                 power_control |= 0;
1276                 pci_write_config_word(tp->pdev,
1277                                       pm + PCI_PM_CTRL,
1278                                       power_control);
1279                 udelay(100);    /* Delay after power state change */
1280
1281                 /* Switch out of Vaux if it is a NIC */
1282                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1283                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1284
1285                 return 0;
1286
1287         case PCI_D1:
1288                 power_control |= 1;
1289                 break;
1290
1291         case PCI_D2:
1292                 power_control |= 2;
1293                 break;
1294
1295         case PCI_D3hot:
1296                 power_control |= 3;
1297                 break;
1298
1299         default:
1300                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1301                        "requested.\n",
1302                        tp->dev->name, state);
1303                 return -EINVAL;
1304         };
1305
1306         power_control |= PCI_PM_CTRL_PME_ENABLE;
1307
1308         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1309         tw32(TG3PCI_MISC_HOST_CTRL,
1310              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1311
1312         if (tp->link_config.phy_is_low_power == 0) {
1313                 tp->link_config.phy_is_low_power = 1;
1314                 tp->link_config.orig_speed = tp->link_config.speed;
1315                 tp->link_config.orig_duplex = tp->link_config.duplex;
1316                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1317         }
1318
1319         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1320                 tp->link_config.speed = SPEED_10;
1321                 tp->link_config.duplex = DUPLEX_HALF;
1322                 tp->link_config.autoneg = AUTONEG_ENABLE;
1323                 tg3_setup_phy(tp, 0);
1324         }
1325
1326         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1327                 u32 val;
1328
1329                 val = tr32(GRC_VCPU_EXT_CTRL);
1330                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1331         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1332                 int i;
1333                 u32 val;
1334
1335                 for (i = 0; i < 200; i++) {
1336                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1337                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1338                                 break;
1339                         msleep(1);
1340                 }
1341         }
1342         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1343                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1344                                                      WOL_DRV_STATE_SHUTDOWN |
1345                                                      WOL_DRV_WOL |
1346                                                      WOL_SET_MAGIC_PKT);
1347
1348         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1349
1350         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1351                 u32 mac_mode;
1352
1353                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1354                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1355                         udelay(40);
1356
1357                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1358                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1359                         else
1360                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1361
1362                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1363                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1364                             ASIC_REV_5700) {
1365                                 u32 speed = (tp->tg3_flags &
1366                                              TG3_FLAG_WOL_SPEED_100MB) ?
1367                                              SPEED_100 : SPEED_10;
1368                                 if (tg3_5700_link_polarity(tp, speed))
1369                                         mac_mode |= MAC_MODE_LINK_POLARITY;
1370                                 else
1371                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
1372                         }
1373                 } else {
1374                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1375                 }
1376
1377                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1378                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1379
1380                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1381                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1382                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1383
1384                 tw32_f(MAC_MODE, mac_mode);
1385                 udelay(100);
1386
1387                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1388                 udelay(10);
1389         }
1390
1391         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1392             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1393              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1394                 u32 base_val;
1395
1396                 base_val = tp->pci_clock_ctrl;
1397                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1398                              CLOCK_CTRL_TXCLK_DISABLE);
1399
1400                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1401                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1402         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1403                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1404                 /* do nothing */
1405         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1406                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1407                 u32 newbits1, newbits2;
1408
1409                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1410                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1411                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1412                                     CLOCK_CTRL_TXCLK_DISABLE |
1413                                     CLOCK_CTRL_ALTCLK);
1414                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1415                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1416                         newbits1 = CLOCK_CTRL_625_CORE;
1417                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1418                 } else {
1419                         newbits1 = CLOCK_CTRL_ALTCLK;
1420                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1421                 }
1422
1423                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1424                             40);
1425
1426                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1427                             40);
1428
1429                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1430                         u32 newbits3;
1431
1432                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1433                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1434                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1435                                             CLOCK_CTRL_TXCLK_DISABLE |
1436                                             CLOCK_CTRL_44MHZ_CORE);
1437                         } else {
1438                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1439                         }
1440
1441                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1442                                     tp->pci_clock_ctrl | newbits3, 40);
1443                 }
1444         }
1445
1446         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1447             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1448                 tg3_power_down_phy(tp);
1449
1450         tg3_frob_aux_power(tp);
1451
1452         /* Workaround for unstable PLL clock */
1453         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1454             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1455                 u32 val = tr32(0x7d00);
1456
1457                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1458                 tw32(0x7d00, val);
1459                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1460                         int err;
1461
1462                         err = tg3_nvram_lock(tp);
1463                         tg3_halt_cpu(tp, RX_CPU_BASE);
1464                         if (!err)
1465                                 tg3_nvram_unlock(tp);
1466                 }
1467         }
1468
1469         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1470
1471         /* Finally, set the new power state. */
1472         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1473         udelay(100);    /* Delay after power state change */
1474
1475         return 0;
1476 }
1477
1478 static void tg3_link_report(struct tg3 *tp)
1479 {
1480         if (!netif_carrier_ok(tp->dev)) {
1481                 if (netif_msg_link(tp))
1482                         printk(KERN_INFO PFX "%s: Link is down.\n",
1483                                tp->dev->name);
1484         } else if (netif_msg_link(tp)) {
1485                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1486                        tp->dev->name,
1487                        (tp->link_config.active_speed == SPEED_1000 ?
1488                         1000 :
1489                         (tp->link_config.active_speed == SPEED_100 ?
1490                          100 : 10)),
1491                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1492                         "full" : "half"));
1493
1494                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1495                        "%s for RX.\n",
1496                        tp->dev->name,
1497                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1498                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1499         }
1500 }
1501
1502 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1503 {
1504         u32 new_tg3_flags = 0;
1505         u32 old_rx_mode = tp->rx_mode;
1506         u32 old_tx_mode = tp->tx_mode;
1507
1508         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1509
1510                 /* Convert 1000BaseX flow control bits to 1000BaseT
1511                  * bits before resolving flow control.
1512                  */
1513                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1514                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1515                                        ADVERTISE_PAUSE_ASYM);
1516                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1517
1518                         if (local_adv & ADVERTISE_1000XPAUSE)
1519                                 local_adv |= ADVERTISE_PAUSE_CAP;
1520                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1521                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1522                         if (remote_adv & LPA_1000XPAUSE)
1523                                 remote_adv |= LPA_PAUSE_CAP;
1524                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1525                                 remote_adv |= LPA_PAUSE_ASYM;
1526                 }
1527
1528                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1529                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1530                                 if (remote_adv & LPA_PAUSE_CAP)
1531                                         new_tg3_flags |=
1532                                                 (TG3_FLAG_RX_PAUSE |
1533                                                 TG3_FLAG_TX_PAUSE);
1534                                 else if (remote_adv & LPA_PAUSE_ASYM)
1535                                         new_tg3_flags |=
1536                                                 (TG3_FLAG_RX_PAUSE);
1537                         } else {
1538                                 if (remote_adv & LPA_PAUSE_CAP)
1539                                         new_tg3_flags |=
1540                                                 (TG3_FLAG_RX_PAUSE |
1541                                                 TG3_FLAG_TX_PAUSE);
1542                         }
1543                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1544                         if ((remote_adv & LPA_PAUSE_CAP) &&
1545                         (remote_adv & LPA_PAUSE_ASYM))
1546                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1547                 }
1548
1549                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1550                 tp->tg3_flags |= new_tg3_flags;
1551         } else {
1552                 new_tg3_flags = tp->tg3_flags;
1553         }
1554
1555         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1556                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1557         else
1558                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1559
1560         if (old_rx_mode != tp->rx_mode) {
1561                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1562         }
1563
1564         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1565                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1566         else
1567                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1568
1569         if (old_tx_mode != tp->tx_mode) {
1570                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1571         }
1572 }
1573
1574 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1575 {
1576         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1577         case MII_TG3_AUX_STAT_10HALF:
1578                 *speed = SPEED_10;
1579                 *duplex = DUPLEX_HALF;
1580                 break;
1581
1582         case MII_TG3_AUX_STAT_10FULL:
1583                 *speed = SPEED_10;
1584                 *duplex = DUPLEX_FULL;
1585                 break;
1586
1587         case MII_TG3_AUX_STAT_100HALF:
1588                 *speed = SPEED_100;
1589                 *duplex = DUPLEX_HALF;
1590                 break;
1591
1592         case MII_TG3_AUX_STAT_100FULL:
1593                 *speed = SPEED_100;
1594                 *duplex = DUPLEX_FULL;
1595                 break;
1596
1597         case MII_TG3_AUX_STAT_1000HALF:
1598                 *speed = SPEED_1000;
1599                 *duplex = DUPLEX_HALF;
1600                 break;
1601
1602         case MII_TG3_AUX_STAT_1000FULL:
1603                 *speed = SPEED_1000;
1604                 *duplex = DUPLEX_FULL;
1605                 break;
1606
1607         default:
1608                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1609                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1610                                  SPEED_10;
1611                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1612                                   DUPLEX_HALF;
1613                         break;
1614                 }
1615                 *speed = SPEED_INVALID;
1616                 *duplex = DUPLEX_INVALID;
1617                 break;
1618         };
1619 }
1620
1621 static void tg3_phy_copper_begin(struct tg3 *tp)
1622 {
1623         u32 new_adv;
1624         int i;
1625
1626         if (tp->link_config.phy_is_low_power) {
1627                 /* Entering low power mode.  Disable gigabit and
1628                  * 100baseT advertisements.
1629                  */
1630                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1631
1632                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1633                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1634                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1635                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1636
1637                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1638         } else if (tp->link_config.speed == SPEED_INVALID) {
1639                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1640                         tp->link_config.advertising &=
1641                                 ~(ADVERTISED_1000baseT_Half |
1642                                   ADVERTISED_1000baseT_Full);
1643
1644                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1645                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1646                         new_adv |= ADVERTISE_10HALF;
1647                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1648                         new_adv |= ADVERTISE_10FULL;
1649                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1650                         new_adv |= ADVERTISE_100HALF;
1651                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1652                         new_adv |= ADVERTISE_100FULL;
1653                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1654
1655                 if (tp->link_config.advertising &
1656                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1657                         new_adv = 0;
1658                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1659                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1660                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1661                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1662                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1663                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1664                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1665                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1666                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1667                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1668                 } else {
1669                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1670                 }
1671         } else {
1672                 /* Asking for a specific link mode. */
1673                 if (tp->link_config.speed == SPEED_1000) {
1674                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1675                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1676
1677                         if (tp->link_config.duplex == DUPLEX_FULL)
1678                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1679                         else
1680                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1681                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1682                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1683                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1684                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1685                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1686                 } else {
1687                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1688
1689                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1690                         if (tp->link_config.speed == SPEED_100) {
1691                                 if (tp->link_config.duplex == DUPLEX_FULL)
1692                                         new_adv |= ADVERTISE_100FULL;
1693                                 else
1694                                         new_adv |= ADVERTISE_100HALF;
1695                         } else {
1696                                 if (tp->link_config.duplex == DUPLEX_FULL)
1697                                         new_adv |= ADVERTISE_10FULL;
1698                                 else
1699                                         new_adv |= ADVERTISE_10HALF;
1700                         }
1701                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1702                 }
1703         }
1704
1705         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1706             tp->link_config.speed != SPEED_INVALID) {
1707                 u32 bmcr, orig_bmcr;
1708
1709                 tp->link_config.active_speed = tp->link_config.speed;
1710                 tp->link_config.active_duplex = tp->link_config.duplex;
1711
1712                 bmcr = 0;
1713                 switch (tp->link_config.speed) {
1714                 default:
1715                 case SPEED_10:
1716                         break;
1717
1718                 case SPEED_100:
1719                         bmcr |= BMCR_SPEED100;
1720                         break;
1721
1722                 case SPEED_1000:
1723                         bmcr |= TG3_BMCR_SPEED1000;
1724                         break;
1725                 };
1726
1727                 if (tp->link_config.duplex == DUPLEX_FULL)
1728                         bmcr |= BMCR_FULLDPLX;
1729
1730                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1731                     (bmcr != orig_bmcr)) {
1732                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1733                         for (i = 0; i < 1500; i++) {
1734                                 u32 tmp;
1735
1736                                 udelay(10);
1737                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1738                                     tg3_readphy(tp, MII_BMSR, &tmp))
1739                                         continue;
1740                                 if (!(tmp & BMSR_LSTATUS)) {
1741                                         udelay(40);
1742                                         break;
1743                                 }
1744                         }
1745                         tg3_writephy(tp, MII_BMCR, bmcr);
1746                         udelay(40);
1747                 }
1748         } else {
1749                 tg3_writephy(tp, MII_BMCR,
1750                              BMCR_ANENABLE | BMCR_ANRESTART);
1751         }
1752 }
1753
1754 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1755 {
1756         int err;
1757
1758         /* Turn off tap power management. */
1759         /* Set Extended packet length bit */
1760         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1761
1762         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1763         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1764
1765         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1766         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1767
1768         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1769         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1770
1771         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1772         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1773
1774         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1775         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1776
1777         udelay(40);
1778
1779         return err;
1780 }
1781
1782 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1783 {
1784         u32 adv_reg, all_mask = 0;
1785
1786         if (mask & ADVERTISED_10baseT_Half)
1787                 all_mask |= ADVERTISE_10HALF;
1788         if (mask & ADVERTISED_10baseT_Full)
1789                 all_mask |= ADVERTISE_10FULL;
1790         if (mask & ADVERTISED_100baseT_Half)
1791                 all_mask |= ADVERTISE_100HALF;
1792         if (mask & ADVERTISED_100baseT_Full)
1793                 all_mask |= ADVERTISE_100FULL;
1794
1795         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1796                 return 0;
1797
1798         if ((adv_reg & all_mask) != all_mask)
1799                 return 0;
1800         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1801                 u32 tg3_ctrl;
1802
1803                 all_mask = 0;
1804                 if (mask & ADVERTISED_1000baseT_Half)
1805                         all_mask |= ADVERTISE_1000HALF;
1806                 if (mask & ADVERTISED_1000baseT_Full)
1807                         all_mask |= ADVERTISE_1000FULL;
1808
1809                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1810                         return 0;
1811
1812                 if ((tg3_ctrl & all_mask) != all_mask)
1813                         return 0;
1814         }
1815         return 1;
1816 }
1817
1818 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1819 {
1820         int current_link_up;
1821         u32 bmsr, dummy;
1822         u16 current_speed;
1823         u8 current_duplex;
1824         int i, err;
1825
1826         tw32(MAC_EVENT, 0);
1827
1828         tw32_f(MAC_STATUS,
1829              (MAC_STATUS_SYNC_CHANGED |
1830               MAC_STATUS_CFG_CHANGED |
1831               MAC_STATUS_MI_COMPLETION |
1832               MAC_STATUS_LNKSTATE_CHANGED));
1833         udelay(40);
1834
1835         tp->mi_mode = MAC_MI_MODE_BASE;
1836         tw32_f(MAC_MI_MODE, tp->mi_mode);
1837         udelay(80);
1838
1839         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1840
1841         /* Some third-party PHYs need to be reset on link going
1842          * down.
1843          */
1844         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1847             netif_carrier_ok(tp->dev)) {
1848                 tg3_readphy(tp, MII_BMSR, &bmsr);
1849                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850                     !(bmsr & BMSR_LSTATUS))
1851                         force_reset = 1;
1852         }
1853         if (force_reset)
1854                 tg3_phy_reset(tp);
1855
1856         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1857                 tg3_readphy(tp, MII_BMSR, &bmsr);
1858                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1859                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1860                         bmsr = 0;
1861
1862                 if (!(bmsr & BMSR_LSTATUS)) {
1863                         err = tg3_init_5401phy_dsp(tp);
1864                         if (err)
1865                                 return err;
1866
1867                         tg3_readphy(tp, MII_BMSR, &bmsr);
1868                         for (i = 0; i < 1000; i++) {
1869                                 udelay(10);
1870                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1871                                     (bmsr & BMSR_LSTATUS)) {
1872                                         udelay(40);
1873                                         break;
1874                                 }
1875                         }
1876
1877                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1878                             !(bmsr & BMSR_LSTATUS) &&
1879                             tp->link_config.active_speed == SPEED_1000) {
1880                                 err = tg3_phy_reset(tp);
1881                                 if (!err)
1882                                         err = tg3_init_5401phy_dsp(tp);
1883                                 if (err)
1884                                         return err;
1885                         }
1886                 }
1887         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1888                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1889                 /* 5701 {A0,B0} CRC bug workaround */
1890                 tg3_writephy(tp, 0x15, 0x0a75);
1891                 tg3_writephy(tp, 0x1c, 0x8c68);
1892                 tg3_writephy(tp, 0x1c, 0x8d68);
1893                 tg3_writephy(tp, 0x1c, 0x8c68);
1894         }
1895
1896         /* Clear pending interrupts... */
1897         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1898         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1899
1900         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1901                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1902         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1903                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1904
1905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1906             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1907                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1908                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1909                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1910                 else
1911                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1912         }
1913
1914         current_link_up = 0;
1915         current_speed = SPEED_INVALID;
1916         current_duplex = DUPLEX_INVALID;
1917
1918         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1919                 u32 val;
1920
1921                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1922                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1923                 if (!(val & (1 << 10))) {
1924                         val |= (1 << 10);
1925                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1926                         goto relink;
1927                 }
1928         }
1929
1930         bmsr = 0;
1931         for (i = 0; i < 100; i++) {
1932                 tg3_readphy(tp, MII_BMSR, &bmsr);
1933                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1934                     (bmsr & BMSR_LSTATUS))
1935                         break;
1936                 udelay(40);
1937         }
1938
1939         if (bmsr & BMSR_LSTATUS) {
1940                 u32 aux_stat, bmcr;
1941
1942                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1943                 for (i = 0; i < 2000; i++) {
1944                         udelay(10);
1945                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1946                             aux_stat)
1947                                 break;
1948                 }
1949
1950                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1951                                              &current_speed,
1952                                              &current_duplex);
1953
1954                 bmcr = 0;
1955                 for (i = 0; i < 200; i++) {
1956                         tg3_readphy(tp, MII_BMCR, &bmcr);
1957                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1958                                 continue;
1959                         if (bmcr && bmcr != 0x7fff)
1960                                 break;
1961                         udelay(10);
1962                 }
1963
1964                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1965                         if (bmcr & BMCR_ANENABLE) {
1966                                 current_link_up = 1;
1967
1968                                 /* Force autoneg restart if we are exiting
1969                                  * low power mode.
1970                                  */
1971                                 if (!tg3_copper_is_advertising_all(tp,
1972                                                 tp->link_config.advertising))
1973                                         current_link_up = 0;
1974                         } else {
1975                                 current_link_up = 0;
1976                         }
1977                 } else {
1978                         if (!(bmcr & BMCR_ANENABLE) &&
1979                             tp->link_config.speed == current_speed &&
1980                             tp->link_config.duplex == current_duplex) {
1981                                 current_link_up = 1;
1982                         } else {
1983                                 current_link_up = 0;
1984                         }
1985                 }
1986
1987                 tp->link_config.active_speed = current_speed;
1988                 tp->link_config.active_duplex = current_duplex;
1989         }
1990
1991         if (current_link_up == 1 &&
1992             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1993             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1994                 u32 local_adv, remote_adv;
1995
1996                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1997                         local_adv = 0;
1998                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1999
2000                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2001                         remote_adv = 0;
2002
2003                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2004
2005                 /* If we are not advertising full pause capability,
2006                  * something is wrong.  Bring the link down and reconfigure.
2007                  */
2008                 if (local_adv != ADVERTISE_PAUSE_CAP) {
2009                         current_link_up = 0;
2010                 } else {
2011                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2012                 }
2013         }
2014 relink:
2015         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2016                 u32 tmp;
2017
2018                 tg3_phy_copper_begin(tp);
2019
2020                 tg3_readphy(tp, MII_BMSR, &tmp);
2021                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2022                     (tmp & BMSR_LSTATUS))
2023                         current_link_up = 1;
2024         }
2025
2026         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2027         if (current_link_up == 1) {
2028                 if (tp->link_config.active_speed == SPEED_100 ||
2029                     tp->link_config.active_speed == SPEED_10)
2030                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2031                 else
2032                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2033         } else
2034                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2035
2036         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2037         if (tp->link_config.active_duplex == DUPLEX_HALF)
2038                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2039
2040         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2041                 if (current_link_up == 1 &&
2042                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2043                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2044                 else
2045                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2046         }
2047
2048         /* ??? Without this setting Netgear GA302T PHY does not
2049          * ??? send/receive packets...
2050          */
2051         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2052             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2053                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2054                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2055                 udelay(80);
2056         }
2057
2058         tw32_f(MAC_MODE, tp->mac_mode);
2059         udelay(40);
2060
2061         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2062                 /* Polled via timer. */
2063                 tw32_f(MAC_EVENT, 0);
2064         } else {
2065                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2066         }
2067         udelay(40);
2068
2069         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2070             current_link_up == 1 &&
2071             tp->link_config.active_speed == SPEED_1000 &&
2072             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2073              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2074                 udelay(120);
2075                 tw32_f(MAC_STATUS,
2076                      (MAC_STATUS_SYNC_CHANGED |
2077                       MAC_STATUS_CFG_CHANGED));
2078                 udelay(40);
2079                 tg3_write_mem(tp,
2080                               NIC_SRAM_FIRMWARE_MBOX,
2081                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2082         }
2083
2084         if (current_link_up != netif_carrier_ok(tp->dev)) {
2085                 if (current_link_up)
2086                         netif_carrier_on(tp->dev);
2087                 else
2088                         netif_carrier_off(tp->dev);
2089                 tg3_link_report(tp);
2090         }
2091
2092         return 0;
2093 }
2094
2095 struct tg3_fiber_aneginfo {
2096         int state;
2097 #define ANEG_STATE_UNKNOWN              0
2098 #define ANEG_STATE_AN_ENABLE            1
2099 #define ANEG_STATE_RESTART_INIT         2
2100 #define ANEG_STATE_RESTART              3
2101 #define ANEG_STATE_DISABLE_LINK_OK      4
2102 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2103 #define ANEG_STATE_ABILITY_DETECT       6
2104 #define ANEG_STATE_ACK_DETECT_INIT      7
2105 #define ANEG_STATE_ACK_DETECT           8
2106 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2107 #define ANEG_STATE_COMPLETE_ACK         10
2108 #define ANEG_STATE_IDLE_DETECT_INIT     11
2109 #define ANEG_STATE_IDLE_DETECT          12
2110 #define ANEG_STATE_LINK_OK              13
2111 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2112 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2113
2114         u32 flags;
2115 #define MR_AN_ENABLE            0x00000001
2116 #define MR_RESTART_AN           0x00000002
2117 #define MR_AN_COMPLETE          0x00000004
2118 #define MR_PAGE_RX              0x00000008
2119 #define MR_NP_LOADED            0x00000010
2120 #define MR_TOGGLE_TX            0x00000020
2121 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2122 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2123 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2124 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2125 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2126 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2127 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2128 #define MR_TOGGLE_RX            0x00002000
2129 #define MR_NP_RX                0x00004000
2130
2131 #define MR_LINK_OK              0x80000000
2132
2133         unsigned long link_time, cur_time;
2134
2135         u32 ability_match_cfg;
2136         int ability_match_count;
2137
2138         char ability_match, idle_match, ack_match;
2139
2140         u32 txconfig, rxconfig;
2141 #define ANEG_CFG_NP             0x00000080
2142 #define ANEG_CFG_ACK            0x00000040
2143 #define ANEG_CFG_RF2            0x00000020
2144 #define ANEG_CFG_RF1            0x00000010
2145 #define ANEG_CFG_PS2            0x00000001
2146 #define ANEG_CFG_PS1            0x00008000
2147 #define ANEG_CFG_HD             0x00004000
2148 #define ANEG_CFG_FD             0x00002000
2149 #define ANEG_CFG_INVAL          0x00001f06
2150
2151 };
2152 #define ANEG_OK         0
2153 #define ANEG_DONE       1
2154 #define ANEG_TIMER_ENAB 2
2155 #define ANEG_FAILED     -1
2156
2157 #define ANEG_STATE_SETTLE_TIME  10000
2158
2159 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2160                                    struct tg3_fiber_aneginfo *ap)
2161 {
2162         unsigned long delta;
2163         u32 rx_cfg_reg;
2164         int ret;
2165
2166         if (ap->state == ANEG_STATE_UNKNOWN) {
2167                 ap->rxconfig = 0;
2168                 ap->link_time = 0;
2169                 ap->cur_time = 0;
2170                 ap->ability_match_cfg = 0;
2171                 ap->ability_match_count = 0;
2172                 ap->ability_match = 0;
2173                 ap->idle_match = 0;
2174                 ap->ack_match = 0;
2175         }
2176         ap->cur_time++;
2177
2178         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2179                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2180
2181                 if (rx_cfg_reg != ap->ability_match_cfg) {
2182                         ap->ability_match_cfg = rx_cfg_reg;
2183                         ap->ability_match = 0;
2184                         ap->ability_match_count = 0;
2185                 } else {
2186                         if (++ap->ability_match_count > 1) {
2187                                 ap->ability_match = 1;
2188                                 ap->ability_match_cfg = rx_cfg_reg;
2189                         }
2190                 }
2191                 if (rx_cfg_reg & ANEG_CFG_ACK)
2192                         ap->ack_match = 1;
2193                 else
2194                         ap->ack_match = 0;
2195
2196                 ap->idle_match = 0;
2197         } else {
2198                 ap->idle_match = 1;
2199                 ap->ability_match_cfg = 0;
2200                 ap->ability_match_count = 0;
2201                 ap->ability_match = 0;
2202                 ap->ack_match = 0;
2203
2204                 rx_cfg_reg = 0;
2205         }
2206
2207         ap->rxconfig = rx_cfg_reg;
2208         ret = ANEG_OK;
2209
2210         switch(ap->state) {
2211         case ANEG_STATE_UNKNOWN:
2212                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2213                         ap->state = ANEG_STATE_AN_ENABLE;
2214
2215                 /* fallthru */
2216         case ANEG_STATE_AN_ENABLE:
2217                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2218                 if (ap->flags & MR_AN_ENABLE) {
2219                         ap->link_time = 0;
2220                         ap->cur_time = 0;
2221                         ap->ability_match_cfg = 0;
2222                         ap->ability_match_count = 0;
2223                         ap->ability_match = 0;
2224                         ap->idle_match = 0;
2225                         ap->ack_match = 0;
2226
2227                         ap->state = ANEG_STATE_RESTART_INIT;
2228                 } else {
2229                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2230                 }
2231                 break;
2232
2233         case ANEG_STATE_RESTART_INIT:
2234                 ap->link_time = ap->cur_time;
2235                 ap->flags &= ~(MR_NP_LOADED);
2236                 ap->txconfig = 0;
2237                 tw32(MAC_TX_AUTO_NEG, 0);
2238                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2239                 tw32_f(MAC_MODE, tp->mac_mode);
2240                 udelay(40);
2241
2242                 ret = ANEG_TIMER_ENAB;
2243                 ap->state = ANEG_STATE_RESTART;
2244
2245                 /* fallthru */
2246         case ANEG_STATE_RESTART:
2247                 delta = ap->cur_time - ap->link_time;
2248                 if (delta > ANEG_STATE_SETTLE_TIME) {
2249                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2250                 } else {
2251                         ret = ANEG_TIMER_ENAB;
2252                 }
2253                 break;
2254
2255         case ANEG_STATE_DISABLE_LINK_OK:
2256                 ret = ANEG_DONE;
2257                 break;
2258
2259         case ANEG_STATE_ABILITY_DETECT_INIT:
2260                 ap->flags &= ~(MR_TOGGLE_TX);
2261                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2262                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2263                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2264                 tw32_f(MAC_MODE, tp->mac_mode);
2265                 udelay(40);
2266
2267                 ap->state = ANEG_STATE_ABILITY_DETECT;
2268                 break;
2269
2270         case ANEG_STATE_ABILITY_DETECT:
2271                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2272                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2273                 }
2274                 break;
2275
2276         case ANEG_STATE_ACK_DETECT_INIT:
2277                 ap->txconfig |= ANEG_CFG_ACK;
2278                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2279                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2280                 tw32_f(MAC_MODE, tp->mac_mode);
2281                 udelay(40);
2282
2283                 ap->state = ANEG_STATE_ACK_DETECT;
2284
2285                 /* fallthru */
2286         case ANEG_STATE_ACK_DETECT:
2287                 if (ap->ack_match != 0) {
2288                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2289                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2290                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2291                         } else {
2292                                 ap->state = ANEG_STATE_AN_ENABLE;
2293                         }
2294                 } else if (ap->ability_match != 0 &&
2295                            ap->rxconfig == 0) {
2296                         ap->state = ANEG_STATE_AN_ENABLE;
2297                 }
2298                 break;
2299
2300         case ANEG_STATE_COMPLETE_ACK_INIT:
2301                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2302                         ret = ANEG_FAILED;
2303                         break;
2304                 }
2305                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2306                                MR_LP_ADV_HALF_DUPLEX |
2307                                MR_LP_ADV_SYM_PAUSE |
2308                                MR_LP_ADV_ASYM_PAUSE |
2309                                MR_LP_ADV_REMOTE_FAULT1 |
2310                                MR_LP_ADV_REMOTE_FAULT2 |
2311                                MR_LP_ADV_NEXT_PAGE |
2312                                MR_TOGGLE_RX |
2313                                MR_NP_RX);
2314                 if (ap->rxconfig & ANEG_CFG_FD)
2315                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2316                 if (ap->rxconfig & ANEG_CFG_HD)
2317                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2318                 if (ap->rxconfig & ANEG_CFG_PS1)
2319                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2320                 if (ap->rxconfig & ANEG_CFG_PS2)
2321                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2322                 if (ap->rxconfig & ANEG_CFG_RF1)
2323                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2324                 if (ap->rxconfig & ANEG_CFG_RF2)
2325                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2326                 if (ap->rxconfig & ANEG_CFG_NP)
2327                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2328
2329                 ap->link_time = ap->cur_time;
2330
2331                 ap->flags ^= (MR_TOGGLE_TX);
2332                 if (ap->rxconfig & 0x0008)
2333                         ap->flags |= MR_TOGGLE_RX;
2334                 if (ap->rxconfig & ANEG_CFG_NP)
2335                         ap->flags |= MR_NP_RX;
2336                 ap->flags |= MR_PAGE_RX;
2337
2338                 ap->state = ANEG_STATE_COMPLETE_ACK;
2339                 ret = ANEG_TIMER_ENAB;
2340                 break;
2341
2342         case ANEG_STATE_COMPLETE_ACK:
2343                 if (ap->ability_match != 0 &&
2344                     ap->rxconfig == 0) {
2345                         ap->state = ANEG_STATE_AN_ENABLE;
2346                         break;
2347                 }
2348                 delta = ap->cur_time - ap->link_time;
2349                 if (delta > ANEG_STATE_SETTLE_TIME) {
2350                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2351                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2352                         } else {
2353                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2354                                     !(ap->flags & MR_NP_RX)) {
2355                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2356                                 } else {
2357                                         ret = ANEG_FAILED;
2358                                 }
2359                         }
2360                 }
2361                 break;
2362
2363         case ANEG_STATE_IDLE_DETECT_INIT:
2364                 ap->link_time = ap->cur_time;
2365                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2366                 tw32_f(MAC_MODE, tp->mac_mode);
2367                 udelay(40);
2368
2369                 ap->state = ANEG_STATE_IDLE_DETECT;
2370                 ret = ANEG_TIMER_ENAB;
2371                 break;
2372
2373         case ANEG_STATE_IDLE_DETECT:
2374                 if (ap->ability_match != 0 &&
2375                     ap->rxconfig == 0) {
2376                         ap->state = ANEG_STATE_AN_ENABLE;
2377                         break;
2378                 }
2379                 delta = ap->cur_time - ap->link_time;
2380                 if (delta > ANEG_STATE_SETTLE_TIME) {
2381                         /* XXX another gem from the Broadcom driver :( */
2382                         ap->state = ANEG_STATE_LINK_OK;
2383                 }
2384                 break;
2385
2386         case ANEG_STATE_LINK_OK:
2387                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2388                 ret = ANEG_DONE;
2389                 break;
2390
2391         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2392                 /* ??? unimplemented */
2393                 break;
2394
2395         case ANEG_STATE_NEXT_PAGE_WAIT:
2396                 /* ??? unimplemented */
2397                 break;
2398
2399         default:
2400                 ret = ANEG_FAILED;
2401                 break;
2402         };
2403
2404         return ret;
2405 }
2406
2407 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2408 {
2409         int res = 0;
2410         struct tg3_fiber_aneginfo aninfo;
2411         int status = ANEG_FAILED;
2412         unsigned int tick;
2413         u32 tmp;
2414
2415         tw32_f(MAC_TX_AUTO_NEG, 0);
2416
2417         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2418         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2419         udelay(40);
2420
2421         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2422         udelay(40);
2423
2424         memset(&aninfo, 0, sizeof(aninfo));
2425         aninfo.flags |= MR_AN_ENABLE;
2426         aninfo.state = ANEG_STATE_UNKNOWN;
2427         aninfo.cur_time = 0;
2428         tick = 0;
2429         while (++tick < 195000) {
2430                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2431                 if (status == ANEG_DONE || status == ANEG_FAILED)
2432                         break;
2433
2434                 udelay(1);
2435         }
2436
2437         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2438         tw32_f(MAC_MODE, tp->mac_mode);
2439         udelay(40);
2440
2441         *flags = aninfo.flags;
2442
2443         if (status == ANEG_DONE &&
2444             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2445                              MR_LP_ADV_FULL_DUPLEX)))
2446                 res = 1;
2447
2448         return res;
2449 }
2450
2451 static void tg3_init_bcm8002(struct tg3 *tp)
2452 {
2453         u32 mac_status = tr32(MAC_STATUS);
2454         int i;
2455
2456         /* Reset when initting first time or we have a link. */
2457         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2458             !(mac_status & MAC_STATUS_PCS_SYNCED))
2459                 return;
2460
2461         /* Set PLL lock range. */
2462         tg3_writephy(tp, 0x16, 0x8007);
2463
2464         /* SW reset */
2465         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2466
2467         /* Wait for reset to complete. */
2468         /* XXX schedule_timeout() ... */
2469         for (i = 0; i < 500; i++)
2470                 udelay(10);
2471
2472         /* Config mode; select PMA/Ch 1 regs. */
2473         tg3_writephy(tp, 0x10, 0x8411);
2474
2475         /* Enable auto-lock and comdet, select txclk for tx. */
2476         tg3_writephy(tp, 0x11, 0x0a10);
2477
2478         tg3_writephy(tp, 0x18, 0x00a0);
2479         tg3_writephy(tp, 0x16, 0x41ff);
2480
2481         /* Assert and deassert POR. */
2482         tg3_writephy(tp, 0x13, 0x0400);
2483         udelay(40);
2484         tg3_writephy(tp, 0x13, 0x0000);
2485
2486         tg3_writephy(tp, 0x11, 0x0a50);
2487         udelay(40);
2488         tg3_writephy(tp, 0x11, 0x0a10);
2489
2490         /* Wait for signal to stabilize */
2491         /* XXX schedule_timeout() ... */
2492         for (i = 0; i < 15000; i++)
2493                 udelay(10);
2494
2495         /* Deselect the channel register so we can read the PHYID
2496          * later.
2497          */
2498         tg3_writephy(tp, 0x10, 0x8011);
2499 }
2500
2501 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2502 {
2503         u32 sg_dig_ctrl, sg_dig_status;
2504         u32 serdes_cfg, expected_sg_dig_ctrl;
2505         int workaround, port_a;
2506         int current_link_up;
2507
2508         serdes_cfg = 0;
2509         expected_sg_dig_ctrl = 0;
2510         workaround = 0;
2511         port_a = 1;
2512         current_link_up = 0;
2513
2514         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2515             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2516                 workaround = 1;
2517                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2518                         port_a = 0;
2519
2520                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2521                 /* preserve bits 20-23 for voltage regulator */
2522                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2523         }
2524
2525         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2526
2527         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2528                 if (sg_dig_ctrl & (1 << 31)) {
2529                         if (workaround) {
2530                                 u32 val = serdes_cfg;
2531
2532                                 if (port_a)
2533                                         val |= 0xc010000;
2534                                 else
2535                                         val |= 0x4010000;
2536                                 tw32_f(MAC_SERDES_CFG, val);
2537                         }
2538                         tw32_f(SG_DIG_CTRL, 0x01388400);
2539                 }
2540                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2541                         tg3_setup_flow_control(tp, 0, 0);
2542                         current_link_up = 1;
2543                 }
2544                 goto out;
2545         }
2546
2547         /* Want auto-negotiation.  */
2548         expected_sg_dig_ctrl = 0x81388400;
2549
2550         /* Pause capability */
2551         expected_sg_dig_ctrl |= (1 << 11);
2552
2553         /* Asymettric pause */
2554         expected_sg_dig_ctrl |= (1 << 12);
2555
2556         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2557                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2558                     tp->serdes_counter &&
2559                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2560                                     MAC_STATUS_RCVD_CFG)) ==
2561                      MAC_STATUS_PCS_SYNCED)) {
2562                         tp->serdes_counter--;
2563                         current_link_up = 1;
2564                         goto out;
2565                 }
2566 restart_autoneg:
2567                 if (workaround)
2568                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2569                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2570                 udelay(5);
2571                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2572
2573                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2574                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2575         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2576                                  MAC_STATUS_SIGNAL_DET)) {
2577                 sg_dig_status = tr32(SG_DIG_STATUS);
2578                 mac_status = tr32(MAC_STATUS);
2579
2580                 if ((sg_dig_status & (1 << 1)) &&
2581                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2582                         u32 local_adv, remote_adv;
2583
2584                         local_adv = ADVERTISE_PAUSE_CAP;
2585                         remote_adv = 0;
2586                         if (sg_dig_status & (1 << 19))
2587                                 remote_adv |= LPA_PAUSE_CAP;
2588                         if (sg_dig_status & (1 << 20))
2589                                 remote_adv |= LPA_PAUSE_ASYM;
2590
2591                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2592                         current_link_up = 1;
2593                         tp->serdes_counter = 0;
2594                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2595                 } else if (!(sg_dig_status & (1 << 1))) {
2596                         if (tp->serdes_counter)
2597                                 tp->serdes_counter--;
2598                         else {
2599                                 if (workaround) {
2600                                         u32 val = serdes_cfg;
2601
2602                                         if (port_a)
2603                                                 val |= 0xc010000;
2604                                         else
2605                                                 val |= 0x4010000;
2606
2607                                         tw32_f(MAC_SERDES_CFG, val);
2608                                 }
2609
2610                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2611                                 udelay(40);
2612
2613                                 /* Link parallel detection - link is up */
2614                                 /* only if we have PCS_SYNC and not */
2615                                 /* receiving config code words */
2616                                 mac_status = tr32(MAC_STATUS);
2617                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2618                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2619                                         tg3_setup_flow_control(tp, 0, 0);
2620                                         current_link_up = 1;
2621                                         tp->tg3_flags2 |=
2622                                                 TG3_FLG2_PARALLEL_DETECT;
2623                                         tp->serdes_counter =
2624                                                 SERDES_PARALLEL_DET_TIMEOUT;
2625                                 } else
2626                                         goto restart_autoneg;
2627                         }
2628                 }
2629         } else {
2630                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2631                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2632         }
2633
2634 out:
2635         return current_link_up;
2636 }
2637
2638 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2639 {
2640         int current_link_up = 0;
2641
2642         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2643                 goto out;
2644
2645         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2646                 u32 flags;
2647                 int i;
2648
2649                 if (fiber_autoneg(tp, &flags)) {
2650                         u32 local_adv, remote_adv;
2651
2652                         local_adv = ADVERTISE_PAUSE_CAP;
2653                         remote_adv = 0;
2654                         if (flags & MR_LP_ADV_SYM_PAUSE)
2655                                 remote_adv |= LPA_PAUSE_CAP;
2656                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2657                                 remote_adv |= LPA_PAUSE_ASYM;
2658
2659                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2660
2661                         current_link_up = 1;
2662                 }
2663                 for (i = 0; i < 30; i++) {
2664                         udelay(20);
2665                         tw32_f(MAC_STATUS,
2666                                (MAC_STATUS_SYNC_CHANGED |
2667                                 MAC_STATUS_CFG_CHANGED));
2668                         udelay(40);
2669                         if ((tr32(MAC_STATUS) &
2670                              (MAC_STATUS_SYNC_CHANGED |
2671                               MAC_STATUS_CFG_CHANGED)) == 0)
2672                                 break;
2673                 }
2674
2675                 mac_status = tr32(MAC_STATUS);
2676                 if (current_link_up == 0 &&
2677                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2678                     !(mac_status & MAC_STATUS_RCVD_CFG))
2679                         current_link_up = 1;
2680         } else {
2681                 /* Forcing 1000FD link up. */
2682                 current_link_up = 1;
2683
2684                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2685                 udelay(40);
2686
2687                 tw32_f(MAC_MODE, tp->mac_mode);
2688                 udelay(40);
2689         }
2690
2691 out:
2692         return current_link_up;
2693 }
2694
2695 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2696 {
2697         u32 orig_pause_cfg;
2698         u16 orig_active_speed;
2699         u8 orig_active_duplex;
2700         u32 mac_status;
2701         int current_link_up;
2702         int i;
2703
2704         orig_pause_cfg =
2705                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2706                                   TG3_FLAG_TX_PAUSE));
2707         orig_active_speed = tp->link_config.active_speed;
2708         orig_active_duplex = tp->link_config.active_duplex;
2709
2710         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2711             netif_carrier_ok(tp->dev) &&
2712             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2713                 mac_status = tr32(MAC_STATUS);
2714                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2715                                MAC_STATUS_SIGNAL_DET |
2716                                MAC_STATUS_CFG_CHANGED |
2717                                MAC_STATUS_RCVD_CFG);
2718                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2719                                    MAC_STATUS_SIGNAL_DET)) {
2720                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2721                                             MAC_STATUS_CFG_CHANGED));
2722                         return 0;
2723                 }
2724         }
2725
2726         tw32_f(MAC_TX_AUTO_NEG, 0);
2727
2728         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2729         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2730         tw32_f(MAC_MODE, tp->mac_mode);
2731         udelay(40);
2732
2733         if (tp->phy_id == PHY_ID_BCM8002)
2734                 tg3_init_bcm8002(tp);
2735
2736         /* Enable link change event even when serdes polling.  */
2737         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2738         udelay(40);
2739
2740         current_link_up = 0;
2741         mac_status = tr32(MAC_STATUS);
2742
2743         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2744                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2745         else
2746                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2747
2748         tp->hw_status->status =
2749                 (SD_STATUS_UPDATED |
2750                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2751
2752         for (i = 0; i < 100; i++) {
2753                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2754                                     MAC_STATUS_CFG_CHANGED));
2755                 udelay(5);
2756                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2757                                          MAC_STATUS_CFG_CHANGED |
2758                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2759                         break;
2760         }
2761
2762         mac_status = tr32(MAC_STATUS);
2763         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2764                 current_link_up = 0;
2765                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2766                     tp->serdes_counter == 0) {
2767                         tw32_f(MAC_MODE, (tp->mac_mode |
2768                                           MAC_MODE_SEND_CONFIGS));
2769                         udelay(1);
2770                         tw32_f(MAC_MODE, tp->mac_mode);
2771                 }
2772         }
2773
2774         if (current_link_up == 1) {
2775                 tp->link_config.active_speed = SPEED_1000;
2776                 tp->link_config.active_duplex = DUPLEX_FULL;
2777                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2778                                     LED_CTRL_LNKLED_OVERRIDE |
2779                                     LED_CTRL_1000MBPS_ON));
2780         } else {
2781                 tp->link_config.active_speed = SPEED_INVALID;
2782                 tp->link_config.active_duplex = DUPLEX_INVALID;
2783                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2784                                     LED_CTRL_LNKLED_OVERRIDE |
2785                                     LED_CTRL_TRAFFIC_OVERRIDE));
2786         }
2787
2788         if (current_link_up != netif_carrier_ok(tp->dev)) {
2789                 if (current_link_up)
2790                         netif_carrier_on(tp->dev);
2791                 else
2792                         netif_carrier_off(tp->dev);
2793                 tg3_link_report(tp);
2794         } else {
2795                 u32 now_pause_cfg =
2796                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2797                                          TG3_FLAG_TX_PAUSE);
2798                 if (orig_pause_cfg != now_pause_cfg ||
2799                     orig_active_speed != tp->link_config.active_speed ||
2800                     orig_active_duplex != tp->link_config.active_duplex)
2801                         tg3_link_report(tp);
2802         }
2803
2804         return 0;
2805 }
2806
2807 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2808 {
2809         int current_link_up, err = 0;
2810         u32 bmsr, bmcr;
2811         u16 current_speed;
2812         u8 current_duplex;
2813
2814         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2815         tw32_f(MAC_MODE, tp->mac_mode);
2816         udelay(40);
2817
2818         tw32(MAC_EVENT, 0);
2819
2820         tw32_f(MAC_STATUS,
2821              (MAC_STATUS_SYNC_CHANGED |
2822               MAC_STATUS_CFG_CHANGED |
2823               MAC_STATUS_MI_COMPLETION |
2824               MAC_STATUS_LNKSTATE_CHANGED));
2825         udelay(40);
2826
2827         if (force_reset)
2828                 tg3_phy_reset(tp);
2829
2830         current_link_up = 0;
2831         current_speed = SPEED_INVALID;
2832         current_duplex = DUPLEX_INVALID;
2833
2834         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2835         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2836         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2837                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2838                         bmsr |= BMSR_LSTATUS;
2839                 else
2840                         bmsr &= ~BMSR_LSTATUS;
2841         }
2842
2843         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2844
2845         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2846             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2847                 /* do nothing, just check for link up at the end */
2848         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2849                 u32 adv, new_adv;
2850
2851                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2852                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2853                                   ADVERTISE_1000XPAUSE |
2854                                   ADVERTISE_1000XPSE_ASYM |
2855                                   ADVERTISE_SLCT);
2856
2857                 /* Always advertise symmetric PAUSE just like copper */
2858                 new_adv |= ADVERTISE_1000XPAUSE;
2859
2860                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2861                         new_adv |= ADVERTISE_1000XHALF;
2862                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2863                         new_adv |= ADVERTISE_1000XFULL;
2864
2865                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2866                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2868                         tg3_writephy(tp, MII_BMCR, bmcr);
2869
2870                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2871                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2872                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2873
2874                         return err;
2875                 }
2876         } else {
2877                 u32 new_bmcr;
2878
2879                 bmcr &= ~BMCR_SPEED1000;
2880                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2881
2882                 if (tp->link_config.duplex == DUPLEX_FULL)
2883                         new_bmcr |= BMCR_FULLDPLX;
2884
2885                 if (new_bmcr != bmcr) {
2886                         /* BMCR_SPEED1000 is a reserved bit that needs
2887                          * to be set on write.
2888                          */
2889                         new_bmcr |= BMCR_SPEED1000;
2890
2891                         /* Force a linkdown */
2892                         if (netif_carrier_ok(tp->dev)) {
2893                                 u32 adv;
2894
2895                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2896                                 adv &= ~(ADVERTISE_1000XFULL |
2897                                          ADVERTISE_1000XHALF |
2898                                          ADVERTISE_SLCT);
2899                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2900                                 tg3_writephy(tp, MII_BMCR, bmcr |
2901                                                            BMCR_ANRESTART |
2902                                                            BMCR_ANENABLE);
2903                                 udelay(10);
2904                                 netif_carrier_off(tp->dev);
2905                         }
2906                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2907                         bmcr = new_bmcr;
2908                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2909                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2910                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2911                             ASIC_REV_5714) {
2912                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2913                                         bmsr |= BMSR_LSTATUS;
2914                                 else
2915                                         bmsr &= ~BMSR_LSTATUS;
2916                         }
2917                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2918                 }
2919         }
2920
2921         if (bmsr & BMSR_LSTATUS) {
2922                 current_speed = SPEED_1000;
2923                 current_link_up = 1;
2924                 if (bmcr & BMCR_FULLDPLX)
2925                         current_duplex = DUPLEX_FULL;
2926                 else
2927                         current_duplex = DUPLEX_HALF;
2928
2929                 if (bmcr & BMCR_ANENABLE) {
2930                         u32 local_adv, remote_adv, common;
2931
2932                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2933                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2934                         common = local_adv & remote_adv;
2935                         if (common & (ADVERTISE_1000XHALF |
2936                                       ADVERTISE_1000XFULL)) {
2937                                 if (common & ADVERTISE_1000XFULL)
2938                                         current_duplex = DUPLEX_FULL;
2939                                 else
2940                                         current_duplex = DUPLEX_HALF;
2941
2942                                 tg3_setup_flow_control(tp, local_adv,
2943                                                        remote_adv);
2944                         }
2945                         else
2946                                 current_link_up = 0;
2947                 }
2948         }
2949
2950         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2951         if (tp->link_config.active_duplex == DUPLEX_HALF)
2952                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2953
2954         tw32_f(MAC_MODE, tp->mac_mode);
2955         udelay(40);
2956
2957         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2958
2959         tp->link_config.active_speed = current_speed;
2960         tp->link_config.active_duplex = current_duplex;
2961
2962         if (current_link_up != netif_carrier_ok(tp->dev)) {
2963                 if (current_link_up)
2964                         netif_carrier_on(tp->dev);
2965                 else {
2966                         netif_carrier_off(tp->dev);
2967                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2968                 }
2969                 tg3_link_report(tp);
2970         }
2971         return err;
2972 }
2973
2974 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2975 {
2976         if (tp->serdes_counter) {
2977                 /* Give autoneg time to complete. */
2978                 tp->serdes_counter--;
2979                 return;
2980         }
2981         if (!netif_carrier_ok(tp->dev) &&
2982             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2983                 u32 bmcr;
2984
2985                 tg3_readphy(tp, MII_BMCR, &bmcr);
2986                 if (bmcr & BMCR_ANENABLE) {
2987                         u32 phy1, phy2;
2988
2989                         /* Select shadow register 0x1f */
2990                         tg3_writephy(tp, 0x1c, 0x7c00);
2991                         tg3_readphy(tp, 0x1c, &phy1);
2992
2993                         /* Select expansion interrupt status register */
2994                         tg3_writephy(tp, 0x17, 0x0f01);
2995                         tg3_readphy(tp, 0x15, &phy2);
2996                         tg3_readphy(tp, 0x15, &phy2);
2997
2998                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2999                                 /* We have signal detect and not receiving
3000                                  * config code words, link is up by parallel
3001                                  * detection.
3002                                  */
3003
3004                                 bmcr &= ~BMCR_ANENABLE;
3005                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3006                                 tg3_writephy(tp, MII_BMCR, bmcr);
3007                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3008                         }
3009                 }
3010         }
3011         else if (netif_carrier_ok(tp->dev) &&
3012                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3013                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3014                 u32 phy2;
3015
3016                 /* Select expansion interrupt status register */
3017                 tg3_writephy(tp, 0x17, 0x0f01);
3018                 tg3_readphy(tp, 0x15, &phy2);
3019                 if (phy2 & 0x20) {
3020                         u32 bmcr;
3021
3022                         /* Config code words received, turn on autoneg. */
3023                         tg3_readphy(tp, MII_BMCR, &bmcr);
3024                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3025
3026                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3027
3028                 }
3029         }
3030 }
3031
3032 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3033 {
3034         int err;
3035
3036         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3037                 err = tg3_setup_fiber_phy(tp, force_reset);
3038         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3039                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3040         } else {
3041                 err = tg3_setup_copper_phy(tp, force_reset);
3042         }
3043
3044         if (tp->link_config.active_speed == SPEED_1000 &&
3045             tp->link_config.active_duplex == DUPLEX_HALF)
3046                 tw32(MAC_TX_LENGTHS,
3047                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3048                       (6 << TX_LENGTHS_IPG_SHIFT) |
3049                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3050         else
3051                 tw32(MAC_TX_LENGTHS,
3052                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3053                       (6 << TX_LENGTHS_IPG_SHIFT) |
3054                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3055
3056         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3057                 if (netif_carrier_ok(tp->dev)) {
3058                         tw32(HOSTCC_STAT_COAL_TICKS,
3059                              tp->coal.stats_block_coalesce_usecs);
3060                 } else {
3061                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3062                 }
3063         }
3064
3065         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3066                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3067                 if (!netif_carrier_ok(tp->dev))
3068                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3069                               tp->pwrmgmt_thresh;
3070                 else
3071                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3072                 tw32(PCIE_PWR_MGMT_THRESH, val);
3073         }
3074
3075         return err;
3076 }
3077
3078 /* This is called whenever we suspect that the system chipset is re-
3079  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3080  * is bogus tx completions. We try to recover by setting the
3081  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3082  * in the workqueue.
3083  */
3084 static void tg3_tx_recover(struct tg3 *tp)
3085 {
3086         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3087                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3088
3089         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3090                "mapped I/O cycles to the network device, attempting to "
3091                "recover. Please report the problem to the driver maintainer "
3092                "and include system chipset information.\n", tp->dev->name);
3093
3094         spin_lock(&tp->lock);
3095         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3096         spin_unlock(&tp->lock);
3097 }
3098
3099 static inline u32 tg3_tx_avail(struct tg3 *tp)
3100 {
3101         smp_mb();
3102         return (tp->tx_pending -
3103                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3104 }
3105
3106 /* Tigon3 never reports partial packet sends.  So we do not
3107  * need special logic to handle SKBs that have not had all
3108  * of their frags sent yet, like SunGEM does.
3109  */
3110 static void tg3_tx(struct tg3 *tp)
3111 {
3112         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3113         u32 sw_idx = tp->tx_cons;
3114
3115         while (sw_idx != hw_idx) {
3116                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3117                 struct sk_buff *skb = ri->skb;
3118                 int i, tx_bug = 0;
3119
3120                 if (unlikely(skb == NULL)) {
3121                         tg3_tx_recover(tp);
3122                         return;
3123                 }
3124
3125                 pci_unmap_single(tp->pdev,
3126                                  pci_unmap_addr(ri, mapping),
3127                                  skb_headlen(skb),
3128                                  PCI_DMA_TODEVICE);
3129
3130                 ri->skb = NULL;
3131
3132                 sw_idx = NEXT_TX(sw_idx);
3133
3134                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3135                         ri = &tp->tx_buffers[sw_idx];
3136                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3137                                 tx_bug = 1;
3138
3139                         pci_unmap_page(tp->pdev,
3140                                        pci_unmap_addr(ri, mapping),
3141                                        skb_shinfo(skb)->frags[i].size,
3142                                        PCI_DMA_TODEVICE);
3143
3144                         sw_idx = NEXT_TX(sw_idx);
3145                 }
3146
3147                 dev_kfree_skb(skb);
3148
3149                 if (unlikely(tx_bug)) {
3150                         tg3_tx_recover(tp);
3151                         return;
3152                 }
3153         }
3154
3155         tp->tx_cons = sw_idx;
3156
3157         /* Need to make the tx_cons update visible to tg3_start_xmit()
3158          * before checking for netif_queue_stopped().  Without the
3159          * memory barrier, there is a small possibility that tg3_start_xmit()
3160          * will miss it and cause the queue to be stopped forever.
3161          */
3162         smp_mb();
3163
3164         if (unlikely(netif_queue_stopped(tp->dev) &&
3165                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3166                 netif_tx_lock(tp->dev);
3167                 if (netif_queue_stopped(tp->dev) &&
3168                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3169                         netif_wake_queue(tp->dev);
3170                 netif_tx_unlock(tp->dev);
3171         }
3172 }
3173
3174 /* Returns size of skb allocated or < 0 on error.
3175  *
3176  * We only need to fill in the address because the other members
3177  * of the RX descriptor are invariant, see tg3_init_rings.
3178  *
3179  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3180  * posting buffers we only dirty the first cache line of the RX
3181  * descriptor (containing the address).  Whereas for the RX status
3182  * buffers the cpu only reads the last cacheline of the RX descriptor
3183  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3184  */
3185 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3186                             int src_idx, u32 dest_idx_unmasked)
3187 {
3188         struct tg3_rx_buffer_desc *desc;
3189         struct ring_info *map, *src_map;
3190         struct sk_buff *skb;
3191         dma_addr_t mapping;
3192         int skb_size, dest_idx;
3193
3194         src_map = NULL;
3195         switch (opaque_key) {
3196         case RXD_OPAQUE_RING_STD:
3197                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3198                 desc = &tp->rx_std[dest_idx];
3199                 map = &tp->rx_std_buffers[dest_idx];
3200                 if (src_idx >= 0)
3201                         src_map = &tp->rx_std_buffers[src_idx];
3202                 skb_size = tp->rx_pkt_buf_sz;
3203                 break;
3204
3205         case RXD_OPAQUE_RING_JUMBO:
3206                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3207                 desc = &tp->rx_jumbo[dest_idx];
3208                 map = &tp->rx_jumbo_buffers[dest_idx];
3209                 if (src_idx >= 0)
3210                         src_map = &tp->rx_jumbo_buffers[src_idx];
3211                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3212                 break;
3213
3214         default:
3215                 return -EINVAL;
3216         };
3217
3218         /* Do not overwrite any of the map or rp information
3219          * until we are sure we can commit to a new buffer.
3220          *
3221          * Callers depend upon this behavior and assume that
3222          * we leave everything unchanged if we fail.
3223          */
3224         skb = netdev_alloc_skb(tp->dev, skb_size);
3225         if (skb == NULL)
3226                 return -ENOMEM;
3227
3228         skb_reserve(skb, tp->rx_offset);
3229
3230         mapping = pci_map_single(tp->pdev, skb->data,
3231                                  skb_size - tp->rx_offset,
3232                                  PCI_DMA_FROMDEVICE);
3233
3234         map->skb = skb;
3235         pci_unmap_addr_set(map, mapping, mapping);
3236
3237         if (src_map != NULL)
3238                 src_map->skb = NULL;
3239
3240         desc->addr_hi = ((u64)mapping >> 32);
3241         desc->addr_lo = ((u64)mapping & 0xffffffff);
3242
3243         return skb_size;
3244 }
3245
3246 /* We only need to move over in the address because the other
3247  * members of the RX descriptor are invariant.  See notes above
3248  * tg3_alloc_rx_skb for full details.
3249  */
3250 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3251                            int src_idx, u32 dest_idx_unmasked)
3252 {
3253         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3254         struct ring_info *src_map, *dest_map;
3255         int dest_idx;
3256
3257         switch (opaque_key) {
3258         case RXD_OPAQUE_RING_STD:
3259                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3260                 dest_desc = &tp->rx_std[dest_idx];
3261                 dest_map = &tp->rx_std_buffers[dest_idx];
3262                 src_desc = &tp->rx_std[src_idx];
3263                 src_map = &tp->rx_std_buffers[src_idx];
3264                 break;
3265
3266         case RXD_OPAQUE_RING_JUMBO:
3267                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3268                 dest_desc = &tp->rx_jumbo[dest_idx];
3269                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3270                 src_desc = &tp->rx_jumbo[src_idx];
3271                 src_map = &tp->rx_jumbo_buffers[src_idx];
3272                 break;
3273
3274         default:
3275                 return;
3276         };
3277
3278         dest_map->skb = src_map->skb;
3279         pci_unmap_addr_set(dest_map, mapping,
3280                            pci_unmap_addr(src_map, mapping));
3281         dest_desc->addr_hi = src_desc->addr_hi;
3282         dest_desc->addr_lo = src_desc->addr_lo;
3283
3284         src_map->skb = NULL;
3285 }
3286
3287 #if TG3_VLAN_TAG_USED
3288 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3289 {
3290         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3291 }
3292 #endif
3293
3294 /* The RX ring scheme is composed of multiple rings which post fresh
3295  * buffers to the chip, and one special ring the chip uses to report
3296  * status back to the host.
3297  *
3298  * The special ring reports the status of received packets to the
3299  * host.  The chip does not write into the original descriptor the
3300  * RX buffer was obtained from.  The chip simply takes the original
3301  * descriptor as provided by the host, updates the status and length
3302  * field, then writes this into the next status ring entry.
3303  *
3304  * Each ring the host uses to post buffers to the chip is described
3305  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3306  * it is first placed into the on-chip ram.  When the packet's length
3307  * is known, it walks down the TG3_BDINFO entries to select the ring.
3308  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3309  * which is within the range of the new packet's length is chosen.
3310  *
3311  * The "separate ring for rx status" scheme may sound queer, but it makes
3312  * sense from a cache coherency perspective.  If only the host writes
3313  * to the buffer post rings, and only the chip writes to the rx status
3314  * rings, then cache lines never move beyond shared-modified state.
3315  * If both the host and chip were to write into the same ring, cache line
3316  * eviction could occur since both entities want it in an exclusive state.
3317  */
3318 static int tg3_rx(struct tg3 *tp, int budget)
3319 {
3320         u32 work_mask, rx_std_posted = 0;
3321         u32 sw_idx = tp->rx_rcb_ptr;
3322         u16 hw_idx;
3323         int received;
3324
3325         hw_idx = tp->hw_status->idx[0].rx_producer;
3326         /*
3327          * We need to order the read of hw_idx and the read of
3328          * the opaque cookie.
3329          */
3330         rmb();
3331         work_mask = 0;
3332         received = 0;
3333         while (sw_idx != hw_idx && budget > 0) {
3334                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3335                 unsigned int len;
3336                 struct sk_buff *skb;
3337                 dma_addr_t dma_addr;
3338                 u32 opaque_key, desc_idx, *post_ptr;
3339
3340                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3341                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3342                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3343                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3344                                                   mapping);
3345                         skb = tp->rx_std_buffers[desc_idx].skb;
3346                         post_ptr = &tp->rx_std_ptr;
3347                         rx_std_posted++;
3348                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3349                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3350                                                   mapping);
3351                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3352                         post_ptr = &tp->rx_jumbo_ptr;
3353                 }
3354                 else {
3355                         goto next_pkt_nopost;
3356                 }
3357
3358                 work_mask |= opaque_key;
3359
3360                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3361                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3362                 drop_it:
3363                         tg3_recycle_rx(tp, opaque_key,
3364                                        desc_idx, *post_ptr);
3365                 drop_it_no_recycle:
3366                         /* Other statistics kept track of by card. */
3367                         tp->net_stats.rx_dropped++;
3368                         goto next_pkt;
3369                 }
3370
3371                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3372
3373                 if (len > RX_COPY_THRESHOLD
3374                         && tp->rx_offset == 2
3375                         /* rx_offset != 2 iff this is a 5701 card running
3376                          * in PCI-X mode [see tg3_get_invariants()] */
3377                 ) {
3378                         int skb_size;
3379
3380                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3381                                                     desc_idx, *post_ptr);
3382                         if (skb_size < 0)
3383                                 goto drop_it;
3384
3385                         pci_unmap_single(tp->pdev, dma_addr,
3386                                          skb_size - tp->rx_offset,
3387                                          PCI_DMA_FROMDEVICE);
3388
3389                         skb_put(skb, len);
3390                 } else {
3391                         struct sk_buff *copy_skb;
3392
3393                         tg3_recycle_rx(tp, opaque_key,
3394                                        desc_idx, *post_ptr);
3395
3396                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3397                         if (copy_skb == NULL)
3398                                 goto drop_it_no_recycle;
3399
3400                         skb_reserve(copy_skb, 2);
3401                         skb_put(copy_skb, len);
3402                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3403                         skb_copy_from_linear_data(skb, copy_skb->data, len);
3404                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3405
3406                         /* We'll reuse the original ring buffer. */
3407                         skb = copy_skb;
3408                 }
3409
3410                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3411                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3412                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3413                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3414                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3415                 else
3416                         skb->ip_summed = CHECKSUM_NONE;
3417
3418                 skb->protocol = eth_type_trans(skb, tp->dev);
3419 #if TG3_VLAN_TAG_USED
3420                 if (tp->vlgrp != NULL &&
3421                     desc->type_flags & RXD_FLAG_VLAN) {
3422                         tg3_vlan_rx(tp, skb,
3423                                     desc->err_vlan & RXD_VLAN_MASK);
3424                 } else
3425 #endif
3426                         netif_receive_skb(skb);
3427
3428                 tp->dev->last_rx = jiffies;
3429                 received++;
3430                 budget--;
3431
3432 next_pkt:
3433                 (*post_ptr)++;
3434
3435                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3436                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3437
3438                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3439                                      TG3_64BIT_REG_LOW, idx);
3440                         work_mask &= ~RXD_OPAQUE_RING_STD;
3441                         rx_std_posted = 0;
3442                 }
3443 next_pkt_nopost:
3444                 sw_idx++;
3445                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3446
3447                 /* Refresh hw_idx to see if there is new work */
3448                 if (sw_idx == hw_idx) {
3449                         hw_idx = tp->hw_status->idx[0].rx_producer;
3450                         rmb();
3451                 }
3452         }
3453
3454         /* ACK the status ring. */
3455         tp->rx_rcb_ptr = sw_idx;
3456         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3457
3458         /* Refill RX ring(s). */
3459         if (work_mask & RXD_OPAQUE_RING_STD) {
3460                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3461                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3462                              sw_idx);
3463         }
3464         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3465                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3466                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3467                              sw_idx);
3468         }
3469         mmiowb();
3470
3471         return received;
3472 }
3473
3474 static int tg3_poll(struct net_device *netdev, int *budget)
3475 {
3476         struct tg3 *tp = netdev_priv(netdev);
3477         struct tg3_hw_status *sblk = tp->hw_status;
3478         int done;
3479
3480         /* handle link change and other phy events */
3481         if (!(tp->tg3_flags &
3482               (TG3_FLAG_USE_LINKCHG_REG |
3483                TG3_FLAG_POLL_SERDES))) {
3484                 if (sblk->status & SD_STATUS_LINK_CHG) {
3485                         sblk->status = SD_STATUS_UPDATED |
3486                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3487                         spin_lock(&tp->lock);
3488                         tg3_setup_phy(tp, 0);
3489                         spin_unlock(&tp->lock);
3490                 }
3491         }
3492
3493         /* run TX completion thread */
3494         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3495                 tg3_tx(tp);
3496                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3497                         netif_rx_complete(netdev);
3498                         schedule_work(&tp->reset_task);
3499                         return 0;
3500                 }
3501         }
3502
3503         /* run RX thread, within the bounds set by NAPI.
3504          * All RX "locking" is done by ensuring outside
3505          * code synchronizes with dev->poll()
3506          */
3507         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3508                 int orig_budget = *budget;
3509                 int work_done;
3510
3511                 if (orig_budget > netdev->quota)
3512                         orig_budget = netdev->quota;
3513
3514                 work_done = tg3_rx(tp, orig_budget);
3515
3516                 *budget -= work_done;
3517                 netdev->quota -= work_done;
3518         }
3519
3520         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3521                 tp->last_tag = sblk->status_tag;
3522                 rmb();
3523         } else
3524                 sblk->status &= ~SD_STATUS_UPDATED;
3525
3526         /* if no more work, tell net stack and NIC we're done */
3527         done = !tg3_has_work(tp);
3528         if (done) {
3529                 netif_rx_complete(netdev);
3530                 tg3_restart_ints(tp);
3531         }
3532
3533         return (done ? 0 : 1);
3534 }
3535
3536 static void tg3_irq_quiesce(struct tg3 *tp)
3537 {
3538         BUG_ON(tp->irq_sync);
3539
3540         tp->irq_sync = 1;
3541         smp_mb();
3542
3543         synchronize_irq(tp->pdev->irq);
3544 }
3545
3546 static inline int tg3_irq_sync(struct tg3 *tp)
3547 {
3548         return tp->irq_sync;
3549 }
3550
3551 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3552  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3553  * with as well.  Most of the time, this is not necessary except when
3554  * shutting down the device.
3555  */
3556 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3557 {
3558         spin_lock_bh(&tp->lock);
3559         if (irq_sync)
3560                 tg3_irq_quiesce(tp);
3561 }
3562
3563 static inline void tg3_full_unlock(struct tg3 *tp)
3564 {
3565         spin_unlock_bh(&tp->lock);
3566 }
3567
3568 /* One-shot MSI handler - Chip automatically disables interrupt
3569  * after sending MSI so driver doesn't have to do it.
3570  */
3571 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3572 {
3573         struct net_device *dev = dev_id;
3574         struct tg3 *tp = netdev_priv(dev);
3575
3576         prefetch(tp->hw_status);
3577         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3578
3579         if (likely(!tg3_irq_sync(tp)))
3580                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3581
3582         return IRQ_HANDLED;
3583 }
3584
3585 /* MSI ISR - No need to check for interrupt sharing and no need to
3586  * flush status block and interrupt mailbox. PCI ordering rules
3587  * guarantee that MSI will arrive after the status block.
3588  */
3589 static irqreturn_t tg3_msi(int irq, void *dev_id)
3590 {
3591         struct net_device *dev = dev_id;
3592         struct tg3 *tp = netdev_priv(dev);
3593
3594         prefetch(tp->hw_status);
3595         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3596         /*
3597          * Writing any value to intr-mbox-0 clears PCI INTA# and
3598          * chip-internal interrupt pending events.
3599          * Writing non-zero to intr-mbox-0 additional tells the
3600          * NIC to stop sending us irqs, engaging "in-intr-handler"
3601          * event coalescing.
3602          */
3603         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3604         if (likely(!tg3_irq_sync(tp)))
3605                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3606
3607         return IRQ_RETVAL(1);
3608 }
3609
3610 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3611 {
3612         struct net_device *dev = dev_id;
3613         struct tg3 *tp = netdev_priv(dev);
3614         struct tg3_hw_status *sblk = tp->hw_status;
3615         unsigned int handled = 1;
3616
3617         /* In INTx mode, it is possible for the interrupt to arrive at
3618          * the CPU before the status block posted prior to the interrupt.
3619          * Reading the PCI State register will confirm whether the
3620          * interrupt is ours and will flush the status block.
3621          */
3622         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3623                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3624                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3625                         handled = 0;
3626                         goto out;
3627                 }
3628         }
3629
3630         /*
3631          * Writing any value to intr-mbox-0 clears PCI INTA# and
3632          * chip-internal interrupt pending events.
3633          * Writing non-zero to intr-mbox-0 additional tells the
3634          * NIC to stop sending us irqs, engaging "in-intr-handler"
3635          * event coalescing.
3636          *
3637          * Flush the mailbox to de-assert the IRQ immediately to prevent
3638          * spurious interrupts.  The flush impacts performance but
3639          * excessive spurious interrupts can be worse in some cases.
3640          */
3641         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3642         if (tg3_irq_sync(tp))
3643                 goto out;
3644         sblk->status &= ~SD_STATUS_UPDATED;
3645         if (likely(tg3_has_work(tp))) {
3646                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3647                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3648         } else {
3649                 /* No work, shared interrupt perhaps?  re-enable
3650                  * interrupts, and flush that PCI write
3651                  */
3652                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3653                                0x00000000);
3654         }
3655 out:
3656         return IRQ_RETVAL(handled);
3657 }
3658
3659 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3660 {
3661         struct net_device *dev = dev_id;
3662         struct tg3 *tp = netdev_priv(dev);
3663         struct tg3_hw_status *sblk = tp->hw_status;
3664         unsigned int handled = 1;
3665
3666         /* In INTx mode, it is possible for the interrupt to arrive at
3667          * the CPU before the status block posted prior to the interrupt.
3668          * Reading the PCI State register will confirm whether the
3669          * interrupt is ours and will flush the status block.
3670          */
3671         if (unlikely(sblk->status_tag == tp->last_tag)) {
3672                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3673                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3674                         handled = 0;
3675                         goto out;
3676                 }
3677         }
3678
3679         /*
3680          * writing any value to intr-mbox-0 clears PCI INTA# and
3681          * chip-internal interrupt pending events.
3682          * writing non-zero to intr-mbox-0 additional tells the
3683          * NIC to stop sending us irqs, engaging "in-intr-handler"
3684          * event coalescing.
3685          *
3686          * Flush the mailbox to de-assert the IRQ immediately to prevent
3687          * spurious interrupts.  The flush impacts performance but
3688          * excessive spurious interrupts can be worse in some cases.
3689          */
3690         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3691         if (tg3_irq_sync(tp))
3692                 goto out;
3693         if (netif_rx_schedule_prep(dev)) {
3694                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3695                 /* Update last_tag to mark that this status has been
3696                  * seen. Because interrupt may be shared, we may be
3697                  * racing with tg3_poll(), so only update last_tag
3698                  * if tg3_poll() is not scheduled.
3699                  */
3700                 tp->last_tag = sblk->status_tag;
3701                 __netif_rx_schedule(dev);
3702         }
3703 out:
3704         return IRQ_RETVAL(handled);
3705 }
3706
3707 /* ISR for interrupt test */
3708 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3709 {
3710         struct net_device *dev = dev_id;
3711         struct tg3 *tp = netdev_priv(dev);
3712         struct tg3_hw_status *sblk = tp->hw_status;
3713
3714         if ((sblk->status & SD_STATUS_UPDATED) ||
3715             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3716                 tg3_disable_ints(tp);
3717                 return IRQ_RETVAL(1);
3718         }
3719         return IRQ_RETVAL(0);
3720 }
3721
3722 static int tg3_init_hw(struct tg3 *, int);
3723 static int tg3_halt(struct tg3 *, int, int);
3724
3725 /* Restart hardware after configuration changes, self-test, etc.
3726  * Invoked with tp->lock held.
3727  */
3728 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3729 {
3730         int err;
3731
3732         err = tg3_init_hw(tp, reset_phy);
3733         if (err) {
3734                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3735                        "aborting.\n", tp->dev->name);
3736                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3737                 tg3_full_unlock(tp);
3738                 del_timer_sync(&tp->timer);
3739                 tp->irq_sync = 0;
3740                 netif_poll_enable(tp->dev);
3741                 dev_close(tp->dev);
3742                 tg3_full_lock(tp, 0);
3743         }
3744         return err;
3745 }
3746
3747 #ifdef CONFIG_NET_POLL_CONTROLLER
3748 static void tg3_poll_controller(struct net_device *dev)
3749 {
3750         struct tg3 *tp = netdev_priv(dev);
3751
3752         tg3_interrupt(tp->pdev->irq, dev);
3753 }
3754 #endif
3755
3756 static void tg3_reset_task(struct work_struct *work)
3757 {
3758         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3759         unsigned int restart_timer;
3760
3761         tg3_full_lock(tp, 0);
3762
3763         if (!netif_running(tp->dev)) {
3764                 tg3_full_unlock(tp);
3765                 return;
3766         }
3767
3768         tg3_full_unlock(tp);
3769
3770         tg3_netif_stop(tp);
3771
3772         tg3_full_lock(tp, 1);
3773
3774         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3775         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3776
3777         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3778                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3779                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3780                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3781                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3782         }
3783
3784         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3785         if (tg3_init_hw(tp, 1))
3786                 goto out;
3787
3788         tg3_netif_start(tp);
3789
3790         if (restart_timer)
3791                 mod_timer(&tp->timer, jiffies + 1);
3792
3793 out:
3794         tg3_full_unlock(tp);
3795 }
3796
3797 static void tg3_dump_short_state(struct tg3 *tp)
3798 {
3799         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3800                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3801         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3802                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3803 }
3804
3805 static void tg3_tx_timeout(struct net_device *dev)
3806 {
3807         struct tg3 *tp = netdev_priv(dev);
3808
3809         if (netif_msg_tx_err(tp)) {
3810                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3811                        dev->name);
3812                 tg3_dump_short_state(tp);
3813         }
3814
3815         schedule_work(&tp->reset_task);
3816 }
3817
3818 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3819 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3820 {
3821         u32 base = (u32) mapping & 0xffffffff;
3822
3823         return ((base > 0xffffdcc0) &&
3824                 (base + len + 8 < base));
3825 }
3826
3827 /* Test for DMA addresses > 40-bit */
3828 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3829                                           int len)
3830 {
3831 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3832         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3833                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3834         return 0;
3835 #else
3836         return 0;
3837 #endif
3838 }
3839
3840 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3841
3842 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3843 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3844                                        u32 last_plus_one, u32 *start,
3845                                        u32 base_flags, u32 mss)
3846 {
3847         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3848         dma_addr_t new_addr = 0;
3849         u32 entry = *start;
3850         int i, ret = 0;
3851
3852         if (!new_skb) {
3853                 ret = -1;
3854         } else {
3855                 /* New SKB is guaranteed to be linear. */
3856                 entry = *start;
3857                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3858                                           PCI_DMA_TODEVICE);
3859                 /* Make sure new skb does not cross any 4G boundaries.
3860                  * Drop the packet if it does.
3861                  */
3862                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3863                         ret = -1;
3864                         dev_kfree_skb(new_skb);
3865                         new_skb = NULL;
3866                 } else {
3867                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3868                                     base_flags, 1 | (mss << 1));
3869                         *start = NEXT_TX(entry);
3870                 }
3871         }
3872
3873         /* Now clean up the sw ring entries. */
3874         i = 0;
3875         while (entry != last_plus_one) {
3876                 int len;
3877
3878                 if (i == 0)
3879                         len = skb_headlen(skb);
3880                 else
3881                         len = skb_shinfo(skb)->frags[i-1].size;
3882                 pci_unmap_single(tp->pdev,
3883                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3884                                  len, PCI_DMA_TODEVICE);
3885                 if (i == 0) {
3886                         tp->tx_buffers[entry].skb = new_skb;
3887                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3888                 } else {
3889                         tp->tx_buffers[entry].skb = NULL;
3890                 }
3891                 entry = NEXT_TX(entry);
3892                 i++;
3893         }
3894
3895         dev_kfree_skb(skb);
3896
3897         return ret;
3898 }
3899
3900 static void tg3_set_txd(struct tg3 *tp, int entry,
3901                         dma_addr_t mapping, int len, u32 flags,
3902                         u32 mss_and_is_end)
3903 {
3904         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3905         int is_end = (mss_and_is_end & 0x1);
3906         u32 mss = (mss_and_is_end >> 1);
3907         u32 vlan_tag = 0;
3908
3909         if (is_end)
3910                 flags |= TXD_FLAG_END;
3911         if (flags & TXD_FLAG_VLAN) {
3912                 vlan_tag = flags >> 16;
3913                 flags &= 0xffff;
3914         }
3915         vlan_tag |= (mss << TXD_MSS_SHIFT);
3916
3917         txd->addr_hi = ((u64) mapping >> 32);
3918         txd->addr_lo = ((u64) mapping & 0xffffffff);
3919         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3920         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3921 }
3922
3923 /* hard_start_xmit for devices that don't have any bugs and
3924  * support TG3_FLG2_HW_TSO_2 only.
3925  */
3926 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3927 {
3928         struct tg3 *tp = netdev_priv(dev);
3929         dma_addr_t mapping;
3930         u32 len, entry, base_flags, mss;
3931
3932         len = skb_headlen(skb);
3933
3934         /* We are running in BH disabled context with netif_tx_lock
3935          * and TX reclaim runs via tp->poll inside of a software
3936          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3937          * no IRQ context deadlocks to worry about either.  Rejoice!
3938          */
3939         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3940                 if (!netif_queue_stopped(dev)) {
3941                         netif_stop_queue(dev);
3942
3943                         /* This is a hard error, log it. */
3944                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3945                                "queue awake!\n", dev->name);
3946                 }
3947                 return NETDEV_TX_BUSY;
3948         }
3949
3950         entry = tp->tx_prod;
3951         base_flags = 0;
3952         mss = 0;
3953         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3954                 int tcp_opt_len, ip_tcp_len;
3955
3956                 if (skb_header_cloned(skb) &&
3957                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3958                         dev_kfree_skb(skb);
3959                         goto out_unlock;
3960                 }
3961
3962                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3963                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3964                 else {
3965                         struct iphdr *iph = ip_hdr(skb);
3966
3967                         tcp_opt_len = tcp_optlen(skb);
3968                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3969
3970                         iph->check = 0;
3971                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3972                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3973                 }
3974
3975                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3976                                TXD_FLAG_CPU_POST_DMA);
3977
3978                 tcp_hdr(skb)->check = 0;
3979
3980         }
3981         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3982                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3983 #if TG3_VLAN_TAG_USED
3984         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3985                 base_flags |= (TXD_FLAG_VLAN |
3986                                (vlan_tx_tag_get(skb) << 16));
3987 #endif
3988
3989         /* Queue skb data, a.k.a. the main skb fragment. */
3990         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3991
3992         tp->tx_buffers[entry].skb = skb;
3993         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3994
3995         tg3_set_txd(tp, entry, mapping, len, base_flags,
3996                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3997
3998         entry = NEXT_TX(entry);
3999
4000         /* Now loop through additional data fragments, and queue them. */
4001         if (skb_shinfo(skb)->nr_frags > 0) {
4002                 unsigned int i, last;
4003
4004                 last = skb_shinfo(skb)->nr_frags - 1;
4005                 for (i = 0; i <= last; i++) {
4006                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4007
4008                         len = frag->size;
4009                         mapping = pci_map_page(tp->pdev,
4010                                                frag->page,
4011                                                frag->page_offset,
4012                                                len, PCI_DMA_TODEVICE);
4013
4014                         tp->tx_buffers[entry].skb = NULL;
4015                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4016
4017                         tg3_set_txd(tp, entry, mapping, len,
4018                                     base_flags, (i == last) | (mss << 1));
4019
4020                         entry = NEXT_TX(entry);
4021                 }
4022         }
4023
4024         /* Packets are ready, update Tx producer idx local and on card. */
4025         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4026
4027         tp->tx_prod = entry;
4028         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4029                 netif_stop_queue(dev);
4030                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4031                         netif_wake_queue(tp->dev);
4032         }
4033
4034 out_unlock:
4035         mmiowb();
4036
4037         dev->trans_start = jiffies;
4038
4039         return NETDEV_TX_OK;
4040 }
4041
4042 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4043
4044 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4045  * TSO header is greater than 80 bytes.
4046  */
4047 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4048 {
4049         struct sk_buff *segs, *nskb;
4050
4051         /* Estimate the number of fragments in the worst case */
4052         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4053                 netif_stop_queue(tp->dev);
4054                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4055                         return NETDEV_TX_BUSY;
4056
4057                 netif_wake_queue(tp->dev);
4058         }
4059
4060         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4061         if (unlikely(IS_ERR(segs)))
4062                 goto tg3_tso_bug_end;
4063
4064         do {
4065                 nskb = segs;
4066                 segs = segs->next;
4067                 nskb->next = NULL;
4068                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4069         } while (segs);
4070
4071 tg3_tso_bug_end:
4072         dev_kfree_skb(skb);
4073
4074         return NETDEV_TX_OK;
4075 }
4076
4077 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4078  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4079  */
4080 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4081 {
4082         struct tg3 *tp = netdev_priv(dev);
4083         dma_addr_t mapping;
4084         u32 len, entry, base_flags, mss;
4085         int would_hit_hwbug;
4086
4087         len = skb_headlen(skb);
4088
4089         /* We are running in BH disabled context with netif_tx_lock
4090          * and TX reclaim runs via tp->poll inside of a software
4091          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4092          * no IRQ context deadlocks to worry about either.  Rejoice!
4093          */
4094         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4095                 if (!netif_queue_stopped(dev)) {
4096                         netif_stop_queue(dev);
4097
4098                         /* This is a hard error, log it. */
4099                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4100                                "queue awake!\n", dev->name);
4101                 }
4102                 return NETDEV_TX_BUSY;
4103         }
4104
4105         entry = tp->tx_prod;
4106         base_flags = 0;
4107         if (skb->ip_summed == CHECKSUM_PARTIAL)
4108                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4109         mss = 0;
4110         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4111                 struct iphdr *iph;
4112                 int tcp_opt_len, ip_tcp_len, hdr_len;
4113
4114                 if (skb_header_cloned(skb) &&
4115                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4116                         dev_kfree_skb(skb);
4117                         goto out_unlock;
4118                 }
4119
4120                 tcp_opt_len = tcp_optlen(skb);
4121                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4122
4123                 hdr_len = ip_tcp_len + tcp_opt_len;
4124                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4125                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4126                         return (tg3_tso_bug(tp, skb));
4127
4128                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4129                                TXD_FLAG_CPU_POST_DMA);
4130
4131                 iph = ip_hdr(skb);
4132                 iph->check = 0;
4133                 iph->tot_len = htons(mss + hdr_len);
4134                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4135                         tcp_hdr(skb)->check = 0;
4136                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4137                 } else
4138                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4139                                                                  iph->daddr, 0,
4140                                                                  IPPROTO_TCP,
4141                                                                  0);
4142
4143                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4144                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4145                         if (tcp_opt_len || iph->ihl > 5) {
4146                                 int tsflags;
4147
4148                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4149                                 mss |= (tsflags << 11);
4150                         }
4151                 } else {
4152                         if (tcp_opt_len || iph->ihl > 5) {
4153                                 int tsflags;
4154
4155                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4156                                 base_flags |= tsflags << 12;
4157                         }
4158                 }
4159         }
4160 #if TG3_VLAN_TAG_USED
4161         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4162                 base_flags |= (TXD_FLAG_VLAN |
4163                                (vlan_tx_tag_get(skb) << 16));
4164 #endif
4165
4166         /* Queue skb data, a.k.a. the main skb fragment. */
4167         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4168
4169         tp->tx_buffers[entry].skb = skb;
4170         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4171
4172         would_hit_hwbug = 0;
4173
4174         if (tg3_4g_overflow_test(mapping, len))
4175                 would_hit_hwbug = 1;
4176
4177         tg3_set_txd(tp, entry, mapping, len, base_flags,
4178                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4179
4180         entry = NEXT_TX(entry);
4181
4182         /* Now loop through additional data fragments, and queue them. */
4183         if (skb_shinfo(skb)->nr_frags > 0) {
4184                 unsigned int i, last;
4185
4186                 last = skb_shinfo(skb)->nr_frags - 1;
4187                 for (i = 0; i <= last; i++) {
4188                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4189
4190                         len = frag->size;
4191                         mapping = pci_map_page(tp->pdev,
4192                                                frag->page,
4193                                                frag->page_offset,
4194                                                len, PCI_DMA_TODEVICE);
4195
4196                         tp->tx_buffers[entry].skb = NULL;
4197                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4198
4199                         if (tg3_4g_overflow_test(mapping, len))
4200                                 would_hit_hwbug = 1;
4201
4202                         if (tg3_40bit_overflow_test(tp, mapping, len))
4203                                 would_hit_hwbug = 1;
4204
4205                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4206                                 tg3_set_txd(tp, entry, mapping, len,
4207                                             base_flags, (i == last)|(mss << 1));
4208                         else
4209                                 tg3_set_txd(tp, entry, mapping, len,
4210                                             base_flags, (i == last));
4211
4212                         entry = NEXT_TX(entry);
4213                 }
4214         }
4215
4216         if (would_hit_hwbug) {
4217                 u32 last_plus_one = entry;
4218                 u32 start;
4219
4220                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4221                 start &= (TG3_TX_RING_SIZE - 1);
4222
4223                 /* If the workaround fails due to memory/mapping
4224                  * failure, silently drop this packet.
4225                  */
4226                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4227                                                 &start, base_flags, mss))
4228                         goto out_unlock;
4229
4230                 entry = start;
4231         }
4232
4233         /* Packets are ready, update Tx producer idx local and on card. */
4234         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4235
4236         tp->tx_prod = entry;
4237         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4238                 netif_stop_queue(dev);
4239                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4240                         netif_wake_queue(tp->dev);
4241         }
4242
4243 out_unlock:
4244         mmiowb();
4245
4246         dev->trans_start = jiffies;
4247
4248         return NETDEV_TX_OK;
4249 }
4250
4251 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4252                                int new_mtu)
4253 {
4254         dev->mtu = new_mtu;
4255
4256         if (new_mtu > ETH_DATA_LEN) {
4257                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4258                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4259                         ethtool_op_set_tso(dev, 0);
4260                 }
4261                 else
4262                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4263         } else {
4264                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4265                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4266                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4267         }
4268 }
4269
4270 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4271 {
4272         struct tg3 *tp = netdev_priv(dev);
4273         int err;
4274
4275         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4276                 return -EINVAL;
4277
4278         if (!netif_running(dev)) {
4279                 /* We'll just catch it later when the
4280                  * device is up'd.
4281                  */
4282                 tg3_set_mtu(dev, tp, new_mtu);
4283                 return 0;
4284         }
4285
4286         tg3_netif_stop(tp);
4287
4288         tg3_full_lock(tp, 1);
4289
4290         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4291
4292         tg3_set_mtu(dev, tp, new_mtu);
4293
4294         err = tg3_restart_hw(tp, 0);
4295
4296         if (!err)
4297                 tg3_netif_start(tp);
4298
4299         tg3_full_unlock(tp);
4300
4301         return err;
4302 }
4303
4304 /* Free up pending packets in all rx/tx rings.
4305  *
4306  * The chip has been shut down and the driver detached from
4307  * the networking, so no interrupts or new tx packets will
4308  * end up in the driver.  tp->{tx,}lock is not held and we are not
4309  * in an interrupt context and thus may sleep.
4310  */
4311 static void tg3_free_rings(struct tg3 *tp)
4312 {
4313         struct ring_info *rxp;
4314         int i;
4315
4316         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4317                 rxp = &tp->rx_std_buffers[i];
4318
4319                 if (rxp->skb == NULL)
4320                         continue;
4321                 pci_unmap_single(tp->pdev,
4322                                  pci_unmap_addr(rxp, mapping),
4323                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4324                                  PCI_DMA_FROMDEVICE);
4325                 dev_kfree_skb_any(rxp->skb);
4326                 rxp->skb = NULL;
4327         }
4328
4329         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4330                 rxp = &tp->rx_jumbo_buffers[i];
4331
4332                 if (rxp->skb == NULL)
4333                         continue;
4334                 pci_unmap_single(tp->pdev,
4335                                  pci_unmap_addr(rxp, mapping),
4336                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4337                                  PCI_DMA_FROMDEVICE);
4338                 dev_kfree_skb_any(rxp->skb);
4339                 rxp->skb = NULL;
4340         }
4341
4342         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4343                 struct tx_ring_info *txp;
4344                 struct sk_buff *skb;
4345                 int j;
4346
4347                 txp = &tp->tx_buffers[i];
4348                 skb = txp->skb;
4349
4350                 if (skb == NULL) {
4351                         i++;
4352                         continue;
4353                 }
4354
4355                 pci_unmap_single(tp->pdev,
4356                                  pci_unmap_addr(txp, mapping),
4357                                  skb_headlen(skb),
4358                                  PCI_DMA_TODEVICE);
4359                 txp->skb = NULL;
4360
4361                 i++;
4362
4363                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4364                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4365                         pci_unmap_page(tp->pdev,
4366                                        pci_unmap_addr(txp, mapping),
4367                                        skb_shinfo(skb)->frags[j].size,
4368                                        PCI_DMA_TODEVICE);
4369                         i++;
4370                 }
4371
4372                 dev_kfree_skb_any(skb);
4373         }
4374 }
4375
4376 /* Initialize tx/rx rings for packet processing.
4377  *
4378  * The chip has been shut down and the driver detached from
4379  * the networking, so no interrupts or new tx packets will
4380  * end up in the driver.  tp->{tx,}lock are held and thus
4381  * we may not sleep.
4382  */
4383 static int tg3_init_rings(struct tg3 *tp)
4384 {
4385         u32 i;
4386
4387         /* Free up all the SKBs. */
4388         tg3_free_rings(tp);
4389
4390         /* Zero out all descriptors. */
4391         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4392         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4393         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4394         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4395
4396         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4397         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4398             (tp->dev->mtu > ETH_DATA_LEN))
4399                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4400
4401         /* Initialize invariants of the rings, we only set this
4402          * stuff once.  This works because the card does not
4403          * write into the rx buffer posting rings.
4404          */
4405         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4406                 struct tg3_rx_buffer_desc *rxd;
4407
4408                 rxd = &tp->rx_std[i];
4409                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4410                         << RXD_LEN_SHIFT;
4411                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4412                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4413                                (i << RXD_OPAQUE_INDEX_SHIFT));
4414         }
4415
4416         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4417                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4418                         struct tg3_rx_buffer_desc *rxd;
4419
4420                         rxd = &tp->rx_jumbo[i];
4421                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4422                                 << RXD_LEN_SHIFT;
4423                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4424                                 RXD_FLAG_JUMBO;
4425                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4426                                (i << RXD_OPAQUE_INDEX_SHIFT));
4427                 }
4428         }
4429
4430         /* Now allocate fresh SKBs for each rx ring. */
4431         for (i = 0; i < tp->rx_pending; i++) {
4432                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4433                         printk(KERN_WARNING PFX
4434                                "%s: Using a smaller RX standard ring, "
4435                                "only %d out of %d buffers were allocated "
4436                                "successfully.\n",
4437                                tp->dev->name, i, tp->rx_pending);
4438                         if (i == 0)
4439                                 return -ENOMEM;
4440                         tp->rx_pending = i;
4441                         break;
4442                 }
4443         }
4444
4445         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4446                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4447                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4448                                              -1, i) < 0) {
4449                                 printk(KERN_WARNING PFX
4450                                        "%s: Using a smaller RX jumbo ring, "
4451                                        "only %d out of %d buffers were "
4452                                        "allocated successfully.\n",
4453                                        tp->dev->name, i, tp->rx_jumbo_pending);
4454                                 if (i == 0) {
4455                                         tg3_free_rings(tp);
4456                                         return -ENOMEM;
4457                                 }
4458                                 tp->rx_jumbo_pending = i;
4459                                 break;
4460                         }
4461                 }
4462         }
4463         return 0;
4464 }
4465
4466 /*
4467  * Must not be invoked with interrupt sources disabled and
4468  * the hardware shutdown down.
4469  */
4470 static void tg3_free_consistent(struct tg3 *tp)
4471 {
4472         kfree(tp->rx_std_buffers);
4473         tp->rx_std_buffers = NULL;
4474         if (tp->rx_std) {
4475                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4476                                     tp->rx_std, tp->rx_std_mapping);
4477                 tp->rx_std = NULL;
4478         }
4479         if (tp->rx_jumbo) {
4480                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4481                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4482                 tp->rx_jumbo = NULL;
4483         }
4484         if (tp->rx_rcb) {
4485                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4486                                     tp->rx_rcb, tp->rx_rcb_mapping);
4487                 tp->rx_rcb = NULL;
4488         }
4489         if (tp->tx_ring) {
4490                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4491                         tp->tx_ring, tp->tx_desc_mapping);
4492                 tp->tx_ring = NULL;
4493         }
4494         if (tp->hw_status) {
4495                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4496                                     tp->hw_status, tp->status_mapping);
4497                 tp->hw_status = NULL;
4498         }
4499         if (tp->hw_stats) {
4500                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4501                                     tp->hw_stats, tp->stats_mapping);
4502                 tp->hw_stats = NULL;
4503         }
4504 }
4505
4506 /*
4507  * Must not be invoked with interrupt sources disabled and
4508  * the hardware shutdown down.  Can sleep.
4509  */
4510 static int tg3_alloc_consistent(struct tg3 *tp)
4511 {
4512         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4513                                       (TG3_RX_RING_SIZE +
4514                                        TG3_RX_JUMBO_RING_SIZE)) +
4515                                      (sizeof(struct tx_ring_info) *
4516                                       TG3_TX_RING_SIZE),
4517                                      GFP_KERNEL);
4518         if (!tp->rx_std_buffers)
4519                 return -ENOMEM;
4520
4521         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4522         tp->tx_buffers = (struct tx_ring_info *)
4523                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4524
4525         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4526                                           &tp->rx_std_mapping);
4527         if (!tp->rx_std)
4528                 goto err_out;
4529
4530         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4531                                             &tp->rx_jumbo_mapping);
4532
4533         if (!tp->rx_jumbo)
4534                 goto err_out;
4535
4536         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4537                                           &tp->rx_rcb_mapping);
4538         if (!tp->rx_rcb)
4539                 goto err_out;
4540
4541         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4542                                            &tp->tx_desc_mapping);
4543         if (!tp->tx_ring)
4544                 goto err_out;
4545
4546         tp->hw_status = pci_alloc_consistent(tp->pdev,
4547                                              TG3_HW_STATUS_SIZE,
4548                                              &tp->status_mapping);
4549         if (!tp->hw_status)
4550                 goto err_out;
4551
4552         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4553                                             sizeof(struct tg3_hw_stats),
4554                                             &tp->stats_mapping);
4555         if (!tp->hw_stats)
4556                 goto err_out;
4557
4558         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4559         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4560
4561         return 0;
4562
4563 err_out:
4564         tg3_free_consistent(tp);
4565         return -ENOMEM;
4566 }
4567
4568 #define MAX_WAIT_CNT 1000
4569
4570 /* To stop a block, clear the enable bit and poll till it
4571  * clears.  tp->lock is held.
4572  */
4573 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4574 {
4575         unsigned int i;
4576         u32 val;
4577
4578         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4579                 switch (ofs) {
4580                 case RCVLSC_MODE:
4581                 case DMAC_MODE:
4582                 case MBFREE_MODE:
4583                 case BUFMGR_MODE:
4584                 case MEMARB_MODE:
4585                         /* We can't enable/disable these bits of the
4586                          * 5705/5750, just say success.
4587                          */
4588                         return 0;
4589
4590                 default:
4591                         break;
4592                 };
4593         }
4594
4595         val = tr32(ofs);
4596         val &= ~enable_bit;
4597         tw32_f(ofs, val);
4598
4599         for (i = 0; i < MAX_WAIT_CNT; i++) {
4600                 udelay(100);
4601                 val = tr32(ofs);
4602                 if ((val & enable_bit) == 0)
4603                         break;
4604         }
4605
4606         if (i == MAX_WAIT_CNT && !silent) {
4607                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4608                        "ofs=%lx enable_bit=%x\n",
4609                        ofs, enable_bit);
4610                 return -ENODEV;
4611         }
4612
4613         return 0;
4614 }
4615
4616 /* tp->lock is held. */
4617 static int tg3_abort_hw(struct tg3 *tp, int silent)
4618 {
4619         int i, err;
4620
4621         tg3_disable_ints(tp);
4622
4623         tp->rx_mode &= ~RX_MODE_ENABLE;
4624         tw32_f(MAC_RX_MODE, tp->rx_mode);
4625         udelay(10);
4626
4627         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4628         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4629         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4630         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4631         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4632         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4633
4634         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4635         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4636         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4637         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4638         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4639         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4640         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4641
4642         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4643         tw32_f(MAC_MODE, tp->mac_mode);
4644         udelay(40);
4645
4646         tp->tx_mode &= ~TX_MODE_ENABLE;
4647         tw32_f(MAC_TX_MODE, tp->tx_mode);
4648
4649         for (i = 0; i < MAX_WAIT_CNT; i++) {
4650                 udelay(100);
4651                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4652                         break;
4653         }
4654         if (i >= MAX_WAIT_CNT) {
4655                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4656                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4657                        tp->dev->name, tr32(MAC_TX_MODE));
4658                 err |= -ENODEV;
4659         }
4660
4661         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4662         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4663         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4664
4665         tw32(FTQ_RESET, 0xffffffff);
4666         tw32(FTQ_RESET, 0x00000000);
4667
4668         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4669         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4670
4671         if (tp->hw_status)
4672                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4673         if (tp->hw_stats)
4674                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4675
4676         return err;
4677 }
4678
4679 /* tp->lock is held. */
4680 static int tg3_nvram_lock(struct tg3 *tp)
4681 {
4682         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4683                 int i;
4684
4685                 if (tp->nvram_lock_cnt == 0) {
4686                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4687                         for (i = 0; i < 8000; i++) {
4688                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4689                                         break;
4690                                 udelay(20);
4691                         }
4692                         if (i == 8000) {
4693                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4694                                 return -ENODEV;
4695                         }
4696                 }
4697                 tp->nvram_lock_cnt++;
4698         }
4699         return 0;
4700 }
4701
4702 /* tp->lock is held. */
4703 static void tg3_nvram_unlock(struct tg3 *tp)
4704 {
4705         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4706                 if (tp->nvram_lock_cnt > 0)
4707                         tp->nvram_lock_cnt--;
4708                 if (tp->nvram_lock_cnt == 0)
4709                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4710         }
4711 }
4712
4713 /* tp->lock is held. */
4714 static void tg3_enable_nvram_access(struct tg3 *tp)
4715 {
4716         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4717             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4718                 u32 nvaccess = tr32(NVRAM_ACCESS);
4719
4720                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4721         }
4722 }
4723
4724 /* tp->lock is held. */
4725 static void tg3_disable_nvram_access(struct tg3 *tp)
4726 {
4727         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4728             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4729                 u32 nvaccess = tr32(NVRAM_ACCESS);
4730
4731                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4732         }
4733 }
4734
4735 /* tp->lock is held. */
4736 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4737 {
4738         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4739                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4740
4741         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4742                 switch (kind) {
4743                 case RESET_KIND_INIT:
4744                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4745                                       DRV_STATE_START);
4746                         break;
4747
4748                 case RESET_KIND_SHUTDOWN:
4749                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4750                                       DRV_STATE_UNLOAD);
4751                         break;
4752
4753                 case RESET_KIND_SUSPEND:
4754                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4755                                       DRV_STATE_SUSPEND);
4756                         break;
4757
4758                 default:
4759                         break;
4760                 };
4761         }
4762 }
4763
4764 /* tp->lock is held. */
4765 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4766 {
4767         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4768                 switch (kind) {
4769                 case RESET_KIND_INIT:
4770                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4771                                       DRV_STATE_START_DONE);
4772                         break;
4773
4774                 case RESET_KIND_SHUTDOWN:
4775                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4776                                       DRV_STATE_UNLOAD_DONE);
4777                         break;
4778
4779                 default:
4780                         break;
4781                 };
4782         }
4783 }
4784
4785 /* tp->lock is held. */
4786 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4787 {
4788         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4789                 switch (kind) {
4790                 case RESET_KIND_INIT:
4791                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4792                                       DRV_STATE_START);
4793                         break;
4794
4795                 case RESET_KIND_SHUTDOWN:
4796                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4797                                       DRV_STATE_UNLOAD);
4798                         break;
4799
4800                 case RESET_KIND_SUSPEND:
4801                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4802                                       DRV_STATE_SUSPEND);
4803                         break;
4804
4805                 default:
4806                         break;
4807                 };
4808         }
4809 }
4810
4811 static int tg3_poll_fw(struct tg3 *tp)
4812 {
4813         int i;
4814         u32 val;
4815
4816         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4817                 /* Wait up to 20ms for init done. */
4818                 for (i = 0; i < 200; i++) {
4819                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4820                                 return 0;
4821                         udelay(100);
4822                 }
4823                 return -ENODEV;
4824         }
4825
4826         /* Wait for firmware initialization to complete. */
4827         for (i = 0; i < 100000; i++) {
4828                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4829                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4830                         break;
4831                 udelay(10);
4832         }
4833
4834         /* Chip might not be fitted with firmware.  Some Sun onboard
4835          * parts are configured like that.  So don't signal the timeout
4836          * of the above loop as an error, but do report the lack of
4837          * running firmware once.
4838          */
4839         if (i >= 100000 &&
4840             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4841                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4842
4843                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4844                        tp->dev->name);
4845         }
4846
4847         return 0;
4848 }
4849
4850 /* Save PCI command register before chip reset */
4851 static void tg3_save_pci_state(struct tg3 *tp)
4852 {
4853         u32 val;
4854
4855         pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
4856         tp->pci_cmd = val;
4857 }
4858
4859 /* Restore PCI state after chip reset */
4860 static void tg3_restore_pci_state(struct tg3 *tp)
4861 {
4862         u32 val;
4863
4864         /* Re-enable indirect register accesses. */
4865         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4866                                tp->misc_host_ctrl);
4867
4868         /* Set MAX PCI retry to zero. */
4869         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4870         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4871             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4872                 val |= PCISTATE_RETRY_SAME_DMA;
4873         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4874
4875         pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
4876
4877         /* Make sure PCI-X relaxed ordering bit is clear. */
4878         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4879         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4880         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4881
4882         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4883                 u32 val;
4884
4885                 /* Chip reset on 5780 will reset MSI enable bit,
4886                  * so need to restore it.
4887                  */
4888                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4889                         u16 ctrl;
4890
4891                         pci_read_config_word(tp->pdev,
4892                                              tp->msi_cap + PCI_MSI_FLAGS,
4893                                              &ctrl);
4894                         pci_write_config_word(tp->pdev,
4895                                               tp->msi_cap + PCI_MSI_FLAGS,
4896                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4897                         val = tr32(MSGINT_MODE);
4898                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4899                 }
4900         }
4901 }
4902
4903 static void tg3_stop_fw(struct tg3 *);
4904
4905 /* tp->lock is held. */
4906 static int tg3_chip_reset(struct tg3 *tp)
4907 {
4908         u32 val;
4909         void (*write_op)(struct tg3 *, u32, u32);
4910         int err;
4911
4912         tg3_nvram_lock(tp);
4913
4914         /* No matching tg3_nvram_unlock() after this because
4915          * chip reset below will undo the nvram lock.
4916          */
4917         tp->nvram_lock_cnt = 0;
4918
4919         /* GRC_MISC_CFG core clock reset will clear the memory
4920          * enable bit in PCI register 4 and the MSI enable bit
4921          * on some chips, so we save relevant registers here.
4922          */
4923         tg3_save_pci_state(tp);
4924
4925         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4926             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4927             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4928                 tw32(GRC_FASTBOOT_PC, 0);
4929
4930         /*
4931          * We must avoid the readl() that normally takes place.
4932          * It locks machines, causes machine checks, and other
4933          * fun things.  So, temporarily disable the 5701
4934          * hardware workaround, while we do the reset.
4935          */
4936         write_op = tp->write32;
4937         if (write_op == tg3_write_flush_reg32)
4938                 tp->write32 = tg3_write32;
4939
4940         /* Prevent the irq handler from reading or writing PCI registers
4941          * during chip reset when the memory enable bit in the PCI command
4942          * register may be cleared.  The chip does not generate interrupt
4943          * at this time, but the irq handler may still be called due to irq
4944          * sharing or irqpoll.
4945          */
4946         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4947         if (tp->hw_status) {
4948                 tp->hw_status->status = 0;
4949                 tp->hw_status->status_tag = 0;
4950         }
4951         tp->last_tag = 0;
4952         smp_mb();
4953         synchronize_irq(tp->pdev->irq);
4954
4955         /* do the reset */
4956         val = GRC_MISC_CFG_CORECLK_RESET;
4957
4958         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4959                 if (tr32(0x7e2c) == 0x60) {
4960                         tw32(0x7e2c, 0x20);
4961                 }
4962                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4963                         tw32(GRC_MISC_CFG, (1 << 29));
4964                         val |= (1 << 29);
4965                 }
4966         }
4967
4968         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4969                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4970                 tw32(GRC_VCPU_EXT_CTRL,
4971                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4972         }
4973
4974         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4975                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4976         tw32(GRC_MISC_CFG, val);
4977
4978         /* restore 5701 hardware bug workaround write method */
4979         tp->write32 = write_op;
4980
4981         /* Unfortunately, we have to delay before the PCI read back.
4982          * Some 575X chips even will not respond to a PCI cfg access
4983          * when the reset command is given to the chip.
4984          *
4985          * How do these hardware designers expect things to work
4986          * properly if the PCI write is posted for a long period
4987          * of time?  It is always necessary to have some method by
4988          * which a register read back can occur to push the write
4989          * out which does the reset.
4990          *
4991          * For most tg3 variants the trick below was working.
4992          * Ho hum...
4993          */
4994         udelay(120);
4995
4996         /* Flush PCI posted writes.  The normal MMIO registers
4997          * are inaccessible at this time so this is the only
4998          * way to make this reliably (actually, this is no longer
4999          * the case, see above).  I tried to use indirect
5000          * register read/write but this upset some 5701 variants.
5001          */
5002         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5003
5004         udelay(120);
5005
5006         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5007                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5008                         int i;
5009                         u32 cfg_val;
5010
5011                         /* Wait for link training to complete.  */
5012                         for (i = 0; i < 5000; i++)
5013                                 udelay(100);
5014
5015                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5016                         pci_write_config_dword(tp->pdev, 0xc4,
5017                                                cfg_val | (1 << 15));
5018                 }
5019                 /* Set PCIE max payload size and clear error status.  */
5020                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5021         }
5022
5023         tg3_restore_pci_state(tp);
5024
5025         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5026
5027         val = 0;
5028         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5029                 val = tr32(MEMARB_MODE);
5030         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5031
5032         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5033                 tg3_stop_fw(tp);
5034                 tw32(0x5000, 0x400);
5035         }
5036
5037         tw32(GRC_MODE, tp->grc_mode);
5038
5039         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5040                 u32 val = tr32(0xc4);
5041
5042                 tw32(0xc4, val | (1 << 15));
5043         }
5044
5045         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5046             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5047                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5048                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5049                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5050                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5051         }
5052
5053         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5054                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5055                 tw32_f(MAC_MODE, tp->mac_mode);
5056         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5057                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5058                 tw32_f(MAC_MODE, tp->mac_mode);
5059         } else
5060                 tw32_f(MAC_MODE, 0);
5061         udelay(40);
5062
5063         err = tg3_poll_fw(tp);
5064         if (err)
5065                 return err;
5066
5067         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5068             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5069                 u32 val = tr32(0x7c00);
5070
5071                 tw32(0x7c00, val | (1 << 25));
5072         }
5073
5074         /* Reprobe ASF enable state.  */
5075         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5076         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5077         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5078         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5079                 u32 nic_cfg;
5080
5081                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5082                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5083                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5084                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5085                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5086                 }
5087         }
5088
5089         return 0;
5090 }
5091
5092 /* tp->lock is held. */
5093 static void tg3_stop_fw(struct tg3 *tp)
5094 {
5095         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5096                 u32 val;
5097                 int i;
5098
5099                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5100                 val = tr32(GRC_RX_CPU_EVENT);
5101                 val |= (1 << 14);
5102                 tw32(GRC_RX_CPU_EVENT, val);
5103
5104                 /* Wait for RX cpu to ACK the event.  */
5105                 for (i = 0; i < 100; i++) {
5106                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5107                                 break;
5108                         udelay(1);
5109                 }
5110         }
5111 }
5112
5113 /* tp->lock is held. */
5114 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5115 {
5116         int err;
5117
5118         tg3_stop_fw(tp);
5119
5120         tg3_write_sig_pre_reset(tp, kind);
5121
5122         tg3_abort_hw(tp, silent);
5123         err = tg3_chip_reset(tp);
5124
5125         tg3_write_sig_legacy(tp, kind);
5126         tg3_write_sig_post_reset(tp, kind);
5127
5128         if (err)
5129                 return err;
5130
5131         return 0;
5132 }
5133
5134 #define TG3_FW_RELEASE_MAJOR    0x0
5135 #define TG3_FW_RELASE_MINOR     0x0
5136 #define TG3_FW_RELEASE_FIX      0x0
5137 #define TG3_FW_START_ADDR       0x08000000
5138 #define TG3_FW_TEXT_ADDR        0x08000000
5139 #define TG3_FW_TEXT_LEN         0x9c0
5140 #define TG3_FW_RODATA_ADDR      0x080009c0
5141 #define TG3_FW_RODATA_LEN       0x60
5142 #define TG3_FW_DATA_ADDR        0x08000a40
5143 #define TG3_FW_DATA_LEN         0x20
5144 #define TG3_FW_SBSS_ADDR        0x08000a60
5145 #define TG3_FW_SBSS_LEN         0xc
5146 #define TG3_FW_BSS_ADDR         0x08000a70
5147 #define TG3_FW_BSS_LEN          0x10
5148
5149 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5150         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5151         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5152         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5153         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5154         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5155         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5156         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5157         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5158         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5159         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5160         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5161         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5162         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5163         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5164         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5165         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5166         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5167         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5168         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5169         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5170         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5171         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5172         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5173         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5174         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5175         0, 0, 0, 0, 0, 0,
5176         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5177         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5178         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5179         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5180         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5181         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5182         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5183         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5184         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5185         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5186         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5187         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5188         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5189         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5190         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5191         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5192         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5193         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5194         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5195         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5196         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5197         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5198         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5199         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5200         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5201         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5202         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5203         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5204         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5205         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5206         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5207         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5208         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5209         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5210         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5211         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5212         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5213         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5214         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5215         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5216         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5217         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5218         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5219         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5220         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5221         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5222         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5223         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5224         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5225         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5226         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5227         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5228         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5229         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5230         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5231         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5232         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5233         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5234         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5235         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5236         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5237         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5238         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5239         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5240         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5241 };
5242
5243 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5244         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5245         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5246         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5247         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5248         0x00000000
5249 };
5250
5251 #if 0 /* All zeros, don't eat up space with it. */
5252 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5253         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5254         0x00000000, 0x00000000, 0x00000000, 0x00000000
5255 };
5256 #endif
5257
5258 #define RX_CPU_SCRATCH_BASE     0x30000
5259 #define RX_CPU_SCRATCH_SIZE     0x04000
5260 #define TX_CPU_SCRATCH_BASE     0x34000
5261 #define TX_CPU_SCRATCH_SIZE     0x04000
5262
5263 /* tp->lock is held. */
5264 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5265 {
5266         int i;
5267
5268         BUG_ON(offset == TX_CPU_BASE &&
5269             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5270
5271         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5272                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5273
5274                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5275                 return 0;
5276         }
5277         if (offset == RX_CPU_BASE) {
5278                 for (i = 0; i < 10000; i++) {
5279                         tw32(offset + CPU_STATE, 0xffffffff);
5280                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5281                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5282                                 break;
5283                 }
5284
5285                 tw32(offset + CPU_STATE, 0xffffffff);
5286                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5287                 udelay(10);
5288         } else {
5289                 for (i = 0; i < 10000; i++) {
5290                         tw32(offset + CPU_STATE, 0xffffffff);
5291                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5292                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5293                                 break;
5294                 }
5295         }
5296
5297         if (i >= 10000) {
5298                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5299                        "and %s CPU\n",
5300                        tp->dev->name,
5301                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5302                 return -ENODEV;
5303         }
5304
5305         /* Clear firmware's nvram arbitration. */
5306         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5307                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5308         return 0;
5309 }
5310
5311 struct fw_info {
5312         unsigned int text_base;
5313         unsigned int text_len;
5314         const u32 *text_data;
5315         unsigned int rodata_base;
5316         unsigned int rodata_len;
5317         const u32 *rodata_data;
5318         unsigned int data_base;
5319         unsigned int data_len;
5320         const u32 *data_data;
5321 };
5322
5323 /* tp->lock is held. */
5324 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5325                                  int cpu_scratch_size, struct fw_info *info)
5326 {
5327         int err, lock_err, i;
5328         void (*write_op)(struct tg3 *, u32, u32);
5329
5330         if (cpu_base == TX_CPU_BASE &&
5331             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5332                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5333                        "TX cpu firmware on %s which is 5705.\n",
5334                        tp->dev->name);
5335                 return -EINVAL;
5336         }
5337
5338         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5339                 write_op = tg3_write_mem;
5340         else
5341                 write_op = tg3_write_indirect_reg32;
5342
5343         /* It is possible that bootcode is still loading at this point.
5344          * Get the nvram lock first before halting the cpu.
5345          */
5346         lock_err = tg3_nvram_lock(tp);
5347         err = tg3_halt_cpu(tp, cpu_base);
5348         if (!lock_err)
5349                 tg3_nvram_unlock(tp);
5350         if (err)
5351                 goto out;
5352
5353         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5354                 write_op(tp, cpu_scratch_base + i, 0);
5355         tw32(cpu_base + CPU_STATE, 0xffffffff);
5356         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5357         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5358                 write_op(tp, (cpu_scratch_base +
5359                               (info->text_base & 0xffff) +
5360                               (i * sizeof(u32))),
5361                          (info->text_data ?
5362                           info->text_data[i] : 0));
5363         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5364                 write_op(tp, (cpu_scratch_base +
5365                               (info->rodata_base & 0xffff) +
5366                               (i * sizeof(u32))),
5367                          (info->rodata_data ?
5368                           info->rodata_data[i] : 0));
5369         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5370                 write_op(tp, (cpu_scratch_base +
5371                               (info->data_base & 0xffff) +
5372                               (i * sizeof(u32))),
5373                          (info->data_data ?
5374                           info->data_data[i] : 0));
5375
5376         err = 0;
5377
5378 out:
5379         return err;
5380 }
5381
5382 /* tp->lock is held. */
5383 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5384 {
5385         struct fw_info info;
5386         int err, i;
5387
5388         info.text_base = TG3_FW_TEXT_ADDR;
5389         info.text_len = TG3_FW_TEXT_LEN;
5390         info.text_data = &tg3FwText[0];
5391         info.rodata_base = TG3_FW_RODATA_ADDR;
5392         info.rodata_len = TG3_FW_RODATA_LEN;
5393         info.rodata_data = &tg3FwRodata[0];
5394         info.data_base = TG3_FW_DATA_ADDR;
5395         info.data_len = TG3_FW_DATA_LEN;
5396         info.data_data = NULL;
5397
5398         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5399                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5400                                     &info);
5401         if (err)
5402                 return err;
5403
5404         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5405                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5406                                     &info);
5407         if (err)
5408                 return err;
5409
5410         /* Now startup only the RX cpu. */
5411         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5412         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5413
5414         for (i = 0; i < 5; i++) {
5415                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5416                         break;
5417                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5418                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5419                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5420                 udelay(1000);
5421         }
5422         if (i >= 5) {
5423                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5424                        "to set RX CPU PC, is %08x should be %08x\n",
5425                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5426                        TG3_FW_TEXT_ADDR);
5427                 return -ENODEV;
5428         }
5429         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5430         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5431
5432         return 0;
5433 }
5434
5435
5436 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5437 #define TG3_TSO_FW_RELASE_MINOR         0x6
5438 #define TG3_TSO_FW_RELEASE_FIX          0x0
5439 #define TG3_TSO_FW_START_ADDR           0x08000000
5440 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5441 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5442 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5443 #define TG3_TSO_FW_RODATA_LEN           0x60
5444 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5445 #define TG3_TSO_FW_DATA_LEN             0x30
5446 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5447 #define TG3_TSO_FW_SBSS_LEN             0x2c
5448 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5449 #define TG3_TSO_FW_BSS_LEN              0x894
5450
5451 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5452         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5453         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5454         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5455         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5456         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5457         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5458         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5459         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5460         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5461         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5462         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5463         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5464         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5465         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5466         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5467         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5468         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5469         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5470         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5471         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5472         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5473         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5474         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5475         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5476         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5477         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5478         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5479         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5480         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5481         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5482         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5483         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5484         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5485         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5486         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5487         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5488         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5489         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5490         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5491         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5492         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5493         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5494         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5495         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5496         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5497         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5498         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5499         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5500         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5501         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5502         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5503         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5504         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5505         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5506         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5507         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5508         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5509         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5510         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5511         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5512         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5513         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5514         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5515         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5516         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5517         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5518         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5519         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5520         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5521         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5522         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5523         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5524         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5525         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5526         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5527         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5528         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5529         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5530         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5531         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5532         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5533         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5534         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5535         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5536         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5537         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5538         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5539         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5540         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5541         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5542         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5543         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5544         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5545         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5546         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5547         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5548         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5549         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5550         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5551         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5552         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5553         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5554         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5555         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5556         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5557         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5558         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5559         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5560         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5561         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5562         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5563         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5564         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5565         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5566         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5567         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5568         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5569         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5570         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5571         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5572         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5573         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5574         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5575         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5576         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5577         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5578         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5579         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5580         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5581         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5582         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5583         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5584         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5585         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5586         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5587         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5588         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5589         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5590         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5591         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5592         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5593         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5594         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5595         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5596         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5597         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5598         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5599         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5600         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5601         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5602         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5603         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5604         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5605         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5606         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5607         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5608         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5609         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5610         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5611         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5612         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5613         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5614         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5615         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5616         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5617         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5618         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5619         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5620         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5621         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5622         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5623         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5624         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5625         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5626         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5627         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5628         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5629         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5630         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5631         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5632         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5633         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5634         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5635         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5636         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5637         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5638         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5639         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5640         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5641         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5642         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5643         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5644         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5645         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5646         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5647         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5648         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5649         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5650         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5651         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5652         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5653         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5654         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5655         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5656         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5657         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5658         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5659         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5660         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5661         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5662         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5663         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5664         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5665         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5666         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5667         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5668         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5669         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5670         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5671         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5672         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5673         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5674         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5675         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5676         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5677         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5678         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5679         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5680         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5681         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5682         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5683         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5684         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5685         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5686         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5687         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5688         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5689         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5690         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5691         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5692         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5693         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5694         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5695         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5696         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5697         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5698         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5699         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5700         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5701         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5702         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5703         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5704         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5705         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5706         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5707         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5708         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5709         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5710         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5711         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5712         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5713         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5714         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5715         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5716         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5717         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5718         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5719         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5720         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5721         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5722         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5723         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5724         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5725         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5726         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5727         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5728         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5729         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5730         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5731         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5732         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5733         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5734         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5735         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5736 };
5737
5738 static const u32 tg3TsoFwRodata[] = {
5739         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5740         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5741         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5742         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5743         0x00000000,
5744 };
5745
5746 static const u32 tg3TsoFwData[] = {
5747         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5748         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5749         0x00000000,
5750 };
5751
5752 /* 5705 needs a special version of the TSO firmware.  */
5753 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5754 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5755 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5756 #define TG3_TSO5_FW_START_ADDR          0x00010000
5757 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5758 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5759 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5760 #define TG3_TSO5_FW_RODATA_LEN          0x50
5761 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5762 #define TG3_TSO5_FW_DATA_LEN            0x20
5763 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5764 #define TG3_TSO5_FW_SBSS_LEN            0x28
5765 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5766 #define TG3_TSO5_FW_BSS_LEN             0x88
5767
5768 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5769         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5770         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5771         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5772         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5773         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5774         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5775         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5776         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5777         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5778         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5779         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5780         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5781         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5782         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5783         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5784         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5785         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5786         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5787         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5788         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5789         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5790         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5791         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5792         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5793         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5794         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5795         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5796         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5797         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5798         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5799         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5800         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5801         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5802         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5803         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5804         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5805         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5806         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5807         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5808         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5809         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5810         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5811         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5812         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5813         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5814         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5815         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5816         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5817         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5818         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5819         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5820         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5821         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5822         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5823         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5824         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5825         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5826         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5827         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5828         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5829         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5830         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5831         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5832         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5833         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5834         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5835         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5836         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5837         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5838         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5839         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5840         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5841         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5842         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5843         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5844         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5845         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5846         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5847         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5848         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5849         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5850         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5851         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5852         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5853         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5854         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5855         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5856         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5857         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5858         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5859         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5860         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5861         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5862         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5863         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5864         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5865         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5866         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5867         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5868         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5869         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5870         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5871         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5872         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5873         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5874         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5875         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5876         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5877         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5878         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5879         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5880         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5881         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5882         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5883         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5884         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5885         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5886         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5887         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5888         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5889         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5890         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5891         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5892         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5893         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5894         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5895         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5896         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5897         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5898         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5899         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5900         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5901         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5902         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5903         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5904         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5905         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5906         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5907         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5908         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5909         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5910         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5911         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5912         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5913         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5914         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5915         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5916         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5917         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5918         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5919         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5920         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5921         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5922         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5923         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5924         0x00000000, 0x00000000, 0x00000000,
5925 };
5926
5927 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5928         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5929         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5930         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5931         0x00000000, 0x00000000, 0x00000000,
5932 };
5933
5934 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5935         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5936         0x00000000, 0x00000000, 0x00000000,
5937 };
5938
5939 /* tp->lock is held. */
5940 static int tg3_load_tso_firmware(struct tg3 *tp)
5941 {
5942         struct fw_info info;
5943         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5944         int err, i;
5945
5946         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5947                 return 0;
5948
5949         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5950                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5951                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5952                 info.text_data = &tg3Tso5FwText[0];
5953                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5954                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5955                 info.rodata_data = &tg3Tso5FwRodata[0];
5956                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5957                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5958                 info.data_data = &tg3Tso5FwData[0];
5959                 cpu_base = RX_CPU_BASE;
5960                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5961                 cpu_scratch_size = (info.text_len +
5962                                     info.rodata_len +
5963                                     info.data_len +
5964                                     TG3_TSO5_FW_SBSS_LEN +
5965                                     TG3_TSO5_FW_BSS_LEN);
5966         } else {
5967                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5968                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5969                 info.text_data = &tg3TsoFwText[0];
5970                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5971                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5972                 info.rodata_data = &tg3TsoFwRodata[0];
5973                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5974                 info.data_len = TG3_TSO_FW_DATA_LEN;
5975                 info.data_data = &tg3TsoFwData[0];
5976                 cpu_base = TX_CPU_BASE;
5977                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5978                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5979         }
5980
5981         err = tg3_load_firmware_cpu(tp, cpu_base,
5982                                     cpu_scratch_base, cpu_scratch_size,
5983                                     &info);
5984         if (err)
5985                 return err;
5986
5987         /* Now startup the cpu. */
5988         tw32(cpu_base + CPU_STATE, 0xffffffff);
5989         tw32_f(cpu_base + CPU_PC,    info.text_base);
5990
5991         for (i = 0; i < 5; i++) {
5992                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5993                         break;
5994                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5995                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5996                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5997                 udelay(1000);
5998         }
5999         if (i >= 5) {
6000                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6001                        "to set CPU PC, is %08x should be %08x\n",
6002                        tp->dev->name, tr32(cpu_base + CPU_PC),
6003                        info.text_base);
6004                 return -ENODEV;
6005         }
6006         tw32(cpu_base + CPU_STATE, 0xffffffff);
6007         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6008         return 0;
6009 }
6010
6011
6012 /* tp->lock is held. */
6013 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6014 {
6015         u32 addr_high, addr_low;
6016         int i;
6017
6018         addr_high = ((tp->dev->dev_addr[0] << 8) |
6019                      tp->dev->dev_addr[1]);
6020         addr_low = ((tp->dev->dev_addr[2] << 24) |
6021                     (tp->dev->dev_addr[3] << 16) |
6022                     (tp->dev->dev_addr[4] <<  8) |
6023                     (tp->dev->dev_addr[5] <<  0));
6024         for (i = 0; i < 4; i++) {
6025                 if (i == 1 && skip_mac_1)
6026                         continue;
6027                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6028                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6029         }
6030
6031         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6033                 for (i = 0; i < 12; i++) {
6034                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6035                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6036                 }
6037         }
6038
6039         addr_high = (tp->dev->dev_addr[0] +
6040                      tp->dev->dev_addr[1] +
6041                      tp->dev->dev_addr[2] +
6042                      tp->dev->dev_addr[3] +
6043                      tp->dev->dev_addr[4] +
6044                      tp->dev->dev_addr[5]) &
6045                 TX_BACKOFF_SEED_MASK;
6046         tw32(MAC_TX_BACKOFF_SEED, addr_high);
6047 }
6048
6049 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6050 {
6051         struct tg3 *tp = netdev_priv(dev);
6052         struct sockaddr *addr = p;
6053         int err = 0, skip_mac_1 = 0;
6054
6055         if (!is_valid_ether_addr(addr->sa_data))
6056                 return -EINVAL;
6057
6058         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6059
6060         if (!netif_running(dev))
6061                 return 0;
6062
6063         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6064                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6065
6066                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6067                 addr0_low = tr32(MAC_ADDR_0_LOW);
6068                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6069                 addr1_low = tr32(MAC_ADDR_1_LOW);
6070
6071                 /* Skip MAC addr 1 if ASF is using it. */
6072                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6073                     !(addr1_high == 0 && addr1_low == 0))
6074                         skip_mac_1 = 1;
6075         }
6076         spin_lock_bh(&tp->lock);
6077         __tg3_set_mac_addr(tp, skip_mac_1);
6078         spin_unlock_bh(&tp->lock);
6079
6080         return err;
6081 }
6082
6083 /* tp->lock is held. */
6084 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6085                            dma_addr_t mapping, u32 maxlen_flags,
6086                            u32 nic_addr)
6087 {
6088         tg3_write_mem(tp,
6089                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6090                       ((u64) mapping >> 32));
6091         tg3_write_mem(tp,
6092                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6093                       ((u64) mapping & 0xffffffff));
6094         tg3_write_mem(tp,
6095                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6096                        maxlen_flags);
6097
6098         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6099                 tg3_write_mem(tp,
6100                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6101                               nic_addr);
6102 }
6103
6104 static void __tg3_set_rx_mode(struct net_device *);
6105 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6106 {
6107         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6108         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6109         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6110         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6111         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6112                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6113                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6114         }
6115         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6116         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6117         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6118                 u32 val = ec->stats_block_coalesce_usecs;
6119
6120                 if (!netif_carrier_ok(tp->dev))
6121                         val = 0;
6122
6123                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6124         }
6125 }
6126
6127 /* tp->lock is held. */
6128 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6129 {
6130         u32 val, rdmac_mode;
6131         int i, err, limit;
6132
6133         tg3_disable_ints(tp);
6134
6135         tg3_stop_fw(tp);
6136
6137         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6138
6139         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6140                 tg3_abort_hw(tp, 1);
6141         }
6142
6143         if (reset_phy)
6144                 tg3_phy_reset(tp);
6145
6146         err = tg3_chip_reset(tp);
6147         if (err)
6148                 return err;
6149
6150         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6151
6152         /* This works around an issue with Athlon chipsets on
6153          * B3 tigon3 silicon.  This bit has no effect on any
6154          * other revision.  But do not set this on PCI Express
6155          * chips.
6156          */
6157         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6158                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6159         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6160
6161         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6162             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6163                 val = tr32(TG3PCI_PCISTATE);
6164                 val |= PCISTATE_RETRY_SAME_DMA;
6165                 tw32(TG3PCI_PCISTATE, val);
6166         }
6167
6168         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6169                 /* Enable some hw fixes.  */
6170                 val = tr32(TG3PCI_MSI_DATA);
6171                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6172                 tw32(TG3PCI_MSI_DATA, val);
6173         }
6174
6175         /* Descriptor ring init may make accesses to the
6176          * NIC SRAM area to setup the TX descriptors, so we
6177          * can only do this after the hardware has been
6178          * successfully reset.
6179          */
6180         err = tg3_init_rings(tp);
6181         if (err)
6182                 return err;
6183
6184         /* This value is determined during the probe time DMA
6185          * engine test, tg3_test_dma.
6186          */
6187         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6188
6189         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6190                           GRC_MODE_4X_NIC_SEND_RINGS |
6191                           GRC_MODE_NO_TX_PHDR_CSUM |
6192                           GRC_MODE_NO_RX_PHDR_CSUM);
6193         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6194
6195         /* Pseudo-header checksum is done by hardware logic and not
6196          * the offload processers, so make the chip do the pseudo-
6197          * header checksums on receive.  For transmit it is more
6198          * convenient to do the pseudo-header checksum in software
6199          * as Linux does that on transmit for us in all cases.
6200          */
6201         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6202
6203         tw32(GRC_MODE,
6204              tp->grc_mode |
6205              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6206
6207         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6208         val = tr32(GRC_MISC_CFG);
6209         val &= ~0xff;
6210         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6211         tw32(GRC_MISC_CFG, val);
6212
6213         /* Initialize MBUF/DESC pool. */
6214         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6215                 /* Do nothing.  */
6216         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6217                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6218                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6219                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6220                 else
6221                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6222                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6223                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6224         }
6225         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6226                 int fw_len;
6227
6228                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6229                           TG3_TSO5_FW_RODATA_LEN +
6230                           TG3_TSO5_FW_DATA_LEN +
6231                           TG3_TSO5_FW_SBSS_LEN +
6232                           TG3_TSO5_FW_BSS_LEN);
6233                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6234                 tw32(BUFMGR_MB_POOL_ADDR,
6235                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6236                 tw32(BUFMGR_MB_POOL_SIZE,
6237                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6238         }
6239
6240         if (tp->dev->mtu <= ETH_DATA_LEN) {
6241                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6242                      tp->bufmgr_config.mbuf_read_dma_low_water);
6243                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6244                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6245                 tw32(BUFMGR_MB_HIGH_WATER,
6246                      tp->bufmgr_config.mbuf_high_water);
6247         } else {
6248                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6249                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6250                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6251                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6252                 tw32(BUFMGR_MB_HIGH_WATER,
6253                      tp->bufmgr_config.mbuf_high_water_jumbo);
6254         }
6255         tw32(BUFMGR_DMA_LOW_WATER,
6256              tp->bufmgr_config.dma_low_water);
6257         tw32(BUFMGR_DMA_HIGH_WATER,
6258              tp->bufmgr_config.dma_high_water);
6259
6260         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6261         for (i = 0; i < 2000; i++) {
6262                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6263                         break;
6264                 udelay(10);
6265         }
6266         if (i >= 2000) {
6267                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6268                        tp->dev->name);
6269                 return -ENODEV;
6270         }
6271
6272         /* Setup replenish threshold. */
6273         val = tp->rx_pending / 8;
6274         if (val == 0)
6275                 val = 1;
6276         else if (val > tp->rx_std_max_post)
6277                 val = tp->rx_std_max_post;
6278         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6279                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6280                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6281
6282                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6283                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6284         }
6285
6286         tw32(RCVBDI_STD_THRESH, val);
6287
6288         /* Initialize TG3_BDINFO's at:
6289          *  RCVDBDI_STD_BD:     standard eth size rx ring
6290          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6291          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6292          *
6293          * like so:
6294          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6295          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6296          *                              ring attribute flags
6297          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6298          *
6299          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6300          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6301          *
6302          * The size of each ring is fixed in the firmware, but the location is
6303          * configurable.
6304          */
6305         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6306              ((u64) tp->rx_std_mapping >> 32));
6307         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6308              ((u64) tp->rx_std_mapping & 0xffffffff));
6309         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6310              NIC_SRAM_RX_BUFFER_DESC);
6311
6312         /* Don't even try to program the JUMBO/MINI buffer descriptor
6313          * configs on 5705.
6314          */
6315         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6316                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6317                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6318         } else {
6319                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6320                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6321
6322                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6323                      BDINFO_FLAGS_DISABLED);
6324
6325                 /* Setup replenish threshold. */
6326                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6327
6328                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6329                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6330                              ((u64) tp->rx_jumbo_mapping >> 32));
6331                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6332                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6333                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6334                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6335                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6336                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6337                 } else {
6338                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6339                              BDINFO_FLAGS_DISABLED);
6340                 }
6341
6342         }
6343
6344         /* There is only one send ring on 5705/5750, no need to explicitly
6345          * disable the others.
6346          */
6347         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6348                 /* Clear out send RCB ring in SRAM. */
6349                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6350                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6351                                       BDINFO_FLAGS_DISABLED);
6352         }
6353
6354         tp->tx_prod = 0;
6355         tp->tx_cons = 0;
6356         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6357         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6358
6359         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6360                        tp->tx_desc_mapping,
6361                        (TG3_TX_RING_SIZE <<
6362                         BDINFO_FLAGS_MAXLEN_SHIFT),
6363                        NIC_SRAM_TX_BUFFER_DESC);
6364
6365         /* There is only one receive return ring on 5705/5750, no need
6366          * to explicitly disable the others.
6367          */
6368         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6369                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6370                      i += TG3_BDINFO_SIZE) {
6371                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6372                                       BDINFO_FLAGS_DISABLED);
6373                 }
6374         }
6375
6376         tp->rx_rcb_ptr = 0;
6377         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6378
6379         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6380                        tp->rx_rcb_mapping,
6381                        (TG3_RX_RCB_RING_SIZE(tp) <<
6382                         BDINFO_FLAGS_MAXLEN_SHIFT),
6383                        0);
6384
6385         tp->rx_std_ptr = tp->rx_pending;
6386         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6387                      tp->rx_std_ptr);
6388
6389         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6390                                                 tp->rx_jumbo_pending : 0;
6391         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6392                      tp->rx_jumbo_ptr);
6393
6394         /* Initialize MAC address and backoff seed. */
6395         __tg3_set_mac_addr(tp, 0);
6396
6397         /* MTU + ethernet header + FCS + optional VLAN tag */
6398         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6399
6400         /* The slot time is changed by tg3_setup_phy if we
6401          * run at gigabit with half duplex.
6402          */
6403         tw32(MAC_TX_LENGTHS,
6404              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6405              (6 << TX_LENGTHS_IPG_SHIFT) |
6406              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6407
6408         /* Receive rules. */
6409         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6410         tw32(RCVLPC_CONFIG, 0x0181);
6411
6412         /* Calculate RDMAC_MODE setting early, we need it to determine
6413          * the RCVLPC_STATE_ENABLE mask.
6414          */
6415         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6416                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6417                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6418                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6419                       RDMAC_MODE_LNGREAD_ENAB);
6420
6421         /* If statement applies to 5705 and 5750 PCI devices only */
6422         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6423              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6424             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6425                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6426                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6427                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6428                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6429                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6430                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6431                 }
6432         }
6433
6434         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6435                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6436
6437         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6438                 rdmac_mode |= (1 << 27);
6439
6440         /* Receive/send statistics. */
6441         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6442                 val = tr32(RCVLPC_STATS_ENABLE);
6443                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6444                 tw32(RCVLPC_STATS_ENABLE, val);
6445         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6446                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6447                 val = tr32(RCVLPC_STATS_ENABLE);
6448                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6449                 tw32(RCVLPC_STATS_ENABLE, val);
6450         } else {
6451                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6452         }
6453         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6454         tw32(SNDDATAI_STATSENAB, 0xffffff);
6455         tw32(SNDDATAI_STATSCTRL,
6456              (SNDDATAI_SCTRL_ENABLE |
6457               SNDDATAI_SCTRL_FASTUPD));
6458
6459         /* Setup host coalescing engine. */
6460         tw32(HOSTCC_MODE, 0);
6461         for (i = 0; i < 2000; i++) {
6462                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6463                         break;
6464                 udelay(10);
6465         }
6466
6467         __tg3_set_coalesce(tp, &tp->coal);
6468
6469         /* set status block DMA address */
6470         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6471              ((u64) tp->status_mapping >> 32));
6472         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6473              ((u64) tp->status_mapping & 0xffffffff));
6474
6475         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6476                 /* Status/statistics block address.  See tg3_timer,
6477                  * the tg3_periodic_fetch_stats call there, and
6478                  * tg3_get_stats to see how this works for 5705/5750 chips.
6479                  */
6480                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6481                      ((u64) tp->stats_mapping >> 32));
6482                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6483                      ((u64) tp->stats_mapping & 0xffffffff));
6484                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6485                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6486         }
6487
6488         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6489
6490         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6491         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6492         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6493                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6494
6495         /* Clear statistics/status block in chip, and status block in ram. */
6496         for (i = NIC_SRAM_STATS_BLK;
6497              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6498              i += sizeof(u32)) {
6499                 tg3_write_mem(tp, i, 0);
6500                 udelay(40);
6501         }
6502         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6503
6504         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6505                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6506                 /* reset to prevent losing 1st rx packet intermittently */
6507                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6508                 udelay(10);
6509         }
6510
6511         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6512                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6513         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6514             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6515             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6516                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6517         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6518         udelay(40);
6519
6520         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6521          * If TG3_FLG2_IS_NIC is zero, we should read the
6522          * register to preserve the GPIO settings for LOMs. The GPIOs,
6523          * whether used as inputs or outputs, are set by boot code after
6524          * reset.
6525          */
6526         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6527                 u32 gpio_mask;
6528
6529                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6530                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6531                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6532
6533                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6534                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6535                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6536
6537                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6538                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6539
6540                 tp->grc_local_ctrl &= ~gpio_mask;
6541                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6542
6543                 /* GPIO1 must be driven high for eeprom write protect */
6544                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6545                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6546                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6547         }
6548         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6549         udelay(100);
6550
6551         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6552         tp->last_tag = 0;
6553
6554         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6555                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6556                 udelay(40);
6557         }
6558
6559         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6560                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6561                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6562                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6563                WDMAC_MODE_LNGREAD_ENAB);
6564
6565         /* If statement applies to 5705 and 5750 PCI devices only */
6566         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6567              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6568             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6569                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6570                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6571                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6572                         /* nothing */
6573                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6574                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6575                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6576                         val |= WDMAC_MODE_RX_ACCEL;
6577                 }
6578         }
6579
6580         /* Enable host coalescing bug fix */
6581         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6582             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6583                 val |= (1 << 29);
6584
6585         tw32_f(WDMAC_MODE, val);
6586         udelay(40);
6587
6588         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6589                 val = tr32(TG3PCI_X_CAPS);
6590                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6591                         val &= ~PCIX_CAPS_BURST_MASK;
6592                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6593                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6594                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6595                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6596                 }
6597                 tw32(TG3PCI_X_CAPS, val);
6598         }
6599
6600         tw32_f(RDMAC_MODE, rdmac_mode);
6601         udelay(40);
6602
6603         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6604         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6605                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6606         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6607         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6608         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6609         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6610         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6611         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6612                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6613         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6614         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6615
6616         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6617                 err = tg3_load_5701_a0_firmware_fix(tp);
6618                 if (err)
6619                         return err;
6620         }
6621
6622         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6623                 err = tg3_load_tso_firmware(tp);
6624                 if (err)
6625                         return err;
6626         }
6627
6628         tp->tx_mode = TX_MODE_ENABLE;
6629         tw32_f(MAC_TX_MODE, tp->tx_mode);
6630         udelay(100);
6631
6632         tp->rx_mode = RX_MODE_ENABLE;
6633         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6634                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6635
6636         tw32_f(MAC_RX_MODE, tp->rx_mode);
6637         udelay(10);
6638
6639         if (tp->link_config.phy_is_low_power) {
6640                 tp->link_config.phy_is_low_power = 0;
6641                 tp->link_config.speed = tp->link_config.orig_speed;
6642                 tp->link_config.duplex = tp->link_config.orig_duplex;
6643                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6644         }
6645
6646         tp->mi_mode = MAC_MI_MODE_BASE;
6647         tw32_f(MAC_MI_MODE, tp->mi_mode);
6648         udelay(80);
6649
6650         tw32(MAC_LED_CTRL, tp->led_ctrl);
6651
6652         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6653         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6654                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6655                 udelay(10);
6656         }
6657         tw32_f(MAC_RX_MODE, tp->rx_mode);
6658         udelay(10);
6659
6660         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6661                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6662                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6663                         /* Set drive transmission level to 1.2V  */
6664                         /* only if the signal pre-emphasis bit is not set  */
6665                         val = tr32(MAC_SERDES_CFG);
6666                         val &= 0xfffff000;
6667                         val |= 0x880;
6668                         tw32(MAC_SERDES_CFG, val);
6669                 }
6670                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6671                         tw32(MAC_SERDES_CFG, 0x616000);
6672         }
6673
6674         /* Prevent chip from dropping frames when flow control
6675          * is enabled.
6676          */
6677         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6678
6679         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6680             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6681                 /* Use hardware link auto-negotiation */
6682                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6683         }
6684
6685         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6686             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6687                 u32 tmp;
6688
6689                 tmp = tr32(SERDES_RX_CTRL);
6690                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6691                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6692                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6693                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6694         }
6695
6696         err = tg3_setup_phy(tp, 0);
6697         if (err)
6698                 return err;
6699
6700         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6701             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6702                 u32 tmp;
6703
6704                 /* Clear CRC stats. */
6705                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6706                         tg3_writephy(tp, MII_TG3_TEST1,
6707                                      tmp | MII_TG3_TEST1_CRC_EN);
6708                         tg3_readphy(tp, 0x14, &tmp);
6709                 }
6710         }
6711
6712         __tg3_set_rx_mode(tp->dev);
6713
6714         /* Initialize receive rules. */
6715         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6716         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6717         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6718         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6719
6720         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6721             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6722                 limit = 8;
6723         else
6724                 limit = 16;
6725         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6726                 limit -= 4;
6727         switch (limit) {
6728         case 16:
6729                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6730         case 15:
6731                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6732         case 14:
6733                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6734         case 13:
6735                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6736         case 12:
6737                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6738         case 11:
6739                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6740         case 10:
6741                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6742         case 9:
6743                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6744         case 8:
6745                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6746         case 7:
6747                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6748         case 6:
6749                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6750         case 5:
6751                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6752         case 4:
6753                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6754         case 3:
6755                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6756         case 2:
6757         case 1:
6758
6759         default:
6760                 break;
6761         };
6762
6763         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6764
6765         return 0;
6766 }
6767
6768 /* Called at device open time to get the chip ready for
6769  * packet processing.  Invoked with tp->lock held.
6770  */
6771 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6772 {
6773         int err;
6774
6775         /* Force the chip into D0. */
6776         err = tg3_set_power_state(tp, PCI_D0);
6777         if (err)
6778                 goto out;
6779
6780         tg3_switch_clocks(tp);
6781
6782         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6783
6784         err = tg3_reset_hw(tp, reset_phy);
6785
6786 out:
6787         return err;
6788 }
6789
6790 #define TG3_STAT_ADD32(PSTAT, REG) \
6791 do {    u32 __val = tr32(REG); \
6792         (PSTAT)->low += __val; \
6793         if ((PSTAT)->low < __val) \
6794                 (PSTAT)->high += 1; \
6795 } while (0)
6796
6797 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6798 {
6799         struct tg3_hw_stats *sp = tp->hw_stats;
6800
6801         if (!netif_carrier_ok(tp->dev))
6802                 return;
6803
6804         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6805         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6806         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6807         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6808         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6809         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6810         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6811         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6812         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6813         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6814         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6815         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6816         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6817
6818         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6819         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6820         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6821         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6822         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6823         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6824         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6825         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6826         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6827         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6828         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6829         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6830         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6831         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6832
6833         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6834         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6835         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6836 }
6837
6838 static void tg3_timer(unsigned long __opaque)
6839 {
6840         struct tg3 *tp = (struct tg3 *) __opaque;
6841
6842         if (tp->irq_sync)
6843                 goto restart_timer;
6844
6845         spin_lock(&tp->lock);
6846
6847         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6848                 /* All of this garbage is because when using non-tagged
6849                  * IRQ status the mailbox/status_block protocol the chip
6850                  * uses with the cpu is race prone.
6851                  */
6852                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6853                         tw32(GRC_LOCAL_CTRL,
6854                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6855                 } else {
6856                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6857                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6858                 }
6859
6860                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6861                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6862                         spin_unlock(&tp->lock);
6863                         schedule_work(&tp->reset_task);
6864                         return;
6865                 }
6866         }
6867
6868         /* This part only runs once per second. */
6869         if (!--tp->timer_counter) {
6870                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6871                         tg3_periodic_fetch_stats(tp);
6872
6873                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6874                         u32 mac_stat;
6875                         int phy_event;
6876
6877                         mac_stat = tr32(MAC_STATUS);
6878
6879                         phy_event = 0;
6880                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6881                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6882                                         phy_event = 1;
6883                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6884                                 phy_event = 1;
6885
6886                         if (phy_event)
6887                                 tg3_setup_phy(tp, 0);
6888                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6889                         u32 mac_stat = tr32(MAC_STATUS);
6890                         int need_setup = 0;
6891
6892                         if (netif_carrier_ok(tp->dev) &&
6893                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6894                                 need_setup = 1;
6895                         }
6896                         if (! netif_carrier_ok(tp->dev) &&
6897                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6898                                          MAC_STATUS_SIGNAL_DET))) {
6899                                 need_setup = 1;
6900                         }
6901                         if (need_setup) {
6902                                 if (!tp->serdes_counter) {
6903                                         tw32_f(MAC_MODE,
6904                                              (tp->mac_mode &
6905                                               ~MAC_MODE_PORT_MODE_MASK));
6906                                         udelay(40);
6907                                         tw32_f(MAC_MODE, tp->mac_mode);
6908                                         udelay(40);
6909                                 }
6910                                 tg3_setup_phy(tp, 0);
6911                         }
6912                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6913                         tg3_serdes_parallel_detect(tp);
6914
6915                 tp->timer_counter = tp->timer_multiplier;
6916         }
6917
6918         /* Heartbeat is only sent once every 2 seconds.
6919          *
6920          * The heartbeat is to tell the ASF firmware that the host
6921          * driver is still alive.  In the event that the OS crashes,
6922          * ASF needs to reset the hardware to free up the FIFO space
6923          * that may be filled with rx packets destined for the host.
6924          * If the FIFO is full, ASF will no longer function properly.
6925          *
6926          * Unintended resets have been reported on real time kernels
6927          * where the timer doesn't run on time.  Netpoll will also have
6928          * same problem.
6929          *
6930          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6931          * to check the ring condition when the heartbeat is expiring
6932          * before doing the reset.  This will prevent most unintended
6933          * resets.
6934          */
6935         if (!--tp->asf_counter) {
6936                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6937                         u32 val;
6938
6939                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6940                                       FWCMD_NICDRV_ALIVE3);
6941                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6942                         /* 5 seconds timeout */
6943                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6944                         val = tr32(GRC_RX_CPU_EVENT);
6945                         val |= (1 << 14);
6946                         tw32(GRC_RX_CPU_EVENT, val);
6947                 }
6948                 tp->asf_counter = tp->asf_multiplier;
6949         }
6950
6951         spin_unlock(&tp->lock);
6952
6953 restart_timer:
6954         tp->timer.expires = jiffies + tp->timer_offset;
6955         add_timer(&tp->timer);
6956 }
6957
6958 static int tg3_request_irq(struct tg3 *tp)
6959 {
6960         irq_handler_t fn;
6961         unsigned long flags;
6962         struct net_device *dev = tp->dev;
6963
6964         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6965                 fn = tg3_msi;
6966                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6967                         fn = tg3_msi_1shot;
6968                 flags = IRQF_SAMPLE_RANDOM;
6969         } else {
6970                 fn = tg3_interrupt;
6971                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6972                         fn = tg3_interrupt_tagged;
6973                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6974         }
6975         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6976 }
6977
6978 static int tg3_test_interrupt(struct tg3 *tp)
6979 {
6980         struct net_device *dev = tp->dev;
6981         int err, i, intr_ok = 0;
6982
6983         if (!netif_running(dev))
6984                 return -ENODEV;
6985
6986         tg3_disable_ints(tp);
6987
6988         free_irq(tp->pdev->irq, dev);
6989
6990         err = request_irq(tp->pdev->irq, tg3_test_isr,
6991                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6992         if (err)
6993                 return err;
6994
6995         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6996         tg3_enable_ints(tp);
6997
6998         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6999                HOSTCC_MODE_NOW);
7000
7001         for (i = 0; i < 5; i++) {
7002                 u32 int_mbox, misc_host_ctrl;
7003
7004                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7005                                         TG3_64BIT_REG_LOW);
7006                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7007
7008                 if ((int_mbox != 0) ||
7009                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7010                         intr_ok = 1;
7011                         break;
7012                 }
7013
7014                 msleep(10);
7015         }
7016
7017         tg3_disable_ints(tp);
7018
7019         free_irq(tp->pdev->irq, dev);
7020
7021         err = tg3_request_irq(tp);
7022
7023         if (err)
7024                 return err;
7025
7026         if (intr_ok)
7027                 return 0;
7028
7029         return -EIO;
7030 }
7031
7032 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7033  * successfully restored
7034  */
7035 static int tg3_test_msi(struct tg3 *tp)
7036 {
7037         struct net_device *dev = tp->dev;
7038         int err;
7039         u16 pci_cmd;
7040
7041         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7042                 return 0;
7043
7044         /* Turn off SERR reporting in case MSI terminates with Master
7045          * Abort.
7046          */
7047         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7048         pci_write_config_word(tp->pdev, PCI_COMMAND,
7049                               pci_cmd & ~PCI_COMMAND_SERR);
7050
7051         err = tg3_test_interrupt(tp);
7052
7053         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7054
7055         if (!err)
7056                 return 0;
7057
7058         /* other failures */
7059         if (err != -EIO)
7060                 return err;
7061
7062         /* MSI test failed, go back to INTx mode */
7063         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7064                "switching to INTx mode. Please report this failure to "
7065                "the PCI maintainer and include system chipset information.\n",
7066                        tp->dev->name);
7067
7068         free_irq(tp->pdev->irq, dev);
7069         pci_disable_msi(tp->pdev);
7070
7071         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7072
7073         err = tg3_request_irq(tp);
7074         if (err)
7075                 return err;
7076
7077         /* Need to reset the chip because the MSI cycle may have terminated
7078          * with Master Abort.
7079          */
7080         tg3_full_lock(tp, 1);
7081
7082         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7083         err = tg3_init_hw(tp, 1);
7084
7085         tg3_full_unlock(tp);
7086
7087         if (err)
7088                 free_irq(tp->pdev->irq, dev);
7089
7090         return err;
7091 }
7092
7093 static int tg3_open(struct net_device *dev)
7094 {
7095         struct tg3 *tp = netdev_priv(dev);
7096         int err;
7097
7098         netif_carrier_off(tp->dev);
7099
7100         tg3_full_lock(tp, 0);
7101
7102         err = tg3_set_power_state(tp, PCI_D0);
7103         if (err) {
7104                 tg3_full_unlock(tp);
7105                 return err;
7106         }
7107
7108         tg3_disable_ints(tp);
7109         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7110
7111         tg3_full_unlock(tp);
7112
7113         /* The placement of this call is tied
7114          * to the setup and use of Host TX descriptors.
7115          */
7116         err = tg3_alloc_consistent(tp);
7117         if (err)
7118                 return err;
7119
7120         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7121                 /* All MSI supporting chips should support tagged
7122                  * status.  Assert that this is the case.
7123                  */
7124                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7125                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7126                                "Not using MSI.\n", tp->dev->name);
7127                 } else if (pci_enable_msi(tp->pdev) == 0) {
7128                         u32 msi_mode;
7129
7130                         /* Hardware bug - MSI won't work if INTX disabled. */
7131                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7132                                 pci_intx(tp->pdev, 1);
7133
7134                         msi_mode = tr32(MSGINT_MODE);
7135                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7136                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7137                 }
7138         }
7139         err = tg3_request_irq(tp);
7140
7141         if (err) {
7142                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7143                         pci_disable_msi(tp->pdev);
7144                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7145                 }
7146                 tg3_free_consistent(tp);
7147                 return err;
7148         }
7149
7150         tg3_full_lock(tp, 0);
7151
7152         err = tg3_init_hw(tp, 1);
7153         if (err) {
7154                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7155                 tg3_free_rings(tp);
7156         } else {
7157                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7158                         tp->timer_offset = HZ;
7159                 else
7160                         tp->timer_offset = HZ / 10;
7161
7162                 BUG_ON(tp->timer_offset > HZ);
7163                 tp->timer_counter = tp->timer_multiplier =
7164                         (HZ / tp->timer_offset);
7165                 tp->asf_counter = tp->asf_multiplier =
7166                         ((HZ / tp->timer_offset) * 2);
7167
7168                 init_timer(&tp->timer);
7169                 tp->timer.expires = jiffies + tp->timer_offset;
7170                 tp->timer.data = (unsigned long) tp;
7171                 tp->timer.function = tg3_timer;
7172         }
7173
7174         tg3_full_unlock(tp);
7175
7176         if (err) {
7177                 free_irq(tp->pdev->irq, dev);
7178                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7179                         pci_disable_msi(tp->pdev);
7180                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7181                 }
7182                 tg3_free_consistent(tp);
7183                 return err;
7184         }
7185
7186         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7187                 err = tg3_test_msi(tp);
7188
7189                 if (err) {
7190                         tg3_full_lock(tp, 0);
7191
7192                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7193                                 pci_disable_msi(tp->pdev);
7194                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7195                         }
7196                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7197                         tg3_free_rings(tp);
7198                         tg3_free_consistent(tp);
7199
7200                         tg3_full_unlock(tp);
7201
7202                         return err;
7203                 }
7204
7205                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7206                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7207                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7208
7209                                 tw32(PCIE_TRANSACTION_CFG,
7210                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7211                         }
7212                 }
7213         }
7214
7215         tg3_full_lock(tp, 0);
7216
7217         add_timer(&tp->timer);
7218         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7219         tg3_enable_ints(tp);
7220
7221         tg3_full_unlock(tp);
7222
7223         netif_start_queue(dev);
7224
7225         return 0;
7226 }
7227
7228 #if 0
7229 /*static*/ void tg3_dump_state(struct tg3 *tp)
7230 {
7231         u32 val32, val32_2, val32_3, val32_4, val32_5;
7232         u16 val16;
7233         int i;
7234
7235         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7236         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7237         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7238                val16, val32);
7239
7240         /* MAC block */
7241         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7242                tr32(MAC_MODE), tr32(MAC_STATUS));
7243         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7244                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7245         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7246                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7247         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7248                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7249
7250         /* Send data initiator control block */
7251         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7252                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7253         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7254                tr32(SNDDATAI_STATSCTRL));
7255
7256         /* Send data completion control block */
7257         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7258
7259         /* Send BD ring selector block */
7260         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7261                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7262
7263         /* Send BD initiator control block */
7264         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7265                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7266
7267         /* Send BD completion control block */
7268         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7269
7270         /* Receive list placement control block */
7271         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7272                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7273         printk("       RCVLPC_STATSCTRL[%08x]\n",
7274                tr32(RCVLPC_STATSCTRL));
7275
7276         /* Receive data and receive BD initiator control block */
7277         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7278                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7279
7280         /* Receive data completion control block */
7281         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7282                tr32(RCVDCC_MODE));
7283
7284         /* Receive BD initiator control block */
7285         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7286                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7287
7288         /* Receive BD completion control block */
7289         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7290                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7291
7292         /* Receive list selector control block */
7293         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7294                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7295
7296         /* Mbuf cluster free block */
7297         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7298                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7299
7300         /* Host coalescing control block */
7301         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7302                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7303         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7304                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7305                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7306         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7307                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7308                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7309         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7310                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7311         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7312                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7313
7314         /* Memory arbiter control block */
7315         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7316                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7317
7318         /* Buffer manager control block */
7319         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7320                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7321         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7322                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7323         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7324                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7325                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7326                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7327
7328         /* Read DMA control block */
7329         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7330                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7331
7332         /* Write DMA control block */
7333         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7334                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7335
7336         /* DMA completion block */
7337         printk("DEBUG: DMAC_MODE[%08x]\n",
7338                tr32(DMAC_MODE));
7339
7340         /* GRC block */
7341         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7342                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7343         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7344                tr32(GRC_LOCAL_CTRL));
7345
7346         /* TG3_BDINFOs */
7347         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7348                tr32(RCVDBDI_JUMBO_BD + 0x0),
7349                tr32(RCVDBDI_JUMBO_BD + 0x4),
7350                tr32(RCVDBDI_JUMBO_BD + 0x8),
7351                tr32(RCVDBDI_JUMBO_BD + 0xc));
7352         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7353                tr32(RCVDBDI_STD_BD + 0x0),
7354                tr32(RCVDBDI_STD_BD + 0x4),
7355                tr32(RCVDBDI_STD_BD + 0x8),
7356                tr32(RCVDBDI_STD_BD + 0xc));
7357         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7358                tr32(RCVDBDI_MINI_BD + 0x0),
7359                tr32(RCVDBDI_MINI_BD + 0x4),
7360                tr32(RCVDBDI_MINI_BD + 0x8),
7361                tr32(RCVDBDI_MINI_BD + 0xc));
7362
7363         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7364         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7365         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7366         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7367         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7368                val32, val32_2, val32_3, val32_4);
7369
7370         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7371         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7372         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7373         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7374         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7375                val32, val32_2, val32_3, val32_4);
7376
7377         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7378         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7379         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7380         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7381         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7382         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7383                val32, val32_2, val32_3, val32_4, val32_5);
7384
7385         /* SW status block */
7386         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7387                tp->hw_status->status,
7388                tp->hw_status->status_tag,
7389                tp->hw_status->rx_jumbo_consumer,
7390                tp->hw_status->rx_consumer,
7391                tp->hw_status->rx_mini_consumer,
7392                tp->hw_status->idx[0].rx_producer,
7393                tp->hw_status->idx[0].tx_consumer);
7394
7395         /* SW statistics block */
7396         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7397                ((u32 *)tp->hw_stats)[0],
7398                ((u32 *)tp->hw_stats)[1],
7399                ((u32 *)tp->hw_stats)[2],
7400                ((u32 *)tp->hw_stats)[3]);
7401
7402         /* Mailboxes */
7403         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7404                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7405                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7406                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7407                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7408
7409         /* NIC side send descriptors. */
7410         for (i = 0; i < 6; i++) {
7411                 unsigned long txd;
7412
7413                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7414                         + (i * sizeof(struct tg3_tx_buffer_desc));
7415                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7416                        i,
7417                        readl(txd + 0x0), readl(txd + 0x4),
7418                        readl(txd + 0x8), readl(txd + 0xc));
7419         }
7420
7421         /* NIC side RX descriptors. */
7422         for (i = 0; i < 6; i++) {
7423                 unsigned long rxd;
7424
7425                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7426                         + (i * sizeof(struct tg3_rx_buffer_desc));
7427                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7428                        i,
7429                        readl(rxd + 0x0), readl(rxd + 0x4),
7430                        readl(rxd + 0x8), readl(rxd + 0xc));
7431                 rxd += (4 * sizeof(u32));
7432                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7433                        i,
7434                        readl(rxd + 0x0), readl(rxd + 0x4),
7435                        readl(rxd + 0x8), readl(rxd + 0xc));
7436         }
7437
7438         for (i = 0; i < 6; i++) {
7439                 unsigned long rxd;
7440
7441                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7442                         + (i * sizeof(struct tg3_rx_buffer_desc));
7443                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7444                        i,
7445                        readl(rxd + 0x0), readl(rxd + 0x4),
7446                        readl(rxd + 0x8), readl(rxd + 0xc));
7447                 rxd += (4 * sizeof(u32));
7448                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7449                        i,
7450                        readl(rxd + 0x0), readl(rxd + 0x4),
7451                        readl(rxd + 0x8), readl(rxd + 0xc));
7452         }
7453 }
7454 #endif
7455
7456 static struct net_device_stats *tg3_get_stats(struct net_device *);
7457 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7458
7459 static int tg3_close(struct net_device *dev)
7460 {
7461         struct tg3 *tp = netdev_priv(dev);
7462
7463         cancel_work_sync(&tp->reset_task);
7464
7465         netif_stop_queue(dev);
7466
7467         del_timer_sync(&tp->timer);
7468
7469         tg3_full_lock(tp, 1);
7470 #if 0
7471         tg3_dump_state(tp);
7472 #endif
7473
7474         tg3_disable_ints(tp);
7475
7476         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7477         tg3_free_rings(tp);
7478         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7479
7480         tg3_full_unlock(tp);
7481
7482         free_irq(tp->pdev->irq, dev);
7483         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7484                 pci_disable_msi(tp->pdev);
7485                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7486         }
7487
7488         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7489                sizeof(tp->net_stats_prev));
7490         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7491                sizeof(tp->estats_prev));
7492
7493         tg3_free_consistent(tp);
7494
7495         tg3_set_power_state(tp, PCI_D3hot);
7496
7497         netif_carrier_off(tp->dev);
7498
7499         return 0;
7500 }
7501
7502 static inline unsigned long get_stat64(tg3_stat64_t *val)
7503 {
7504         unsigned long ret;
7505
7506 #if (BITS_PER_LONG == 32)
7507         ret = val->low;
7508 #else
7509         ret = ((u64)val->high << 32) | ((u64)val->low);
7510 #endif
7511         return ret;
7512 }
7513
7514 static unsigned long calc_crc_errors(struct tg3 *tp)
7515 {
7516         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7517
7518         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7519             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7520              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7521                 u32 val;
7522
7523                 spin_lock_bh(&tp->lock);
7524                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7525                         tg3_writephy(tp, MII_TG3_TEST1,
7526                                      val | MII_TG3_TEST1_CRC_EN);
7527                         tg3_readphy(tp, 0x14, &val);
7528                 } else
7529                         val = 0;
7530                 spin_unlock_bh(&tp->lock);
7531
7532                 tp->phy_crc_errors += val;
7533
7534                 return tp->phy_crc_errors;
7535         }
7536
7537         return get_stat64(&hw_stats->rx_fcs_errors);
7538 }
7539
7540 #define ESTAT_ADD(member) \
7541         estats->member =        old_estats->member + \
7542                                 get_stat64(&hw_stats->member)
7543
7544 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7545 {
7546         struct tg3_ethtool_stats *estats = &tp->estats;
7547         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7548         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7549
7550         if (!hw_stats)
7551                 return old_estats;
7552
7553         ESTAT_ADD(rx_octets);
7554         ESTAT_ADD(rx_fragments);
7555         ESTAT_ADD(rx_ucast_packets);
7556         ESTAT_ADD(rx_mcast_packets);
7557         ESTAT_ADD(rx_bcast_packets);
7558         ESTAT_ADD(rx_fcs_errors);
7559         ESTAT_ADD(rx_align_errors);
7560         ESTAT_ADD(rx_xon_pause_rcvd);
7561         ESTAT_ADD(rx_xoff_pause_rcvd);
7562         ESTAT_ADD(rx_mac_ctrl_rcvd);
7563         ESTAT_ADD(rx_xoff_entered);
7564         ESTAT_ADD(rx_frame_too_long_errors);
7565         ESTAT_ADD(rx_jabbers);
7566         ESTAT_ADD(rx_undersize_packets);
7567         ESTAT_ADD(rx_in_length_errors);
7568         ESTAT_ADD(rx_out_length_errors);
7569         ESTAT_ADD(rx_64_or_less_octet_packets);
7570         ESTAT_ADD(rx_65_to_127_octet_packets);
7571         ESTAT_ADD(rx_128_to_255_octet_packets);
7572         ESTAT_ADD(rx_256_to_511_octet_packets);
7573         ESTAT_ADD(rx_512_to_1023_octet_packets);
7574         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7575         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7576         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7577         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7578         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7579
7580         ESTAT_ADD(tx_octets);
7581         ESTAT_ADD(tx_collisions);
7582         ESTAT_ADD(tx_xon_sent);
7583         ESTAT_ADD(tx_xoff_sent);
7584         ESTAT_ADD(tx_flow_control);
7585         ESTAT_ADD(tx_mac_errors);
7586         ESTAT_ADD(tx_single_collisions);
7587         ESTAT_ADD(tx_mult_collisions);
7588         ESTAT_ADD(tx_deferred);
7589         ESTAT_ADD(tx_excessive_collisions);
7590         ESTAT_ADD(tx_late_collisions);
7591         ESTAT_ADD(tx_collide_2times);
7592         ESTAT_ADD(tx_collide_3times);
7593         ESTAT_ADD(tx_collide_4times);
7594         ESTAT_ADD(tx_collide_5times);
7595         ESTAT_ADD(tx_collide_6times);
7596         ESTAT_ADD(tx_collide_7times);
7597         ESTAT_ADD(tx_collide_8times);
7598         ESTAT_ADD(tx_collide_9times);
7599         ESTAT_ADD(tx_collide_10times);
7600         ESTAT_ADD(tx_collide_11times);
7601         ESTAT_ADD(tx_collide_12times);
7602         ESTAT_ADD(tx_collide_13times);
7603         ESTAT_ADD(tx_collide_14times);
7604         ESTAT_ADD(tx_collide_15times);
7605         ESTAT_ADD(tx_ucast_packets);
7606         ESTAT_ADD(tx_mcast_packets);
7607         ESTAT_ADD(tx_bcast_packets);
7608         ESTAT_ADD(tx_carrier_sense_errors);
7609         ESTAT_ADD(tx_discards);
7610         ESTAT_ADD(tx_errors);
7611
7612         ESTAT_ADD(dma_writeq_full);
7613         ESTAT_ADD(dma_write_prioq_full);
7614         ESTAT_ADD(rxbds_empty);
7615         ESTAT_ADD(rx_discards);
7616         ESTAT_ADD(rx_errors);
7617         ESTAT_ADD(rx_threshold_hit);
7618
7619         ESTAT_ADD(dma_readq_full);
7620         ESTAT_ADD(dma_read_prioq_full);
7621         ESTAT_ADD(tx_comp_queue_full);
7622
7623         ESTAT_ADD(ring_set_send_prod_index);
7624         ESTAT_ADD(ring_status_update);
7625         ESTAT_ADD(nic_irqs);
7626         ESTAT_ADD(nic_avoided_irqs);
7627         ESTAT_ADD(nic_tx_threshold_hit);
7628
7629         return estats;
7630 }
7631
7632 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7633 {
7634         struct tg3 *tp = netdev_priv(dev);
7635         struct net_device_stats *stats = &tp->net_stats;
7636         struct net_device_stats *old_stats = &tp->net_stats_prev;
7637         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7638
7639         if (!hw_stats)
7640                 return old_stats;
7641
7642         stats->rx_packets = old_stats->rx_packets +
7643                 get_stat64(&hw_stats->rx_ucast_packets) +
7644                 get_stat64(&hw_stats->rx_mcast_packets) +
7645                 get_stat64(&hw_stats->rx_bcast_packets);
7646
7647         stats->tx_packets = old_stats->tx_packets +
7648                 get_stat64(&hw_stats->tx_ucast_packets) +
7649                 get_stat64(&hw_stats->tx_mcast_packets) +
7650                 get_stat64(&hw_stats->tx_bcast_packets);
7651
7652         stats->rx_bytes = old_stats->rx_bytes +
7653                 get_stat64(&hw_stats->rx_octets);
7654         stats->tx_bytes = old_stats->tx_bytes +
7655                 get_stat64(&hw_stats->tx_octets);
7656
7657         stats->rx_errors = old_stats->rx_errors +
7658                 get_stat64(&hw_stats->rx_errors);
7659         stats->tx_errors = old_stats->tx_errors +
7660                 get_stat64(&hw_stats->tx_errors) +
7661                 get_stat64(&hw_stats->tx_mac_errors) +
7662                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7663                 get_stat64(&hw_stats->tx_discards);
7664
7665         stats->multicast = old_stats->multicast +
7666                 get_stat64(&hw_stats->rx_mcast_packets);
7667         stats->collisions = old_stats->collisions +
7668                 get_stat64(&hw_stats->tx_collisions);
7669
7670         stats->rx_length_errors = old_stats->rx_length_errors +
7671                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7672                 get_stat64(&hw_stats->rx_undersize_packets);
7673
7674         stats->rx_over_errors = old_stats->rx_over_errors +
7675                 get_stat64(&hw_stats->rxbds_empty);
7676         stats->rx_frame_errors = old_stats->rx_frame_errors +
7677                 get_stat64(&hw_stats->rx_align_errors);
7678         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7679                 get_stat64(&hw_stats->tx_discards);
7680         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7681                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7682
7683         stats->rx_crc_errors = old_stats->rx_crc_errors +
7684                 calc_crc_errors(tp);
7685
7686         stats->rx_missed_errors = old_stats->rx_missed_errors +
7687                 get_stat64(&hw_stats->rx_discards);
7688
7689         return stats;
7690 }
7691
7692 static inline u32 calc_crc(unsigned char *buf, int len)
7693 {
7694         u32 reg;
7695         u32 tmp;
7696         int j, k;
7697
7698         reg = 0xffffffff;
7699
7700         for (j = 0; j < len; j++) {
7701                 reg ^= buf[j];
7702
7703                 for (k = 0; k < 8; k++) {
7704                         tmp = reg & 0x01;
7705
7706                         reg >>= 1;
7707
7708                         if (tmp) {
7709                                 reg ^= 0xedb88320;
7710                         }
7711                 }
7712         }
7713
7714         return ~reg;
7715 }
7716
7717 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7718 {
7719         /* accept or reject all multicast frames */
7720         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7721         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7722         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7723         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7724 }
7725
7726 static void __tg3_set_rx_mode(struct net_device *dev)
7727 {
7728         struct tg3 *tp = netdev_priv(dev);
7729         u32 rx_mode;
7730
7731         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7732                                   RX_MODE_KEEP_VLAN_TAG);
7733
7734         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7735          * flag clear.
7736          */
7737 #if TG3_VLAN_TAG_USED
7738         if (!tp->vlgrp &&
7739             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7740                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7741 #else
7742         /* By definition, VLAN is disabled always in this
7743          * case.
7744          */
7745         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7746                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7747 #endif
7748
7749         if (dev->flags & IFF_PROMISC) {
7750                 /* Promiscuous mode. */
7751                 rx_mode |= RX_MODE_PROMISC;
7752         } else if (dev->flags & IFF_ALLMULTI) {
7753                 /* Accept all multicast. */
7754                 tg3_set_multi (tp, 1);
7755         } else if (dev->mc_count < 1) {
7756                 /* Reject all multicast. */
7757                 tg3_set_multi (tp, 0);
7758         } else {
7759                 /* Accept one or more multicast(s). */
7760                 struct dev_mc_list *mclist;
7761                 unsigned int i;
7762                 u32 mc_filter[4] = { 0, };
7763                 u32 regidx;
7764                 u32 bit;
7765                 u32 crc;
7766
7767                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7768                      i++, mclist = mclist->next) {
7769
7770                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7771                         bit = ~crc & 0x7f;
7772                         regidx = (bit & 0x60) >> 5;
7773                         bit &= 0x1f;
7774                         mc_filter[regidx] |= (1 << bit);
7775                 }
7776
7777                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7778                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7779                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7780                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7781         }
7782
7783         if (rx_mode != tp->rx_mode) {
7784                 tp->rx_mode = rx_mode;
7785                 tw32_f(MAC_RX_MODE, rx_mode);
7786                 udelay(10);
7787         }
7788 }
7789
7790 static void tg3_set_rx_mode(struct net_device *dev)
7791 {
7792         struct tg3 *tp = netdev_priv(dev);
7793
7794         if (!netif_running(dev))
7795                 return;
7796
7797         tg3_full_lock(tp, 0);
7798         __tg3_set_rx_mode(dev);
7799         tg3_full_unlock(tp);
7800 }
7801
7802 #define TG3_REGDUMP_LEN         (32 * 1024)
7803
7804 static int tg3_get_regs_len(struct net_device *dev)
7805 {
7806         return TG3_REGDUMP_LEN;
7807 }
7808
7809 static void tg3_get_regs(struct net_device *dev,
7810                 struct ethtool_regs *regs, void *_p)
7811 {
7812         u32 *p = _p;
7813         struct tg3 *tp = netdev_priv(dev);
7814         u8 *orig_p = _p;
7815         int i;
7816
7817         regs->version = 0;
7818
7819         memset(p, 0, TG3_REGDUMP_LEN);
7820
7821         if (tp->link_config.phy_is_low_power)
7822                 return;
7823
7824         tg3_full_lock(tp, 0);
7825
7826 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7827 #define GET_REG32_LOOP(base,len)                \
7828 do {    p = (u32 *)(orig_p + (base));           \
7829         for (i = 0; i < len; i += 4)            \
7830                 __GET_REG32((base) + i);        \
7831 } while (0)
7832 #define GET_REG32_1(reg)                        \
7833 do {    p = (u32 *)(orig_p + (reg));            \
7834         __GET_REG32((reg));                     \
7835 } while (0)
7836
7837         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7838         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7839         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7840         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7841         GET_REG32_1(SNDDATAC_MODE);
7842         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7843         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7844         GET_REG32_1(SNDBDC_MODE);
7845         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7846         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7847         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7848         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7849         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7850         GET_REG32_1(RCVDCC_MODE);
7851         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7852         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7853         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7854         GET_REG32_1(MBFREE_MODE);
7855         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7856         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7857         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7858         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7859         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7860         GET_REG32_1(RX_CPU_MODE);
7861         GET_REG32_1(RX_CPU_STATE);
7862         GET_REG32_1(RX_CPU_PGMCTR);
7863         GET_REG32_1(RX_CPU_HWBKPT);
7864         GET_REG32_1(TX_CPU_MODE);
7865         GET_REG32_1(TX_CPU_STATE);
7866         GET_REG32_1(TX_CPU_PGMCTR);
7867         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7868         GET_REG32_LOOP(FTQ_RESET, 0x120);
7869         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7870         GET_REG32_1(DMAC_MODE);
7871         GET_REG32_LOOP(GRC_MODE, 0x4c);
7872         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7873                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7874
7875 #undef __GET_REG32
7876 #undef GET_REG32_LOOP
7877 #undef GET_REG32_1
7878
7879         tg3_full_unlock(tp);
7880 }
7881
7882 static int tg3_get_eeprom_len(struct net_device *dev)
7883 {
7884         struct tg3 *tp = netdev_priv(dev);
7885
7886         return tp->nvram_size;
7887 }
7888
7889 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7890 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7891
7892 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7893 {
7894         struct tg3 *tp = netdev_priv(dev);
7895         int ret;
7896         u8  *pd;
7897         u32 i, offset, len, val, b_offset, b_count;
7898
7899         if (tp->link_config.phy_is_low_power)
7900                 return -EAGAIN;
7901
7902         offset = eeprom->offset;
7903         len = eeprom->len;
7904         eeprom->len = 0;
7905
7906         eeprom->magic = TG3_EEPROM_MAGIC;
7907
7908         if (offset & 3) {
7909                 /* adjustments to start on required 4 byte boundary */
7910                 b_offset = offset & 3;
7911                 b_count = 4 - b_offset;
7912                 if (b_count > len) {
7913                         /* i.e. offset=1 len=2 */
7914                         b_count = len;
7915                 }
7916                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7917                 if (ret)
7918                         return ret;
7919                 val = cpu_to_le32(val);
7920                 memcpy(data, ((char*)&val) + b_offset, b_count);
7921                 len -= b_count;
7922                 offset += b_count;
7923                 eeprom->len += b_count;
7924         }
7925
7926         /* read bytes upto the last 4 byte boundary */
7927         pd = &data[eeprom->len];
7928         for (i = 0; i < (len - (len & 3)); i += 4) {
7929                 ret = tg3_nvram_read(tp, offset + i, &val);
7930                 if (ret) {
7931                         eeprom->len += i;
7932                         return ret;
7933                 }
7934                 val = cpu_to_le32(val);
7935                 memcpy(pd + i, &val, 4);
7936         }
7937         eeprom->len += i;
7938
7939         if (len & 3) {
7940                 /* read last bytes not ending on 4 byte boundary */
7941                 pd = &data[eeprom->len];
7942                 b_count = len & 3;
7943                 b_offset = offset + len - b_count;
7944                 ret = tg3_nvram_read(tp, b_offset, &val);
7945                 if (ret)
7946                         return ret;
7947                 val = cpu_to_le32(val);
7948                 memcpy(pd, ((char*)&val), b_count);
7949                 eeprom->len += b_count;
7950         }
7951         return 0;
7952 }
7953
7954 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7955
7956 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7957 {
7958         struct tg3 *tp = netdev_priv(dev);
7959         int ret;
7960         u32 offset, len, b_offset, odd_len, start, end;
7961         u8 *buf;
7962
7963         if (tp->link_config.phy_is_low_power)
7964                 return -EAGAIN;
7965
7966         if (eeprom->magic != TG3_EEPROM_MAGIC)
7967                 return -EINVAL;
7968
7969         offset = eeprom->offset;
7970         len = eeprom->len;
7971
7972         if ((b_offset = (offset & 3))) {
7973                 /* adjustments to start on required 4 byte boundary */
7974                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7975                 if (ret)
7976                         return ret;
7977                 start = cpu_to_le32(start);
7978                 len += b_offset;
7979                 offset &= ~3;
7980                 if (len < 4)
7981                         len = 4;
7982         }
7983
7984         odd_len = 0;
7985         if (len & 3) {
7986                 /* adjustments to end on required 4 byte boundary */
7987                 odd_len = 1;
7988                 len = (len + 3) & ~3;
7989                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7990                 if (ret)
7991                         return ret;
7992                 end = cpu_to_le32(end);
7993         }
7994
7995         buf = data;
7996         if (b_offset || odd_len) {
7997                 buf = kmalloc(len, GFP_KERNEL);
7998                 if (buf == 0)
7999                         return -ENOMEM;
8000                 if (b_offset)
8001                         memcpy(buf, &start, 4);
8002                 if (odd_len)
8003                         memcpy(buf+len-4, &end, 4);
8004                 memcpy(buf + b_offset, data, eeprom->len);
8005         }
8006
8007         ret = tg3_nvram_write_block(tp, offset, len, buf);
8008
8009         if (buf != data)
8010                 kfree(buf);
8011
8012         return ret;
8013 }
8014
8015 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8016 {
8017         struct tg3 *tp = netdev_priv(dev);
8018
8019         cmd->supported = (SUPPORTED_Autoneg);
8020
8021         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8022                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8023                                    SUPPORTED_1000baseT_Full);
8024
8025         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8026                 cmd->supported |= (SUPPORTED_100baseT_Half |
8027                                   SUPPORTED_100baseT_Full |
8028                                   SUPPORTED_10baseT_Half |
8029                                   SUPPORTED_10baseT_Full |
8030                                   SUPPORTED_MII);
8031                 cmd->port = PORT_TP;
8032         } else {
8033                 cmd->supported |= SUPPORTED_FIBRE;
8034                 cmd->port = PORT_FIBRE;
8035         }
8036
8037         cmd->advertising = tp->link_config.advertising;
8038         if (netif_running(dev)) {
8039                 cmd->speed = tp->link_config.active_speed;
8040                 cmd->duplex = tp->link_config.active_duplex;
8041         }
8042         cmd->phy_address = PHY_ADDR;
8043         cmd->transceiver = 0;
8044         cmd->autoneg = tp->link_config.autoneg;
8045         cmd->maxtxpkt = 0;
8046         cmd->maxrxpkt = 0;
8047         return 0;
8048 }
8049
8050 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8051 {
8052         struct tg3 *tp = netdev_priv(dev);
8053
8054         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8055                 /* These are the only valid advertisement bits allowed.  */
8056                 if (cmd->autoneg == AUTONEG_ENABLE &&
8057                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8058                                           ADVERTISED_1000baseT_Full |
8059                                           ADVERTISED_Autoneg |
8060                                           ADVERTISED_FIBRE)))
8061                         return -EINVAL;
8062                 /* Fiber can only do SPEED_1000.  */
8063                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8064                          (cmd->speed != SPEED_1000))
8065                         return -EINVAL;
8066         /* Copper cannot force SPEED_1000.  */
8067         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8068                    (cmd->speed == SPEED_1000))
8069                 return -EINVAL;
8070         else if ((cmd->speed == SPEED_1000) &&
8071                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8072                 return -EINVAL;
8073
8074         tg3_full_lock(tp, 0);
8075
8076         tp->link_config.autoneg = cmd->autoneg;
8077         if (cmd->autoneg == AUTONEG_ENABLE) {
8078                 tp->link_config.advertising = cmd->advertising;
8079                 tp->link_config.speed = SPEED_INVALID;
8080                 tp->link_config.duplex = DUPLEX_INVALID;
8081         } else {
8082                 tp->link_config.advertising = 0;
8083                 tp->link_config.speed = cmd->speed;
8084                 tp->link_config.duplex = cmd->duplex;
8085         }
8086
8087         tp->link_config.orig_speed = tp->link_config.speed;
8088         tp->link_config.orig_duplex = tp->link_config.duplex;
8089         tp->link_config.orig_autoneg = tp->link_config.autoneg;
8090
8091         if (netif_running(dev))
8092                 tg3_setup_phy(tp, 1);
8093
8094         tg3_full_unlock(tp);
8095
8096         return 0;
8097 }
8098
8099 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8100 {
8101         struct tg3 *tp = netdev_priv(dev);
8102
8103         strcpy(info->driver, DRV_MODULE_NAME);
8104         strcpy(info->version, DRV_MODULE_VERSION);
8105         strcpy(info->fw_version, tp->fw_ver);
8106         strcpy(info->bus_info, pci_name(tp->pdev));
8107 }
8108
8109 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8110 {
8111         struct tg3 *tp = netdev_priv(dev);
8112
8113         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8114                 wol->supported = WAKE_MAGIC;
8115         else
8116                 wol->supported = 0;
8117         wol->wolopts = 0;
8118         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8119                 wol->wolopts = WAKE_MAGIC;
8120         memset(&wol->sopass, 0, sizeof(wol->sopass));
8121 }
8122
8123 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8124 {
8125         struct tg3 *tp = netdev_priv(dev);
8126
8127         if (wol->wolopts & ~WAKE_MAGIC)
8128                 return -EINVAL;
8129         if ((wol->wolopts & WAKE_MAGIC) &&
8130             !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8131                 return -EINVAL;
8132
8133         spin_lock_bh(&tp->lock);
8134         if (wol->wolopts & WAKE_MAGIC)
8135                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8136         else
8137                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8138         spin_unlock_bh(&tp->lock);
8139
8140         return 0;
8141 }
8142
8143 static u32 tg3_get_msglevel(struct net_device *dev)
8144 {
8145         struct tg3 *tp = netdev_priv(dev);
8146         return tp->msg_enable;
8147 }
8148
8149 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8150 {
8151         struct tg3 *tp = netdev_priv(dev);
8152         tp->msg_enable = value;
8153 }
8154
8155 static int tg3_set_tso(struct net_device *dev, u32 value)
8156 {
8157         struct tg3 *tp = netdev_priv(dev);
8158
8159         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8160                 if (value)
8161                         return -EINVAL;
8162                 return 0;
8163         }
8164         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8165             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8166                 if (value)
8167                         dev->features |= NETIF_F_TSO6;
8168                 else
8169                         dev->features &= ~NETIF_F_TSO6;
8170         }
8171         return ethtool_op_set_tso(dev, value);
8172 }
8173
8174 static int tg3_nway_reset(struct net_device *dev)
8175 {
8176         struct tg3 *tp = netdev_priv(dev);
8177         u32 bmcr;
8178         int r;
8179
8180         if (!netif_running(dev))
8181                 return -EAGAIN;
8182
8183         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8184                 return -EINVAL;
8185
8186         spin_lock_bh(&tp->lock);
8187         r = -EINVAL;
8188         tg3_readphy(tp, MII_BMCR, &bmcr);
8189         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8190             ((bmcr & BMCR_ANENABLE) ||
8191              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8192                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8193                                            BMCR_ANENABLE);
8194                 r = 0;
8195         }
8196         spin_unlock_bh(&tp->lock);
8197
8198         return r;
8199 }
8200
8201 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8202 {
8203         struct tg3 *tp = netdev_priv(dev);
8204
8205         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8206         ering->rx_mini_max_pending = 0;
8207         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8208                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8209         else
8210                 ering->rx_jumbo_max_pending = 0;
8211
8212         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8213
8214         ering->rx_pending = tp->rx_pending;
8215         ering->rx_mini_pending = 0;
8216         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8217                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8218         else
8219                 ering->rx_jumbo_pending = 0;
8220
8221         ering->tx_pending = tp->tx_pending;
8222 }
8223
8224 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8225 {
8226         struct tg3 *tp = netdev_priv(dev);
8227         int irq_sync = 0, err = 0;
8228
8229         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8230             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8231             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8232             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8233             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8234              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8235                 return -EINVAL;
8236
8237         if (netif_running(dev)) {
8238                 tg3_netif_stop(tp);
8239                 irq_sync = 1;
8240         }
8241
8242         tg3_full_lock(tp, irq_sync);
8243
8244         tp->rx_pending = ering->rx_pending;
8245
8246         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8247             tp->rx_pending > 63)
8248                 tp->rx_pending = 63;
8249         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8250         tp->tx_pending = ering->tx_pending;
8251
8252         if (netif_running(dev)) {
8253                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8254                 err = tg3_restart_hw(tp, 1);
8255                 if (!err)
8256                         tg3_netif_start(tp);
8257         }
8258
8259         tg3_full_unlock(tp);
8260
8261         return err;
8262 }
8263
8264 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8265 {
8266         struct tg3 *tp = netdev_priv(dev);
8267
8268         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8269         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8270         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8271 }
8272
8273 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8274 {
8275         struct tg3 *tp = netdev_priv(dev);
8276         int irq_sync = 0, err = 0;
8277
8278         if (netif_running(dev)) {
8279                 tg3_netif_stop(tp);
8280                 irq_sync = 1;
8281         }
8282
8283         tg3_full_lock(tp, irq_sync);
8284
8285         if (epause->autoneg)
8286                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8287         else
8288                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8289         if (epause->rx_pause)
8290                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8291         else
8292                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8293         if (epause->tx_pause)
8294                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8295         else
8296                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8297
8298         if (netif_running(dev)) {
8299                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8300                 err = tg3_restart_hw(tp, 1);
8301                 if (!err)
8302                         tg3_netif_start(tp);
8303         }
8304
8305         tg3_full_unlock(tp);
8306
8307         return err;
8308 }
8309
8310 static u32 tg3_get_rx_csum(struct net_device *dev)
8311 {
8312         struct tg3 *tp = netdev_priv(dev);
8313         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8314 }
8315
8316 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8317 {
8318         struct tg3 *tp = netdev_priv(dev);
8319
8320         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8321                 if (data != 0)
8322                         return -EINVAL;
8323                 return 0;
8324         }
8325
8326         spin_lock_bh(&tp->lock);
8327         if (data)
8328                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8329         else
8330                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8331         spin_unlock_bh(&tp->lock);
8332
8333         return 0;
8334 }
8335
8336 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8337 {
8338         struct tg3 *tp = netdev_priv(dev);
8339
8340         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8341                 if (data != 0)
8342                         return -EINVAL;
8343                 return 0;
8344         }
8345
8346         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8347             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8348                 ethtool_op_set_tx_ipv6_csum(dev, data);
8349         else
8350                 ethtool_op_set_tx_csum(dev, data);
8351
8352         return 0;
8353 }
8354
8355 static int tg3_get_stats_count (struct net_device *dev)
8356 {
8357         return TG3_NUM_STATS;
8358 }
8359
8360 static int tg3_get_test_count (struct net_device *dev)
8361 {
8362         return TG3_NUM_TEST;
8363 }
8364
8365 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8366 {
8367         switch (stringset) {
8368         case ETH_SS_STATS:
8369                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8370                 break;
8371         case ETH_SS_TEST:
8372                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8373                 break;
8374         default:
8375                 WARN_ON(1);     /* we need a WARN() */
8376                 break;
8377         }
8378 }
8379
8380 static int tg3_phys_id(struct net_device *dev, u32 data)
8381 {
8382         struct tg3 *tp = netdev_priv(dev);
8383         int i;
8384
8385         if (!netif_running(tp->dev))
8386                 return -EAGAIN;
8387
8388         if (data == 0)
8389                 data = 2;
8390
8391         for (i = 0; i < (data * 2); i++) {
8392                 if ((i % 2) == 0)
8393                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8394                                            LED_CTRL_1000MBPS_ON |
8395                                            LED_CTRL_100MBPS_ON |
8396                                            LED_CTRL_10MBPS_ON |
8397                                            LED_CTRL_TRAFFIC_OVERRIDE |
8398                                            LED_CTRL_TRAFFIC_BLINK |
8399                                            LED_CTRL_TRAFFIC_LED);
8400
8401                 else
8402                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8403                                            LED_CTRL_TRAFFIC_OVERRIDE);
8404
8405                 if (msleep_interruptible(500))
8406                         break;
8407         }
8408         tw32(MAC_LED_CTRL, tp->led_ctrl);
8409         return 0;
8410 }
8411
8412 static void tg3_get_ethtool_stats (struct net_device *dev,
8413                                    struct ethtool_stats *estats, u64 *tmp_stats)
8414 {
8415         struct tg3 *tp = netdev_priv(dev);
8416         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8417 }
8418
8419 #define NVRAM_TEST_SIZE 0x100
8420 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8421 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8422 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8423
8424 static int tg3_test_nvram(struct tg3 *tp)
8425 {
8426         u32 *buf, csum, magic;
8427         int i, j, err = 0, size;
8428
8429         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8430                 return -EIO;
8431
8432         if (magic == TG3_EEPROM_MAGIC)
8433                 size = NVRAM_TEST_SIZE;
8434         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8435                 if ((magic & 0xe00000) == 0x200000)
8436                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8437                 else
8438                         return 0;
8439         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8440                 size = NVRAM_SELFBOOT_HW_SIZE;
8441         else
8442                 return -EIO;
8443
8444         buf = kmalloc(size, GFP_KERNEL);
8445         if (buf == NULL)
8446                 return -ENOMEM;
8447
8448         err = -EIO;
8449         for (i = 0, j = 0; i < size; i += 4, j++) {
8450                 u32 val;
8451
8452                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8453                         break;
8454                 buf[j] = cpu_to_le32(val);
8455         }
8456         if (i < size)
8457                 goto out;
8458
8459         /* Selfboot format */
8460         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8461             TG3_EEPROM_MAGIC_FW) {
8462                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8463
8464                 for (i = 0; i < size; i++)
8465                         csum8 += buf8[i];
8466
8467                 if (csum8 == 0) {
8468                         err = 0;
8469                         goto out;
8470                 }
8471
8472                 err = -EIO;
8473                 goto out;
8474         }
8475
8476         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8477             TG3_EEPROM_MAGIC_HW) {
8478                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8479                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8480                 u8 *buf8 = (u8 *) buf;
8481                 int j, k;
8482
8483                 /* Separate the parity bits and the data bytes.  */
8484                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8485                         if ((i == 0) || (i == 8)) {
8486                                 int l;
8487                                 u8 msk;
8488
8489                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8490                                         parity[k++] = buf8[i] & msk;
8491                                 i++;
8492                         }
8493                         else if (i == 16) {
8494                                 int l;
8495                                 u8 msk;
8496
8497                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8498                                         parity[k++] = buf8[i] & msk;
8499                                 i++;
8500
8501                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8502                                         parity[k++] = buf8[i] & msk;
8503                                 i++;
8504                         }
8505                         data[j++] = buf8[i];
8506                 }
8507
8508                 err = -EIO;
8509                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8510                         u8 hw8 = hweight8(data[i]);
8511
8512                         if ((hw8 & 0x1) && parity[i])
8513                                 goto out;
8514                         else if (!(hw8 & 0x1) && !parity[i])
8515                                 goto out;
8516                 }
8517                 err = 0;
8518                 goto out;
8519         }
8520
8521         /* Bootstrap checksum at offset 0x10 */
8522         csum = calc_crc((unsigned char *) buf, 0x10);
8523         if(csum != cpu_to_le32(buf[0x10/4]))
8524                 goto out;
8525
8526         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8527         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8528         if (csum != cpu_to_le32(buf[0xfc/4]))
8529                  goto out;
8530
8531         err = 0;
8532
8533 out:
8534         kfree(buf);
8535         return err;
8536 }
8537
8538 #define TG3_SERDES_TIMEOUT_SEC  2
8539 #define TG3_COPPER_TIMEOUT_SEC  6
8540
8541 static int tg3_test_link(struct tg3 *tp)
8542 {
8543         int i, max;
8544
8545         if (!netif_running(tp->dev))
8546                 return -ENODEV;
8547
8548         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8549                 max = TG3_SERDES_TIMEOUT_SEC;
8550         else
8551                 max = TG3_COPPER_TIMEOUT_SEC;
8552
8553         for (i = 0; i < max; i++) {
8554                 if (netif_carrier_ok(tp->dev))
8555                         return 0;
8556
8557                 if (msleep_interruptible(1000))
8558                         break;
8559         }
8560
8561         return -EIO;
8562 }
8563
8564 /* Only test the commonly used registers */
8565 static int tg3_test_registers(struct tg3 *tp)
8566 {
8567         int i, is_5705, is_5750;
8568         u32 offset, read_mask, write_mask, val, save_val, read_val;
8569         static struct {
8570                 u16 offset;
8571                 u16 flags;
8572 #define TG3_FL_5705     0x1
8573 #define TG3_FL_NOT_5705 0x2
8574 #define TG3_FL_NOT_5788 0x4
8575 #define TG3_FL_NOT_5750 0x8
8576                 u32 read_mask;
8577                 u32 write_mask;
8578         } reg_tbl[] = {
8579                 /* MAC Control Registers */
8580                 { MAC_MODE, TG3_FL_NOT_5705,
8581                         0x00000000, 0x00ef6f8c },
8582                 { MAC_MODE, TG3_FL_5705,
8583                         0x00000000, 0x01ef6b8c },
8584                 { MAC_STATUS, TG3_FL_NOT_5705,
8585                         0x03800107, 0x00000000 },
8586                 { MAC_STATUS, TG3_FL_5705,
8587                         0x03800100, 0x00000000 },
8588                 { MAC_ADDR_0_HIGH, 0x0000,
8589                         0x00000000, 0x0000ffff },
8590                 { MAC_ADDR_0_LOW, 0x0000,
8591                         0x00000000, 0xffffffff },
8592                 { MAC_RX_MTU_SIZE, 0x0000,
8593                         0x00000000, 0x0000ffff },
8594                 { MAC_TX_MODE, 0x0000,
8595                         0x00000000, 0x00000070 },
8596                 { MAC_TX_LENGTHS, 0x0000,
8597                         0x00000000, 0x00003fff },
8598                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8599                         0x00000000, 0x000007fc },
8600                 { MAC_RX_MODE, TG3_FL_5705,
8601                         0x00000000, 0x000007dc },
8602                 { MAC_HASH_REG_0, 0x0000,
8603                         0x00000000, 0xffffffff },
8604                 { MAC_HASH_REG_1, 0x0000,
8605                         0x00000000, 0xffffffff },
8606                 { MAC_HASH_REG_2, 0x0000,
8607                         0x00000000, 0xffffffff },
8608                 { MAC_HASH_REG_3, 0x0000,
8609                         0x00000000, 0xffffffff },
8610
8611                 /* Receive Data and Receive BD Initiator Control Registers. */
8612                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8613                         0x00000000, 0xffffffff },
8614                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8615                         0x00000000, 0xffffffff },
8616                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8617                         0x00000000, 0x00000003 },
8618                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8619                         0x00000000, 0xffffffff },
8620                 { RCVDBDI_STD_BD+0, 0x0000,
8621                         0x00000000, 0xffffffff },
8622                 { RCVDBDI_STD_BD+4, 0x0000,
8623                         0x00000000, 0xffffffff },
8624                 { RCVDBDI_STD_BD+8, 0x0000,
8625                         0x00000000, 0xffff0002 },
8626                 { RCVDBDI_STD_BD+0xc, 0x0000,
8627                         0x00000000, 0xffffffff },
8628
8629                 /* Receive BD Initiator Control Registers. */
8630                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8631                         0x00000000, 0xffffffff },
8632                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8633                         0x00000000, 0x000003ff },
8634                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8635                         0x00000000, 0xffffffff },
8636
8637                 /* Host Coalescing Control Registers. */
8638                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8639                         0x00000000, 0x00000004 },
8640                 { HOSTCC_MODE, TG3_FL_5705,
8641                         0x00000000, 0x000000f6 },
8642                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8643                         0x00000000, 0xffffffff },
8644                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8645                         0x00000000, 0x000003ff },
8646                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8647                         0x00000000, 0xffffffff },
8648                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8649                         0x00000000, 0x000003ff },
8650                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8651                         0x00000000, 0xffffffff },
8652                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8653                         0x00000000, 0x000000ff },
8654                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8655                         0x00000000, 0xffffffff },
8656                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8657                         0x00000000, 0x000000ff },
8658                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8659                         0x00000000, 0xffffffff },
8660                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8661                         0x00000000, 0xffffffff },
8662                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8663                         0x00000000, 0xffffffff },
8664                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8665                         0x00000000, 0x000000ff },
8666                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8667                         0x00000000, 0xffffffff },
8668                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8669                         0x00000000, 0x000000ff },
8670                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8671                         0x00000000, 0xffffffff },
8672                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8673                         0x00000000, 0xffffffff },
8674                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8675                         0x00000000, 0xffffffff },
8676                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8677                         0x00000000, 0xffffffff },
8678                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8679                         0x00000000, 0xffffffff },
8680                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8681                         0xffffffff, 0x00000000 },
8682                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8683                         0xffffffff, 0x00000000 },
8684
8685                 /* Buffer Manager Control Registers. */
8686                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8687                         0x00000000, 0x007fff80 },
8688                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8689                         0x00000000, 0x007fffff },
8690                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8691                         0x00000000, 0x0000003f },
8692                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8693                         0x00000000, 0x000001ff },
8694                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8695                         0x00000000, 0x000001ff },
8696                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8697                         0xffffffff, 0x00000000 },
8698                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8699                         0xffffffff, 0x00000000 },
8700
8701                 /* Mailbox Registers */
8702                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8703                         0x00000000, 0x000001ff },
8704                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8705                         0x00000000, 0x000001ff },
8706                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8707                         0x00000000, 0x000007ff },
8708                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8709                         0x00000000, 0x000001ff },
8710
8711                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8712         };
8713
8714         is_5705 = is_5750 = 0;
8715         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8716                 is_5705 = 1;
8717                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8718                         is_5750 = 1;
8719         }
8720
8721         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8722                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8723                         continue;
8724
8725                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8726                         continue;
8727
8728                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8729                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8730                         continue;
8731
8732                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8733                         continue;
8734
8735                 offset = (u32) reg_tbl[i].offset;
8736                 read_mask = reg_tbl[i].read_mask;
8737                 write_mask = reg_tbl[i].write_mask;
8738
8739                 /* Save the original register content */
8740                 save_val = tr32(offset);
8741
8742                 /* Determine the read-only value. */
8743                 read_val = save_val & read_mask;
8744
8745                 /* Write zero to the register, then make sure the read-only bits
8746                  * are not changed and the read/write bits are all zeros.
8747                  */
8748                 tw32(offset, 0);
8749
8750                 val = tr32(offset);
8751
8752                 /* Test the read-only and read/write bits. */
8753                 if (((val & read_mask) != read_val) || (val & write_mask))
8754                         goto out;
8755
8756                 /* Write ones to all the bits defined by RdMask and WrMask, then
8757                  * make sure the read-only bits are not changed and the
8758                  * read/write bits are all ones.
8759                  */
8760                 tw32(offset, read_mask | write_mask);
8761
8762                 val = tr32(offset);
8763
8764                 /* Test the read-only bits. */
8765                 if ((val & read_mask) != read_val)
8766                         goto out;
8767
8768                 /* Test the read/write bits. */
8769                 if ((val & write_mask) != write_mask)
8770                         goto out;
8771
8772                 tw32(offset, save_val);
8773         }
8774
8775         return 0;
8776
8777 out:
8778         if (netif_msg_hw(tp))
8779                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8780                        offset);
8781         tw32(offset, save_val);
8782         return -EIO;
8783 }
8784
8785 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8786 {
8787         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8788         int i;
8789         u32 j;
8790
8791         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8792                 for (j = 0; j < len; j += 4) {
8793                         u32 val;
8794
8795                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8796                         tg3_read_mem(tp, offset + j, &val);
8797                         if (val != test_pattern[i])
8798                                 return -EIO;
8799                 }
8800         }
8801         return 0;
8802 }
8803
8804 static int tg3_test_memory(struct tg3 *tp)
8805 {
8806         static struct mem_entry {
8807                 u32 offset;
8808                 u32 len;
8809         } mem_tbl_570x[] = {
8810                 { 0x00000000, 0x00b50},
8811                 { 0x00002000, 0x1c000},
8812                 { 0xffffffff, 0x00000}
8813         }, mem_tbl_5705[] = {
8814                 { 0x00000100, 0x0000c},
8815                 { 0x00000200, 0x00008},
8816                 { 0x00004000, 0x00800},
8817                 { 0x00006000, 0x01000},
8818                 { 0x00008000, 0x02000},
8819                 { 0x00010000, 0x0e000},
8820                 { 0xffffffff, 0x00000}
8821         }, mem_tbl_5755[] = {
8822                 { 0x00000200, 0x00008},
8823                 { 0x00004000, 0x00800},
8824                 { 0x00006000, 0x00800},
8825                 { 0x00008000, 0x02000},
8826                 { 0x00010000, 0x0c000},
8827                 { 0xffffffff, 0x00000}
8828         }, mem_tbl_5906[] = {
8829                 { 0x00000200, 0x00008},
8830                 { 0x00004000, 0x00400},
8831                 { 0x00006000, 0x00400},
8832                 { 0x00008000, 0x01000},
8833                 { 0x00010000, 0x01000},
8834                 { 0xffffffff, 0x00000}
8835         };
8836         struct mem_entry *mem_tbl;
8837         int err = 0;
8838         int i;
8839
8840         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8841                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8842                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8843                         mem_tbl = mem_tbl_5755;
8844                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8845                         mem_tbl = mem_tbl_5906;
8846                 else
8847                         mem_tbl = mem_tbl_5705;
8848         } else
8849                 mem_tbl = mem_tbl_570x;
8850
8851         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8852                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8853                     mem_tbl[i].len)) != 0)
8854                         break;
8855         }
8856
8857         return err;
8858 }
8859
8860 #define TG3_MAC_LOOPBACK        0
8861 #define TG3_PHY_LOOPBACK        1
8862
8863 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8864 {
8865         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8866         u32 desc_idx;
8867         struct sk_buff *skb, *rx_skb;
8868         u8 *tx_data;
8869         dma_addr_t map;
8870         int num_pkts, tx_len, rx_len, i, err;
8871         struct tg3_rx_buffer_desc *desc;
8872
8873         if (loopback_mode == TG3_MAC_LOOPBACK) {
8874                 /* HW errata - mac loopback fails in some cases on 5780.
8875                  * Normal traffic and PHY loopback are not affected by
8876                  * errata.
8877                  */
8878                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8879                         return 0;
8880
8881                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8882                            MAC_MODE_PORT_INT_LPBACK;
8883                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8884                         mac_mode |= MAC_MODE_LINK_POLARITY;
8885                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8886                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8887                 else
8888                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8889                 tw32(MAC_MODE, mac_mode);
8890         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8891                 u32 val;
8892
8893                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8894                         u32 phytest;
8895
8896                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8897                                 u32 phy;
8898
8899                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8900                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8901                                 if (!tg3_readphy(tp, 0x1b, &phy))
8902                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8903                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8904                         }
8905                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8906                 } else
8907                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8908
8909                 tg3_phy_toggle_automdix(tp, 0);
8910
8911                 tg3_writephy(tp, MII_BMCR, val);
8912                 udelay(40);
8913
8914                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
8915                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8916                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8917                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8918                 } else
8919                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8920
8921                 /* reset to prevent losing 1st rx packet intermittently */
8922                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8923                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8924                         udelay(10);
8925                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8926                 }
8927                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
8928                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8929                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8930                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
8931                                 mac_mode |= MAC_MODE_LINK_POLARITY;
8932                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8933                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8934                 }
8935                 tw32(MAC_MODE, mac_mode);
8936         }
8937         else
8938                 return -EINVAL;
8939
8940         err = -EIO;
8941
8942         tx_len = 1514;
8943         skb = netdev_alloc_skb(tp->dev, tx_len);
8944         if (!skb)
8945                 return -ENOMEM;
8946
8947         tx_data = skb_put(skb, tx_len);
8948         memcpy(tx_data, tp->dev->dev_addr, 6);
8949         memset(tx_data + 6, 0x0, 8);
8950
8951         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8952
8953         for (i = 14; i < tx_len; i++)
8954                 tx_data[i] = (u8) (i & 0xff);
8955
8956         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8957
8958         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8959              HOSTCC_MODE_NOW);
8960
8961         udelay(10);
8962
8963         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8964
8965         num_pkts = 0;
8966
8967         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8968
8969         tp->tx_prod++;
8970         num_pkts++;
8971
8972         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8973                      tp->tx_prod);
8974         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8975
8976         udelay(10);
8977
8978         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8979         for (i = 0; i < 25; i++) {
8980                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8981                        HOSTCC_MODE_NOW);
8982
8983                 udelay(10);
8984
8985                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8986                 rx_idx = tp->hw_status->idx[0].rx_producer;
8987                 if ((tx_idx == tp->tx_prod) &&
8988                     (rx_idx == (rx_start_idx + num_pkts)))
8989                         break;
8990         }
8991
8992         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8993         dev_kfree_skb(skb);
8994
8995         if (tx_idx != tp->tx_prod)
8996                 goto out;
8997
8998         if (rx_idx != rx_start_idx + num_pkts)
8999                 goto out;
9000
9001         desc = &tp->rx_rcb[rx_start_idx];
9002         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
9003         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
9004         if (opaque_key != RXD_OPAQUE_RING_STD)
9005                 goto out;
9006
9007         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
9008             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
9009                 goto out;
9010
9011         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
9012         if (rx_len != tx_len)
9013                 goto out;
9014
9015         rx_skb = tp->rx_std_buffers[desc_idx].skb;
9016
9017         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
9018         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
9019
9020         for (i = 14; i < tx_len; i++) {
9021                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
9022                         goto out;
9023         }
9024         err = 0;
9025
9026         /* tg3_free_rings will unmap and free the rx_skb */
9027 out:
9028         return err;
9029 }
9030
9031 #define TG3_MAC_LOOPBACK_FAILED         1
9032 #define TG3_PHY_LOOPBACK_FAILED         2
9033 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
9034                                          TG3_PHY_LOOPBACK_FAILED)
9035
9036 static int tg3_test_loopback(struct tg3 *tp)
9037 {
9038         int err = 0;
9039
9040         if (!netif_running(tp->dev))
9041                 return TG3_LOOPBACK_FAILED;
9042
9043         err = tg3_reset_hw(tp, 1);
9044         if (err)
9045                 return TG3_LOOPBACK_FAILED;
9046
9047         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9048                 err |= TG3_MAC_LOOPBACK_FAILED;
9049         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9050                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9051                         err |= TG3_PHY_LOOPBACK_FAILED;
9052         }
9053
9054         return err;
9055 }
9056
9057 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9058                           u64 *data)
9059 {
9060         struct tg3 *tp = netdev_priv(dev);
9061
9062         if (tp->link_config.phy_is_low_power)
9063                 tg3_set_power_state(tp, PCI_D0);
9064
9065         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9066
9067         if (tg3_test_nvram(tp) != 0) {
9068                 etest->flags |= ETH_TEST_FL_FAILED;
9069                 data[0] = 1;
9070         }
9071         if (tg3_test_link(tp) != 0) {
9072                 etest->flags |= ETH_TEST_FL_FAILED;
9073                 data[1] = 1;
9074         }
9075         if (etest->flags & ETH_TEST_FL_OFFLINE) {
9076                 int err, irq_sync = 0;
9077
9078                 if (netif_running(dev)) {
9079                         tg3_netif_stop(tp);
9080                         irq_sync = 1;
9081                 }
9082
9083                 tg3_full_lock(tp, irq_sync);
9084
9085                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9086                 err = tg3_nvram_lock(tp);
9087                 tg3_halt_cpu(tp, RX_CPU_BASE);
9088                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9089                         tg3_halt_cpu(tp, TX_CPU_BASE);
9090                 if (!err)
9091                         tg3_nvram_unlock(tp);
9092
9093                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9094                         tg3_phy_reset(tp);
9095
9096                 if (tg3_test_registers(tp) != 0) {
9097                         etest->flags |= ETH_TEST_FL_FAILED;
9098                         data[2] = 1;
9099                 }
9100                 if (tg3_test_memory(tp) != 0) {
9101                         etest->flags |= ETH_TEST_FL_FAILED;
9102                         data[3] = 1;
9103                 }
9104                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9105                         etest->flags |= ETH_TEST_FL_FAILED;
9106
9107                 tg3_full_unlock(tp);
9108
9109                 if (tg3_test_interrupt(tp) != 0) {
9110                         etest->flags |= ETH_TEST_FL_FAILED;
9111                         data[5] = 1;
9112                 }
9113
9114                 tg3_full_lock(tp, 0);
9115
9116                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9117                 if (netif_running(dev)) {
9118                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9119                         if (!tg3_restart_hw(tp, 1))
9120                                 tg3_netif_start(tp);
9121                 }
9122
9123                 tg3_full_unlock(tp);
9124         }
9125         if (tp->link_config.phy_is_low_power)
9126                 tg3_set_power_state(tp, PCI_D3hot);
9127
9128 }
9129
9130 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9131 {
9132         struct mii_ioctl_data *data = if_mii(ifr);
9133         struct tg3 *tp = netdev_priv(dev);
9134         int err;
9135
9136         switch(cmd) {
9137         case SIOCGMIIPHY:
9138                 data->phy_id = PHY_ADDR;
9139
9140                 /* fallthru */
9141         case SIOCGMIIREG: {
9142                 u32 mii_regval;
9143
9144                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9145                         break;                  /* We have no PHY */
9146
9147                 if (tp->link_config.phy_is_low_power)
9148                         return -EAGAIN;
9149
9150                 spin_lock_bh(&tp->lock);
9151                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9152                 spin_unlock_bh(&tp->lock);
9153
9154                 data->val_out = mii_regval;
9155
9156                 return err;
9157         }
9158
9159         case SIOCSMIIREG:
9160                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9161                         break;                  /* We have no PHY */
9162
9163                 if (!capable(CAP_NET_ADMIN))
9164                         return -EPERM;
9165
9166                 if (tp->link_config.phy_is_low_power)
9167                         return -EAGAIN;
9168
9169                 spin_lock_bh(&tp->lock);
9170                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9171                 spin_unlock_bh(&tp->lock);
9172
9173                 return err;
9174
9175         default:
9176                 /* do nothing */
9177                 break;
9178         }
9179         return -EOPNOTSUPP;
9180 }
9181
9182 #if TG3_VLAN_TAG_USED
9183 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9184 {
9185         struct tg3 *tp = netdev_priv(dev);
9186
9187         if (netif_running(dev))
9188                 tg3_netif_stop(tp);
9189
9190         tg3_full_lock(tp, 0);
9191
9192         tp->vlgrp = grp;
9193
9194         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9195         __tg3_set_rx_mode(dev);
9196
9197         if (netif_running(dev))
9198                 tg3_netif_start(tp);
9199
9200         tg3_full_unlock(tp);
9201 }
9202 #endif
9203
9204 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9205 {
9206         struct tg3 *tp = netdev_priv(dev);
9207
9208         memcpy(ec, &tp->coal, sizeof(*ec));
9209         return 0;
9210 }
9211
9212 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9213 {
9214         struct tg3 *tp = netdev_priv(dev);
9215         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9216         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9217
9218         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9219                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9220                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9221                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9222                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9223         }
9224
9225         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9226             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9227             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9228             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9229             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9230             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9231             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9232             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9233             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9234             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9235                 return -EINVAL;
9236
9237         /* No rx interrupts will be generated if both are zero */
9238         if ((ec->rx_coalesce_usecs == 0) &&
9239             (ec->rx_max_coalesced_frames == 0))
9240                 return -EINVAL;
9241
9242         /* No tx interrupts will be generated if both are zero */
9243         if ((ec->tx_coalesce_usecs == 0) &&
9244             (ec->tx_max_coalesced_frames == 0))
9245                 return -EINVAL;
9246
9247         /* Only copy relevant parameters, ignore all others. */
9248         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9249         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9250         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9251         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9252         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9253         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9254         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9255         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9256         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9257
9258         if (netif_running(dev)) {
9259                 tg3_full_lock(tp, 0);
9260                 __tg3_set_coalesce(tp, &tp->coal);
9261                 tg3_full_unlock(tp);
9262         }
9263         return 0;
9264 }
9265
9266 static const struct ethtool_ops tg3_ethtool_ops = {
9267         .get_settings           = tg3_get_settings,
9268         .set_settings           = tg3_set_settings,
9269         .get_drvinfo            = tg3_get_drvinfo,
9270         .get_regs_len           = tg3_get_regs_len,
9271         .get_regs               = tg3_get_regs,
9272         .get_wol                = tg3_get_wol,
9273         .set_wol                = tg3_set_wol,
9274         .get_msglevel           = tg3_get_msglevel,
9275         .set_msglevel           = tg3_set_msglevel,
9276         .nway_reset             = tg3_nway_reset,
9277         .get_link               = ethtool_op_get_link,
9278         .get_eeprom_len         = tg3_get_eeprom_len,
9279         .get_eeprom             = tg3_get_eeprom,
9280         .set_eeprom             = tg3_set_eeprom,
9281         .get_ringparam          = tg3_get_ringparam,
9282         .set_ringparam          = tg3_set_ringparam,
9283         .get_pauseparam         = tg3_get_pauseparam,
9284         .set_pauseparam         = tg3_set_pauseparam,
9285         .get_rx_csum            = tg3_get_rx_csum,
9286         .set_rx_csum            = tg3_set_rx_csum,
9287         .get_tx_csum            = ethtool_op_get_tx_csum,
9288         .set_tx_csum            = tg3_set_tx_csum,
9289         .get_sg                 = ethtool_op_get_sg,
9290         .set_sg                 = ethtool_op_set_sg,
9291         .get_tso                = ethtool_op_get_tso,
9292         .set_tso                = tg3_set_tso,
9293         .self_test_count        = tg3_get_test_count,
9294         .self_test              = tg3_self_test,
9295         .get_strings            = tg3_get_strings,
9296         .phys_id                = tg3_phys_id,
9297         .get_stats_count        = tg3_get_stats_count,
9298         .get_ethtool_stats      = tg3_get_ethtool_stats,
9299         .get_coalesce           = tg3_get_coalesce,
9300         .set_coalesce           = tg3_set_coalesce,
9301 };
9302
9303 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9304 {
9305         u32 cursize, val, magic;
9306
9307         tp->nvram_size = EEPROM_CHIP_SIZE;
9308
9309         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9310                 return;
9311
9312         if ((magic != TG3_EEPROM_MAGIC) &&
9313             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9314             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9315                 return;
9316
9317         /*
9318          * Size the chip by reading offsets at increasing powers of two.
9319          * When we encounter our validation signature, we know the addressing
9320          * has wrapped around, and thus have our chip size.
9321          */
9322         cursize = 0x10;
9323
9324         while (cursize < tp->nvram_size) {
9325                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9326                         return;
9327
9328                 if (val == magic)
9329                         break;
9330
9331                 cursize <<= 1;
9332         }
9333
9334         tp->nvram_size = cursize;
9335 }
9336
9337 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9338 {
9339         u32 val;
9340
9341         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9342                 return;
9343
9344         /* Selfboot format */
9345         if (val != TG3_EEPROM_MAGIC) {
9346                 tg3_get_eeprom_size(tp);
9347                 return;
9348         }
9349
9350         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9351                 if (val != 0) {
9352                         tp->nvram_size = (val >> 16) * 1024;
9353                         return;
9354                 }
9355         }
9356         tp->nvram_size = 0x80000;
9357 }
9358
9359 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9360 {
9361         u32 nvcfg1;
9362
9363         nvcfg1 = tr32(NVRAM_CFG1);
9364         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9365                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9366         }
9367         else {
9368                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9369                 tw32(NVRAM_CFG1, nvcfg1);
9370         }
9371
9372         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9373             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9374                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9375                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9376                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9377                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9378                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9379                                 break;
9380                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9381                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9382                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9383                                 break;
9384                         case FLASH_VENDOR_ATMEL_EEPROM:
9385                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9386                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9387                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9388                                 break;
9389                         case FLASH_VENDOR_ST:
9390                                 tp->nvram_jedecnum = JEDEC_ST;
9391                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9392                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9393                                 break;
9394                         case FLASH_VENDOR_SAIFUN:
9395                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9396                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9397                                 break;
9398                         case FLASH_VENDOR_SST_SMALL:
9399                         case FLASH_VENDOR_SST_LARGE:
9400                                 tp->nvram_jedecnum = JEDEC_SST;
9401                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9402                                 break;
9403                 }
9404         }
9405         else {
9406                 tp->nvram_jedecnum = JEDEC_ATMEL;
9407                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9408                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9409         }
9410 }
9411
9412 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9413 {
9414         u32 nvcfg1;
9415
9416         nvcfg1 = tr32(NVRAM_CFG1);
9417
9418         /* NVRAM protection for TPM */
9419         if (nvcfg1 & (1 << 27))
9420                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9421
9422         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9423                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9424                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9425                         tp->nvram_jedecnum = JEDEC_ATMEL;
9426                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9427                         break;
9428                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9429                         tp->nvram_jedecnum = JEDEC_ATMEL;
9430                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9431                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9432                         break;
9433                 case FLASH_5752VENDOR_ST_M45PE10:
9434                 case FLASH_5752VENDOR_ST_M45PE20:
9435                 case FLASH_5752VENDOR_ST_M45PE40:
9436                         tp->nvram_jedecnum = JEDEC_ST;
9437                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9438                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9439                         break;
9440         }
9441
9442         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9443                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9444                         case FLASH_5752PAGE_SIZE_256:
9445                                 tp->nvram_pagesize = 256;
9446                                 break;
9447                         case FLASH_5752PAGE_SIZE_512:
9448                                 tp->nvram_pagesize = 512;
9449                                 break;
9450                         case FLASH_5752PAGE_SIZE_1K:
9451                                 tp->nvram_pagesize = 1024;
9452                                 break;
9453                         case FLASH_5752PAGE_SIZE_2K:
9454                                 tp->nvram_pagesize = 2048;
9455                                 break;
9456                         case FLASH_5752PAGE_SIZE_4K:
9457                                 tp->nvram_pagesize = 4096;
9458                                 break;
9459                         case FLASH_5752PAGE_SIZE_264:
9460                                 tp->nvram_pagesize = 264;
9461                                 break;
9462                 }
9463         }
9464         else {
9465                 /* For eeprom, set pagesize to maximum eeprom size */
9466                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9467
9468                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9469                 tw32(NVRAM_CFG1, nvcfg1);
9470         }
9471 }
9472
9473 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9474 {
9475         u32 nvcfg1, protect = 0;
9476
9477         nvcfg1 = tr32(NVRAM_CFG1);
9478
9479         /* NVRAM protection for TPM */
9480         if (nvcfg1 & (1 << 27)) {
9481                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9482                 protect = 1;
9483         }
9484
9485         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9486         switch (nvcfg1) {
9487                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9488                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9489                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9490                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
9491                         tp->nvram_jedecnum = JEDEC_ATMEL;
9492                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9493                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9494                         tp->nvram_pagesize = 264;
9495                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
9496                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
9497                                 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9498                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9499                                 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9500                         else
9501                                 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9502                         break;
9503                 case FLASH_5752VENDOR_ST_M45PE10:
9504                 case FLASH_5752VENDOR_ST_M45PE20:
9505                 case FLASH_5752VENDOR_ST_M45PE40:
9506                         tp->nvram_jedecnum = JEDEC_ST;
9507                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9508                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9509                         tp->nvram_pagesize = 256;
9510                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9511                                 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9512                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9513                                 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9514                         else
9515                                 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9516                         break;
9517         }
9518 }
9519
9520 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9521 {
9522         u32 nvcfg1;
9523
9524         nvcfg1 = tr32(NVRAM_CFG1);
9525
9526         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9527                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9528                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9529                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9530                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9531                         tp->nvram_jedecnum = JEDEC_ATMEL;
9532                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9533                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9534
9535                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9536                         tw32(NVRAM_CFG1, nvcfg1);
9537                         break;
9538                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9539                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9540                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9541                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9542                         tp->nvram_jedecnum = JEDEC_ATMEL;
9543                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9544                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9545                         tp->nvram_pagesize = 264;
9546                         break;
9547                 case FLASH_5752VENDOR_ST_M45PE10:
9548                 case FLASH_5752VENDOR_ST_M45PE20:
9549                 case FLASH_5752VENDOR_ST_M45PE40:
9550                         tp->nvram_jedecnum = JEDEC_ST;
9551                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9552                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9553                         tp->nvram_pagesize = 256;
9554                         break;
9555         }
9556 }
9557
9558 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9559 {
9560         tp->nvram_jedecnum = JEDEC_ATMEL;
9561         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9562         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9563 }
9564
9565 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9566 static void __devinit tg3_nvram_init(struct tg3 *tp)
9567 {
9568         tw32_f(GRC_EEPROM_ADDR,
9569              (EEPROM_ADDR_FSM_RESET |
9570               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9571                EEPROM_ADDR_CLKPERD_SHIFT)));
9572
9573         msleep(1);
9574
9575         /* Enable seeprom accesses. */
9576         tw32_f(GRC_LOCAL_CTRL,
9577              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9578         udelay(100);
9579
9580         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9581             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9582                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9583
9584                 if (tg3_nvram_lock(tp)) {
9585                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9586                                "tg3_nvram_init failed.\n", tp->dev->name);
9587                         return;
9588                 }
9589                 tg3_enable_nvram_access(tp);
9590
9591                 tp->nvram_size = 0;
9592
9593                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9594                         tg3_get_5752_nvram_info(tp);
9595                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9596                         tg3_get_5755_nvram_info(tp);
9597                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9598                         tg3_get_5787_nvram_info(tp);
9599                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9600                         tg3_get_5906_nvram_info(tp);
9601                 else
9602                         tg3_get_nvram_info(tp);
9603
9604                 if (tp->nvram_size == 0)
9605                         tg3_get_nvram_size(tp);
9606
9607                 tg3_disable_nvram_access(tp);
9608                 tg3_nvram_unlock(tp);
9609
9610         } else {
9611                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9612
9613                 tg3_get_eeprom_size(tp);
9614         }
9615 }
9616
9617 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9618                                         u32 offset, u32 *val)
9619 {
9620         u32 tmp;
9621         int i;
9622
9623         if (offset > EEPROM_ADDR_ADDR_MASK ||
9624             (offset % 4) != 0)
9625                 return -EINVAL;
9626
9627         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9628                                         EEPROM_ADDR_DEVID_MASK |
9629                                         EEPROM_ADDR_READ);
9630         tw32(GRC_EEPROM_ADDR,
9631              tmp |
9632              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9633              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9634               EEPROM_ADDR_ADDR_MASK) |
9635              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9636
9637         for (i = 0; i < 1000; i++) {
9638                 tmp = tr32(GRC_EEPROM_ADDR);
9639
9640                 if (tmp & EEPROM_ADDR_COMPLETE)
9641                         break;
9642                 msleep(1);
9643         }
9644         if (!(tmp & EEPROM_ADDR_COMPLETE))
9645                 return -EBUSY;
9646
9647         *val = tr32(GRC_EEPROM_DATA);
9648         return 0;
9649 }
9650
9651 #define NVRAM_CMD_TIMEOUT 10000
9652
9653 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9654 {
9655         int i;
9656
9657         tw32(NVRAM_CMD, nvram_cmd);
9658         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9659                 udelay(10);
9660                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9661                         udelay(10);
9662                         break;
9663                 }
9664         }
9665         if (i == NVRAM_CMD_TIMEOUT) {
9666                 return -EBUSY;
9667         }
9668         return 0;
9669 }
9670
9671 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9672 {
9673         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9674             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9675             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9676             (tp->nvram_jedecnum == JEDEC_ATMEL))
9677
9678                 addr = ((addr / tp->nvram_pagesize) <<
9679                         ATMEL_AT45DB0X1B_PAGE_POS) +
9680                        (addr % tp->nvram_pagesize);
9681
9682         return addr;
9683 }
9684
9685 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9686 {
9687         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9688             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9689             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9690             (tp->nvram_jedecnum == JEDEC_ATMEL))
9691
9692                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9693                         tp->nvram_pagesize) +
9694                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9695
9696         return addr;
9697 }
9698
9699 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9700 {
9701         int ret;
9702
9703         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9704                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9705
9706         offset = tg3_nvram_phys_addr(tp, offset);
9707
9708         if (offset > NVRAM_ADDR_MSK)
9709                 return -EINVAL;
9710
9711         ret = tg3_nvram_lock(tp);
9712         if (ret)
9713                 return ret;
9714
9715         tg3_enable_nvram_access(tp);
9716
9717         tw32(NVRAM_ADDR, offset);
9718         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9719                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9720
9721         if (ret == 0)
9722                 *val = swab32(tr32(NVRAM_RDDATA));
9723
9724         tg3_disable_nvram_access(tp);
9725
9726         tg3_nvram_unlock(tp);
9727
9728         return ret;
9729 }
9730
9731 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9732 {
9733         int err;
9734         u32 tmp;
9735
9736         err = tg3_nvram_read(tp, offset, &tmp);
9737         *val = swab32(tmp);
9738         return err;
9739 }
9740
9741 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9742                                     u32 offset, u32 len, u8 *buf)
9743 {
9744         int i, j, rc = 0;
9745         u32 val;
9746
9747         for (i = 0; i < len; i += 4) {
9748                 u32 addr, data;
9749
9750                 addr = offset + i;
9751
9752                 memcpy(&data, buf + i, 4);
9753
9754                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9755
9756                 val = tr32(GRC_EEPROM_ADDR);
9757                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9758
9759                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9760                         EEPROM_ADDR_READ);
9761                 tw32(GRC_EEPROM_ADDR, val |
9762                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9763                         (addr & EEPROM_ADDR_ADDR_MASK) |
9764                         EEPROM_ADDR_START |
9765                         EEPROM_ADDR_WRITE);
9766
9767                 for (j = 0; j < 1000; j++) {
9768                         val = tr32(GRC_EEPROM_ADDR);
9769
9770                         if (val & EEPROM_ADDR_COMPLETE)
9771                                 break;
9772                         msleep(1);
9773                 }
9774                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9775                         rc = -EBUSY;
9776                         break;
9777                 }
9778         }
9779
9780         return rc;
9781 }
9782
9783 /* offset and length are dword aligned */
9784 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9785                 u8 *buf)
9786 {
9787         int ret = 0;
9788         u32 pagesize = tp->nvram_pagesize;
9789         u32 pagemask = pagesize - 1;
9790         u32 nvram_cmd;
9791         u8 *tmp;
9792
9793         tmp = kmalloc(pagesize, GFP_KERNEL);
9794         if (tmp == NULL)
9795                 return -ENOMEM;
9796
9797         while (len) {
9798                 int j;
9799                 u32 phy_addr, page_off, size;
9800
9801                 phy_addr = offset & ~pagemask;
9802
9803                 for (j = 0; j < pagesize; j += 4) {
9804                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9805                                                 (u32 *) (tmp + j))))
9806                                 break;
9807                 }
9808                 if (ret)
9809                         break;
9810
9811                 page_off = offset & pagemask;
9812                 size = pagesize;
9813                 if (len < size)
9814                         size = len;
9815
9816                 len -= size;
9817
9818                 memcpy(tmp + page_off, buf, size);
9819
9820                 offset = offset + (pagesize - page_off);
9821
9822                 tg3_enable_nvram_access(tp);
9823
9824                 /*
9825                  * Before we can erase the flash page, we need
9826                  * to issue a special "write enable" command.
9827                  */
9828                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9829
9830                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9831                         break;
9832
9833                 /* Erase the target page */
9834                 tw32(NVRAM_ADDR, phy_addr);
9835
9836                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9837                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9838
9839                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9840                         break;
9841
9842                 /* Issue another write enable to start the write. */
9843                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9844
9845                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9846                         break;
9847
9848                 for (j = 0; j < pagesize; j += 4) {
9849                         u32 data;
9850
9851                         data = *((u32 *) (tmp + j));
9852                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9853
9854                         tw32(NVRAM_ADDR, phy_addr + j);
9855
9856                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9857                                 NVRAM_CMD_WR;
9858
9859                         if (j == 0)
9860                                 nvram_cmd |= NVRAM_CMD_FIRST;
9861                         else if (j == (pagesize - 4))
9862                                 nvram_cmd |= NVRAM_CMD_LAST;
9863
9864                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9865                                 break;
9866                 }
9867                 if (ret)
9868                         break;
9869         }
9870
9871         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9872         tg3_nvram_exec_cmd(tp, nvram_cmd);
9873
9874         kfree(tmp);
9875
9876         return ret;
9877 }
9878
9879 /* offset and length are dword aligned */
9880 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9881                 u8 *buf)
9882 {
9883         int i, ret = 0;
9884
9885         for (i = 0; i < len; i += 4, offset += 4) {
9886                 u32 data, page_off, phy_addr, nvram_cmd;
9887
9888                 memcpy(&data, buf + i, 4);
9889                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9890
9891                 page_off = offset % tp->nvram_pagesize;
9892
9893                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9894
9895                 tw32(NVRAM_ADDR, phy_addr);
9896
9897                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9898
9899                 if ((page_off == 0) || (i == 0))
9900                         nvram_cmd |= NVRAM_CMD_FIRST;
9901                 if (page_off == (tp->nvram_pagesize - 4))
9902                         nvram_cmd |= NVRAM_CMD_LAST;
9903
9904                 if (i == (len - 4))
9905                         nvram_cmd |= NVRAM_CMD_LAST;
9906
9907                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9908                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9909                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9910                     (tp->nvram_jedecnum == JEDEC_ST) &&
9911                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9912
9913                         if ((ret = tg3_nvram_exec_cmd(tp,
9914                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9915                                 NVRAM_CMD_DONE)))
9916
9917                                 break;
9918                 }
9919                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9920                         /* We always do complete word writes to eeprom. */
9921                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9922                 }
9923
9924                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9925                         break;
9926         }
9927         return ret;
9928 }
9929
9930 /* offset and length are dword aligned */
9931 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9932 {
9933         int ret;
9934
9935         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9936                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9937                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9938                 udelay(40);
9939         }
9940
9941         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9942                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9943         }
9944         else {
9945                 u32 grc_mode;
9946
9947                 ret = tg3_nvram_lock(tp);
9948                 if (ret)
9949                         return ret;
9950
9951                 tg3_enable_nvram_access(tp);
9952                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9953                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9954                         tw32(NVRAM_WRITE1, 0x406);
9955
9956                 grc_mode = tr32(GRC_MODE);
9957                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9958
9959                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9960                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9961
9962                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9963                                 buf);
9964                 }
9965                 else {
9966                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9967                                 buf);
9968                 }
9969
9970                 grc_mode = tr32(GRC_MODE);
9971                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9972
9973                 tg3_disable_nvram_access(tp);
9974                 tg3_nvram_unlock(tp);
9975         }
9976
9977         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9978                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9979                 udelay(40);
9980         }
9981
9982         return ret;
9983 }
9984
9985 struct subsys_tbl_ent {
9986         u16 subsys_vendor, subsys_devid;
9987         u32 phy_id;
9988 };
9989
9990 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9991         /* Broadcom boards. */
9992         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9993         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9994         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9995         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9996         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9997         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9998         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9999         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
10000         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
10001         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
10002         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
10003
10004         /* 3com boards. */
10005         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
10006         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
10007         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
10008         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
10009         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
10010
10011         /* DELL boards. */
10012         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
10013         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
10014         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
10015         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
10016
10017         /* Compaq boards. */
10018         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
10019         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
10020         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
10021         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
10022         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
10023
10024         /* IBM boards. */
10025         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10026 };
10027
10028 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10029 {
10030         int i;
10031
10032         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10033                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10034                      tp->pdev->subsystem_vendor) &&
10035                     (subsys_id_to_phy_id[i].subsys_devid ==
10036                      tp->pdev->subsystem_device))
10037                         return &subsys_id_to_phy_id[i];
10038         }
10039         return NULL;
10040 }
10041
10042 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10043 {
10044         u32 val;
10045         u16 pmcsr;
10046
10047         /* On some early chips the SRAM cannot be accessed in D3hot state,
10048          * so need make sure we're in D0.
10049          */
10050         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10051         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10052         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10053         msleep(1);
10054
10055         /* Make sure register accesses (indirect or otherwise)
10056          * will function correctly.
10057          */
10058         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10059                                tp->misc_host_ctrl);
10060
10061         /* The memory arbiter has to be enabled in order for SRAM accesses
10062          * to succeed.  Normally on powerup the tg3 chip firmware will make
10063          * sure it is enabled, but other entities such as system netboot
10064          * code might disable it.
10065          */
10066         val = tr32(MEMARB_MODE);
10067         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10068
10069         tp->phy_id = PHY_ID_INVALID;
10070         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10071
10072         /* Assume an onboard device and WOL capable by default.  */
10073         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10074
10075         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10076                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10077                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10078                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10079                 }
10080                 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10081                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10082                 return;
10083         }
10084
10085         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10086         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10087                 u32 nic_cfg, led_cfg;
10088                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10089                 int eeprom_phy_serdes = 0;
10090
10091                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10092                 tp->nic_sram_data_cfg = nic_cfg;
10093
10094                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10095                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10096                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10097                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10098                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10099                     (ver > 0) && (ver < 0x100))
10100                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10101
10102                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10103                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10104                         eeprom_phy_serdes = 1;
10105
10106                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10107                 if (nic_phy_id != 0) {
10108                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10109                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10110
10111                         eeprom_phy_id  = (id1 >> 16) << 10;
10112                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10113                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10114                 } else
10115                         eeprom_phy_id = 0;
10116
10117                 tp->phy_id = eeprom_phy_id;
10118                 if (eeprom_phy_serdes) {
10119                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10120                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10121                         else
10122                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10123                 }
10124
10125                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10126                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10127                                     SHASTA_EXT_LED_MODE_MASK);
10128                 else
10129                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10130
10131                 switch (led_cfg) {
10132                 default:
10133                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10134                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10135                         break;
10136
10137                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10138                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10139                         break;
10140
10141                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10142                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10143
10144                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10145                          * read on some older 5700/5701 bootcode.
10146                          */
10147                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10148                             ASIC_REV_5700 ||
10149                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10150                             ASIC_REV_5701)
10151                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10152
10153                         break;
10154
10155                 case SHASTA_EXT_LED_SHARED:
10156                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10157                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10158                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10159                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10160                                                  LED_CTRL_MODE_PHY_2);
10161                         break;
10162
10163                 case SHASTA_EXT_LED_MAC:
10164                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10165                         break;
10166
10167                 case SHASTA_EXT_LED_COMBO:
10168                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10169                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10170                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10171                                                  LED_CTRL_MODE_PHY_2);
10172                         break;
10173
10174                 };
10175
10176                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10177                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10178                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10179                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10180
10181                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10182                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10183                         if ((tp->pdev->subsystem_vendor ==
10184                              PCI_VENDOR_ID_ARIMA) &&
10185                             (tp->pdev->subsystem_device == 0x205a ||
10186                              tp->pdev->subsystem_device == 0x2063))
10187                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10188                 } else {
10189                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10190                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10191                 }
10192
10193                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10194                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10195                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10196                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10197                 }
10198                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10199                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10200                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10201
10202                 if (cfg2 & (1 << 17))
10203                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10204
10205                 /* serdes signal pre-emphasis in register 0x590 set by */
10206                 /* bootcode if bit 18 is set */
10207                 if (cfg2 & (1 << 18))
10208                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10209
10210                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10211                         u32 cfg3;
10212
10213                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10214                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10215                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10216                 }
10217         }
10218 }
10219
10220 static int __devinit tg3_phy_probe(struct tg3 *tp)
10221 {
10222         u32 hw_phy_id_1, hw_phy_id_2;
10223         u32 hw_phy_id, hw_phy_id_masked;
10224         int err;
10225
10226         /* Reading the PHY ID register can conflict with ASF
10227          * firwmare access to the PHY hardware.
10228          */
10229         err = 0;
10230         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10231                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10232         } else {
10233                 /* Now read the physical PHY_ID from the chip and verify
10234                  * that it is sane.  If it doesn't look good, we fall back
10235                  * to either the hard-coded table based PHY_ID and failing
10236                  * that the value found in the eeprom area.
10237                  */
10238                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10239                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10240
10241                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10242                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10243                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10244
10245                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10246         }
10247
10248         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10249                 tp->phy_id = hw_phy_id;
10250                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10251                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10252                 else
10253                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10254         } else {
10255                 if (tp->phy_id != PHY_ID_INVALID) {
10256                         /* Do nothing, phy ID already set up in
10257                          * tg3_get_eeprom_hw_cfg().
10258                          */
10259                 } else {
10260                         struct subsys_tbl_ent *p;
10261
10262                         /* No eeprom signature?  Try the hardcoded
10263                          * subsys device table.
10264                          */
10265                         p = lookup_by_subsys(tp);
10266                         if (!p)
10267                                 return -ENODEV;
10268
10269                         tp->phy_id = p->phy_id;
10270                         if (!tp->phy_id ||
10271                             tp->phy_id == PHY_ID_BCM8002)
10272                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10273                 }
10274         }
10275
10276         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10277             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10278                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10279
10280                 tg3_readphy(tp, MII_BMSR, &bmsr);
10281                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10282                     (bmsr & BMSR_LSTATUS))
10283                         goto skip_phy_reset;
10284
10285                 err = tg3_phy_reset(tp);
10286                 if (err)
10287                         return err;
10288
10289                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10290                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10291                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10292                 tg3_ctrl = 0;
10293                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10294                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10295                                     MII_TG3_CTRL_ADV_1000_FULL);
10296                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10297                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10298                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10299                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10300                 }
10301
10302                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10303                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10304                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10305                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10306                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10307
10308                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10309                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10310
10311                         tg3_writephy(tp, MII_BMCR,
10312                                      BMCR_ANENABLE | BMCR_ANRESTART);
10313                 }
10314                 tg3_phy_set_wirespeed(tp);
10315
10316                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10317                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10318                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10319         }
10320
10321 skip_phy_reset:
10322         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10323                 err = tg3_init_5401phy_dsp(tp);
10324                 if (err)
10325                         return err;
10326         }
10327
10328         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10329                 err = tg3_init_5401phy_dsp(tp);
10330         }
10331
10332         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10333                 tp->link_config.advertising =
10334                         (ADVERTISED_1000baseT_Half |
10335                          ADVERTISED_1000baseT_Full |
10336                          ADVERTISED_Autoneg |
10337                          ADVERTISED_FIBRE);
10338         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10339                 tp->link_config.advertising &=
10340                         ~(ADVERTISED_1000baseT_Half |
10341                           ADVERTISED_1000baseT_Full);
10342
10343         return err;
10344 }
10345
10346 static void __devinit tg3_read_partno(struct tg3 *tp)
10347 {
10348         unsigned char vpd_data[256];
10349         unsigned int i;
10350         u32 magic;
10351
10352         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10353                 goto out_not_found;
10354
10355         if (magic == TG3_EEPROM_MAGIC) {
10356                 for (i = 0; i < 256; i += 4) {
10357                         u32 tmp;
10358
10359                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10360                                 goto out_not_found;
10361
10362                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10363                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10364                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10365                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10366                 }
10367         } else {
10368                 int vpd_cap;
10369
10370                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10371                 for (i = 0; i < 256; i += 4) {
10372                         u32 tmp, j = 0;
10373                         u16 tmp16;
10374
10375                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10376                                               i);
10377                         while (j++ < 100) {
10378                                 pci_read_config_word(tp->pdev, vpd_cap +
10379                                                      PCI_VPD_ADDR, &tmp16);
10380                                 if (tmp16 & 0x8000)
10381                                         break;
10382                                 msleep(1);
10383                         }
10384                         if (!(tmp16 & 0x8000))
10385                                 goto out_not_found;
10386
10387                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10388                                               &tmp);
10389                         tmp = cpu_to_le32(tmp);
10390                         memcpy(&vpd_data[i], &tmp, 4);
10391                 }
10392         }
10393
10394         /* Now parse and find the part number. */
10395         for (i = 0; i < 254; ) {
10396                 unsigned char val = vpd_data[i];
10397                 unsigned int block_end;
10398
10399                 if (val == 0x82 || val == 0x91) {
10400                         i = (i + 3 +
10401                              (vpd_data[i + 1] +
10402                               (vpd_data[i + 2] << 8)));
10403                         continue;
10404                 }
10405
10406                 if (val != 0x90)
10407                         goto out_not_found;
10408
10409                 block_end = (i + 3 +
10410                              (vpd_data[i + 1] +
10411                               (vpd_data[i + 2] << 8)));
10412                 i += 3;
10413
10414                 if (block_end > 256)
10415                         goto out_not_found;
10416
10417                 while (i < (block_end - 2)) {
10418                         if (vpd_data[i + 0] == 'P' &&
10419                             vpd_data[i + 1] == 'N') {
10420                                 int partno_len = vpd_data[i + 2];
10421
10422                                 i += 3;
10423                                 if (partno_len > 24 || (partno_len + i) > 256)
10424                                         goto out_not_found;
10425
10426                                 memcpy(tp->board_part_number,
10427                                        &vpd_data[i], partno_len);
10428
10429                                 /* Success. */
10430                                 return;
10431                         }
10432                         i += 3 + vpd_data[i + 2];
10433                 }
10434
10435                 /* Part number not found. */
10436                 goto out_not_found;
10437         }
10438
10439 out_not_found:
10440         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10441                 strcpy(tp->board_part_number, "BCM95906");
10442         else
10443                 strcpy(tp->board_part_number, "none");
10444 }
10445
10446 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10447 {
10448         u32 val, offset, start;
10449
10450         if (tg3_nvram_read_swab(tp, 0, &val))
10451                 return;
10452
10453         if (val != TG3_EEPROM_MAGIC)
10454                 return;
10455
10456         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10457             tg3_nvram_read_swab(tp, 0x4, &start))
10458                 return;
10459
10460         offset = tg3_nvram_logical_addr(tp, offset);
10461         if (tg3_nvram_read_swab(tp, offset, &val))
10462                 return;
10463
10464         if ((val & 0xfc000000) == 0x0c000000) {
10465                 u32 ver_offset, addr;
10466                 int i;
10467
10468                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10469                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10470                         return;
10471
10472                 if (val != 0)
10473                         return;
10474
10475                 addr = offset + ver_offset - start;
10476                 for (i = 0; i < 16; i += 4) {
10477                         if (tg3_nvram_read(tp, addr + i, &val))
10478                                 return;
10479
10480                         val = cpu_to_le32(val);
10481                         memcpy(tp->fw_ver + i, &val, 4);
10482                 }
10483         }
10484 }
10485
10486 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10487
10488 static int __devinit tg3_get_invariants(struct tg3 *tp)
10489 {
10490         static struct pci_device_id write_reorder_chipsets[] = {
10491                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10492                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10493                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10494                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10495                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10496                              PCI_DEVICE_ID_VIA_8385_0) },
10497                 { },
10498         };
10499         u32 misc_ctrl_reg;
10500         u32 cacheline_sz_reg;
10501         u32 pci_state_reg, grc_misc_cfg;
10502         u32 val;
10503         u16 pci_cmd;
10504         int err, pcie_cap;
10505
10506         /* Force memory write invalidate off.  If we leave it on,
10507          * then on 5700_BX chips we have to enable a workaround.
10508          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10509          * to match the cacheline size.  The Broadcom driver have this
10510          * workaround but turns MWI off all the times so never uses
10511          * it.  This seems to suggest that the workaround is insufficient.
10512          */
10513         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10514         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10515         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10516
10517         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10518          * has the register indirect write enable bit set before
10519          * we try to access any of the MMIO registers.  It is also
10520          * critical that the PCI-X hw workaround situation is decided
10521          * before that as well.
10522          */
10523         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10524                               &misc_ctrl_reg);
10525
10526         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10527                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10528
10529         /* Wrong chip ID in 5752 A0. This code can be removed later
10530          * as A0 is not in production.
10531          */
10532         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10533                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10534
10535         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10536          * we need to disable memory and use config. cycles
10537          * only to access all registers. The 5702/03 chips
10538          * can mistakenly decode the special cycles from the
10539          * ICH chipsets as memory write cycles, causing corruption
10540          * of register and memory space. Only certain ICH bridges
10541          * will drive special cycles with non-zero data during the
10542          * address phase which can fall within the 5703's address
10543          * range. This is not an ICH bug as the PCI spec allows
10544          * non-zero address during special cycles. However, only
10545          * these ICH bridges are known to drive non-zero addresses
10546          * during special cycles.
10547          *
10548          * Since special cycles do not cross PCI bridges, we only
10549          * enable this workaround if the 5703 is on the secondary
10550          * bus of these ICH bridges.
10551          */
10552         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10553             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10554                 static struct tg3_dev_id {
10555                         u32     vendor;
10556                         u32     device;
10557                         u32     rev;
10558                 } ich_chipsets[] = {
10559                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10560                           PCI_ANY_ID },
10561                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10562                           PCI_ANY_ID },
10563                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10564                           0xa },
10565                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10566                           PCI_ANY_ID },
10567                         { },
10568                 };
10569                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10570                 struct pci_dev *bridge = NULL;
10571
10572                 while (pci_id->vendor != 0) {
10573                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10574                                                 bridge);
10575                         if (!bridge) {
10576                                 pci_id++;
10577                                 continue;
10578                         }
10579                         if (pci_id->rev != PCI_ANY_ID) {
10580                                 if (bridge->revision > pci_id->rev)
10581                                         continue;
10582                         }
10583                         if (bridge->subordinate &&
10584                             (bridge->subordinate->number ==
10585                              tp->pdev->bus->number)) {
10586
10587                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10588                                 pci_dev_put(bridge);
10589                                 break;
10590                         }
10591                 }
10592         }
10593
10594         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10595          * DMA addresses > 40-bit. This bridge may have other additional
10596          * 57xx devices behind it in some 4-port NIC designs for example.
10597          * Any tg3 device found behind the bridge will also need the 40-bit
10598          * DMA workaround.
10599          */
10600         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10601             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10602                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10603                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10604                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10605         }
10606         else {
10607                 struct pci_dev *bridge = NULL;
10608
10609                 do {
10610                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10611                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10612                                                 bridge);
10613                         if (bridge && bridge->subordinate &&
10614                             (bridge->subordinate->number <=
10615                              tp->pdev->bus->number) &&
10616                             (bridge->subordinate->subordinate >=
10617                              tp->pdev->bus->number)) {
10618                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10619                                 pci_dev_put(bridge);
10620                                 break;
10621                         }
10622                 } while (bridge);
10623         }
10624
10625         /* Initialize misc host control in PCI block. */
10626         tp->misc_host_ctrl |= (misc_ctrl_reg &
10627                                MISC_HOST_CTRL_CHIPREV);
10628         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10629                                tp->misc_host_ctrl);
10630
10631         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10632                               &cacheline_sz_reg);
10633
10634         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10635         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10636         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10637         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10638
10639         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10640             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10641                 tp->pdev_peer = tg3_find_peer(tp);
10642
10643         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10644             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10645             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10646             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10647             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10648             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10649                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10650
10651         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10652             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10653                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10654
10655         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10656                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10657                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10658                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10659                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10660                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10661                      tp->pdev_peer == tp->pdev))
10662                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10663
10664                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10665                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10666                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10667                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10668                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10669                 } else {
10670                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10671                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10672                                 ASIC_REV_5750 &&
10673                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10674                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10675                 }
10676         }
10677
10678         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10679             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10680             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10681             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10682             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10683             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10684                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10685
10686         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10687         if (pcie_cap != 0) {
10688                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10689                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10690                         u16 lnkctl;
10691
10692                         pci_read_config_word(tp->pdev,
10693                                              pcie_cap + PCI_EXP_LNKCTL,
10694                                              &lnkctl);
10695                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10696                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10697                 }
10698         }
10699
10700         /* If we have an AMD 762 or VIA K8T800 chipset, write
10701          * reordering to the mailbox registers done by the host
10702          * controller can cause major troubles.  We read back from
10703          * every mailbox register write to force the writes to be
10704          * posted to the chip in order.
10705          */
10706         if (pci_dev_present(write_reorder_chipsets) &&
10707             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10708                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10709
10710         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10711             tp->pci_lat_timer < 64) {
10712                 tp->pci_lat_timer = 64;
10713
10714                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10715                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10716                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10717                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10718
10719                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10720                                        cacheline_sz_reg);
10721         }
10722
10723         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10724                               &pci_state_reg);
10725
10726         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10727                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10728
10729                 /* If this is a 5700 BX chipset, and we are in PCI-X
10730                  * mode, enable register write workaround.
10731                  *
10732                  * The workaround is to use indirect register accesses
10733                  * for all chip writes not to mailbox registers.
10734                  */
10735                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10736                         u32 pm_reg;
10737                         u16 pci_cmd;
10738
10739                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10740
10741                         /* The chip can have it's power management PCI config
10742                          * space registers clobbered due to this bug.
10743                          * So explicitly force the chip into D0 here.
10744                          */
10745                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10746                                               &pm_reg);
10747                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10748                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10749                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10750                                                pm_reg);
10751
10752                         /* Also, force SERR#/PERR# in PCI command. */
10753                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10754                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10755                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10756                 }
10757         }
10758
10759         /* 5700 BX chips need to have their TX producer index mailboxes
10760          * written twice to workaround a bug.
10761          */
10762         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10763                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10764
10765         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10766                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10767         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10768                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10769
10770         /* Chip-specific fixup from Broadcom driver */
10771         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10772             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10773                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10774                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10775         }
10776
10777         /* Default fast path register access methods */
10778         tp->read32 = tg3_read32;
10779         tp->write32 = tg3_write32;
10780         tp->read32_mbox = tg3_read32;
10781         tp->write32_mbox = tg3_write32;
10782         tp->write32_tx_mbox = tg3_write32;
10783         tp->write32_rx_mbox = tg3_write32;
10784
10785         /* Various workaround register access methods */
10786         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10787                 tp->write32 = tg3_write_indirect_reg32;
10788         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10789                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10790                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10791                 /*
10792                  * Back to back register writes can cause problems on these
10793                  * chips, the workaround is to read back all reg writes
10794                  * except those to mailbox regs.
10795                  *
10796                  * See tg3_write_indirect_reg32().
10797                  */
10798                 tp->write32 = tg3_write_flush_reg32;
10799         }
10800
10801
10802         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10803             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10804                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10805                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10806                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10807         }
10808
10809         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10810                 tp->read32 = tg3_read_indirect_reg32;
10811                 tp->write32 = tg3_write_indirect_reg32;
10812                 tp->read32_mbox = tg3_read_indirect_mbox;
10813                 tp->write32_mbox = tg3_write_indirect_mbox;
10814                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10815                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10816
10817                 iounmap(tp->regs);
10818                 tp->regs = NULL;
10819
10820                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10821                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10822                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10823         }
10824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10825                 tp->read32_mbox = tg3_read32_mbox_5906;
10826                 tp->write32_mbox = tg3_write32_mbox_5906;
10827                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10828                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10829         }
10830
10831         if (tp->write32 == tg3_write_indirect_reg32 ||
10832             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10833              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10834               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10835                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10836
10837         /* Get eeprom hw config before calling tg3_set_power_state().
10838          * In particular, the TG3_FLG2_IS_NIC flag must be
10839          * determined before calling tg3_set_power_state() so that
10840          * we know whether or not to switch out of Vaux power.
10841          * When the flag is set, it means that GPIO1 is used for eeprom
10842          * write protect and also implies that it is a LOM where GPIOs
10843          * are not used to switch power.
10844          */
10845         tg3_get_eeprom_hw_cfg(tp);
10846
10847         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10848          * GPIO1 driven high will bring 5700's external PHY out of reset.
10849          * It is also used as eeprom write protect on LOMs.
10850          */
10851         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10852         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10853             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10854                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10855                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10856         /* Unused GPIO3 must be driven as output on 5752 because there
10857          * are no pull-up resistors on unused GPIO pins.
10858          */
10859         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10860                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10861
10862         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10863                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10864
10865         /* Force the chip into D0. */
10866         err = tg3_set_power_state(tp, PCI_D0);
10867         if (err) {
10868                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10869                        pci_name(tp->pdev));
10870                 return err;
10871         }
10872
10873         /* 5700 B0 chips do not support checksumming correctly due
10874          * to hardware bugs.
10875          */
10876         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10877                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10878
10879         /* Derive initial jumbo mode from MTU assigned in
10880          * ether_setup() via the alloc_etherdev() call
10881          */
10882         if (tp->dev->mtu > ETH_DATA_LEN &&
10883             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10884                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10885
10886         /* Determine WakeOnLan speed to use. */
10887         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10888             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10889             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10890             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10891                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10892         } else {
10893                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10894         }
10895
10896         /* A few boards don't want Ethernet@WireSpeed phy feature */
10897         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10898             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10899              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10900              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10901             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10902             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10903                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10904
10905         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10906             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10907                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10908         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10909                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10910
10911         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10912                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10913                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10914                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10915                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10916                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10917                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10918                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10919                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10920                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10921         }
10922
10923         tp->coalesce_mode = 0;
10924         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10925             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10926                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10927
10928         /* Initialize MAC MI mode, polling disabled. */
10929         tw32_f(MAC_MI_MODE, tp->mi_mode);
10930         udelay(80);
10931
10932         /* Initialize data/descriptor byte/word swapping. */
10933         val = tr32(GRC_MODE);
10934         val &= GRC_MODE_HOST_STACKUP;
10935         tw32(GRC_MODE, val | tp->grc_mode);
10936
10937         tg3_switch_clocks(tp);
10938
10939         /* Clear this out for sanity. */
10940         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10941
10942         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10943                               &pci_state_reg);
10944         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10945             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10946                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10947
10948                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10949                     chiprevid == CHIPREV_ID_5701_B0 ||
10950                     chiprevid == CHIPREV_ID_5701_B2 ||
10951                     chiprevid == CHIPREV_ID_5701_B5) {
10952                         void __iomem *sram_base;
10953
10954                         /* Write some dummy words into the SRAM status block
10955                          * area, see if it reads back correctly.  If the return
10956                          * value is bad, force enable the PCIX workaround.
10957                          */
10958                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10959
10960                         writel(0x00000000, sram_base);
10961                         writel(0x00000000, sram_base + 4);
10962                         writel(0xffffffff, sram_base + 4);
10963                         if (readl(sram_base) != 0x00000000)
10964                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10965                 }
10966         }
10967
10968         udelay(50);
10969         tg3_nvram_init(tp);
10970
10971         grc_misc_cfg = tr32(GRC_MISC_CFG);
10972         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10973
10974         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10975             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10976              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10977                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10978
10979         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10980             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10981                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10982         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10983                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10984                                       HOSTCC_MODE_CLRTICK_TXBD);
10985
10986                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10987                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10988                                        tp->misc_host_ctrl);
10989         }
10990
10991         /* these are limited to 10/100 only */
10992         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10993              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10994             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10995              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10996              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10997               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10998               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10999             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
11000              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
11001               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
11002               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
11003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11004                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
11005
11006         err = tg3_phy_probe(tp);
11007         if (err) {
11008                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
11009                        pci_name(tp->pdev), err);
11010                 /* ... but do not return immediately ... */
11011         }
11012
11013         tg3_read_partno(tp);
11014         tg3_read_fw_ver(tp);
11015
11016         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
11017                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11018         } else {
11019                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11020                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
11021                 else
11022                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11023         }
11024
11025         /* 5700 {AX,BX} chips have a broken status block link
11026          * change bit implementation, so we must use the
11027          * status register in those cases.
11028          */
11029         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11030                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11031         else
11032                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11033
11034         /* The led_ctrl is set during tg3_phy_probe, here we might
11035          * have to force the link status polling mechanism based
11036          * upon subsystem IDs.
11037          */
11038         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11039             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11040             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11041                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11042                                   TG3_FLAG_USE_LINKCHG_REG);
11043         }
11044
11045         /* For all SERDES we poll the MAC status register. */
11046         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11047                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11048         else
11049                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11050
11051         /* All chips before 5787 can get confused if TX buffers
11052          * straddle the 4GB address boundary in some cases.
11053          */
11054         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11055             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11057                 tp->dev->hard_start_xmit = tg3_start_xmit;
11058         else
11059                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11060
11061         tp->rx_offset = 2;
11062         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11063             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11064                 tp->rx_offset = 0;
11065
11066         tp->rx_std_max_post = TG3_RX_RING_SIZE;
11067
11068         /* Increment the rx prod index on the rx std ring by at most
11069          * 8 for these chips to workaround hw errata.
11070          */
11071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11074                 tp->rx_std_max_post = 8;
11075
11076         /* By default, disable wake-on-lan.  User can change this
11077          * using ETHTOOL_SWOL.
11078          */
11079         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11080
11081         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11082                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11083                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
11084
11085         return err;
11086 }
11087
11088 #ifdef CONFIG_SPARC
11089 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11090 {
11091         struct net_device *dev = tp->dev;
11092         struct pci_dev *pdev = tp->pdev;
11093         struct device_node *dp = pci_device_to_OF_node(pdev);
11094         const unsigned char *addr;
11095         int len;
11096
11097         addr = of_get_property(dp, "local-mac-address", &len);
11098         if (addr && len == 6) {
11099                 memcpy(dev->dev_addr, addr, 6);
11100                 memcpy(dev->perm_addr, dev->dev_addr, 6);
11101                 return 0;
11102         }
11103         return -ENODEV;
11104 }
11105
11106 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11107 {
11108         struct net_device *dev = tp->dev;
11109
11110         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11111         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11112         return 0;
11113 }
11114 #endif
11115
11116 static int __devinit tg3_get_device_address(struct tg3 *tp)
11117 {
11118         struct net_device *dev = tp->dev;
11119         u32 hi, lo, mac_offset;
11120         int addr_ok = 0;
11121
11122 #ifdef CONFIG_SPARC
11123         if (!tg3_get_macaddr_sparc(tp))
11124                 return 0;
11125 #endif
11126
11127         mac_offset = 0x7c;
11128         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11129             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11130                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11131                         mac_offset = 0xcc;
11132                 if (tg3_nvram_lock(tp))
11133                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11134                 else
11135                         tg3_nvram_unlock(tp);
11136         }
11137         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11138                 mac_offset = 0x10;
11139
11140         /* First try to get it from MAC address mailbox. */
11141         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11142         if ((hi >> 16) == 0x484b) {
11143                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11144                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11145
11146                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11147                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11148                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11149                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11150                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11151
11152                 /* Some old bootcode may report a 0 MAC address in SRAM */
11153                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11154         }
11155         if (!addr_ok) {
11156                 /* Next, try NVRAM. */
11157                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11158                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11159                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11160                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11161                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11162                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11163                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11164                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11165                 }
11166                 /* Finally just fetch it out of the MAC control regs. */
11167                 else {
11168                         hi = tr32(MAC_ADDR_0_HIGH);
11169                         lo = tr32(MAC_ADDR_0_LOW);
11170
11171                         dev->dev_addr[5] = lo & 0xff;
11172                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11173                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11174                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11175                         dev->dev_addr[1] = hi & 0xff;
11176                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11177                 }
11178         }
11179
11180         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11181 #ifdef CONFIG_SPARC64
11182                 if (!tg3_get_default_macaddr_sparc(tp))
11183                         return 0;
11184 #endif
11185                 return -EINVAL;
11186         }
11187         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11188         return 0;
11189 }
11190
11191 #define BOUNDARY_SINGLE_CACHELINE       1
11192 #define BOUNDARY_MULTI_CACHELINE        2
11193
11194 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11195 {
11196         int cacheline_size;
11197         u8 byte;
11198         int goal;
11199
11200         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11201         if (byte == 0)
11202                 cacheline_size = 1024;
11203         else
11204                 cacheline_size = (int) byte * 4;
11205
11206         /* On 5703 and later chips, the boundary bits have no
11207          * effect.
11208          */
11209         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11210             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11211             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11212                 goto out;
11213
11214 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11215         goal = BOUNDARY_MULTI_CACHELINE;
11216 #else
11217 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11218         goal = BOUNDARY_SINGLE_CACHELINE;
11219 #else
11220         goal = 0;
11221 #endif
11222 #endif
11223
11224         if (!goal)
11225                 goto out;
11226
11227         /* PCI controllers on most RISC systems tend to disconnect
11228          * when a device tries to burst across a cache-line boundary.
11229          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11230          *
11231          * Unfortunately, for PCI-E there are only limited
11232          * write-side controls for this, and thus for reads
11233          * we will still get the disconnects.  We'll also waste
11234          * these PCI cycles for both read and write for chips
11235          * other than 5700 and 5701 which do not implement the
11236          * boundary bits.
11237          */
11238         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11239             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11240                 switch (cacheline_size) {
11241                 case 16:
11242                 case 32:
11243                 case 64:
11244                 case 128:
11245                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11246                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11247                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11248                         } else {
11249                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11250                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11251                         }
11252                         break;
11253
11254                 case 256:
11255                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11256                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11257                         break;
11258
11259                 default:
11260                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11261                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11262                         break;
11263                 };
11264         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11265                 switch (cacheline_size) {
11266                 case 16:
11267                 case 32:
11268                 case 64:
11269                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11270                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11271                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11272                                 break;
11273                         }
11274                         /* fallthrough */
11275                 case 128:
11276                 default:
11277                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11278                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11279                         break;
11280                 };
11281         } else {
11282                 switch (cacheline_size) {
11283                 case 16:
11284                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11285                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11286                                         DMA_RWCTRL_WRITE_BNDRY_16);
11287                                 break;
11288                         }
11289                         /* fallthrough */
11290                 case 32:
11291                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11292                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11293                                         DMA_RWCTRL_WRITE_BNDRY_32);
11294                                 break;
11295                         }
11296                         /* fallthrough */
11297                 case 64:
11298                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11299                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11300                                         DMA_RWCTRL_WRITE_BNDRY_64);
11301                                 break;
11302                         }
11303                         /* fallthrough */
11304                 case 128:
11305                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11306                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11307                                         DMA_RWCTRL_WRITE_BNDRY_128);
11308                                 break;
11309                         }
11310                         /* fallthrough */
11311                 case 256:
11312                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11313                                 DMA_RWCTRL_WRITE_BNDRY_256);
11314                         break;
11315                 case 512:
11316                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11317                                 DMA_RWCTRL_WRITE_BNDRY_512);
11318                         break;
11319                 case 1024:
11320                 default:
11321                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11322                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11323                         break;
11324                 };
11325         }
11326
11327 out:
11328         return val;
11329 }
11330
11331 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11332 {
11333         struct tg3_internal_buffer_desc test_desc;
11334         u32 sram_dma_descs;
11335         int i, ret;
11336
11337         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11338
11339         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11340         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11341         tw32(RDMAC_STATUS, 0);
11342         tw32(WDMAC_STATUS, 0);
11343
11344         tw32(BUFMGR_MODE, 0);
11345         tw32(FTQ_RESET, 0);
11346
11347         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11348         test_desc.addr_lo = buf_dma & 0xffffffff;
11349         test_desc.nic_mbuf = 0x00002100;
11350         test_desc.len = size;
11351
11352         /*
11353          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11354          * the *second* time the tg3 driver was getting loaded after an
11355          * initial scan.
11356          *
11357          * Broadcom tells me:
11358          *   ...the DMA engine is connected to the GRC block and a DMA
11359          *   reset may affect the GRC block in some unpredictable way...
11360          *   The behavior of resets to individual blocks has not been tested.
11361          *
11362          * Broadcom noted the GRC reset will also reset all sub-components.
11363          */
11364         if (to_device) {
11365                 test_desc.cqid_sqid = (13 << 8) | 2;
11366
11367                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11368                 udelay(40);
11369         } else {
11370                 test_desc.cqid_sqid = (16 << 8) | 7;
11371
11372                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11373                 udelay(40);
11374         }
11375         test_desc.flags = 0x00000005;
11376
11377         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11378                 u32 val;
11379
11380                 val = *(((u32 *)&test_desc) + i);
11381                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11382                                        sram_dma_descs + (i * sizeof(u32)));
11383                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11384         }
11385         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11386
11387         if (to_device) {
11388                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11389         } else {
11390                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11391         }
11392
11393         ret = -ENODEV;
11394         for (i = 0; i < 40; i++) {
11395                 u32 val;
11396
11397                 if (to_device)
11398                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11399                 else
11400                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11401                 if ((val & 0xffff) == sram_dma_descs) {
11402                         ret = 0;
11403                         break;
11404                 }
11405
11406                 udelay(100);
11407         }
11408
11409         return ret;
11410 }
11411
11412 #define TEST_BUFFER_SIZE        0x2000
11413
11414 static int __devinit tg3_test_dma(struct tg3 *tp)
11415 {
11416         dma_addr_t buf_dma;
11417         u32 *buf, saved_dma_rwctrl;
11418         int ret;
11419
11420         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11421         if (!buf) {
11422                 ret = -ENOMEM;
11423                 goto out_nofree;
11424         }
11425
11426         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11427                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11428
11429         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11430
11431         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11432                 /* DMA read watermark not used on PCIE */
11433                 tp->dma_rwctrl |= 0x00180000;
11434         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11435                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11436                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11437                         tp->dma_rwctrl |= 0x003f0000;
11438                 else
11439                         tp->dma_rwctrl |= 0x003f000f;
11440         } else {
11441                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11442                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11443                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11444                         u32 read_water = 0x7;
11445
11446                         /* If the 5704 is behind the EPB bridge, we can
11447                          * do the less restrictive ONE_DMA workaround for
11448                          * better performance.
11449                          */
11450                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11451                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11452                                 tp->dma_rwctrl |= 0x8000;
11453                         else if (ccval == 0x6 || ccval == 0x7)
11454                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11455
11456                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11457                                 read_water = 4;
11458                         /* Set bit 23 to enable PCIX hw bug fix */
11459                         tp->dma_rwctrl |=
11460                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11461                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11462                                 (1 << 23);
11463                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11464                         /* 5780 always in PCIX mode */
11465                         tp->dma_rwctrl |= 0x00144000;
11466                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11467                         /* 5714 always in PCIX mode */
11468                         tp->dma_rwctrl |= 0x00148000;
11469                 } else {
11470                         tp->dma_rwctrl |= 0x001b000f;
11471                 }
11472         }
11473
11474         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11475             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11476                 tp->dma_rwctrl &= 0xfffffff0;
11477
11478         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11479             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11480                 /* Remove this if it causes problems for some boards. */
11481                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11482
11483                 /* On 5700/5701 chips, we need to set this bit.
11484                  * Otherwise the chip will issue cacheline transactions
11485                  * to streamable DMA memory with not all the byte
11486                  * enables turned on.  This is an error on several
11487                  * RISC PCI controllers, in particular sparc64.
11488                  *
11489                  * On 5703/5704 chips, this bit has been reassigned
11490                  * a different meaning.  In particular, it is used
11491                  * on those chips to enable a PCI-X workaround.
11492                  */
11493                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11494         }
11495
11496         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11497
11498 #if 0
11499         /* Unneeded, already done by tg3_get_invariants.  */
11500         tg3_switch_clocks(tp);
11501 #endif
11502
11503         ret = 0;
11504         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11505             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11506                 goto out;
11507
11508         /* It is best to perform DMA test with maximum write burst size
11509          * to expose the 5700/5701 write DMA bug.
11510          */
11511         saved_dma_rwctrl = tp->dma_rwctrl;
11512         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11513         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11514
11515         while (1) {
11516                 u32 *p = buf, i;
11517
11518                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11519                         p[i] = i;
11520
11521                 /* Send the buffer to the chip. */
11522                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11523                 if (ret) {
11524                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11525                         break;
11526                 }
11527
11528 #if 0
11529                 /* validate data reached card RAM correctly. */
11530                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11531                         u32 val;
11532                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11533                         if (le32_to_cpu(val) != p[i]) {
11534                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11535                                 /* ret = -ENODEV here? */
11536                         }
11537                         p[i] = 0;
11538                 }
11539 #endif
11540                 /* Now read it back. */
11541                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11542                 if (ret) {
11543                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11544
11545                         break;
11546                 }
11547
11548                 /* Verify it. */
11549                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11550                         if (p[i] == i)
11551                                 continue;
11552
11553                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11554                             DMA_RWCTRL_WRITE_BNDRY_16) {
11555                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11556                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11557                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11558                                 break;
11559                         } else {
11560                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11561                                 ret = -ENODEV;
11562                                 goto out;
11563                         }
11564                 }
11565
11566                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11567                         /* Success. */
11568                         ret = 0;
11569                         break;
11570                 }
11571         }
11572         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11573             DMA_RWCTRL_WRITE_BNDRY_16) {
11574                 static struct pci_device_id dma_wait_state_chipsets[] = {
11575                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11576                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11577                         { },
11578                 };
11579
11580                 /* DMA test passed without adjusting DMA boundary,
11581                  * now look for chipsets that are known to expose the
11582                  * DMA bug without failing the test.
11583                  */
11584                 if (pci_dev_present(dma_wait_state_chipsets)) {
11585                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11586                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11587                 }
11588                 else
11589                         /* Safe to use the calculated DMA boundary. */
11590                         tp->dma_rwctrl = saved_dma_rwctrl;
11591
11592                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11593         }
11594
11595 out:
11596         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11597 out_nofree:
11598         return ret;
11599 }
11600
11601 static void __devinit tg3_init_link_config(struct tg3 *tp)
11602 {
11603         tp->link_config.advertising =
11604                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11605                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11606                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11607                  ADVERTISED_Autoneg | ADVERTISED_MII);
11608         tp->link_config.speed = SPEED_INVALID;
11609         tp->link_config.duplex = DUPLEX_INVALID;
11610         tp->link_config.autoneg = AUTONEG_ENABLE;
11611         tp->link_config.active_speed = SPEED_INVALID;
11612         tp->link_config.active_duplex = DUPLEX_INVALID;
11613         tp->link_config.phy_is_low_power = 0;
11614         tp->link_config.orig_speed = SPEED_INVALID;
11615         tp->link_config.orig_duplex = DUPLEX_INVALID;
11616         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11617 }
11618
11619 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11620 {
11621         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11622                 tp->bufmgr_config.mbuf_read_dma_low_water =
11623                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11624                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11625                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11626                 tp->bufmgr_config.mbuf_high_water =
11627                         DEFAULT_MB_HIGH_WATER_5705;
11628                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11629                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11630                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11631                         tp->bufmgr_config.mbuf_high_water =
11632                                 DEFAULT_MB_HIGH_WATER_5906;
11633                 }
11634
11635                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11636                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11637                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11638                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11639                 tp->bufmgr_config.mbuf_high_water_jumbo =
11640                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11641         } else {
11642                 tp->bufmgr_config.mbuf_read_dma_low_water =
11643                         DEFAULT_MB_RDMA_LOW_WATER;
11644                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11645                         DEFAULT_MB_MACRX_LOW_WATER;
11646                 tp->bufmgr_config.mbuf_high_water =
11647                         DEFAULT_MB_HIGH_WATER;
11648
11649                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11650                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11651                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11652                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11653                 tp->bufmgr_config.mbuf_high_water_jumbo =
11654                         DEFAULT_MB_HIGH_WATER_JUMBO;
11655         }
11656
11657         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11658         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11659 }
11660
11661 static char * __devinit tg3_phy_string(struct tg3 *tp)
11662 {
11663         switch (tp->phy_id & PHY_ID_MASK) {
11664         case PHY_ID_BCM5400:    return "5400";
11665         case PHY_ID_BCM5401:    return "5401";
11666         case PHY_ID_BCM5411:    return "5411";
11667         case PHY_ID_BCM5701:    return "5701";
11668         case PHY_ID_BCM5703:    return "5703";
11669         case PHY_ID_BCM5704:    return "5704";
11670         case PHY_ID_BCM5705:    return "5705";
11671         case PHY_ID_BCM5750:    return "5750";
11672         case PHY_ID_BCM5752:    return "5752";
11673         case PHY_ID_BCM5714:    return "5714";
11674         case PHY_ID_BCM5780:    return "5780";
11675         case PHY_ID_BCM5755:    return "5755";
11676         case PHY_ID_BCM5787:    return "5787";
11677         case PHY_ID_BCM5756:    return "5722/5756";
11678         case PHY_ID_BCM5906:    return "5906";
11679         case PHY_ID_BCM8002:    return "8002/serdes";
11680         case 0:                 return "serdes";
11681         default:                return "unknown";
11682         };
11683 }
11684
11685 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11686 {
11687         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11688                 strcpy(str, "PCI Express");
11689                 return str;
11690         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11691                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11692
11693                 strcpy(str, "PCIX:");
11694
11695                 if ((clock_ctrl == 7) ||
11696                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11697                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11698                         strcat(str, "133MHz");
11699                 else if (clock_ctrl == 0)
11700                         strcat(str, "33MHz");
11701                 else if (clock_ctrl == 2)
11702                         strcat(str, "50MHz");
11703                 else if (clock_ctrl == 4)
11704                         strcat(str, "66MHz");
11705                 else if (clock_ctrl == 6)
11706                         strcat(str, "100MHz");
11707         } else {
11708                 strcpy(str, "PCI:");
11709                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11710                         strcat(str, "66MHz");
11711                 else
11712                         strcat(str, "33MHz");
11713         }
11714         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11715                 strcat(str, ":32-bit");
11716         else
11717                 strcat(str, ":64-bit");
11718         return str;
11719 }
11720
11721 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11722 {
11723         struct pci_dev *peer;
11724         unsigned int func, devnr = tp->pdev->devfn & ~7;
11725
11726         for (func = 0; func < 8; func++) {
11727                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11728                 if (peer && peer != tp->pdev)
11729                         break;
11730                 pci_dev_put(peer);
11731         }
11732         /* 5704 can be configured in single-port mode, set peer to
11733          * tp->pdev in that case.
11734          */
11735         if (!peer) {
11736                 peer = tp->pdev;
11737                 return peer;
11738         }
11739
11740         /*
11741          * We don't need to keep the refcount elevated; there's no way
11742          * to remove one half of this device without removing the other
11743          */
11744         pci_dev_put(peer);
11745
11746         return peer;
11747 }
11748
11749 static void __devinit tg3_init_coal(struct tg3 *tp)
11750 {
11751         struct ethtool_coalesce *ec = &tp->coal;
11752
11753         memset(ec, 0, sizeof(*ec));
11754         ec->cmd = ETHTOOL_GCOALESCE;
11755         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11756         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11757         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11758         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11759         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11760         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11761         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11762         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11763         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11764
11765         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11766                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11767                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11768                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11769                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11770                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11771         }
11772
11773         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11774                 ec->rx_coalesce_usecs_irq = 0;
11775                 ec->tx_coalesce_usecs_irq = 0;
11776                 ec->stats_block_coalesce_usecs = 0;
11777         }
11778 }
11779
11780 static int __devinit tg3_init_one(struct pci_dev *pdev,
11781                                   const struct pci_device_id *ent)
11782 {
11783         static int tg3_version_printed = 0;
11784         unsigned long tg3reg_base, tg3reg_len;
11785         struct net_device *dev;
11786         struct tg3 *tp;
11787         int i, err, pm_cap;
11788         char str[40];
11789         u64 dma_mask, persist_dma_mask;
11790
11791         if (tg3_version_printed++ == 0)
11792                 printk(KERN_INFO "%s", version);
11793
11794         err = pci_enable_device(pdev);
11795         if (err) {
11796                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11797                        "aborting.\n");
11798                 return err;
11799         }
11800
11801         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11802                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11803                        "base address, aborting.\n");
11804                 err = -ENODEV;
11805                 goto err_out_disable_pdev;
11806         }
11807
11808         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11809         if (err) {
11810                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11811                        "aborting.\n");
11812                 goto err_out_disable_pdev;
11813         }
11814
11815         pci_set_master(pdev);
11816
11817         /* Find power-management capability. */
11818         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11819         if (pm_cap == 0) {
11820                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11821                        "aborting.\n");
11822                 err = -EIO;
11823                 goto err_out_free_res;
11824         }
11825
11826         tg3reg_base = pci_resource_start(pdev, 0);
11827         tg3reg_len = pci_resource_len(pdev, 0);
11828
11829         dev = alloc_etherdev(sizeof(*tp));
11830         if (!dev) {
11831                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11832                 err = -ENOMEM;
11833                 goto err_out_free_res;
11834         }
11835
11836         SET_MODULE_OWNER(dev);
11837         SET_NETDEV_DEV(dev, &pdev->dev);
11838
11839 #if TG3_VLAN_TAG_USED
11840         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11841         dev->vlan_rx_register = tg3_vlan_rx_register;
11842 #endif
11843
11844         tp = netdev_priv(dev);
11845         tp->pdev = pdev;
11846         tp->dev = dev;
11847         tp->pm_cap = pm_cap;
11848         tp->mac_mode = TG3_DEF_MAC_MODE;
11849         tp->rx_mode = TG3_DEF_RX_MODE;
11850         tp->tx_mode = TG3_DEF_TX_MODE;
11851         tp->mi_mode = MAC_MI_MODE_BASE;
11852         if (tg3_debug > 0)
11853                 tp->msg_enable = tg3_debug;
11854         else
11855                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11856
11857         /* The word/byte swap controls here control register access byte
11858          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11859          * setting below.
11860          */
11861         tp->misc_host_ctrl =
11862                 MISC_HOST_CTRL_MASK_PCI_INT |
11863                 MISC_HOST_CTRL_WORD_SWAP |
11864                 MISC_HOST_CTRL_INDIR_ACCESS |
11865                 MISC_HOST_CTRL_PCISTATE_RW;
11866
11867         /* The NONFRM (non-frame) byte/word swap controls take effect
11868          * on descriptor entries, anything which isn't packet data.
11869          *
11870          * The StrongARM chips on the board (one for tx, one for rx)
11871          * are running in big-endian mode.
11872          */
11873         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11874                         GRC_MODE_WSWAP_NONFRM_DATA);
11875 #ifdef __BIG_ENDIAN
11876         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11877 #endif
11878         spin_lock_init(&tp->lock);
11879         spin_lock_init(&tp->indirect_lock);
11880         INIT_WORK(&tp->reset_task, tg3_reset_task);
11881
11882         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11883         if (tp->regs == 0UL) {
11884                 printk(KERN_ERR PFX "Cannot map device registers, "
11885                        "aborting.\n");
11886                 err = -ENOMEM;
11887                 goto err_out_free_dev;
11888         }
11889
11890         tg3_init_link_config(tp);
11891
11892         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11893         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11894         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11895
11896         dev->open = tg3_open;
11897         dev->stop = tg3_close;
11898         dev->get_stats = tg3_get_stats;
11899         dev->set_multicast_list = tg3_set_rx_mode;
11900         dev->set_mac_address = tg3_set_mac_addr;
11901         dev->do_ioctl = tg3_ioctl;
11902         dev->tx_timeout = tg3_tx_timeout;
11903         dev->poll = tg3_poll;
11904         dev->ethtool_ops = &tg3_ethtool_ops;
11905         dev->weight = 64;
11906         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11907         dev->change_mtu = tg3_change_mtu;
11908         dev->irq = pdev->irq;
11909 #ifdef CONFIG_NET_POLL_CONTROLLER
11910         dev->poll_controller = tg3_poll_controller;
11911 #endif
11912
11913         err = tg3_get_invariants(tp);
11914         if (err) {
11915                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11916                        "aborting.\n");
11917                 goto err_out_iounmap;
11918         }
11919
11920         /* The EPB bridge inside 5714, 5715, and 5780 and any
11921          * device behind the EPB cannot support DMA addresses > 40-bit.
11922          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11923          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11924          * do DMA address check in tg3_start_xmit().
11925          */
11926         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11927                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11928         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11929                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11930 #ifdef CONFIG_HIGHMEM
11931                 dma_mask = DMA_64BIT_MASK;
11932 #endif
11933         } else
11934                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11935
11936         /* Configure DMA attributes. */
11937         if (dma_mask > DMA_32BIT_MASK) {
11938                 err = pci_set_dma_mask(pdev, dma_mask);
11939                 if (!err) {
11940                         dev->features |= NETIF_F_HIGHDMA;
11941                         err = pci_set_consistent_dma_mask(pdev,
11942                                                           persist_dma_mask);
11943                         if (err < 0) {
11944                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11945                                        "DMA for consistent allocations\n");
11946                                 goto err_out_iounmap;
11947                         }
11948                 }
11949         }
11950         if (err || dma_mask == DMA_32BIT_MASK) {
11951                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11952                 if (err) {
11953                         printk(KERN_ERR PFX "No usable DMA configuration, "
11954                                "aborting.\n");
11955                         goto err_out_iounmap;
11956                 }
11957         }
11958
11959         tg3_init_bufmgr_config(tp);
11960
11961         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11962                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11963         }
11964         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11965             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11966             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11968             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11969                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11970         } else {
11971                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11972         }
11973
11974         /* TSO is on by default on chips that support hardware TSO.
11975          * Firmware TSO on older chips gives lower performance, so it
11976          * is off by default, but can be enabled using ethtool.
11977          */
11978         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11979                 dev->features |= NETIF_F_TSO;
11980                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11981                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11982                         dev->features |= NETIF_F_TSO6;
11983         }
11984
11985
11986         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11987             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11988             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11989                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11990                 tp->rx_pending = 63;
11991         }
11992
11993         err = tg3_get_device_address(tp);
11994         if (err) {
11995                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11996                        "aborting.\n");
11997                 goto err_out_iounmap;
11998         }
11999
12000         /*
12001          * Reset chip in case UNDI or EFI driver did not shutdown
12002          * DMA self test will enable WDMAC and we'll see (spurious)
12003          * pending DMA on the PCI bus at that point.
12004          */
12005         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
12006             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
12007                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
12008                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12009         }
12010
12011         err = tg3_test_dma(tp);
12012         if (err) {
12013                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
12014                 goto err_out_iounmap;
12015         }
12016
12017         /* Tigon3 can do ipv4 only... and some chips have buggy
12018          * checksumming.
12019          */
12020         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
12021                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
12022                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12023                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
12024                         dev->features |= NETIF_F_IPV6_CSUM;
12025
12026                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12027         } else
12028                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12029
12030         /* flow control autonegotiation is default behavior */
12031         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12032
12033         tg3_init_coal(tp);
12034
12035         pci_set_drvdata(pdev, dev);
12036
12037         err = register_netdev(dev);
12038         if (err) {
12039                 printk(KERN_ERR PFX "Cannot register net device, "
12040                        "aborting.\n");
12041                 goto err_out_iounmap;
12042         }
12043
12044         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
12045                dev->name,
12046                tp->board_part_number,
12047                tp->pci_chip_rev_id,
12048                tg3_phy_string(tp),
12049                tg3_bus_string(tp, str),
12050                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12051                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12052                  "10/100/1000Base-T")));
12053
12054         for (i = 0; i < 6; i++)
12055                 printk("%2.2x%c", dev->dev_addr[i],
12056                        i == 5 ? '\n' : ':');
12057
12058         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
12059                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
12060                dev->name,
12061                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12062                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12063                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12064                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
12065                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12066                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12067         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12068                dev->name, tp->dma_rwctrl,
12069                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12070                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12071
12072         return 0;
12073
12074 err_out_iounmap:
12075         if (tp->regs) {
12076                 iounmap(tp->regs);
12077                 tp->regs = NULL;
12078         }
12079
12080 err_out_free_dev:
12081         free_netdev(dev);
12082
12083 err_out_free_res:
12084         pci_release_regions(pdev);
12085
12086 err_out_disable_pdev:
12087         pci_disable_device(pdev);
12088         pci_set_drvdata(pdev, NULL);
12089         return err;
12090 }
12091
12092 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12093 {
12094         struct net_device *dev = pci_get_drvdata(pdev);
12095
12096         if (dev) {
12097                 struct tg3 *tp = netdev_priv(dev);
12098
12099                 flush_scheduled_work();
12100                 unregister_netdev(dev);
12101                 if (tp->regs) {
12102                         iounmap(tp->regs);
12103                         tp->regs = NULL;
12104                 }
12105                 free_netdev(dev);
12106                 pci_release_regions(pdev);
12107                 pci_disable_device(pdev);
12108                 pci_set_drvdata(pdev, NULL);
12109         }
12110 }
12111
12112 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12113 {
12114         struct net_device *dev = pci_get_drvdata(pdev);
12115         struct tg3 *tp = netdev_priv(dev);
12116         int err;
12117
12118         /* PCI register 4 needs to be saved whether netif_running() or not.
12119          * MSI address and data need to be saved if using MSI and
12120          * netif_running().
12121          */
12122         pci_save_state(pdev);
12123
12124         if (!netif_running(dev))
12125                 return 0;
12126
12127         flush_scheduled_work();
12128         tg3_netif_stop(tp);
12129
12130         del_timer_sync(&tp->timer);
12131
12132         tg3_full_lock(tp, 1);
12133         tg3_disable_ints(tp);
12134         tg3_full_unlock(tp);
12135
12136         netif_device_detach(dev);
12137
12138         tg3_full_lock(tp, 0);
12139         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12140         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12141         tg3_full_unlock(tp);
12142
12143         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12144         if (err) {
12145                 tg3_full_lock(tp, 0);
12146
12147                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12148                 if (tg3_restart_hw(tp, 1))
12149                         goto out;
12150
12151                 tp->timer.expires = jiffies + tp->timer_offset;
12152                 add_timer(&tp->timer);
12153
12154                 netif_device_attach(dev);
12155                 tg3_netif_start(tp);
12156
12157 out:
12158                 tg3_full_unlock(tp);
12159         }
12160
12161         return err;
12162 }
12163
12164 static int tg3_resume(struct pci_dev *pdev)
12165 {
12166         struct net_device *dev = pci_get_drvdata(pdev);
12167         struct tg3 *tp = netdev_priv(dev);
12168         int err;
12169
12170         pci_restore_state(tp->pdev);
12171
12172         if (!netif_running(dev))
12173                 return 0;
12174
12175         err = tg3_set_power_state(tp, PCI_D0);
12176         if (err)
12177                 return err;
12178
12179         /* Hardware bug - MSI won't work if INTX disabled. */
12180         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
12181             (tp->tg3_flags2 & TG3_FLG2_USING_MSI))
12182                 pci_intx(tp->pdev, 1);
12183
12184         netif_device_attach(dev);
12185
12186         tg3_full_lock(tp, 0);
12187
12188         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12189         err = tg3_restart_hw(tp, 1);
12190         if (err)
12191                 goto out;
12192
12193         tp->timer.expires = jiffies + tp->timer_offset;
12194         add_timer(&tp->timer);
12195
12196         tg3_netif_start(tp);
12197
12198 out:
12199         tg3_full_unlock(tp);
12200
12201         return err;
12202 }
12203
12204 static struct pci_driver tg3_driver = {
12205         .name           = DRV_MODULE_NAME,
12206         .id_table       = tg3_pci_tbl,
12207         .probe          = tg3_init_one,
12208         .remove         = __devexit_p(tg3_remove_one),
12209         .suspend        = tg3_suspend,
12210         .resume         = tg3_resume
12211 };
12212
12213 static int __init tg3_init(void)
12214 {
12215         return pci_register_driver(&tg3_driver);
12216 }
12217
12218 static void __exit tg3_cleanup(void)
12219 {
12220         pci_unregister_driver(&tg3_driver);
12221 }
12222
12223 module_init(tg3_init);
12224 module_exit(tg3_cleanup);