drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2007 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43
  44 #include <net/checksum.h>
  45 #include <net/ip.h>
  46
  47 #include <asm/system.h>
  48 #include <asm/io.h>
  49 #include <asm/byteorder.h>
  50 #include <asm/uaccess.h>
  51
  52 #ifdef CONFIG_SPARC
  53 #include <asm/idprom.h>
  54 #include <asm/prom.h>
  55 #endif
  56
  57 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  58 #define TG3_VLAN_TAG_USED 1
  59 #else
  60 #define TG3_VLAN_TAG_USED 0
  61 #endif
  62
  63 #define TG3_TSO_SUPPORT 1
  64
  65 #include "tg3.h"
  66
  67 #define DRV_MODULE_NAME         "tg3"
  68 #define PFX DRV_MODULE_NAME     ": "
  69 #define DRV_MODULE_VERSION      "3.93"
  70 #define DRV_MODULE_RELDATE      "May 22, 2008"
  71
  72 #define TG3_DEF_MAC_MODE        0
  73 #define TG3_DEF_RX_MODE         0
  74 #define TG3_DEF_TX_MODE         0
  75 #define TG3_DEF_MSG_ENABLE        \
  76         (NETIF_MSG_DRV          | \
  77          NETIF_MSG_PROBE        | \
  78          NETIF_MSG_LINK         | \
  79          NETIF_MSG_TIMER        | \
  80          NETIF_MSG_IFDOWN       | \
  81          NETIF_MSG_IFUP         | \
  82          NETIF_MSG_RX_ERR       | \
  83          NETIF_MSG_TX_ERR)
  84
  85 /* length of time before we decide the hardware is borked,
  86  * and dev->tx_timeout() should be called to fix the problem
  87  */
  88 #define TG3_TX_TIMEOUT                  (5 * HZ)
  89
  90 /* hardware minimum and maximum for a single frame's data payload */
  91 #define TG3_MIN_MTU                     60
  92 #define TG3_MAX_MTU(tp) \
  93         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  94
  95 /* These numbers seem to be hard coded in the NIC firmware somehow.
  96  * You can't change the ring sizes, but you can change where you place
  97  * them in the NIC onboard memory.
  98  */
  99 #define TG3_RX_RING_SIZE                512
 100 #define TG3_DEF_RX_RING_PENDING         200
 101 #define TG3_RX_JUMBO_RING_SIZE          256
 102 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 103
 104 /* Do not place this n-ring entries value into the tp struct itself,
 105  * we really want to expose these constants to GCC so that modulo et
 106  * al.  operations are done with shifts and masks instead of with
 107  * hw multiply/modulo instructions.  Another solution would be to
 108  * replace things like '% foo' with '& (foo - 1)'.
 109  */
 110 #define TG3_RX_RCB_RING_SIZE(tp)        \
 111         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 112
 113 #define TG3_TX_RING_SIZE                512
 114 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 115
 116 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_RING_SIZE)
 118 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_JUMBO_RING_SIZE)
 120 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 121                                    TG3_RX_RCB_RING_SIZE(tp))
 122 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 123                                  TG3_TX_RING_SIZE)
 124 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 125
 126 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 127 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 128
 129 /* minimum number of free TX descriptors required to wake up TX process */
 130 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 131
 132 /* number of ETHTOOL_GSTATS u64's */
 133 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 134
 135 #define TG3_NUM_TEST            6
 136
 137 static char version[] __devinitdata =
 138         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 139
 140 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 141 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 142 MODULE_LICENSE("GPL");
 143 MODULE_VERSION(DRV_MODULE_VERSION);
 144
 145 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 146 module_param(tg3_debug, int, 0);
 147 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 148
 149 static struct pci_device_id tg3_pci_tbl[] = {
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5785)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 216         {}
 217 };
 218
 219 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 220
 221 static const struct {
 222         const char string[ETH_GSTRING_LEN];
 223 } ethtool_stats_keys[TG3_NUM_STATS] = {
 224         { "rx_octets" },
 225         { "rx_fragments" },
 226         { "rx_ucast_packets" },
 227         { "rx_mcast_packets" },
 228         { "rx_bcast_packets" },
 229         { "rx_fcs_errors" },
 230         { "rx_align_errors" },
 231         { "rx_xon_pause_rcvd" },
 232         { "rx_xoff_pause_rcvd" },
 233         { "rx_mac_ctrl_rcvd" },
 234         { "rx_xoff_entered" },
 235         { "rx_frame_too_long_errors" },
 236         { "rx_jabbers" },
 237         { "rx_undersize_packets" },
 238         { "rx_in_length_errors" },
 239         { "rx_out_length_errors" },
 240         { "rx_64_or_less_octet_packets" },
 241         { "rx_65_to_127_octet_packets" },
 242         { "rx_128_to_255_octet_packets" },
 243         { "rx_256_to_511_octet_packets" },
 244         { "rx_512_to_1023_octet_packets" },
 245         { "rx_1024_to_1522_octet_packets" },
 246         { "rx_1523_to_2047_octet_packets" },
 247         { "rx_2048_to_4095_octet_packets" },
 248         { "rx_4096_to_8191_octet_packets" },
 249         { "rx_8192_to_9022_octet_packets" },
 250
 251         { "tx_octets" },
 252         { "tx_collisions" },
 253
 254         { "tx_xon_sent" },
 255         { "tx_xoff_sent" },
 256         { "tx_flow_control" },
 257         { "tx_mac_errors" },
 258         { "tx_single_collisions" },
 259         { "tx_mult_collisions" },
 260         { "tx_deferred" },
 261         { "tx_excessive_collisions" },
 262         { "tx_late_collisions" },
 263         { "tx_collide_2times" },
 264         { "tx_collide_3times" },
 265         { "tx_collide_4times" },
 266         { "tx_collide_5times" },
 267         { "tx_collide_6times" },
 268         { "tx_collide_7times" },
 269         { "tx_collide_8times" },
 270         { "tx_collide_9times" },
 271         { "tx_collide_10times" },
 272         { "tx_collide_11times" },
 273         { "tx_collide_12times" },
 274         { "tx_collide_13times" },
 275         { "tx_collide_14times" },
 276         { "tx_collide_15times" },
 277         { "tx_ucast_packets" },
 278         { "tx_mcast_packets" },
 279         { "tx_bcast_packets" },
 280         { "tx_carrier_sense_errors" },
 281         { "tx_discards" },
 282         { "tx_errors" },
 283
 284         { "dma_writeq_full" },
 285         { "dma_write_prioq_full" },
 286         { "rxbds_empty" },
 287         { "rx_discards" },
 288         { "rx_errors" },
 289         { "rx_threshold_hit" },
 290
 291         { "dma_readq_full" },
 292         { "dma_read_prioq_full" },
 293         { "tx_comp_queue_full" },
 294
 295         { "ring_set_send_prod_index" },
 296         { "ring_status_update" },
 297         { "nic_irqs" },
 298         { "nic_avoided_irqs" },
 299         { "nic_tx_threshold_hit" }
 300 };
 301
 302 static const struct {
 303         const char string[ETH_GSTRING_LEN];
 304 } ethtool_test_keys[TG3_NUM_TEST] = {
 305         { "nvram test     (online) " },
 306         { "link test      (online) " },
 307         { "register test  (offline)" },
 308         { "memory test    (offline)" },
 309         { "loopback test  (offline)" },
 310         { "interrupt test (offline)" },
 311 };
 312
 313 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 314 {
 315         writel(val, tp->regs + off);
 316 }
 317
 318 static u32 tg3_read32(struct tg3 *tp, u32 off)
 319 {
 320         return (readl(tp->regs + off));
 321 }
 322
 323 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 324 {
 325         writel(val, tp->aperegs + off);
 326 }
 327
 328 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 329 {
 330         return (readl(tp->aperegs + off));
 331 }
 332
 333 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 334 {
 335         unsigned long flags;
 336
 337         spin_lock_irqsave(&tp->indirect_lock, flags);
 338         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 339         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 340         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 341 }
 342
 343 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         writel(val, tp->regs + off);
 346         readl(tp->regs + off);
 347 }
 348
 349 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 350 {
 351         unsigned long flags;
 352         u32 val;
 353
 354         spin_lock_irqsave(&tp->indirect_lock, flags);
 355         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 356         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 357         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 358         return val;
 359 }
 360
 361 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 362 {
 363         unsigned long flags;
 364
 365         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 366                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 367                                        TG3_64BIT_REG_LOW, val);
 368                 return;
 369         }
 370         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 371                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 372                                        TG3_64BIT_REG_LOW, val);
 373                 return;
 374         }
 375
 376         spin_lock_irqsave(&tp->indirect_lock, flags);
 377         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 378         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 379         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 380
 381         /* In indirect mode when disabling interrupts, we also need
 382          * to clear the interrupt bit in the GRC local ctrl register.
 383          */
 384         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 385             (val == 0x1)) {
 386                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 387                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 388         }
 389 }
 390
 391 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 392 {
 393         unsigned long flags;
 394         u32 val;
 395
 396         spin_lock_irqsave(&tp->indirect_lock, flags);
 397         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 398         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 399         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 400         return val;
 401 }
 402
 403 /* usec_wait specifies the wait time in usec when writing to certain registers
 404  * where it is unsafe to read back the register without some delay.
 405  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 406  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 407  */
 408 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 409 {
 410         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 411             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 412                 /* Non-posted methods */
 413                 tp->write32(tp, off, val);
 414         else {
 415                 /* Posted method */
 416                 tg3_write32(tp, off, val);
 417                 if (usec_wait)
 418                         udelay(usec_wait);
 419                 tp->read32(tp, off);
 420         }
 421         /* Wait again after the read for the posted method to guarantee that
 422          * the wait time is met.
 423          */
 424         if (usec_wait)
 425                 udelay(usec_wait);
 426 }
 427
 428 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 429 {
 430         tp->write32_mbox(tp, off, val);
 431         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 432             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 433                 tp->read32_mbox(tp, off);
 434 }
 435
 436 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 437 {
 438         void __iomem *mbox = tp->regs + off;
 439         writel(val, mbox);
 440         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 441                 writel(val, mbox);
 442         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 443                 readl(mbox);
 444 }
 445
 446 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 447 {
 448         return (readl(tp->regs + off + GRCMBOX_BASE));
 449 }
 450
 451 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 452 {
 453         writel(val, tp->regs + off + GRCMBOX_BASE);
 454 }
 455
 456 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 457 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 458 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 459 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 460 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 461
 462 #define tw32(reg,val)           tp->write32(tp, reg, val)
 463 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 464 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 465 #define tr32(reg)               tp->read32(tp, reg)
 466
 467 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 468 {
 469         unsigned long flags;
 470
 471         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 472             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 473                 return;
 474
 475         spin_lock_irqsave(&tp->indirect_lock, flags);
 476         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 477                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 478                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 479
 480                 /* Always leave this as zero. */
 481                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 482         } else {
 483                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 484                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 485
 486                 /* Always leave this as zero. */
 487                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 488         }
 489         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 490 }
 491
 492 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 493 {
 494         unsigned long flags;
 495
 496         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 497             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 498                 *val = 0;
 499                 return;
 500         }
 501
 502         spin_lock_irqsave(&tp->indirect_lock, flags);
 503         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 504                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 505                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 506
 507                 /* Always leave this as zero. */
 508                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 509         } else {
 510                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 511                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 512
 513                 /* Always leave this as zero. */
 514                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 515         }
 516         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 517 }
 518
 519 static void tg3_ape_lock_init(struct tg3 *tp)
 520 {
 521         int i;
 522
 523         /* Make sure the driver hasn't any stale locks. */
 524         for (i = 0; i < 8; i++)
 525                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
 526                                 APE_LOCK_GRANT_DRIVER);
 527 }
 528
 529 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 530 {
 531         int i, off;
 532         int ret = 0;
 533         u32 status;
 534
 535         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 536                 return 0;
 537
 538         switch (locknum) {
 539                 case TG3_APE_LOCK_MEM:
 540                         break;
 541                 default:
 542                         return -EINVAL;
 543         }
 544
 545         off = 4 * locknum;
 546
 547         tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
 548
 549         /* Wait for up to 1 millisecond to acquire lock. */
 550         for (i = 0; i < 100; i++) {
 551                 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
 552                 if (status == APE_LOCK_GRANT_DRIVER)
 553                         break;
 554                 udelay(10);
 555         }
 556
 557         if (status != APE_LOCK_GRANT_DRIVER) {
 558                 /* Revoke the lock request. */
 559                 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
 560                                 APE_LOCK_GRANT_DRIVER);
 561
 562                 ret = -EBUSY;
 563         }
 564
 565         return ret;
 566 }
 567
 568 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 569 {
 570         int off;
 571
 572         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 573                 return;
 574
 575         switch (locknum) {
 576                 case TG3_APE_LOCK_MEM:
 577                         break;
 578                 default:
 579                         return;
 580         }
 581
 582         off = 4 * locknum;
 583         tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
 584 }
 585
 586 static void tg3_disable_ints(struct tg3 *tp)
 587 {
 588         tw32(TG3PCI_MISC_HOST_CTRL,
 589              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 590         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 591 }
 592
 593 static inline void tg3_cond_int(struct tg3 *tp)
 594 {
 595         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 596             (tp->hw_status->status & SD_STATUS_UPDATED))
 597                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 598         else
 599                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 600                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 601 }
 602
 603 static void tg3_enable_ints(struct tg3 *tp)
 604 {
 605         tp->irq_sync = 0;
 606         wmb();
 607
 608         tw32(TG3PCI_MISC_HOST_CTRL,
 609              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 610         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 611                        (tp->last_tag << 24));
 612         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 613                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 614                                (tp->last_tag << 24));
 615         tg3_cond_int(tp);
 616 }
 617
 618 static inline unsigned int tg3_has_work(struct tg3 *tp)
 619 {
 620         struct tg3_hw_status *sblk = tp->hw_status;
 621         unsigned int work_exists = 0;
 622
 623         /* check for phy events */
 624         if (!(tp->tg3_flags &
 625               (TG3_FLAG_USE_LINKCHG_REG |
 626                TG3_FLAG_POLL_SERDES))) {
 627                 if (sblk->status & SD_STATUS_LINK_CHG)
 628                         work_exists = 1;
 629         }
 630         /* check for RX/TX work to do */
 631         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 632             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 633                 work_exists = 1;
 634
 635         return work_exists;
 636 }
 637
 638 /* tg3_restart_ints
 639  *  similar to tg3_enable_ints, but it accurately determines whether there
 640  *  is new work pending and can return without flushing the PIO write
 641  *  which reenables interrupts
 642  */
 643 static void tg3_restart_ints(struct tg3 *tp)
 644 {
 645         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 646                      tp->last_tag << 24);
 647         mmiowb();
 648
 649         /* When doing tagged status, this work check is unnecessary.
 650          * The last_tag we write above tells the chip which piece of
 651          * work we've completed.
 652          */
 653         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 654             tg3_has_work(tp))
 655                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 656                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 657 }
 658
 659 static inline void tg3_netif_stop(struct tg3 *tp)
 660 {
 661         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 662         napi_disable(&tp->napi);
 663         netif_tx_disable(tp->dev);
 664 }
 665
 666 static inline void tg3_netif_start(struct tg3 *tp)
 667 {
 668         netif_wake_queue(tp->dev);
 669         /* NOTE: unconditional netif_wake_queue is only appropriate
 670          * so long as all callers are assured to have free tx slots
 671          * (such as after tg3_init_hw)
 672          */
 673         napi_enable(&tp->napi);
 674         tp->hw_status->status |= SD_STATUS_UPDATED;
 675         tg3_enable_ints(tp);
 676 }
 677
 678 static void tg3_switch_clocks(struct tg3 *tp)
 679 {
 680         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 681         u32 orig_clock_ctrl;
 682
 683         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 684             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 685                 return;
 686
 687         orig_clock_ctrl = clock_ctrl;
 688         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 689                        CLOCK_CTRL_CLKRUN_OENABLE |
 690                        0x1f);
 691         tp->pci_clock_ctrl = clock_ctrl;
 692
 693         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 694                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 695                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 696                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 697                 }
 698         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 699                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 700                             clock_ctrl |
 701                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 702                             40);
 703                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 704                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 705                             40);
 706         }
 707         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 708 }
 709
 710 #define PHY_BUSY_LOOPS  5000
 711
 712 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 713 {
 714         u32 frame_val;
 715         unsigned int loops;
 716         int ret;
 717
 718         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 719                 tw32_f(MAC_MI_MODE,
 720                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 721                 udelay(80);
 722         }
 723
 724         *val = 0x0;
 725
 726         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 727                       MI_COM_PHY_ADDR_MASK);
 728         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 729                       MI_COM_REG_ADDR_MASK);
 730         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 731
 732         tw32_f(MAC_MI_COM, frame_val);
 733
 734         loops = PHY_BUSY_LOOPS;
 735         while (loops != 0) {
 736                 udelay(10);
 737                 frame_val = tr32(MAC_MI_COM);
 738
 739                 if ((frame_val & MI_COM_BUSY) == 0) {
 740                         udelay(5);
 741                         frame_val = tr32(MAC_MI_COM);
 742                         break;
 743                 }
 744                 loops -= 1;
 745         }
 746
 747         ret = -EBUSY;
 748         if (loops != 0) {
 749                 *val = frame_val & MI_COM_DATA_MASK;
 750                 ret = 0;
 751         }
 752
 753         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 754                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 755                 udelay(80);
 756         }
 757
 758         return ret;
 759 }
 760
 761 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 762 {
 763         u32 frame_val;
 764         unsigned int loops;
 765         int ret;
 766
 767         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 768             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 769                 return 0;
 770
 771         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 772                 tw32_f(MAC_MI_MODE,
 773                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 774                 udelay(80);
 775         }
 776
 777         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 778                       MI_COM_PHY_ADDR_MASK);
 779         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 780                       MI_COM_REG_ADDR_MASK);
 781         frame_val |= (val & MI_COM_DATA_MASK);
 782         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 783
 784         tw32_f(MAC_MI_COM, frame_val);
 785
 786         loops = PHY_BUSY_LOOPS;
 787         while (loops != 0) {
 788                 udelay(10);
 789                 frame_val = tr32(MAC_MI_COM);
 790                 if ((frame_val & MI_COM_BUSY) == 0) {
 791                         udelay(5);
 792                         frame_val = tr32(MAC_MI_COM);
 793                         break;
 794                 }
 795                 loops -= 1;
 796         }
 797
 798         ret = -EBUSY;
 799         if (loops != 0)
 800                 ret = 0;
 801
 802         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 803                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 804                 udelay(80);
 805         }
 806
 807         return ret;
 808 }
 809
 810 static int tg3_bmcr_reset(struct tg3 *tp)
 811 {
 812         u32 phy_control;
 813         int limit, err;
 814
 815         /* OK, reset it, and poll the BMCR_RESET bit until it
 816          * clears or we time out.
 817          */
 818         phy_control = BMCR_RESET;
 819         err = tg3_writephy(tp, MII_BMCR, phy_control);
 820         if (err != 0)
 821                 return -EBUSY;
 822
 823         limit = 5000;
 824         while (limit--) {
 825                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 826                 if (err != 0)
 827                         return -EBUSY;
 828
 829                 if ((phy_control & BMCR_RESET) == 0) {
 830                         udelay(40);
 831                         break;
 832                 }
 833                 udelay(10);
 834         }
 835         if (limit <= 0)
 836                 return -EBUSY;
 837
 838         return 0;
 839 }
 840
 841 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 842 {
 843         struct tg3 *tp = (struct tg3 *)bp->priv;
 844         u32 val;
 845
 846         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 847                 return -EAGAIN;
 848
 849         if (tg3_readphy(tp, reg, &val))
 850                 return -EIO;
 851
 852         return val;
 853 }
 854
 855 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 856 {
 857         struct tg3 *tp = (struct tg3 *)bp->priv;
 858
 859         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_PAUSED)
 860                 return -EAGAIN;
 861
 862         if (tg3_writephy(tp, reg, val))
 863                 return -EIO;
 864
 865         return 0;
 866 }
 867
 868 static int tg3_mdio_reset(struct mii_bus *bp)
 869 {
 870         return 0;
 871 }
 872
 873 static void tg3_mdio_config(struct tg3 *tp)
 874 {
 875         u32 val;
 876
 877         if (tp->mdio_bus.phy_map[PHY_ADDR]->interface !=
 878             PHY_INTERFACE_MODE_RGMII)
 879                 return;
 880
 881         val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |
 882                                     MAC_PHYCFG1_RGMII_SND_STAT_EN);
 883         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 884                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 885                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
 886                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 887                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
 888         }
 889         tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);
 890
 891         val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);
 892         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
 893                 val |= MAC_PHYCFG2_INBAND_ENABLE;
 894         tw32(MAC_PHYCFG2, val);
 895
 896         val = tr32(MAC_EXT_RGMII_MODE);
 897         val &= ~(MAC_RGMII_MODE_RX_INT_B |
 898                  MAC_RGMII_MODE_RX_QUALITY |
 899                  MAC_RGMII_MODE_RX_ACTIVITY |
 900                  MAC_RGMII_MODE_RX_ENG_DET |
 901                  MAC_RGMII_MODE_TX_ENABLE |
 902                  MAC_RGMII_MODE_TX_LOWPWR |
 903                  MAC_RGMII_MODE_TX_RESET);
 904         if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {
 905                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 906                         val |= MAC_RGMII_MODE_RX_INT_B |
 907                                MAC_RGMII_MODE_RX_QUALITY |
 908                                MAC_RGMII_MODE_RX_ACTIVITY |
 909                                MAC_RGMII_MODE_RX_ENG_DET;
 910                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 911                         val |= MAC_RGMII_MODE_TX_ENABLE |
 912                                MAC_RGMII_MODE_TX_LOWPWR |
 913                                MAC_RGMII_MODE_TX_RESET;
 914         }
 915         tw32(MAC_EXT_RGMII_MODE, val);
 916 }
 917
 918 static void tg3_mdio_start(struct tg3 *tp)
 919 {
 920         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 921                 mutex_lock(&tp->mdio_bus.mdio_lock);
 922                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
 923                 mutex_unlock(&tp->mdio_bus.mdio_lock);
 924         }
 925
 926         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
 927         tw32_f(MAC_MI_MODE, tp->mi_mode);
 928         udelay(80);
 929
 930         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)
 931                 tg3_mdio_config(tp);
 932 }
 933
 934 static void tg3_mdio_stop(struct tg3 *tp)
 935 {
 936         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
 937                 mutex_lock(&tp->mdio_bus.mdio_lock);
 938                 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_PAUSED;
 939                 mutex_unlock(&tp->mdio_bus.mdio_lock);
 940         }
 941 }
 942
 943 static int tg3_mdio_init(struct tg3 *tp)
 944 {
 945         int i;
 946         u32 reg;
 947         struct phy_device *phydev;
 948         struct mii_bus *mdio_bus = &tp->mdio_bus;
 949
 950         tg3_mdio_start(tp);
 951
 952         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
 953             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
 954                 return 0;
 955
 956         memset(mdio_bus, 0, sizeof(*mdio_bus));
 957
 958         mdio_bus->name     = "tg3 mdio bus";
 959         snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%x",
 960                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
 961         mdio_bus->priv     = tp;
 962         mdio_bus->dev      = &tp->pdev->dev;
 963         mdio_bus->read     = &tg3_mdio_read;
 964         mdio_bus->write    = &tg3_mdio_write;
 965         mdio_bus->reset    = &tg3_mdio_reset;
 966         mdio_bus->phy_mask = ~(1 << PHY_ADDR);
 967         mdio_bus->irq      = &tp->mdio_irq[0];
 968
 969         for (i = 0; i < PHY_MAX_ADDR; i++)
 970                 mdio_bus->irq[i] = PHY_POLL;
 971
 972         /* The bus registration will look for all the PHYs on the mdio bus.
 973          * Unfortunately, it does not ensure the PHY is powered up before
 974          * accessing the PHY ID registers.  A chip reset is the
 975          * quickest way to bring the device back to an operational state..
 976          */
 977         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
 978                 tg3_bmcr_reset(tp);
 979
 980         i = mdiobus_register(mdio_bus);
 981         if (i) {
 982                 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
 983                         tp->dev->name, i);
 984                 return i;
 985         }
 986
 987         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
 988
 989         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
 990
 991         switch (phydev->phy_id) {
 992         case TG3_PHY_ID_BCM50610:
 993                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
 994                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
 995                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
 996                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
 997                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
 998                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
 999                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1000                 break;
1001         case TG3_PHY_ID_BCMAC131:
1002                 phydev->interface = PHY_INTERFACE_MODE_MII;
1003                 break;
1004         }
1005
1006         tg3_mdio_config(tp);
1007
1008         return 0;
1009 }
1010
1011 static void tg3_mdio_fini(struct tg3 *tp)
1012 {
1013         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1014                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1015                 mdiobus_unregister(&tp->mdio_bus);
1016                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_PAUSED;
1017         }
1018 }
1019
1020 /* tp->lock is held. */
1021 static void tg3_wait_for_event_ack(struct tg3 *tp)
1022 {
1023         int i;
1024
1025         /* Wait for up to 2.5 milliseconds */
1026         for (i = 0; i < 250000; i++) {
1027                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1028                         break;
1029                 udelay(10);
1030         }
1031 }
1032
1033 /* tp->lock is held. */
1034 static void tg3_ump_link_report(struct tg3 *tp)
1035 {
1036         u32 reg;
1037         u32 val;
1038
1039         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1040             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1041                 return;
1042
1043         tg3_wait_for_event_ack(tp);
1044
1045         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1046
1047         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1048
1049         val = 0;
1050         if (!tg3_readphy(tp, MII_BMCR, &reg))
1051                 val = reg << 16;
1052         if (!tg3_readphy(tp, MII_BMSR, &reg))
1053                 val |= (reg & 0xffff);
1054         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1055
1056         val = 0;
1057         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1058                 val = reg << 16;
1059         if (!tg3_readphy(tp, MII_LPA, &reg))
1060                 val |= (reg & 0xffff);
1061         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1062
1063         val = 0;
1064         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1065                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1066                         val = reg << 16;
1067                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1068                         val |= (reg & 0xffff);
1069         }
1070         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1071
1072         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1073                 val = reg << 16;
1074         else
1075                 val = 0;
1076         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1077
1078         val = tr32(GRC_RX_CPU_EVENT);
1079         val |= GRC_RX_CPU_DRIVER_EVENT;
1080         tw32_f(GRC_RX_CPU_EVENT, val);
1081 }
1082
1083 static void tg3_link_report(struct tg3 *tp)
1084 {
1085         if (!netif_carrier_ok(tp->dev)) {
1086                 if (netif_msg_link(tp))
1087                         printk(KERN_INFO PFX "%s: Link is down.\n",
1088                                tp->dev->name);
1089                 tg3_ump_link_report(tp);
1090         } else if (netif_msg_link(tp)) {
1091                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1092                        tp->dev->name,
1093                        (tp->link_config.active_speed == SPEED_1000 ?
1094                         1000 :
1095                         (tp->link_config.active_speed == SPEED_100 ?
1096                          100 : 10)),
1097                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1098                         "full" : "half"));
1099
1100                 printk(KERN_INFO PFX
1101                        "%s: Flow control is %s for TX and %s for RX.\n",
1102                        tp->dev->name,
1103                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX) ?
1104                        "on" : "off",
1105                        (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX) ?
1106                        "on" : "off");
1107                 tg3_ump_link_report(tp);
1108         }
1109 }
1110
1111 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1112 {
1113         u16 miireg;
1114
1115         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1116                 miireg = ADVERTISE_PAUSE_CAP;
1117         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1118                 miireg = ADVERTISE_PAUSE_ASYM;
1119         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1120                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1121         else
1122                 miireg = 0;
1123
1124         return miireg;
1125 }
1126
1127 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1128 {
1129         u16 miireg;
1130
1131         if ((flow_ctrl & TG3_FLOW_CTRL_TX) && (flow_ctrl & TG3_FLOW_CTRL_RX))
1132                 miireg = ADVERTISE_1000XPAUSE;
1133         else if (flow_ctrl & TG3_FLOW_CTRL_TX)
1134                 miireg = ADVERTISE_1000XPSE_ASYM;
1135         else if (flow_ctrl & TG3_FLOW_CTRL_RX)
1136                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1137         else
1138                 miireg = 0;
1139
1140         return miireg;
1141 }
1142
1143 static u8 tg3_resolve_flowctrl_1000T(u16 lcladv, u16 rmtadv)
1144 {
1145         u8 cap = 0;
1146
1147         if (lcladv & ADVERTISE_PAUSE_CAP) {
1148                 if (lcladv & ADVERTISE_PAUSE_ASYM) {
1149                         if (rmtadv & LPA_PAUSE_CAP)
1150                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1151                         else if (rmtadv & LPA_PAUSE_ASYM)
1152                                 cap = TG3_FLOW_CTRL_RX;
1153                 } else {
1154                         if (rmtadv & LPA_PAUSE_CAP)
1155                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1156                 }
1157         } else if (lcladv & ADVERTISE_PAUSE_ASYM) {
1158                 if ((rmtadv & LPA_PAUSE_CAP) && (rmtadv & LPA_PAUSE_ASYM))
1159                         cap = TG3_FLOW_CTRL_TX;
1160         }
1161
1162         return cap;
1163 }
1164
1165 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1166 {
1167         u8 cap = 0;
1168
1169         if (lcladv & ADVERTISE_1000XPAUSE) {
1170                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1171                         if (rmtadv & LPA_1000XPAUSE)
1172                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1173                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1174                                 cap = TG3_FLOW_CTRL_RX;
1175                 } else {
1176                         if (rmtadv & LPA_1000XPAUSE)
1177                                 cap = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
1178                 }
1179         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1180                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1181                         cap = TG3_FLOW_CTRL_TX;
1182         }
1183
1184         return cap;
1185 }
1186
1187 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1188 {
1189         u8 autoneg;
1190         u8 flowctrl = 0;
1191         u32 old_rx_mode = tp->rx_mode;
1192         u32 old_tx_mode = tp->tx_mode;
1193
1194         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1195                 autoneg = tp->mdio_bus.phy_map[PHY_ADDR]->autoneg;
1196         else
1197                 autoneg = tp->link_config.autoneg;
1198
1199         if (autoneg == AUTONEG_ENABLE &&
1200             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1201                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1202                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1203                 else
1204                         flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv);
1205         } else
1206                 flowctrl = tp->link_config.flowctrl;
1207
1208         tp->link_config.active_flowctrl = flowctrl;
1209
1210         if (flowctrl & TG3_FLOW_CTRL_RX)
1211                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1212         else
1213                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1214
1215         if (old_rx_mode != tp->rx_mode)
1216                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1217
1218         if (flowctrl & TG3_FLOW_CTRL_TX)
1219                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1220         else
1221                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1222
1223         if (old_tx_mode != tp->tx_mode)
1224                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1225 }
1226
1227 static void tg3_adjust_link(struct net_device *dev)
1228 {
1229         u8 oldflowctrl, linkmesg = 0;
1230         u32 mac_mode, lcl_adv, rmt_adv;
1231         struct tg3 *tp = netdev_priv(dev);
1232         struct phy_device *phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1233
1234         spin_lock(&tp->lock);
1235
1236         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1237                                     MAC_MODE_HALF_DUPLEX);
1238
1239         oldflowctrl = tp->link_config.active_flowctrl;
1240
1241         if (phydev->link) {
1242                 lcl_adv = 0;
1243                 rmt_adv = 0;
1244
1245                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1246                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1247                 else
1248                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1249
1250                 if (phydev->duplex == DUPLEX_HALF)
1251                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1252                 else {
1253                         lcl_adv = tg3_advert_flowctrl_1000T(
1254                                   tp->link_config.flowctrl);
1255
1256                         if (phydev->pause)
1257                                 rmt_adv = LPA_PAUSE_CAP;
1258                         if (phydev->asym_pause)
1259                                 rmt_adv |= LPA_PAUSE_ASYM;
1260                 }
1261
1262                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1263         } else
1264                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1265
1266         if (mac_mode != tp->mac_mode) {
1267                 tp->mac_mode = mac_mode;
1268                 tw32_f(MAC_MODE, tp->mac_mode);
1269                 udelay(40);
1270         }
1271
1272         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1273                 tw32(MAC_TX_LENGTHS,
1274                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1275                       (6 << TX_LENGTHS_IPG_SHIFT) |
1276                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1277         else
1278                 tw32(MAC_TX_LENGTHS,
1279                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1280                       (6 << TX_LENGTHS_IPG_SHIFT) |
1281                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1282
1283         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1284             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1285             phydev->speed != tp->link_config.active_speed ||
1286             phydev->duplex != tp->link_config.active_duplex ||
1287             oldflowctrl != tp->link_config.active_flowctrl)
1288             linkmesg = 1;
1289
1290         tp->link_config.active_speed = phydev->speed;
1291         tp->link_config.active_duplex = phydev->duplex;
1292
1293         spin_unlock(&tp->lock);
1294
1295         if (linkmesg)
1296                 tg3_link_report(tp);
1297 }
1298
1299 static int tg3_phy_init(struct tg3 *tp)
1300 {
1301         struct phy_device *phydev;
1302
1303         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1304                 return 0;
1305
1306         /* Bring the PHY back to a known state. */
1307         tg3_bmcr_reset(tp);
1308
1309         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1310
1311         /* Attach the MAC to the PHY. */
1312         phydev = phy_connect(tp->dev, phydev->dev.bus_id, tg3_adjust_link,
1313                              phydev->dev_flags, phydev->interface);
1314         if (IS_ERR(phydev)) {
1315                 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1316                 return PTR_ERR(phydev);
1317         }
1318
1319         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1320
1321         /* Mask with MAC supported features. */
1322         phydev->supported &= (PHY_GBIT_FEATURES |
1323                               SUPPORTED_Pause |
1324                               SUPPORTED_Asym_Pause);
1325
1326         phydev->advertising = phydev->supported;
1327
1328         printk(KERN_INFO
1329                "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1330                tp->dev->name, phydev->drv->name, phydev->dev.bus_id);
1331
1332         return 0;
1333 }
1334
1335 static void tg3_phy_start(struct tg3 *tp)
1336 {
1337         struct phy_device *phydev;
1338
1339         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1340                 return;
1341
1342         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
1343
1344         if (tp->link_config.phy_is_low_power) {
1345                 tp->link_config.phy_is_low_power = 0;
1346                 phydev->speed = tp->link_config.orig_speed;
1347                 phydev->duplex = tp->link_config.orig_duplex;
1348                 phydev->autoneg = tp->link_config.orig_autoneg;
1349                 phydev->advertising = tp->link_config.orig_advertising;
1350         }
1351
1352         phy_start(phydev);
1353
1354         phy_start_aneg(phydev);
1355 }
1356
1357 static void tg3_phy_stop(struct tg3 *tp)
1358 {
1359         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1360                 return;
1361
1362         phy_stop(tp->mdio_bus.phy_map[PHY_ADDR]);
1363 }
1364
1365 static void tg3_phy_fini(struct tg3 *tp)
1366 {
1367         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1368                 phy_disconnect(tp->mdio_bus.phy_map[PHY_ADDR]);
1369                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1370         }
1371 }
1372
1373 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1374 {
1375         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1376         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1377 }
1378
1379 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1380 {
1381         u32 phy;
1382
1383         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1384             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1385                 return;
1386
1387         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1388                 u32 ephy;
1389
1390                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
1391                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1392                                      ephy | MII_TG3_EPHY_SHADOW_EN);
1393                         if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
1394                                 if (enable)
1395                                         phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
1396                                 else
1397                                         phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
1398                                 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
1399                         }
1400                         tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
1401                 }
1402         } else {
1403                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1404                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1405                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1406                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1407                         if (enable)
1408                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1409                         else
1410                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1411                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1412                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1413                 }
1414         }
1415 }
1416
1417 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1418 {
1419         u32 val;
1420
1421         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1422                 return;
1423
1424         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1425             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1426                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1427                              (val | (1 << 15) | (1 << 4)));
1428 }
1429
1430 static void tg3_phy_apply_otp(struct tg3 *tp)
1431 {
1432         u32 otp, phy;
1433
1434         if (!tp->phy_otp)
1435                 return;
1436
1437         otp = tp->phy_otp;
1438
1439         /* Enable SM_DSP clock and tx 6dB coding. */
1440         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1441               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1442               MII_TG3_AUXCTL_ACTL_TX_6DB;
1443         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1444
1445         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1446         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1447         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1448
1449         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1450               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1451         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1452
1453         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1454         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1455         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1456
1457         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1458         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1459
1460         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1461         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1462
1463         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1464               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1465         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1466
1467         /* Turn off SM_DSP clock. */
1468         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1469               MII_TG3_AUXCTL_ACTL_TX_6DB;
1470         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1471 }
1472
1473 static int tg3_wait_macro_done(struct tg3 *tp)
1474 {
1475         int limit = 100;
1476
1477         while (limit--) {
1478                 u32 tmp32;
1479
1480                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1481                         if ((tmp32 & 0x1000) == 0)
1482                                 break;
1483                 }
1484         }
1485         if (limit <= 0)
1486                 return -EBUSY;
1487
1488         return 0;
1489 }
1490
1491 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1492 {
1493         static const u32 test_pat[4][6] = {
1494         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1495         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1496         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1497         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1498         };
1499         int chan;
1500
1501         for (chan = 0; chan < 4; chan++) {
1502                 int i;
1503
1504                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1505                              (chan * 0x2000) | 0x0200);
1506                 tg3_writephy(tp, 0x16, 0x0002);
1507
1508                 for (i = 0; i < 6; i++)
1509                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1510                                      test_pat[chan][i]);
1511
1512                 tg3_writephy(tp, 0x16, 0x0202);
1513                 if (tg3_wait_macro_done(tp)) {
1514                         *resetp = 1;
1515                         return -EBUSY;
1516                 }
1517
1518                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1519                              (chan * 0x2000) | 0x0200);
1520                 tg3_writephy(tp, 0x16, 0x0082);
1521                 if (tg3_wait_macro_done(tp)) {
1522                         *resetp = 1;
1523                         return -EBUSY;
1524                 }
1525
1526                 tg3_writephy(tp, 0x16, 0x0802);
1527                 if (tg3_wait_macro_done(tp)) {
1528                         *resetp = 1;
1529                         return -EBUSY;
1530                 }
1531
1532                 for (i = 0; i < 6; i += 2) {
1533                         u32 low, high;
1534
1535                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1536                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1537                             tg3_wait_macro_done(tp)) {
1538                                 *resetp = 1;
1539                                 return -EBUSY;
1540                         }
1541                         low &= 0x7fff;
1542                         high &= 0x000f;
1543                         if (low != test_pat[chan][i] ||
1544                             high != test_pat[chan][i+1]) {
1545                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1546                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1547                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1548
1549                                 return -EBUSY;
1550                         }
1551                 }
1552         }
1553
1554         return 0;
1555 }
1556
1557 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1558 {
1559         int chan;
1560
1561         for (chan = 0; chan < 4; chan++) {
1562                 int i;
1563
1564                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1565                              (chan * 0x2000) | 0x0200);
1566                 tg3_writephy(tp, 0x16, 0x0002);
1567                 for (i = 0; i < 6; i++)
1568                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1569                 tg3_writephy(tp, 0x16, 0x0202);
1570                 if (tg3_wait_macro_done(tp))
1571                         return -EBUSY;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1578 {
1579         u32 reg32, phy9_orig;
1580         int retries, do_phy_reset, err;
1581
1582         retries = 10;
1583         do_phy_reset = 1;
1584         do {
1585                 if (do_phy_reset) {
1586                         err = tg3_bmcr_reset(tp);
1587                         if (err)
1588                                 return err;
1589                         do_phy_reset = 0;
1590                 }
1591
1592                 /* Disable transmitter and interrupt.  */
1593                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1594                         continue;
1595
1596                 reg32 |= 0x3000;
1597                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1598
1599                 /* Set full-duplex, 1000 mbps.  */
1600                 tg3_writephy(tp, MII_BMCR,
1601                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1602
1603                 /* Set to master mode.  */
1604                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1605                         continue;
1606
1607                 tg3_writephy(tp, MII_TG3_CTRL,
1608                              (MII_TG3_CTRL_AS_MASTER |
1609                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1610
1611                 /* Enable SM_DSP_CLOCK and 6dB.  */
1612                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1613
1614                 /* Block the PHY control access.  */
1615                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1616                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1617
1618                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1619                 if (!err)
1620                         break;
1621         } while (--retries);
1622
1623         err = tg3_phy_reset_chanpat(tp);
1624         if (err)
1625                 return err;
1626
1627         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1628         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1629
1630         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1631         tg3_writephy(tp, 0x16, 0x0000);
1632
1633         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1634             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1635                 /* Set Extended packet length bit for jumbo frames */
1636                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1637         }
1638         else {
1639                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1640         }
1641
1642         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1643
1644         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1645                 reg32 &= ~0x3000;
1646                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1647         } else if (!err)
1648                 err = -EBUSY;
1649
1650         return err;
1651 }
1652
1653 /* This will reset the tigon3 PHY if there is no valid
1654  * link unless the FORCE argument is non-zero.
1655  */
1656 static int tg3_phy_reset(struct tg3 *tp)
1657 {
1658         u32 cpmuctrl;
1659         u32 phy_status;
1660         int err;
1661
1662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1663                 u32 val;
1664
1665                 val = tr32(GRC_MISC_CFG);
1666                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1667                 udelay(40);
1668         }
1669         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1670         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1671         if (err != 0)
1672                 return -EBUSY;
1673
1674         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1675                 netif_carrier_off(tp->dev);
1676                 tg3_link_report(tp);
1677         }
1678
1679         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1680             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1681             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1682                 err = tg3_phy_reset_5703_4_5(tp);
1683                 if (err)
1684                         return err;
1685                 goto out;
1686         }
1687
1688         cpmuctrl = 0;
1689         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1690             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1691                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1692                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1693                         tw32(TG3_CPMU_CTRL,
1694                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1695         }
1696
1697         err = tg3_bmcr_reset(tp);
1698         if (err)
1699                 return err;
1700
1701         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1702                 u32 phy;
1703
1704                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1705                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1706
1707                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1708         }
1709
1710         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1711                 u32 val;
1712
1713                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1714                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1715                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1716                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1717                         udelay(40);
1718                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1719                 }
1720
1721                 /* Disable GPHY autopowerdown. */
1722                 tg3_writephy(tp, MII_TG3_MISC_SHDW,
1723                              MII_TG3_MISC_SHDW_WREN |
1724                              MII_TG3_MISC_SHDW_APD_SEL |
1725                              MII_TG3_MISC_SHDW_APD_WKTM_84MS);
1726         }
1727
1728         tg3_phy_apply_otp(tp);
1729
1730 out:
1731         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1732                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1733                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1734                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1735                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1736                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1737                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1738         }
1739         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1740                 tg3_writephy(tp, 0x1c, 0x8d68);
1741                 tg3_writephy(tp, 0x1c, 0x8d68);
1742         }
1743         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1744                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1745                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1746                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1747                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1748                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1749                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1750                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1751                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1752         }
1753         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1754                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1755                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1756                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1757                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1758                         tg3_writephy(tp, MII_TG3_TEST1,
1759                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1760                 } else
1761                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1762                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1763         }
1764         /* Set Extended packet length bit (bit 14) on all chips that */
1765         /* support jumbo frames */
1766         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1767                 /* Cannot do read-modify-write on 5401 */
1768                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1769         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1770                 u32 phy_reg;
1771
1772                 /* Set bit 14 with read-modify-write to preserve other bits */
1773                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1774                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1775                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1776         }
1777
1778         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1779          * jumbo frames transmission.
1780          */
1781         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1782                 u32 phy_reg;
1783
1784                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1785                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1786                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1787         }
1788
1789         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1790                 /* adjust output voltage */
1791                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1792         }
1793
1794         tg3_phy_toggle_automdix(tp, 1);
1795         tg3_phy_set_wirespeed(tp);
1796         return 0;
1797 }
1798
1799 static void tg3_frob_aux_power(struct tg3 *tp)
1800 {
1801         struct tg3 *tp_peer = tp;
1802
1803         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1804                 return;
1805
1806         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1807             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1808                 struct net_device *dev_peer;
1809
1810                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1811                 /* remove_one() may have been run on the peer. */
1812                 if (!dev_peer)
1813                         tp_peer = tp;
1814                 else
1815                         tp_peer = netdev_priv(dev_peer);
1816         }
1817
1818         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1819             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1820             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1821             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1822                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1823                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1824                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1825                                     (GRC_LCLCTRL_GPIO_OE0 |
1826                                      GRC_LCLCTRL_GPIO_OE1 |
1827                                      GRC_LCLCTRL_GPIO_OE2 |
1828                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1829                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1830                                     100);
1831                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1832                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1833                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1834                                              GRC_LCLCTRL_GPIO_OE1 |
1835                                              GRC_LCLCTRL_GPIO_OE2 |
1836                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
1837                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
1838                                              tp->grc_local_ctrl;
1839                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1840
1841                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1842                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1843
1844                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1845                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1846                 } else {
1847                         u32 no_gpio2;
1848                         u32 grc_local_ctrl = 0;
1849
1850                         if (tp_peer != tp &&
1851                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1852                                 return;
1853
1854                         /* Workaround to prevent overdrawing Amps. */
1855                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1856                             ASIC_REV_5714) {
1857                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1858                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1859                                             grc_local_ctrl, 100);
1860                         }
1861
1862                         /* On 5753 and variants, GPIO2 cannot be used. */
1863                         no_gpio2 = tp->nic_sram_data_cfg &
1864                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1865
1866                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1867                                          GRC_LCLCTRL_GPIO_OE1 |
1868                                          GRC_LCLCTRL_GPIO_OE2 |
1869                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1870                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1871                         if (no_gpio2) {
1872                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1873                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1874                         }
1875                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1876                                                     grc_local_ctrl, 100);
1877
1878                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1879
1880                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1881                                                     grc_local_ctrl, 100);
1882
1883                         if (!no_gpio2) {
1884                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1885                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1886                                             grc_local_ctrl, 100);
1887                         }
1888                 }
1889         } else {
1890                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1891                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1892                         if (tp_peer != tp &&
1893                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1894                                 return;
1895
1896                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1897                                     (GRC_LCLCTRL_GPIO_OE1 |
1898                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1899
1900                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1901                                     GRC_LCLCTRL_GPIO_OE1, 100);
1902
1903                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1904                                     (GRC_LCLCTRL_GPIO_OE1 |
1905                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1906                 }
1907         }
1908 }
1909
1910 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1911 {
1912         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1913                 return 1;
1914         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1915                 if (speed != SPEED_10)
1916                         return 1;
1917         } else if (speed == SPEED_10)
1918                 return 1;
1919
1920         return 0;
1921 }
1922
1923 static int tg3_setup_phy(struct tg3 *, int);
1924
1925 #define RESET_KIND_SHUTDOWN     0
1926 #define RESET_KIND_INIT         1
1927 #define RESET_KIND_SUSPEND      2
1928
1929 static void tg3_write_sig_post_reset(struct tg3 *, int);
1930 static int tg3_halt_cpu(struct tg3 *, u32);
1931 static int tg3_nvram_lock(struct tg3 *);
1932 static void tg3_nvram_unlock(struct tg3 *);
1933
1934 static void tg3_power_down_phy(struct tg3 *tp)
1935 {
1936         u32 val;
1937
1938         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1939                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1940                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1941                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1942
1943                         sg_dig_ctrl |=
1944                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1945                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1946                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1947                 }
1948                 return;
1949         }
1950
1951         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1952                 tg3_bmcr_reset(tp);
1953                 val = tr32(GRC_MISC_CFG);
1954                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1955                 udelay(40);
1956                 return;
1957         } else if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
1958                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1959                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1961         }
1962
1963         /* The PHY should not be powered down on some chips because
1964          * of bugs.
1965          */
1966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1967             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1968             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1969              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1970                 return;
1971
1972         if (tp->tg3_flags3 & TG3_FLG3_5761_5784_AX_FIXES) {
1973                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1974                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1975                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
1976                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1977         }
1978
1979         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1980 }
1981
1982 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1983 {
1984         u32 misc_host_ctrl;
1985         u16 power_control, power_caps;
1986         int pm = tp->pm_cap;
1987
1988         /* Make sure register accesses (indirect or otherwise)
1989          * will function correctly.
1990          */
1991         pci_write_config_dword(tp->pdev,
1992                                TG3PCI_MISC_HOST_CTRL,
1993                                tp->misc_host_ctrl);
1994
1995         pci_read_config_word(tp->pdev,
1996                              pm + PCI_PM_CTRL,
1997                              &power_control);
1998         power_control |= PCI_PM_CTRL_PME_STATUS;
1999         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
2000         switch (state) {
2001         case PCI_D0:
2002                 power_control |= 0;
2003                 pci_write_config_word(tp->pdev,
2004                                       pm + PCI_PM_CTRL,
2005                                       power_control);
2006                 udelay(100);    /* Delay after power state change */
2007
2008                 /* Switch out of Vaux if it is a NIC */
2009                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2010                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2011
2012                 return 0;
2013
2014         case PCI_D1:
2015                 power_control |= 1;
2016                 break;
2017
2018         case PCI_D2:
2019                 power_control |= 2;
2020                 break;
2021
2022         case PCI_D3hot:
2023                 power_control |= 3;
2024                 break;
2025
2026         default:
2027                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
2028                        "requested.\n",
2029                        tp->dev->name, state);
2030                 return -EINVAL;
2031         }
2032
2033         power_control |= PCI_PM_CTRL_PME_ENABLE;
2034
2035         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2036         tw32(TG3PCI_MISC_HOST_CTRL,
2037              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2038
2039         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2040                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2041                     !tp->link_config.phy_is_low_power) {
2042                         struct phy_device *phydev;
2043                         u32 advertising;
2044
2045                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
2046
2047                         tp->link_config.phy_is_low_power = 1;
2048
2049                         tp->link_config.orig_speed = phydev->speed;
2050                         tp->link_config.orig_duplex = phydev->duplex;
2051                         tp->link_config.orig_autoneg = phydev->autoneg;
2052                         tp->link_config.orig_advertising = phydev->advertising;
2053
2054                         advertising = ADVERTISED_TP |
2055                                       ADVERTISED_Pause |
2056                                       ADVERTISED_Autoneg |
2057                                       ADVERTISED_10baseT_Half;
2058
2059                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2060                             (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
2061                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2062                                         advertising |=
2063                                                 ADVERTISED_100baseT_Half |
2064                                                 ADVERTISED_100baseT_Full |
2065                                                 ADVERTISED_10baseT_Full;
2066                                 else
2067                                         advertising |= ADVERTISED_10baseT_Full;
2068                         }
2069
2070                         phydev->advertising = advertising;
2071
2072                         phy_start_aneg(phydev);
2073                 }
2074         } else {
2075                 if (tp->link_config.phy_is_low_power == 0) {
2076                         tp->link_config.phy_is_low_power = 1;
2077                         tp->link_config.orig_speed = tp->link_config.speed;
2078                         tp->link_config.orig_duplex = tp->link_config.duplex;
2079                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2080                 }
2081
2082                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2083                         tp->link_config.speed = SPEED_10;
2084                         tp->link_config.duplex = DUPLEX_HALF;
2085                         tp->link_config.autoneg = AUTONEG_ENABLE;
2086                         tg3_setup_phy(tp, 0);
2087                 }
2088         }
2089
2090         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2091                 u32 val;
2092
2093                 val = tr32(GRC_VCPU_EXT_CTRL);
2094                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2095         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2096                 int i;
2097                 u32 val;
2098
2099                 for (i = 0; i < 200; i++) {
2100                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2101                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2102                                 break;
2103                         msleep(1);
2104                 }
2105         }
2106         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2107                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2108                                                      WOL_DRV_STATE_SHUTDOWN |
2109                                                      WOL_DRV_WOL |
2110                                                      WOL_SET_MAGIC_PKT);
2111
2112         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
2113
2114         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
2115                 u32 mac_mode;
2116
2117                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2118                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
2119                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2120                                 udelay(40);
2121                         }
2122
2123                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2124                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2125                         else
2126                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2127
2128                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2129                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2130                             ASIC_REV_5700) {
2131                                 u32 speed = (tp->tg3_flags &
2132                                              TG3_FLAG_WOL_SPEED_100MB) ?
2133                                              SPEED_100 : SPEED_10;
2134                                 if (tg3_5700_link_polarity(tp, speed))
2135                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2136                                 else
2137                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2138                         }
2139                 } else {
2140                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2141                 }
2142
2143                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2144                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2145
2146                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
2147                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
2148                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2149
2150                 tw32_f(MAC_MODE, mac_mode);
2151                 udelay(100);
2152
2153                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2154                 udelay(10);
2155         }
2156
2157         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2158             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2159              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2160                 u32 base_val;
2161
2162                 base_val = tp->pci_clock_ctrl;
2163                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2164                              CLOCK_CTRL_TXCLK_DISABLE);
2165
2166                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2167                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2168         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2169                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2170                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2171                 /* do nothing */
2172         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2173                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2174                 u32 newbits1, newbits2;
2175
2176                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2177                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2178                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2179                                     CLOCK_CTRL_TXCLK_DISABLE |
2180                                     CLOCK_CTRL_ALTCLK);
2181                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2182                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2183                         newbits1 = CLOCK_CTRL_625_CORE;
2184                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2185                 } else {
2186                         newbits1 = CLOCK_CTRL_ALTCLK;
2187                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2188                 }
2189
2190                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2191                             40);
2192
2193                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2194                             40);
2195
2196                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2197                         u32 newbits3;
2198
2199                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2200                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2201                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2202                                             CLOCK_CTRL_TXCLK_DISABLE |
2203                                             CLOCK_CTRL_44MHZ_CORE);
2204                         } else {
2205                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2206                         }
2207
2208                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2209                                     tp->pci_clock_ctrl | newbits3, 40);
2210                 }
2211         }
2212
2213         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
2214             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
2215             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
2216                 tg3_power_down_phy(tp);
2217
2218         tg3_frob_aux_power(tp);
2219
2220         /* Workaround for unstable PLL clock */
2221         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2222             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2223                 u32 val = tr32(0x7d00);
2224
2225                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2226                 tw32(0x7d00, val);
2227                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2228                         int err;
2229
2230                         err = tg3_nvram_lock(tp);
2231                         tg3_halt_cpu(tp, RX_CPU_BASE);
2232                         if (!err)
2233                                 tg3_nvram_unlock(tp);
2234                 }
2235         }
2236
2237         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2238
2239         /* Finally, set the new power state. */
2240         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
2241         udelay(100);    /* Delay after power state change */
2242
2243         return 0;
2244 }
2245
2246 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2247 {
2248         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2249         case MII_TG3_AUX_STAT_10HALF:
2250                 *speed = SPEED_10;
2251                 *duplex = DUPLEX_HALF;
2252                 break;
2253
2254         case MII_TG3_AUX_STAT_10FULL:
2255                 *speed = SPEED_10;
2256                 *duplex = DUPLEX_FULL;
2257                 break;
2258
2259         case MII_TG3_AUX_STAT_100HALF:
2260                 *speed = SPEED_100;
2261                 *duplex = DUPLEX_HALF;
2262                 break;
2263
2264         case MII_TG3_AUX_STAT_100FULL:
2265                 *speed = SPEED_100;
2266                 *duplex = DUPLEX_FULL;
2267                 break;
2268
2269         case MII_TG3_AUX_STAT_1000HALF:
2270                 *speed = SPEED_1000;
2271                 *duplex = DUPLEX_HALF;
2272                 break;
2273
2274         case MII_TG3_AUX_STAT_1000FULL:
2275                 *speed = SPEED_1000;
2276                 *duplex = DUPLEX_FULL;
2277                 break;
2278
2279         default:
2280                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2281                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2282                                  SPEED_10;
2283                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2284                                   DUPLEX_HALF;
2285                         break;
2286                 }
2287                 *speed = SPEED_INVALID;
2288                 *duplex = DUPLEX_INVALID;
2289                 break;
2290         }
2291 }
2292
2293 static void tg3_phy_copper_begin(struct tg3 *tp)
2294 {
2295         u32 new_adv;
2296         int i;
2297
2298         if (tp->link_config.phy_is_low_power) {
2299                 /* Entering low power mode.  Disable gigabit and
2300                  * 100baseT advertisements.
2301                  */
2302                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2303
2304                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2305                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2306                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2307                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2308
2309                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2310         } else if (tp->link_config.speed == SPEED_INVALID) {
2311                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2312                         tp->link_config.advertising &=
2313                                 ~(ADVERTISED_1000baseT_Half |
2314                                   ADVERTISED_1000baseT_Full);
2315
2316                 new_adv = ADVERTISE_CSMA;
2317                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2318                         new_adv |= ADVERTISE_10HALF;
2319                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2320                         new_adv |= ADVERTISE_10FULL;
2321                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2322                         new_adv |= ADVERTISE_100HALF;
2323                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2324                         new_adv |= ADVERTISE_100FULL;
2325
2326                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2327
2328                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2329
2330                 if (tp->link_config.advertising &
2331                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2332                         new_adv = 0;
2333                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2334                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2335                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2336                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2337                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2338                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2339                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2340                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2341                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2342                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2343                 } else {
2344                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2345                 }
2346         } else {
2347                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2348                 new_adv |= ADVERTISE_CSMA;
2349
2350                 /* Asking for a specific link mode. */
2351                 if (tp->link_config.speed == SPEED_1000) {
2352                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2353
2354                         if (tp->link_config.duplex == DUPLEX_FULL)
2355                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2356                         else
2357                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2358                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2359                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2360                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2361                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2362                 } else {
2363                         if (tp->link_config.speed == SPEED_100) {
2364                                 if (tp->link_config.duplex == DUPLEX_FULL)
2365                                         new_adv |= ADVERTISE_100FULL;
2366                                 else
2367                                         new_adv |= ADVERTISE_100HALF;
2368                         } else {
2369                                 if (tp->link_config.duplex == DUPLEX_FULL)
2370                                         new_adv |= ADVERTISE_10FULL;
2371                                 else
2372                                         new_adv |= ADVERTISE_10HALF;
2373                         }
2374                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2375
2376                         new_adv = 0;
2377                 }
2378
2379                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2380         }
2381
2382         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2383             tp->link_config.speed != SPEED_INVALID) {
2384                 u32 bmcr, orig_bmcr;
2385
2386                 tp->link_config.active_speed = tp->link_config.speed;
2387                 tp->link_config.active_duplex = tp->link_config.duplex;
2388
2389                 bmcr = 0;
2390                 switch (tp->link_config.speed) {
2391                 default:
2392                 case SPEED_10:
2393                         break;
2394
2395                 case SPEED_100:
2396                         bmcr |= BMCR_SPEED100;
2397                         break;
2398
2399                 case SPEED_1000:
2400                         bmcr |= TG3_BMCR_SPEED1000;
2401                         break;
2402                 }
2403
2404                 if (tp->link_config.duplex == DUPLEX_FULL)
2405                         bmcr |= BMCR_FULLDPLX;
2406
2407                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2408                     (bmcr != orig_bmcr)) {
2409                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2410                         for (i = 0; i < 1500; i++) {
2411                                 u32 tmp;
2412
2413                                 udelay(10);
2414                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2415                                     tg3_readphy(tp, MII_BMSR, &tmp))
2416                                         continue;
2417                                 if (!(tmp & BMSR_LSTATUS)) {
2418                                         udelay(40);
2419                                         break;
2420                                 }
2421                         }
2422                         tg3_writephy(tp, MII_BMCR, bmcr);
2423                         udelay(40);
2424                 }
2425         } else {
2426                 tg3_writephy(tp, MII_BMCR,
2427                              BMCR_ANENABLE | BMCR_ANRESTART);
2428         }
2429 }
2430
2431 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2432 {
2433         int err;
2434
2435         /* Turn off tap power management. */
2436         /* Set Extended packet length bit */
2437         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2438
2439         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2440         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2441
2442         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2443         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2444
2445         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2446         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2447
2448         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2449         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2450
2451         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2452         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2453
2454         udelay(40);
2455
2456         return err;
2457 }
2458
2459 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2460 {
2461         u32 adv_reg, all_mask = 0;
2462
2463         if (mask & ADVERTISED_10baseT_Half)
2464                 all_mask |= ADVERTISE_10HALF;
2465         if (mask & ADVERTISED_10baseT_Full)
2466                 all_mask |= ADVERTISE_10FULL;
2467         if (mask & ADVERTISED_100baseT_Half)
2468                 all_mask |= ADVERTISE_100HALF;
2469         if (mask & ADVERTISED_100baseT_Full)
2470                 all_mask |= ADVERTISE_100FULL;
2471
2472         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2473                 return 0;
2474
2475         if ((adv_reg & all_mask) != all_mask)
2476                 return 0;
2477         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2478                 u32 tg3_ctrl;
2479
2480                 all_mask = 0;
2481                 if (mask & ADVERTISED_1000baseT_Half)
2482                         all_mask |= ADVERTISE_1000HALF;
2483                 if (mask & ADVERTISED_1000baseT_Full)
2484                         all_mask |= ADVERTISE_1000FULL;
2485
2486                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2487                         return 0;
2488
2489                 if ((tg3_ctrl & all_mask) != all_mask)
2490                         return 0;
2491         }
2492         return 1;
2493 }
2494
2495 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2496 {
2497         u32 curadv, reqadv;
2498
2499         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2500                 return 1;
2501
2502         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2503         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2504
2505         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2506                 if (curadv != reqadv)
2507                         return 0;
2508
2509                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2510                         tg3_readphy(tp, MII_LPA, rmtadv);
2511         } else {
2512                 /* Reprogram the advertisement register, even if it
2513                  * does not affect the current link.  If the link
2514                  * gets renegotiated in the future, we can save an
2515                  * additional renegotiation cycle by advertising
2516                  * it correctly in the first place.
2517                  */
2518                 if (curadv != reqadv) {
2519                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
2520                                      ADVERTISE_PAUSE_ASYM);
2521                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
2522                 }
2523         }
2524
2525         return 1;
2526 }
2527
2528 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
2529 {
2530         int current_link_up;
2531         u32 bmsr, dummy;
2532         u32 lcl_adv, rmt_adv;
2533         u16 current_speed;
2534         u8 current_duplex;
2535         int i, err;
2536
2537         tw32(MAC_EVENT, 0);
2538
2539         tw32_f(MAC_STATUS,
2540              (MAC_STATUS_SYNC_CHANGED |
2541               MAC_STATUS_CFG_CHANGED |
2542               MAC_STATUS_MI_COMPLETION |
2543               MAC_STATUS_LNKSTATE_CHANGED));
2544         udelay(40);
2545
2546         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
2547                 tw32_f(MAC_MI_MODE,
2548                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
2549                 udelay(80);
2550         }
2551
2552         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
2553
2554         /* Some third-party PHYs need to be reset on link going
2555          * down.
2556          */
2557         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2558              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2559              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2560             netif_carrier_ok(tp->dev)) {
2561                 tg3_readphy(tp, MII_BMSR, &bmsr);
2562                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2563                     !(bmsr & BMSR_LSTATUS))
2564                         force_reset = 1;
2565         }
2566         if (force_reset)
2567                 tg3_phy_reset(tp);
2568
2569         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
2570                 tg3_readphy(tp, MII_BMSR, &bmsr);
2571                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
2572                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
2573                         bmsr = 0;
2574
2575                 if (!(bmsr & BMSR_LSTATUS)) {
2576                         err = tg3_init_5401phy_dsp(tp);
2577                         if (err)
2578                                 return err;
2579
2580                         tg3_readphy(tp, MII_BMSR, &bmsr);
2581                         for (i = 0; i < 1000; i++) {
2582                                 udelay(10);
2583                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2584                                     (bmsr & BMSR_LSTATUS)) {
2585                                         udelay(40);
2586                                         break;
2587                                 }
2588                         }
2589
2590                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
2591                             !(bmsr & BMSR_LSTATUS) &&
2592                             tp->link_config.active_speed == SPEED_1000) {
2593                                 err = tg3_phy_reset(tp);
2594                                 if (!err)
2595                                         err = tg3_init_5401phy_dsp(tp);
2596                                 if (err)
2597                                         return err;
2598                         }
2599                 }
2600         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2601                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2602                 /* 5701 {A0,B0} CRC bug workaround */
2603                 tg3_writephy(tp, 0x15, 0x0a75);
2604                 tg3_writephy(tp, 0x1c, 0x8c68);
2605                 tg3_writephy(tp, 0x1c, 0x8d68);
2606                 tg3_writephy(tp, 0x1c, 0x8c68);
2607         }
2608
2609         /* Clear pending interrupts... */
2610         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2611         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
2612
2613         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
2614                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
2615         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
2616                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
2617
2618         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2619             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2620                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
2621                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2622                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
2623                 else
2624                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
2625         }
2626
2627         current_link_up = 0;
2628         current_speed = SPEED_INVALID;
2629         current_duplex = DUPLEX_INVALID;
2630
2631         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
2632                 u32 val;
2633
2634                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
2635                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
2636                 if (!(val & (1 << 10))) {
2637                         val |= (1 << 10);
2638                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2639                         goto relink;
2640                 }
2641         }
2642
2643         bmsr = 0;
2644         for (i = 0; i < 100; i++) {
2645                 tg3_readphy(tp, MII_BMSR, &bmsr);
2646                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
2647                     (bmsr & BMSR_LSTATUS))
2648                         break;
2649                 udelay(40);
2650         }
2651
2652         if (bmsr & BMSR_LSTATUS) {
2653                 u32 aux_stat, bmcr;
2654
2655                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
2656                 for (i = 0; i < 2000; i++) {
2657                         udelay(10);
2658                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
2659                             aux_stat)
2660                                 break;
2661                 }
2662
2663                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
2664                                              &current_speed,
2665                                              &current_duplex);
2666
2667                 bmcr = 0;
2668                 for (i = 0; i < 200; i++) {
2669                         tg3_readphy(tp, MII_BMCR, &bmcr);
2670                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
2671                                 continue;
2672                         if (bmcr && bmcr != 0x7fff)
2673                                 break;
2674                         udelay(10);
2675                 }
2676
2677                 lcl_adv = 0;
2678                 rmt_adv = 0;
2679
2680                 tp->link_config.active_speed = current_speed;
2681                 tp->link_config.active_duplex = current_duplex;
2682
2683                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2684                         if ((bmcr & BMCR_ANENABLE) &&
2685                             tg3_copper_is_advertising_all(tp,
2686                                                 tp->link_config.advertising)) {
2687                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
2688                                                                   &rmt_adv))
2689                                         current_link_up = 1;
2690                         }
2691                 } else {
2692                         if (!(bmcr & BMCR_ANENABLE) &&
2693                             tp->link_config.speed == current_speed &&
2694                             tp->link_config.duplex == current_duplex &&
2695                             tp->link_config.flowctrl ==
2696                             tp->link_config.active_flowctrl) {
2697                                 current_link_up = 1;
2698                         }
2699                 }
2700
2701                 if (current_link_up == 1 &&
2702                     tp->link_config.active_duplex == DUPLEX_FULL)
2703                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2704         }
2705
2706 relink:
2707         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2708                 u32 tmp;
2709
2710                 tg3_phy_copper_begin(tp);
2711
2712                 tg3_readphy(tp, MII_BMSR, &tmp);
2713                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2714                     (tmp & BMSR_LSTATUS))
2715                         current_link_up = 1;
2716         }
2717
2718         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2719         if (current_link_up == 1) {
2720                 if (tp->link_config.active_speed == SPEED_100 ||
2721                     tp->link_config.active_speed == SPEED_10)
2722                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2723                 else
2724                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2725         } else
2726                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2727
2728         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2729         if (tp->link_config.active_duplex == DUPLEX_HALF)
2730                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2731
2732         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2733                 if (current_link_up == 1 &&
2734                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2735                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2736                 else
2737                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2738         }
2739
2740         /* ??? Without this setting Netgear GA302T PHY does not
2741          * ??? send/receive packets...
2742          */
2743         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2744             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2745                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2746                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2747                 udelay(80);
2748         }
2749
2750         tw32_f(MAC_MODE, tp->mac_mode);
2751         udelay(40);
2752
2753         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2754                 /* Polled via timer. */
2755                 tw32_f(MAC_EVENT, 0);
2756         } else {
2757                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2758         }
2759         udelay(40);
2760
2761         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2762             current_link_up == 1 &&
2763             tp->link_config.active_speed == SPEED_1000 &&
2764             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2765              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2766                 udelay(120);
2767                 tw32_f(MAC_STATUS,
2768                      (MAC_STATUS_SYNC_CHANGED |
2769                       MAC_STATUS_CFG_CHANGED));
2770                 udelay(40);
2771                 tg3_write_mem(tp,
2772                               NIC_SRAM_FIRMWARE_MBOX,
2773                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2774         }
2775
2776         if (current_link_up != netif_carrier_ok(tp->dev)) {
2777                 if (current_link_up)
2778                         netif_carrier_on(tp->dev);
2779                 else
2780                         netif_carrier_off(tp->dev);
2781                 tg3_link_report(tp);
2782         }
2783
2784         return 0;
2785 }
2786
2787 struct tg3_fiber_aneginfo {
2788         int state;
2789 #define ANEG_STATE_UNKNOWN              0
2790 #define ANEG_STATE_AN_ENABLE            1
2791 #define ANEG_STATE_RESTART_INIT         2
2792 #define ANEG_STATE_RESTART              3
2793 #define ANEG_STATE_DISABLE_LINK_OK      4
2794 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2795 #define ANEG_STATE_ABILITY_DETECT       6
2796 #define ANEG_STATE_ACK_DETECT_INIT      7
2797 #define ANEG_STATE_ACK_DETECT           8
2798 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2799 #define ANEG_STATE_COMPLETE_ACK         10
2800 #define ANEG_STATE_IDLE_DETECT_INIT     11
2801 #define ANEG_STATE_IDLE_DETECT          12
2802 #define ANEG_STATE_LINK_OK              13
2803 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2804 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2805
2806         u32 flags;
2807 #define MR_AN_ENABLE            0x00000001
2808 #define MR_RESTART_AN           0x00000002
2809 #define MR_AN_COMPLETE          0x00000004
2810 #define MR_PAGE_RX              0x00000008
2811 #define MR_NP_LOADED            0x00000010
2812 #define MR_TOGGLE_TX            0x00000020
2813 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2814 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2815 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2816 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2817 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2818 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2819 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2820 #define MR_TOGGLE_RX            0x00002000
2821 #define MR_NP_RX                0x00004000
2822
2823 #define MR_LINK_OK              0x80000000
2824
2825         unsigned long link_time, cur_time;
2826
2827         u32 ability_match_cfg;
2828         int ability_match_count;
2829
2830         char ability_match, idle_match, ack_match;
2831
2832         u32 txconfig, rxconfig;
2833 #define ANEG_CFG_NP             0x00000080
2834 #define ANEG_CFG_ACK            0x00000040
2835 #define ANEG_CFG_RF2            0x00000020
2836 #define ANEG_CFG_RF1            0x00000010
2837 #define ANEG_CFG_PS2            0x00000001
2838 #define ANEG_CFG_PS1            0x00008000
2839 #define ANEG_CFG_HD             0x00004000
2840 #define ANEG_CFG_FD             0x00002000
2841 #define ANEG_CFG_INVAL          0x00001f06
2842
2843 };
2844 #define ANEG_OK         0
2845 #define ANEG_DONE       1
2846 #define ANEG_TIMER_ENAB 2
2847 #define ANEG_FAILED     -1
2848
2849 #define ANEG_STATE_SETTLE_TIME  10000
2850
2851 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2852                                    struct tg3_fiber_aneginfo *ap)
2853 {
2854         u16 flowctrl;
2855         unsigned long delta;
2856         u32 rx_cfg_reg;
2857         int ret;
2858
2859         if (ap->state == ANEG_STATE_UNKNOWN) {
2860                 ap->rxconfig = 0;
2861                 ap->link_time = 0;
2862                 ap->cur_time = 0;
2863                 ap->ability_match_cfg = 0;
2864                 ap->ability_match_count = 0;
2865                 ap->ability_match = 0;
2866                 ap->idle_match = 0;
2867                 ap->ack_match = 0;
2868         }
2869         ap->cur_time++;
2870
2871         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2872                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2873
2874                 if (rx_cfg_reg != ap->ability_match_cfg) {
2875                         ap->ability_match_cfg = rx_cfg_reg;
2876                         ap->ability_match = 0;
2877                         ap->ability_match_count = 0;
2878                 } else {
2879                         if (++ap->ability_match_count > 1) {
2880                                 ap->ability_match = 1;
2881                                 ap->ability_match_cfg = rx_cfg_reg;
2882                         }
2883                 }
2884                 if (rx_cfg_reg & ANEG_CFG_ACK)
2885                         ap->ack_match = 1;
2886                 else
2887                         ap->ack_match = 0;
2888
2889                 ap->idle_match = 0;
2890         } else {
2891                 ap->idle_match = 1;
2892                 ap->ability_match_cfg = 0;
2893                 ap->ability_match_count = 0;
2894                 ap->ability_match = 0;
2895                 ap->ack_match = 0;
2896
2897                 rx_cfg_reg = 0;
2898         }
2899
2900         ap->rxconfig = rx_cfg_reg;
2901         ret = ANEG_OK;
2902
2903         switch(ap->state) {
2904         case ANEG_STATE_UNKNOWN:
2905                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2906                         ap->state = ANEG_STATE_AN_ENABLE;
2907
2908                 /* fallthru */
2909         case ANEG_STATE_AN_ENABLE:
2910                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2911                 if (ap->flags & MR_AN_ENABLE) {
2912                         ap->link_time = 0;
2913                         ap->cur_time = 0;
2914                         ap->ability_match_cfg = 0;
2915                         ap->ability_match_count = 0;
2916                         ap->ability_match = 0;
2917                         ap->idle_match = 0;
2918                         ap->ack_match = 0;
2919
2920                         ap->state = ANEG_STATE_RESTART_INIT;
2921                 } else {
2922                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2923                 }
2924                 break;
2925
2926         case ANEG_STATE_RESTART_INIT:
2927                 ap->link_time = ap->cur_time;
2928                 ap->flags &= ~(MR_NP_LOADED);
2929                 ap->txconfig = 0;
2930                 tw32(MAC_TX_AUTO_NEG, 0);
2931                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2932                 tw32_f(MAC_MODE, tp->mac_mode);
2933                 udelay(40);
2934
2935                 ret = ANEG_TIMER_ENAB;
2936                 ap->state = ANEG_STATE_RESTART;
2937
2938                 /* fallthru */
2939         case ANEG_STATE_RESTART:
2940                 delta = ap->cur_time - ap->link_time;
2941                 if (delta > ANEG_STATE_SETTLE_TIME) {
2942                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2943                 } else {
2944                         ret = ANEG_TIMER_ENAB;
2945                 }
2946                 break;
2947
2948         case ANEG_STATE_DISABLE_LINK_OK:
2949                 ret = ANEG_DONE;
2950                 break;
2951
2952         case ANEG_STATE_ABILITY_DETECT_INIT:
2953                 ap->flags &= ~(MR_TOGGLE_TX);
2954                 ap->txconfig = ANEG_CFG_FD;
2955                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
2956                 if (flowctrl & ADVERTISE_1000XPAUSE)
2957                         ap->txconfig |= ANEG_CFG_PS1;
2958                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
2959                         ap->txconfig |= ANEG_CFG_PS2;
2960                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2961                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2962                 tw32_f(MAC_MODE, tp->mac_mode);
2963                 udelay(40);
2964
2965                 ap->state = ANEG_STATE_ABILITY_DETECT;
2966                 break;
2967
2968         case ANEG_STATE_ABILITY_DETECT:
2969                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2970                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2971                 }
2972                 break;
2973
2974         case ANEG_STATE_ACK_DETECT_INIT:
2975                 ap->txconfig |= ANEG_CFG_ACK;
2976                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2977                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2978                 tw32_f(MAC_MODE, tp->mac_mode);
2979                 udelay(40);
2980
2981                 ap->state = ANEG_STATE_ACK_DETECT;
2982
2983                 /* fallthru */
2984         case ANEG_STATE_ACK_DETECT:
2985                 if (ap->ack_match != 0) {
2986                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2987                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2988                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2989                         } else {
2990                                 ap->state = ANEG_STATE_AN_ENABLE;
2991                         }
2992                 } else if (ap->ability_match != 0 &&
2993                            ap->rxconfig == 0) {
2994                         ap->state = ANEG_STATE_AN_ENABLE;
2995                 }
2996                 break;
2997
2998         case ANEG_STATE_COMPLETE_ACK_INIT:
2999                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3000                         ret = ANEG_FAILED;
3001                         break;
3002                 }
3003                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3004                                MR_LP_ADV_HALF_DUPLEX |
3005                                MR_LP_ADV_SYM_PAUSE |
3006                                MR_LP_ADV_ASYM_PAUSE |
3007                                MR_LP_ADV_REMOTE_FAULT1 |
3008                                MR_LP_ADV_REMOTE_FAULT2 |
3009                                MR_LP_ADV_NEXT_PAGE |
3010                                MR_TOGGLE_RX |
3011                                MR_NP_RX);
3012                 if (ap->rxconfig & ANEG_CFG_FD)
3013                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3014                 if (ap->rxconfig & ANEG_CFG_HD)
3015                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3016                 if (ap->rxconfig & ANEG_CFG_PS1)
3017                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3018                 if (ap->rxconfig & ANEG_CFG_PS2)
3019                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3020                 if (ap->rxconfig & ANEG_CFG_RF1)
3021                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3022                 if (ap->rxconfig & ANEG_CFG_RF2)
3023                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3024                 if (ap->rxconfig & ANEG_CFG_NP)
3025                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3026
3027                 ap->link_time = ap->cur_time;
3028
3029                 ap->flags ^= (MR_TOGGLE_TX);
3030                 if (ap->rxconfig & 0x0008)
3031                         ap->flags |= MR_TOGGLE_RX;
3032                 if (ap->rxconfig & ANEG_CFG_NP)
3033                         ap->flags |= MR_NP_RX;
3034                 ap->flags |= MR_PAGE_RX;
3035
3036                 ap->state = ANEG_STATE_COMPLETE_ACK;
3037                 ret = ANEG_TIMER_ENAB;
3038                 break;
3039
3040         case ANEG_STATE_COMPLETE_ACK:
3041                 if (ap->ability_match != 0 &&
3042                     ap->rxconfig == 0) {
3043                         ap->state = ANEG_STATE_AN_ENABLE;
3044                         break;
3045                 }
3046                 delta = ap->cur_time - ap->link_time;
3047                 if (delta > ANEG_STATE_SETTLE_TIME) {
3048                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3049                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3050                         } else {
3051                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3052                                     !(ap->flags & MR_NP_RX)) {
3053                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3054                                 } else {
3055                                         ret = ANEG_FAILED;
3056                                 }
3057                         }
3058                 }
3059                 break;
3060
3061         case ANEG_STATE_IDLE_DETECT_INIT:
3062                 ap->link_time = ap->cur_time;
3063                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3064                 tw32_f(MAC_MODE, tp->mac_mode);
3065                 udelay(40);
3066
3067                 ap->state = ANEG_STATE_IDLE_DETECT;
3068                 ret = ANEG_TIMER_ENAB;
3069                 break;
3070
3071         case ANEG_STATE_IDLE_DETECT:
3072                 if (ap->ability_match != 0 &&
3073                     ap->rxconfig == 0) {
3074                         ap->state = ANEG_STATE_AN_ENABLE;
3075                         break;
3076                 }
3077                 delta = ap->cur_time - ap->link_time;
3078                 if (delta > ANEG_STATE_SETTLE_TIME) {
3079                         /* XXX another gem from the Broadcom driver :( */
3080                         ap->state = ANEG_STATE_LINK_OK;
3081                 }
3082                 break;
3083
3084         case ANEG_STATE_LINK_OK:
3085                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3086                 ret = ANEG_DONE;
3087                 break;
3088
3089         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3090                 /* ??? unimplemented */
3091                 break;
3092
3093         case ANEG_STATE_NEXT_PAGE_WAIT:
3094                 /* ??? unimplemented */
3095                 break;
3096
3097         default:
3098                 ret = ANEG_FAILED;
3099                 break;
3100         }
3101
3102         return ret;
3103 }
3104
3105 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3106 {
3107         int res = 0;
3108         struct tg3_fiber_aneginfo aninfo;
3109         int status = ANEG_FAILED;
3110         unsigned int tick;
3111         u32 tmp;
3112
3113         tw32_f(MAC_TX_AUTO_NEG, 0);
3114
3115         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3116         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3117         udelay(40);
3118
3119         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3120         udelay(40);
3121
3122         memset(&aninfo, 0, sizeof(aninfo));
3123         aninfo.flags |= MR_AN_ENABLE;
3124         aninfo.state = ANEG_STATE_UNKNOWN;
3125         aninfo.cur_time = 0;
3126         tick = 0;
3127         while (++tick < 195000) {
3128                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3129                 if (status == ANEG_DONE || status == ANEG_FAILED)
3130                         break;
3131
3132                 udelay(1);
3133         }
3134
3135         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3136         tw32_f(MAC_MODE, tp->mac_mode);
3137         udelay(40);
3138
3139         *txflags = aninfo.txconfig;
3140         *rxflags = aninfo.flags;
3141
3142         if (status == ANEG_DONE &&
3143             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3144                              MR_LP_ADV_FULL_DUPLEX)))
3145                 res = 1;
3146
3147         return res;
3148 }
3149
3150 static void tg3_init_bcm8002(struct tg3 *tp)
3151 {
3152         u32 mac_status = tr32(MAC_STATUS);
3153         int i;
3154
3155         /* Reset when initting first time or we have a link. */
3156         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3157             !(mac_status & MAC_STATUS_PCS_SYNCED))
3158                 return;
3159
3160         /* Set PLL lock range. */
3161         tg3_writephy(tp, 0x16, 0x8007);
3162
3163         /* SW reset */
3164         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3165
3166         /* Wait for reset to complete. */
3167         /* XXX schedule_timeout() ... */
3168         for (i = 0; i < 500; i++)
3169                 udelay(10);
3170
3171         /* Config mode; select PMA/Ch 1 regs. */
3172         tg3_writephy(tp, 0x10, 0x8411);
3173
3174         /* Enable auto-lock and comdet, select txclk for tx. */
3175         tg3_writephy(tp, 0x11, 0x0a10);
3176
3177         tg3_writephy(tp, 0x18, 0x00a0);
3178         tg3_writephy(tp, 0x16, 0x41ff);
3179
3180         /* Assert and deassert POR. */
3181         tg3_writephy(tp, 0x13, 0x0400);
3182         udelay(40);
3183         tg3_writephy(tp, 0x13, 0x0000);
3184
3185         tg3_writephy(tp, 0x11, 0x0a50);
3186         udelay(40);
3187         tg3_writephy(tp, 0x11, 0x0a10);
3188
3189         /* Wait for signal to stabilize */
3190         /* XXX schedule_timeout() ... */
3191         for (i = 0; i < 15000; i++)
3192                 udelay(10);
3193
3194         /* Deselect the channel register so we can read the PHYID
3195          * later.
3196          */
3197         tg3_writephy(tp, 0x10, 0x8011);
3198 }
3199
3200 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3201 {
3202         u16 flowctrl;
3203         u32 sg_dig_ctrl, sg_dig_status;
3204         u32 serdes_cfg, expected_sg_dig_ctrl;
3205         int workaround, port_a;
3206         int current_link_up;
3207
3208         serdes_cfg = 0;
3209         expected_sg_dig_ctrl = 0;
3210         workaround = 0;
3211         port_a = 1;
3212         current_link_up = 0;
3213
3214         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3215             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3216                 workaround = 1;
3217                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3218                         port_a = 0;
3219
3220                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3221                 /* preserve bits 20-23 for voltage regulator */
3222                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3223         }
3224
3225         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3226
3227         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3228                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3229                         if (workaround) {
3230                                 u32 val = serdes_cfg;
3231
3232                                 if (port_a)
3233                                         val |= 0xc010000;
3234                                 else
3235                                         val |= 0x4010000;
3236                                 tw32_f(MAC_SERDES_CFG, val);
3237                         }
3238
3239                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3240                 }
3241                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3242                         tg3_setup_flow_control(tp, 0, 0);
3243                         current_link_up = 1;
3244                 }
3245                 goto out;
3246         }
3247
3248         /* Want auto-negotiation.  */
3249         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3250
3251         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3252         if (flowctrl & ADVERTISE_1000XPAUSE)
3253                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3254         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3255                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3256
3257         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3258                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3259                     tp->serdes_counter &&
3260                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3261                                     MAC_STATUS_RCVD_CFG)) ==
3262                      MAC_STATUS_PCS_SYNCED)) {
3263                         tp->serdes_counter--;
3264                         current_link_up = 1;
3265                         goto out;
3266                 }
3267 restart_autoneg:
3268                 if (workaround)
3269                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3270                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3271                 udelay(5);
3272                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3273
3274                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3275                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3276         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3277                                  MAC_STATUS_SIGNAL_DET)) {
3278                 sg_dig_status = tr32(SG_DIG_STATUS);
3279                 mac_status = tr32(MAC_STATUS);
3280
3281                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3282                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3283                         u32 local_adv = 0, remote_adv = 0;
3284
3285                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3286                                 local_adv |= ADVERTISE_1000XPAUSE;
3287                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3288                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3289
3290                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3291                                 remote_adv |= LPA_1000XPAUSE;
3292                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3293                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3294
3295                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3296                         current_link_up = 1;
3297                         tp->serdes_counter = 0;
3298                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3299                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3300                         if (tp->serdes_counter)
3301                                 tp->serdes_counter--;
3302                         else {
3303                                 if (workaround) {
3304                                         u32 val = serdes_cfg;
3305
3306                                         if (port_a)
3307                                                 val |= 0xc010000;
3308                                         else
3309                                                 val |= 0x4010000;
3310
3311                                         tw32_f(MAC_SERDES_CFG, val);
3312                                 }
3313
3314                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3315                                 udelay(40);
3316
3317                                 /* Link parallel detection - link is up */
3318                                 /* only if we have PCS_SYNC and not */
3319                                 /* receiving config code words */
3320                                 mac_status = tr32(MAC_STATUS);
3321                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3322                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3323                                         tg3_setup_flow_control(tp, 0, 0);
3324                                         current_link_up = 1;
3325                                         tp->tg3_flags2 |=
3326                                                 TG3_FLG2_PARALLEL_DETECT;
3327                                         tp->serdes_counter =
3328                                                 SERDES_PARALLEL_DET_TIMEOUT;
3329                                 } else
3330                                         goto restart_autoneg;
3331                         }
3332                 }
3333         } else {
3334                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3335                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3336         }
3337
3338 out:
3339         return current_link_up;
3340 }
3341
3342 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3343 {
3344         int current_link_up = 0;
3345
3346         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3347                 goto out;
3348
3349         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3350                 u32 txflags, rxflags;
3351                 int i;
3352
3353                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3354                         u32 local_adv = 0, remote_adv = 0;
3355
3356                         if (txflags & ANEG_CFG_PS1)
3357                                 local_adv |= ADVERTISE_1000XPAUSE;
3358                         if (txflags & ANEG_CFG_PS2)
3359                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3360
3361                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3362                                 remote_adv |= LPA_1000XPAUSE;
3363                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3364                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3365
3366                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3367
3368                         current_link_up = 1;
3369                 }
3370                 for (i = 0; i < 30; i++) {
3371                         udelay(20);
3372                         tw32_f(MAC_STATUS,
3373                                (MAC_STATUS_SYNC_CHANGED |
3374                                 MAC_STATUS_CFG_CHANGED));
3375                         udelay(40);
3376                         if ((tr32(MAC_STATUS) &
3377                              (MAC_STATUS_SYNC_CHANGED |
3378                               MAC_STATUS_CFG_CHANGED)) == 0)
3379                                 break;
3380                 }
3381
3382                 mac_status = tr32(MAC_STATUS);
3383                 if (current_link_up == 0 &&
3384                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3385                     !(mac_status & MAC_STATUS_RCVD_CFG))
3386                         current_link_up = 1;
3387         } else {
3388                 tg3_setup_flow_control(tp, 0, 0);
3389
3390                 /* Forcing 1000FD link up. */
3391                 current_link_up = 1;
3392
3393                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3394                 udelay(40);
3395
3396                 tw32_f(MAC_MODE, tp->mac_mode);
3397                 udelay(40);
3398         }
3399
3400 out:
3401         return current_link_up;
3402 }
3403
3404 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3405 {
3406         u32 orig_pause_cfg;
3407         u16 orig_active_speed;
3408         u8 orig_active_duplex;
3409         u32 mac_status;
3410         int current_link_up;
3411         int i;
3412
3413         orig_pause_cfg = tp->link_config.active_flowctrl;
3414         orig_active_speed = tp->link_config.active_speed;
3415         orig_active_duplex = tp->link_config.active_duplex;
3416
3417         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3418             netif_carrier_ok(tp->dev) &&
3419             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3420                 mac_status = tr32(MAC_STATUS);
3421                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3422                                MAC_STATUS_SIGNAL_DET |
3423                                MAC_STATUS_CFG_CHANGED |
3424                                MAC_STATUS_RCVD_CFG);
3425                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3426                                    MAC_STATUS_SIGNAL_DET)) {
3427                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3428                                             MAC_STATUS_CFG_CHANGED));
3429                         return 0;
3430                 }
3431         }
3432
3433         tw32_f(MAC_TX_AUTO_NEG, 0);
3434
3435         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3436         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3437         tw32_f(MAC_MODE, tp->mac_mode);
3438         udelay(40);
3439
3440         if (tp->phy_id == PHY_ID_BCM8002)
3441                 tg3_init_bcm8002(tp);
3442
3443         /* Enable link change event even when serdes polling.  */
3444         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3445         udelay(40);
3446
3447         current_link_up = 0;
3448         mac_status = tr32(MAC_STATUS);
3449
3450         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3451                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3452         else
3453                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3454
3455         tp->hw_status->status =
3456                 (SD_STATUS_UPDATED |
3457                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
3458
3459         for (i = 0; i < 100; i++) {
3460                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3461                                     MAC_STATUS_CFG_CHANGED));
3462                 udelay(5);
3463                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3464                                          MAC_STATUS_CFG_CHANGED |
3465                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3466                         break;
3467         }
3468
3469         mac_status = tr32(MAC_STATUS);
3470         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3471                 current_link_up = 0;
3472                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3473                     tp->serdes_counter == 0) {
3474                         tw32_f(MAC_MODE, (tp->mac_mode |
3475                                           MAC_MODE_SEND_CONFIGS));
3476                         udelay(1);
3477                         tw32_f(MAC_MODE, tp->mac_mode);
3478                 }
3479         }
3480
3481         if (current_link_up == 1) {
3482                 tp->link_config.active_speed = SPEED_1000;
3483                 tp->link_config.active_duplex = DUPLEX_FULL;
3484                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3485                                     LED_CTRL_LNKLED_OVERRIDE |
3486                                     LED_CTRL_1000MBPS_ON));
3487         } else {
3488                 tp->link_config.active_speed = SPEED_INVALID;
3489                 tp->link_config.active_duplex = DUPLEX_INVALID;
3490                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3491                                     LED_CTRL_LNKLED_OVERRIDE |
3492                                     LED_CTRL_TRAFFIC_OVERRIDE));
3493         }
3494
3495         if (current_link_up != netif_carrier_ok(tp->dev)) {
3496                 if (current_link_up)
3497                         netif_carrier_on(tp->dev);
3498                 else
3499                         netif_carrier_off(tp->dev);
3500                 tg3_link_report(tp);
3501         } else {
3502                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
3503                 if (orig_pause_cfg != now_pause_cfg ||
3504                     orig_active_speed != tp->link_config.active_speed ||
3505                     orig_active_duplex != tp->link_config.active_duplex)
3506                         tg3_link_report(tp);
3507         }
3508
3509         return 0;
3510 }
3511
3512 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
3513 {
3514         int current_link_up, err = 0;
3515         u32 bmsr, bmcr;
3516         u16 current_speed;
3517         u8 current_duplex;
3518         u32 local_adv, remote_adv;
3519
3520         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3521         tw32_f(MAC_MODE, tp->mac_mode);
3522         udelay(40);
3523
3524         tw32(MAC_EVENT, 0);
3525
3526         tw32_f(MAC_STATUS,
3527              (MAC_STATUS_SYNC_CHANGED |
3528               MAC_STATUS_CFG_CHANGED |
3529               MAC_STATUS_MI_COMPLETION |
3530               MAC_STATUS_LNKSTATE_CHANGED));
3531         udelay(40);
3532
3533         if (force_reset)
3534                 tg3_phy_reset(tp);
3535
3536         current_link_up = 0;
3537         current_speed = SPEED_INVALID;
3538         current_duplex = DUPLEX_INVALID;
3539
3540         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3541         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3542         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
3543                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3544                         bmsr |= BMSR_LSTATUS;
3545                 else
3546                         bmsr &= ~BMSR_LSTATUS;
3547         }
3548
3549         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
3550
3551         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
3552             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3553                 /* do nothing, just check for link up at the end */
3554         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3555                 u32 adv, new_adv;
3556
3557                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3558                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
3559                                   ADVERTISE_1000XPAUSE |
3560                                   ADVERTISE_1000XPSE_ASYM |
3561                                   ADVERTISE_SLCT);
3562
3563                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3564
3565                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
3566                         new_adv |= ADVERTISE_1000XHALF;
3567                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
3568                         new_adv |= ADVERTISE_1000XFULL;
3569
3570                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
3571                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
3572                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
3573                         tg3_writephy(tp, MII_BMCR, bmcr);
3574
3575                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3576                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
3577                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3578
3579                         return err;
3580                 }
3581         } else {
3582                 u32 new_bmcr;
3583
3584                 bmcr &= ~BMCR_SPEED1000;
3585                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
3586
3587                 if (tp->link_config.duplex == DUPLEX_FULL)
3588                         new_bmcr |= BMCR_FULLDPLX;
3589
3590                 if (new_bmcr != bmcr) {
3591                         /* BMCR_SPEED1000 is a reserved bit that needs
3592                          * to be set on write.
3593                          */
3594                         new_bmcr |= BMCR_SPEED1000;
3595
3596                         /* Force a linkdown */
3597                         if (netif_carrier_ok(tp->dev)) {
3598                                 u32 adv;
3599
3600                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
3601                                 adv &= ~(ADVERTISE_1000XFULL |
3602                                          ADVERTISE_1000XHALF |
3603                                          ADVERTISE_SLCT);
3604                                 tg3_writephy(tp, MII_ADVERTISE, adv);
3605                                 tg3_writephy(tp, MII_BMCR, bmcr |
3606                                                            BMCR_ANRESTART |
3607                                                            BMCR_ANENABLE);
3608                                 udelay(10);
3609                                 netif_carrier_off(tp->dev);
3610                         }
3611                         tg3_writephy(tp, MII_BMCR, new_bmcr);
3612                         bmcr = new_bmcr;
3613                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3614                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
3615                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3616                             ASIC_REV_5714) {
3617                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
3618                                         bmsr |= BMSR_LSTATUS;
3619                                 else
3620                                         bmsr &= ~BMSR_LSTATUS;
3621                         }
3622                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3623                 }
3624         }
3625
3626         if (bmsr & BMSR_LSTATUS) {
3627                 current_speed = SPEED_1000;
3628                 current_link_up = 1;
3629                 if (bmcr & BMCR_FULLDPLX)
3630                         current_duplex = DUPLEX_FULL;
3631                 else
3632                         current_duplex = DUPLEX_HALF;
3633
3634                 local_adv = 0;
3635                 remote_adv = 0;
3636
3637                 if (bmcr & BMCR_ANENABLE) {
3638                         u32 common;
3639
3640                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
3641                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
3642                         common = local_adv & remote_adv;
3643                         if (common & (ADVERTISE_1000XHALF |
3644                                       ADVERTISE_1000XFULL)) {
3645                                 if (common & ADVERTISE_1000XFULL)
3646                                         current_duplex = DUPLEX_FULL;
3647                                 else
3648                                         current_duplex = DUPLEX_HALF;
3649                         }
3650                         else
3651                                 current_link_up = 0;
3652                 }
3653         }
3654
3655         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
3656                 tg3_setup_flow_control(tp, local_adv, remote_adv);
3657
3658         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3659         if (tp->link_config.active_duplex == DUPLEX_HALF)
3660                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3661
3662         tw32_f(MAC_MODE, tp->mac_mode);
3663         udelay(40);
3664
3665         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3666
3667         tp->link_config.active_speed = current_speed;
3668         tp->link_config.active_duplex = current_duplex;
3669
3670         if (current_link_up != netif_carrier_ok(tp->dev)) {
3671                 if (current_link_up)
3672                         netif_carrier_on(tp->dev);
3673                 else {
3674                         netif_carrier_off(tp->dev);
3675                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3676                 }
3677                 tg3_link_report(tp);
3678         }
3679         return err;
3680 }
3681
3682 static void tg3_serdes_parallel_detect(struct tg3 *tp)
3683 {
3684         if (tp->serdes_counter) {
3685                 /* Give autoneg time to complete. */
3686                 tp->serdes_counter--;
3687                 return;
3688         }
3689         if (!netif_carrier_ok(tp->dev) &&
3690             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
3691                 u32 bmcr;
3692
3693                 tg3_readphy(tp, MII_BMCR, &bmcr);
3694                 if (bmcr & BMCR_ANENABLE) {
3695                         u32 phy1, phy2;
3696
3697                         /* Select shadow register 0x1f */
3698                         tg3_writephy(tp, 0x1c, 0x7c00);
3699                         tg3_readphy(tp, 0x1c, &phy1);
3700
3701                         /* Select expansion interrupt status register */
3702                         tg3_writephy(tp, 0x17, 0x0f01);
3703                         tg3_readphy(tp, 0x15, &phy2);
3704                         tg3_readphy(tp, 0x15, &phy2);
3705
3706                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
3707                                 /* We have signal detect and not receiving
3708                                  * config code words, link is up by parallel
3709                                  * detection.
3710                                  */
3711
3712                                 bmcr &= ~BMCR_ANENABLE;
3713                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3714                                 tg3_writephy(tp, MII_BMCR, bmcr);
3715                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3716                         }
3717                 }
3718         }
3719         else if (netif_carrier_ok(tp->dev) &&
3720                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3721                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3722                 u32 phy2;
3723
3724                 /* Select expansion interrupt status register */
3725                 tg3_writephy(tp, 0x17, 0x0f01);
3726                 tg3_readphy(tp, 0x15, &phy2);
3727                 if (phy2 & 0x20) {
3728                         u32 bmcr;
3729
3730                         /* Config code words received, turn on autoneg. */
3731                         tg3_readphy(tp, MII_BMCR, &bmcr);
3732                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3733
3734                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3735
3736                 }
3737         }
3738 }
3739
3740 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3741 {
3742         int err;
3743
3744         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3745                 err = tg3_setup_fiber_phy(tp, force_reset);
3746         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3747                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3748         } else {
3749                 err = tg3_setup_copper_phy(tp, force_reset);
3750         }
3751
3752         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
3753             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
3754                 u32 val, scale;
3755
3756                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
3757                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
3758                         scale = 65;
3759                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
3760                         scale = 6;
3761                 else
3762                         scale = 12;
3763
3764                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
3765                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
3766                 tw32(GRC_MISC_CFG, val);
3767         }
3768
3769         if (tp->link_config.active_speed == SPEED_1000 &&
3770             tp->link_config.active_duplex == DUPLEX_HALF)
3771                 tw32(MAC_TX_LENGTHS,
3772                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3773                       (6 << TX_LENGTHS_IPG_SHIFT) |
3774                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3775         else
3776                 tw32(MAC_TX_LENGTHS,
3777                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3778                       (6 << TX_LENGTHS_IPG_SHIFT) |
3779                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3780
3781         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3782                 if (netif_carrier_ok(tp->dev)) {
3783                         tw32(HOSTCC_STAT_COAL_TICKS,
3784                              tp->coal.stats_block_coalesce_usecs);
3785                 } else {
3786                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3787                 }
3788         }
3789
3790         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3791                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3792                 if (!netif_carrier_ok(tp->dev))
3793                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3794                               tp->pwrmgmt_thresh;
3795                 else
3796                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3797                 tw32(PCIE_PWR_MGMT_THRESH, val);
3798         }
3799
3800         return err;
3801 }
3802
3803 /* This is called whenever we suspect that the system chipset is re-
3804  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3805  * is bogus tx completions. We try to recover by setting the
3806  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3807  * in the workqueue.
3808  */
3809 static void tg3_tx_recover(struct tg3 *tp)
3810 {
3811         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3812                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3813
3814         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3815                "mapped I/O cycles to the network device, attempting to "
3816                "recover. Please report the problem to the driver maintainer "
3817                "and include system chipset information.\n", tp->dev->name);
3818
3819         spin_lock(&tp->lock);
3820         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3821         spin_unlock(&tp->lock);
3822 }
3823
3824 static inline u32 tg3_tx_avail(struct tg3 *tp)
3825 {
3826         smp_mb();
3827         return (tp->tx_pending -
3828                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3829 }
3830
3831 /* Tigon3 never reports partial packet sends.  So we do not
3832  * need special logic to handle SKBs that have not had all
3833  * of their frags sent yet, like SunGEM does.
3834  */
3835 static void tg3_tx(struct tg3 *tp)
3836 {
3837         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3838         u32 sw_idx = tp->tx_cons;
3839
3840         while (sw_idx != hw_idx) {
3841                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3842                 struct sk_buff *skb = ri->skb;
3843                 int i, tx_bug = 0;
3844
3845                 if (unlikely(skb == NULL)) {
3846                         tg3_tx_recover(tp);
3847                         return;
3848                 }
3849
3850                 pci_unmap_single(tp->pdev,
3851                                  pci_unmap_addr(ri, mapping),
3852                                  skb_headlen(skb),
3853                                  PCI_DMA_TODEVICE);
3854
3855                 ri->skb = NULL;
3856
3857                 sw_idx = NEXT_TX(sw_idx);
3858
3859                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3860                         ri = &tp->tx_buffers[sw_idx];
3861                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3862                                 tx_bug = 1;
3863
3864                         pci_unmap_page(tp->pdev,
3865                                        pci_unmap_addr(ri, mapping),
3866                                        skb_shinfo(skb)->frags[i].size,
3867                                        PCI_DMA_TODEVICE);
3868
3869                         sw_idx = NEXT_TX(sw_idx);
3870                 }
3871
3872                 dev_kfree_skb(skb);
3873
3874                 if (unlikely(tx_bug)) {
3875                         tg3_tx_recover(tp);
3876                         return;
3877                 }
3878         }
3879
3880         tp->tx_cons = sw_idx;
3881
3882         /* Need to make the tx_cons update visible to tg3_start_xmit()
3883          * before checking for netif_queue_stopped().  Without the
3884          * memory barrier, there is a small possibility that tg3_start_xmit()
3885          * will miss it and cause the queue to be stopped forever.
3886          */
3887         smp_mb();
3888
3889         if (unlikely(netif_queue_stopped(tp->dev) &&
3890                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3891                 netif_tx_lock(tp->dev);
3892                 if (netif_queue_stopped(tp->dev) &&
3893                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3894                         netif_wake_queue(tp->dev);
3895                 netif_tx_unlock(tp->dev);
3896         }
3897 }
3898
3899 /* Returns size of skb allocated or < 0 on error.
3900  *
3901  * We only need to fill in the address because the other members
3902  * of the RX descriptor are invariant, see tg3_init_rings.
3903  *
3904  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3905  * posting buffers we only dirty the first cache line of the RX
3906  * descriptor (containing the address).  Whereas for the RX status
3907  * buffers the cpu only reads the last cacheline of the RX descriptor
3908  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3909  */
3910 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3911                             int src_idx, u32 dest_idx_unmasked)
3912 {
3913         struct tg3_rx_buffer_desc *desc;
3914         struct ring_info *map, *src_map;
3915         struct sk_buff *skb;
3916         dma_addr_t mapping;
3917         int skb_size, dest_idx;
3918
3919         src_map = NULL;
3920         switch (opaque_key) {
3921         case RXD_OPAQUE_RING_STD:
3922                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3923                 desc = &tp->rx_std[dest_idx];
3924                 map = &tp->rx_std_buffers[dest_idx];
3925                 if (src_idx >= 0)
3926                         src_map = &tp->rx_std_buffers[src_idx];
3927                 skb_size = tp->rx_pkt_buf_sz;
3928                 break;
3929
3930         case RXD_OPAQUE_RING_JUMBO:
3931                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3932                 desc = &tp->rx_jumbo[dest_idx];
3933                 map = &tp->rx_jumbo_buffers[dest_idx];
3934                 if (src_idx >= 0)
3935                         src_map = &tp->rx_jumbo_buffers[src_idx];
3936                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3937                 break;
3938
3939         default:
3940                 return -EINVAL;
3941         }
3942
3943         /* Do not overwrite any of the map or rp information
3944          * until we are sure we can commit to a new buffer.
3945          *
3946          * Callers depend upon this behavior and assume that
3947          * we leave everything unchanged if we fail.
3948          */
3949         skb = netdev_alloc_skb(tp->dev, skb_size);
3950         if (skb == NULL)
3951                 return -ENOMEM;
3952
3953         skb_reserve(skb, tp->rx_offset);
3954
3955         mapping = pci_map_single(tp->pdev, skb->data,
3956                                  skb_size - tp->rx_offset,
3957                                  PCI_DMA_FROMDEVICE);
3958
3959         map->skb = skb;
3960         pci_unmap_addr_set(map, mapping, mapping);
3961
3962         if (src_map != NULL)
3963                 src_map->skb = NULL;
3964
3965         desc->addr_hi = ((u64)mapping >> 32);
3966         desc->addr_lo = ((u64)mapping & 0xffffffff);
3967
3968         return skb_size;
3969 }
3970
3971 /* We only need to move over in the address because the other
3972  * members of the RX descriptor are invariant.  See notes above
3973  * tg3_alloc_rx_skb for full details.
3974  */
3975 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3976                            int src_idx, u32 dest_idx_unmasked)
3977 {
3978         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3979         struct ring_info *src_map, *dest_map;
3980         int dest_idx;
3981
3982         switch (opaque_key) {
3983         case RXD_OPAQUE_RING_STD:
3984                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3985                 dest_desc = &tp->rx_std[dest_idx];
3986                 dest_map = &tp->rx_std_buffers[dest_idx];
3987                 src_desc = &tp->rx_std[src_idx];
3988                 src_map = &tp->rx_std_buffers[src_idx];
3989                 break;
3990
3991         case RXD_OPAQUE_RING_JUMBO:
3992                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3993                 dest_desc = &tp->rx_jumbo[dest_idx];
3994                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3995                 src_desc = &tp->rx_jumbo[src_idx];
3996                 src_map = &tp->rx_jumbo_buffers[src_idx];
3997                 break;
3998
3999         default:
4000                 return;
4001         }
4002
4003         dest_map->skb = src_map->skb;
4004         pci_unmap_addr_set(dest_map, mapping,
4005                            pci_unmap_addr(src_map, mapping));
4006         dest_desc->addr_hi = src_desc->addr_hi;
4007         dest_desc->addr_lo = src_desc->addr_lo;
4008
4009         src_map->skb = NULL;
4010 }
4011
4012 #if TG3_VLAN_TAG_USED
4013 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
4014 {
4015         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
4016 }
4017 #endif
4018
4019 /* The RX ring scheme is composed of multiple rings which post fresh
4020  * buffers to the chip, and one special ring the chip uses to report
4021  * status back to the host.
4022  *
4023  * The special ring reports the status of received packets to the
4024  * host.  The chip does not write into the original descriptor the
4025  * RX buffer was obtained from.  The chip simply takes the original
4026  * descriptor as provided by the host, updates the status and length
4027  * field, then writes this into the next status ring entry.
4028  *
4029  * Each ring the host uses to post buffers to the chip is described
4030  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4031  * it is first placed into the on-chip ram.  When the packet's length
4032  * is known, it walks down the TG3_BDINFO entries to select the ring.
4033  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4034  * which is within the range of the new packet's length is chosen.
4035  *
4036  * The "separate ring for rx status" scheme may sound queer, but it makes
4037  * sense from a cache coherency perspective.  If only the host writes
4038  * to the buffer post rings, and only the chip writes to the rx status
4039  * rings, then cache lines never move beyond shared-modified state.
4040  * If both the host and chip were to write into the same ring, cache line
4041  * eviction could occur since both entities want it in an exclusive state.
4042  */
4043 static int tg3_rx(struct tg3 *tp, int budget)
4044 {
4045         u32 work_mask, rx_std_posted = 0;
4046         u32 sw_idx = tp->rx_rcb_ptr;
4047         u16 hw_idx;
4048         int received;
4049
4050         hw_idx = tp->hw_status->idx[0].rx_producer;
4051         /*
4052          * We need to order the read of hw_idx and the read of
4053          * the opaque cookie.
4054          */
4055         rmb();
4056         work_mask = 0;
4057         received = 0;
4058         while (sw_idx != hw_idx && budget > 0) {
4059                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
4060                 unsigned int len;
4061                 struct sk_buff *skb;
4062                 dma_addr_t dma_addr;
4063                 u32 opaque_key, desc_idx, *post_ptr;
4064
4065                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4066                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4067                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4068                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
4069                                                   mapping);
4070                         skb = tp->rx_std_buffers[desc_idx].skb;
4071                         post_ptr = &tp->rx_std_ptr;
4072                         rx_std_posted++;
4073                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4074                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
4075                                                   mapping);
4076                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
4077                         post_ptr = &tp->rx_jumbo_ptr;
4078                 }
4079                 else {
4080                         goto next_pkt_nopost;
4081                 }
4082
4083                 work_mask |= opaque_key;
4084
4085                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4086                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4087                 drop_it:
4088                         tg3_recycle_rx(tp, opaque_key,
4089                                        desc_idx, *post_ptr);
4090                 drop_it_no_recycle:
4091                         /* Other statistics kept track of by card. */
4092                         tp->net_stats.rx_dropped++;
4093                         goto next_pkt;
4094                 }
4095
4096                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
4097
4098                 if (len > RX_COPY_THRESHOLD
4099                         && tp->rx_offset == 2
4100                         /* rx_offset != 2 iff this is a 5701 card running
4101                          * in PCI-X mode [see tg3_get_invariants()] */
4102                 ) {
4103                         int skb_size;
4104
4105                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
4106                                                     desc_idx, *post_ptr);
4107                         if (skb_size < 0)
4108                                 goto drop_it;
4109
4110                         pci_unmap_single(tp->pdev, dma_addr,
4111                                          skb_size - tp->rx_offset,
4112                                          PCI_DMA_FROMDEVICE);
4113
4114                         skb_put(skb, len);
4115                 } else {
4116                         struct sk_buff *copy_skb;
4117
4118                         tg3_recycle_rx(tp, opaque_key,
4119                                        desc_idx, *post_ptr);
4120
4121                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
4122                         if (copy_skb == NULL)
4123                                 goto drop_it_no_recycle;
4124
4125                         skb_reserve(copy_skb, 2);
4126                         skb_put(copy_skb, len);
4127                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4128                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4129                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4130
4131                         /* We'll reuse the original ring buffer. */
4132                         skb = copy_skb;
4133                 }
4134
4135                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4136                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4137                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4138                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4139                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4140                 else
4141                         skb->ip_summed = CHECKSUM_NONE;
4142
4143                 skb->protocol = eth_type_trans(skb, tp->dev);
4144 #if TG3_VLAN_TAG_USED
4145                 if (tp->vlgrp != NULL &&
4146                     desc->type_flags & RXD_FLAG_VLAN) {
4147                         tg3_vlan_rx(tp, skb,
4148                                     desc->err_vlan & RXD_VLAN_MASK);
4149                 } else
4150 #endif
4151                         netif_receive_skb(skb);
4152
4153                 tp->dev->last_rx = jiffies;
4154                 received++;
4155                 budget--;
4156
4157 next_pkt:
4158                 (*post_ptr)++;
4159
4160                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4161                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4162
4163                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
4164                                      TG3_64BIT_REG_LOW, idx);
4165                         work_mask &= ~RXD_OPAQUE_RING_STD;
4166                         rx_std_posted = 0;
4167                 }
4168 next_pkt_nopost:
4169                 sw_idx++;
4170                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4171
4172                 /* Refresh hw_idx to see if there is new work */
4173                 if (sw_idx == hw_idx) {
4174                         hw_idx = tp->hw_status->idx[0].rx_producer;
4175                         rmb();
4176                 }
4177         }
4178
4179         /* ACK the status ring. */
4180         tp->rx_rcb_ptr = sw_idx;
4181         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
4182
4183         /* Refill RX ring(s). */
4184         if (work_mask & RXD_OPAQUE_RING_STD) {
4185                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
4186                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4187                              sw_idx);
4188         }
4189         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4190                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
4191                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4192                              sw_idx);
4193         }
4194         mmiowb();
4195
4196         return received;
4197 }
4198
4199 static int tg3_poll_work(struct tg3 *tp, int work_done, int budget)
4200 {
4201         struct tg3_hw_status *sblk = tp->hw_status;
4202
4203         /* handle link change and other phy events */
4204         if (!(tp->tg3_flags &
4205               (TG3_FLAG_USE_LINKCHG_REG |
4206                TG3_FLAG_POLL_SERDES))) {
4207                 if (sblk->status & SD_STATUS_LINK_CHG) {
4208                         sblk->status = SD_STATUS_UPDATED |
4209                                 (sblk->status & ~SD_STATUS_LINK_CHG);
4210                         spin_lock(&tp->lock);
4211                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4212                                 tw32_f(MAC_STATUS,
4213                                      (MAC_STATUS_SYNC_CHANGED |
4214                                       MAC_STATUS_CFG_CHANGED |
4215                                       MAC_STATUS_MI_COMPLETION |
4216                                       MAC_STATUS_LNKSTATE_CHANGED));
4217                                 udelay(40);
4218                         } else
4219                                 tg3_setup_phy(tp, 0);
4220                         spin_unlock(&tp->lock);
4221                 }
4222         }
4223
4224         /* run TX completion thread */
4225         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
4226                 tg3_tx(tp);
4227                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4228                         return work_done;
4229         }
4230
4231         /* run RX thread, within the bounds set by NAPI.
4232          * All RX "locking" is done by ensuring outside
4233          * code synchronizes with tg3->napi.poll()
4234          */
4235         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
4236                 work_done += tg3_rx(tp, budget - work_done);
4237
4238         return work_done;
4239 }
4240
4241 static int tg3_poll(struct napi_struct *napi, int budget)
4242 {
4243         struct tg3 *tp = container_of(napi, struct tg3, napi);
4244         int work_done = 0;
4245         struct tg3_hw_status *sblk = tp->hw_status;
4246
4247         while (1) {
4248                 work_done = tg3_poll_work(tp, work_done, budget);
4249
4250                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4251                         goto tx_recovery;
4252
4253                 if (unlikely(work_done >= budget))
4254                         break;
4255
4256                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4257                         /* tp->last_tag is used in tg3_restart_ints() below
4258                          * to tell the hw how much work has been processed,
4259                          * so we must read it before checking for more work.
4260                          */
4261                         tp->last_tag = sblk->status_tag;
4262                         rmb();
4263                 } else
4264                         sblk->status &= ~SD_STATUS_UPDATED;
4265
4266                 if (likely(!tg3_has_work(tp))) {
4267                         netif_rx_complete(tp->dev, napi);
4268                         tg3_restart_ints(tp);
4269                         break;
4270                 }
4271         }
4272
4273         return work_done;
4274
4275 tx_recovery:
4276         /* work_done is guaranteed to be less than budget. */
4277         netif_rx_complete(tp->dev, napi);
4278         schedule_work(&tp->reset_task);
4279         return work_done;
4280 }
4281
4282 static void tg3_irq_quiesce(struct tg3 *tp)
4283 {
4284         BUG_ON(tp->irq_sync);
4285
4286         tp->irq_sync = 1;
4287         smp_mb();
4288
4289         synchronize_irq(tp->pdev->irq);
4290 }
4291
4292 static inline int tg3_irq_sync(struct tg3 *tp)
4293 {
4294         return tp->irq_sync;
4295 }
4296
4297 /* Fully shutdown all tg3 driver activity elsewhere in the system.
4298  * If irq_sync is non-zero, then the IRQ handler must be synchronized
4299  * with as well.  Most of the time, this is not necessary except when
4300  * shutting down the device.
4301  */
4302 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
4303 {
4304         spin_lock_bh(&tp->lock);
4305         if (irq_sync)
4306                 tg3_irq_quiesce(tp);
4307 }
4308
4309 static inline void tg3_full_unlock(struct tg3 *tp)
4310 {
4311         spin_unlock_bh(&tp->lock);
4312 }
4313
4314 /* One-shot MSI handler - Chip automatically disables interrupt
4315  * after sending MSI so driver doesn't have to do it.
4316  */
4317 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
4318 {
4319         struct net_device *dev = dev_id;
4320         struct tg3 *tp = netdev_priv(dev);
4321
4322         prefetch(tp->hw_status);
4323         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4324
4325         if (likely(!tg3_irq_sync(tp)))
4326                 netif_rx_schedule(dev, &tp->napi);
4327
4328         return IRQ_HANDLED;
4329 }
4330
4331 /* MSI ISR - No need to check for interrupt sharing and no need to
4332  * flush status block and interrupt mailbox. PCI ordering rules
4333  * guarantee that MSI will arrive after the status block.
4334  */
4335 static irqreturn_t tg3_msi(int irq, void *dev_id)
4336 {
4337         struct net_device *dev = dev_id;
4338         struct tg3 *tp = netdev_priv(dev);
4339
4340         prefetch(tp->hw_status);
4341         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4342         /*
4343          * Writing any value to intr-mbox-0 clears PCI INTA# and
4344          * chip-internal interrupt pending events.
4345          * Writing non-zero to intr-mbox-0 additional tells the
4346          * NIC to stop sending us irqs, engaging "in-intr-handler"
4347          * event coalescing.
4348          */
4349         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4350         if (likely(!tg3_irq_sync(tp)))
4351                 netif_rx_schedule(dev, &tp->napi);
4352
4353         return IRQ_RETVAL(1);
4354 }
4355
4356 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
4357 {
4358         struct net_device *dev = dev_id;
4359         struct tg3 *tp = netdev_priv(dev);
4360         struct tg3_hw_status *sblk = tp->hw_status;
4361         unsigned int handled = 1;
4362
4363         /* In INTx mode, it is possible for the interrupt to arrive at
4364          * the CPU before the status block posted prior to the interrupt.
4365          * Reading the PCI State register will confirm whether the
4366          * interrupt is ours and will flush the status block.
4367          */
4368         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
4369                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4370                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4371                         handled = 0;
4372                         goto out;
4373                 }
4374         }
4375
4376         /*
4377          * Writing any value to intr-mbox-0 clears PCI INTA# and
4378          * chip-internal interrupt pending events.
4379          * Writing non-zero to intr-mbox-0 additional tells the
4380          * NIC to stop sending us irqs, engaging "in-intr-handler"
4381          * event coalescing.
4382          *
4383          * Flush the mailbox to de-assert the IRQ immediately to prevent
4384          * spurious interrupts.  The flush impacts performance but
4385          * excessive spurious interrupts can be worse in some cases.
4386          */
4387         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4388         if (tg3_irq_sync(tp))
4389                 goto out;
4390         sblk->status &= ~SD_STATUS_UPDATED;
4391         if (likely(tg3_has_work(tp))) {
4392                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4393                 netif_rx_schedule(dev, &tp->napi);
4394         } else {
4395                 /* No work, shared interrupt perhaps?  re-enable
4396                  * interrupts, and flush that PCI write
4397                  */
4398                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
4399                                0x00000000);
4400         }
4401 out:
4402         return IRQ_RETVAL(handled);
4403 }
4404
4405 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
4406 {
4407         struct net_device *dev = dev_id;
4408         struct tg3 *tp = netdev_priv(dev);
4409         struct tg3_hw_status *sblk = tp->hw_status;
4410         unsigned int handled = 1;
4411
4412         /* In INTx mode, it is possible for the interrupt to arrive at
4413          * the CPU before the status block posted prior to the interrupt.
4414          * Reading the PCI State register will confirm whether the
4415          * interrupt is ours and will flush the status block.
4416          */
4417         if (unlikely(sblk->status_tag == tp->last_tag)) {
4418                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
4419                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4420                         handled = 0;
4421                         goto out;
4422                 }
4423         }
4424
4425         /*
4426          * writing any value to intr-mbox-0 clears PCI INTA# and
4427          * chip-internal interrupt pending events.
4428          * writing non-zero to intr-mbox-0 additional tells the
4429          * NIC to stop sending us irqs, engaging "in-intr-handler"
4430          * event coalescing.
4431          *
4432          * Flush the mailbox to de-assert the IRQ immediately to prevent
4433          * spurious interrupts.  The flush impacts performance but
4434          * excessive spurious interrupts can be worse in some cases.
4435          */
4436         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
4437         if (tg3_irq_sync(tp))
4438                 goto out;
4439         if (netif_rx_schedule_prep(dev, &tp->napi)) {
4440                 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
4441                 /* Update last_tag to mark that this status has been
4442                  * seen. Because interrupt may be shared, we may be
4443                  * racing with tg3_poll(), so only update last_tag
4444                  * if tg3_poll() is not scheduled.
4445                  */
4446                 tp->last_tag = sblk->status_tag;
4447                 __netif_rx_schedule(dev, &tp->napi);
4448         }
4449 out:
4450         return IRQ_RETVAL(handled);
4451 }
4452
4453 /* ISR for interrupt test */
4454 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
4455 {
4456         struct net_device *dev = dev_id;
4457         struct tg3 *tp = netdev_priv(dev);
4458         struct tg3_hw_status *sblk = tp->hw_status;
4459
4460         if ((sblk->status & SD_STATUS_UPDATED) ||
4461             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
4462                 tg3_disable_ints(tp);
4463                 return IRQ_RETVAL(1);
4464         }
4465         return IRQ_RETVAL(0);
4466 }
4467
4468 static int tg3_init_hw(struct tg3 *, int);
4469 static int tg3_halt(struct tg3 *, int, int);
4470
4471 /* Restart hardware after configuration changes, self-test, etc.
4472  * Invoked with tp->lock held.
4473  */
4474 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
4475         __releases(tp->lock)
4476         __acquires(tp->lock)
4477 {
4478         int err;
4479
4480         err = tg3_init_hw(tp, reset_phy);
4481         if (err) {
4482                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
4483                        "aborting.\n", tp->dev->name);
4484                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4485                 tg3_full_unlock(tp);
4486                 del_timer_sync(&tp->timer);
4487                 tp->irq_sync = 0;
4488                 napi_enable(&tp->napi);
4489                 dev_close(tp->dev);
4490                 tg3_full_lock(tp, 0);
4491         }
4492         return err;
4493 }
4494
4495 #ifdef CONFIG_NET_POLL_CONTROLLER
4496 static void tg3_poll_controller(struct net_device *dev)
4497 {
4498         struct tg3 *tp = netdev_priv(dev);
4499
4500         tg3_interrupt(tp->pdev->irq, dev);
4501 }
4502 #endif
4503
4504 static void tg3_reset_task(struct work_struct *work)
4505 {
4506         struct tg3 *tp = container_of(work, struct tg3, reset_task);
4507         int err;
4508         unsigned int restart_timer;
4509
4510         tg3_full_lock(tp, 0);
4511
4512         if (!netif_running(tp->dev)) {
4513                 tg3_full_unlock(tp);
4514                 return;
4515         }
4516
4517         tg3_full_unlock(tp);
4518
4519         tg3_phy_stop(tp);
4520
4521         tg3_netif_stop(tp);
4522
4523         tg3_full_lock(tp, 1);
4524
4525         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
4526         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
4527
4528         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
4529                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
4530                 tp->write32_rx_mbox = tg3_write_flush_reg32;
4531                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
4532                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
4533         }
4534
4535         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
4536         err = tg3_init_hw(tp, 1);
4537         if (err)
4538                 goto out;
4539
4540         tg3_netif_start(tp);
4541
4542         if (restart_timer)
4543                 mod_timer(&tp->timer, jiffies + 1);
4544
4545 out:
4546         tg3_full_unlock(tp);
4547
4548         if (!err)
4549                 tg3_phy_start(tp);
4550 }
4551
4552 static void tg3_dump_short_state(struct tg3 *tp)
4553 {
4554         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
4555                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
4556         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
4557                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
4558 }
4559
4560 static void tg3_tx_timeout(struct net_device *dev)
4561 {
4562         struct tg3 *tp = netdev_priv(dev);
4563
4564         if (netif_msg_tx_err(tp)) {
4565                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
4566                        dev->name);
4567                 tg3_dump_short_state(tp);
4568         }
4569
4570         schedule_work(&tp->reset_task);
4571 }
4572
4573 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
4574 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
4575 {
4576         u32 base = (u32) mapping & 0xffffffff;
4577
4578         return ((base > 0xffffdcc0) &&
4579                 (base + len + 8 < base));
4580 }
4581
4582 /* Test for DMA addresses > 40-bit */
4583 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
4584                                           int len)
4585 {
4586 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
4587         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
4588                 return (((u64) mapping + len) > DMA_40BIT_MASK);
4589         return 0;
4590 #else
4591         return 0;
4592 #endif
4593 }
4594
4595 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
4596
4597 /* Workaround 4GB and 40-bit hardware DMA bugs. */
4598 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
4599                                        u32 last_plus_one, u32 *start,
4600                                        u32 base_flags, u32 mss)
4601 {
4602         struct sk_buff *new_skb;
4603         dma_addr_t new_addr = 0;
4604         u32 entry = *start;
4605         int i, ret = 0;
4606
4607         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
4608                 new_skb = skb_copy(skb, GFP_ATOMIC);
4609         else {
4610                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
4611
4612                 new_skb = skb_copy_expand(skb,
4613                                           skb_headroom(skb) + more_headroom,
4614                                           skb_tailroom(skb), GFP_ATOMIC);
4615         }
4616
4617         if (!new_skb) {
4618                 ret = -1;
4619         } else {
4620                 /* New SKB is guaranteed to be linear. */
4621                 entry = *start;
4622                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
4623                                           PCI_DMA_TODEVICE);
4624                 /* Make sure new skb does not cross any 4G boundaries.
4625                  * Drop the packet if it does.
4626                  */
4627                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
4628                         ret = -1;
4629                         dev_kfree_skb(new_skb);
4630                         new_skb = NULL;
4631                 } else {
4632                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
4633                                     base_flags, 1 | (mss << 1));
4634                         *start = NEXT_TX(entry);
4635                 }
4636         }
4637
4638         /* Now clean up the sw ring entries. */
4639         i = 0;
4640         while (entry != last_plus_one) {
4641                 int len;
4642
4643                 if (i == 0)
4644                         len = skb_headlen(skb);
4645                 else
4646                         len = skb_shinfo(skb)->frags[i-1].size;
4647                 pci_unmap_single(tp->pdev,
4648                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
4649                                  len, PCI_DMA_TODEVICE);
4650                 if (i == 0) {
4651                         tp->tx_buffers[entry].skb = new_skb;
4652                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
4653                 } else {
4654                         tp->tx_buffers[entry].skb = NULL;
4655                 }
4656                 entry = NEXT_TX(entry);
4657                 i++;
4658         }
4659
4660         dev_kfree_skb(skb);
4661
4662         return ret;
4663 }
4664
4665 static void tg3_set_txd(struct tg3 *tp, int entry,
4666                         dma_addr_t mapping, int len, u32 flags,
4667                         u32 mss_and_is_end)
4668 {
4669         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
4670         int is_end = (mss_and_is_end & 0x1);
4671         u32 mss = (mss_and_is_end >> 1);
4672         u32 vlan_tag = 0;
4673
4674         if (is_end)
4675                 flags |= TXD_FLAG_END;
4676         if (flags & TXD_FLAG_VLAN) {
4677                 vlan_tag = flags >> 16;
4678                 flags &= 0xffff;
4679         }
4680         vlan_tag |= (mss << TXD_MSS_SHIFT);
4681
4682         txd->addr_hi = ((u64) mapping >> 32);
4683         txd->addr_lo = ((u64) mapping & 0xffffffff);
4684         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
4685         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
4686 }
4687
4688 /* hard_start_xmit for devices that don't have any bugs and
4689  * support TG3_FLG2_HW_TSO_2 only.
4690  */
4691 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
4692 {
4693         struct tg3 *tp = netdev_priv(dev);
4694         dma_addr_t mapping;
4695         u32 len, entry, base_flags, mss;
4696
4697         len = skb_headlen(skb);
4698
4699         /* We are running in BH disabled context with netif_tx_lock
4700          * and TX reclaim runs via tp->napi.poll inside of a software
4701          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4702          * no IRQ context deadlocks to worry about either.  Rejoice!
4703          */
4704         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4705                 if (!netif_queue_stopped(dev)) {
4706                         netif_stop_queue(dev);
4707
4708                         /* This is a hard error, log it. */
4709                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4710                                "queue awake!\n", dev->name);
4711                 }
4712                 return NETDEV_TX_BUSY;
4713         }
4714
4715         entry = tp->tx_prod;
4716         base_flags = 0;
4717         mss = 0;
4718         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4719                 int tcp_opt_len, ip_tcp_len;
4720
4721                 if (skb_header_cloned(skb) &&
4722                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4723                         dev_kfree_skb(skb);
4724                         goto out_unlock;
4725                 }
4726
4727                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
4728                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
4729                 else {
4730                         struct iphdr *iph = ip_hdr(skb);
4731
4732                         tcp_opt_len = tcp_optlen(skb);
4733                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4734
4735                         iph->check = 0;
4736                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4737                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
4738                 }
4739
4740                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4741                                TXD_FLAG_CPU_POST_DMA);
4742
4743                 tcp_hdr(skb)->check = 0;
4744
4745         }
4746         else if (skb->ip_summed == CHECKSUM_PARTIAL)
4747                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4748 #if TG3_VLAN_TAG_USED
4749         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4750                 base_flags |= (TXD_FLAG_VLAN |
4751                                (vlan_tx_tag_get(skb) << 16));
4752 #endif
4753
4754         /* Queue skb data, a.k.a. the main skb fragment. */
4755         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4756
4757         tp->tx_buffers[entry].skb = skb;
4758         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4759
4760         tg3_set_txd(tp, entry, mapping, len, base_flags,
4761                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4762
4763         entry = NEXT_TX(entry);
4764
4765         /* Now loop through additional data fragments, and queue them. */
4766         if (skb_shinfo(skb)->nr_frags > 0) {
4767                 unsigned int i, last;
4768
4769                 last = skb_shinfo(skb)->nr_frags - 1;
4770                 for (i = 0; i <= last; i++) {
4771                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4772
4773                         len = frag->size;
4774                         mapping = pci_map_page(tp->pdev,
4775                                                frag->page,
4776                                                frag->page_offset,
4777                                                len, PCI_DMA_TODEVICE);
4778
4779                         tp->tx_buffers[entry].skb = NULL;
4780                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4781
4782                         tg3_set_txd(tp, entry, mapping, len,
4783                                     base_flags, (i == last) | (mss << 1));
4784
4785                         entry = NEXT_TX(entry);
4786                 }
4787         }
4788
4789         /* Packets are ready, update Tx producer idx local and on card. */
4790         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4791
4792         tp->tx_prod = entry;
4793         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4794                 netif_stop_queue(dev);
4795                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4796                         netif_wake_queue(tp->dev);
4797         }
4798
4799 out_unlock:
4800         mmiowb();
4801
4802         dev->trans_start = jiffies;
4803
4804         return NETDEV_TX_OK;
4805 }
4806
4807 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4808
4809 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4810  * TSO header is greater than 80 bytes.
4811  */
4812 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4813 {
4814         struct sk_buff *segs, *nskb;
4815
4816         /* Estimate the number of fragments in the worst case */
4817         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4818                 netif_stop_queue(tp->dev);
4819                 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4820                         return NETDEV_TX_BUSY;
4821
4822                 netif_wake_queue(tp->dev);
4823         }
4824
4825         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4826         if (IS_ERR(segs))
4827                 goto tg3_tso_bug_end;
4828
4829         do {
4830                 nskb = segs;
4831                 segs = segs->next;
4832                 nskb->next = NULL;
4833                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4834         } while (segs);
4835
4836 tg3_tso_bug_end:
4837         dev_kfree_skb(skb);
4838
4839         return NETDEV_TX_OK;
4840 }
4841
4842 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4843  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4844  */
4845 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4846 {
4847         struct tg3 *tp = netdev_priv(dev);
4848         dma_addr_t mapping;
4849         u32 len, entry, base_flags, mss;
4850         int would_hit_hwbug;
4851
4852         len = skb_headlen(skb);
4853
4854         /* We are running in BH disabled context with netif_tx_lock
4855          * and TX reclaim runs via tp->napi.poll inside of a software
4856          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4857          * no IRQ context deadlocks to worry about either.  Rejoice!
4858          */
4859         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4860                 if (!netif_queue_stopped(dev)) {
4861                         netif_stop_queue(dev);
4862
4863                         /* This is a hard error, log it. */
4864                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4865                                "queue awake!\n", dev->name);
4866                 }
4867                 return NETDEV_TX_BUSY;
4868         }
4869
4870         entry = tp->tx_prod;
4871         base_flags = 0;
4872         if (skb->ip_summed == CHECKSUM_PARTIAL)
4873                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4874         mss = 0;
4875         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4876                 struct iphdr *iph;
4877                 int tcp_opt_len, ip_tcp_len, hdr_len;
4878
4879                 if (skb_header_cloned(skb) &&
4880                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4881                         dev_kfree_skb(skb);
4882                         goto out_unlock;
4883                 }
4884
4885                 tcp_opt_len = tcp_optlen(skb);
4886                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4887
4888                 hdr_len = ip_tcp_len + tcp_opt_len;
4889                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4890                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4891                         return (tg3_tso_bug(tp, skb));
4892
4893                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4894                                TXD_FLAG_CPU_POST_DMA);
4895
4896                 iph = ip_hdr(skb);
4897                 iph->check = 0;
4898                 iph->tot_len = htons(mss + hdr_len);
4899                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4900                         tcp_hdr(skb)->check = 0;
4901                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4902                 } else
4903                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4904                                                                  iph->daddr, 0,
4905                                                                  IPPROTO_TCP,
4906                                                                  0);
4907
4908                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4909                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4910                         if (tcp_opt_len || iph->ihl > 5) {
4911                                 int tsflags;
4912
4913                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4914                                 mss |= (tsflags << 11);
4915                         }
4916                 } else {
4917                         if (tcp_opt_len || iph->ihl > 5) {
4918                                 int tsflags;
4919
4920                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4921                                 base_flags |= tsflags << 12;
4922                         }
4923                 }
4924         }
4925 #if TG3_VLAN_TAG_USED
4926         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4927                 base_flags |= (TXD_FLAG_VLAN |
4928                                (vlan_tx_tag_get(skb) << 16));
4929 #endif
4930
4931         /* Queue skb data, a.k.a. the main skb fragment. */
4932         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4933
4934         tp->tx_buffers[entry].skb = skb;
4935         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4936
4937         would_hit_hwbug = 0;
4938
4939         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
4940                 would_hit_hwbug = 1;
4941         else if (tg3_4g_overflow_test(mapping, len))
4942                 would_hit_hwbug = 1;
4943
4944         tg3_set_txd(tp, entry, mapping, len, base_flags,
4945                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4946
4947         entry = NEXT_TX(entry);
4948
4949         /* Now loop through additional data fragments, and queue them. */
4950         if (skb_shinfo(skb)->nr_frags > 0) {
4951                 unsigned int i, last;
4952
4953                 last = skb_shinfo(skb)->nr_frags - 1;
4954                 for (i = 0; i <= last; i++) {
4955                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4956
4957                         len = frag->size;
4958                         mapping = pci_map_page(tp->pdev,
4959                                                frag->page,
4960                                                frag->page_offset,
4961                                                len, PCI_DMA_TODEVICE);
4962
4963                         tp->tx_buffers[entry].skb = NULL;
4964                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4965
4966                         if (tg3_4g_overflow_test(mapping, len))
4967                                 would_hit_hwbug = 1;
4968
4969                         if (tg3_40bit_overflow_test(tp, mapping, len))
4970                                 would_hit_hwbug = 1;
4971
4972                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4973                                 tg3_set_txd(tp, entry, mapping, len,
4974                                             base_flags, (i == last)|(mss << 1));
4975                         else
4976                                 tg3_set_txd(tp, entry, mapping, len,
4977                                             base_flags, (i == last));
4978
4979                         entry = NEXT_TX(entry);
4980                 }
4981         }
4982
4983         if (would_hit_hwbug) {
4984                 u32 last_plus_one = entry;
4985                 u32 start;
4986
4987                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4988                 start &= (TG3_TX_RING_SIZE - 1);
4989
4990                 /* If the workaround fails due to memory/mapping
4991                  * failure, silently drop this packet.
4992                  */
4993                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4994                                                 &start, base_flags, mss))
4995                         goto out_unlock;
4996
4997                 entry = start;
4998         }
4999
5000         /* Packets are ready, update Tx producer idx local and on card. */
5001         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
5002
5003         tp->tx_prod = entry;
5004         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
5005                 netif_stop_queue(dev);
5006                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
5007                         netif_wake_queue(tp->dev);
5008         }
5009
5010 out_unlock:
5011         mmiowb();
5012
5013         dev->trans_start = jiffies;
5014
5015         return NETDEV_TX_OK;
5016 }
5017
5018 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5019                                int new_mtu)
5020 {
5021         dev->mtu = new_mtu;
5022
5023         if (new_mtu > ETH_DATA_LEN) {
5024                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5025                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5026                         ethtool_op_set_tso(dev, 0);
5027                 }
5028                 else
5029                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5030         } else {
5031                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5032                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5033                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5034         }
5035 }
5036
5037 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5038 {
5039         struct tg3 *tp = netdev_priv(dev);
5040         int err;
5041
5042         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5043                 return -EINVAL;
5044
5045         if (!netif_running(dev)) {
5046                 /* We'll just catch it later when the
5047                  * device is up'd.
5048                  */
5049                 tg3_set_mtu(dev, tp, new_mtu);
5050                 return 0;
5051         }
5052
5053         tg3_phy_stop(tp);
5054
5055         tg3_netif_stop(tp);
5056
5057         tg3_full_lock(tp, 1);
5058
5059         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5060
5061         tg3_set_mtu(dev, tp, new_mtu);
5062
5063         err = tg3_restart_hw(tp, 0);
5064
5065         if (!err)
5066                 tg3_netif_start(tp);
5067
5068         tg3_full_unlock(tp);
5069
5070         if (!err)
5071                 tg3_phy_start(tp);
5072
5073         return err;
5074 }
5075
5076 /* Free up pending packets in all rx/tx rings.
5077  *
5078  * The chip has been shut down and the driver detached from
5079  * the networking, so no interrupts or new tx packets will
5080  * end up in the driver.  tp->{tx,}lock is not held and we are not
5081  * in an interrupt context and thus may sleep.
5082  */
5083 static void tg3_free_rings(struct tg3 *tp)
5084 {
5085         struct ring_info *rxp;
5086         int i;
5087
5088         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5089                 rxp = &tp->rx_std_buffers[i];
5090
5091                 if (rxp->skb == NULL)
5092                         continue;
5093                 pci_unmap_single(tp->pdev,
5094                                  pci_unmap_addr(rxp, mapping),
5095                                  tp->rx_pkt_buf_sz - tp->rx_offset,
5096                                  PCI_DMA_FROMDEVICE);
5097                 dev_kfree_skb_any(rxp->skb);
5098                 rxp->skb = NULL;
5099         }
5100
5101         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5102                 rxp = &tp->rx_jumbo_buffers[i];
5103
5104                 if (rxp->skb == NULL)
5105                         continue;
5106                 pci_unmap_single(tp->pdev,
5107                                  pci_unmap_addr(rxp, mapping),
5108                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
5109                                  PCI_DMA_FROMDEVICE);
5110                 dev_kfree_skb_any(rxp->skb);
5111                 rxp->skb = NULL;
5112         }
5113
5114         for (i = 0; i < TG3_TX_RING_SIZE; ) {
5115                 struct tx_ring_info *txp;
5116                 struct sk_buff *skb;
5117                 int j;
5118
5119                 txp = &tp->tx_buffers[i];
5120                 skb = txp->skb;
5121
5122                 if (skb == NULL) {
5123                         i++;
5124                         continue;
5125                 }
5126
5127                 pci_unmap_single(tp->pdev,
5128                                  pci_unmap_addr(txp, mapping),
5129                                  skb_headlen(skb),
5130                                  PCI_DMA_TODEVICE);
5131                 txp->skb = NULL;
5132
5133                 i++;
5134
5135                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
5136                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
5137                         pci_unmap_page(tp->pdev,
5138                                        pci_unmap_addr(txp, mapping),
5139                                        skb_shinfo(skb)->frags[j].size,
5140                                        PCI_DMA_TODEVICE);
5141                         i++;
5142                 }
5143
5144                 dev_kfree_skb_any(skb);
5145         }
5146 }
5147
5148 /* Initialize tx/rx rings for packet processing.
5149  *
5150  * The chip has been shut down and the driver detached from
5151  * the networking, so no interrupts or new tx packets will
5152  * end up in the driver.  tp->{tx,}lock are held and thus
5153  * we may not sleep.
5154  */
5155 static int tg3_init_rings(struct tg3 *tp)
5156 {
5157         u32 i;
5158
5159         /* Free up all the SKBs. */
5160         tg3_free_rings(tp);
5161
5162         /* Zero out all descriptors. */
5163         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
5164         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
5165         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
5166         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
5167
5168         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
5169         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5170             (tp->dev->mtu > ETH_DATA_LEN))
5171                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
5172
5173         /* Initialize invariants of the rings, we only set this
5174          * stuff once.  This works because the card does not
5175          * write into the rx buffer posting rings.
5176          */
5177         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5178                 struct tg3_rx_buffer_desc *rxd;
5179
5180                 rxd = &tp->rx_std[i];
5181                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
5182                         << RXD_LEN_SHIFT;
5183                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
5184                 rxd->opaque = (RXD_OPAQUE_RING_STD |
5185                                (i << RXD_OPAQUE_INDEX_SHIFT));
5186         }
5187
5188         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5189                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
5190                         struct tg3_rx_buffer_desc *rxd;
5191
5192                         rxd = &tp->rx_jumbo[i];
5193                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
5194                                 << RXD_LEN_SHIFT;
5195                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
5196                                 RXD_FLAG_JUMBO;
5197                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
5198                                (i << RXD_OPAQUE_INDEX_SHIFT));
5199                 }
5200         }
5201
5202         /* Now allocate fresh SKBs for each rx ring. */
5203         for (i = 0; i < tp->rx_pending; i++) {
5204                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
5205                         printk(KERN_WARNING PFX
5206                                "%s: Using a smaller RX standard ring, "
5207                                "only %d out of %d buffers were allocated "
5208                                "successfully.\n",
5209                                tp->dev->name, i, tp->rx_pending);
5210                         if (i == 0)
5211                                 return -ENOMEM;
5212                         tp->rx_pending = i;
5213                         break;
5214                 }
5215         }
5216
5217         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5218                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
5219                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
5220                                              -1, i) < 0) {
5221                                 printk(KERN_WARNING PFX
5222                                        "%s: Using a smaller RX jumbo ring, "
5223                                        "only %d out of %d buffers were "
5224                                        "allocated successfully.\n",
5225                                        tp->dev->name, i, tp->rx_jumbo_pending);
5226                                 if (i == 0) {
5227                                         tg3_free_rings(tp);
5228                                         return -ENOMEM;
5229                                 }
5230                                 tp->rx_jumbo_pending = i;
5231                                 break;
5232                         }
5233                 }
5234         }
5235         return 0;
5236 }
5237
5238 /*
5239  * Must not be invoked with interrupt sources disabled and
5240  * the hardware shutdown down.
5241  */
5242 static void tg3_free_consistent(struct tg3 *tp)
5243 {
5244         kfree(tp->rx_std_buffers);
5245         tp->rx_std_buffers = NULL;
5246         if (tp->rx_std) {
5247                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
5248                                     tp->rx_std, tp->rx_std_mapping);
5249                 tp->rx_std = NULL;
5250         }
5251         if (tp->rx_jumbo) {
5252                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5253                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
5254                 tp->rx_jumbo = NULL;
5255         }
5256         if (tp->rx_rcb) {
5257                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5258                                     tp->rx_rcb, tp->rx_rcb_mapping);
5259                 tp->rx_rcb = NULL;
5260         }
5261         if (tp->tx_ring) {
5262                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
5263                         tp->tx_ring, tp->tx_desc_mapping);
5264                 tp->tx_ring = NULL;
5265         }
5266         if (tp->hw_status) {
5267                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
5268                                     tp->hw_status, tp->status_mapping);
5269                 tp->hw_status = NULL;
5270         }
5271         if (tp->hw_stats) {
5272                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
5273                                     tp->hw_stats, tp->stats_mapping);
5274                 tp->hw_stats = NULL;
5275         }
5276 }
5277
5278 /*
5279  * Must not be invoked with interrupt sources disabled and
5280  * the hardware shutdown down.  Can sleep.
5281  */
5282 static int tg3_alloc_consistent(struct tg3 *tp)
5283 {
5284         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
5285                                       (TG3_RX_RING_SIZE +
5286                                        TG3_RX_JUMBO_RING_SIZE)) +
5287                                      (sizeof(struct tx_ring_info) *
5288                                       TG3_TX_RING_SIZE),
5289                                      GFP_KERNEL);
5290         if (!tp->rx_std_buffers)
5291                 return -ENOMEM;
5292
5293         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
5294         tp->tx_buffers = (struct tx_ring_info *)
5295                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
5296
5297         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
5298                                           &tp->rx_std_mapping);
5299         if (!tp->rx_std)
5300                 goto err_out;
5301
5302         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
5303                                             &tp->rx_jumbo_mapping);
5304
5305         if (!tp->rx_jumbo)
5306                 goto err_out;
5307
5308         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
5309                                           &tp->rx_rcb_mapping);
5310         if (!tp->rx_rcb)
5311                 goto err_out;
5312
5313         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
5314                                            &tp->tx_desc_mapping);
5315         if (!tp->tx_ring)
5316                 goto err_out;
5317
5318         tp->hw_status = pci_alloc_consistent(tp->pdev,
5319                                              TG3_HW_STATUS_SIZE,
5320                                              &tp->status_mapping);
5321         if (!tp->hw_status)
5322                 goto err_out;
5323
5324         tp->hw_stats = pci_alloc_consistent(tp->pdev,
5325                                             sizeof(struct tg3_hw_stats),
5326                                             &tp->stats_mapping);
5327         if (!tp->hw_stats)
5328                 goto err_out;
5329
5330         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5331         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5332
5333         return 0;
5334
5335 err_out:
5336         tg3_free_consistent(tp);
5337         return -ENOMEM;
5338 }
5339
5340 #define MAX_WAIT_CNT 1000
5341
5342 /* To stop a block, clear the enable bit and poll till it
5343  * clears.  tp->lock is held.
5344  */
5345 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
5346 {
5347         unsigned int i;
5348         u32 val;
5349
5350         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5351                 switch (ofs) {
5352                 case RCVLSC_MODE:
5353                 case DMAC_MODE:
5354                 case MBFREE_MODE:
5355                 case BUFMGR_MODE:
5356                 case MEMARB_MODE:
5357                         /* We can't enable/disable these bits of the
5358                          * 5705/5750, just say success.
5359                          */
5360                         return 0;
5361
5362                 default:
5363                         break;
5364                 }
5365         }
5366
5367         val = tr32(ofs);
5368         val &= ~enable_bit;
5369         tw32_f(ofs, val);
5370
5371         for (i = 0; i < MAX_WAIT_CNT; i++) {
5372                 udelay(100);
5373                 val = tr32(ofs);
5374                 if ((val & enable_bit) == 0)
5375                         break;
5376         }
5377
5378         if (i == MAX_WAIT_CNT && !silent) {
5379                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
5380                        "ofs=%lx enable_bit=%x\n",
5381                        ofs, enable_bit);
5382                 return -ENODEV;
5383         }
5384
5385         return 0;
5386 }
5387
5388 /* tp->lock is held. */
5389 static int tg3_abort_hw(struct tg3 *tp, int silent)
5390 {
5391         int i, err;
5392
5393         tg3_disable_ints(tp);
5394
5395         tp->rx_mode &= ~RX_MODE_ENABLE;
5396         tw32_f(MAC_RX_MODE, tp->rx_mode);
5397         udelay(10);
5398
5399         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
5400         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
5401         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
5402         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
5403         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
5404         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
5405
5406         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
5407         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
5408         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
5409         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
5410         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
5411         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
5412         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
5413
5414         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
5415         tw32_f(MAC_MODE, tp->mac_mode);
5416         udelay(40);
5417
5418         tp->tx_mode &= ~TX_MODE_ENABLE;
5419         tw32_f(MAC_TX_MODE, tp->tx_mode);
5420
5421         for (i = 0; i < MAX_WAIT_CNT; i++) {
5422                 udelay(100);
5423                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
5424                         break;
5425         }
5426         if (i >= MAX_WAIT_CNT) {
5427                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
5428                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
5429                        tp->dev->name, tr32(MAC_TX_MODE));
5430                 err |= -ENODEV;
5431         }
5432
5433         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
5434         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
5435         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
5436
5437         tw32(FTQ_RESET, 0xffffffff);
5438         tw32(FTQ_RESET, 0x00000000);
5439
5440         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
5441         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
5442
5443         if (tp->hw_status)
5444                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5445         if (tp->hw_stats)
5446                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
5447
5448         return err;
5449 }
5450
5451 /* tp->lock is held. */
5452 static int tg3_nvram_lock(struct tg3 *tp)
5453 {
5454         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5455                 int i;
5456
5457                 if (tp->nvram_lock_cnt == 0) {
5458                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
5459                         for (i = 0; i < 8000; i++) {
5460                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
5461                                         break;
5462                                 udelay(20);
5463                         }
5464                         if (i == 8000) {
5465                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
5466                                 return -ENODEV;
5467                         }
5468                 }
5469                 tp->nvram_lock_cnt++;
5470         }
5471         return 0;
5472 }
5473
5474 /* tp->lock is held. */
5475 static void tg3_nvram_unlock(struct tg3 *tp)
5476 {
5477         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
5478                 if (tp->nvram_lock_cnt > 0)
5479                         tp->nvram_lock_cnt--;
5480                 if (tp->nvram_lock_cnt == 0)
5481                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
5482         }
5483 }
5484
5485 /* tp->lock is held. */
5486 static void tg3_enable_nvram_access(struct tg3 *tp)
5487 {
5488         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5489             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5490                 u32 nvaccess = tr32(NVRAM_ACCESS);
5491
5492                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
5493         }
5494 }
5495
5496 /* tp->lock is held. */
5497 static void tg3_disable_nvram_access(struct tg3 *tp)
5498 {
5499         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
5500             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
5501                 u32 nvaccess = tr32(NVRAM_ACCESS);
5502
5503                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
5504         }
5505 }
5506
5507 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
5508 {
5509         int i;
5510         u32 apedata;
5511
5512         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
5513         if (apedata != APE_SEG_SIG_MAGIC)
5514                 return;
5515
5516         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
5517         if (apedata != APE_FW_STATUS_READY)
5518                 return;
5519
5520         /* Wait for up to 1 millisecond for APE to service previous event. */
5521         for (i = 0; i < 10; i++) {
5522                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
5523                         return;
5524
5525                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
5526
5527                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5528                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
5529                                         event | APE_EVENT_STATUS_EVENT_PENDING);
5530
5531                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
5532
5533                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5534                         break;
5535
5536                 udelay(100);
5537         }
5538
5539         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
5540                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
5541 }
5542
5543 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
5544 {
5545         u32 event;
5546         u32 apedata;
5547
5548         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
5549                 return;
5550
5551         switch (kind) {
5552                 case RESET_KIND_INIT:
5553                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
5554                                         APE_HOST_SEG_SIG_MAGIC);
5555                         tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
5556                                         APE_HOST_SEG_LEN_MAGIC);
5557                         apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
5558                         tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
5559                         tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
5560                                         APE_HOST_DRIVER_ID_MAGIC);
5561                         tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
5562                                         APE_HOST_BEHAV_NO_PHYLOCK);
5563
5564                         event = APE_EVENT_STATUS_STATE_START;
5565                         break;
5566                 case RESET_KIND_SHUTDOWN:
5567                         event = APE_EVENT_STATUS_STATE_UNLOAD;
5568                         break;
5569                 case RESET_KIND_SUSPEND:
5570                         event = APE_EVENT_STATUS_STATE_SUSPEND;
5571                         break;
5572                 default:
5573                         return;
5574         }
5575
5576         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
5577
5578         tg3_ape_send_event(tp, event);
5579 }
5580
5581 /* tp->lock is held. */
5582 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
5583 {
5584         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
5585                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
5586
5587         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5588                 switch (kind) {
5589                 case RESET_KIND_INIT:
5590                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5591                                       DRV_STATE_START);
5592                         break;
5593
5594                 case RESET_KIND_SHUTDOWN:
5595                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5596                                       DRV_STATE_UNLOAD);
5597                         break;
5598
5599                 case RESET_KIND_SUSPEND:
5600                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5601                                       DRV_STATE_SUSPEND);
5602                         break;
5603
5604                 default:
5605                         break;
5606                 }
5607         }
5608
5609         if (kind == RESET_KIND_INIT ||
5610             kind == RESET_KIND_SUSPEND)
5611                 tg3_ape_driver_state_change(tp, kind);
5612 }
5613
5614 /* tp->lock is held. */
5615 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
5616 {
5617         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
5618                 switch (kind) {
5619                 case RESET_KIND_INIT:
5620                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5621                                       DRV_STATE_START_DONE);
5622                         break;
5623
5624                 case RESET_KIND_SHUTDOWN:
5625                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5626                                       DRV_STATE_UNLOAD_DONE);
5627                         break;
5628
5629                 default:
5630                         break;
5631                 }
5632         }
5633
5634         if (kind == RESET_KIND_SHUTDOWN)
5635                 tg3_ape_driver_state_change(tp, kind);
5636 }
5637
5638 /* tp->lock is held. */
5639 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
5640 {
5641         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5642                 switch (kind) {
5643                 case RESET_KIND_INIT:
5644                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5645                                       DRV_STATE_START);
5646                         break;
5647
5648                 case RESET_KIND_SHUTDOWN:
5649                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5650                                       DRV_STATE_UNLOAD);
5651                         break;
5652
5653                 case RESET_KIND_SUSPEND:
5654                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
5655                                       DRV_STATE_SUSPEND);
5656                         break;
5657
5658                 default:
5659                         break;
5660                 }
5661         }
5662 }
5663
5664 static int tg3_poll_fw(struct tg3 *tp)
5665 {
5666         int i;
5667         u32 val;
5668
5669         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5670                 /* Wait up to 20ms for init done. */
5671                 for (i = 0; i < 200; i++) {
5672                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
5673                                 return 0;
5674                         udelay(100);
5675                 }
5676                 return -ENODEV;
5677         }
5678
5679         /* Wait for firmware initialization to complete. */
5680         for (i = 0; i < 100000; i++) {
5681                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
5682                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
5683                         break;
5684                 udelay(10);
5685         }
5686
5687         /* Chip might not be fitted with firmware.  Some Sun onboard
5688          * parts are configured like that.  So don't signal the timeout
5689          * of the above loop as an error, but do report the lack of
5690          * running firmware once.
5691          */
5692         if (i >= 100000 &&
5693             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
5694                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
5695
5696                 printk(KERN_INFO PFX "%s: No firmware running.\n",
5697                        tp->dev->name);
5698         }
5699
5700         return 0;
5701 }
5702
5703 /* Save PCI command register before chip reset */
5704 static void tg3_save_pci_state(struct tg3 *tp)
5705 {
5706         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5707 }
5708
5709 /* Restore PCI state after chip reset */
5710 static void tg3_restore_pci_state(struct tg3 *tp)
5711 {
5712         u32 val;
5713
5714         /* Re-enable indirect register accesses. */
5715         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
5716                                tp->misc_host_ctrl);
5717
5718         /* Set MAX PCI retry to zero. */
5719         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
5720         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5721             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
5722                 val |= PCISTATE_RETRY_SAME_DMA;
5723         /* Allow reads and writes to the APE register and memory space. */
5724         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
5725                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
5726                        PCISTATE_ALLOW_APE_SHMEM_WR;
5727         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5728
5729         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5730
5731         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5732                 pcie_set_readrq(tp->pdev, 4096);
5733         else {
5734                 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
5735                                       tp->pci_cacheline_sz);
5736                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
5737                                       tp->pci_lat_timer);
5738         }
5739
5740         /* Make sure PCI-X relaxed ordering bit is clear. */
5741         if (tp->pcix_cap) {
5742                 u16 pcix_cmd;
5743
5744                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5745                                      &pcix_cmd);
5746                 pcix_cmd &= ~PCI_X_CMD_ERO;
5747                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
5748                                       pcix_cmd);
5749         }
5750
5751         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5752
5753                 /* Chip reset on 5780 will reset MSI enable bit,
5754                  * so need to restore it.
5755                  */
5756                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
5757                         u16 ctrl;
5758
5759                         pci_read_config_word(tp->pdev,
5760                                              tp->msi_cap + PCI_MSI_FLAGS,
5761                                              &ctrl);
5762                         pci_write_config_word(tp->pdev,
5763                                               tp->msi_cap + PCI_MSI_FLAGS,
5764                                               ctrl | PCI_MSI_FLAGS_ENABLE);
5765                         val = tr32(MSGINT_MODE);
5766                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5767                 }
5768         }
5769 }
5770
5771 static void tg3_stop_fw(struct tg3 *);
5772
5773 /* tp->lock is held. */
5774 static int tg3_chip_reset(struct tg3 *tp)
5775 {
5776         u32 val;
5777         void (*write_op)(struct tg3 *, u32, u32);
5778         int err;
5779
5780         tg3_nvram_lock(tp);
5781
5782         tg3_mdio_stop(tp);
5783
5784         /* No matching tg3_nvram_unlock() after this because
5785          * chip reset below will undo the nvram lock.
5786          */
5787         tp->nvram_lock_cnt = 0;
5788
5789         /* GRC_MISC_CFG core clock reset will clear the memory
5790          * enable bit in PCI register 4 and the MSI enable bit
5791          * on some chips, so we save relevant registers here.
5792          */
5793         tg3_save_pci_state(tp);
5794
5795         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
5796             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
5797             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
5798             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
5799             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
5800             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
5801                 tw32(GRC_FASTBOOT_PC, 0);
5802
5803         /*
5804          * We must avoid the readl() that normally takes place.
5805          * It locks machines, causes machine checks, and other
5806          * fun things.  So, temporarily disable the 5701
5807          * hardware workaround, while we do the reset.
5808          */
5809         write_op = tp->write32;
5810         if (write_op == tg3_write_flush_reg32)
5811                 tp->write32 = tg3_write32;
5812
5813         /* Prevent the irq handler from reading or writing PCI registers
5814          * during chip reset when the memory enable bit in the PCI command
5815          * register may be cleared.  The chip does not generate interrupt
5816          * at this time, but the irq handler may still be called due to irq
5817          * sharing or irqpoll.
5818          */
5819         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
5820         if (tp->hw_status) {
5821                 tp->hw_status->status = 0;
5822                 tp->hw_status->status_tag = 0;
5823         }
5824         tp->last_tag = 0;
5825         smp_mb();
5826         synchronize_irq(tp->pdev->irq);
5827
5828         /* do the reset */
5829         val = GRC_MISC_CFG_CORECLK_RESET;
5830
5831         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5832                 if (tr32(0x7e2c) == 0x60) {
5833                         tw32(0x7e2c, 0x20);
5834                 }
5835                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5836                         tw32(GRC_MISC_CFG, (1 << 29));
5837                         val |= (1 << 29);
5838                 }
5839         }
5840
5841         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5842                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
5843                 tw32(GRC_VCPU_EXT_CTRL,
5844                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
5845         }
5846
5847         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5848                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
5849         tw32(GRC_MISC_CFG, val);
5850
5851         /* restore 5701 hardware bug workaround write method */
5852         tp->write32 = write_op;
5853
5854         /* Unfortunately, we have to delay before the PCI read back.
5855          * Some 575X chips even will not respond to a PCI cfg access
5856          * when the reset command is given to the chip.
5857          *
5858          * How do these hardware designers expect things to work
5859          * properly if the PCI write is posted for a long period
5860          * of time?  It is always necessary to have some method by
5861          * which a register read back can occur to push the write
5862          * out which does the reset.
5863          *
5864          * For most tg3 variants the trick below was working.
5865          * Ho hum...
5866          */
5867         udelay(120);
5868
5869         /* Flush PCI posted writes.  The normal MMIO registers
5870          * are inaccessible at this time so this is the only
5871          * way to make this reliably (actually, this is no longer
5872          * the case, see above).  I tried to use indirect
5873          * register read/write but this upset some 5701 variants.
5874          */
5875         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
5876
5877         udelay(120);
5878
5879         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
5880                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
5881                         int i;
5882                         u32 cfg_val;
5883
5884                         /* Wait for link training to complete.  */
5885                         for (i = 0; i < 5000; i++)
5886                                 udelay(100);
5887
5888                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
5889                         pci_write_config_dword(tp->pdev, 0xc4,
5890                                                cfg_val | (1 << 15));
5891                 }
5892                 /* Set PCIE max payload size and clear error status.  */
5893                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
5894         }
5895
5896         tg3_restore_pci_state(tp);
5897
5898         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
5899
5900         val = 0;
5901         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5902                 val = tr32(MEMARB_MODE);
5903         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5904
5905         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5906                 tg3_stop_fw(tp);
5907                 tw32(0x5000, 0x400);
5908         }
5909
5910         tw32(GRC_MODE, tp->grc_mode);
5911
5912         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5913                 val = tr32(0xc4);
5914
5915                 tw32(0xc4, val | (1 << 15));
5916         }
5917
5918         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5919             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5920                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5921                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5922                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5923                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5924         }
5925
5926         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5927                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5928                 tw32_f(MAC_MODE, tp->mac_mode);
5929         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5930                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5931                 tw32_f(MAC_MODE, tp->mac_mode);
5932         } else
5933                 tw32_f(MAC_MODE, 0);
5934         udelay(40);
5935
5936         tg3_mdio_start(tp);
5937
5938         err = tg3_poll_fw(tp);
5939         if (err)
5940                 return err;
5941
5942         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5943             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5944                 val = tr32(0x7c00);
5945
5946                 tw32(0x7c00, val | (1 << 25));
5947         }
5948
5949         /* Reprobe ASF enable state.  */
5950         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5951         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5952         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5953         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5954                 u32 nic_cfg;
5955
5956                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5957                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5958                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5959                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5960                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5961                 }
5962         }
5963
5964         return 0;
5965 }
5966
5967 /* tp->lock is held. */
5968 static void tg3_stop_fw(struct tg3 *tp)
5969 {
5970         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
5971            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
5972                 u32 val;
5973
5974                 /* Wait for RX cpu to ACK the previous event. */
5975                 tg3_wait_for_event_ack(tp);
5976
5977                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5978                 val = tr32(GRC_RX_CPU_EVENT);
5979                 val |= GRC_RX_CPU_DRIVER_EVENT;
5980                 tw32(GRC_RX_CPU_EVENT, val);
5981
5982                 /* Wait for RX cpu to ACK this event. */
5983                 tg3_wait_for_event_ack(tp);
5984         }
5985 }
5986
5987 /* tp->lock is held. */
5988 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5989 {
5990         int err;
5991
5992         tg3_stop_fw(tp);
5993
5994         tg3_write_sig_pre_reset(tp, kind);
5995
5996         tg3_abort_hw(tp, silent);
5997         err = tg3_chip_reset(tp);
5998
5999         tg3_write_sig_legacy(tp, kind);
6000         tg3_write_sig_post_reset(tp, kind);
6001
6002         if (err)
6003                 return err;
6004
6005         return 0;
6006 }
6007
6008 #define TG3_FW_RELEASE_MAJOR    0x0
6009 #define TG3_FW_RELASE_MINOR     0x0
6010 #define TG3_FW_RELEASE_FIX      0x0
6011 #define TG3_FW_START_ADDR       0x08000000
6012 #define TG3_FW_TEXT_ADDR        0x08000000
6013 #define TG3_FW_TEXT_LEN         0x9c0
6014 #define TG3_FW_RODATA_ADDR      0x080009c0
6015 #define TG3_FW_RODATA_LEN       0x60
6016 #define TG3_FW_DATA_ADDR        0x08000a40
6017 #define TG3_FW_DATA_LEN         0x20
6018 #define TG3_FW_SBSS_ADDR        0x08000a60
6019 #define TG3_FW_SBSS_LEN         0xc
6020 #define TG3_FW_BSS_ADDR         0x08000a70
6021 #define TG3_FW_BSS_LEN          0x10
6022
6023 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
6024         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
6025         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
6026         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
6027         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
6028         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
6029         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
6030         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
6031         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
6032         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
6033         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
6034         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
6035         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
6036         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
6037         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
6038         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
6039         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6040         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
6041         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
6042         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
6043         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6044         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
6045         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
6046         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6047         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6048         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6049         0, 0, 0, 0, 0, 0,
6050         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
6051         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6052         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6053         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6054         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
6055         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
6056         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
6057         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
6058         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6059         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
6060         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
6061         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6062         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6063         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6064         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
6065         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
6066         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
6067         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
6068         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
6069         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
6070         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
6071         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
6072         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
6073         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
6074         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
6075         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
6076         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
6077         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
6078         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
6079         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
6080         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
6081         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
6082         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
6083         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
6084         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
6085         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
6086         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
6087         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
6088         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
6089         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
6090         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
6091         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
6092         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
6093         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
6094         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
6095         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
6096         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
6097         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
6098         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
6099         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
6100         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
6101         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
6102         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
6103         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
6104         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
6105         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
6106         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
6107         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
6108         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
6109         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
6110         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
6111         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
6112         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
6113         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
6114         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
6115 };
6116
6117 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
6118         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
6119         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
6120         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6121         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
6122         0x00000000
6123 };
6124
6125 #if 0 /* All zeros, don't eat up space with it. */
6126 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
6127         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6128         0x00000000, 0x00000000, 0x00000000, 0x00000000
6129 };
6130 #endif
6131
6132 #define RX_CPU_SCRATCH_BASE     0x30000
6133 #define RX_CPU_SCRATCH_SIZE     0x04000
6134 #define TX_CPU_SCRATCH_BASE     0x34000
6135 #define TX_CPU_SCRATCH_SIZE     0x04000
6136
6137 /* tp->lock is held. */
6138 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
6139 {
6140         int i;
6141
6142         BUG_ON(offset == TX_CPU_BASE &&
6143             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
6144
6145         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6146                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
6147
6148                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
6149                 return 0;
6150         }
6151         if (offset == RX_CPU_BASE) {
6152                 for (i = 0; i < 10000; i++) {
6153                         tw32(offset + CPU_STATE, 0xffffffff);
6154                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6155                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6156                                 break;
6157                 }
6158
6159                 tw32(offset + CPU_STATE, 0xffffffff);
6160                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
6161                 udelay(10);
6162         } else {
6163                 for (i = 0; i < 10000; i++) {
6164                         tw32(offset + CPU_STATE, 0xffffffff);
6165                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
6166                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
6167                                 break;
6168                 }
6169         }
6170
6171         if (i >= 10000) {
6172                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
6173                        "and %s CPU\n",
6174                        tp->dev->name,
6175                        (offset == RX_CPU_BASE ? "RX" : "TX"));
6176                 return -ENODEV;
6177         }
6178
6179         /* Clear firmware's nvram arbitration. */
6180         if (tp->tg3_flags & TG3_FLAG_NVRAM)
6181                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
6182         return 0;
6183 }
6184
6185 struct fw_info {
6186         unsigned int text_base;
6187         unsigned int text_len;
6188         const u32 *text_data;
6189         unsigned int rodata_base;
6190         unsigned int rodata_len;
6191         const u32 *rodata_data;
6192         unsigned int data_base;
6193         unsigned int data_len;
6194         const u32 *data_data;
6195 };
6196
6197 /* tp->lock is held. */
6198 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
6199                                  int cpu_scratch_size, struct fw_info *info)
6200 {
6201         int err, lock_err, i;
6202         void (*write_op)(struct tg3 *, u32, u32);
6203
6204         if (cpu_base == TX_CPU_BASE &&
6205             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6206                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
6207                        "TX cpu firmware on %s which is 5705.\n",
6208                        tp->dev->name);
6209                 return -EINVAL;
6210         }
6211
6212         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6213                 write_op = tg3_write_mem;
6214         else
6215                 write_op = tg3_write_indirect_reg32;
6216
6217         /* It is possible that bootcode is still loading at this point.
6218          * Get the nvram lock first before halting the cpu.
6219          */
6220         lock_err = tg3_nvram_lock(tp);
6221         err = tg3_halt_cpu(tp, cpu_base);
6222         if (!lock_err)
6223                 tg3_nvram_unlock(tp);
6224         if (err)
6225                 goto out;
6226
6227         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
6228                 write_op(tp, cpu_scratch_base + i, 0);
6229         tw32(cpu_base + CPU_STATE, 0xffffffff);
6230         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
6231         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
6232                 write_op(tp, (cpu_scratch_base +
6233                               (info->text_base & 0xffff) +
6234                               (i * sizeof(u32))),
6235                          (info->text_data ?
6236                           info->text_data[i] : 0));
6237         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
6238                 write_op(tp, (cpu_scratch_base +
6239                               (info->rodata_base & 0xffff) +
6240                               (i * sizeof(u32))),
6241                          (info->rodata_data ?
6242                           info->rodata_data[i] : 0));
6243         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
6244                 write_op(tp, (cpu_scratch_base +
6245                               (info->data_base & 0xffff) +
6246                               (i * sizeof(u32))),
6247                          (info->data_data ?
6248                           info->data_data[i] : 0));
6249
6250         err = 0;
6251
6252 out:
6253         return err;
6254 }
6255
6256 /* tp->lock is held. */
6257 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
6258 {
6259         struct fw_info info;
6260         int err, i;
6261
6262         info.text_base = TG3_FW_TEXT_ADDR;
6263         info.text_len = TG3_FW_TEXT_LEN;
6264         info.text_data = &tg3FwText[0];
6265         info.rodata_base = TG3_FW_RODATA_ADDR;
6266         info.rodata_len = TG3_FW_RODATA_LEN;
6267         info.rodata_data = &tg3FwRodata[0];
6268         info.data_base = TG3_FW_DATA_ADDR;
6269         info.data_len = TG3_FW_DATA_LEN;
6270         info.data_data = NULL;
6271
6272         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
6273                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
6274                                     &info);
6275         if (err)
6276                 return err;
6277
6278         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
6279                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
6280                                     &info);
6281         if (err)
6282                 return err;
6283
6284         /* Now startup only the RX cpu. */
6285         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6286         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
6287
6288         for (i = 0; i < 5; i++) {
6289                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
6290                         break;
6291                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6292                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
6293                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
6294                 udelay(1000);
6295         }
6296         if (i >= 5) {
6297                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
6298                        "to set RX CPU PC, is %08x should be %08x\n",
6299                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
6300                        TG3_FW_TEXT_ADDR);
6301                 return -ENODEV;
6302         }
6303         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
6304         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
6305
6306         return 0;
6307 }
6308
6309
6310 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
6311 #define TG3_TSO_FW_RELASE_MINOR         0x6
6312 #define TG3_TSO_FW_RELEASE_FIX          0x0
6313 #define TG3_TSO_FW_START_ADDR           0x08000000
6314 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
6315 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
6316 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
6317 #define TG3_TSO_FW_RODATA_LEN           0x60
6318 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
6319 #define TG3_TSO_FW_DATA_LEN             0x30
6320 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
6321 #define TG3_TSO_FW_SBSS_LEN             0x2c
6322 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
6323 #define TG3_TSO_FW_BSS_LEN              0x894
6324
6325 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
6326         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
6327         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
6328         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6329         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
6330         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
6331         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
6332         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
6333         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
6334         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
6335         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
6336         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
6337         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
6338         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
6339         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
6340         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
6341         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
6342         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
6343         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
6344         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6345         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
6346         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
6347         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
6348         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
6349         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
6350         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
6351         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
6352         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
6353         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
6354         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
6355         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6356         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
6357         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
6358         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
6359         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
6360         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
6361         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
6362         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
6363         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
6364         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
6365         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
6366         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
6367         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
6368         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
6369         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
6370         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
6371         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
6372         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
6373         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6374         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
6375         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
6376         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
6377         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
6378         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
6379         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
6380         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
6381         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
6382         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
6383         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
6384         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
6385         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
6386         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
6387         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
6388         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
6389         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
6390         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
6391         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
6392         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
6393         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
6394         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
6395         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
6396         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
6397         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
6398         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
6399         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
6400         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
6401         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
6402         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
6403         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
6404         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
6405         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
6406         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
6407         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
6408         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
6409         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
6410         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
6411         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
6412         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
6413         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
6414         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
6415         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
6416         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
6417         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
6418         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
6419         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
6420         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
6421         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
6422         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
6423         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
6424         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
6425         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
6426         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
6427         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
6428         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
6429         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
6430         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
6431         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
6432         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
6433         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
6434         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
6435         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
6436         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
6437         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
6438         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
6439         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
6440         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
6441         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
6442         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
6443         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
6444         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
6445         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
6446         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
6447         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
6448         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
6449         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
6450         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
6451         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
6452         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
6453         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
6454         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
6455         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
6456         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
6457         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
6458         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
6459         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
6460         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
6461         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
6462         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
6463         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
6464         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6465         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
6466         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
6467         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
6468         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
6469         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
6470         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
6471         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
6472         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
6473         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
6474         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
6475         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
6476         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
6477         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
6478         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
6479         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
6480         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
6481         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
6482         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
6483         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
6484         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
6485         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
6486         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
6487         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
6488         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
6489         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
6490         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
6491         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
6492         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
6493         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
6494         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
6495         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
6496         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
6497         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
6498         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
6499         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
6500         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
6501         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
6502         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
6503         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
6504         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
6505         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
6506         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
6507         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
6508         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
6509         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
6510         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
6511         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
6512         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
6513         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
6514         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
6515         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
6516         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
6517         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
6518         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
6519         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
6520         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
6521         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
6522         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
6523         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
6524         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
6525         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
6526         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
6527         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
6528         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
6529         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
6530         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
6531         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
6532         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
6533         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
6534         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
6535         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
6536         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
6537         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
6538         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
6539         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
6540         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
6541         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
6542         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
6543         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
6544         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
6545         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
6546         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6547         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
6548         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
6549         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
6550         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
6551         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
6552         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
6553         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
6554         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
6555         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
6556         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
6557         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
6558         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
6559         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
6560         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
6561         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
6562         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
6563         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
6564         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
6565         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
6566         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
6567         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
6568         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
6569         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
6570         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
6571         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
6572         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
6573         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
6574         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
6575         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
6576         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
6577         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
6578         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
6579         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
6580         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
6581         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
6582         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
6583         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
6584         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
6585         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
6586         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
6587         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
6588         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
6589         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
6590         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
6591         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
6592         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
6593         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
6594         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
6595         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
6596         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
6597         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
6598         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
6599         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
6600         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
6601         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
6602         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
6603         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
6604         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
6605         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
6606         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
6607         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
6608         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
6609         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
6610 };
6611
6612 static const u32 tg3TsoFwRodata[] = {
6613         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6614         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
6615         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
6616         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
6617         0x00000000,
6618 };
6619
6620 static const u32 tg3TsoFwData[] = {
6621         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
6622         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
6623         0x00000000,
6624 };
6625
6626 /* 5705 needs a special version of the TSO firmware.  */
6627 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
6628 #define TG3_TSO5_FW_RELASE_MINOR        0x2
6629 #define TG3_TSO5_FW_RELEASE_FIX         0x0
6630 #define TG3_TSO5_FW_START_ADDR          0x00010000
6631 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
6632 #define TG3_TSO5_FW_TEXT_LEN            0xe90
6633 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
6634 #define TG3_TSO5_FW_RODATA_LEN          0x50
6635 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
6636 #define TG3_TSO5_FW_DATA_LEN            0x20
6637 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
6638 #define TG3_TSO5_FW_SBSS_LEN            0x28
6639 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
6640 #define TG3_TSO5_FW_BSS_LEN             0x88
6641
6642 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
6643         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
6644         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
6645         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
6646         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
6647         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
6648         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
6649         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6650         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
6651         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
6652         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
6653         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
6654         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
6655         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
6656         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
6657         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
6658         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
6659         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
6660         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
6661         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
6662         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
6663         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
6664         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
6665         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
6666         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
6667         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
6668         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
6669         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
6670         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
6671         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
6672         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
6673         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6674         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
6675         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
6676         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
6677         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
6678         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
6679         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
6680         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
6681         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
6682         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
6683         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
6684         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
6685         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
6686         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
6687         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
6688         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
6689         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
6690         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
6691         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
6692         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
6693         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
6694         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
6695         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
6696         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
6697         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
6698         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
6699         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
6700         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
6701         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
6702         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
6703         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
6704         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
6705         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
6706         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
6707         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
6708         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
6709         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
6710         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
6711         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
6712         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
6713         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
6714         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
6715         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
6716         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
6717         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
6718         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
6719         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
6720         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
6721         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
6722         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
6723         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
6724         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
6725         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
6726         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
6727         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
6728         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
6729         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
6730         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
6731         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
6732         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
6733         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
6734         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
6735         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
6736         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
6737         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
6738         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
6739         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
6740         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
6741         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
6742         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
6743         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
6744         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
6745         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
6746         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
6747         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
6748         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
6749         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6750         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6751         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
6752         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
6753         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
6754         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
6755         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
6756         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
6757         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
6758         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
6759         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
6760         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
6761         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
6762         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
6763         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
6764         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
6765         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
6766         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
6767         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
6768         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
6769         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
6770         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
6771         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
6772         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
6773         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
6774         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
6775         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
6776         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
6777         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
6778         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
6779         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
6780         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
6781         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
6782         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
6783         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
6784         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
6785         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
6786         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
6787         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
6788         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
6789         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
6790         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
6791         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
6792         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
6793         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
6794         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
6795         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
6796         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
6797         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
6798         0x00000000, 0x00000000, 0x00000000,
6799 };
6800
6801 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
6802         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
6803         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
6804         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
6805         0x00000000, 0x00000000, 0x00000000,
6806 };
6807
6808 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
6809         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
6810         0x00000000, 0x00000000, 0x00000000,
6811 };
6812
6813 /* tp->lock is held. */
6814 static int tg3_load_tso_firmware(struct tg3 *tp)
6815 {
6816         struct fw_info info;
6817         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
6818         int err, i;
6819
6820         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6821                 return 0;
6822
6823         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6824                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
6825                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
6826                 info.text_data = &tg3Tso5FwText[0];
6827                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
6828                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
6829                 info.rodata_data = &tg3Tso5FwRodata[0];
6830                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
6831                 info.data_len = TG3_TSO5_FW_DATA_LEN;
6832                 info.data_data = &tg3Tso5FwData[0];
6833                 cpu_base = RX_CPU_BASE;
6834                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
6835                 cpu_scratch_size = (info.text_len +
6836                                     info.rodata_len +
6837                                     info.data_len +
6838                                     TG3_TSO5_FW_SBSS_LEN +
6839                                     TG3_TSO5_FW_BSS_LEN);
6840         } else {
6841                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
6842                 info.text_len = TG3_TSO_FW_TEXT_LEN;
6843                 info.text_data = &tg3TsoFwText[0];
6844                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
6845                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
6846                 info.rodata_data = &tg3TsoFwRodata[0];
6847                 info.data_base = TG3_TSO_FW_DATA_ADDR;
6848                 info.data_len = TG3_TSO_FW_DATA_LEN;
6849                 info.data_data = &tg3TsoFwData[0];
6850                 cpu_base = TX_CPU_BASE;
6851                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
6852                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
6853         }
6854
6855         err = tg3_load_firmware_cpu(tp, cpu_base,
6856                                     cpu_scratch_base, cpu_scratch_size,
6857                                     &info);
6858         if (err)
6859                 return err;
6860
6861         /* Now startup the cpu. */
6862         tw32(cpu_base + CPU_STATE, 0xffffffff);
6863         tw32_f(cpu_base + CPU_PC,    info.text_base);
6864
6865         for (i = 0; i < 5; i++) {
6866                 if (tr32(cpu_base + CPU_PC) == info.text_base)
6867                         break;
6868                 tw32(cpu_base + CPU_STATE, 0xffffffff);
6869                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
6870                 tw32_f(cpu_base + CPU_PC,    info.text_base);
6871                 udelay(1000);
6872         }
6873         if (i >= 5) {
6874                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
6875                        "to set CPU PC, is %08x should be %08x\n",
6876                        tp->dev->name, tr32(cpu_base + CPU_PC),
6877                        info.text_base);
6878                 return -ENODEV;
6879         }
6880         tw32(cpu_base + CPU_STATE, 0xffffffff);
6881         tw32_f(cpu_base + CPU_MODE,  0x00000000);
6882         return 0;
6883 }
6884
6885
6886 /* tp->lock is held. */
6887 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
6888 {
6889         u32 addr_high, addr_low;
6890         int i;
6891
6892         addr_high = ((tp->dev->dev_addr[0] << 8) |
6893                      tp->dev->dev_addr[1]);
6894         addr_low = ((tp->dev->dev_addr[2] << 24) |
6895                     (tp->dev->dev_addr[3] << 16) |
6896                     (tp->dev->dev_addr[4] <<  8) |
6897                     (tp->dev->dev_addr[5] <<  0));
6898         for (i = 0; i < 4; i++) {
6899                 if (i == 1 && skip_mac_1)
6900                         continue;
6901                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6902                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6903         }
6904
6905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6906             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6907                 for (i = 0; i < 12; i++) {
6908                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6909                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6910                 }
6911         }
6912
6913         addr_high = (tp->dev->dev_addr[0] +
6914                      tp->dev->dev_addr[1] +
6915                      tp->dev->dev_addr[2] +
6916                      tp->dev->dev_addr[3] +
6917                      tp->dev->dev_addr[4] +
6918                      tp->dev->dev_addr[5]) &
6919                 TX_BACKOFF_SEED_MASK;
6920         tw32(MAC_TX_BACKOFF_SEED, addr_high);
6921 }
6922
6923 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6924 {
6925         struct tg3 *tp = netdev_priv(dev);
6926         struct sockaddr *addr = p;
6927         int err = 0, skip_mac_1 = 0;
6928
6929         if (!is_valid_ether_addr(addr->sa_data))
6930                 return -EINVAL;
6931
6932         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6933
6934         if (!netif_running(dev))
6935                 return 0;
6936
6937         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6938                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6939
6940                 addr0_high = tr32(MAC_ADDR_0_HIGH);
6941                 addr0_low = tr32(MAC_ADDR_0_LOW);
6942                 addr1_high = tr32(MAC_ADDR_1_HIGH);
6943                 addr1_low = tr32(MAC_ADDR_1_LOW);
6944
6945                 /* Skip MAC addr 1 if ASF is using it. */
6946                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6947                     !(addr1_high == 0 && addr1_low == 0))
6948                         skip_mac_1 = 1;
6949         }
6950         spin_lock_bh(&tp->lock);
6951         __tg3_set_mac_addr(tp, skip_mac_1);
6952         spin_unlock_bh(&tp->lock);
6953
6954         return err;
6955 }
6956
6957 /* tp->lock is held. */
6958 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6959                            dma_addr_t mapping, u32 maxlen_flags,
6960                            u32 nic_addr)
6961 {
6962         tg3_write_mem(tp,
6963                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6964                       ((u64) mapping >> 32));
6965         tg3_write_mem(tp,
6966                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6967                       ((u64) mapping & 0xffffffff));
6968         tg3_write_mem(tp,
6969                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6970                        maxlen_flags);
6971
6972         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6973                 tg3_write_mem(tp,
6974                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6975                               nic_addr);
6976 }
6977
6978 static void __tg3_set_rx_mode(struct net_device *);
6979 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6980 {
6981         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6982         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6983         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6984         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6985         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6986                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6987                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6988         }
6989         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6990         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6991         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6992                 u32 val = ec->stats_block_coalesce_usecs;
6993
6994                 if (!netif_carrier_ok(tp->dev))
6995                         val = 0;
6996
6997                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6998         }
6999 }
7000
7001 /* tp->lock is held. */
7002 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7003 {
7004         u32 val, rdmac_mode;
7005         int i, err, limit;
7006
7007         tg3_disable_ints(tp);
7008
7009         tg3_stop_fw(tp);
7010
7011         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7012
7013         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7014                 tg3_abort_hw(tp, 1);
7015         }
7016
7017         if (reset_phy &&
7018             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7019                 tg3_phy_reset(tp);
7020
7021         err = tg3_chip_reset(tp);
7022         if (err)
7023                 return err;
7024
7025         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7026
7027         if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
7028             tp->pci_chip_rev_id == CHIPREV_ID_5784_A1) {
7029                 val = tr32(TG3_CPMU_CTRL);
7030                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7031                 tw32(TG3_CPMU_CTRL, val);
7032
7033                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7034                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7035                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7036                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7037
7038                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7039                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7040                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7041                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7042
7043                 val = tr32(TG3_CPMU_HST_ACC);
7044                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7045                 val |= CPMU_HST_ACC_MACCLK_6_25;
7046                 tw32(TG3_CPMU_HST_ACC, val);
7047         }
7048
7049         /* This works around an issue with Athlon chipsets on
7050          * B3 tigon3 silicon.  This bit has no effect on any
7051          * other revision.  But do not set this on PCI Express
7052          * chips and don't even touch the clocks if the CPMU is present.
7053          */
7054         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7055                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7056                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7057                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7058         }
7059
7060         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7061             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7062                 val = tr32(TG3PCI_PCISTATE);
7063                 val |= PCISTATE_RETRY_SAME_DMA;
7064                 tw32(TG3PCI_PCISTATE, val);
7065         }
7066
7067         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7068                 /* Allow reads and writes to the
7069                  * APE register and memory space.
7070                  */
7071                 val = tr32(TG3PCI_PCISTATE);
7072                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7073                        PCISTATE_ALLOW_APE_SHMEM_WR;
7074                 tw32(TG3PCI_PCISTATE, val);
7075         }
7076
7077         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7078                 /* Enable some hw fixes.  */
7079                 val = tr32(TG3PCI_MSI_DATA);
7080                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7081                 tw32(TG3PCI_MSI_DATA, val);
7082         }
7083
7084         /* Descriptor ring init may make accesses to the
7085          * NIC SRAM area to setup the TX descriptors, so we
7086          * can only do this after the hardware has been
7087          * successfully reset.
7088          */
7089         err = tg3_init_rings(tp);
7090         if (err)
7091                 return err;
7092
7093         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7094             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
7095             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
7096                 /* This value is determined during the probe time DMA
7097                  * engine test, tg3_test_dma.
7098                  */
7099                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7100         }
7101
7102         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7103                           GRC_MODE_4X_NIC_SEND_RINGS |
7104                           GRC_MODE_NO_TX_PHDR_CSUM |
7105                           GRC_MODE_NO_RX_PHDR_CSUM);
7106         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7107
7108         /* Pseudo-header checksum is done by hardware logic and not
7109          * the offload processers, so make the chip do the pseudo-
7110          * header checksums on receive.  For transmit it is more
7111          * convenient to do the pseudo-header checksum in software
7112          * as Linux does that on transmit for us in all cases.
7113          */
7114         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7115
7116         tw32(GRC_MODE,
7117              tp->grc_mode |
7118              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7119
7120         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7121         val = tr32(GRC_MISC_CFG);
7122         val &= ~0xff;
7123         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7124         tw32(GRC_MISC_CFG, val);
7125
7126         /* Initialize MBUF/DESC pool. */
7127         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7128                 /* Do nothing.  */
7129         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7130                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7131                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7132                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7133                 else
7134                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7135                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7136                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7137         }
7138         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7139                 int fw_len;
7140
7141                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
7142                           TG3_TSO5_FW_RODATA_LEN +
7143                           TG3_TSO5_FW_DATA_LEN +
7144                           TG3_TSO5_FW_SBSS_LEN +
7145                           TG3_TSO5_FW_BSS_LEN);
7146                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7147                 tw32(BUFMGR_MB_POOL_ADDR,
7148                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7149                 tw32(BUFMGR_MB_POOL_SIZE,
7150                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7151         }
7152
7153         if (tp->dev->mtu <= ETH_DATA_LEN) {
7154                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7155                      tp->bufmgr_config.mbuf_read_dma_low_water);
7156                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7157                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7158                 tw32(BUFMGR_MB_HIGH_WATER,
7159                      tp->bufmgr_config.mbuf_high_water);
7160         } else {
7161                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7162                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7163                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7164                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7165                 tw32(BUFMGR_MB_HIGH_WATER,
7166                      tp->bufmgr_config.mbuf_high_water_jumbo);
7167         }
7168         tw32(BUFMGR_DMA_LOW_WATER,
7169              tp->bufmgr_config.dma_low_water);
7170         tw32(BUFMGR_DMA_HIGH_WATER,
7171              tp->bufmgr_config.dma_high_water);
7172
7173         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7174         for (i = 0; i < 2000; i++) {
7175                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7176                         break;
7177                 udelay(10);
7178         }
7179         if (i >= 2000) {
7180                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7181                        tp->dev->name);
7182                 return -ENODEV;
7183         }
7184
7185         /* Setup replenish threshold. */
7186         val = tp->rx_pending / 8;
7187         if (val == 0)
7188                 val = 1;
7189         else if (val > tp->rx_std_max_post)
7190                 val = tp->rx_std_max_post;
7191         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7192                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7193                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7194
7195                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7196                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7197         }
7198
7199         tw32(RCVBDI_STD_THRESH, val);
7200
7201         /* Initialize TG3_BDINFO's at:
7202          *  RCVDBDI_STD_BD:     standard eth size rx ring
7203          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7204          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7205          *
7206          * like so:
7207          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7208          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7209          *                              ring attribute flags
7210          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7211          *
7212          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7213          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7214          *
7215          * The size of each ring is fixed in the firmware, but the location is
7216          * configurable.
7217          */
7218         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7219              ((u64) tp->rx_std_mapping >> 32));
7220         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7221              ((u64) tp->rx_std_mapping & 0xffffffff));
7222         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7223              NIC_SRAM_RX_BUFFER_DESC);
7224
7225         /* Don't even try to program the JUMBO/MINI buffer descriptor
7226          * configs on 5705.
7227          */
7228         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
7229                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7230                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
7231         } else {
7232                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
7233                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7234
7235                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7236                      BDINFO_FLAGS_DISABLED);
7237
7238                 /* Setup replenish threshold. */
7239                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7240
7241                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7242                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7243                              ((u64) tp->rx_jumbo_mapping >> 32));
7244                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7245                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
7246                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7247                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
7248                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7249                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7250                 } else {
7251                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7252                              BDINFO_FLAGS_DISABLED);
7253                 }
7254
7255         }
7256
7257         /* There is only one send ring on 5705/5750, no need to explicitly
7258          * disable the others.
7259          */
7260         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7261                 /* Clear out send RCB ring in SRAM. */
7262                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
7263                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7264                                       BDINFO_FLAGS_DISABLED);
7265         }
7266
7267         tp->tx_prod = 0;
7268         tp->tx_cons = 0;
7269         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7270         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
7271
7272         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
7273                        tp->tx_desc_mapping,
7274                        (TG3_TX_RING_SIZE <<
7275                         BDINFO_FLAGS_MAXLEN_SHIFT),
7276                        NIC_SRAM_TX_BUFFER_DESC);
7277
7278         /* There is only one receive return ring on 5705/5750, no need
7279          * to explicitly disable the others.
7280          */
7281         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7282                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
7283                      i += TG3_BDINFO_SIZE) {
7284                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
7285                                       BDINFO_FLAGS_DISABLED);
7286                 }
7287         }
7288
7289         tp->rx_rcb_ptr = 0;
7290         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
7291
7292         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
7293                        tp->rx_rcb_mapping,
7294                        (TG3_RX_RCB_RING_SIZE(tp) <<
7295                         BDINFO_FLAGS_MAXLEN_SHIFT),
7296                        0);
7297
7298         tp->rx_std_ptr = tp->rx_pending;
7299         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7300                      tp->rx_std_ptr);
7301
7302         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7303                                                 tp->rx_jumbo_pending : 0;
7304         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7305                      tp->rx_jumbo_ptr);
7306
7307         /* Initialize MAC address and backoff seed. */
7308         __tg3_set_mac_addr(tp, 0);
7309
7310         /* MTU + ethernet header + FCS + optional VLAN tag */
7311         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
7312
7313         /* The slot time is changed by tg3_setup_phy if we
7314          * run at gigabit with half duplex.
7315          */
7316         tw32(MAC_TX_LENGTHS,
7317              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7318              (6 << TX_LENGTHS_IPG_SHIFT) |
7319              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7320
7321         /* Receive rules. */
7322         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7323         tw32(RCVLPC_CONFIG, 0x0181);
7324
7325         /* Calculate RDMAC_MODE setting early, we need it to determine
7326          * the RCVLPC_STATE_ENABLE mask.
7327          */
7328         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7329                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7330                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7331                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7332                       RDMAC_MODE_LNGREAD_ENAB);
7333
7334         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7335             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7336                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7337                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7338                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7339
7340         /* If statement applies to 5705 and 5750 PCI devices only */
7341         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7342              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7343             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7344                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7345                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7346                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7347                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7348                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7349                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7350                 }
7351         }
7352
7353         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7354                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7355
7356         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7357                 rdmac_mode |= (1 << 27);
7358
7359         /* Receive/send statistics. */
7360         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7361                 val = tr32(RCVLPC_STATS_ENABLE);
7362                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7363                 tw32(RCVLPC_STATS_ENABLE, val);
7364         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7365                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7366                 val = tr32(RCVLPC_STATS_ENABLE);
7367                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7368                 tw32(RCVLPC_STATS_ENABLE, val);
7369         } else {
7370                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7371         }
7372         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7373         tw32(SNDDATAI_STATSENAB, 0xffffff);
7374         tw32(SNDDATAI_STATSCTRL,
7375              (SNDDATAI_SCTRL_ENABLE |
7376               SNDDATAI_SCTRL_FASTUPD));
7377
7378         /* Setup host coalescing engine. */
7379         tw32(HOSTCC_MODE, 0);
7380         for (i = 0; i < 2000; i++) {
7381                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7382                         break;
7383                 udelay(10);
7384         }
7385
7386         __tg3_set_coalesce(tp, &tp->coal);
7387
7388         /* set status block DMA address */
7389         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7390              ((u64) tp->status_mapping >> 32));
7391         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7392              ((u64) tp->status_mapping & 0xffffffff));
7393
7394         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7395                 /* Status/statistics block address.  See tg3_timer,
7396                  * the tg3_periodic_fetch_stats call there, and
7397                  * tg3_get_stats to see how this works for 5705/5750 chips.
7398                  */
7399                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7400                      ((u64) tp->stats_mapping >> 32));
7401                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7402                      ((u64) tp->stats_mapping & 0xffffffff));
7403                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7404                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7405         }
7406
7407         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7408
7409         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7410         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7411         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7412                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7413
7414         /* Clear statistics/status block in chip, and status block in ram. */
7415         for (i = NIC_SRAM_STATS_BLK;
7416              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7417              i += sizeof(u32)) {
7418                 tg3_write_mem(tp, i, 0);
7419                 udelay(40);
7420         }
7421         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
7422
7423         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7424                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7425                 /* reset to prevent losing 1st rx packet intermittently */
7426                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7427                 udelay(10);
7428         }
7429
7430         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7431                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7432         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7433             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7434             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7435                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7436         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7437         udelay(40);
7438
7439         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7440          * If TG3_FLG2_IS_NIC is zero, we should read the
7441          * register to preserve the GPIO settings for LOMs. The GPIOs,
7442          * whether used as inputs or outputs, are set by boot code after
7443          * reset.
7444          */
7445         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7446                 u32 gpio_mask;
7447
7448                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7449                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7450                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7451
7452                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7453                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7454                                      GRC_LCLCTRL_GPIO_OUTPUT3;
7455
7456                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7457                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7458
7459                 tp->grc_local_ctrl &= ~gpio_mask;
7460                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7461
7462                 /* GPIO1 must be driven high for eeprom write protect */
7463                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7464                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7465                                                GRC_LCLCTRL_GPIO_OUTPUT1);
7466         }
7467         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7468         udelay(100);
7469
7470         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
7471         tp->last_tag = 0;
7472
7473         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7474                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
7475                 udelay(40);
7476         }
7477
7478         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
7479                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
7480                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
7481                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
7482                WDMAC_MODE_LNGREAD_ENAB);
7483
7484         /* If statement applies to 5705 and 5750 PCI devices only */
7485         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7486              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
7488                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
7489                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
7490                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
7491                         /* nothing */
7492                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7493                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7494                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
7495                         val |= WDMAC_MODE_RX_ACCEL;
7496                 }
7497         }
7498
7499         /* Enable host coalescing bug fix */
7500         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
7501             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) ||
7502             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) ||
7503             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) ||
7504             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785))
7505                 val |= WDMAC_MODE_STATUS_TAG_FIX;
7506
7507         tw32_f(WDMAC_MODE, val);
7508         udelay(40);
7509
7510         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7511                 u16 pcix_cmd;
7512
7513                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7514                                      &pcix_cmd);
7515                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
7516                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
7517                         pcix_cmd |= PCI_X_CMD_READ_2K;
7518                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
7519                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
7520                         pcix_cmd |= PCI_X_CMD_READ_2K;
7521                 }
7522                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7523                                       pcix_cmd);
7524         }
7525
7526         tw32_f(RDMAC_MODE, rdmac_mode);
7527         udelay(40);
7528
7529         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
7530         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7531                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
7532
7533         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
7534                 tw32(SNDDATAC_MODE,
7535                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
7536         else
7537                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
7538
7539         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
7540         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
7541         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
7542         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
7543         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7544                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
7545         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
7546         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
7547
7548         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
7549                 err = tg3_load_5701_a0_firmware_fix(tp);
7550                 if (err)
7551                         return err;
7552         }
7553
7554         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7555                 err = tg3_load_tso_firmware(tp);
7556                 if (err)
7557                         return err;
7558         }
7559
7560         tp->tx_mode = TX_MODE_ENABLE;
7561         tw32_f(MAC_TX_MODE, tp->tx_mode);
7562         udelay(100);
7563
7564         tp->rx_mode = RX_MODE_ENABLE;
7565         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7566             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7567             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
7568             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
7569                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
7570
7571         tw32_f(MAC_RX_MODE, tp->rx_mode);
7572         udelay(10);
7573
7574         tw32(MAC_LED_CTRL, tp->led_ctrl);
7575
7576         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
7577         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7578                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7579                 udelay(10);
7580         }
7581         tw32_f(MAC_RX_MODE, tp->rx_mode);
7582         udelay(10);
7583
7584         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7585                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
7586                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
7587                         /* Set drive transmission level to 1.2V  */
7588                         /* only if the signal pre-emphasis bit is not set  */
7589                         val = tr32(MAC_SERDES_CFG);
7590                         val &= 0xfffff000;
7591                         val |= 0x880;
7592                         tw32(MAC_SERDES_CFG, val);
7593                 }
7594                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
7595                         tw32(MAC_SERDES_CFG, 0x616000);
7596         }
7597
7598         /* Prevent chip from dropping frames when flow control
7599          * is enabled.
7600          */
7601         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
7602
7603         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
7604             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
7605                 /* Use hardware link auto-negotiation */
7606                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
7607         }
7608
7609         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
7610             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
7611                 u32 tmp;
7612
7613                 tmp = tr32(SERDES_RX_CTRL);
7614                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
7615                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
7616                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
7617                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7618         }
7619
7620         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
7621                 if (tp->link_config.phy_is_low_power) {
7622                         tp->link_config.phy_is_low_power = 0;
7623                         tp->link_config.speed = tp->link_config.orig_speed;
7624                         tp->link_config.duplex = tp->link_config.orig_duplex;
7625                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
7626                 }
7627
7628                 err = tg3_setup_phy(tp, 0);
7629                 if (err)
7630                         return err;
7631
7632                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7633                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
7634                         u32 tmp;
7635
7636                         /* Clear CRC stats. */
7637                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
7638                                 tg3_writephy(tp, MII_TG3_TEST1,
7639                                              tmp | MII_TG3_TEST1_CRC_EN);
7640                                 tg3_readphy(tp, 0x14, &tmp);
7641                         }
7642                 }
7643         }
7644
7645         __tg3_set_rx_mode(tp->dev);
7646
7647         /* Initialize receive rules. */
7648         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
7649         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
7650         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
7651         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
7652
7653         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7654             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
7655                 limit = 8;
7656         else
7657                 limit = 16;
7658         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
7659                 limit -= 4;
7660         switch (limit) {
7661         case 16:
7662                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
7663         case 15:
7664                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
7665         case 14:
7666                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
7667         case 13:
7668                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
7669         case 12:
7670                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
7671         case 11:
7672                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
7673         case 10:
7674                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
7675         case 9:
7676                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
7677         case 8:
7678                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
7679         case 7:
7680                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
7681         case 6:
7682                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
7683         case 5:
7684                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
7685         case 4:
7686                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
7687         case 3:
7688                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
7689         case 2:
7690         case 1:
7691
7692         default:
7693                 break;
7694         }
7695
7696         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7697                 /* Write our heartbeat update interval to APE. */
7698                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
7699                                 APE_HOST_HEARTBEAT_INT_DISABLE);
7700
7701         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
7702
7703         return 0;
7704 }
7705
7706 /* Called at device open time to get the chip ready for
7707  * packet processing.  Invoked with tp->lock held.
7708  */
7709 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
7710 {
7711         int err;
7712
7713         /* Force the chip into D0. */
7714         err = tg3_set_power_state(tp, PCI_D0);
7715         if (err)
7716                 goto out;
7717
7718         tg3_switch_clocks(tp);
7719
7720         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
7721
7722         err = tg3_reset_hw(tp, reset_phy);
7723
7724 out:
7725         return err;
7726 }
7727
7728 #define TG3_STAT_ADD32(PSTAT, REG) \
7729 do {    u32 __val = tr32(REG); \
7730         (PSTAT)->low += __val; \
7731         if ((PSTAT)->low < __val) \
7732                 (PSTAT)->high += 1; \
7733 } while (0)
7734
7735 static void tg3_periodic_fetch_stats(struct tg3 *tp)
7736 {
7737         struct tg3_hw_stats *sp = tp->hw_stats;
7738
7739         if (!netif_carrier_ok(tp->dev))
7740                 return;
7741
7742         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
7743         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
7744         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
7745         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
7746         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
7747         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
7748         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
7749         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
7750         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
7751         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
7752         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
7753         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
7754         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
7755
7756         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
7757         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
7758         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
7759         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
7760         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
7761         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
7762         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
7763         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
7764         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
7765         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
7766         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
7767         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
7768         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
7769         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
7770
7771         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
7772         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
7773         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
7774 }
7775
7776 static void tg3_timer(unsigned long __opaque)
7777 {
7778         struct tg3 *tp = (struct tg3 *) __opaque;
7779
7780         if (tp->irq_sync)
7781                 goto restart_timer;
7782
7783         spin_lock(&tp->lock);
7784
7785         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7786                 /* All of this garbage is because when using non-tagged
7787                  * IRQ status the mailbox/status_block protocol the chip
7788                  * uses with the cpu is race prone.
7789                  */
7790                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
7791                         tw32(GRC_LOCAL_CTRL,
7792                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
7793                 } else {
7794                         tw32(HOSTCC_MODE, tp->coalesce_mode |
7795                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
7796                 }
7797
7798                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
7799                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
7800                         spin_unlock(&tp->lock);
7801                         schedule_work(&tp->reset_task);
7802                         return;
7803                 }
7804         }
7805
7806         /* This part only runs once per second. */
7807         if (!--tp->timer_counter) {
7808                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7809                         tg3_periodic_fetch_stats(tp);
7810
7811                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
7812                         u32 mac_stat;
7813                         int phy_event;
7814
7815                         mac_stat = tr32(MAC_STATUS);
7816
7817                         phy_event = 0;
7818                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
7819                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
7820                                         phy_event = 1;
7821                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
7822                                 phy_event = 1;
7823
7824                         if (phy_event)
7825                                 tg3_setup_phy(tp, 0);
7826                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
7827                         u32 mac_stat = tr32(MAC_STATUS);
7828                         int need_setup = 0;
7829
7830                         if (netif_carrier_ok(tp->dev) &&
7831                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
7832                                 need_setup = 1;
7833                         }
7834                         if (! netif_carrier_ok(tp->dev) &&
7835                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
7836                                          MAC_STATUS_SIGNAL_DET))) {
7837                                 need_setup = 1;
7838                         }
7839                         if (need_setup) {
7840                                 if (!tp->serdes_counter) {
7841                                         tw32_f(MAC_MODE,
7842                                              (tp->mac_mode &
7843                                               ~MAC_MODE_PORT_MODE_MASK));
7844                                         udelay(40);
7845                                         tw32_f(MAC_MODE, tp->mac_mode);
7846                                         udelay(40);
7847                                 }
7848                                 tg3_setup_phy(tp, 0);
7849                         }
7850                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
7851                         tg3_serdes_parallel_detect(tp);
7852
7853                 tp->timer_counter = tp->timer_multiplier;
7854         }
7855
7856         /* Heartbeat is only sent once every 2 seconds.
7857          *
7858          * The heartbeat is to tell the ASF firmware that the host
7859          * driver is still alive.  In the event that the OS crashes,
7860          * ASF needs to reset the hardware to free up the FIFO space
7861          * that may be filled with rx packets destined for the host.
7862          * If the FIFO is full, ASF will no longer function properly.
7863          *
7864          * Unintended resets have been reported on real time kernels
7865          * where the timer doesn't run on time.  Netpoll will also have
7866          * same problem.
7867          *
7868          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
7869          * to check the ring condition when the heartbeat is expiring
7870          * before doing the reset.  This will prevent most unintended
7871          * resets.
7872          */
7873         if (!--tp->asf_counter) {
7874                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7875                         u32 val;
7876
7877                         tg3_wait_for_event_ack(tp);
7878
7879                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
7880                                       FWCMD_NICDRV_ALIVE3);
7881                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
7882                         /* 5 seconds timeout */
7883                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
7884                         val = tr32(GRC_RX_CPU_EVENT);
7885                         val |= GRC_RX_CPU_DRIVER_EVENT;
7886                         tw32_f(GRC_RX_CPU_EVENT, val);
7887                 }
7888                 tp->asf_counter = tp->asf_multiplier;
7889         }
7890
7891         spin_unlock(&tp->lock);
7892
7893 restart_timer:
7894         tp->timer.expires = jiffies + tp->timer_offset;
7895         add_timer(&tp->timer);
7896 }
7897
7898 static int tg3_request_irq(struct tg3 *tp)
7899 {
7900         irq_handler_t fn;
7901         unsigned long flags;
7902         struct net_device *dev = tp->dev;
7903
7904         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7905                 fn = tg3_msi;
7906                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
7907                         fn = tg3_msi_1shot;
7908                 flags = IRQF_SAMPLE_RANDOM;
7909         } else {
7910                 fn = tg3_interrupt;
7911                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7912                         fn = tg3_interrupt_tagged;
7913                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
7914         }
7915         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
7916 }
7917
7918 static int tg3_test_interrupt(struct tg3 *tp)
7919 {
7920         struct net_device *dev = tp->dev;
7921         int err, i, intr_ok = 0;
7922
7923         if (!netif_running(dev))
7924                 return -ENODEV;
7925
7926         tg3_disable_ints(tp);
7927
7928         free_irq(tp->pdev->irq, dev);
7929
7930         err = request_irq(tp->pdev->irq, tg3_test_isr,
7931                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
7932         if (err)
7933                 return err;
7934
7935         tp->hw_status->status &= ~SD_STATUS_UPDATED;
7936         tg3_enable_ints(tp);
7937
7938         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
7939                HOSTCC_MODE_NOW);
7940
7941         for (i = 0; i < 5; i++) {
7942                 u32 int_mbox, misc_host_ctrl;
7943
7944                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
7945                                         TG3_64BIT_REG_LOW);
7946                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
7947
7948                 if ((int_mbox != 0) ||
7949                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
7950                         intr_ok = 1;
7951                         break;
7952                 }
7953
7954                 msleep(10);
7955         }
7956
7957         tg3_disable_ints(tp);
7958
7959         free_irq(tp->pdev->irq, dev);
7960
7961         err = tg3_request_irq(tp);
7962
7963         if (err)
7964                 return err;
7965
7966         if (intr_ok)
7967                 return 0;
7968
7969         return -EIO;
7970 }
7971
7972 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7973  * successfully restored
7974  */
7975 static int tg3_test_msi(struct tg3 *tp)
7976 {
7977         struct net_device *dev = tp->dev;
7978         int err;
7979         u16 pci_cmd;
7980
7981         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7982                 return 0;
7983
7984         /* Turn off SERR reporting in case MSI terminates with Master
7985          * Abort.
7986          */
7987         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7988         pci_write_config_word(tp->pdev, PCI_COMMAND,
7989                               pci_cmd & ~PCI_COMMAND_SERR);
7990
7991         err = tg3_test_interrupt(tp);
7992
7993         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7994
7995         if (!err)
7996                 return 0;
7997
7998         /* other failures */
7999         if (err != -EIO)
8000                 return err;
8001
8002         /* MSI test failed, go back to INTx mode */
8003         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8004                "switching to INTx mode. Please report this failure to "
8005                "the PCI maintainer and include system chipset information.\n",
8006                        tp->dev->name);
8007
8008         free_irq(tp->pdev->irq, dev);
8009         pci_disable_msi(tp->pdev);
8010
8011         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8012
8013         err = tg3_request_irq(tp);
8014         if (err)
8015                 return err;
8016
8017         /* Need to reset the chip because the MSI cycle may have terminated
8018          * with Master Abort.
8019          */
8020         tg3_full_lock(tp, 1);
8021
8022         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8023         err = tg3_init_hw(tp, 1);
8024
8025         tg3_full_unlock(tp);
8026
8027         if (err)
8028                 free_irq(tp->pdev->irq, dev);
8029
8030         return err;
8031 }
8032
8033 static int tg3_open(struct net_device *dev)
8034 {
8035         struct tg3 *tp = netdev_priv(dev);
8036         int err;
8037
8038         netif_carrier_off(tp->dev);
8039
8040         tg3_full_lock(tp, 0);
8041
8042         err = tg3_set_power_state(tp, PCI_D0);
8043         if (err) {
8044                 tg3_full_unlock(tp);
8045                 return err;
8046         }
8047
8048         tg3_disable_ints(tp);
8049         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8050
8051         tg3_full_unlock(tp);
8052
8053         /* The placement of this call is tied
8054          * to the setup and use of Host TX descriptors.
8055          */
8056         err = tg3_alloc_consistent(tp);
8057         if (err)
8058                 return err;
8059
8060         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
8061                 /* All MSI supporting chips should support tagged
8062                  * status.  Assert that this is the case.
8063                  */
8064                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8065                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8066                                "Not using MSI.\n", tp->dev->name);
8067                 } else if (pci_enable_msi(tp->pdev) == 0) {
8068                         u32 msi_mode;
8069
8070                         msi_mode = tr32(MSGINT_MODE);
8071                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8072                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8073                 }
8074         }
8075         err = tg3_request_irq(tp);
8076
8077         if (err) {
8078                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8079                         pci_disable_msi(tp->pdev);
8080                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8081                 }
8082                 tg3_free_consistent(tp);
8083                 return err;
8084         }
8085
8086         napi_enable(&tp->napi);
8087
8088         tg3_full_lock(tp, 0);
8089
8090         err = tg3_init_hw(tp, 1);
8091         if (err) {
8092                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8093                 tg3_free_rings(tp);
8094         } else {
8095                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8096                         tp->timer_offset = HZ;
8097                 else
8098                         tp->timer_offset = HZ / 10;
8099
8100                 BUG_ON(tp->timer_offset > HZ);
8101                 tp->timer_counter = tp->timer_multiplier =
8102                         (HZ / tp->timer_offset);
8103                 tp->asf_counter = tp->asf_multiplier =
8104                         ((HZ / tp->timer_offset) * 2);
8105
8106                 init_timer(&tp->timer);
8107                 tp->timer.expires = jiffies + tp->timer_offset;
8108                 tp->timer.data = (unsigned long) tp;
8109                 tp->timer.function = tg3_timer;
8110         }
8111
8112         tg3_full_unlock(tp);
8113
8114         if (err) {
8115                 napi_disable(&tp->napi);
8116                 free_irq(tp->pdev->irq, dev);
8117                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8118                         pci_disable_msi(tp->pdev);
8119                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8120                 }
8121                 tg3_free_consistent(tp);
8122                 return err;
8123         }
8124
8125         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8126                 err = tg3_test_msi(tp);
8127
8128                 if (err) {
8129                         tg3_full_lock(tp, 0);
8130
8131                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8132                                 pci_disable_msi(tp->pdev);
8133                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8134                         }
8135                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8136                         tg3_free_rings(tp);
8137                         tg3_free_consistent(tp);
8138
8139                         tg3_full_unlock(tp);
8140
8141                         napi_disable(&tp->napi);
8142
8143                         return err;
8144                 }
8145
8146                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8147                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
8148                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
8149
8150                                 tw32(PCIE_TRANSACTION_CFG,
8151                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
8152                         }
8153                 }
8154         }
8155
8156         tg3_phy_start(tp);
8157
8158         tg3_full_lock(tp, 0);
8159
8160         add_timer(&tp->timer);
8161         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8162         tg3_enable_ints(tp);
8163
8164         tg3_full_unlock(tp);
8165
8166         netif_start_queue(dev);
8167
8168         return 0;
8169 }
8170
8171 #if 0
8172 /*static*/ void tg3_dump_state(struct tg3 *tp)
8173 {
8174         u32 val32, val32_2, val32_3, val32_4, val32_5;
8175         u16 val16;
8176         int i;
8177
8178         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8179         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8180         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8181                val16, val32);
8182
8183         /* MAC block */
8184         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8185                tr32(MAC_MODE), tr32(MAC_STATUS));
8186         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8187                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8188         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8189                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8190         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8191                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8192
8193         /* Send data initiator control block */
8194         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8195                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8196         printk("       SNDDATAI_STATSCTRL[%08x]\n",
8197                tr32(SNDDATAI_STATSCTRL));
8198
8199         /* Send data completion control block */
8200         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8201
8202         /* Send BD ring selector block */
8203         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8204                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8205
8206         /* Send BD initiator control block */
8207         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8208                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8209
8210         /* Send BD completion control block */
8211         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8212
8213         /* Receive list placement control block */
8214         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8215                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8216         printk("       RCVLPC_STATSCTRL[%08x]\n",
8217                tr32(RCVLPC_STATSCTRL));
8218
8219         /* Receive data and receive BD initiator control block */
8220         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8221                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8222
8223         /* Receive data completion control block */
8224         printk("DEBUG: RCVDCC_MODE[%08x]\n",
8225                tr32(RCVDCC_MODE));
8226
8227         /* Receive BD initiator control block */
8228         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8229                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8230
8231         /* Receive BD completion control block */
8232         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8233                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8234
8235         /* Receive list selector control block */
8236         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8237                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8238
8239         /* Mbuf cluster free block */
8240         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8241                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8242
8243         /* Host coalescing control block */
8244         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8245                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8246         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8247                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8248                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8249         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8250                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8251                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8252         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8253                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8254         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8255                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8256
8257         /* Memory arbiter control block */
8258         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8259                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8260
8261         /* Buffer manager control block */
8262         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8263                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8264         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8265                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8266         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8267                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8268                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8269                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8270
8271         /* Read DMA control block */
8272         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8273                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8274
8275         /* Write DMA control block */
8276         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8277                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8278
8279         /* DMA completion block */
8280         printk("DEBUG: DMAC_MODE[%08x]\n",
8281                tr32(DMAC_MODE));
8282
8283         /* GRC block */
8284         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8285                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8286         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8287                tr32(GRC_LOCAL_CTRL));
8288
8289         /* TG3_BDINFOs */
8290         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
8291                tr32(RCVDBDI_JUMBO_BD + 0x0),
8292                tr32(RCVDBDI_JUMBO_BD + 0x4),
8293                tr32(RCVDBDI_JUMBO_BD + 0x8),
8294                tr32(RCVDBDI_JUMBO_BD + 0xc));
8295         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
8296                tr32(RCVDBDI_STD_BD + 0x0),
8297                tr32(RCVDBDI_STD_BD + 0x4),
8298                tr32(RCVDBDI_STD_BD + 0x8),
8299                tr32(RCVDBDI_STD_BD + 0xc));
8300         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
8301                tr32(RCVDBDI_MINI_BD + 0x0),
8302                tr32(RCVDBDI_MINI_BD + 0x4),
8303                tr32(RCVDBDI_MINI_BD + 0x8),
8304                tr32(RCVDBDI_MINI_BD + 0xc));
8305
8306         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
8307         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
8308         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
8309         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
8310         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
8311                val32, val32_2, val32_3, val32_4);
8312
8313         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
8314         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
8315         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
8316         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
8317         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
8318                val32, val32_2, val32_3, val32_4);
8319
8320         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
8321         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
8322         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
8323         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
8324         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
8325         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
8326                val32, val32_2, val32_3, val32_4, val32_5);
8327
8328         /* SW status block */
8329         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
8330                tp->hw_status->status,
8331                tp->hw_status->status_tag,
8332                tp->hw_status->rx_jumbo_consumer,
8333                tp->hw_status->rx_consumer,
8334                tp->hw_status->rx_mini_consumer,
8335                tp->hw_status->idx[0].rx_producer,
8336                tp->hw_status->idx[0].tx_consumer);
8337
8338         /* SW statistics block */
8339         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
8340                ((u32 *)tp->hw_stats)[0],
8341                ((u32 *)tp->hw_stats)[1],
8342                ((u32 *)tp->hw_stats)[2],
8343                ((u32 *)tp->hw_stats)[3]);
8344
8345         /* Mailboxes */
8346         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
8347                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
8348                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
8349                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
8350                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
8351
8352         /* NIC side send descriptors. */
8353         for (i = 0; i < 6; i++) {
8354                 unsigned long txd;
8355
8356                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
8357                         + (i * sizeof(struct tg3_tx_buffer_desc));
8358                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
8359                        i,
8360                        readl(txd + 0x0), readl(txd + 0x4),
8361                        readl(txd + 0x8), readl(txd + 0xc));
8362         }
8363
8364         /* NIC side RX descriptors. */
8365         for (i = 0; i < 6; i++) {
8366                 unsigned long rxd;
8367
8368                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
8369                         + (i * sizeof(struct tg3_rx_buffer_desc));
8370                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
8371                        i,
8372                        readl(rxd + 0x0), readl(rxd + 0x4),
8373                        readl(rxd + 0x8), readl(rxd + 0xc));
8374                 rxd += (4 * sizeof(u32));
8375                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
8376                        i,
8377                        readl(rxd + 0x0), readl(rxd + 0x4),
8378                        readl(rxd + 0x8), readl(rxd + 0xc));
8379         }
8380
8381         for (i = 0; i < 6; i++) {
8382                 unsigned long rxd;
8383
8384                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
8385                         + (i * sizeof(struct tg3_rx_buffer_desc));
8386                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
8387                        i,
8388                        readl(rxd + 0x0), readl(rxd + 0x4),
8389                        readl(rxd + 0x8), readl(rxd + 0xc));
8390                 rxd += (4 * sizeof(u32));
8391                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
8392                        i,
8393                        readl(rxd + 0x0), readl(rxd + 0x4),
8394                        readl(rxd + 0x8), readl(rxd + 0xc));
8395         }
8396 }
8397 #endif
8398
8399 static struct net_device_stats *tg3_get_stats(struct net_device *);
8400 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
8401
8402 static int tg3_close(struct net_device *dev)
8403 {
8404         struct tg3 *tp = netdev_priv(dev);
8405
8406         napi_disable(&tp->napi);
8407         cancel_work_sync(&tp->reset_task);
8408
8409         netif_stop_queue(dev);
8410
8411         del_timer_sync(&tp->timer);
8412
8413         tg3_full_lock(tp, 1);
8414 #if 0
8415         tg3_dump_state(tp);
8416 #endif
8417
8418         tg3_disable_ints(tp);
8419
8420         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8421         tg3_free_rings(tp);
8422         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8423
8424         tg3_full_unlock(tp);
8425
8426         free_irq(tp->pdev->irq, dev);
8427         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8428                 pci_disable_msi(tp->pdev);
8429                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8430         }
8431
8432         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
8433                sizeof(tp->net_stats_prev));
8434         memcpy(&tp->estats_prev, tg3_get_estats(tp),
8435                sizeof(tp->estats_prev));
8436
8437         tg3_free_consistent(tp);
8438
8439         tg3_set_power_state(tp, PCI_D3hot);
8440
8441         netif_carrier_off(tp->dev);
8442
8443         return 0;
8444 }
8445
8446 static inline unsigned long get_stat64(tg3_stat64_t *val)
8447 {
8448         unsigned long ret;
8449
8450 #if (BITS_PER_LONG == 32)
8451         ret = val->low;
8452 #else
8453         ret = ((u64)val->high << 32) | ((u64)val->low);
8454 #endif
8455         return ret;
8456 }
8457
8458 static unsigned long calc_crc_errors(struct tg3 *tp)
8459 {
8460         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8461
8462         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8463             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
8464              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
8465                 u32 val;
8466
8467                 spin_lock_bh(&tp->lock);
8468                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
8469                         tg3_writephy(tp, MII_TG3_TEST1,
8470                                      val | MII_TG3_TEST1_CRC_EN);
8471                         tg3_readphy(tp, 0x14, &val);
8472                 } else
8473                         val = 0;
8474                 spin_unlock_bh(&tp->lock);
8475
8476                 tp->phy_crc_errors += val;
8477
8478                 return tp->phy_crc_errors;
8479         }
8480
8481         return get_stat64(&hw_stats->rx_fcs_errors);
8482 }
8483
8484 #define ESTAT_ADD(member) \
8485         estats->member =        old_estats->member + \
8486                                 get_stat64(&hw_stats->member)
8487
8488 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
8489 {
8490         struct tg3_ethtool_stats *estats = &tp->estats;
8491         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
8492         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8493
8494         if (!hw_stats)
8495                 return old_estats;
8496
8497         ESTAT_ADD(rx_octets);
8498         ESTAT_ADD(rx_fragments);
8499         ESTAT_ADD(rx_ucast_packets);
8500         ESTAT_ADD(rx_mcast_packets);
8501         ESTAT_ADD(rx_bcast_packets);
8502         ESTAT_ADD(rx_fcs_errors);
8503         ESTAT_ADD(rx_align_errors);
8504         ESTAT_ADD(rx_xon_pause_rcvd);
8505         ESTAT_ADD(rx_xoff_pause_rcvd);
8506         ESTAT_ADD(rx_mac_ctrl_rcvd);
8507         ESTAT_ADD(rx_xoff_entered);
8508         ESTAT_ADD(rx_frame_too_long_errors);
8509         ESTAT_ADD(rx_jabbers);
8510         ESTAT_ADD(rx_undersize_packets);
8511         ESTAT_ADD(rx_in_length_errors);
8512         ESTAT_ADD(rx_out_length_errors);
8513         ESTAT_ADD(rx_64_or_less_octet_packets);
8514         ESTAT_ADD(rx_65_to_127_octet_packets);
8515         ESTAT_ADD(rx_128_to_255_octet_packets);
8516         ESTAT_ADD(rx_256_to_511_octet_packets);
8517         ESTAT_ADD(rx_512_to_1023_octet_packets);
8518         ESTAT_ADD(rx_1024_to_1522_octet_packets);
8519         ESTAT_ADD(rx_1523_to_2047_octet_packets);
8520         ESTAT_ADD(rx_2048_to_4095_octet_packets);
8521         ESTAT_ADD(rx_4096_to_8191_octet_packets);
8522         ESTAT_ADD(rx_8192_to_9022_octet_packets);
8523
8524         ESTAT_ADD(tx_octets);
8525         ESTAT_ADD(tx_collisions);
8526         ESTAT_ADD(tx_xon_sent);
8527         ESTAT_ADD(tx_xoff_sent);
8528         ESTAT_ADD(tx_flow_control);
8529         ESTAT_ADD(tx_mac_errors);
8530         ESTAT_ADD(tx_single_collisions);
8531         ESTAT_ADD(tx_mult_collisions);
8532         ESTAT_ADD(tx_deferred);
8533         ESTAT_ADD(tx_excessive_collisions);
8534         ESTAT_ADD(tx_late_collisions);
8535         ESTAT_ADD(tx_collide_2times);
8536         ESTAT_ADD(tx_collide_3times);
8537         ESTAT_ADD(tx_collide_4times);
8538         ESTAT_ADD(tx_collide_5times);
8539         ESTAT_ADD(tx_collide_6times);
8540         ESTAT_ADD(tx_collide_7times);
8541         ESTAT_ADD(tx_collide_8times);
8542         ESTAT_ADD(tx_collide_9times);
8543         ESTAT_ADD(tx_collide_10times);
8544         ESTAT_ADD(tx_collide_11times);
8545         ESTAT_ADD(tx_collide_12times);
8546         ESTAT_ADD(tx_collide_13times);
8547         ESTAT_ADD(tx_collide_14times);
8548         ESTAT_ADD(tx_collide_15times);
8549         ESTAT_ADD(tx_ucast_packets);
8550         ESTAT_ADD(tx_mcast_packets);
8551         ESTAT_ADD(tx_bcast_packets);
8552         ESTAT_ADD(tx_carrier_sense_errors);
8553         ESTAT_ADD(tx_discards);
8554         ESTAT_ADD(tx_errors);
8555
8556         ESTAT_ADD(dma_writeq_full);
8557         ESTAT_ADD(dma_write_prioq_full);
8558         ESTAT_ADD(rxbds_empty);
8559         ESTAT_ADD(rx_discards);
8560         ESTAT_ADD(rx_errors);
8561         ESTAT_ADD(rx_threshold_hit);
8562
8563         ESTAT_ADD(dma_readq_full);
8564         ESTAT_ADD(dma_read_prioq_full);
8565         ESTAT_ADD(tx_comp_queue_full);
8566
8567         ESTAT_ADD(ring_set_send_prod_index);
8568         ESTAT_ADD(ring_status_update);
8569         ESTAT_ADD(nic_irqs);
8570         ESTAT_ADD(nic_avoided_irqs);
8571         ESTAT_ADD(nic_tx_threshold_hit);
8572
8573         return estats;
8574 }
8575
8576 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
8577 {
8578         struct tg3 *tp = netdev_priv(dev);
8579         struct net_device_stats *stats = &tp->net_stats;
8580         struct net_device_stats *old_stats = &tp->net_stats_prev;
8581         struct tg3_hw_stats *hw_stats = tp->hw_stats;
8582
8583         if (!hw_stats)
8584                 return old_stats;
8585
8586         stats->rx_packets = old_stats->rx_packets +
8587                 get_stat64(&hw_stats->rx_ucast_packets) +
8588                 get_stat64(&hw_stats->rx_mcast_packets) +
8589                 get_stat64(&hw_stats->rx_bcast_packets);
8590
8591         stats->tx_packets = old_stats->tx_packets +
8592                 get_stat64(&hw_stats->tx_ucast_packets) +
8593                 get_stat64(&hw_stats->tx_mcast_packets) +
8594                 get_stat64(&hw_stats->tx_bcast_packets);
8595
8596         stats->rx_bytes = old_stats->rx_bytes +
8597                 get_stat64(&hw_stats->rx_octets);
8598         stats->tx_bytes = old_stats->tx_bytes +
8599                 get_stat64(&hw_stats->tx_octets);
8600
8601         stats->rx_errors = old_stats->rx_errors +
8602                 get_stat64(&hw_stats->rx_errors);
8603         stats->tx_errors = old_stats->tx_errors +
8604                 get_stat64(&hw_stats->tx_errors) +
8605                 get_stat64(&hw_stats->tx_mac_errors) +
8606                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
8607                 get_stat64(&hw_stats->tx_discards);
8608
8609         stats->multicast = old_stats->multicast +
8610                 get_stat64(&hw_stats->rx_mcast_packets);
8611         stats->collisions = old_stats->collisions +
8612                 get_stat64(&hw_stats->tx_collisions);
8613
8614         stats->rx_length_errors = old_stats->rx_length_errors +
8615                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
8616                 get_stat64(&hw_stats->rx_undersize_packets);
8617
8618         stats->rx_over_errors = old_stats->rx_over_errors +
8619                 get_stat64(&hw_stats->rxbds_empty);
8620         stats->rx_frame_errors = old_stats->rx_frame_errors +
8621                 get_stat64(&hw_stats->rx_align_errors);
8622         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
8623                 get_stat64(&hw_stats->tx_discards);
8624         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
8625                 get_stat64(&hw_stats->tx_carrier_sense_errors);
8626
8627         stats->rx_crc_errors = old_stats->rx_crc_errors +
8628                 calc_crc_errors(tp);
8629
8630         stats->rx_missed_errors = old_stats->rx_missed_errors +
8631                 get_stat64(&hw_stats->rx_discards);
8632
8633         return stats;
8634 }
8635
8636 static inline u32 calc_crc(unsigned char *buf, int len)
8637 {
8638         u32 reg;
8639         u32 tmp;
8640         int j, k;
8641
8642         reg = 0xffffffff;
8643
8644         for (j = 0; j < len; j++) {
8645                 reg ^= buf[j];
8646
8647                 for (k = 0; k < 8; k++) {
8648                         tmp = reg & 0x01;
8649
8650                         reg >>= 1;
8651
8652                         if (tmp) {
8653                                 reg ^= 0xedb88320;
8654                         }
8655                 }
8656         }
8657
8658         return ~reg;
8659 }
8660
8661 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
8662 {
8663         /* accept or reject all multicast frames */
8664         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
8665         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
8666         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
8667         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
8668 }
8669
8670 static void __tg3_set_rx_mode(struct net_device *dev)
8671 {
8672         struct tg3 *tp = netdev_priv(dev);
8673         u32 rx_mode;
8674
8675         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
8676                                   RX_MODE_KEEP_VLAN_TAG);
8677
8678         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
8679          * flag clear.
8680          */
8681 #if TG3_VLAN_TAG_USED
8682         if (!tp->vlgrp &&
8683             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8684                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8685 #else
8686         /* By definition, VLAN is disabled always in this
8687          * case.
8688          */
8689         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
8690                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
8691 #endif
8692
8693         if (dev->flags & IFF_PROMISC) {
8694                 /* Promiscuous mode. */
8695                 rx_mode |= RX_MODE_PROMISC;
8696         } else if (dev->flags & IFF_ALLMULTI) {
8697                 /* Accept all multicast. */
8698                 tg3_set_multi (tp, 1);
8699         } else if (dev->mc_count < 1) {
8700                 /* Reject all multicast. */
8701                 tg3_set_multi (tp, 0);
8702         } else {
8703                 /* Accept one or more multicast(s). */
8704                 struct dev_mc_list *mclist;
8705                 unsigned int i;
8706                 u32 mc_filter[4] = { 0, };
8707                 u32 regidx;
8708                 u32 bit;
8709                 u32 crc;
8710
8711                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
8712                      i++, mclist = mclist->next) {
8713
8714                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
8715                         bit = ~crc & 0x7f;
8716                         regidx = (bit & 0x60) >> 5;
8717                         bit &= 0x1f;
8718                         mc_filter[regidx] |= (1 << bit);
8719                 }
8720
8721                 tw32(MAC_HASH_REG_0, mc_filter[0]);
8722                 tw32(MAC_HASH_REG_1, mc_filter[1]);
8723                 tw32(MAC_HASH_REG_2, mc_filter[2]);
8724                 tw32(MAC_HASH_REG_3, mc_filter[3]);
8725         }
8726
8727         if (rx_mode != tp->rx_mode) {
8728                 tp->rx_mode = rx_mode;
8729                 tw32_f(MAC_RX_MODE, rx_mode);
8730                 udelay(10);
8731         }
8732 }
8733
8734 static void tg3_set_rx_mode(struct net_device *dev)
8735 {
8736         struct tg3 *tp = netdev_priv(dev);
8737
8738         if (!netif_running(dev))
8739                 return;
8740
8741         tg3_full_lock(tp, 0);
8742         __tg3_set_rx_mode(dev);
8743         tg3_full_unlock(tp);
8744 }
8745
8746 #define TG3_REGDUMP_LEN         (32 * 1024)
8747
8748 static int tg3_get_regs_len(struct net_device *dev)
8749 {
8750         return TG3_REGDUMP_LEN;
8751 }
8752
8753 static void tg3_get_regs(struct net_device *dev,
8754                 struct ethtool_regs *regs, void *_p)
8755 {
8756         u32 *p = _p;
8757         struct tg3 *tp = netdev_priv(dev);
8758         u8 *orig_p = _p;
8759         int i;
8760
8761         regs->version = 0;
8762
8763         memset(p, 0, TG3_REGDUMP_LEN);
8764
8765         if (tp->link_config.phy_is_low_power)
8766                 return;
8767
8768         tg3_full_lock(tp, 0);
8769
8770 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
8771 #define GET_REG32_LOOP(base,len)                \
8772 do {    p = (u32 *)(orig_p + (base));           \
8773         for (i = 0; i < len; i += 4)            \
8774                 __GET_REG32((base) + i);        \
8775 } while (0)
8776 #define GET_REG32_1(reg)                        \
8777 do {    p = (u32 *)(orig_p + (reg));            \
8778         __GET_REG32((reg));                     \
8779 } while (0)
8780
8781         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
8782         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
8783         GET_REG32_LOOP(MAC_MODE, 0x4f0);
8784         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
8785         GET_REG32_1(SNDDATAC_MODE);
8786         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
8787         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
8788         GET_REG32_1(SNDBDC_MODE);
8789         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
8790         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
8791         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
8792         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
8793         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
8794         GET_REG32_1(RCVDCC_MODE);
8795         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
8796         GET_REG32_LOOP(RCVCC_MODE, 0x14);
8797         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
8798         GET_REG32_1(MBFREE_MODE);
8799         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
8800         GET_REG32_LOOP(MEMARB_MODE, 0x10);
8801         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
8802         GET_REG32_LOOP(RDMAC_MODE, 0x08);
8803         GET_REG32_LOOP(WDMAC_MODE, 0x08);
8804         GET_REG32_1(RX_CPU_MODE);
8805         GET_REG32_1(RX_CPU_STATE);
8806         GET_REG32_1(RX_CPU_PGMCTR);
8807         GET_REG32_1(RX_CPU_HWBKPT);
8808         GET_REG32_1(TX_CPU_MODE);
8809         GET_REG32_1(TX_CPU_STATE);
8810         GET_REG32_1(TX_CPU_PGMCTR);
8811         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
8812         GET_REG32_LOOP(FTQ_RESET, 0x120);
8813         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
8814         GET_REG32_1(DMAC_MODE);
8815         GET_REG32_LOOP(GRC_MODE, 0x4c);
8816         if (tp->tg3_flags & TG3_FLAG_NVRAM)
8817                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
8818
8819 #undef __GET_REG32
8820 #undef GET_REG32_LOOP
8821 #undef GET_REG32_1
8822
8823         tg3_full_unlock(tp);
8824 }
8825
8826 static int tg3_get_eeprom_len(struct net_device *dev)
8827 {
8828         struct tg3 *tp = netdev_priv(dev);
8829
8830         return tp->nvram_size;
8831 }
8832
8833 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
8834 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val);
8835 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
8836
8837 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8838 {
8839         struct tg3 *tp = netdev_priv(dev);
8840         int ret;
8841         u8  *pd;
8842         u32 i, offset, len, b_offset, b_count;
8843         __le32 val;
8844
8845         if (tp->link_config.phy_is_low_power)
8846                 return -EAGAIN;
8847
8848         offset = eeprom->offset;
8849         len = eeprom->len;
8850         eeprom->len = 0;
8851
8852         eeprom->magic = TG3_EEPROM_MAGIC;
8853
8854         if (offset & 3) {
8855                 /* adjustments to start on required 4 byte boundary */
8856                 b_offset = offset & 3;
8857                 b_count = 4 - b_offset;
8858                 if (b_count > len) {
8859                         /* i.e. offset=1 len=2 */
8860                         b_count = len;
8861                 }
8862                 ret = tg3_nvram_read_le(tp, offset-b_offset, &val);
8863                 if (ret)
8864                         return ret;
8865                 memcpy(data, ((char*)&val) + b_offset, b_count);
8866                 len -= b_count;
8867                 offset += b_count;
8868                 eeprom->len += b_count;
8869         }
8870
8871         /* read bytes upto the last 4 byte boundary */
8872         pd = &data[eeprom->len];
8873         for (i = 0; i < (len - (len & 3)); i += 4) {
8874                 ret = tg3_nvram_read_le(tp, offset + i, &val);
8875                 if (ret) {
8876                         eeprom->len += i;
8877                         return ret;
8878                 }
8879                 memcpy(pd + i, &val, 4);
8880         }
8881         eeprom->len += i;
8882
8883         if (len & 3) {
8884                 /* read last bytes not ending on 4 byte boundary */
8885                 pd = &data[eeprom->len];
8886                 b_count = len & 3;
8887                 b_offset = offset + len - b_count;
8888                 ret = tg3_nvram_read_le(tp, b_offset, &val);
8889                 if (ret)
8890                         return ret;
8891                 memcpy(pd, &val, b_count);
8892                 eeprom->len += b_count;
8893         }
8894         return 0;
8895 }
8896
8897 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
8898
8899 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
8900 {
8901         struct tg3 *tp = netdev_priv(dev);
8902         int ret;
8903         u32 offset, len, b_offset, odd_len;
8904         u8 *buf;
8905         __le32 start, end;
8906
8907         if (tp->link_config.phy_is_low_power)
8908                 return -EAGAIN;
8909
8910         if (eeprom->magic != TG3_EEPROM_MAGIC)
8911                 return -EINVAL;
8912
8913         offset = eeprom->offset;
8914         len = eeprom->len;
8915
8916         if ((b_offset = (offset & 3))) {
8917                 /* adjustments to start on required 4 byte boundary */
8918                 ret = tg3_nvram_read_le(tp, offset-b_offset, &start);
8919                 if (ret)
8920                         return ret;
8921                 len += b_offset;
8922                 offset &= ~3;
8923                 if (len < 4)
8924                         len = 4;
8925         }
8926
8927         odd_len = 0;
8928         if (len & 3) {
8929                 /* adjustments to end on required 4 byte boundary */
8930                 odd_len = 1;
8931                 len = (len + 3) & ~3;
8932                 ret = tg3_nvram_read_le(tp, offset+len-4, &end);
8933                 if (ret)
8934                         return ret;
8935         }
8936
8937         buf = data;
8938         if (b_offset || odd_len) {
8939                 buf = kmalloc(len, GFP_KERNEL);
8940                 if (!buf)
8941                         return -ENOMEM;
8942                 if (b_offset)
8943                         memcpy(buf, &start, 4);
8944                 if (odd_len)
8945                         memcpy(buf+len-4, &end, 4);
8946                 memcpy(buf + b_offset, data, eeprom->len);
8947         }
8948
8949         ret = tg3_nvram_write_block(tp, offset, len, buf);
8950
8951         if (buf != data)
8952                 kfree(buf);
8953
8954         return ret;
8955 }
8956
8957 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8958 {
8959         struct tg3 *tp = netdev_priv(dev);
8960
8961         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
8962                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
8963                         return -EAGAIN;
8964                 return phy_ethtool_gset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
8965         }
8966
8967         cmd->supported = (SUPPORTED_Autoneg);
8968
8969         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
8970                 cmd->supported |= (SUPPORTED_1000baseT_Half |
8971                                    SUPPORTED_1000baseT_Full);
8972
8973         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
8974                 cmd->supported |= (SUPPORTED_100baseT_Half |
8975                                   SUPPORTED_100baseT_Full |
8976                                   SUPPORTED_10baseT_Half |
8977                                   SUPPORTED_10baseT_Full |
8978                                   SUPPORTED_TP);
8979                 cmd->port = PORT_TP;
8980         } else {
8981                 cmd->supported |= SUPPORTED_FIBRE;
8982                 cmd->port = PORT_FIBRE;
8983         }
8984
8985         cmd->advertising = tp->link_config.advertising;
8986         if (netif_running(dev)) {
8987                 cmd->speed = tp->link_config.active_speed;
8988                 cmd->duplex = tp->link_config.active_duplex;
8989         }
8990         cmd->phy_address = PHY_ADDR;
8991         cmd->transceiver = 0;
8992         cmd->autoneg = tp->link_config.autoneg;
8993         cmd->maxtxpkt = 0;
8994         cmd->maxrxpkt = 0;
8995         return 0;
8996 }
8997
8998 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8999 {
9000         struct tg3 *tp = netdev_priv(dev);
9001
9002         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9003                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9004                         return -EAGAIN;
9005                 return phy_ethtool_sset(tp->mdio_bus.phy_map[PHY_ADDR], cmd);
9006         }
9007
9008         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9009                 /* These are the only valid advertisement bits allowed.  */
9010                 if (cmd->autoneg == AUTONEG_ENABLE &&
9011                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
9012                                           ADVERTISED_1000baseT_Full |
9013                                           ADVERTISED_Autoneg |
9014                                           ADVERTISED_FIBRE)))
9015                         return -EINVAL;
9016                 /* Fiber can only do SPEED_1000.  */
9017                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9018                          (cmd->speed != SPEED_1000))
9019                         return -EINVAL;
9020         /* Copper cannot force SPEED_1000.  */
9021         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
9022                    (cmd->speed == SPEED_1000))
9023                 return -EINVAL;
9024         else if ((cmd->speed == SPEED_1000) &&
9025                  (tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9026                 return -EINVAL;
9027
9028         tg3_full_lock(tp, 0);
9029
9030         tp->link_config.autoneg = cmd->autoneg;
9031         if (cmd->autoneg == AUTONEG_ENABLE) {
9032                 tp->link_config.advertising = (cmd->advertising |
9033                                               ADVERTISED_Autoneg);
9034                 tp->link_config.speed = SPEED_INVALID;
9035                 tp->link_config.duplex = DUPLEX_INVALID;
9036         } else {
9037                 tp->link_config.advertising = 0;
9038                 tp->link_config.speed = cmd->speed;
9039                 tp->link_config.duplex = cmd->duplex;
9040         }
9041
9042         tp->link_config.orig_speed = tp->link_config.speed;
9043         tp->link_config.orig_duplex = tp->link_config.duplex;
9044         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9045
9046         if (netif_running(dev))
9047                 tg3_setup_phy(tp, 1);
9048
9049         tg3_full_unlock(tp);
9050
9051         return 0;
9052 }
9053
9054 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9055 {
9056         struct tg3 *tp = netdev_priv(dev);
9057
9058         strcpy(info->driver, DRV_MODULE_NAME);
9059         strcpy(info->version, DRV_MODULE_VERSION);
9060         strcpy(info->fw_version, tp->fw_ver);
9061         strcpy(info->bus_info, pci_name(tp->pdev));
9062 }
9063
9064 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9065 {
9066         struct tg3 *tp = netdev_priv(dev);
9067
9068         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
9069                 wol->supported = WAKE_MAGIC;
9070         else
9071                 wol->supported = 0;
9072         wol->wolopts = 0;
9073         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
9074                 wol->wolopts = WAKE_MAGIC;
9075         memset(&wol->sopass, 0, sizeof(wol->sopass));
9076 }
9077
9078 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9079 {
9080         struct tg3 *tp = netdev_priv(dev);
9081
9082         if (wol->wolopts & ~WAKE_MAGIC)
9083                 return -EINVAL;
9084         if ((wol->wolopts & WAKE_MAGIC) &&
9085             !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
9086                 return -EINVAL;
9087
9088         spin_lock_bh(&tp->lock);
9089         if (wol->wolopts & WAKE_MAGIC)
9090                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9091         else
9092                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9093         spin_unlock_bh(&tp->lock);
9094
9095         return 0;
9096 }
9097
9098 static u32 tg3_get_msglevel(struct net_device *dev)
9099 {
9100         struct tg3 *tp = netdev_priv(dev);
9101         return tp->msg_enable;
9102 }
9103
9104 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9105 {
9106         struct tg3 *tp = netdev_priv(dev);
9107         tp->msg_enable = value;
9108 }
9109
9110 static int tg3_set_tso(struct net_device *dev, u32 value)
9111 {
9112         struct tg3 *tp = netdev_priv(dev);
9113
9114         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9115                 if (value)
9116                         return -EINVAL;
9117                 return 0;
9118         }
9119         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
9120             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
9121                 if (value) {
9122                         dev->features |= NETIF_F_TSO6;
9123                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9124                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9125                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9126                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9127                                 dev->features |= NETIF_F_TSO_ECN;
9128                 } else
9129                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9130         }
9131         return ethtool_op_set_tso(dev, value);
9132 }
9133
9134 static int tg3_nway_reset(struct net_device *dev)
9135 {
9136         struct tg3 *tp = netdev_priv(dev);
9137         int r;
9138
9139         if (!netif_running(dev))
9140                 return -EAGAIN;
9141
9142         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9143                 return -EINVAL;
9144
9145         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9146                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9147                         return -EAGAIN;
9148                 r = phy_start_aneg(tp->mdio_bus.phy_map[PHY_ADDR]);
9149         } else {
9150                 u32 bmcr;
9151
9152                 spin_lock_bh(&tp->lock);
9153                 r = -EINVAL;
9154                 tg3_readphy(tp, MII_BMCR, &bmcr);
9155                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9156                     ((bmcr & BMCR_ANENABLE) ||
9157                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9158                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9159                                                    BMCR_ANENABLE);
9160                         r = 0;
9161                 }
9162                 spin_unlock_bh(&tp->lock);
9163         }
9164
9165         return r;
9166 }
9167
9168 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9169 {
9170         struct tg3 *tp = netdev_priv(dev);
9171
9172         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9173         ering->rx_mini_max_pending = 0;
9174         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9175                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9176         else
9177                 ering->rx_jumbo_max_pending = 0;
9178
9179         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9180
9181         ering->rx_pending = tp->rx_pending;
9182         ering->rx_mini_pending = 0;
9183         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9184                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9185         else
9186                 ering->rx_jumbo_pending = 0;
9187
9188         ering->tx_pending = tp->tx_pending;
9189 }
9190
9191 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9192 {
9193         struct tg3 *tp = netdev_priv(dev);
9194         int irq_sync = 0, err = 0;
9195
9196         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9197             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9198             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9199             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9200             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9201              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9202                 return -EINVAL;
9203
9204         if (netif_running(dev)) {
9205                 tg3_phy_stop(tp);
9206                 tg3_netif_stop(tp);
9207                 irq_sync = 1;
9208         }
9209
9210         tg3_full_lock(tp, irq_sync);
9211
9212         tp->rx_pending = ering->rx_pending;
9213
9214         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9215             tp->rx_pending > 63)
9216                 tp->rx_pending = 63;
9217         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9218         tp->tx_pending = ering->tx_pending;
9219
9220         if (netif_running(dev)) {
9221                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9222                 err = tg3_restart_hw(tp, 1);
9223                 if (!err)
9224                         tg3_netif_start(tp);
9225         }
9226
9227         tg3_full_unlock(tp);
9228
9229         if (irq_sync && !err)
9230                 tg3_phy_start(tp);
9231
9232         return err;
9233 }
9234
9235 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9236 {
9237         struct tg3 *tp = netdev_priv(dev);
9238
9239         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9240
9241         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_RX)
9242                 epause->rx_pause = 1;
9243         else
9244                 epause->rx_pause = 0;
9245
9246         if (tp->link_config.active_flowctrl & TG3_FLOW_CTRL_TX)
9247                 epause->tx_pause = 1;
9248         else
9249                 epause->tx_pause = 0;
9250 }
9251
9252 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9253 {
9254         struct tg3 *tp = netdev_priv(dev);
9255         int err = 0;
9256
9257         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9258                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9259                         return -EAGAIN;
9260
9261                 if (epause->autoneg) {
9262                         u32 newadv;
9263                         struct phy_device *phydev;
9264
9265                         phydev = tp->mdio_bus.phy_map[PHY_ADDR];
9266
9267                         if (epause->rx_pause) {
9268                                 if (epause->tx_pause)
9269                                         newadv = ADVERTISED_Pause;
9270                                 else
9271                                         newadv = ADVERTISED_Pause |
9272                                                  ADVERTISED_Asym_Pause;
9273                         } else if (epause->tx_pause) {
9274                                 newadv = ADVERTISED_Asym_Pause;
9275                         } else
9276                                 newadv = 0;
9277
9278                         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9279                                 u32 oldadv = phydev->advertising &
9280                                              (ADVERTISED_Pause |
9281                                               ADVERTISED_Asym_Pause);
9282                                 if (oldadv != newadv) {
9283                                         phydev->advertising &=
9284                                                 ~(ADVERTISED_Pause |
9285                                                   ADVERTISED_Asym_Pause);
9286                                         phydev->advertising |= newadv;
9287                                         err = phy_start_aneg(phydev);
9288                                 }
9289                         } else {
9290                                 tp->link_config.advertising &=
9291                                                 ~(ADVERTISED_Pause |
9292                                                   ADVERTISED_Asym_Pause);
9293                                 tp->link_config.advertising |= newadv;
9294                         }
9295                 } else {
9296                         if (epause->rx_pause)
9297                                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9298                         else
9299                                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9300
9301                         if (epause->tx_pause)
9302                                 tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9303                         else
9304                                 tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9305
9306                         if (netif_running(dev))
9307                                 tg3_setup_flow_control(tp, 0, 0);
9308                 }
9309         } else {
9310                 int irq_sync = 0;
9311
9312                 if (netif_running(dev)) {
9313                         tg3_netif_stop(tp);
9314                         irq_sync = 1;
9315                 }
9316
9317                 tg3_full_lock(tp, irq_sync);
9318
9319                 if (epause->autoneg)
9320                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9321                 else
9322                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9323                 if (epause->rx_pause)
9324                         tp->link_config.flowctrl |= TG3_FLOW_CTRL_RX;
9325                 else
9326                         tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_RX;
9327                 if (epause->tx_pause)
9328                         tp->link_config.flowctrl |= TG3_FLOW_CTRL_TX;
9329                 else
9330                         tp->link_config.flowctrl &= ~TG3_FLOW_CTRL_TX;
9331
9332                 if (netif_running(dev)) {
9333                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9334                         err = tg3_restart_hw(tp, 1);
9335                         if (!err)
9336                                 tg3_netif_start(tp);
9337                 }
9338
9339                 tg3_full_unlock(tp);
9340         }
9341
9342         return err;
9343 }
9344
9345 static u32 tg3_get_rx_csum(struct net_device *dev)
9346 {
9347         struct tg3 *tp = netdev_priv(dev);
9348         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
9349 }
9350
9351 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
9352 {
9353         struct tg3 *tp = netdev_priv(dev);
9354
9355         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9356                 if (data != 0)
9357                         return -EINVAL;
9358                 return 0;
9359         }
9360
9361         spin_lock_bh(&tp->lock);
9362         if (data)
9363                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
9364         else
9365                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
9366         spin_unlock_bh(&tp->lock);
9367
9368         return 0;
9369 }
9370
9371 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
9372 {
9373         struct tg3 *tp = netdev_priv(dev);
9374
9375         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
9376                 if (data != 0)
9377                         return -EINVAL;
9378                 return 0;
9379         }
9380
9381         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9382             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9383             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9384             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9385             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9386                 ethtool_op_set_tx_ipv6_csum(dev, data);
9387         else
9388                 ethtool_op_set_tx_csum(dev, data);
9389
9390         return 0;
9391 }
9392
9393 static int tg3_get_sset_count (struct net_device *dev, int sset)
9394 {
9395         switch (sset) {
9396         case ETH_SS_TEST:
9397                 return TG3_NUM_TEST;
9398         case ETH_SS_STATS:
9399                 return TG3_NUM_STATS;
9400         default:
9401                 return -EOPNOTSUPP;
9402         }
9403 }
9404
9405 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
9406 {
9407         switch (stringset) {
9408         case ETH_SS_STATS:
9409                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
9410                 break;
9411         case ETH_SS_TEST:
9412                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
9413                 break;
9414         default:
9415                 WARN_ON(1);     /* we need a WARN() */
9416                 break;
9417         }
9418 }
9419
9420 static int tg3_phys_id(struct net_device *dev, u32 data)
9421 {
9422         struct tg3 *tp = netdev_priv(dev);
9423         int i;
9424
9425         if (!netif_running(tp->dev))
9426                 return -EAGAIN;
9427
9428         if (data == 0)
9429                 data = UINT_MAX / 2;
9430
9431         for (i = 0; i < (data * 2); i++) {
9432                 if ((i % 2) == 0)
9433                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9434                                            LED_CTRL_1000MBPS_ON |
9435                                            LED_CTRL_100MBPS_ON |
9436                                            LED_CTRL_10MBPS_ON |
9437                                            LED_CTRL_TRAFFIC_OVERRIDE |
9438                                            LED_CTRL_TRAFFIC_BLINK |
9439                                            LED_CTRL_TRAFFIC_LED);
9440
9441                 else
9442                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
9443                                            LED_CTRL_TRAFFIC_OVERRIDE);
9444
9445                 if (msleep_interruptible(500))
9446                         break;
9447         }
9448         tw32(MAC_LED_CTRL, tp->led_ctrl);
9449         return 0;
9450 }
9451
9452 static void tg3_get_ethtool_stats (struct net_device *dev,
9453                                    struct ethtool_stats *estats, u64 *tmp_stats)
9454 {
9455         struct tg3 *tp = netdev_priv(dev);
9456         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
9457 }
9458
9459 #define NVRAM_TEST_SIZE 0x100
9460 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
9461 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
9462 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
9463 #define NVRAM_SELFBOOT_HW_SIZE 0x20
9464 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
9465
9466 static int tg3_test_nvram(struct tg3 *tp)
9467 {
9468         u32 csum, magic;
9469         __le32 *buf;
9470         int i, j, k, err = 0, size;
9471
9472         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9473                 return -EIO;
9474
9475         if (magic == TG3_EEPROM_MAGIC)
9476                 size = NVRAM_TEST_SIZE;
9477         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
9478                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
9479                     TG3_EEPROM_SB_FORMAT_1) {
9480                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
9481                         case TG3_EEPROM_SB_REVISION_0:
9482                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
9483                                 break;
9484                         case TG3_EEPROM_SB_REVISION_2:
9485                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
9486                                 break;
9487                         case TG3_EEPROM_SB_REVISION_3:
9488                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
9489                                 break;
9490                         default:
9491                                 return 0;
9492                         }
9493                 } else
9494                         return 0;
9495         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
9496                 size = NVRAM_SELFBOOT_HW_SIZE;
9497         else
9498                 return -EIO;
9499
9500         buf = kmalloc(size, GFP_KERNEL);
9501         if (buf == NULL)
9502                 return -ENOMEM;
9503
9504         err = -EIO;
9505         for (i = 0, j = 0; i < size; i += 4, j++) {
9506                 if ((err = tg3_nvram_read_le(tp, i, &buf[j])) != 0)
9507                         break;
9508         }
9509         if (i < size)
9510                 goto out;
9511
9512         /* Selfboot format */
9513         magic = swab32(le32_to_cpu(buf[0]));
9514         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
9515             TG3_EEPROM_MAGIC_FW) {
9516                 u8 *buf8 = (u8 *) buf, csum8 = 0;
9517
9518                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
9519                     TG3_EEPROM_SB_REVISION_2) {
9520                         /* For rev 2, the csum doesn't include the MBA. */
9521                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
9522                                 csum8 += buf8[i];
9523                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
9524                                 csum8 += buf8[i];
9525                 } else {
9526                         for (i = 0; i < size; i++)
9527                                 csum8 += buf8[i];
9528                 }
9529
9530                 if (csum8 == 0) {
9531                         err = 0;
9532                         goto out;
9533                 }
9534
9535                 err = -EIO;
9536                 goto out;
9537         }
9538
9539         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
9540             TG3_EEPROM_MAGIC_HW) {
9541                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
9542                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
9543                 u8 *buf8 = (u8 *) buf;
9544
9545                 /* Separate the parity bits and the data bytes.  */
9546                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
9547                         if ((i == 0) || (i == 8)) {
9548                                 int l;
9549                                 u8 msk;
9550
9551                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
9552                                         parity[k++] = buf8[i] & msk;
9553                                 i++;
9554                         }
9555                         else if (i == 16) {
9556                                 int l;
9557                                 u8 msk;
9558
9559                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
9560                                         parity[k++] = buf8[i] & msk;
9561                                 i++;
9562
9563                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
9564                                         parity[k++] = buf8[i] & msk;
9565                                 i++;
9566                         }
9567                         data[j++] = buf8[i];
9568                 }
9569
9570                 err = -EIO;
9571                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
9572                         u8 hw8 = hweight8(data[i]);
9573
9574                         if ((hw8 & 0x1) && parity[i])
9575                                 goto out;
9576                         else if (!(hw8 & 0x1) && !parity[i])
9577                                 goto out;
9578                 }
9579                 err = 0;
9580                 goto out;
9581         }
9582
9583         /* Bootstrap checksum at offset 0x10 */
9584         csum = calc_crc((unsigned char *) buf, 0x10);
9585         if(csum != le32_to_cpu(buf[0x10/4]))
9586                 goto out;
9587
9588         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
9589         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
9590         if (csum != le32_to_cpu(buf[0xfc/4]))
9591                  goto out;
9592
9593         err = 0;
9594
9595 out:
9596         kfree(buf);
9597         return err;
9598 }
9599
9600 #define TG3_SERDES_TIMEOUT_SEC  2
9601 #define TG3_COPPER_TIMEOUT_SEC  6
9602
9603 static int tg3_test_link(struct tg3 *tp)
9604 {
9605         int i, max;
9606
9607         if (!netif_running(tp->dev))
9608                 return -ENODEV;
9609
9610         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9611                 max = TG3_SERDES_TIMEOUT_SEC;
9612         else
9613                 max = TG3_COPPER_TIMEOUT_SEC;
9614
9615         for (i = 0; i < max; i++) {
9616                 if (netif_carrier_ok(tp->dev))
9617                         return 0;
9618
9619                 if (msleep_interruptible(1000))
9620                         break;
9621         }
9622
9623         return -EIO;
9624 }
9625
9626 /* Only test the commonly used registers */
9627 static int tg3_test_registers(struct tg3 *tp)
9628 {
9629         int i, is_5705, is_5750;
9630         u32 offset, read_mask, write_mask, val, save_val, read_val;
9631         static struct {
9632                 u16 offset;
9633                 u16 flags;
9634 #define TG3_FL_5705     0x1
9635 #define TG3_FL_NOT_5705 0x2
9636 #define TG3_FL_NOT_5788 0x4
9637 #define TG3_FL_NOT_5750 0x8
9638                 u32 read_mask;
9639                 u32 write_mask;
9640         } reg_tbl[] = {
9641                 /* MAC Control Registers */
9642                 { MAC_MODE, TG3_FL_NOT_5705,
9643                         0x00000000, 0x00ef6f8c },
9644                 { MAC_MODE, TG3_FL_5705,
9645                         0x00000000, 0x01ef6b8c },
9646                 { MAC_STATUS, TG3_FL_NOT_5705,
9647                         0x03800107, 0x00000000 },
9648                 { MAC_STATUS, TG3_FL_5705,
9649                         0x03800100, 0x00000000 },
9650                 { MAC_ADDR_0_HIGH, 0x0000,
9651                         0x00000000, 0x0000ffff },
9652                 { MAC_ADDR_0_LOW, 0x0000,
9653                         0x00000000, 0xffffffff },
9654                 { MAC_RX_MTU_SIZE, 0x0000,
9655                         0x00000000, 0x0000ffff },
9656                 { MAC_TX_MODE, 0x0000,
9657                         0x00000000, 0x00000070 },
9658                 { MAC_TX_LENGTHS, 0x0000,
9659                         0x00000000, 0x00003fff },
9660                 { MAC_RX_MODE, TG3_FL_NOT_5705,
9661                         0x00000000, 0x000007fc },
9662                 { MAC_RX_MODE, TG3_FL_5705,
9663                         0x00000000, 0x000007dc },
9664                 { MAC_HASH_REG_0, 0x0000,
9665                         0x00000000, 0xffffffff },
9666                 { MAC_HASH_REG_1, 0x0000,
9667                         0x00000000, 0xffffffff },
9668                 { MAC_HASH_REG_2, 0x0000,
9669                         0x00000000, 0xffffffff },
9670                 { MAC_HASH_REG_3, 0x0000,
9671                         0x00000000, 0xffffffff },
9672
9673                 /* Receive Data and Receive BD Initiator Control Registers. */
9674                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
9675                         0x00000000, 0xffffffff },
9676                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
9677                         0x00000000, 0xffffffff },
9678                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
9679                         0x00000000, 0x00000003 },
9680                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
9681                         0x00000000, 0xffffffff },
9682                 { RCVDBDI_STD_BD+0, 0x0000,
9683                         0x00000000, 0xffffffff },
9684                 { RCVDBDI_STD_BD+4, 0x0000,
9685                         0x00000000, 0xffffffff },
9686                 { RCVDBDI_STD_BD+8, 0x0000,
9687                         0x00000000, 0xffff0002 },
9688                 { RCVDBDI_STD_BD+0xc, 0x0000,
9689                         0x00000000, 0xffffffff },
9690
9691                 /* Receive BD Initiator Control Registers. */
9692                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
9693                         0x00000000, 0xffffffff },
9694                 { RCVBDI_STD_THRESH, TG3_FL_5705,
9695                         0x00000000, 0x000003ff },
9696                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
9697                         0x00000000, 0xffffffff },
9698
9699                 /* Host Coalescing Control Registers. */
9700                 { HOSTCC_MODE, TG3_FL_NOT_5705,
9701                         0x00000000, 0x00000004 },
9702                 { HOSTCC_MODE, TG3_FL_5705,
9703                         0x00000000, 0x000000f6 },
9704                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
9705                         0x00000000, 0xffffffff },
9706                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
9707                         0x00000000, 0x000003ff },
9708                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
9709                         0x00000000, 0xffffffff },
9710                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
9711                         0x00000000, 0x000003ff },
9712                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
9713                         0x00000000, 0xffffffff },
9714                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9715                         0x00000000, 0x000000ff },
9716                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
9717                         0x00000000, 0xffffffff },
9718                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
9719                         0x00000000, 0x000000ff },
9720                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
9721                         0x00000000, 0xffffffff },
9722                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
9723                         0x00000000, 0xffffffff },
9724                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9725                         0x00000000, 0xffffffff },
9726                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9727                         0x00000000, 0x000000ff },
9728                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
9729                         0x00000000, 0xffffffff },
9730                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
9731                         0x00000000, 0x000000ff },
9732                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
9733                         0x00000000, 0xffffffff },
9734                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
9735                         0x00000000, 0xffffffff },
9736                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
9737                         0x00000000, 0xffffffff },
9738                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
9739                         0x00000000, 0xffffffff },
9740                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
9741                         0x00000000, 0xffffffff },
9742                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
9743                         0xffffffff, 0x00000000 },
9744                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
9745                         0xffffffff, 0x00000000 },
9746
9747                 /* Buffer Manager Control Registers. */
9748                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
9749                         0x00000000, 0x007fff80 },
9750                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
9751                         0x00000000, 0x007fffff },
9752                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
9753                         0x00000000, 0x0000003f },
9754                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
9755                         0x00000000, 0x000001ff },
9756                 { BUFMGR_MB_HIGH_WATER, 0x0000,
9757                         0x00000000, 0x000001ff },
9758                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
9759                         0xffffffff, 0x00000000 },
9760                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
9761                         0xffffffff, 0x00000000 },
9762
9763                 /* Mailbox Registers */
9764                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
9765                         0x00000000, 0x000001ff },
9766                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
9767                         0x00000000, 0x000001ff },
9768                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
9769                         0x00000000, 0x000007ff },
9770                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
9771                         0x00000000, 0x000001ff },
9772
9773                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
9774         };
9775
9776         is_5705 = is_5750 = 0;
9777         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9778                 is_5705 = 1;
9779                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9780                         is_5750 = 1;
9781         }
9782
9783         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
9784                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
9785                         continue;
9786
9787                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
9788                         continue;
9789
9790                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9791                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
9792                         continue;
9793
9794                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
9795                         continue;
9796
9797                 offset = (u32) reg_tbl[i].offset;
9798                 read_mask = reg_tbl[i].read_mask;
9799                 write_mask = reg_tbl[i].write_mask;
9800
9801                 /* Save the original register content */
9802                 save_val = tr32(offset);
9803
9804                 /* Determine the read-only value. */
9805                 read_val = save_val & read_mask;
9806
9807                 /* Write zero to the register, then make sure the read-only bits
9808                  * are not changed and the read/write bits are all zeros.
9809                  */
9810                 tw32(offset, 0);
9811
9812                 val = tr32(offset);
9813
9814                 /* Test the read-only and read/write bits. */
9815                 if (((val & read_mask) != read_val) || (val & write_mask))
9816                         goto out;
9817
9818                 /* Write ones to all the bits defined by RdMask and WrMask, then
9819                  * make sure the read-only bits are not changed and the
9820                  * read/write bits are all ones.
9821                  */
9822                 tw32(offset, read_mask | write_mask);
9823
9824                 val = tr32(offset);
9825
9826                 /* Test the read-only bits. */
9827                 if ((val & read_mask) != read_val)
9828                         goto out;
9829
9830                 /* Test the read/write bits. */
9831                 if ((val & write_mask) != write_mask)
9832                         goto out;
9833
9834                 tw32(offset, save_val);
9835         }
9836
9837         return 0;
9838
9839 out:
9840         if (netif_msg_hw(tp))
9841                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
9842                        offset);
9843         tw32(offset, save_val);
9844         return -EIO;
9845 }
9846
9847 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
9848 {
9849         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
9850         int i;
9851         u32 j;
9852
9853         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
9854                 for (j = 0; j < len; j += 4) {
9855                         u32 val;
9856
9857                         tg3_write_mem(tp, offset + j, test_pattern[i]);
9858                         tg3_read_mem(tp, offset + j, &val);
9859                         if (val != test_pattern[i])
9860                                 return -EIO;
9861                 }
9862         }
9863         return 0;
9864 }
9865
9866 static int tg3_test_memory(struct tg3 *tp)
9867 {
9868         static struct mem_entry {
9869                 u32 offset;
9870                 u32 len;
9871         } mem_tbl_570x[] = {
9872                 { 0x00000000, 0x00b50},
9873                 { 0x00002000, 0x1c000},
9874                 { 0xffffffff, 0x00000}
9875         }, mem_tbl_5705[] = {
9876                 { 0x00000100, 0x0000c},
9877                 { 0x00000200, 0x00008},
9878                 { 0x00004000, 0x00800},
9879                 { 0x00006000, 0x01000},
9880                 { 0x00008000, 0x02000},
9881                 { 0x00010000, 0x0e000},
9882                 { 0xffffffff, 0x00000}
9883         }, mem_tbl_5755[] = {
9884                 { 0x00000200, 0x00008},
9885                 { 0x00004000, 0x00800},
9886                 { 0x00006000, 0x00800},
9887                 { 0x00008000, 0x02000},
9888                 { 0x00010000, 0x0c000},
9889                 { 0xffffffff, 0x00000}
9890         }, mem_tbl_5906[] = {
9891                 { 0x00000200, 0x00008},
9892                 { 0x00004000, 0x00400},
9893                 { 0x00006000, 0x00400},
9894                 { 0x00008000, 0x01000},
9895                 { 0x00010000, 0x01000},
9896                 { 0xffffffff, 0x00000}
9897         };
9898         struct mem_entry *mem_tbl;
9899         int err = 0;
9900         int i;
9901
9902         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9903                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
9904                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
9905                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
9906                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9907                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
9908                         mem_tbl = mem_tbl_5755;
9909                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9910                         mem_tbl = mem_tbl_5906;
9911                 else
9912                         mem_tbl = mem_tbl_5705;
9913         } else
9914                 mem_tbl = mem_tbl_570x;
9915
9916         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
9917                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
9918                     mem_tbl[i].len)) != 0)
9919                         break;
9920         }
9921
9922         return err;
9923 }
9924
9925 #define TG3_MAC_LOOPBACK        0
9926 #define TG3_PHY_LOOPBACK        1
9927
9928 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
9929 {
9930         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
9931         u32 desc_idx;
9932         struct sk_buff *skb, *rx_skb;
9933         u8 *tx_data;
9934         dma_addr_t map;
9935         int num_pkts, tx_len, rx_len, i, err;
9936         struct tg3_rx_buffer_desc *desc;
9937
9938         if (loopback_mode == TG3_MAC_LOOPBACK) {
9939                 /* HW errata - mac loopback fails in some cases on 5780.
9940                  * Normal traffic and PHY loopback are not affected by
9941                  * errata.
9942                  */
9943                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
9944                         return 0;
9945
9946                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
9947                            MAC_MODE_PORT_INT_LPBACK;
9948                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9949                         mac_mode |= MAC_MODE_LINK_POLARITY;
9950                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9951                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9952                 else
9953                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9954                 tw32(MAC_MODE, mac_mode);
9955         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
9956                 u32 val;
9957
9958                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9959                         u32 phytest;
9960
9961                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
9962                                 u32 phy;
9963
9964                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
9965                                              phytest | MII_TG3_EPHY_SHADOW_EN);
9966                                 if (!tg3_readphy(tp, 0x1b, &phy))
9967                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
9968                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
9969                         }
9970                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
9971                 } else
9972                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
9973
9974                 tg3_phy_toggle_automdix(tp, 0);
9975
9976                 tg3_writephy(tp, MII_BMCR, val);
9977                 udelay(40);
9978
9979                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
9980                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9981                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
9982                         mac_mode |= MAC_MODE_PORT_MODE_MII;
9983                 } else
9984                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
9985
9986                 /* reset to prevent losing 1st rx packet intermittently */
9987                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
9988                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
9989                         udelay(10);
9990                         tw32_f(MAC_RX_MODE, tp->rx_mode);
9991                 }
9992                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
9993                         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
9994                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
9995                         else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
9996                                 mac_mode |= MAC_MODE_LINK_POLARITY;
9997                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
9998                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
9999                 }
10000                 tw32(MAC_MODE, mac_mode);
10001         }
10002         else
10003                 return -EINVAL;
10004
10005         err = -EIO;
10006
10007         tx_len = 1514;
10008         skb = netdev_alloc_skb(tp->dev, tx_len);
10009         if (!skb)
10010                 return -ENOMEM;
10011
10012         tx_data = skb_put(skb, tx_len);
10013         memcpy(tx_data, tp->dev->dev_addr, 6);
10014         memset(tx_data + 6, 0x0, 8);
10015
10016         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10017
10018         for (i = 14; i < tx_len; i++)
10019                 tx_data[i] = (u8) (i & 0xff);
10020
10021         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10022
10023         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10024              HOSTCC_MODE_NOW);
10025
10026         udelay(10);
10027
10028         rx_start_idx = tp->hw_status->idx[0].rx_producer;
10029
10030         num_pkts = 0;
10031
10032         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
10033
10034         tp->tx_prod++;
10035         num_pkts++;
10036
10037         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
10038                      tp->tx_prod);
10039         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
10040
10041         udelay(10);
10042
10043         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
10044         for (i = 0; i < 25; i++) {
10045                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10046                        HOSTCC_MODE_NOW);
10047
10048                 udelay(10);
10049
10050                 tx_idx = tp->hw_status->idx[0].tx_consumer;
10051                 rx_idx = tp->hw_status->idx[0].rx_producer;
10052                 if ((tx_idx == tp->tx_prod) &&
10053                     (rx_idx == (rx_start_idx + num_pkts)))
10054                         break;
10055         }
10056
10057         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10058         dev_kfree_skb(skb);
10059
10060         if (tx_idx != tp->tx_prod)
10061                 goto out;
10062
10063         if (rx_idx != rx_start_idx + num_pkts)
10064                 goto out;
10065
10066         desc = &tp->rx_rcb[rx_start_idx];
10067         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10068         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10069         if (opaque_key != RXD_OPAQUE_RING_STD)
10070                 goto out;
10071
10072         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10073             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10074                 goto out;
10075
10076         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10077         if (rx_len != tx_len)
10078                 goto out;
10079
10080         rx_skb = tp->rx_std_buffers[desc_idx].skb;
10081
10082         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
10083         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10084
10085         for (i = 14; i < tx_len; i++) {
10086                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10087                         goto out;
10088         }
10089         err = 0;
10090
10091         /* tg3_free_rings will unmap and free the rx_skb */
10092 out:
10093         return err;
10094 }
10095
10096 #define TG3_MAC_LOOPBACK_FAILED         1
10097 #define TG3_PHY_LOOPBACK_FAILED         2
10098 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10099                                          TG3_PHY_LOOPBACK_FAILED)
10100
10101 static int tg3_test_loopback(struct tg3 *tp)
10102 {
10103         int err = 0;
10104         u32 cpmuctrl = 0;
10105
10106         if (!netif_running(tp->dev))
10107                 return TG3_LOOPBACK_FAILED;
10108
10109         err = tg3_reset_hw(tp, 1);
10110         if (err)
10111                 return TG3_LOOPBACK_FAILED;
10112
10113         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10114             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10115             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10116                 int i;
10117                 u32 status;
10118
10119                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10120
10121                 /* Wait for up to 40 microseconds to acquire lock. */
10122                 for (i = 0; i < 4; i++) {
10123                         status = tr32(TG3_CPMU_MUTEX_GNT);
10124                         if (status == CPMU_MUTEX_GNT_DRIVER)
10125                                 break;
10126                         udelay(10);
10127                 }
10128
10129                 if (status != CPMU_MUTEX_GNT_DRIVER)
10130                         return TG3_LOOPBACK_FAILED;
10131
10132                 /* Turn off link-based power management. */
10133                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10134                 tw32(TG3_CPMU_CTRL,
10135                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10136                                   CPMU_CTRL_LINK_AWARE_MODE));
10137         }
10138
10139         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10140                 err |= TG3_MAC_LOOPBACK_FAILED;
10141
10142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10143             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10144             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
10145                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10146
10147                 /* Release the mutex */
10148                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10149         }
10150
10151         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10152             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10153                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10154                         err |= TG3_PHY_LOOPBACK_FAILED;
10155         }
10156
10157         return err;
10158 }
10159
10160 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10161                           u64 *data)
10162 {
10163         struct tg3 *tp = netdev_priv(dev);
10164
10165         if (tp->link_config.phy_is_low_power)
10166                 tg3_set_power_state(tp, PCI_D0);
10167
10168         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10169
10170         if (tg3_test_nvram(tp) != 0) {
10171                 etest->flags |= ETH_TEST_FL_FAILED;
10172                 data[0] = 1;
10173         }
10174         if (tg3_test_link(tp) != 0) {
10175                 etest->flags |= ETH_TEST_FL_FAILED;
10176                 data[1] = 1;
10177         }
10178         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10179                 int err, err2 = 0, irq_sync = 0;
10180
10181                 if (netif_running(dev)) {
10182                         tg3_phy_stop(tp);
10183                         tg3_netif_stop(tp);
10184                         irq_sync = 1;
10185                 }
10186
10187                 tg3_full_lock(tp, irq_sync);
10188
10189                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10190                 err = tg3_nvram_lock(tp);
10191                 tg3_halt_cpu(tp, RX_CPU_BASE);
10192                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10193                         tg3_halt_cpu(tp, TX_CPU_BASE);
10194                 if (!err)
10195                         tg3_nvram_unlock(tp);
10196
10197                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10198                         tg3_phy_reset(tp);
10199
10200                 if (tg3_test_registers(tp) != 0) {
10201                         etest->flags |= ETH_TEST_FL_FAILED;
10202                         data[2] = 1;
10203                 }
10204                 if (tg3_test_memory(tp) != 0) {
10205                         etest->flags |= ETH_TEST_FL_FAILED;
10206                         data[3] = 1;
10207                 }
10208                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10209                         etest->flags |= ETH_TEST_FL_FAILED;
10210
10211                 tg3_full_unlock(tp);
10212
10213                 if (tg3_test_interrupt(tp) != 0) {
10214                         etest->flags |= ETH_TEST_FL_FAILED;
10215                         data[5] = 1;
10216                 }
10217
10218                 tg3_full_lock(tp, 0);
10219
10220                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10221                 if (netif_running(dev)) {
10222                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10223                         err2 = tg3_restart_hw(tp, 1);
10224                         if (!err2)
10225                                 tg3_netif_start(tp);
10226                 }
10227
10228                 tg3_full_unlock(tp);
10229
10230                 if (irq_sync && !err2)
10231                         tg3_phy_start(tp);
10232         }
10233         if (tp->link_config.phy_is_low_power)
10234                 tg3_set_power_state(tp, PCI_D3hot);
10235
10236 }
10237
10238 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10239 {
10240         struct mii_ioctl_data *data = if_mii(ifr);
10241         struct tg3 *tp = netdev_priv(dev);
10242         int err;
10243
10244         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10245                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10246                         return -EAGAIN;
10247                 return phy_mii_ioctl(tp->mdio_bus.phy_map[PHY_ADDR], data, cmd);
10248         }
10249
10250         switch(cmd) {
10251         case SIOCGMIIPHY:
10252                 data->phy_id = PHY_ADDR;
10253
10254                 /* fallthru */
10255         case SIOCGMIIREG: {
10256                 u32 mii_regval;
10257
10258                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10259                         break;                  /* We have no PHY */
10260
10261                 if (tp->link_config.phy_is_low_power)
10262                         return -EAGAIN;
10263
10264                 spin_lock_bh(&tp->lock);
10265                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10266                 spin_unlock_bh(&tp->lock);
10267
10268                 data->val_out = mii_regval;
10269
10270                 return err;
10271         }
10272
10273         case SIOCSMIIREG:
10274                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10275                         break;                  /* We have no PHY */
10276
10277                 if (!capable(CAP_NET_ADMIN))
10278                         return -EPERM;
10279
10280                 if (tp->link_config.phy_is_low_power)
10281                         return -EAGAIN;
10282
10283                 spin_lock_bh(&tp->lock);
10284                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10285                 spin_unlock_bh(&tp->lock);
10286
10287                 return err;
10288
10289         default:
10290                 /* do nothing */
10291                 break;
10292         }
10293         return -EOPNOTSUPP;
10294 }
10295
10296 #if TG3_VLAN_TAG_USED
10297 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10298 {
10299         struct tg3 *tp = netdev_priv(dev);
10300
10301         if (netif_running(dev))
10302                 tg3_netif_stop(tp);
10303
10304         tg3_full_lock(tp, 0);
10305
10306         tp->vlgrp = grp;
10307
10308         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
10309         __tg3_set_rx_mode(dev);
10310
10311         if (netif_running(dev))
10312                 tg3_netif_start(tp);
10313
10314         tg3_full_unlock(tp);
10315 }
10316 #endif
10317
10318 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10319 {
10320         struct tg3 *tp = netdev_priv(dev);
10321
10322         memcpy(ec, &tp->coal, sizeof(*ec));
10323         return 0;
10324 }
10325
10326 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
10327 {
10328         struct tg3 *tp = netdev_priv(dev);
10329         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
10330         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
10331
10332         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
10333                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
10334                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
10335                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
10336                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
10337         }
10338
10339         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
10340             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
10341             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
10342             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
10343             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
10344             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
10345             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
10346             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
10347             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
10348             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
10349                 return -EINVAL;
10350
10351         /* No rx interrupts will be generated if both are zero */
10352         if ((ec->rx_coalesce_usecs == 0) &&
10353             (ec->rx_max_coalesced_frames == 0))
10354                 return -EINVAL;
10355
10356         /* No tx interrupts will be generated if both are zero */
10357         if ((ec->tx_coalesce_usecs == 0) &&
10358             (ec->tx_max_coalesced_frames == 0))
10359                 return -EINVAL;
10360
10361         /* Only copy relevant parameters, ignore all others. */
10362         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
10363         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
10364         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
10365         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
10366         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
10367         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
10368         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
10369         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
10370         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
10371
10372         if (netif_running(dev)) {
10373                 tg3_full_lock(tp, 0);
10374                 __tg3_set_coalesce(tp, &tp->coal);
10375                 tg3_full_unlock(tp);
10376         }
10377         return 0;
10378 }
10379
10380 static const struct ethtool_ops tg3_ethtool_ops = {
10381         .get_settings           = tg3_get_settings,
10382         .set_settings           = tg3_set_settings,
10383         .get_drvinfo            = tg3_get_drvinfo,
10384         .get_regs_len           = tg3_get_regs_len,
10385         .get_regs               = tg3_get_regs,
10386         .get_wol                = tg3_get_wol,
10387         .set_wol                = tg3_set_wol,
10388         .get_msglevel           = tg3_get_msglevel,
10389         .set_msglevel           = tg3_set_msglevel,
10390         .nway_reset             = tg3_nway_reset,
10391         .get_link               = ethtool_op_get_link,
10392         .get_eeprom_len         = tg3_get_eeprom_len,
10393         .get_eeprom             = tg3_get_eeprom,
10394         .set_eeprom             = tg3_set_eeprom,
10395         .get_ringparam          = tg3_get_ringparam,
10396         .set_ringparam          = tg3_set_ringparam,
10397         .get_pauseparam         = tg3_get_pauseparam,
10398         .set_pauseparam         = tg3_set_pauseparam,
10399         .get_rx_csum            = tg3_get_rx_csum,
10400         .set_rx_csum            = tg3_set_rx_csum,
10401         .set_tx_csum            = tg3_set_tx_csum,
10402         .set_sg                 = ethtool_op_set_sg,
10403         .set_tso                = tg3_set_tso,
10404         .self_test              = tg3_self_test,
10405         .get_strings            = tg3_get_strings,
10406         .phys_id                = tg3_phys_id,
10407         .get_ethtool_stats      = tg3_get_ethtool_stats,
10408         .get_coalesce           = tg3_get_coalesce,
10409         .set_coalesce           = tg3_set_coalesce,
10410         .get_sset_count         = tg3_get_sset_count,
10411 };
10412
10413 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
10414 {
10415         u32 cursize, val, magic;
10416
10417         tp->nvram_size = EEPROM_CHIP_SIZE;
10418
10419         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
10420                 return;
10421
10422         if ((magic != TG3_EEPROM_MAGIC) &&
10423             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
10424             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
10425                 return;
10426
10427         /*
10428          * Size the chip by reading offsets at increasing powers of two.
10429          * When we encounter our validation signature, we know the addressing
10430          * has wrapped around, and thus have our chip size.
10431          */
10432         cursize = 0x10;
10433
10434         while (cursize < tp->nvram_size) {
10435                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
10436                         return;
10437
10438                 if (val == magic)
10439                         break;
10440
10441                 cursize <<= 1;
10442         }
10443
10444         tp->nvram_size = cursize;
10445 }
10446
10447 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
10448 {
10449         u32 val;
10450
10451         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
10452                 return;
10453
10454         /* Selfboot format */
10455         if (val != TG3_EEPROM_MAGIC) {
10456                 tg3_get_eeprom_size(tp);
10457                 return;
10458         }
10459
10460         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
10461                 if (val != 0) {
10462                         tp->nvram_size = (val >> 16) * 1024;
10463                         return;
10464                 }
10465         }
10466         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10467 }
10468
10469 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
10470 {
10471         u32 nvcfg1;
10472
10473         nvcfg1 = tr32(NVRAM_CFG1);
10474         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
10475                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
10476         }
10477         else {
10478                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10479                 tw32(NVRAM_CFG1, nvcfg1);
10480         }
10481
10482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
10483             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
10484                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
10485                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
10486                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10487                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10488                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10489                                 break;
10490                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
10491                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10492                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
10493                                 break;
10494                         case FLASH_VENDOR_ATMEL_EEPROM:
10495                                 tp->nvram_jedecnum = JEDEC_ATMEL;
10496                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10497                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10498                                 break;
10499                         case FLASH_VENDOR_ST:
10500                                 tp->nvram_jedecnum = JEDEC_ST;
10501                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
10502                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10503                                 break;
10504                         case FLASH_VENDOR_SAIFUN:
10505                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
10506                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
10507                                 break;
10508                         case FLASH_VENDOR_SST_SMALL:
10509                         case FLASH_VENDOR_SST_LARGE:
10510                                 tp->nvram_jedecnum = JEDEC_SST;
10511                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
10512                                 break;
10513                 }
10514         }
10515         else {
10516                 tp->nvram_jedecnum = JEDEC_ATMEL;
10517                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
10518                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10519         }
10520 }
10521
10522 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
10523 {
10524         u32 nvcfg1;
10525
10526         nvcfg1 = tr32(NVRAM_CFG1);
10527
10528         /* NVRAM protection for TPM */
10529         if (nvcfg1 & (1 << 27))
10530                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10531
10532         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10533                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
10534                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
10535                         tp->nvram_jedecnum = JEDEC_ATMEL;
10536                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10537                         break;
10538                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10539                         tp->nvram_jedecnum = JEDEC_ATMEL;
10540                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10541                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10542                         break;
10543                 case FLASH_5752VENDOR_ST_M45PE10:
10544                 case FLASH_5752VENDOR_ST_M45PE20:
10545                 case FLASH_5752VENDOR_ST_M45PE40:
10546                         tp->nvram_jedecnum = JEDEC_ST;
10547                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10548                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10549                         break;
10550         }
10551
10552         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
10553                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
10554                         case FLASH_5752PAGE_SIZE_256:
10555                                 tp->nvram_pagesize = 256;
10556                                 break;
10557                         case FLASH_5752PAGE_SIZE_512:
10558                                 tp->nvram_pagesize = 512;
10559                                 break;
10560                         case FLASH_5752PAGE_SIZE_1K:
10561                                 tp->nvram_pagesize = 1024;
10562                                 break;
10563                         case FLASH_5752PAGE_SIZE_2K:
10564                                 tp->nvram_pagesize = 2048;
10565                                 break;
10566                         case FLASH_5752PAGE_SIZE_4K:
10567                                 tp->nvram_pagesize = 4096;
10568                                 break;
10569                         case FLASH_5752PAGE_SIZE_264:
10570                                 tp->nvram_pagesize = 264;
10571                                 break;
10572                 }
10573         }
10574         else {
10575                 /* For eeprom, set pagesize to maximum eeprom size */
10576                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10577
10578                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10579                 tw32(NVRAM_CFG1, nvcfg1);
10580         }
10581 }
10582
10583 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
10584 {
10585         u32 nvcfg1, protect = 0;
10586
10587         nvcfg1 = tr32(NVRAM_CFG1);
10588
10589         /* NVRAM protection for TPM */
10590         if (nvcfg1 & (1 << 27)) {
10591                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10592                 protect = 1;
10593         }
10594
10595         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10596         switch (nvcfg1) {
10597                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10598                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10599                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10600                 case FLASH_5755VENDOR_ATMEL_FLASH_5:
10601                         tp->nvram_jedecnum = JEDEC_ATMEL;
10602                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10603                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10604                         tp->nvram_pagesize = 264;
10605                         if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
10606                             nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
10607                                 tp->nvram_size = (protect ? 0x3e200 :
10608                                                   TG3_NVRAM_SIZE_512KB);
10609                         else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
10610                                 tp->nvram_size = (protect ? 0x1f200 :
10611                                                   TG3_NVRAM_SIZE_256KB);
10612                         else
10613                                 tp->nvram_size = (protect ? 0x1f200 :
10614                                                   TG3_NVRAM_SIZE_128KB);
10615                         break;
10616                 case FLASH_5752VENDOR_ST_M45PE10:
10617                 case FLASH_5752VENDOR_ST_M45PE20:
10618                 case FLASH_5752VENDOR_ST_M45PE40:
10619                         tp->nvram_jedecnum = JEDEC_ST;
10620                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10621                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10622                         tp->nvram_pagesize = 256;
10623                         if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
10624                                 tp->nvram_size = (protect ?
10625                                                   TG3_NVRAM_SIZE_64KB :
10626                                                   TG3_NVRAM_SIZE_128KB);
10627                         else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
10628                                 tp->nvram_size = (protect ?
10629                                                   TG3_NVRAM_SIZE_64KB :
10630                                                   TG3_NVRAM_SIZE_256KB);
10631                         else
10632                                 tp->nvram_size = (protect ?
10633                                                   TG3_NVRAM_SIZE_128KB :
10634                                                   TG3_NVRAM_SIZE_512KB);
10635                         break;
10636         }
10637 }
10638
10639 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
10640 {
10641         u32 nvcfg1;
10642
10643         nvcfg1 = tr32(NVRAM_CFG1);
10644
10645         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
10646                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
10647                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
10648                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
10649                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
10650                         tp->nvram_jedecnum = JEDEC_ATMEL;
10651                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10652                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10653
10654                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
10655                         tw32(NVRAM_CFG1, nvcfg1);
10656                         break;
10657                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
10658                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
10659                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
10660                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
10661                         tp->nvram_jedecnum = JEDEC_ATMEL;
10662                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10663                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10664                         tp->nvram_pagesize = 264;
10665                         break;
10666                 case FLASH_5752VENDOR_ST_M45PE10:
10667                 case FLASH_5752VENDOR_ST_M45PE20:
10668                 case FLASH_5752VENDOR_ST_M45PE40:
10669                         tp->nvram_jedecnum = JEDEC_ST;
10670                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10671                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10672                         tp->nvram_pagesize = 256;
10673                         break;
10674         }
10675 }
10676
10677 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
10678 {
10679         u32 nvcfg1, protect = 0;
10680
10681         nvcfg1 = tr32(NVRAM_CFG1);
10682
10683         /* NVRAM protection for TPM */
10684         if (nvcfg1 & (1 << 27)) {
10685                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
10686                 protect = 1;
10687         }
10688
10689         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
10690         switch (nvcfg1) {
10691                 case FLASH_5761VENDOR_ATMEL_ADB021D:
10692                 case FLASH_5761VENDOR_ATMEL_ADB041D:
10693                 case FLASH_5761VENDOR_ATMEL_ADB081D:
10694                 case FLASH_5761VENDOR_ATMEL_ADB161D:
10695                 case FLASH_5761VENDOR_ATMEL_MDB021D:
10696                 case FLASH_5761VENDOR_ATMEL_MDB041D:
10697                 case FLASH_5761VENDOR_ATMEL_MDB081D:
10698                 case FLASH_5761VENDOR_ATMEL_MDB161D:
10699                         tp->nvram_jedecnum = JEDEC_ATMEL;
10700                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10701                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10702                         tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
10703                         tp->nvram_pagesize = 256;
10704                         break;
10705                 case FLASH_5761VENDOR_ST_A_M45PE20:
10706                 case FLASH_5761VENDOR_ST_A_M45PE40:
10707                 case FLASH_5761VENDOR_ST_A_M45PE80:
10708                 case FLASH_5761VENDOR_ST_A_M45PE16:
10709                 case FLASH_5761VENDOR_ST_M_M45PE20:
10710                 case FLASH_5761VENDOR_ST_M_M45PE40:
10711                 case FLASH_5761VENDOR_ST_M_M45PE80:
10712                 case FLASH_5761VENDOR_ST_M_M45PE16:
10713                         tp->nvram_jedecnum = JEDEC_ST;
10714                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10715                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
10716                         tp->nvram_pagesize = 256;
10717                         break;
10718         }
10719
10720         if (protect) {
10721                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
10722         } else {
10723                 switch (nvcfg1) {
10724                         case FLASH_5761VENDOR_ATMEL_ADB161D:
10725                         case FLASH_5761VENDOR_ATMEL_MDB161D:
10726                         case FLASH_5761VENDOR_ST_A_M45PE16:
10727                         case FLASH_5761VENDOR_ST_M_M45PE16:
10728                                 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
10729                                 break;
10730                         case FLASH_5761VENDOR_ATMEL_ADB081D:
10731                         case FLASH_5761VENDOR_ATMEL_MDB081D:
10732                         case FLASH_5761VENDOR_ST_A_M45PE80:
10733                         case FLASH_5761VENDOR_ST_M_M45PE80:
10734                                 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
10735                                 break;
10736                         case FLASH_5761VENDOR_ATMEL_ADB041D:
10737                         case FLASH_5761VENDOR_ATMEL_MDB041D:
10738                         case FLASH_5761VENDOR_ST_A_M45PE40:
10739                         case FLASH_5761VENDOR_ST_M_M45PE40:
10740                                 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
10741                                 break;
10742                         case FLASH_5761VENDOR_ATMEL_ADB021D:
10743                         case FLASH_5761VENDOR_ATMEL_MDB021D:
10744                         case FLASH_5761VENDOR_ST_A_M45PE20:
10745                         case FLASH_5761VENDOR_ST_M_M45PE20:
10746                                 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
10747                                 break;
10748                 }
10749         }
10750 }
10751
10752 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
10753 {
10754         tp->nvram_jedecnum = JEDEC_ATMEL;
10755         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
10756         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
10757 }
10758
10759 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
10760 static void __devinit tg3_nvram_init(struct tg3 *tp)
10761 {
10762         tw32_f(GRC_EEPROM_ADDR,
10763              (EEPROM_ADDR_FSM_RESET |
10764               (EEPROM_DEFAULT_CLOCK_PERIOD <<
10765                EEPROM_ADDR_CLKPERD_SHIFT)));
10766
10767         msleep(1);
10768
10769         /* Enable seeprom accesses. */
10770         tw32_f(GRC_LOCAL_CTRL,
10771              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
10772         udelay(100);
10773
10774         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10775             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
10776                 tp->tg3_flags |= TG3_FLAG_NVRAM;
10777
10778                 if (tg3_nvram_lock(tp)) {
10779                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
10780                                "tg3_nvram_init failed.\n", tp->dev->name);
10781                         return;
10782                 }
10783                 tg3_enable_nvram_access(tp);
10784
10785                 tp->nvram_size = 0;
10786
10787                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10788                         tg3_get_5752_nvram_info(tp);
10789                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10790                         tg3_get_5755_nvram_info(tp);
10791                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10792                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
10793                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10794                         tg3_get_5787_nvram_info(tp);
10795                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
10796                         tg3_get_5761_nvram_info(tp);
10797                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10798                         tg3_get_5906_nvram_info(tp);
10799                 else
10800                         tg3_get_nvram_info(tp);
10801
10802                 if (tp->nvram_size == 0)
10803                         tg3_get_nvram_size(tp);
10804
10805                 tg3_disable_nvram_access(tp);
10806                 tg3_nvram_unlock(tp);
10807
10808         } else {
10809                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
10810
10811                 tg3_get_eeprom_size(tp);
10812         }
10813 }
10814
10815 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
10816                                         u32 offset, u32 *val)
10817 {
10818         u32 tmp;
10819         int i;
10820
10821         if (offset > EEPROM_ADDR_ADDR_MASK ||
10822             (offset % 4) != 0)
10823                 return -EINVAL;
10824
10825         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
10826                                         EEPROM_ADDR_DEVID_MASK |
10827                                         EEPROM_ADDR_READ);
10828         tw32(GRC_EEPROM_ADDR,
10829              tmp |
10830              (0 << EEPROM_ADDR_DEVID_SHIFT) |
10831              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
10832               EEPROM_ADDR_ADDR_MASK) |
10833              EEPROM_ADDR_READ | EEPROM_ADDR_START);
10834
10835         for (i = 0; i < 1000; i++) {
10836                 tmp = tr32(GRC_EEPROM_ADDR);
10837
10838                 if (tmp & EEPROM_ADDR_COMPLETE)
10839                         break;
10840                 msleep(1);
10841         }
10842         if (!(tmp & EEPROM_ADDR_COMPLETE))
10843                 return -EBUSY;
10844
10845         *val = tr32(GRC_EEPROM_DATA);
10846         return 0;
10847 }
10848
10849 #define NVRAM_CMD_TIMEOUT 10000
10850
10851 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
10852 {
10853         int i;
10854
10855         tw32(NVRAM_CMD, nvram_cmd);
10856         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
10857                 udelay(10);
10858                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
10859                         udelay(10);
10860                         break;
10861                 }
10862         }
10863         if (i == NVRAM_CMD_TIMEOUT) {
10864                 return -EBUSY;
10865         }
10866         return 0;
10867 }
10868
10869 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
10870 {
10871         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10872             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10873             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10874            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10875             (tp->nvram_jedecnum == JEDEC_ATMEL))
10876
10877                 addr = ((addr / tp->nvram_pagesize) <<
10878                         ATMEL_AT45DB0X1B_PAGE_POS) +
10879                        (addr % tp->nvram_pagesize);
10880
10881         return addr;
10882 }
10883
10884 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
10885 {
10886         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
10887             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
10888             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
10889            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
10890             (tp->nvram_jedecnum == JEDEC_ATMEL))
10891
10892                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
10893                         tp->nvram_pagesize) +
10894                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
10895
10896         return addr;
10897 }
10898
10899 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
10900 {
10901         int ret;
10902
10903         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
10904                 return tg3_nvram_read_using_eeprom(tp, offset, val);
10905
10906         offset = tg3_nvram_phys_addr(tp, offset);
10907
10908         if (offset > NVRAM_ADDR_MSK)
10909                 return -EINVAL;
10910
10911         ret = tg3_nvram_lock(tp);
10912         if (ret)
10913                 return ret;
10914
10915         tg3_enable_nvram_access(tp);
10916
10917         tw32(NVRAM_ADDR, offset);
10918         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
10919                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
10920
10921         if (ret == 0)
10922                 *val = swab32(tr32(NVRAM_RDDATA));
10923
10924         tg3_disable_nvram_access(tp);
10925
10926         tg3_nvram_unlock(tp);
10927
10928         return ret;
10929 }
10930
10931 static int tg3_nvram_read_le(struct tg3 *tp, u32 offset, __le32 *val)
10932 {
10933         u32 v;
10934         int res = tg3_nvram_read(tp, offset, &v);
10935         if (!res)
10936                 *val = cpu_to_le32(v);
10937         return res;
10938 }
10939
10940 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
10941 {
10942         int err;
10943         u32 tmp;
10944
10945         err = tg3_nvram_read(tp, offset, &tmp);
10946         *val = swab32(tmp);
10947         return err;
10948 }
10949
10950 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
10951                                     u32 offset, u32 len, u8 *buf)
10952 {
10953         int i, j, rc = 0;
10954         u32 val;
10955
10956         for (i = 0; i < len; i += 4) {
10957                 u32 addr;
10958                 __le32 data;
10959
10960                 addr = offset + i;
10961
10962                 memcpy(&data, buf + i, 4);
10963
10964                 tw32(GRC_EEPROM_DATA, le32_to_cpu(data));
10965
10966                 val = tr32(GRC_EEPROM_ADDR);
10967                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
10968
10969                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
10970                         EEPROM_ADDR_READ);
10971                 tw32(GRC_EEPROM_ADDR, val |
10972                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
10973                         (addr & EEPROM_ADDR_ADDR_MASK) |
10974                         EEPROM_ADDR_START |
10975                         EEPROM_ADDR_WRITE);
10976
10977                 for (j = 0; j < 1000; j++) {
10978                         val = tr32(GRC_EEPROM_ADDR);
10979
10980                         if (val & EEPROM_ADDR_COMPLETE)
10981                                 break;
10982                         msleep(1);
10983                 }
10984                 if (!(val & EEPROM_ADDR_COMPLETE)) {
10985                         rc = -EBUSY;
10986                         break;
10987                 }
10988         }
10989
10990         return rc;
10991 }
10992
10993 /* offset and length are dword aligned */
10994 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
10995                 u8 *buf)
10996 {
10997         int ret = 0;
10998         u32 pagesize = tp->nvram_pagesize;
10999         u32 pagemask = pagesize - 1;
11000         u32 nvram_cmd;
11001         u8 *tmp;
11002
11003         tmp = kmalloc(pagesize, GFP_KERNEL);
11004         if (tmp == NULL)
11005                 return -ENOMEM;
11006
11007         while (len) {
11008                 int j;
11009                 u32 phy_addr, page_off, size;
11010
11011                 phy_addr = offset & ~pagemask;
11012
11013                 for (j = 0; j < pagesize; j += 4) {
11014                         if ((ret = tg3_nvram_read_le(tp, phy_addr + j,
11015                                                 (__le32 *) (tmp + j))))
11016                                 break;
11017                 }
11018                 if (ret)
11019                         break;
11020
11021                 page_off = offset & pagemask;
11022                 size = pagesize;
11023                 if (len < size)
11024                         size = len;
11025
11026                 len -= size;
11027
11028                 memcpy(tmp + page_off, buf, size);
11029
11030                 offset = offset + (pagesize - page_off);
11031
11032                 tg3_enable_nvram_access(tp);
11033
11034                 /*
11035                  * Before we can erase the flash page, we need
11036                  * to issue a special "write enable" command.
11037                  */
11038                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11039
11040                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11041                         break;
11042
11043                 /* Erase the target page */
11044                 tw32(NVRAM_ADDR, phy_addr);
11045
11046                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11047                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11048
11049                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11050                         break;
11051
11052                 /* Issue another write enable to start the write. */
11053                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11054
11055                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11056                         break;
11057
11058                 for (j = 0; j < pagesize; j += 4) {
11059                         __be32 data;
11060
11061                         data = *((__be32 *) (tmp + j));
11062                         /* swab32(le32_to_cpu(data)), actually */
11063                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11064
11065                         tw32(NVRAM_ADDR, phy_addr + j);
11066
11067                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11068                                 NVRAM_CMD_WR;
11069
11070                         if (j == 0)
11071                                 nvram_cmd |= NVRAM_CMD_FIRST;
11072                         else if (j == (pagesize - 4))
11073                                 nvram_cmd |= NVRAM_CMD_LAST;
11074
11075                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11076                                 break;
11077                 }
11078                 if (ret)
11079                         break;
11080         }
11081
11082         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11083         tg3_nvram_exec_cmd(tp, nvram_cmd);
11084
11085         kfree(tmp);
11086
11087         return ret;
11088 }
11089
11090 /* offset and length are dword aligned */
11091 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11092                 u8 *buf)
11093 {
11094         int i, ret = 0;
11095
11096         for (i = 0; i < len; i += 4, offset += 4) {
11097                 u32 page_off, phy_addr, nvram_cmd;
11098                 __be32 data;
11099
11100                 memcpy(&data, buf + i, 4);
11101                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11102
11103                 page_off = offset % tp->nvram_pagesize;
11104
11105                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11106
11107                 tw32(NVRAM_ADDR, phy_addr);
11108
11109                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11110
11111                 if ((page_off == 0) || (i == 0))
11112                         nvram_cmd |= NVRAM_CMD_FIRST;
11113                 if (page_off == (tp->nvram_pagesize - 4))
11114                         nvram_cmd |= NVRAM_CMD_LAST;
11115
11116                 if (i == (len - 4))
11117                         nvram_cmd |= NVRAM_CMD_LAST;
11118
11119                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
11120                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
11121                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
11122                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784) &&
11123                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) &&
11124                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) &&
11125                     (tp->nvram_jedecnum == JEDEC_ST) &&
11126                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11127
11128                         if ((ret = tg3_nvram_exec_cmd(tp,
11129                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11130                                 NVRAM_CMD_DONE)))
11131
11132                                 break;
11133                 }
11134                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11135                         /* We always do complete word writes to eeprom. */
11136                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11137                 }
11138
11139                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11140                         break;
11141         }
11142         return ret;
11143 }
11144
11145 /* offset and length are dword aligned */
11146 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11147 {
11148         int ret;
11149
11150         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11151                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11152                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11153                 udelay(40);
11154         }
11155
11156         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11157                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11158         }
11159         else {
11160                 u32 grc_mode;
11161
11162                 ret = tg3_nvram_lock(tp);
11163                 if (ret)
11164                         return ret;
11165
11166                 tg3_enable_nvram_access(tp);
11167                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11168                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
11169                         tw32(NVRAM_WRITE1, 0x406);
11170
11171                 grc_mode = tr32(GRC_MODE);
11172                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11173
11174                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11175                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11176
11177                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11178                                 buf);
11179                 }
11180                 else {
11181                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11182                                 buf);
11183                 }
11184
11185                 grc_mode = tr32(GRC_MODE);
11186                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11187
11188                 tg3_disable_nvram_access(tp);
11189                 tg3_nvram_unlock(tp);
11190         }
11191
11192         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11193                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11194                 udelay(40);
11195         }
11196
11197         return ret;
11198 }
11199
11200 struct subsys_tbl_ent {
11201         u16 subsys_vendor, subsys_devid;
11202         u32 phy_id;
11203 };
11204
11205 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
11206         /* Broadcom boards. */
11207         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
11208         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
11209         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
11210         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
11211         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
11212         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
11213         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
11214         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
11215         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
11216         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
11217         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
11218
11219         /* 3com boards. */
11220         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
11221         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
11222         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
11223         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
11224         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
11225
11226         /* DELL boards. */
11227         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
11228         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
11229         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
11230         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
11231
11232         /* Compaq boards. */
11233         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
11234         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
11235         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
11236         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
11237         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
11238
11239         /* IBM boards. */
11240         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
11241 };
11242
11243 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
11244 {
11245         int i;
11246
11247         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
11248                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
11249                      tp->pdev->subsystem_vendor) &&
11250                     (subsys_id_to_phy_id[i].subsys_devid ==
11251                      tp->pdev->subsystem_device))
11252                         return &subsys_id_to_phy_id[i];
11253         }
11254         return NULL;
11255 }
11256
11257 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
11258 {
11259         u32 val;
11260         u16 pmcsr;
11261
11262         /* On some early chips the SRAM cannot be accessed in D3hot state,
11263          * so need make sure we're in D0.
11264          */
11265         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
11266         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
11267         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
11268         msleep(1);
11269
11270         /* Make sure register accesses (indirect or otherwise)
11271          * will function correctly.
11272          */
11273         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11274                                tp->misc_host_ctrl);
11275
11276         /* The memory arbiter has to be enabled in order for SRAM accesses
11277          * to succeed.  Normally on powerup the tg3 chip firmware will make
11278          * sure it is enabled, but other entities such as system netboot
11279          * code might disable it.
11280          */
11281         val = tr32(MEMARB_MODE);
11282         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
11283
11284         tp->phy_id = PHY_ID_INVALID;
11285         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11286
11287         /* Assume an onboard device and WOL capable by default.  */
11288         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
11289
11290         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11291                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
11292                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11293                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11294                 }
11295                 val = tr32(VCPU_CFGSHDW);
11296                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
11297                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11298                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
11299                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
11300                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11301                 return;
11302         }
11303
11304         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
11305         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
11306                 u32 nic_cfg, led_cfg;
11307                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
11308                 int eeprom_phy_serdes = 0;
11309
11310                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
11311                 tp->nic_sram_data_cfg = nic_cfg;
11312
11313                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
11314                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
11315                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
11316                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
11317                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
11318                     (ver > 0) && (ver < 0x100))
11319                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
11320
11321                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11322                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
11323
11324                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
11325                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
11326                         eeprom_phy_serdes = 1;
11327
11328                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
11329                 if (nic_phy_id != 0) {
11330                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
11331                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
11332
11333                         eeprom_phy_id  = (id1 >> 16) << 10;
11334                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
11335                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
11336                 } else
11337                         eeprom_phy_id = 0;
11338
11339                 tp->phy_id = eeprom_phy_id;
11340                 if (eeprom_phy_serdes) {
11341                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
11342                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
11343                         else
11344                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11345                 }
11346
11347                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11348                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
11349                                     SHASTA_EXT_LED_MODE_MASK);
11350                 else
11351                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
11352
11353                 switch (led_cfg) {
11354                 default:
11355                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
11356                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11357                         break;
11358
11359                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
11360                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11361                         break;
11362
11363                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
11364                         tp->led_ctrl = LED_CTRL_MODE_MAC;
11365
11366                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
11367                          * read on some older 5700/5701 bootcode.
11368                          */
11369                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
11370                             ASIC_REV_5700 ||
11371                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
11372                             ASIC_REV_5701)
11373                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11374
11375                         break;
11376
11377                 case SHASTA_EXT_LED_SHARED:
11378                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
11379                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
11380                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
11381                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11382                                                  LED_CTRL_MODE_PHY_2);
11383                         break;
11384
11385                 case SHASTA_EXT_LED_MAC:
11386                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
11387                         break;
11388
11389                 case SHASTA_EXT_LED_COMBO:
11390                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
11391                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
11392                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
11393                                                  LED_CTRL_MODE_PHY_2);
11394                         break;
11395
11396                 }
11397
11398                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11399                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
11400                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
11401                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
11402
11403                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
11404                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
11405
11406                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
11407                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
11408                         if ((tp->pdev->subsystem_vendor ==
11409                              PCI_VENDOR_ID_ARIMA) &&
11410                             (tp->pdev->subsystem_device == 0x205a ||
11411                              tp->pdev->subsystem_device == 0x2063))
11412                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11413                 } else {
11414                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
11415                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
11416                 }
11417
11418                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
11419                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
11420                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
11421                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
11422                 }
11423                 if (nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE)
11424                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
11425                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
11426                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
11427                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
11428
11429                 if (tp->tg3_flags & TG3_FLAG_WOL_CAP &&
11430                     nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)
11431                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
11432
11433                 if (cfg2 & (1 << 17))
11434                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
11435
11436                 /* serdes signal pre-emphasis in register 0x590 set by */
11437                 /* bootcode if bit 18 is set */
11438                 if (cfg2 & (1 << 18))
11439                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
11440
11441                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11442                         u32 cfg3;
11443
11444                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
11445                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
11446                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
11447                 }
11448
11449                 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
11450                         tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
11451                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
11452                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
11453                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
11454                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
11455         }
11456 }
11457
11458 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
11459 {
11460         int i;
11461         u32 val;
11462
11463         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
11464         tw32(OTP_CTRL, cmd);
11465
11466         /* Wait for up to 1 ms for command to execute. */
11467         for (i = 0; i < 100; i++) {
11468                 val = tr32(OTP_STATUS);
11469                 if (val & OTP_STATUS_CMD_DONE)
11470                         break;
11471                 udelay(10);
11472         }
11473
11474         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
11475 }
11476
11477 /* Read the gphy configuration from the OTP region of the chip.  The gphy
11478  * configuration is a 32-bit value that straddles the alignment boundary.
11479  * We do two 32-bit reads and then shift and merge the results.
11480  */
11481 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
11482 {
11483         u32 bhalf_otp, thalf_otp;
11484
11485         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
11486
11487         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
11488                 return 0;
11489
11490         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
11491
11492         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11493                 return 0;
11494
11495         thalf_otp = tr32(OTP_READ_DATA);
11496
11497         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
11498
11499         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
11500                 return 0;
11501
11502         bhalf_otp = tr32(OTP_READ_DATA);
11503
11504         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
11505 }
11506
11507 static int __devinit tg3_phy_probe(struct tg3 *tp)
11508 {
11509         u32 hw_phy_id_1, hw_phy_id_2;
11510         u32 hw_phy_id, hw_phy_id_masked;
11511         int err;
11512
11513         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
11514                 return tg3_phy_init(tp);
11515
11516         /* Reading the PHY ID register can conflict with ASF
11517          * firwmare access to the PHY hardware.
11518          */
11519         err = 0;
11520         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11521             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
11522                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
11523         } else {
11524                 /* Now read the physical PHY_ID from the chip and verify
11525                  * that it is sane.  If it doesn't look good, we fall back
11526                  * to either the hard-coded table based PHY_ID and failing
11527                  * that the value found in the eeprom area.
11528                  */
11529                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
11530                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
11531
11532                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
11533                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
11534                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
11535
11536                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
11537         }
11538
11539         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
11540                 tp->phy_id = hw_phy_id;
11541                 if (hw_phy_id_masked == PHY_ID_BCM8002)
11542                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11543                 else
11544                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
11545         } else {
11546                 if (tp->phy_id != PHY_ID_INVALID) {
11547                         /* Do nothing, phy ID already set up in
11548                          * tg3_get_eeprom_hw_cfg().
11549                          */
11550                 } else {
11551                         struct subsys_tbl_ent *p;
11552
11553                         /* No eeprom signature?  Try the hardcoded
11554                          * subsys device table.
11555                          */
11556                         p = lookup_by_subsys(tp);
11557                         if (!p)
11558                                 return -ENODEV;
11559
11560                         tp->phy_id = p->phy_id;
11561                         if (!tp->phy_id ||
11562                             tp->phy_id == PHY_ID_BCM8002)
11563                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
11564                 }
11565         }
11566
11567         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
11568             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
11569             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
11570                 u32 bmsr, adv_reg, tg3_ctrl, mask;
11571
11572                 tg3_readphy(tp, MII_BMSR, &bmsr);
11573                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
11574                     (bmsr & BMSR_LSTATUS))
11575                         goto skip_phy_reset;
11576
11577                 err = tg3_phy_reset(tp);
11578                 if (err)
11579                         return err;
11580
11581                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
11582                            ADVERTISE_100HALF | ADVERTISE_100FULL |
11583                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
11584                 tg3_ctrl = 0;
11585                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
11586                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
11587                                     MII_TG3_CTRL_ADV_1000_FULL);
11588                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
11589                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
11590                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
11591                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
11592                 }
11593
11594                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11595                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11596                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
11597                 if (!tg3_copper_is_advertising_all(tp, mask)) {
11598                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11599
11600                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11601                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11602
11603                         tg3_writephy(tp, MII_BMCR,
11604                                      BMCR_ANENABLE | BMCR_ANRESTART);
11605                 }
11606                 tg3_phy_set_wirespeed(tp);
11607
11608                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
11609                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
11610                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
11611         }
11612
11613 skip_phy_reset:
11614         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
11615                 err = tg3_init_5401phy_dsp(tp);
11616                 if (err)
11617                         return err;
11618         }
11619
11620         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
11621                 err = tg3_init_5401phy_dsp(tp);
11622         }
11623
11624         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
11625                 tp->link_config.advertising =
11626                         (ADVERTISED_1000baseT_Half |
11627                          ADVERTISED_1000baseT_Full |
11628                          ADVERTISED_Autoneg |
11629                          ADVERTISED_FIBRE);
11630         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
11631                 tp->link_config.advertising &=
11632                         ~(ADVERTISED_1000baseT_Half |
11633                           ADVERTISED_1000baseT_Full);
11634
11635         return err;
11636 }
11637
11638 static void __devinit tg3_read_partno(struct tg3 *tp)
11639 {
11640         unsigned char vpd_data[256];
11641         unsigned int i;
11642         u32 magic;
11643
11644         if (tg3_nvram_read_swab(tp, 0x0, &magic))
11645                 goto out_not_found;
11646
11647         if (magic == TG3_EEPROM_MAGIC) {
11648                 for (i = 0; i < 256; i += 4) {
11649                         u32 tmp;
11650
11651                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
11652                                 goto out_not_found;
11653
11654                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
11655                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
11656                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
11657                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
11658                 }
11659         } else {
11660                 int vpd_cap;
11661
11662                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
11663                 for (i = 0; i < 256; i += 4) {
11664                         u32 tmp, j = 0;
11665                         __le32 v;
11666                         u16 tmp16;
11667
11668                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
11669                                               i);
11670                         while (j++ < 100) {
11671                                 pci_read_config_word(tp->pdev, vpd_cap +
11672                                                      PCI_VPD_ADDR, &tmp16);
11673                                 if (tmp16 & 0x8000)
11674                                         break;
11675                                 msleep(1);
11676                         }
11677                         if (!(tmp16 & 0x8000))
11678                                 goto out_not_found;
11679
11680                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
11681                                               &tmp);
11682                         v = cpu_to_le32(tmp);
11683                         memcpy(&vpd_data[i], &v, 4);
11684                 }
11685         }
11686
11687         /* Now parse and find the part number. */
11688         for (i = 0; i < 254; ) {
11689                 unsigned char val = vpd_data[i];
11690                 unsigned int block_end;
11691
11692                 if (val == 0x82 || val == 0x91) {
11693                         i = (i + 3 +
11694                              (vpd_data[i + 1] +
11695                               (vpd_data[i + 2] << 8)));
11696                         continue;
11697                 }
11698
11699                 if (val != 0x90)
11700                         goto out_not_found;
11701
11702                 block_end = (i + 3 +
11703                              (vpd_data[i + 1] +
11704                               (vpd_data[i + 2] << 8)));
11705                 i += 3;
11706
11707                 if (block_end > 256)
11708                         goto out_not_found;
11709
11710                 while (i < (block_end - 2)) {
11711                         if (vpd_data[i + 0] == 'P' &&
11712                             vpd_data[i + 1] == 'N') {
11713                                 int partno_len = vpd_data[i + 2];
11714
11715                                 i += 3;
11716                                 if (partno_len > 24 || (partno_len + i) > 256)
11717                                         goto out_not_found;
11718
11719                                 memcpy(tp->board_part_number,
11720                                        &vpd_data[i], partno_len);
11721
11722                                 /* Success. */
11723                                 return;
11724                         }
11725                         i += 3 + vpd_data[i + 2];
11726                 }
11727
11728                 /* Part number not found. */
11729                 goto out_not_found;
11730         }
11731
11732 out_not_found:
11733         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11734                 strcpy(tp->board_part_number, "BCM95906");
11735         else
11736                 strcpy(tp->board_part_number, "none");
11737 }
11738
11739 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
11740 {
11741         u32 val;
11742
11743         if (tg3_nvram_read_swab(tp, offset, &val) ||
11744             (val & 0xfc000000) != 0x0c000000 ||
11745             tg3_nvram_read_swab(tp, offset + 4, &val) ||
11746             val != 0)
11747                 return 0;
11748
11749         return 1;
11750 }
11751
11752 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
11753 {
11754         u32 val, offset, start;
11755         u32 ver_offset;
11756         int i, bcnt;
11757
11758         if (tg3_nvram_read_swab(tp, 0, &val))
11759                 return;
11760
11761         if (val != TG3_EEPROM_MAGIC)
11762                 return;
11763
11764         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
11765             tg3_nvram_read_swab(tp, 0x4, &start))
11766                 return;
11767
11768         offset = tg3_nvram_logical_addr(tp, offset);
11769
11770         if (!tg3_fw_img_is_valid(tp, offset) ||
11771             tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
11772                 return;
11773
11774         offset = offset + ver_offset - start;
11775         for (i = 0; i < 16; i += 4) {
11776                 __le32 v;
11777                 if (tg3_nvram_read_le(tp, offset + i, &v))
11778                         return;
11779
11780                 memcpy(tp->fw_ver + i, &v, 4);
11781         }
11782
11783         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
11784              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
11785                 return;
11786
11787         for (offset = TG3_NVM_DIR_START;
11788              offset < TG3_NVM_DIR_END;
11789              offset += TG3_NVM_DIRENT_SIZE) {
11790                 if (tg3_nvram_read_swab(tp, offset, &val))
11791                         return;
11792
11793                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
11794                         break;
11795         }
11796
11797         if (offset == TG3_NVM_DIR_END)
11798                 return;
11799
11800         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11801                 start = 0x08000000;
11802         else if (tg3_nvram_read_swab(tp, offset - 4, &start))
11803                 return;
11804
11805         if (tg3_nvram_read_swab(tp, offset + 4, &offset) ||
11806             !tg3_fw_img_is_valid(tp, offset) ||
11807             tg3_nvram_read_swab(tp, offset + 8, &val))
11808                 return;
11809
11810         offset += val - start;
11811
11812         bcnt = strlen(tp->fw_ver);
11813
11814         tp->fw_ver[bcnt++] = ',';
11815         tp->fw_ver[bcnt++] = ' ';
11816
11817         for (i = 0; i < 4; i++) {
11818                 __le32 v;
11819                 if (tg3_nvram_read_le(tp, offset, &v))
11820                         return;
11821
11822                 offset += sizeof(v);
11823
11824                 if (bcnt > TG3_VER_SIZE - sizeof(v)) {
11825                         memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt);
11826                         break;
11827                 }
11828
11829                 memcpy(&tp->fw_ver[bcnt], &v, sizeof(v));
11830                 bcnt += sizeof(v);
11831         }
11832
11833         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
11834 }
11835
11836 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
11837
11838 static int __devinit tg3_get_invariants(struct tg3 *tp)
11839 {
11840         static struct pci_device_id write_reorder_chipsets[] = {
11841                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11842                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
11843                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
11844                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
11845                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
11846                              PCI_DEVICE_ID_VIA_8385_0) },
11847                 { },
11848         };
11849         u32 misc_ctrl_reg;
11850         u32 cacheline_sz_reg;
11851         u32 pci_state_reg, grc_misc_cfg;
11852         u32 val;
11853         u16 pci_cmd;
11854         int err, pcie_cap;
11855
11856         /* Force memory write invalidate off.  If we leave it on,
11857          * then on 5700_BX chips we have to enable a workaround.
11858          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
11859          * to match the cacheline size.  The Broadcom driver have this
11860          * workaround but turns MWI off all the times so never uses
11861          * it.  This seems to suggest that the workaround is insufficient.
11862          */
11863         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11864         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
11865         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11866
11867         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
11868          * has the register indirect write enable bit set before
11869          * we try to access any of the MMIO registers.  It is also
11870          * critical that the PCI-X hw workaround situation is decided
11871          * before that as well.
11872          */
11873         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
11874                               &misc_ctrl_reg);
11875
11876         tp->pci_chip_rev_id = (misc_ctrl_reg >>
11877                                MISC_HOST_CTRL_CHIPREV_SHIFT);
11878         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
11879                 u32 prod_id_asic_rev;
11880
11881                 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
11882                                       &prod_id_asic_rev);
11883                 tp->pci_chip_rev_id = prod_id_asic_rev & PROD_ID_ASIC_REV_MASK;
11884         }
11885
11886         /* Wrong chip ID in 5752 A0. This code can be removed later
11887          * as A0 is not in production.
11888          */
11889         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
11890                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
11891
11892         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
11893          * we need to disable memory and use config. cycles
11894          * only to access all registers. The 5702/03 chips
11895          * can mistakenly decode the special cycles from the
11896          * ICH chipsets as memory write cycles, causing corruption
11897          * of register and memory space. Only certain ICH bridges
11898          * will drive special cycles with non-zero data during the
11899          * address phase which can fall within the 5703's address
11900          * range. This is not an ICH bug as the PCI spec allows
11901          * non-zero address during special cycles. However, only
11902          * these ICH bridges are known to drive non-zero addresses
11903          * during special cycles.
11904          *
11905          * Since special cycles do not cross PCI bridges, we only
11906          * enable this workaround if the 5703 is on the secondary
11907          * bus of these ICH bridges.
11908          */
11909         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
11910             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
11911                 static struct tg3_dev_id {
11912                         u32     vendor;
11913                         u32     device;
11914                         u32     rev;
11915                 } ich_chipsets[] = {
11916                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
11917                           PCI_ANY_ID },
11918                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
11919                           PCI_ANY_ID },
11920                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
11921                           0xa },
11922                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
11923                           PCI_ANY_ID },
11924                         { },
11925                 };
11926                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
11927                 struct pci_dev *bridge = NULL;
11928
11929                 while (pci_id->vendor != 0) {
11930                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
11931                                                 bridge);
11932                         if (!bridge) {
11933                                 pci_id++;
11934                                 continue;
11935                         }
11936                         if (pci_id->rev != PCI_ANY_ID) {
11937                                 if (bridge->revision > pci_id->rev)
11938                                         continue;
11939                         }
11940                         if (bridge->subordinate &&
11941                             (bridge->subordinate->number ==
11942                              tp->pdev->bus->number)) {
11943
11944                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
11945                                 pci_dev_put(bridge);
11946                                 break;
11947                         }
11948                 }
11949         }
11950
11951         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
11952                 static struct tg3_dev_id {
11953                         u32     vendor;
11954                         u32     device;
11955                 } bridge_chipsets[] = {
11956                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
11957                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
11958                         { },
11959                 };
11960                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
11961                 struct pci_dev *bridge = NULL;
11962
11963                 while (pci_id->vendor != 0) {
11964                         bridge = pci_get_device(pci_id->vendor,
11965                                                 pci_id->device,
11966                                                 bridge);
11967                         if (!bridge) {
11968                                 pci_id++;
11969                                 continue;
11970                         }
11971                         if (bridge->subordinate &&
11972                             (bridge->subordinate->number <=
11973                              tp->pdev->bus->number) &&
11974                             (bridge->subordinate->subordinate >=
11975                              tp->pdev->bus->number)) {
11976                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
11977                                 pci_dev_put(bridge);
11978                                 break;
11979                         }
11980                 }
11981         }
11982
11983         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
11984          * DMA addresses > 40-bit. This bridge may have other additional
11985          * 57xx devices behind it in some 4-port NIC designs for example.
11986          * Any tg3 device found behind the bridge will also need the 40-bit
11987          * DMA workaround.
11988          */
11989         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
11990             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11991                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
11992                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
11993                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
11994         }
11995         else {
11996                 struct pci_dev *bridge = NULL;
11997
11998                 do {
11999                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12000                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12001                                                 bridge);
12002                         if (bridge && bridge->subordinate &&
12003                             (bridge->subordinate->number <=
12004                              tp->pdev->bus->number) &&
12005                             (bridge->subordinate->subordinate >=
12006                              tp->pdev->bus->number)) {
12007                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12008                                 pci_dev_put(bridge);
12009                                 break;
12010                         }
12011                 } while (bridge);
12012         }
12013
12014         /* Initialize misc host control in PCI block. */
12015         tp->misc_host_ctrl |= (misc_ctrl_reg &
12016                                MISC_HOST_CTRL_CHIPREV);
12017         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12018                                tp->misc_host_ctrl);
12019
12020         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12021                               &cacheline_sz_reg);
12022
12023         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
12024         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
12025         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
12026         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
12027
12028         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12029             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
12030                 tp->pdev_peer = tg3_find_peer(tp);
12031
12032         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12034             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12037             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12038             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12039             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
12040             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12041                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
12042
12043         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
12044             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12045                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
12046
12047         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
12048                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
12049                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
12050                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
12051                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
12052                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
12053                      tp->pdev_peer == tp->pdev))
12054                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
12055
12056                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12057                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12058                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12059                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12060                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12061                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12062                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
12063                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
12064                 } else {
12065                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
12066                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12067                                 ASIC_REV_5750 &&
12068                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
12069                                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
12070                 }
12071         }
12072
12073         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12074              (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12075                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
12076
12077         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
12078         if (pcie_cap != 0) {
12079                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
12080
12081                 pcie_set_readrq(tp->pdev, 4096);
12082
12083                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12084                         u16 lnkctl;
12085
12086                         pci_read_config_word(tp->pdev,
12087                                              pcie_cap + PCI_EXP_LNKCTL,
12088                                              &lnkctl);
12089                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
12090                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
12091                 }
12092         }
12093
12094         /* If we have an AMD 762 or VIA K8T800 chipset, write
12095          * reordering to the mailbox registers done by the host
12096          * controller can cause major troubles.  We read back from
12097          * every mailbox register write to force the writes to be
12098          * posted to the chip in order.
12099          */
12100         if (pci_dev_present(write_reorder_chipsets) &&
12101             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12102                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
12103
12104         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12105             tp->pci_lat_timer < 64) {
12106                 tp->pci_lat_timer = 64;
12107
12108                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
12109                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
12110                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
12111                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
12112
12113                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
12114                                        cacheline_sz_reg);
12115         }
12116
12117         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
12118             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12119                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
12120                 if (!tp->pcix_cap) {
12121                         printk(KERN_ERR PFX "Cannot find PCI-X "
12122                                             "capability, aborting.\n");
12123                         return -EIO;
12124                 }
12125         }
12126
12127         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12128                               &pci_state_reg);
12129
12130         if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
12131                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
12132
12133                 /* If this is a 5700 BX chipset, and we are in PCI-X
12134                  * mode, enable register write workaround.
12135                  *
12136                  * The workaround is to use indirect register accesses
12137                  * for all chip writes not to mailbox registers.
12138                  */
12139                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
12140                         u32 pm_reg;
12141
12142                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12143
12144                         /* The chip can have it's power management PCI config
12145                          * space registers clobbered due to this bug.
12146                          * So explicitly force the chip into D0 here.
12147                          */
12148                         pci_read_config_dword(tp->pdev,
12149                                               tp->pm_cap + PCI_PM_CTRL,
12150                                               &pm_reg);
12151                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
12152                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
12153                         pci_write_config_dword(tp->pdev,
12154                                                tp->pm_cap + PCI_PM_CTRL,
12155                                                pm_reg);
12156
12157                         /* Also, force SERR#/PERR# in PCI command. */
12158                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12159                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
12160                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12161                 }
12162         }
12163
12164         /* 5700 BX chips need to have their TX producer index mailboxes
12165          * written twice to workaround a bug.
12166          */
12167         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
12168                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
12169
12170         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
12171                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
12172         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
12173                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
12174
12175         /* Chip-specific fixup from Broadcom driver */
12176         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
12177             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
12178                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
12179                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
12180         }
12181
12182         /* Default fast path register access methods */
12183         tp->read32 = tg3_read32;
12184         tp->write32 = tg3_write32;
12185         tp->read32_mbox = tg3_read32;
12186         tp->write32_mbox = tg3_write32;
12187         tp->write32_tx_mbox = tg3_write32;
12188         tp->write32_rx_mbox = tg3_write32;
12189
12190         /* Various workaround register access methods */
12191         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
12192                 tp->write32 = tg3_write_indirect_reg32;
12193         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
12194                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12195                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
12196                 /*
12197                  * Back to back register writes can cause problems on these
12198                  * chips, the workaround is to read back all reg writes
12199                  * except those to mailbox regs.
12200                  *
12201                  * See tg3_write_indirect_reg32().
12202                  */
12203                 tp->write32 = tg3_write_flush_reg32;
12204         }
12205
12206
12207         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
12208             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
12209                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
12210                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
12211                         tp->write32_rx_mbox = tg3_write_flush_reg32;
12212         }
12213
12214         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
12215                 tp->read32 = tg3_read_indirect_reg32;
12216                 tp->write32 = tg3_write_indirect_reg32;
12217                 tp->read32_mbox = tg3_read_indirect_mbox;
12218                 tp->write32_mbox = tg3_write_indirect_mbox;
12219                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
12220                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
12221
12222                 iounmap(tp->regs);
12223                 tp->regs = NULL;
12224
12225                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12226                 pci_cmd &= ~PCI_COMMAND_MEMORY;
12227                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12228         }
12229         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12230                 tp->read32_mbox = tg3_read32_mbox_5906;
12231                 tp->write32_mbox = tg3_write32_mbox_5906;
12232                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
12233                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
12234         }
12235
12236         if (tp->write32 == tg3_write_indirect_reg32 ||
12237             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12238              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12239               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
12240                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
12241
12242         /* Get eeprom hw config before calling tg3_set_power_state().
12243          * In particular, the TG3_FLG2_IS_NIC flag must be
12244          * determined before calling tg3_set_power_state() so that
12245          * we know whether or not to switch out of Vaux power.
12246          * When the flag is set, it means that GPIO1 is used for eeprom
12247          * write protect and also implies that it is a LOM where GPIOs
12248          * are not used to switch power.
12249          */
12250         tg3_get_eeprom_hw_cfg(tp);
12251
12252         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
12253                 /* Allow reads and writes to the
12254                  * APE register and memory space.
12255                  */
12256                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
12257                                  PCISTATE_ALLOW_APE_SHMEM_WR;
12258                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
12259                                        pci_state_reg);
12260         }
12261
12262         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12263             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12264             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
12265                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
12266
12267                 if (tp->pci_chip_rev_id == CHIPREV_ID_5784_A0 ||
12268                     tp->pci_chip_rev_id == CHIPREV_ID_5784_A1 ||
12269                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A0 ||
12270                     tp->pci_chip_rev_id == CHIPREV_ID_5761_A1)
12271                         tp->tg3_flags3 |= TG3_FLG3_5761_5784_AX_FIXES;
12272         }
12273
12274         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
12275          * GPIO1 driven high will bring 5700's external PHY out of reset.
12276          * It is also used as eeprom write protect on LOMs.
12277          */
12278         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
12279         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12280             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
12281                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
12282                                        GRC_LCLCTRL_GPIO_OUTPUT1);
12283         /* Unused GPIO3 must be driven as output on 5752 because there
12284          * are no pull-up resistors on unused GPIO pins.
12285          */
12286         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
12287                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
12288
12289         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12290                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12291
12292         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
12293                 /* Turn off the debug UART. */
12294                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
12295                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
12296                         /* Keep VMain power. */
12297                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
12298                                               GRC_LCLCTRL_GPIO_OUTPUT0;
12299         }
12300
12301         /* Force the chip into D0. */
12302         err = tg3_set_power_state(tp, PCI_D0);
12303         if (err) {
12304                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
12305                        pci_name(tp->pdev));
12306                 return err;
12307         }
12308
12309         /* 5700 B0 chips do not support checksumming correctly due
12310          * to hardware bugs.
12311          */
12312         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
12313                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
12314
12315         /* Derive initial jumbo mode from MTU assigned in
12316          * ether_setup() via the alloc_etherdev() call
12317          */
12318         if (tp->dev->mtu > ETH_DATA_LEN &&
12319             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
12320                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
12321
12322         /* Determine WakeOnLan speed to use. */
12323         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12324             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12325             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
12326             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
12327                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
12328         } else {
12329                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
12330         }
12331
12332         /* A few boards don't want Ethernet@WireSpeed phy feature */
12333         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
12334             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
12335              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
12336              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
12337             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
12338             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
12339                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
12340
12341         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
12342             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
12343                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
12344         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
12345                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
12346
12347         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
12348                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12349                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12350                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12351                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
12352                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
12353                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
12354                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
12355                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
12356                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
12357                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906 &&
12358                            GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
12359                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
12360         }
12361
12362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12363             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
12364                 tp->phy_otp = tg3_read_otp_phycfg(tp);
12365                 if (tp->phy_otp == 0)
12366                         tp->phy_otp = TG3_OTP_DEFAULT;
12367         }
12368
12369         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
12370                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
12371         else
12372                 tp->mi_mode = MAC_MI_MODE_BASE;
12373
12374         tp->coalesce_mode = 0;
12375         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
12376             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
12377                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
12378
12379         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12380                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12381
12382         err = tg3_mdio_init(tp);
12383         if (err)
12384                 return err;
12385
12386         /* Initialize data/descriptor byte/word swapping. */
12387         val = tr32(GRC_MODE);
12388         val &= GRC_MODE_HOST_STACKUP;
12389         tw32(GRC_MODE, val | tp->grc_mode);
12390
12391         tg3_switch_clocks(tp);
12392
12393         /* Clear this out for sanity. */
12394         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
12395
12396         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
12397                               &pci_state_reg);
12398         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
12399             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
12400                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
12401
12402                 if (chiprevid == CHIPREV_ID_5701_A0 ||
12403                     chiprevid == CHIPREV_ID_5701_B0 ||
12404                     chiprevid == CHIPREV_ID_5701_B2 ||
12405                     chiprevid == CHIPREV_ID_5701_B5) {
12406                         void __iomem *sram_base;
12407
12408                         /* Write some dummy words into the SRAM status block
12409                          * area, see if it reads back correctly.  If the return
12410                          * value is bad, force enable the PCIX workaround.
12411                          */
12412                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
12413
12414                         writel(0x00000000, sram_base);
12415                         writel(0x00000000, sram_base + 4);
12416                         writel(0xffffffff, sram_base + 4);
12417                         if (readl(sram_base) != 0x00000000)
12418                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
12419                 }
12420         }
12421
12422         udelay(50);
12423         tg3_nvram_init(tp);
12424
12425         grc_misc_cfg = tr32(GRC_MISC_CFG);
12426         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
12427
12428         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12429             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
12430              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
12431                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
12432
12433         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
12434             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
12435                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
12436         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
12437                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
12438                                       HOSTCC_MODE_CLRTICK_TXBD);
12439
12440                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
12441                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12442                                        tp->misc_host_ctrl);
12443         }
12444
12445         /* these are limited to 10/100 only */
12446         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
12447              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
12448             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
12449              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12450              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
12451               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
12452               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
12453             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
12454              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
12455               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
12456               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
12457             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12458                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
12459
12460         err = tg3_phy_probe(tp);
12461         if (err) {
12462                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
12463                        pci_name(tp->pdev), err);
12464                 /* ... but do not return immediately ... */
12465                 tg3_mdio_fini(tp);
12466         }
12467
12468         tg3_read_partno(tp);
12469         tg3_read_fw_ver(tp);
12470
12471         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
12472                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12473         } else {
12474                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12475                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
12476                 else
12477                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
12478         }
12479
12480         /* 5700 {AX,BX} chips have a broken status block link
12481          * change bit implementation, so we must use the
12482          * status register in those cases.
12483          */
12484         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
12485                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
12486         else
12487                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
12488
12489         /* The led_ctrl is set during tg3_phy_probe, here we might
12490          * have to force the link status polling mechanism based
12491          * upon subsystem IDs.
12492          */
12493         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
12494             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12495             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
12496                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
12497                                   TG3_FLAG_USE_LINKCHG_REG);
12498         }
12499
12500         /* For all SERDES we poll the MAC status register. */
12501         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
12502                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
12503         else
12504                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
12505
12506         /* All chips before 5787 can get confused if TX buffers
12507          * straddle the 4GB address boundary in some cases.
12508          */
12509         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12510             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12511             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12512             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12513             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12514             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12515                 tp->dev->hard_start_xmit = tg3_start_xmit;
12516         else
12517                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
12518
12519         tp->rx_offset = 2;
12520         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
12521             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
12522                 tp->rx_offset = 0;
12523
12524         tp->rx_std_max_post = TG3_RX_RING_SIZE;
12525
12526         /* Increment the rx prod index on the rx std ring by at most
12527          * 8 for these chips to workaround hw errata.
12528          */
12529         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12530             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
12531             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
12532                 tp->rx_std_max_post = 8;
12533
12534         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
12535                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
12536                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
12537
12538         return err;
12539 }
12540
12541 #ifdef CONFIG_SPARC
12542 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
12543 {
12544         struct net_device *dev = tp->dev;
12545         struct pci_dev *pdev = tp->pdev;
12546         struct device_node *dp = pci_device_to_OF_node(pdev);
12547         const unsigned char *addr;
12548         int len;
12549
12550         addr = of_get_property(dp, "local-mac-address", &len);
12551         if (addr && len == 6) {
12552                 memcpy(dev->dev_addr, addr, 6);
12553                 memcpy(dev->perm_addr, dev->dev_addr, 6);
12554                 return 0;
12555         }
12556         return -ENODEV;
12557 }
12558
12559 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
12560 {
12561         struct net_device *dev = tp->dev;
12562
12563         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
12564         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
12565         return 0;
12566 }
12567 #endif
12568
12569 static int __devinit tg3_get_device_address(struct tg3 *tp)
12570 {
12571         struct net_device *dev = tp->dev;
12572         u32 hi, lo, mac_offset;
12573         int addr_ok = 0;
12574
12575 #ifdef CONFIG_SPARC
12576         if (!tg3_get_macaddr_sparc(tp))
12577                 return 0;
12578 #endif
12579
12580         mac_offset = 0x7c;
12581         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
12582             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
12583                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
12584                         mac_offset = 0xcc;
12585                 if (tg3_nvram_lock(tp))
12586                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
12587                 else
12588                         tg3_nvram_unlock(tp);
12589         }
12590         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12591                 mac_offset = 0x10;
12592
12593         /* First try to get it from MAC address mailbox. */
12594         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
12595         if ((hi >> 16) == 0x484b) {
12596                 dev->dev_addr[0] = (hi >>  8) & 0xff;
12597                 dev->dev_addr[1] = (hi >>  0) & 0xff;
12598
12599                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
12600                 dev->dev_addr[2] = (lo >> 24) & 0xff;
12601                 dev->dev_addr[3] = (lo >> 16) & 0xff;
12602                 dev->dev_addr[4] = (lo >>  8) & 0xff;
12603                 dev->dev_addr[5] = (lo >>  0) & 0xff;
12604
12605                 /* Some old bootcode may report a 0 MAC address in SRAM */
12606                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
12607         }
12608         if (!addr_ok) {
12609                 /* Next, try NVRAM. */
12610                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
12611                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
12612                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
12613                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
12614                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
12615                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
12616                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
12617                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
12618                 }
12619                 /* Finally just fetch it out of the MAC control regs. */
12620                 else {
12621                         hi = tr32(MAC_ADDR_0_HIGH);
12622                         lo = tr32(MAC_ADDR_0_LOW);
12623
12624                         dev->dev_addr[5] = lo & 0xff;
12625                         dev->dev_addr[4] = (lo >> 8) & 0xff;
12626                         dev->dev_addr[3] = (lo >> 16) & 0xff;
12627                         dev->dev_addr[2] = (lo >> 24) & 0xff;
12628                         dev->dev_addr[1] = hi & 0xff;
12629                         dev->dev_addr[0] = (hi >> 8) & 0xff;
12630                 }
12631         }
12632
12633         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
12634 #ifdef CONFIG_SPARC
12635                 if (!tg3_get_default_macaddr_sparc(tp))
12636                         return 0;
12637 #endif
12638                 return -EINVAL;
12639         }
12640         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
12641         return 0;
12642 }
12643
12644 #define BOUNDARY_SINGLE_CACHELINE       1
12645 #define BOUNDARY_MULTI_CACHELINE        2
12646
12647 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
12648 {
12649         int cacheline_size;
12650         u8 byte;
12651         int goal;
12652
12653         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
12654         if (byte == 0)
12655                 cacheline_size = 1024;
12656         else
12657                 cacheline_size = (int) byte * 4;
12658
12659         /* On 5703 and later chips, the boundary bits have no
12660          * effect.
12661          */
12662         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12663             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
12664             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
12665                 goto out;
12666
12667 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
12668         goal = BOUNDARY_MULTI_CACHELINE;
12669 #else
12670 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
12671         goal = BOUNDARY_SINGLE_CACHELINE;
12672 #else
12673         goal = 0;
12674 #endif
12675 #endif
12676
12677         if (!goal)
12678                 goto out;
12679
12680         /* PCI controllers on most RISC systems tend to disconnect
12681          * when a device tries to burst across a cache-line boundary.
12682          * Therefore, letting tg3 do so just wastes PCI bandwidth.
12683          *
12684          * Unfortunately, for PCI-E there are only limited
12685          * write-side controls for this, and thus for reads
12686          * we will still get the disconnects.  We'll also waste
12687          * these PCI cycles for both read and write for chips
12688          * other than 5700 and 5701 which do not implement the
12689          * boundary bits.
12690          */
12691         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
12692             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
12693                 switch (cacheline_size) {
12694                 case 16:
12695                 case 32:
12696                 case 64:
12697                 case 128:
12698                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12699                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
12700                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
12701                         } else {
12702                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12703                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12704                         }
12705                         break;
12706
12707                 case 256:
12708                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
12709                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
12710                         break;
12711
12712                 default:
12713                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
12714                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
12715                         break;
12716                 }
12717         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12718                 switch (cacheline_size) {
12719                 case 16:
12720                 case 32:
12721                 case 64:
12722                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12723                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12724                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
12725                                 break;
12726                         }
12727                         /* fallthrough */
12728                 case 128:
12729                 default:
12730                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
12731                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
12732                         break;
12733                 }
12734         } else {
12735                 switch (cacheline_size) {
12736                 case 16:
12737                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12738                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
12739                                         DMA_RWCTRL_WRITE_BNDRY_16);
12740                                 break;
12741                         }
12742                         /* fallthrough */
12743                 case 32:
12744                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12745                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
12746                                         DMA_RWCTRL_WRITE_BNDRY_32);
12747                                 break;
12748                         }
12749                         /* fallthrough */
12750                 case 64:
12751                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12752                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
12753                                         DMA_RWCTRL_WRITE_BNDRY_64);
12754                                 break;
12755                         }
12756                         /* fallthrough */
12757                 case 128:
12758                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
12759                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
12760                                         DMA_RWCTRL_WRITE_BNDRY_128);
12761                                 break;
12762                         }
12763                         /* fallthrough */
12764                 case 256:
12765                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
12766                                 DMA_RWCTRL_WRITE_BNDRY_256);
12767                         break;
12768                 case 512:
12769                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
12770                                 DMA_RWCTRL_WRITE_BNDRY_512);
12771                         break;
12772                 case 1024:
12773                 default:
12774                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
12775                                 DMA_RWCTRL_WRITE_BNDRY_1024);
12776                         break;
12777                 }
12778         }
12779
12780 out:
12781         return val;
12782 }
12783
12784 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
12785 {
12786         struct tg3_internal_buffer_desc test_desc;
12787         u32 sram_dma_descs;
12788         int i, ret;
12789
12790         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
12791
12792         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
12793         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
12794         tw32(RDMAC_STATUS, 0);
12795         tw32(WDMAC_STATUS, 0);
12796
12797         tw32(BUFMGR_MODE, 0);
12798         tw32(FTQ_RESET, 0);
12799
12800         test_desc.addr_hi = ((u64) buf_dma) >> 32;
12801         test_desc.addr_lo = buf_dma & 0xffffffff;
12802         test_desc.nic_mbuf = 0x00002100;
12803         test_desc.len = size;
12804
12805         /*
12806          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
12807          * the *second* time the tg3 driver was getting loaded after an
12808          * initial scan.
12809          *
12810          * Broadcom tells me:
12811          *   ...the DMA engine is connected to the GRC block and a DMA
12812          *   reset may affect the GRC block in some unpredictable way...
12813          *   The behavior of resets to individual blocks has not been tested.
12814          *
12815          * Broadcom noted the GRC reset will also reset all sub-components.
12816          */
12817         if (to_device) {
12818                 test_desc.cqid_sqid = (13 << 8) | 2;
12819
12820                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
12821                 udelay(40);
12822         } else {
12823                 test_desc.cqid_sqid = (16 << 8) | 7;
12824
12825                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
12826                 udelay(40);
12827         }
12828         test_desc.flags = 0x00000005;
12829
12830         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
12831                 u32 val;
12832
12833                 val = *(((u32 *)&test_desc) + i);
12834                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
12835                                        sram_dma_descs + (i * sizeof(u32)));
12836                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
12837         }
12838         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
12839
12840         if (to_device) {
12841                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
12842         } else {
12843                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
12844         }
12845
12846         ret = -ENODEV;
12847         for (i = 0; i < 40; i++) {
12848                 u32 val;
12849
12850                 if (to_device)
12851                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
12852                 else
12853                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
12854                 if ((val & 0xffff) == sram_dma_descs) {
12855                         ret = 0;
12856                         break;
12857                 }
12858
12859                 udelay(100);
12860         }
12861
12862         return ret;
12863 }
12864
12865 #define TEST_BUFFER_SIZE        0x2000
12866
12867 static int __devinit tg3_test_dma(struct tg3 *tp)
12868 {
12869         dma_addr_t buf_dma;
12870         u32 *buf, saved_dma_rwctrl;
12871         int ret;
12872
12873         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
12874         if (!buf) {
12875                 ret = -ENOMEM;
12876                 goto out_nofree;
12877         }
12878
12879         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
12880                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
12881
12882         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
12883
12884         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12885                 /* DMA read watermark not used on PCIE */
12886                 tp->dma_rwctrl |= 0x00180000;
12887         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
12888                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
12889                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
12890                         tp->dma_rwctrl |= 0x003f0000;
12891                 else
12892                         tp->dma_rwctrl |= 0x003f000f;
12893         } else {
12894                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12895                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
12896                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
12897                         u32 read_water = 0x7;
12898
12899                         /* If the 5704 is behind the EPB bridge, we can
12900                          * do the less restrictive ONE_DMA workaround for
12901                          * better performance.
12902                          */
12903                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
12904                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12905                                 tp->dma_rwctrl |= 0x8000;
12906                         else if (ccval == 0x6 || ccval == 0x7)
12907                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
12908
12909                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
12910                                 read_water = 4;
12911                         /* Set bit 23 to enable PCIX hw bug fix */
12912                         tp->dma_rwctrl |=
12913                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
12914                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
12915                                 (1 << 23);
12916                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
12917                         /* 5780 always in PCIX mode */
12918                         tp->dma_rwctrl |= 0x00144000;
12919                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12920                         /* 5714 always in PCIX mode */
12921                         tp->dma_rwctrl |= 0x00148000;
12922                 } else {
12923                         tp->dma_rwctrl |= 0x001b000f;
12924                 }
12925         }
12926
12927         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
12928             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
12929                 tp->dma_rwctrl &= 0xfffffff0;
12930
12931         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12932             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
12933                 /* Remove this if it causes problems for some boards. */
12934                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
12935
12936                 /* On 5700/5701 chips, we need to set this bit.
12937                  * Otherwise the chip will issue cacheline transactions
12938                  * to streamable DMA memory with not all the byte
12939                  * enables turned on.  This is an error on several
12940                  * RISC PCI controllers, in particular sparc64.
12941                  *
12942                  * On 5703/5704 chips, this bit has been reassigned
12943                  * a different meaning.  In particular, it is used
12944                  * on those chips to enable a PCI-X workaround.
12945                  */
12946                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
12947         }
12948
12949         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12950
12951 #if 0
12952         /* Unneeded, already done by tg3_get_invariants.  */
12953         tg3_switch_clocks(tp);
12954 #endif
12955
12956         ret = 0;
12957         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
12958             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
12959                 goto out;
12960
12961         /* It is best to perform DMA test with maximum write burst size
12962          * to expose the 5700/5701 write DMA bug.
12963          */
12964         saved_dma_rwctrl = tp->dma_rwctrl;
12965         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
12966         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
12967
12968         while (1) {
12969                 u32 *p = buf, i;
12970
12971                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
12972                         p[i] = i;
12973
12974                 /* Send the buffer to the chip. */
12975                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
12976                 if (ret) {
12977                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
12978                         break;
12979                 }
12980
12981 #if 0
12982                 /* validate data reached card RAM correctly. */
12983                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
12984                         u32 val;
12985                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
12986                         if (le32_to_cpu(val) != p[i]) {
12987                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
12988                                 /* ret = -ENODEV here? */
12989                         }
12990                         p[i] = 0;
12991                 }
12992 #endif
12993                 /* Now read it back. */
12994                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
12995                 if (ret) {
12996                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
12997
12998                         break;
12999                 }
13000
13001                 /* Verify it. */
13002                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
13003                         if (p[i] == i)
13004                                 continue;
13005
13006                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13007                             DMA_RWCTRL_WRITE_BNDRY_16) {
13008                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13009                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13010                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13011                                 break;
13012                         } else {
13013                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
13014                                 ret = -ENODEV;
13015                                 goto out;
13016                         }
13017                 }
13018
13019                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
13020                         /* Success. */
13021                         ret = 0;
13022                         break;
13023                 }
13024         }
13025         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
13026             DMA_RWCTRL_WRITE_BNDRY_16) {
13027                 static struct pci_device_id dma_wait_state_chipsets[] = {
13028                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
13029                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
13030                         { },
13031                 };
13032
13033                 /* DMA test passed without adjusting DMA boundary,
13034                  * now look for chipsets that are known to expose the
13035                  * DMA bug without failing the test.
13036                  */
13037                 if (pci_dev_present(dma_wait_state_chipsets)) {
13038                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13039                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
13040                 }
13041                 else
13042                         /* Safe to use the calculated DMA boundary. */
13043                         tp->dma_rwctrl = saved_dma_rwctrl;
13044
13045                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13046         }
13047
13048 out:
13049         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
13050 out_nofree:
13051         return ret;
13052 }
13053
13054 static void __devinit tg3_init_link_config(struct tg3 *tp)
13055 {
13056         tp->link_config.advertising =
13057                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
13058                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
13059                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
13060                  ADVERTISED_Autoneg | ADVERTISED_MII);
13061         tp->link_config.speed = SPEED_INVALID;
13062         tp->link_config.duplex = DUPLEX_INVALID;
13063         tp->link_config.autoneg = AUTONEG_ENABLE;
13064         tp->link_config.active_speed = SPEED_INVALID;
13065         tp->link_config.active_duplex = DUPLEX_INVALID;
13066         tp->link_config.phy_is_low_power = 0;
13067         tp->link_config.orig_speed = SPEED_INVALID;
13068         tp->link_config.orig_duplex = DUPLEX_INVALID;
13069         tp->link_config.orig_autoneg = AUTONEG_INVALID;
13070 }
13071
13072 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
13073 {
13074         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13075                 tp->bufmgr_config.mbuf_read_dma_low_water =
13076                         DEFAULT_MB_RDMA_LOW_WATER_5705;
13077                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13078                         DEFAULT_MB_MACRX_LOW_WATER_5705;
13079                 tp->bufmgr_config.mbuf_high_water =
13080                         DEFAULT_MB_HIGH_WATER_5705;
13081                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13082                         tp->bufmgr_config.mbuf_mac_rx_low_water =
13083                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
13084                         tp->bufmgr_config.mbuf_high_water =
13085                                 DEFAULT_MB_HIGH_WATER_5906;
13086                 }
13087
13088                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13089                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
13090                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13091                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
13092                 tp->bufmgr_config.mbuf_high_water_jumbo =
13093                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
13094         } else {
13095                 tp->bufmgr_config.mbuf_read_dma_low_water =
13096                         DEFAULT_MB_RDMA_LOW_WATER;
13097                 tp->bufmgr_config.mbuf_mac_rx_low_water =
13098                         DEFAULT_MB_MACRX_LOW_WATER;
13099                 tp->bufmgr_config.mbuf_high_water =
13100                         DEFAULT_MB_HIGH_WATER;
13101
13102                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
13103                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
13104                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
13105                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
13106                 tp->bufmgr_config.mbuf_high_water_jumbo =
13107                         DEFAULT_MB_HIGH_WATER_JUMBO;
13108         }
13109
13110         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
13111         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
13112 }
13113
13114 static char * __devinit tg3_phy_string(struct tg3 *tp)
13115 {
13116         switch (tp->phy_id & PHY_ID_MASK) {
13117         case PHY_ID_BCM5400:    return "5400";
13118         case PHY_ID_BCM5401:    return "5401";
13119         case PHY_ID_BCM5411:    return "5411";
13120         case PHY_ID_BCM5701:    return "5701";
13121         case PHY_ID_BCM5703:    return "5703";
13122         case PHY_ID_BCM5704:    return "5704";
13123         case PHY_ID_BCM5705:    return "5705";
13124         case PHY_ID_BCM5750:    return "5750";
13125         case PHY_ID_BCM5752:    return "5752";
13126         case PHY_ID_BCM5714:    return "5714";
13127         case PHY_ID_BCM5780:    return "5780";
13128         case PHY_ID_BCM5755:    return "5755";
13129         case PHY_ID_BCM5787:    return "5787";
13130         case PHY_ID_BCM5784:    return "5784";
13131         case PHY_ID_BCM5756:    return "5722/5756";
13132         case PHY_ID_BCM5906:    return "5906";
13133         case PHY_ID_BCM5761:    return "5761";
13134         case PHY_ID_BCM8002:    return "8002/serdes";
13135         case 0:                 return "serdes";
13136         default:                return "unknown";
13137         }
13138 }
13139
13140 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
13141 {
13142         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13143                 strcpy(str, "PCI Express");
13144                 return str;
13145         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13146                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
13147
13148                 strcpy(str, "PCIX:");
13149
13150                 if ((clock_ctrl == 7) ||
13151                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
13152                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
13153                         strcat(str, "133MHz");
13154                 else if (clock_ctrl == 0)
13155                         strcat(str, "33MHz");
13156                 else if (clock_ctrl == 2)
13157                         strcat(str, "50MHz");
13158                 else if (clock_ctrl == 4)
13159                         strcat(str, "66MHz");
13160                 else if (clock_ctrl == 6)
13161                         strcat(str, "100MHz");
13162         } else {
13163                 strcpy(str, "PCI:");
13164                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
13165                         strcat(str, "66MHz");
13166                 else
13167                         strcat(str, "33MHz");
13168         }
13169         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
13170                 strcat(str, ":32-bit");
13171         else
13172                 strcat(str, ":64-bit");
13173         return str;
13174 }
13175
13176 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
13177 {
13178         struct pci_dev *peer;
13179         unsigned int func, devnr = tp->pdev->devfn & ~7;
13180
13181         for (func = 0; func < 8; func++) {
13182                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
13183                 if (peer && peer != tp->pdev)
13184                         break;
13185                 pci_dev_put(peer);
13186         }
13187         /* 5704 can be configured in single-port mode, set peer to
13188          * tp->pdev in that case.
13189          */
13190         if (!peer) {
13191                 peer = tp->pdev;
13192                 return peer;
13193         }
13194
13195         /*
13196          * We don't need to keep the refcount elevated; there's no way
13197          * to remove one half of this device without removing the other
13198          */
13199         pci_dev_put(peer);
13200
13201         return peer;
13202 }
13203
13204 static void __devinit tg3_init_coal(struct tg3 *tp)
13205 {
13206         struct ethtool_coalesce *ec = &tp->coal;
13207
13208         memset(ec, 0, sizeof(*ec));
13209         ec->cmd = ETHTOOL_GCOALESCE;
13210         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
13211         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
13212         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
13213         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
13214         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
13215         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
13216         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
13217         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
13218         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
13219
13220         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
13221                                  HOSTCC_MODE_CLRTICK_TXBD)) {
13222                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
13223                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
13224                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
13225                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
13226         }
13227
13228         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
13229                 ec->rx_coalesce_usecs_irq = 0;
13230                 ec->tx_coalesce_usecs_irq = 0;
13231                 ec->stats_block_coalesce_usecs = 0;
13232         }
13233 }
13234
13235 static int __devinit tg3_init_one(struct pci_dev *pdev,
13236                                   const struct pci_device_id *ent)
13237 {
13238         static int tg3_version_printed = 0;
13239         resource_size_t tg3reg_base;
13240         unsigned long tg3reg_len;
13241         struct net_device *dev;
13242         struct tg3 *tp;
13243         int err, pm_cap;
13244         char str[40];
13245         u64 dma_mask, persist_dma_mask;
13246         DECLARE_MAC_BUF(mac);
13247
13248         if (tg3_version_printed++ == 0)
13249                 printk(KERN_INFO "%s", version);
13250
13251         err = pci_enable_device(pdev);
13252         if (err) {
13253                 printk(KERN_ERR PFX "Cannot enable PCI device, "
13254                        "aborting.\n");
13255                 return err;
13256         }
13257
13258         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
13259                 printk(KERN_ERR PFX "Cannot find proper PCI device "
13260                        "base address, aborting.\n");
13261                 err = -ENODEV;
13262                 goto err_out_disable_pdev;
13263         }
13264
13265         err = pci_request_regions(pdev, DRV_MODULE_NAME);
13266         if (err) {
13267                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
13268                        "aborting.\n");
13269                 goto err_out_disable_pdev;
13270         }
13271
13272         pci_set_master(pdev);
13273
13274         /* Find power-management capability. */
13275         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
13276         if (pm_cap == 0) {
13277                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
13278                        "aborting.\n");
13279                 err = -EIO;
13280                 goto err_out_free_res;
13281         }
13282
13283         tg3reg_base = pci_resource_start(pdev, 0);
13284         tg3reg_len = pci_resource_len(pdev, 0);
13285
13286         dev = alloc_etherdev(sizeof(*tp));
13287         if (!dev) {
13288                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
13289                 err = -ENOMEM;
13290                 goto err_out_free_res;
13291         }
13292
13293         SET_NETDEV_DEV(dev, &pdev->dev);
13294
13295 #if TG3_VLAN_TAG_USED
13296         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
13297         dev->vlan_rx_register = tg3_vlan_rx_register;
13298 #endif
13299
13300         tp = netdev_priv(dev);
13301         tp->pdev = pdev;
13302         tp->dev = dev;
13303         tp->pm_cap = pm_cap;
13304         tp->mac_mode = TG3_DEF_MAC_MODE;
13305         tp->rx_mode = TG3_DEF_RX_MODE;
13306         tp->tx_mode = TG3_DEF_TX_MODE;
13307
13308         if (tg3_debug > 0)
13309                 tp->msg_enable = tg3_debug;
13310         else
13311                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
13312
13313         /* The word/byte swap controls here control register access byte
13314          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
13315          * setting below.
13316          */
13317         tp->misc_host_ctrl =
13318                 MISC_HOST_CTRL_MASK_PCI_INT |
13319                 MISC_HOST_CTRL_WORD_SWAP |
13320                 MISC_HOST_CTRL_INDIR_ACCESS |
13321                 MISC_HOST_CTRL_PCISTATE_RW;
13322
13323         /* The NONFRM (non-frame) byte/word swap controls take effect
13324          * on descriptor entries, anything which isn't packet data.
13325          *
13326          * The StrongARM chips on the board (one for tx, one for rx)
13327          * are running in big-endian mode.
13328          */
13329         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
13330                         GRC_MODE_WSWAP_NONFRM_DATA);
13331 #ifdef __BIG_ENDIAN
13332         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
13333 #endif
13334         spin_lock_init(&tp->lock);
13335         spin_lock_init(&tp->indirect_lock);
13336         INIT_WORK(&tp->reset_task, tg3_reset_task);
13337
13338         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
13339         if (!tp->regs) {
13340                 printk(KERN_ERR PFX "Cannot map device registers, "
13341                        "aborting.\n");
13342                 err = -ENOMEM;
13343                 goto err_out_free_dev;
13344         }
13345
13346         tg3_init_link_config(tp);
13347
13348         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
13349         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
13350         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
13351
13352         dev->open = tg3_open;
13353         dev->stop = tg3_close;
13354         dev->get_stats = tg3_get_stats;
13355         dev->set_multicast_list = tg3_set_rx_mode;
13356         dev->set_mac_address = tg3_set_mac_addr;
13357         dev->do_ioctl = tg3_ioctl;
13358         dev->tx_timeout = tg3_tx_timeout;
13359         netif_napi_add(dev, &tp->napi, tg3_poll, 64);
13360         dev->ethtool_ops = &tg3_ethtool_ops;
13361         dev->watchdog_timeo = TG3_TX_TIMEOUT;
13362         dev->change_mtu = tg3_change_mtu;
13363         dev->irq = pdev->irq;
13364 #ifdef CONFIG_NET_POLL_CONTROLLER
13365         dev->poll_controller = tg3_poll_controller;
13366 #endif
13367
13368         err = tg3_get_invariants(tp);
13369         if (err) {
13370                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
13371                        "aborting.\n");
13372                 goto err_out_iounmap;
13373         }
13374
13375         /* The EPB bridge inside 5714, 5715, and 5780 and any
13376          * device behind the EPB cannot support DMA addresses > 40-bit.
13377          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
13378          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
13379          * do DMA address check in tg3_start_xmit().
13380          */
13381         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
13382                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
13383         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
13384                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
13385 #ifdef CONFIG_HIGHMEM
13386                 dma_mask = DMA_64BIT_MASK;
13387 #endif
13388         } else
13389                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
13390
13391         /* Configure DMA attributes. */
13392         if (dma_mask > DMA_32BIT_MASK) {
13393                 err = pci_set_dma_mask(pdev, dma_mask);
13394                 if (!err) {
13395                         dev->features |= NETIF_F_HIGHDMA;
13396                         err = pci_set_consistent_dma_mask(pdev,
13397                                                           persist_dma_mask);
13398                         if (err < 0) {
13399                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
13400                                        "DMA for consistent allocations\n");
13401                                 goto err_out_iounmap;
13402                         }
13403                 }
13404         }
13405         if (err || dma_mask == DMA_32BIT_MASK) {
13406                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
13407                 if (err) {
13408                         printk(KERN_ERR PFX "No usable DMA configuration, "
13409                                "aborting.\n");
13410                         goto err_out_iounmap;
13411                 }
13412         }
13413
13414         tg3_init_bufmgr_config(tp);
13415
13416         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13417                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
13418         }
13419         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13420             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13421             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
13422             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13423             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
13424                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
13425         } else {
13426                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
13427         }
13428
13429         /* TSO is on by default on chips that support hardware TSO.
13430          * Firmware TSO on older chips gives lower performance, so it
13431          * is off by default, but can be enabled using ethtool.
13432          */
13433         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
13434                 dev->features |= NETIF_F_TSO;
13435                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
13436                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
13437                         dev->features |= NETIF_F_TSO6;
13438                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13439                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13440                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
13441                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13442                         dev->features |= NETIF_F_TSO_ECN;
13443         }
13444
13445
13446         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
13447             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
13448             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
13449                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
13450                 tp->rx_pending = 63;
13451         }
13452
13453         err = tg3_get_device_address(tp);
13454         if (err) {
13455                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
13456                        "aborting.\n");
13457                 goto err_out_iounmap;
13458         }
13459
13460         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13461                 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
13462                         printk(KERN_ERR PFX "Cannot find proper PCI device "
13463                                "base address for APE, aborting.\n");
13464                         err = -ENODEV;
13465                         goto err_out_iounmap;
13466                 }
13467
13468                 tg3reg_base = pci_resource_start(pdev, 2);
13469                 tg3reg_len = pci_resource_len(pdev, 2);
13470
13471                 tp->aperegs = ioremap_nocache(tg3reg_base, tg3reg_len);
13472                 if (!tp->aperegs) {
13473                         printk(KERN_ERR PFX "Cannot map APE registers, "
13474                                "aborting.\n");
13475                         err = -ENOMEM;
13476                         goto err_out_iounmap;
13477                 }
13478
13479                 tg3_ape_lock_init(tp);
13480         }
13481
13482         /*
13483          * Reset chip in case UNDI or EFI driver did not shutdown
13484          * DMA self test will enable WDMAC and we'll see (spurious)
13485          * pending DMA on the PCI bus at that point.
13486          */
13487         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
13488             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
13489                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
13490                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13491         }
13492
13493         err = tg3_test_dma(tp);
13494         if (err) {
13495                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
13496                 goto err_out_apeunmap;
13497         }
13498
13499         /* Tigon3 can do ipv4 only... and some chips have buggy
13500          * checksumming.
13501          */
13502         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
13503                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13504                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13505                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13506                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13507                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13508                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
13509                         dev->features |= NETIF_F_IPV6_CSUM;
13510
13511                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13512         } else
13513                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
13514
13515         /* flow control autonegotiation is default behavior */
13516         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
13517         tp->link_config.flowctrl = TG3_FLOW_CTRL_TX | TG3_FLOW_CTRL_RX;
13518
13519         tg3_init_coal(tp);
13520
13521         pci_set_drvdata(pdev, dev);
13522
13523         err = register_netdev(dev);
13524         if (err) {
13525                 printk(KERN_ERR PFX "Cannot register net device, "
13526                        "aborting.\n");
13527                 goto err_out_apeunmap;
13528         }
13529
13530         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] "
13531                "(%s) %s Ethernet %s\n",
13532                dev->name,
13533                tp->board_part_number,
13534                tp->pci_chip_rev_id,
13535                tg3_phy_string(tp),
13536                tg3_bus_string(tp, str),
13537                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
13538                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
13539                  "10/100/1000Base-T")),
13540                print_mac(mac, dev->dev_addr));
13541
13542         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
13543                "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
13544                dev->name,
13545                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
13546                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
13547                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
13548                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
13549                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
13550                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
13551         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
13552                dev->name, tp->dma_rwctrl,
13553                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
13554                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
13555
13556         return 0;
13557
13558 err_out_apeunmap:
13559         if (tp->aperegs) {
13560                 iounmap(tp->aperegs);
13561                 tp->aperegs = NULL;
13562         }
13563
13564 err_out_iounmap:
13565         if (tp->regs) {
13566                 iounmap(tp->regs);
13567                 tp->regs = NULL;
13568         }
13569
13570 err_out_free_dev:
13571         free_netdev(dev);
13572
13573 err_out_free_res:
13574         pci_release_regions(pdev);
13575
13576 err_out_disable_pdev:
13577         pci_disable_device(pdev);
13578         pci_set_drvdata(pdev, NULL);
13579         return err;
13580 }
13581
13582 static void __devexit tg3_remove_one(struct pci_dev *pdev)
13583 {
13584         struct net_device *dev = pci_get_drvdata(pdev);
13585
13586         if (dev) {
13587                 struct tg3 *tp = netdev_priv(dev);
13588
13589                 flush_scheduled_work();
13590
13591                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
13592                         tg3_phy_fini(tp);
13593                         tg3_mdio_fini(tp);
13594                 }
13595
13596                 unregister_netdev(dev);
13597                 if (tp->aperegs) {
13598                         iounmap(tp->aperegs);
13599                         tp->aperegs = NULL;
13600                 }
13601                 if (tp->regs) {
13602                         iounmap(tp->regs);
13603                         tp->regs = NULL;
13604                 }
13605                 free_netdev(dev);
13606                 pci_release_regions(pdev);
13607                 pci_disable_device(pdev);
13608                 pci_set_drvdata(pdev, NULL);
13609         }
13610 }
13611
13612 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
13613 {
13614         struct net_device *dev = pci_get_drvdata(pdev);
13615         struct tg3 *tp = netdev_priv(dev);
13616         int err;
13617
13618         /* PCI register 4 needs to be saved whether netif_running() or not.
13619          * MSI address and data need to be saved if using MSI and
13620          * netif_running().
13621          */
13622         pci_save_state(pdev);
13623
13624         if (!netif_running(dev))
13625                 return 0;
13626
13627         flush_scheduled_work();
13628         tg3_phy_stop(tp);
13629         tg3_netif_stop(tp);
13630
13631         del_timer_sync(&tp->timer);
13632
13633         tg3_full_lock(tp, 1);
13634         tg3_disable_ints(tp);
13635         tg3_full_unlock(tp);
13636
13637         netif_device_detach(dev);
13638
13639         tg3_full_lock(tp, 0);
13640         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13641         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
13642         tg3_full_unlock(tp);
13643
13644         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
13645         if (err) {
13646                 int err2;
13647
13648                 tg3_full_lock(tp, 0);
13649
13650                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13651                 err2 = tg3_restart_hw(tp, 1);
13652                 if (err2)
13653                         goto out;
13654
13655                 tp->timer.expires = jiffies + tp->timer_offset;
13656                 add_timer(&tp->timer);
13657
13658                 netif_device_attach(dev);
13659                 tg3_netif_start(tp);
13660
13661 out:
13662                 tg3_full_unlock(tp);
13663
13664                 if (!err2)
13665                         tg3_phy_start(tp);
13666         }
13667
13668         return err;
13669 }
13670
13671 static int tg3_resume(struct pci_dev *pdev)
13672 {
13673         struct net_device *dev = pci_get_drvdata(pdev);
13674         struct tg3 *tp = netdev_priv(dev);
13675         int err;
13676
13677         pci_restore_state(tp->pdev);
13678
13679         if (!netif_running(dev))
13680                 return 0;
13681
13682         err = tg3_set_power_state(tp, PCI_D0);
13683         if (err)
13684                 return err;
13685
13686         netif_device_attach(dev);
13687
13688         tg3_full_lock(tp, 0);
13689
13690         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
13691         err = tg3_restart_hw(tp, 1);
13692         if (err)
13693                 goto out;
13694
13695         tp->timer.expires = jiffies + tp->timer_offset;
13696         add_timer(&tp->timer);
13697
13698         tg3_netif_start(tp);
13699
13700 out:
13701         tg3_full_unlock(tp);
13702
13703         if (!err)
13704                 tg3_phy_start(tp);
13705
13706         return err;
13707 }
13708
13709 static struct pci_driver tg3_driver = {
13710         .name           = DRV_MODULE_NAME,
13711         .id_table       = tg3_pci_tbl,
13712         .probe          = tg3_init_one,
13713         .remove         = __devexit_p(tg3_remove_one),
13714         .suspend        = tg3_suspend,
13715         .resume         = tg3_resume
13716 };
13717
13718 static int __init tg3_init(void)
13719 {
13720         return pci_register_driver(&tg3_driver);
13721 }
13722
13723 static void __exit tg3_cleanup(void)
13724 {
13725         pci_unregister_driver(&tg3_driver);
13726 }
13727
13728 module_init(tg3_init);
13729 module_exit(tg3_cleanup);