drivers/net/stmmac/dwmac_lib.c

   1 /*******************************************************************************
   2   Copyright (C) 2007-2009  STMicroelectronics Ltd
   3
   4   This program is free software; you can redistribute it and/or modify it
   5   under the terms and conditions of the GNU General Public License,
   6   version 2, as published by the Free Software Foundation.
   7
   8   This program is distributed in the hope it will be useful, but WITHOUT
   9   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11   more details.
  12
  13   You should have received a copy of the GNU General Public License along with
  14   this program; if not, write to the Free Software Foundation, Inc.,
  15   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16
  17   The full GNU General Public License is included in this distribution in
  18   the file called "COPYING".
  19
  20   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  21 *******************************************************************************/
  22
  23 #include <linux/io.h>
  24 #include "common.h"
  25 #include "dwmac_dma.h"
  26
  27 #undef DWMAC_DMA_DEBUG
  28 #ifdef DWMAC_DMA_DEBUG
  29 #define DWMAC_LIB_DBG(fmt, args...)  printk(fmt, ## args)
  30 #else
  31 #define DWMAC_LIB_DBG(fmt, args...)  do { } while (0)
  32 #endif
  33
  34 /* CSR1 enables the transmit DMA to check for new descriptor */
  35 void dwmac_enable_dma_transmission(void __iomem *ioaddr)
  36 {
  37         writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
  38 }
  39
  40 void dwmac_enable_dma_irq(void __iomem *ioaddr)
  41 {
  42         writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
  43 }
  44
  45 void dwmac_disable_dma_irq(void __iomem *ioaddr)
  46 {
  47         writel(0, ioaddr + DMA_INTR_ENA);
  48 }
  49
  50 void dwmac_dma_start_tx(void __iomem *ioaddr)
  51 {
  52         u32 value = readl(ioaddr + DMA_CONTROL);
  53         value |= DMA_CONTROL_ST;
  54         writel(value, ioaddr + DMA_CONTROL);
  55 }
  56
  57 void dwmac_dma_stop_tx(void __iomem *ioaddr)
  58 {
  59         u32 value = readl(ioaddr + DMA_CONTROL);
  60         value &= ~DMA_CONTROL_ST;
  61         writel(value, ioaddr + DMA_CONTROL);
  62 }
  63
  64 void dwmac_dma_start_rx(void __iomem *ioaddr)
  65 {
  66         u32 value = readl(ioaddr + DMA_CONTROL);
  67         value |= DMA_CONTROL_SR;
  68         writel(value, ioaddr + DMA_CONTROL);
  69 }
  70
  71 void dwmac_dma_stop_rx(void __iomem *ioaddr)
  72 {
  73         u32 value = readl(ioaddr + DMA_CONTROL);
  74         value &= ~DMA_CONTROL_SR;
  75         writel(value, ioaddr + DMA_CONTROL);
  76 }
  77
  78 #ifdef DWMAC_DMA_DEBUG
  79 static void show_tx_process_state(unsigned int status)
  80 {
  81         unsigned int state;
  82         state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
  83
  84         switch (state) {
  85         case 0:
  86                 pr_info("- TX (Stopped): Reset or Stop command\n");
  87                 break;
  88         case 1:
  89                 pr_info("- TX (Running):Fetching the Tx desc\n");
  90                 break;
  91         case 2:
  92                 pr_info("- TX (Running): Waiting for end of tx\n");
  93                 break;
  94         case 3:
  95                 pr_info("- TX (Running): Reading the data "
  96                        "and queuing the data into the Tx buf\n");
  97                 break;
  98         case 6:
  99                 pr_info("- TX (Suspended): Tx Buff Underflow "
 100                        "or an unavailable Transmit descriptor\n");
 101                 break;
 102         case 7:
 103                 pr_info("- TX (Running): Closing Tx descriptor\n");
 104                 break;
 105         default:
 106                 break;
 107         }
 108 }
 109
 110 static void show_rx_process_state(unsigned int status)
 111 {
 112         unsigned int state;
 113         state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
 114
 115         switch (state) {
 116         case 0:
 117                 pr_info("- RX (Stopped): Reset or Stop command\n");
 118                 break;
 119         case 1:
 120                 pr_info("- RX (Running): Fetching the Rx desc\n");
 121                 break;
 122         case 2:
 123                 pr_info("- RX (Running):Checking for end of pkt\n");
 124                 break;
 125         case 3:
 126                 pr_info("- RX (Running): Waiting for Rx pkt\n");
 127                 break;
 128         case 4:
 129                 pr_info("- RX (Suspended): Unavailable Rx buf\n");
 130                 break;
 131         case 5:
 132                 pr_info("- RX (Running): Closing Rx descriptor\n");
 133                 break;
 134         case 6:
 135                 pr_info("- RX(Running): Flushing the current frame"
 136                        " from the Rx buf\n");
 137                 break;
 138         case 7:
 139                 pr_info("- RX (Running): Queuing the Rx frame"
 140                        " from the Rx buf into memory\n");
 141                 break;
 142         default:
 143                 break;
 144         }
 145 }
 146 #endif
 147
 148 int dwmac_dma_interrupt(void __iomem *ioaddr,
 149                         struct stmmac_extra_stats *x)
 150 {
 151         int ret = 0;
 152         /* read the status register (CSR5) */
 153         u32 intr_status = readl(ioaddr + DMA_STATUS);
 154
 155         DWMAC_LIB_DBG(KERN_INFO "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
 156 #ifdef DWMAC_DMA_DEBUG
 157         /* It displays the DMA process states (CSR5 register) */
 158         show_tx_process_state(intr_status);
 159         show_rx_process_state(intr_status);
 160 #endif
 161         /* ABNORMAL interrupts */
 162         if (unlikely(intr_status & DMA_STATUS_AIS)) {
 163                 DWMAC_LIB_DBG(KERN_INFO "CSR5[15] DMA ABNORMAL IRQ: ");
 164                 if (unlikely(intr_status & DMA_STATUS_UNF)) {
 165                         DWMAC_LIB_DBG(KERN_INFO "transmit underflow\n");
 166                         ret = tx_hard_error_bump_tc;
 167                         x->tx_undeflow_irq++;
 168                 }
 169                 if (unlikely(intr_status & DMA_STATUS_TJT)) {
 170                         DWMAC_LIB_DBG(KERN_INFO "transmit jabber\n");
 171                         x->tx_jabber_irq++;
 172                 }
 173                 if (unlikely(intr_status & DMA_STATUS_OVF)) {
 174                         DWMAC_LIB_DBG(KERN_INFO "recv overflow\n");
 175                         x->rx_overflow_irq++;
 176                 }
 177                 if (unlikely(intr_status & DMA_STATUS_RU)) {
 178                         DWMAC_LIB_DBG(KERN_INFO "receive buffer unavailable\n");
 179                         x->rx_buf_unav_irq++;
 180                 }
 181                 if (unlikely(intr_status & DMA_STATUS_RPS)) {
 182                         DWMAC_LIB_DBG(KERN_INFO "receive process stopped\n");
 183                         x->rx_process_stopped_irq++;
 184                 }
 185                 if (unlikely(intr_status & DMA_STATUS_RWT)) {
 186                         DWMAC_LIB_DBG(KERN_INFO "receive watchdog\n");
 187                         x->rx_watchdog_irq++;
 188                 }
 189                 if (unlikely(intr_status & DMA_STATUS_ETI)) {
 190                         DWMAC_LIB_DBG(KERN_INFO "transmit early interrupt\n");
 191                         x->tx_early_irq++;
 192                 }
 193                 if (unlikely(intr_status & DMA_STATUS_TPS)) {
 194                         DWMAC_LIB_DBG(KERN_INFO "transmit process stopped\n");
 195                         x->tx_process_stopped_irq++;
 196                         ret = tx_hard_error;
 197                 }
 198                 if (unlikely(intr_status & DMA_STATUS_FBI)) {
 199                         DWMAC_LIB_DBG(KERN_INFO "fatal bus error\n");
 200                         x->fatal_bus_error_irq++;
 201                         ret = tx_hard_error;
 202                 }
 203         }
 204         /* TX/RX NORMAL interrupts */
 205         if (intr_status & DMA_STATUS_NIS) {
 206                 x->normal_irq_n++;
 207                 if (likely((intr_status & DMA_STATUS_RI) ||
 208                          (intr_status & (DMA_STATUS_TI))))
 209                                 ret = handle_tx_rx;
 210         }
 211         /* Optional hardware blocks, interrupts should be disabled */
 212         if (unlikely(intr_status &
 213                      (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
 214                 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
 215         /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
 216         writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
 217
 218         DWMAC_LIB_DBG(KERN_INFO "\n\n");
 219         return ret;
 220 }
 221
 222 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
 223 {
 224         u32 csr6 = readl(ioaddr + DMA_CONTROL);
 225         writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
 226
 227         do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
 228 }
 229
 230 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
 231                          unsigned int high, unsigned int low)
 232 {
 233         unsigned long data;
 234
 235         data = (addr[5] << 8) | addr[4];
 236         writel(data, ioaddr + high);
 237         data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
 238         writel(data, ioaddr + low);
 239 }
 240
 241 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
 242                          unsigned int high, unsigned int low)
 243 {
 244         unsigned int hi_addr, lo_addr;
 245
 246         /* Read the MAC address from the hardware */
 247         hi_addr = readl(ioaddr + high);
 248         lo_addr = readl(ioaddr + low);
 249
 250         /* Extract the MAC address from the high and low words */
 251         addr[0] = lo_addr & 0xff;
 252         addr[1] = (lo_addr >> 8) & 0xff;
 253         addr[2] = (lo_addr >> 16) & 0xff;
 254         addr[3] = (lo_addr >> 24) & 0xff;
 255         addr[4] = hi_addr & 0xff;
 256         addr[5] = (hi_addr >> 8) & 0xff;
 257 }
 258