1 /******************************************************************************
4 * Project: Gigabit Ethernet Adapters, Common Modules
5 * Version: $Revision: 1.52 $
6 * Date: $Date: 2003/10/02 16:35:50 $
7 * Purpose: Defines and Macros for Gigabit Ethernet Controller
9 ******************************************************************************/
11 /******************************************************************************
13 * (C)Copyright 1998-2002 SysKonnect.
14 * (C)Copyright 2002-2003 Marvell.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * The information in this file is provided "AS IS" without warranty.
23 ******************************************************************************/
30 #endif /* __cplusplus */
32 /* defines ********************************************************************/
37 * The XMAC registers are 16 or 32 bits wide.
38 * The XMACs host processor interface is set to 16 bit mode,
39 * therefore ALL registers will be addressed with 16 bit accesses.
41 * The following macros are provided to access the XMAC registers
42 * XM_IN16(), XM_OUT16, XM_IN32(), XM_OUT32(), XM_INADR(), XM_OUTADR(),
43 * XM_INHASH(), and XM_OUTHASH().
44 * The macros are defined in SkGeHw.h.
46 * Note: NA reg = Network Address e.g DA, SA etc.
49 #define XM_MMU_CMD 0x0000 /* 16 bit r/w MMU Command Register */
50 /* 0x0004: reserved */
51 #define XM_POFF 0x0008 /* 32 bit r/w Packet Offset Register */
52 #define XM_BURST 0x000c /* 32 bit r/w Burst Register for half duplex*/
53 #define XM_1L_VLAN_TAG 0x0010 /* 16 bit r/w One Level VLAN Tag ID */
54 #define XM_2L_VLAN_TAG 0x0014 /* 16 bit r/w Two Level VLAN Tag ID */
55 /* 0x0018 - 0x001e: reserved */
56 #define XM_TX_CMD 0x0020 /* 16 bit r/w Transmit Command Register */
57 #define XM_TX_RT_LIM 0x0024 /* 16 bit r/w Transmit Retry Limit Register */
58 #define XM_TX_STIME 0x0028 /* 16 bit r/w Transmit Slottime Register */
59 #define XM_TX_IPG 0x002c /* 16 bit r/w Transmit Inter Packet Gap */
60 #define XM_RX_CMD 0x0030 /* 16 bit r/w Receive Command Register */
61 #define XM_PHY_ADDR 0x0034 /* 16 bit r/w PHY Address Register */
62 #define XM_PHY_DATA 0x0038 /* 16 bit r/w PHY Data Register */
63 /* 0x003c: reserved */
64 #define XM_GP_PORT 0x0040 /* 32 bit r/w General Purpose Port Register */
65 #define XM_IMSK 0x0044 /* 16 bit r/w Interrupt Mask Register */
66 #define XM_ISRC 0x0048 /* 16 bit r/o Interrupt Status Register */
67 #define XM_HW_CFG 0x004c /* 16 bit r/w Hardware Config Register */
68 /* 0x0050 - 0x005e: reserved */
69 #define XM_TX_LO_WM 0x0060 /* 16 bit r/w Tx FIFO Low Water Mark */
70 #define XM_TX_HI_WM 0x0062 /* 16 bit r/w Tx FIFO High Water Mark */
71 #define XM_TX_THR 0x0064 /* 16 bit r/w Tx Request Threshold */
72 #define XM_HT_THR 0x0066 /* 16 bit r/w Host Request Threshold */
73 #define XM_PAUSE_DA 0x0068 /* NA reg r/w Pause Destination Address */
74 /* 0x006e: reserved */
75 #define XM_CTL_PARA 0x0070 /* 32 bit r/w Control Parameter Register */
76 #define XM_MAC_OPCODE 0x0074 /* 16 bit r/w Opcode for MAC control frames */
77 #define XM_MAC_PTIME 0x0076 /* 16 bit r/w Pause time for MAC ctrl frames*/
78 #define XM_TX_STAT 0x0078 /* 32 bit r/o Tx Status LIFO Register */
80 /* 0x0080 - 0x00fc: 16 NA reg r/w Exact Match Address Registers */
81 /* use the XM_EXM() macro to address */
82 #define XM_EXM_START 0x0080 /* r/w Start Address of the EXM Regs */
87 * returns the XMAC address offset of specified Exact Match Addr Reg
89 * para: Reg EXM register to addr (0 .. 15)
91 * usage: XM_INADDR(IoC, MAC_1, XM_EXM(i), &val[i]);
93 #define XM_EXM(Reg) (XM_EXM_START + ((Reg) << 3))
95 #define XM_SRC_CHK 0x0100 /* NA reg r/w Source Check Address Register */
96 #define XM_SA 0x0108 /* NA reg r/w Station Address Register */
97 #define XM_HSM 0x0110 /* 64 bit r/w Hash Match Address Registers */
98 #define XM_RX_LO_WM 0x0118 /* 16 bit r/w Receive Low Water Mark */
99 #define XM_RX_HI_WM 0x011a /* 16 bit r/w Receive High Water Mark */
100 #define XM_RX_THR 0x011c /* 32 bit r/w Receive Request Threshold */
101 #define XM_DEV_ID 0x0120 /* 32 bit r/o Device ID Register */
102 #define XM_MODE 0x0124 /* 32 bit r/w Mode Register */
103 #define XM_LSA 0x0128 /* NA reg r/o Last Source Register */
104 /* 0x012e: reserved */
105 #define XM_TS_READ 0x0130 /* 32 bit r/o Time Stamp Read Register */
106 #define XM_TS_LOAD 0x0134 /* 32 bit r/o Time Stamp Load Value */
107 /* 0x0138 - 0x01fe: reserved */
108 #define XM_STAT_CMD 0x0200 /* 16 bit r/w Statistics Command Register */
109 #define XM_RX_CNT_EV 0x0204 /* 32 bit r/o Rx Counter Event Register */
110 #define XM_TX_CNT_EV 0x0208 /* 32 bit r/o Tx Counter Event Register */
111 #define XM_RX_EV_MSK 0x020c /* 32 bit r/w Rx Counter Event Mask */
112 #define XM_TX_EV_MSK 0x0210 /* 32 bit r/w Tx Counter Event Mask */
113 /* 0x0204 - 0x027e: reserved */
114 #define XM_TXF_OK 0x0280 /* 32 bit r/o Frames Transmitted OK Conuter */
115 #define XM_TXO_OK_HI 0x0284 /* 32 bit r/o Octets Transmitted OK High Cnt*/
116 #define XM_TXO_OK_LO 0x0288 /* 32 bit r/o Octets Transmitted OK Low Cnt */
117 #define XM_TXF_BC_OK 0x028c /* 32 bit r/o Broadcast Frames Xmitted OK */
118 #define XM_TXF_MC_OK 0x0290 /* 32 bit r/o Multicast Frames Xmitted OK */
119 #define XM_TXF_UC_OK 0x0294 /* 32 bit r/o Unicast Frames Xmitted OK */
120 #define XM_TXF_LONG 0x0298 /* 32 bit r/o Tx Long Frame Counter */
121 #define XM_TXE_BURST 0x029c /* 32 bit r/o Tx Burst Event Counter */
122 #define XM_TXF_MPAUSE 0x02a0 /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
123 #define XM_TXF_MCTRL 0x02a4 /* 32 bit r/o Tx MAC Ctrl Frame Counter */
124 #define XM_TXF_SNG_COL 0x02a8 /* 32 bit r/o Tx Single Collision Counter */
125 #define XM_TXF_MUL_COL 0x02ac /* 32 bit r/o Tx Multiple Collision Counter */
126 #define XM_TXF_ABO_COL 0x02b0 /* 32 bit r/o Tx aborted due to Exces. Col. */
127 #define XM_TXF_LAT_COL 0x02b4 /* 32 bit r/o Tx Late Collision Counter */
128 #define XM_TXF_DEF 0x02b8 /* 32 bit r/o Tx Deferred Frame Counter */
129 #define XM_TXF_EX_DEF 0x02bc /* 32 bit r/o Tx Excessive Deferall Counter */
130 #define XM_TXE_FIFO_UR 0x02c0 /* 32 bit r/o Tx FIFO Underrun Event Cnt */
131 #define XM_TXE_CS_ERR 0x02c4 /* 32 bit r/o Tx Carrier Sense Error Cnt */
132 #define XM_TXP_UTIL 0x02c8 /* 32 bit r/o Tx Utilization in % */
133 /* 0x02cc - 0x02ce: reserved */
134 #define XM_TXF_64B 0x02d0 /* 32 bit r/o 64 Byte Tx Frame Counter */
135 #define XM_TXF_127B 0x02d4 /* 32 bit r/o 65-127 Byte Tx Frame Counter */
136 #define XM_TXF_255B 0x02d8 /* 32 bit r/o 128-255 Byte Tx Frame Counter */
137 #define XM_TXF_511B 0x02dc /* 32 bit r/o 256-511 Byte Tx Frame Counter */
138 #define XM_TXF_1023B 0x02e0 /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
139 #define XM_TXF_MAX_SZ 0x02e4 /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
140 /* 0x02e8 - 0x02fe: reserved */
141 #define XM_RXF_OK 0x0300 /* 32 bit r/o Frames Received OK */
142 #define XM_RXO_OK_HI 0x0304 /* 32 bit r/o Octets Received OK High Cnt */
143 #define XM_RXO_OK_LO 0x0308 /* 32 bit r/o Octets Received OK Low Counter*/
144 #define XM_RXF_BC_OK 0x030c /* 32 bit r/o Broadcast Frames Received OK */
145 #define XM_RXF_MC_OK 0x0310 /* 32 bit r/o Multicast Frames Received OK */
146 #define XM_RXF_UC_OK 0x0314 /* 32 bit r/o Unicast Frames Received OK */
147 #define XM_RXF_MPAUSE 0x0318 /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
148 #define XM_RXF_MCTRL 0x031c /* 32 bit r/o Rx MAC Ctrl Frame Counter */
149 #define XM_RXF_INV_MP 0x0320 /* 32 bit r/o Rx invalid Pause Frame Cnt */
150 #define XM_RXF_INV_MOC 0x0324 /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
151 #define XM_RXE_BURST 0x0328 /* 32 bit r/o Rx Burst Event Counter */
152 #define XM_RXE_FMISS 0x032c /* 32 bit r/o Rx Missed Frames Event Cnt */
153 #define XM_RXF_FRA_ERR 0x0330 /* 32 bit r/o Rx Framing Error Counter */
154 #define XM_RXE_FIFO_OV 0x0334 /* 32 bit r/o Rx FIFO overflow Event Cnt */
155 #define XM_RXF_JAB_PKT 0x0338 /* 32 bit r/o Rx Jabber Packet Frame Cnt */
156 #define XM_RXE_CAR_ERR 0x033c /* 32 bit r/o Rx Carrier Event Error Cnt */
157 #define XM_RXF_LEN_ERR 0x0340 /* 32 bit r/o Rx in Range Length Error */
158 #define XM_RXE_SYM_ERR 0x0344 /* 32 bit r/o Rx Symbol Error Counter */
159 #define XM_RXE_SHT_ERR 0x0348 /* 32 bit r/o Rx Short Event Error Cnt */
160 #define XM_RXE_RUNT 0x034c /* 32 bit r/o Rx Runt Event Counter */
161 #define XM_RXF_LNG_ERR 0x0350 /* 32 bit r/o Rx Frame too Long Error Cnt */
162 #define XM_RXF_FCS_ERR 0x0354 /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
163 /* 0x0358 - 0x035a: reserved */
164 #define XM_RXF_CEX_ERR 0x035c /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
165 #define XM_RXP_UTIL 0x0360 /* 32 bit r/o Rx Utilization in % */
166 /* 0x0364 - 0x0366: reserved */
167 #define XM_RXF_64B 0x0368 /* 32 bit r/o 64 Byte Rx Frame Counter */
168 #define XM_RXF_127B 0x036c /* 32 bit r/o 65-127 Byte Rx Frame Counter */
169 #define XM_RXF_255B 0x0370 /* 32 bit r/o 128-255 Byte Rx Frame Counter */
170 #define XM_RXF_511B 0x0374 /* 32 bit r/o 256-511 Byte Rx Frame Counter */
171 #define XM_RXF_1023B 0x0378 /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
172 #define XM_RXF_MAX_SZ 0x037c /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
173 /* 0x02e8 - 0x02fe: reserved */
176 /*----------------------------------------------------------------------------*/
178 * XMAC Bit Definitions
180 * If the bit access behaviour differs from the register access behaviour
181 * (r/w, r/o) this is documented after the bit number.
182 * The following bit access behaviours are used:
187 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
188 /* Bit 15..13: reserved */
189 #define XM_MMU_PHY_RDY (1<<12) /* Bit 12: PHY Read Ready */
190 #define XM_MMU_PHY_BUSY (1<<11) /* Bit 11: PHY Busy */
191 #define XM_MMU_IGN_PF (1<<10) /* Bit 10: Ignore Pause Frame */
192 #define XM_MMU_MAC_LB (1<<9) /* Bit 9: Enable MAC Loopback */
193 /* Bit 8: reserved */
194 #define XM_MMU_FRC_COL (1<<7) /* Bit 7: Force Collision */
195 #define XM_MMU_SIM_COL (1<<6) /* Bit 6: Simulate Collision */
196 #define XM_MMU_NO_PRE (1<<5) /* Bit 5: No MDIO Preamble */
197 #define XM_MMU_GMII_FD (1<<4) /* Bit 4: GMII uses Full Duplex */
198 #define XM_MMU_RAT_CTRL (1<<3) /* Bit 3: Enable Rate Control */
199 #define XM_MMU_GMII_LOOP (1<<2) /* Bit 2: PHY is in Loopback Mode */
200 #define XM_MMU_ENA_RX (1<<1) /* Bit 1: Enable Receiver */
201 #define XM_MMU_ENA_TX (1<<0) /* Bit 0: Enable Transmitter */
204 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
205 /* Bit 15..7: reserved */
206 #define XM_TX_BK2BK (1<<6) /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
207 #define XM_TX_ENC_BYP (1<<5) /* Bit 5: Set Encoder in Bypass Mode */
208 #define XM_TX_SAM_LINE (1<<4) /* Bit 4: (sc) Start utilization calculation */
209 #define XM_TX_NO_GIG_MD (1<<3) /* Bit 3: Disable Carrier Extension */
210 #define XM_TX_NO_PRE (1<<2) /* Bit 2: Disable Preamble Generation */
211 #define XM_TX_NO_CRC (1<<1) /* Bit 1: Disable CRC Generation */
212 #define XM_TX_AUTO_PAD (1<<0) /* Bit 0: Enable Automatic Padding */
215 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
216 /* Bit 15..5: reserved */
217 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
220 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
221 /* Bit 15..7: reserved */
222 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
225 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
226 /* Bit 15..8: reserved */
227 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
230 /* XM_RX_CMD 16 bit r/w Receive Command Register */
231 /* Bit 15..9: reserved */
232 #define XM_RX_LENERR_OK (1<<8) /* Bit 8 don't set Rx Err bit for */
233 /* inrange error packets */
234 #define XM_RX_BIG_PK_OK (1<<7) /* Bit 7 don't set Rx Err bit for */
236 #define XM_RX_IPG_CAP (1<<6) /* Bit 6 repl. type field with IPG */
237 #define XM_RX_TP_MD (1<<5) /* Bit 5: Enable transparent Mode */
238 #define XM_RX_STRIP_FCS (1<<4) /* Bit 4: Enable FCS Stripping */
239 #define XM_RX_SELF_RX (1<<3) /* Bit 3: Enable Rx of own packets */
240 #define XM_RX_SAM_LINE (1<<2) /* Bit 2: (sc) Start utilization calculation */
241 #define XM_RX_STRIP_PAD (1<<1) /* Bit 1: Strip pad bytes of Rx frames */
242 #define XM_RX_DIS_CEXT (1<<0) /* Bit 0: Disable carrier ext. check */
245 /* XM_PHY_ADDR 16 bit r/w PHY Address Register */
246 /* Bit 15..5: reserved */
247 #define XM_PHY_ADDR_SZ 0x1f /* Bit 4..0: PHY Address bits */
250 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
251 /* Bit 31..7: reserved */
252 #define XM_GP_ANIP (1L<<6) /* Bit 6: (ro) Auto-Neg. in progress */
253 #define XM_GP_FRC_INT (1L<<5) /* Bit 5: (sc) Force Interrupt */
254 /* Bit 4: reserved */
255 #define XM_GP_RES_MAC (1L<<3) /* Bit 3: (sc) Reset MAC and FIFOs */
256 #define XM_GP_RES_STAT (1L<<2) /* Bit 2: (sc) Reset the statistics module */
257 /* Bit 1: reserved */
258 #define XM_GP_INP_ASS (1L<<0) /* Bit 0: (ro) GP Input Pin asserted */
261 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
262 /* XM_ISRC 16 bit r/o Interrupt Status Register */
263 /* Bit 15: reserved */
264 #define XM_IS_LNK_AE (1<<14) /* Bit 14: Link Asynchronous Event */
265 #define XM_IS_TX_ABORT (1<<13) /* Bit 13: Transmit Abort, late Col. etc */
266 #define XM_IS_FRC_INT (1<<12) /* Bit 12: Force INT bit set in GP */
267 #define XM_IS_INP_ASS (1<<11) /* Bit 11: Input Asserted, GP bit 0 set */
268 #define XM_IS_LIPA_RC (1<<10) /* Bit 10: Link Partner requests config */
269 #define XM_IS_RX_PAGE (1<<9) /* Bit 9: Page Received */
270 #define XM_IS_TX_PAGE (1<<8) /* Bit 8: Next Page Loaded for Transmit */
271 #define XM_IS_AND (1<<7) /* Bit 7: Auto-Negotiation Done */
272 #define XM_IS_TSC_OV (1<<6) /* Bit 6: Time Stamp Counter Overflow */
273 #define XM_IS_RXC_OV (1<<5) /* Bit 5: Rx Counter Event Overflow */
274 #define XM_IS_TXC_OV (1<<4) /* Bit 4: Tx Counter Event Overflow */
275 #define XM_IS_RXF_OV (1<<3) /* Bit 3: Receive FIFO Overflow */
276 #define XM_IS_TXF_UR (1<<2) /* Bit 2: Transmit FIFO Underrun */
277 #define XM_IS_TX_COMP (1<<1) /* Bit 1: Frame Tx Complete */
278 #define XM_IS_RX_COMP (1<<0) /* Bit 0: Frame Rx Complete */
280 #define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE |\
281 XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | XM_IS_TXF_UR))
284 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
285 /* Bit 15.. 4: reserved */
286 #define XM_HW_GEN_EOP (1<<3) /* Bit 3: generate End of Packet pulse */
287 #define XM_HW_COM4SIG (1<<2) /* Bit 2: use Comma Detect for Sig. Det.*/
288 /* Bit 1: reserved */
289 #define XM_HW_GMII_MD (1<<0) /* Bit 0: GMII Interface selected */
292 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
293 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
294 /* Bit 15..10 reserved */
295 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
297 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
298 /* XM_HT_THR 16 bit r/w Host Request Threshold */
299 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
300 /* Bit 15..11 reserved */
301 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
304 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
305 #define XM_ST_VALID (1UL<<31) /* Bit 31: Status Valid */
306 #define XM_ST_BYTE_CNT (0x3fffL<<17) /* Bit 30..17: Tx frame Length */
307 #define XM_ST_RETRY_CNT (0x1fL<<12) /* Bit 16..12: Retry Count */
308 #define XM_ST_EX_COL (1L<<11) /* Bit 11: Excessive Collisions */
309 #define XM_ST_EX_DEF (1L<<10) /* Bit 10: Excessive Deferral */
310 #define XM_ST_BURST (1L<<9) /* Bit 9: p. xmitted in burst md*/
311 #define XM_ST_DEFER (1L<<8) /* Bit 8: packet was defered */
312 #define XM_ST_BC (1L<<7) /* Bit 7: Broadcast packet */
313 #define XM_ST_MC (1L<<6) /* Bit 6: Multicast packet */
314 #define XM_ST_UC (1L<<5) /* Bit 5: Unicast packet */
315 #define XM_ST_TX_UR (1L<<4) /* Bit 4: FIFO Underrun occured */
316 #define XM_ST_CS_ERR (1L<<3) /* Bit 3: Carrier Sense Error */
317 #define XM_ST_LAT_COL (1L<<2) /* Bit 2: Late Collision Error */
318 #define XM_ST_MUL_COL (1L<<1) /* Bit 1: Multiple Collisions */
319 #define XM_ST_SGN_COL (1L<<0) /* Bit 0: Single Collision */
321 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
322 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
323 /* Bit 15..11: reserved */
324 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
327 /* XM_DEV_ID 32 bit r/o Device ID Register */
328 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
329 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
332 /* XM_MODE 32 bit r/w Mode Register */
333 /* Bit 31..27: reserved */
334 #define XM_MD_ENA_REJ (1L<<26) /* Bit 26: Enable Frame Reject */
335 #define XM_MD_SPOE_E (1L<<25) /* Bit 25: Send Pause on Edge */
336 /* extern generated */
337 #define XM_MD_TX_REP (1L<<24) /* Bit 24: Transmit Repeater Mode */
338 #define XM_MD_SPOFF_I (1L<<23) /* Bit 23: Send Pause on FIFO full */
339 /* intern generated */
340 #define XM_MD_LE_STW (1L<<22) /* Bit 22: Rx Stat Word in Little Endian */
341 #define XM_MD_TX_CONT (1L<<21) /* Bit 21: Send Continuous */
342 #define XM_MD_TX_PAUSE (1L<<20) /* Bit 20: (sc) Send Pause Frame */
343 #define XM_MD_ATS (1L<<19) /* Bit 19: Append Time Stamp */
344 #define XM_MD_SPOL_I (1L<<18) /* Bit 18: Send Pause on Low */
345 /* intern generated */
346 #define XM_MD_SPOH_I (1L<<17) /* Bit 17: Send Pause on High */
347 /* intern generated */
348 #define XM_MD_CAP (1L<<16) /* Bit 16: Check Address Pair */
349 #define XM_MD_ENA_HASH (1L<<15) /* Bit 15: Enable Hashing */
350 #define XM_MD_CSA (1L<<14) /* Bit 14: Check Station Address */
351 #define XM_MD_CAA (1L<<13) /* Bit 13: Check Address Array */
352 #define XM_MD_RX_MCTRL (1L<<12) /* Bit 12: Rx MAC Control Frame */
353 #define XM_MD_RX_RUNT (1L<<11) /* Bit 11: Rx Runt Frames */
354 #define XM_MD_RX_IRLE (1L<<10) /* Bit 10: Rx in Range Len Err Frame */
355 #define XM_MD_RX_LONG (1L<<9) /* Bit 9: Rx Long Frame */
356 #define XM_MD_RX_CRCE (1L<<8) /* Bit 8: Rx CRC Error Frame */
357 #define XM_MD_RX_ERR (1L<<7) /* Bit 7: Rx Error Frame */
358 #define XM_MD_DIS_UC (1L<<6) /* Bit 6: Disable Rx Unicast */
359 #define XM_MD_DIS_MC (1L<<5) /* Bit 5: Disable Rx Multicast */
360 #define XM_MD_DIS_BC (1L<<4) /* Bit 4: Disable Rx Broadcast */
361 #define XM_MD_ENA_PROM (1L<<3) /* Bit 3: Enable Promiscuous */
362 #define XM_MD_ENA_BE (1L<<2) /* Bit 2: Enable Big Endian */
363 #define XM_MD_FTF (1L<<1) /* Bit 1: (sc) Flush Tx FIFO */
364 #define XM_MD_FRF (1L<<0) /* Bit 0: (sc) Flush Rx FIFO */
366 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
367 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
368 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA | XM_MD_CAA)
370 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
371 /* Bit 16..6: reserved */
372 #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */
373 #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */
374 #define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
375 #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */
376 #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */
377 #define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
380 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
381 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
382 #define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
383 #define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/
384 #define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/
385 #define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/
386 #define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */
387 #define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */
388 #define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */
389 #define XMR_UTIL_UR (1L<<24) /* Bit 24: Rx Util Cnt Underrun */
390 #define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */
391 /* Bit 22: reserved */
392 #define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */
393 #define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/
394 #define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */
395 #define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/
396 #define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */
397 /* Bit 16: reserved */
398 #define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */
399 #define XMR_JAB_PKT_OV (1L<<14) /* Bit 14: Rx Jabb Packet Cnt Ov */
400 #define XMR_FIFO_OV (1L<<13) /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
401 #define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */
402 #define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */
403 #define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */
404 #define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/
405 #define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */
406 #define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
407 #define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
408 #define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/
409 #define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */
410 #define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */
411 #define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/
412 #define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/
413 #define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */
415 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
417 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
418 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
419 /* Bit 31..26: reserved */
420 #define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
421 #define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/
422 #define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/
423 #define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/
424 #define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */
425 #define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */
426 #define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */
427 #define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */
428 #define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/
429 #define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
430 #define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */
431 #define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */
432 #define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */
433 #define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/
434 #define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */
435 #define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */
436 #define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/
437 #define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
438 #define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */
439 #define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */
440 #define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */
441 #define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */
442 #define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */
443 #define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/
444 #define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/
445 #define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */
447 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
450 * Receive Frame Status Encoding
452 #define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
453 #define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/
454 #define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/
455 #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */
456 #define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */
457 #define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */
458 /* Bit 12: reserved */
459 #define XMR_FS_BURST (1L<<11) /* Bit 11: Burst Mode */
460 #define XMR_FS_CEX_ERR (1L<<10) /* Bit 10: Carrier Ext. Error */
461 #define XMR_FS_802_3 (1L<<9) /* Bit 9: 802.3 Frame */
462 #define XMR_FS_COL_ERR (1L<<8) /* Bit 8: Collision Error */
463 #define XMR_FS_CAR_ERR (1L<<7) /* Bit 7: Carrier Event Error */
464 #define XMR_FS_LEN_ERR (1L<<6) /* Bit 6: In-Range Length Error */
465 #define XMR_FS_FRA_ERR (1L<<5) /* Bit 5: Framing Error */
466 #define XMR_FS_RUNT (1L<<4) /* Bit 4: Runt Frame */
467 #define XMR_FS_LNG_ERR (1L<<3) /* Bit 3: Giant (Jumbo) Frame */
468 #define XMR_FS_FCS_ERR (1L<<2) /* Bit 2: Frame Check Sequ Err */
469 #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */
470 #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */
473 * XMR_FS_ERR will be set if
474 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
475 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
476 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
477 * XMR_FS_ERR unless the corresponding bit in the Receive Command
480 #define XMR_FS_ANY_ERR XMR_FS_ERR
482 /*----------------------------------------------------------------------------*/
484 * XMAC-PHY Registers, indirect addressed over the XMAC
486 #define PHY_XMAC_CTRL 0x00 /* 16 bit r/w PHY Control Register */
487 #define PHY_XMAC_STAT 0x01 /* 16 bit r/w PHY Status Register */
488 #define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
489 #define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
490 #define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
491 #define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */
492 #define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
493 #define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */
494 #define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
495 /* 0x09 - 0x0e: reserved */
496 #define PHY_XMAC_EXT_STAT 0x0f /* 16 bit r/o Ext Status Register */
497 #define PHY_XMAC_RES_ABI 0x10 /* 16 bit r/o PHY Resolved Ability */
499 /*----------------------------------------------------------------------------*/
501 * Broadcom-PHY Registers, indirect addressed over XMAC
503 #define PHY_BCOM_CTRL 0x00 /* 16 bit r/w PHY Control Register */
504 #define PHY_BCOM_STAT 0x01 /* 16 bit r/o PHY Status Register */
505 #define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
506 #define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
507 #define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
508 #define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
509 #define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
510 #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */
511 #define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
512 /* Broadcom-specific registers */
513 #define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
514 #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
515 /* 0x0b - 0x0e: reserved */
516 #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
517 #define PHY_BCOM_P_EXT_CTRL 0x10 /* 16 bit r/w PHY Extended Ctrl Reg */
518 #define PHY_BCOM_P_EXT_STAT 0x11 /* 16 bit r/o PHY Extended Stat Reg */
519 #define PHY_BCOM_RE_CTR 0x12 /* 16 bit r/w Receive Error Counter */
520 #define PHY_BCOM_FC_CTR 0x13 /* 16 bit r/w False Carrier Sense Cnt */
521 #define PHY_BCOM_RNO_CTR 0x14 /* 16 bit r/w Receiver NOT_OK Cnt */
522 /* 0x15 - 0x17: reserved */
523 #define PHY_BCOM_AUX_CTRL 0x18 /* 16 bit r/w Auxiliary Control Reg */
524 #define PHY_BCOM_AUX_STAT 0x19 /* 16 bit r/o Auxiliary Stat Summary */
525 #define PHY_BCOM_INT_STAT 0x1a /* 16 bit r/o Interrupt Status Reg */
526 #define PHY_BCOM_INT_MASK 0x1b /* 16 bit r/w Interrupt Mask Reg */
528 /* 0x1d - 0x1f: test registers */
530 /*----------------------------------------------------------------------------*/
532 * Marvel-PHY Registers, indirect addressed over GMAC
534 #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */
535 #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */
536 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
537 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
538 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
539 #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
540 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
541 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
542 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
543 /* Marvel-specific registers */
544 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
545 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
546 /* 0x0b - 0x0e: reserved */
547 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
548 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */
549 #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */
550 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
551 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
552 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
553 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
554 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
556 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
557 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
558 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
559 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
560 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
561 /* 0x1d - 0x1f: reserved */
563 /*----------------------------------------------------------------------------*/
565 * Level One-PHY Registers, indirect addressed over XMAC
567 #define PHY_LONE_CTRL 0x00 /* 16 bit r/w PHY Control Register */
568 #define PHY_LONE_STAT 0x01 /* 16 bit r/o PHY Status Register */
569 #define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
570 #define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
571 #define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
572 #define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
573 #define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
574 #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */
575 #define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
576 /* Level One-specific registers */
577 #define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/
578 #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
579 /* 0x0b -0x0e: reserved */
580 #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
581 #define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/
582 #define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */
583 #define PHY_LONE_INT_ENAB 0x12 /* 16 bit r/w Interrupt Enable Reg */
584 #define PHY_LONE_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
585 #define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */
586 #define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */
587 #define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */
588 /* 0x17 -0x1c: reserved */
590 /*----------------------------------------------------------------------------*/
592 * National-PHY Registers, indirect addressed over XMAC
594 #define PHY_NAT_CTRL 0x00 /* 16 bit r/w PHY Control Register */
595 #define PHY_NAT_STAT 0x01 /* 16 bit r/w PHY Status Register */
596 #define PHY_NAT_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
597 #define PHY_NAT_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
598 #define PHY_NAT_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
599 #define PHY_NAT_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
600 #define PHY_NAT_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
601 #define PHY_NAT_NEPG 0x07 /* 16 bit r/w Next Page Register */
602 #define PHY_NAT_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner Reg */
603 /* National-specific registers */
604 #define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
605 #define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
606 /* 0x0b -0x0e: reserved */
607 #define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */
608 #define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */
609 #define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */
610 #define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */
611 #define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */
612 #define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */
613 /* 0x15 -0x18: reserved */
614 #define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */
617 /*----------------------------------------------------------------------------*/
620 * PHY bit definitions
621 * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
622 * XMAC/Broadcom/LevelOne/National/Marvell-specific.
623 * All other are general.
626 /***** PHY_XMAC_CTRL 16 bit r/w PHY Control Register *****/
627 /***** PHY_BCOM_CTRL 16 bit r/w PHY Control Register *****/
628 /***** PHY_MARV_CTRL 16 bit r/w PHY Status Register *****/
629 /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/
630 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */
631 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
632 #define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
633 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
634 #define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */
635 #define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */
636 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
637 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
638 #define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */
639 #define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */
640 /* Bit 5..0: reserved */
642 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */
643 #define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */
644 #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */
647 /***** PHY_XMAC_STAT 16 bit r/w PHY Status Register *****/
648 /***** PHY_BCOM_STAT 16 bit r/w PHY Status Register *****/
649 /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/
650 /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/
651 /* Bit 15..9: reserved */
652 /* (BC/L1) 100/10 Mbps cap bits ignored*/
653 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
654 /* Bit 7: reserved */
655 #define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */
656 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
657 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */
658 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
659 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
660 #define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */
661 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
664 /***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
665 /***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
666 /***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
667 /***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
668 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
669 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
670 #define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */
672 /* different Broadcom PHY Ids */
673 #define PHY_BCOM_ID1_A1 0x6041
674 #define PHY_BCOM_ID1_B2 0x6043
675 #define PHY_BCOM_ID1_C0 0x6044
676 #define PHY_BCOM_ID1_C5 0x6047
679 /***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
680 /***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
681 #define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */
682 #define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
683 #define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */
684 /* Bit 11.. 9: reserved */
685 #define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */
686 #define PHY_X_AN_HD (1<<6) /* Bit 6: Half Duplex */
687 #define PHY_X_AN_FD (1<<5) /* Bit 5: Full Duplex */
688 /* Bit 4.. 0: reserved */
690 /***** PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
691 /***** PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
692 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
693 /* Bit 14: reserved */
694 #define PHY_B_AN_RF (1<<13) /* Bit 13: Remote Fault */
695 /* Bit 12: reserved */
696 #define PHY_B_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */
697 #define PHY_B_AN_PC (1<<10) /* Bit 10: Pause Capable */
698 /* Bit 9..5: 100/10 BT cap bits ingnored */
699 #define PHY_B_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/
701 /***** PHY_LONE_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
702 /***** PHY_LONE_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
703 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
704 /* Bit 14: reserved */
705 #define PHY_L_AN_RF (1<<13) /* Bit 13: Remote Fault */
706 /* Bit 12: reserved */
707 #define PHY_L_AN_ASP (1<<11) /* Bit 11: Asymmetric Pause */
708 #define PHY_L_AN_PC (1<<10) /* Bit 10: Pause Capable */
709 /* Bit 9..5: 100/10 BT cap bits ingnored */
710 #define PHY_L_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/
712 /***** PHY_NAT_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
713 /***** PHY_NAT_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
714 /* PHY_AN_NXT_PG (see XMAC) Bit 15: Request Next Page */
715 /* Bit 14: reserved */
716 #define PHY_N_AN_RF (1<<13) /* Bit 13: Remote Fault */
717 /* Bit 12: reserved */
718 #define PHY_N_AN_100F (1<<11) /* Bit 11: 100Base-T2 FD Support */
719 #define PHY_N_AN_100H (1<<10) /* Bit 10: 100Base-T2 HD Support */
720 /* Bit 9..5: 100/10 BT cap bits ingnored */
721 #define PHY_N_AN_SEL 0x1f /* Bit 4..0: Selector Field, 00001=Ethernet*/
723 /* field type definition for PHY_x_AN_SEL */
724 #define PHY_SEL_TYPE 0x01 /* 00001 = Ethernet */
726 /***** PHY_XMAC_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/
727 /* Bit 15..4: reserved */
728 #define PHY_ANE_LP_NP (1<<3) /* Bit 3: Link Partner can Next Page */
729 #define PHY_ANE_LOC_NP (1<<2) /* Bit 2: Local PHY can Next Page */
730 #define PHY_ANE_RX_PG (1<<1) /* Bit 1: Page Received */
731 /* Bit 0: reserved */
733 /***** PHY_BCOM_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/
734 /***** PHY_LONE_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/
735 /***** PHY_MARV_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/
736 /* Bit 15..5: reserved */
737 #define PHY_ANE_PAR_DF (1<<4) /* Bit 4: Parallel Detection Fault */
738 /* PHY_ANE_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
739 /* PHY_ANE_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
740 /* PHY_ANE_RX_PG (see XMAC) Bit 1: Page Received */
741 #define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
743 /***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/
744 /***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/
745 /***** PHY_LONE_NEPG 16 bit r/w Next Page Register *****/
746 /***** PHY_XMAC_NEPG_LP 16 bit r/o Next Page Link Partner *****/
747 /***** PHY_BCOM_NEPG_LP 16 bit r/o Next Page Link Partner *****/
748 /***** PHY_LONE_NEPG_LP 16 bit r/o Next Page Link Partner *****/
749 #define PHY_NP_MORE (1<<15) /* Bit 15: More, Next Pages to follow */
750 #define PHY_NP_ACK1 (1<<14) /* Bit 14: (ro) Ack1, for receiving a message */
751 #define PHY_NP_MSG_VAL (1<<13) /* Bit 13: Message Page valid */
752 #define PHY_NP_ACK2 (1<<12) /* Bit 12: Ack2, comply with msg content */
753 #define PHY_NP_TOG (1<<11) /* Bit 11: Toggle Bit, ensure sync */
754 #define PHY_NP_MSG 0x07ff /* Bit 10..0: Message from/to Link Partner */
759 /***** PHY_XMAC_EXT_STAT 16 bit r/w Extended Status Register *****/
760 #define PHY_X_EX_FD (1<<15) /* Bit 15: Device Supports Full Duplex */
761 #define PHY_X_EX_HD (1<<14) /* Bit 14: Device Supports Half Duplex */
762 /* Bit 13..0: reserved */
764 /***** PHY_XMAC_RES_ABI 16 bit r/o PHY Resolved Ability *****/
765 /* Bit 15..9: reserved */
766 #define PHY_X_RS_PAUSE (3<<7) /* Bit 8..7: selected Pause Mode */
767 #define PHY_X_RS_HD (1<<6) /* Bit 6: Half Duplex Mode selected */
768 #define PHY_X_RS_FD (1<<5) /* Bit 5: Full Duplex Mode selected */
769 #define PHY_X_RS_ABLMIS (1<<4) /* Bit 4: duplex or pause cap mismatch */
770 #define PHY_X_RS_PAUMIS (1<<3) /* Bit 3: pause capability mismatch */
771 /* Bit 2..0: reserved */
773 * Remote Fault Bits (PHY_X_AN_RFB) encoding
775 #define X_RFB_OK (0<<12) /* Bit 13..12 No errors, Link OK */
776 #define X_RFB_LF (1<<12) /* Bit 13..12 Link Failure */
777 #define X_RFB_OFF (2<<12) /* Bit 13..12 Offline */
778 #define X_RFB_AN_ERR (3<<12) /* Bit 13..12 Auto-Negotiation Error */
781 * Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding
783 #define PHY_X_P_NO_PAUSE (0<<7) /* Bit 8..7: no Pause Mode */
784 #define PHY_X_P_SYM_MD (1<<7) /* Bit 8..7: symmetric Pause Mode */
785 #define PHY_X_P_ASYM_MD (2<<7) /* Bit 8..7: asymmetric Pause Mode */
786 #define PHY_X_P_BOTH_MD (3<<7) /* Bit 8..7: both Pause Mode */
792 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
793 #define PHY_B_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
794 #define PHY_B_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
795 #define PHY_B_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
796 #define PHY_B_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
797 #define PHY_B_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
798 #define PHY_B_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
799 /* Bit 7..0: reserved */
801 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
802 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
803 #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
804 #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
805 #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
806 #define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */
807 #define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
808 #define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
809 /* Bit 9..8: reserved */
810 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
812 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
813 #define PHY_B_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
814 #define PHY_B_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
815 #define PHY_B_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
816 #define PHY_B_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
817 /* Bit 11..0: reserved */
819 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
820 #define PHY_B_PEC_MAC_PHY (1<<15) /* Bit 15: 10BIT/GMI-Interface */
821 #define PHY_B_PEC_DIS_CROSS (1<<14) /* Bit 14: Disable MDI Crossover */
822 #define PHY_B_PEC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */
823 #define PHY_B_PEC_INT_DIS (1<<12) /* Bit 12: Interrupts Disabled */
824 #define PHY_B_PEC_F_INT (1<<11) /* Bit 11: Force Interrupt */
825 #define PHY_B_PEC_BY_45 (1<<10) /* Bit 10: Bypass 4B5B-Decoder */
826 #define PHY_B_PEC_BY_SCR (1<<9) /* Bit 9: Bypass Scrambler */
827 #define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */
828 #define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */
829 #define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */
830 #define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */
831 #define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */
832 #define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */
833 #define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */
834 #define PHY_B_PEC_3_LED (1<<1) /* Bit 1: Three Link LED mode */
835 #define PHY_B_PEC_HIGH_LA (1<<0) /* Bit 0: GMII FIFO Elasticy */
837 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
838 /* Bit 15..14: reserved */
839 #define PHY_B_PES_CROSS_STAT (1<<13) /* Bit 13: MDI Crossover Status */
840 #define PHY_B_PES_INT_STAT (1<<12) /* Bit 12: Interrupt Status */
841 #define PHY_B_PES_RRS (1<<11) /* Bit 11: Remote Receiver Stat. */
842 #define PHY_B_PES_LRS (1<<10) /* Bit 10: Local Receiver Stat. */
843 #define PHY_B_PES_LOCKED (1<<9) /* Bit 9: Locked */
844 #define PHY_B_PES_LS (1<<8) /* Bit 8: Link Status */
845 #define PHY_B_PES_RF (1<<7) /* Bit 7: Remote Fault */
846 #define PHY_B_PES_CE_ER (1<<6) /* Bit 6: Carrier Ext Error */
847 #define PHY_B_PES_BAD_SSD (1<<5) /* Bit 5: Bad SSD */
848 #define PHY_B_PES_BAD_ESD (1<<4) /* Bit 4: Bad ESD */
849 #define PHY_B_PES_RX_ER (1<<3) /* Bit 3: Receive Error */
850 #define PHY_B_PES_TX_ER (1<<2) /* Bit 2: Transmit Error */
851 #define PHY_B_PES_LOCK_ER (1<<1) /* Bit 1: Lock Error */
852 #define PHY_B_PES_MLT3_ER (1<<0) /* Bit 0: MLT3 code Error */
854 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
855 /* Bit 15..8: reserved */
856 #define PHY_B_FC_CTR 0xff /* Bit 7..0: False Carrier Counter */
858 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
859 #define PHY_B_RC_LOC_MSK 0xff00 /* Bit 15..8: Local Rx NOT_OK cnt */
860 #define PHY_B_RC_REM_MSK 0x00ff /* Bit 7..0: Remote Rx NOT_OK cnt */
862 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
863 #define PHY_B_AC_L_SQE (1<<15) /* Bit 15: Low Squelch */
864 #define PHY_B_AC_LONG_PACK (1<<14) /* Bit 14: Rx Long Packets */
865 #define PHY_B_AC_ER_CTRL (3<<12) /* Bit 13..12: Edgerate Control */
866 /* Bit 11: reserved */
867 #define PHY_B_AC_TX_TST (1<<10) /* Bit 10: Tx test bit, always 1 */
868 /* Bit 9.. 8: reserved */
869 #define PHY_B_AC_DIS_PRF (1<<7) /* Bit 7: dis part resp filter */
870 /* Bit 6: reserved */
871 #define PHY_B_AC_DIS_PM (1<<5) /* Bit 5: dis power management */
872 /* Bit 4: reserved */
873 #define PHY_B_AC_DIAG (1<<3) /* Bit 3: Diagnostic Mode */
874 /* Bit 2.. 0: reserved */
876 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
877 #define PHY_B_AS_AN_C (1<<15) /* Bit 15: AutoNeg complete */
878 #define PHY_B_AS_AN_CA (1<<14) /* Bit 14: AN Complete Ack */
879 #define PHY_B_AS_ANACK_D (1<<13) /* Bit 13: AN Ack Detect */
880 #define PHY_B_AS_ANAB_D (1<<12) /* Bit 12: AN Ability Detect */
881 #define PHY_B_AS_NPW (1<<11) /* Bit 11: AN Next Page Wait */
882 #define PHY_B_AS_AN_RES_MSK (7<<8) /* Bit 10..8: AN HDC */
883 #define PHY_B_AS_PDF (1<<7) /* Bit 7: Parallel Detect. Fault */
884 #define PHY_B_AS_RF (1<<6) /* Bit 6: Remote Fault */
885 #define PHY_B_AS_ANP_R (1<<5) /* Bit 5: AN Page Received */
886 #define PHY_B_AS_LP_ANAB (1<<4) /* Bit 4: LP AN Ability */
887 #define PHY_B_AS_LP_NPAB (1<<3) /* Bit 3: LP Next Page Ability */
888 #define PHY_B_AS_LS (1<<2) /* Bit 2: Link Status */
889 #define PHY_B_AS_PRR (1<<1) /* Bit 1: Pause Resolution-Rx */
890 #define PHY_B_AS_PRT (1<<0) /* Bit 0: Pause Resolution-Tx */
892 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
894 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
895 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
896 /* Bit 15: reserved */
897 #define PHY_B_IS_PSE (1<<14) /* Bit 14: Pair Swap Error */
898 #define PHY_B_IS_MDXI_SC (1<<13) /* Bit 13: MDIX Status Change */
899 #define PHY_B_IS_HCT (1<<12) /* Bit 12: counter above 32k */
900 #define PHY_B_IS_LCT (1<<11) /* Bit 11: counter above 128 */
901 #define PHY_B_IS_AN_PR (1<<10) /* Bit 10: Page Received */
902 #define PHY_B_IS_NO_HDCL (1<<9) /* Bit 9: No HCD Link */
903 #define PHY_B_IS_NO_HDC (1<<8) /* Bit 8: No HCD */
904 #define PHY_B_IS_NEG_USHDC (1<<7) /* Bit 7: Negotiated Unsup. HCD */
905 #define PHY_B_IS_SCR_S_ER (1<<6) /* Bit 6: Scrambler Sync Error */
906 #define PHY_B_IS_RRS_CHANGE (1<<5) /* Bit 5: Remote Rx Stat Change */
907 #define PHY_B_IS_LRS_CHANGE (1<<4) /* Bit 4: Local Rx Stat Change */
908 #define PHY_B_IS_DUP_CHANGE (1<<3) /* Bit 3: Duplex Mode Change */
909 #define PHY_B_IS_LSP_CHANGE (1<<2) /* Bit 2: Link Speed Change */
910 #define PHY_B_IS_LST_CHANGE (1<<1) /* Bit 1: Link Status Changed */
911 #define PHY_B_IS_CRC_ER (1<<0) /* Bit 0: CRC Error */
913 #define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
915 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
916 #define PHY_B_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */
917 #define PHY_B_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */
918 #define PHY_B_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
919 #define PHY_B_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
922 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
924 #define PHY_B_RES_1000FD (7<<8) /* Bit 10..8: 1000Base-T Full Dup. */
925 #define PHY_B_RES_1000HD (6<<8) /* Bit 10..8: 1000Base-T Half Dup. */
926 /* others: 100/10: invalid for us */
931 /***** PHY_LONE_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
932 #define PHY_L_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
933 #define PHY_L_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
934 #define PHY_L_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
935 #define PHY_L_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
936 #define PHY_L_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
937 #define PHY_L_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
938 /* Bit 7..0: reserved */
940 /***** PHY_LONE_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
941 #define PHY_L_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
942 #define PHY_L_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
943 #define PHY_L_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
944 #define PHY_L_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */
945 #define PHY_L_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
946 #define PHY_L_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
947 /* Bit 9..8: reserved */
948 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
950 /***** PHY_LONE_EXT_STAT 16 bit r/o Extended Status Register *****/
951 #define PHY_L_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
952 #define PHY_L_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
953 #define PHY_L_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
954 #define PHY_L_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
955 /* Bit 11..0: reserved */
957 /***** PHY_LONE_PORT_CFG 16 bit r/w Port Configuration Reg *****/
958 #define PHY_L_PC_REP_MODE (1<<15) /* Bit 15: Repeater Mode */
959 /* Bit 14: reserved */
960 #define PHY_L_PC_TX_DIS (1<<13) /* Bit 13: Tx output Disabled */
961 #define PHY_L_PC_BY_SCR (1<<12) /* Bit 12: Bypass Scrambler */
962 #define PHY_L_PC_BY_45 (1<<11) /* Bit 11: Bypass 4B5B-Decoder */
963 #define PHY_L_PC_JAB_DIS (1<<10) /* Bit 10: Jabber Disabled */
964 #define PHY_L_PC_SQE (1<<9) /* Bit 9: Enable Heartbeat */
965 #define PHY_L_PC_TP_LOOP (1<<8) /* Bit 8: TP Loopback */
966 #define PHY_L_PC_SSS (1<<7) /* Bit 7: Smart Speed Selection */
967 #define PHY_L_PC_FIFO_SIZE (1<<6) /* Bit 6: FIFO Size */
968 #define PHY_L_PC_PRE_EN (1<<5) /* Bit 5: Preamble Enable */
969 #define PHY_L_PC_CIM (1<<4) /* Bit 4: Carrier Integrity Mon */
970 #define PHY_L_PC_10_SER (1<<3) /* Bit 3: Use Serial Output */
971 #define PHY_L_PC_ANISOL (1<<2) /* Bit 2: Unisolate Port */
972 #define PHY_L_PC_TEN_BIT (1<<1) /* Bit 1: 10bit iface mode on */
973 #define PHY_L_PC_ALTCLOCK (1<<0) /* Bit 0: (ro) ALTCLOCK Mode on */
975 /***** PHY_LONE_Q_STAT 16 bit r/o Quick Status Reg *****/
976 #define PHY_L_QS_D_RATE (3<<14) /* Bit 15..14: Data Rate */
977 #define PHY_L_QS_TX_STAT (1<<13) /* Bit 13: Transmitting */
978 #define PHY_L_QS_RX_STAT (1<<12) /* Bit 12: Receiving */
979 #define PHY_L_QS_COL_STAT (1<<11) /* Bit 11: Collision */
980 #define PHY_L_QS_L_STAT (1<<10) /* Bit 10: Link is up */
981 #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */
982 #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */
983 #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */
984 #define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */
985 #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */
986 #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */
987 #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */
988 #define PHY_L_QS_EVENT (1<<0) /* Bit 0: Event has occurred */
990 /***** PHY_LONE_INT_ENAB 16 bit r/w Interrupt Enable Reg *****/
991 /***** PHY_LONE_INT_STAT 16 bit r/o Interrupt Status Reg *****/
992 /* Bit 15..14: reserved */
993 #define PHY_L_IS_AN_F (1<<13) /* Bit 13: Auto-Negotiation fault */
994 /* Bit 12: not described */
995 #define PHY_L_IS_CROSS (1<<11) /* Bit 11: Crossover used */
996 #define PHY_L_IS_POL (1<<10) /* Bit 10: Polarity correct. used */
997 #define PHY_L_IS_SS (1<<9) /* Bit 9: Smart Speed Downgrade */
998 #define PHY_L_IS_CFULL (1<<8) /* Bit 8: Counter Full */
999 #define PHY_L_IS_AN_C (1<<7) /* Bit 7: AutoNeg Complete */
1000 #define PHY_L_IS_SPEED (1<<6) /* Bit 6: Speed Changed */
1001 #define PHY_L_IS_DUP (1<<5) /* Bit 5: Duplex Changed */
1002 #define PHY_L_IS_LS (1<<4) /* Bit 4: Link Status Changed */
1003 #define PHY_L_IS_ISOL (1<<3) /* Bit 3: Isolate Occured */
1004 #define PHY_L_IS_MDINT (1<<2) /* Bit 2: (ro) STAT: MII Int Pending */
1005 #define PHY_L_IS_INTEN (1<<1) /* Bit 1: ENAB: Enable IRQs */
1006 #define PHY_L_IS_FORCE (1<<0) /* Bit 0: ENAB: Force Interrupt */
1009 #define PHY_L_DEF_MSK (PHY_L_IS_LS | PHY_L_IS_ISOL | PHY_L_IS_INTEN)
1011 /***** PHY_LONE_LED_CFG 16 bit r/w LED Configuration Reg *****/
1012 #define PHY_L_LC_LEDC (3<<14) /* Bit 15..14: Col/Blink/On/Off */
1013 #define PHY_L_LC_LEDR (3<<12) /* Bit 13..12: Rx/Blink/On/Off */
1014 #define PHY_L_LC_LEDT (3<<10) /* Bit 11..10: Tx/Blink/On/Off */
1015 #define PHY_L_LC_LEDG (3<<8) /* Bit 9..8: Giga/Blink/On/Off */
1016 #define PHY_L_LC_LEDS (3<<6) /* Bit 7..6: 10-100/Blink/On/Off */
1017 #define PHY_L_LC_LEDL (3<<4) /* Bit 5..4: Link/Blink/On/Off */
1018 #define PHY_L_LC_LEDF (3<<2) /* Bit 3..2: Duplex/Blink/On/Off */
1019 #define PHY_L_LC_PSTRECH (1<<1) /* Bit 1: Strech LED Pulses */
1020 #define PHY_L_LC_FREQ (1<<0) /* Bit 0: 30/100 ms */
1022 /***** PHY_LONE_PORT_CTRL 16 bit r/w Port Control Reg *****/
1023 #define PHY_L_PC_TX_TCLK (1<<15) /* Bit 15: Enable TX_TCLK */
1024 /* Bit 14: reserved */
1025 #define PHY_L_PC_ALT_NP (1<<13) /* Bit 14: Alternate Next Page */
1026 #define PHY_L_PC_GMII_ALT (1<<12) /* Bit 13: Alternate GMII driver */
1027 /* Bit 11: reserved */
1028 #define PHY_L_PC_TEN_CRS (1<<10) /* Bit 10: Extend CRS*/
1029 /* Bit 9..0: not described */
1031 /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
1032 #define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */
1033 #define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */
1037 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
1039 #define PHY_L_P_NO_PAUSE (0<<10) /* Bit 11..10: no Pause Mode */
1040 #define PHY_L_P_SYM_MD (1<<10) /* Bit 11..10: symmetric Pause Mode */
1041 #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
1042 #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
1048 /***** PHY_NAT_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1049 #define PHY_N_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
1050 #define PHY_N_1000C_MSE (1<<12) /* Bit 12: Master/Slave Enable */
1051 #define PHY_N_1000C_MSC (1<<11) /* Bit 11: M/S Configuration */
1052 #define PHY_N_1000C_RD (1<<10) /* Bit 10: Repeater/DTE */
1053 #define PHY_N_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
1054 #define PHY_N_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
1055 #define PHY_N_1000C_APC (1<<7) /* Bit 7: Asymmetric Pause Cap. */
1056 /* Bit 6..0: reserved */
1058 /***** PHY_NAT_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1059 #define PHY_N_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */
1060 #define PHY_N_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */
1061 #define PHY_N_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */
1062 #define PHY_N_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status*/
1063 #define PHY_N_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */
1064 #define PHY_N_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */
1065 #define PHY_N_1000C_LP_APC (1<<9) /* Bit 9: LP Asym. Pause Cap. */
1066 /* Bit 8: reserved */
1067 #define PHY_N_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */
1069 /***** PHY_NAT_EXT_STAT 16 bit r/o Extended Status Register *****/
1070 #define PHY_N_ES_X_FD_CAP (1<<15) /* Bit 15: 1000Base-X FD capable */
1071 #define PHY_N_ES_X_HD_CAP (1<<14) /* Bit 14: 1000Base-X HD capable */
1072 #define PHY_N_ES_T_FD_CAP (1<<13) /* Bit 13: 1000Base-T FD capable */
1073 #define PHY_N_ES_T_HD_CAP (1<<12) /* Bit 12: 1000Base-T HD capable */
1074 /* Bit 11..0: reserved */
1076 /* todo: those are still missing */
1077 /***** PHY_NAT_EXT_CTRL1 16 bit r/o Extended Control Reg1 *****/
1078 /***** PHY_NAT_Q_STAT1 16 bit r/o Quick Status Reg1 *****/
1079 /***** PHY_NAT_10B_OP 16 bit r/o 10Base-T Operations Reg *****/
1080 /***** PHY_NAT_EXT_CTRL2 16 bit r/o Extended Control Reg1 *****/
1081 /***** PHY_NAT_Q_STAT2 16 bit r/o Quick Status Reg2 *****/
1082 /***** PHY_NAT_PHY_ADDR 16 bit r/o PHY Address Register *****/
1087 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1088 /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/
1089 #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
1090 #define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */
1091 #define PHY_M_AN_RF BIT_13 /* Remote Fault */
1092 /* Bit 12: reserved */
1093 #define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
1094 #define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */
1095 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
1096 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
1097 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
1098 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
1100 /* special defines for FIBER (88E1011S only) */
1101 #define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */
1102 #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
1103 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
1104 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
1106 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1107 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
1108 #define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */
1109 #define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */
1110 #define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */
1112 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1113 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
1114 #define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */
1115 #define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */
1116 #define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */
1117 #define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
1118 #define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
1119 /* Bit 7..0: reserved */
1121 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1122 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
1123 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
1124 #define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */
1125 #define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */
1126 #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
1127 #define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */
1128 #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
1129 #define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */
1130 #define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */
1131 #define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */
1132 #define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */
1133 #define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */
1135 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */
1136 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */
1138 #define PHY_M_PC_MDI_XMODE(x) SHIFT5(x)
1139 #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
1140 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */
1141 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
1143 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1144 #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
1145 #define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */
1146 #define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */
1147 #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
1148 #define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */
1149 #define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */
1150 #define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */
1151 #define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */
1152 #define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */
1153 #define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */
1154 #define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */
1155 #define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */
1156 #define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */
1157 #define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */
1158 #define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */
1159 #define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */
1161 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1163 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1164 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1165 #define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */
1166 #define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */
1167 #define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */
1168 #define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */
1169 #define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */
1170 #define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */
1171 #define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */
1172 #define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */
1173 #define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */
1174 #define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */
1175 #define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */
1176 #define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */
1177 /* Bit 3..2: reserved */
1178 #define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */
1179 #define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */
1181 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
1182 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
1184 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1185 #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */
1186 #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */
1187 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */
1188 #define PHY_M_EC_FIB_AN_ENA (1<<3) /* Bit 3: Fiber Auto-Neg. Enable */
1190 #define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */
1191 #define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */
1192 #define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */
1194 #define MAC_TX_CLK_0_MHZ 2
1195 #define MAC_TX_CLK_2_5_MHZ 6
1196 #define MAC_TX_CLK_25_MHZ 7
1198 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1199 #define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */
1200 #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
1201 #define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */
1202 #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
1203 /* Bit 7.. 5: reserved */
1204 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
1205 #define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */
1206 #define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */
1207 #define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */
1209 #define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */
1211 #define PULS_NO_STR 0 /* no pulse stretching */
1212 #define PULS_21MS 1 /* 21 ms to 42 ms */
1213 #define PULS_42MS 2 /* 42 ms to 84 ms */
1214 #define PULS_84MS 3 /* 84 ms to 170 ms */
1215 #define PULS_170MS 4 /* 170 ms to 340 ms */
1216 #define PULS_340MS 5 /* 340 ms to 670 ms */
1217 #define PULS_670MS 6 /* 670 ms to 1.3 s */
1218 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */
1220 #define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */
1222 #define BLINK_42MS 0 /* 42 ms */
1223 #define BLINK_84MS 1 /* 84 ms */
1224 #define BLINK_170MS 2 /* 170 ms */
1225 #define BLINK_340MS 3 /* 340 ms */
1226 #define BLINK_670MS 4 /* 670 ms */
1227 /* values 5 - 7: reserved */
1229 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1230 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */
1231 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */
1232 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */
1233 #define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */
1234 #define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */
1235 #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */
1237 #define MO_LED_NORM 0
1238 #define MO_LED_BLINK 1
1239 #define MO_LED_OFF 2
1242 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1243 /* Bit 15.. 7: reserved */
1244 #define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */
1245 #define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */
1246 #define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */
1247 #define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */
1248 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
1250 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1251 #define PHY_M_FC_AUTO_SEL (1<<15) /* Bit 15: Fiber/Copper Auto Sel. dis. */
1252 #define PHY_M_FC_AN_REG_ACC (1<<14) /* Bit 14: Fiber/Copper Autoneg. reg acc */
1253 #define PHY_M_FC_RESULUTION (1<<13) /* Bit 13: Fiber/Copper Resulution */
1254 #define PHY_M_SER_IF_AN_BP (1<<12) /* Bit 12: Ser IF autoneg. bypass enable */
1255 #define PHY_M_SER_IF_BP_ST (1<<11) /* Bit 11: Ser IF autoneg. bypass status */
1256 #define PHY_M_IRQ_POLARITY (1<<10) /* Bit 10: IRQ polarity */
1257 /* Bit 9..4: reserved */
1258 #define PHY_M_UNDOC1 (1<< 7) /* undocumented bit !! */
1259 #define PHY_M_MODE_MASK (0xf<<0)/* Bit 3..0: copy of HWCFG MODE[3:0] */
1262 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1263 #define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */
1264 #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */
1265 /* Bit 12.. 8: reserved */
1266 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */
1268 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1269 #define CABD_STAT_NORMAL 0
1270 #define CABD_STAT_SHORT 1
1271 #define CABD_STAT_OPEN 2
1272 #define CABD_STAT_FAIL 3
1278 * The GMAC registers are 16 or 32 bits wide.
1279 * The GMACs host processor interface is 16 bits wide,
1280 * therefore ALL registers will be addressed with 16 bit accesses.
1282 * The following macros are provided to access the GMAC registers
1283 * GM_IN16(), GM_OUT16, GM_IN32(), GM_OUT32(), GM_INADR(), GM_OUTADR(),
1284 * GM_INHASH(), and GM_OUTHASH().
1285 * The macros are defined in SkGeHw.h.
1287 * Note: NA reg = Network Address e.g DA, SA etc.
1291 /* Port Registers */
1292 #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */
1293 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */
1294 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */
1295 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */
1296 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1297 #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */
1298 #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */
1300 /* Source Address Registers */
1301 #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */
1302 #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */
1303 #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */
1304 #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */
1305 #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */
1306 #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */
1308 /* Multicast Address Hash Registers */
1309 #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */
1310 #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */
1311 #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */
1312 #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */
1314 /* Interrupt Source Registers */
1315 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */
1316 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */
1317 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */
1319 /* Interrupt Mask Registers */
1320 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */
1321 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */
1322 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1324 /* Serial Management Interface (SMI) Registers */
1325 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */
1326 #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */
1327 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */
1330 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1331 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1334 * MIB Counters base address definitions (low word) -
1335 * use offset 4 for access to high word (32 bit r/o)
1337 #define GM_RXF_UC_OK \
1338 (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */
1339 #define GM_RXF_BC_OK \
1340 (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */
1341 #define GM_RXF_MPAUSE \
1342 (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */
1343 #define GM_RXF_MC_OK \
1344 (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */
1345 #define GM_RXF_FCS_ERR \
1346 (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */
1347 /* GM_MIB_CNT_BASE + 40: reserved */
1348 #define GM_RXO_OK_LO \
1349 (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */
1350 #define GM_RXO_OK_HI \
1351 (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */
1352 #define GM_RXO_ERR_LO \
1353 (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */
1354 #define GM_RXO_ERR_HI \
1355 (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */
1356 #define GM_RXF_SHT \
1357 (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */
1358 #define GM_RXE_FRAG \
1359 (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */
1360 #define GM_RXF_64B \
1361 (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */
1362 #define GM_RXF_127B \
1363 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1364 #define GM_RXF_255B \
1365 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1366 #define GM_RXF_511B \
1367 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1368 #define GM_RXF_1023B \
1369 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1370 #define GM_RXF_1518B \
1371 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1372 #define GM_RXF_MAX_SZ \
1373 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1374 #define GM_RXF_LNG_ERR \
1375 (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */
1376 #define GM_RXF_JAB_PKT \
1377 (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */
1378 /* GM_MIB_CNT_BASE + 168: reserved */
1379 #define GM_RXE_FIFO_OV \
1380 (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */
1381 /* GM_MIB_CNT_BASE + 184: reserved */
1382 #define GM_TXF_UC_OK \
1383 (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */
1384 #define GM_TXF_BC_OK \
1385 (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */
1386 #define GM_TXF_MPAUSE \
1387 (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */
1388 #define GM_TXF_MC_OK \
1389 (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */
1390 #define GM_TXO_OK_LO \
1391 (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */
1392 #define GM_TXO_OK_HI \
1393 (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */
1394 #define GM_TXF_64B \
1395 (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */
1396 #define GM_TXF_127B \
1397 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1398 #define GM_TXF_255B \
1399 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1400 #define GM_TXF_511B \
1401 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1402 #define GM_TXF_1023B \
1403 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1404 #define GM_TXF_1518B \
1405 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1406 #define GM_TXF_MAX_SZ \
1407 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1408 /* GM_MIB_CNT_BASE + 296: reserved */
1409 #define GM_TXF_COL \
1410 (GM_MIB_CNT_BASE + 304) /* Tx Collision */
1411 #define GM_TXF_LAT_COL \
1412 (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */
1413 #define GM_TXF_ABO_COL \
1414 (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */
1415 #define GM_TXF_MUL_COL \
1416 (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */
1417 #define GM_TXF_SNG_COL \
1418 (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */
1419 #define GM_TXE_FIFO_UR \
1420 (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */
1422 /*----------------------------------------------------------------------------*/
1424 * GMAC Bit Definitions
1426 * If the bit access behaviour differs from the register access behaviour
1427 * (r/w, r/o) this is documented after the bit number.
1428 * The following bit access behaviours are used:
1429 * (sc) self clearing
1433 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1434 #define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */
1435 #define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */
1436 #define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow-Control Mode Disabled */
1437 #define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */
1438 #define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */
1439 #define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */
1440 #define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */
1441 #define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */
1442 /* Bit 7..6: reserved */
1443 #define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */
1444 #define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1445 #define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */
1446 #define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow-Control Mode Disabled */
1447 #define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */
1448 /* Bit 0: reserved */
1450 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1451 /* Bit 15: reserved */
1452 #define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */
1453 #define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow-Control Mode */
1454 #define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */
1455 #define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */
1456 #define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */
1457 #define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */
1458 #define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */
1459 #define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */
1460 #define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */
1461 #define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */
1462 #define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow-Control Mode */
1463 #define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */
1464 #define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update Duplex */
1465 #define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update Flow-C. */
1466 #define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update Speed */
1468 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1469 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
1472 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1473 #define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */
1474 #define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */
1475 #define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */
1476 #define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold */
1478 #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
1480 #define TX_COL_DEF 0x04
1482 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1483 #define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */
1484 #define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */
1485 #define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */
1486 #define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */
1488 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1489 #define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */
1490 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */
1491 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */
1492 /* Bit 3..0: reserved */
1494 #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
1495 #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
1496 #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
1498 #define TX_JAM_LEN_DEF 0x03
1499 #define TX_JAM_IPG_DEF 0x0b
1500 #define TX_IPG_JAM_DEF 0x1c
1502 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1503 #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder (r/o) */
1504 #define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive Tx trials */
1505 #define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Len) */
1506 #define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Len) */
1507 /* Bit 7..5: reserved */
1508 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1510 #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK)
1511 #define DATA_BLIND_DEF 0x04
1513 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1514 #define IPG_DATA_DEF 0x1e
1516 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1517 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */
1518 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */
1519 #define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/
1520 #define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */
1521 #define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */
1522 /* Bit 2..0: reserved */
1524 #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
1525 #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
1527 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1528 /* Bit 15..6: reserved */
1529 #define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */
1530 #define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */
1531 /* Bit 3..0: reserved */
1533 /* Receive Frame Status Encoding */
1534 #define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
1535 /* Bit 15..14: reserved */
1536 #define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */
1537 #define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */
1538 #define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */
1539 #define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */
1540 #define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */
1541 #define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */
1542 #define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */
1543 #define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */
1544 #define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */
1545 #define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */
1546 #define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */
1547 /* Bit 2: reserved */
1548 #define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */
1549 #define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */
1552 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1554 #define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \
1561 /* Rx GMAC FIFO Flush Mask (default) */
1562 #define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \
1570 /* typedefs *******************************************************************/
1573 /* function prototypes ********************************************************/
1577 #endif /* __cplusplus */
1579 #endif /* __INC_XMAC_H */
git.openpandora.org / pandora-kernel.git / blob