drivers/net/sfc/falcon.c

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/pci.h>
  14 #include <linux/module.h>
  15 #include <linux/seq_file.h>
  16 #include <linux/i2c.h>
  17 #include <linux/i2c-algo-bit.h>
  18 #include "net_driver.h"
  19 #include "bitfield.h"
  20 #include "efx.h"
  21 #include "mac.h"
  22 #include "gmii.h"
  23 #include "spi.h"
  24 #include "falcon.h"
  25 #include "falcon_hwdefs.h"
  26 #include "falcon_io.h"
  27 #include "mdio_10g.h"
  28 #include "phy.h"
  29 #include "boards.h"
  30 #include "workarounds.h"
  31
  32 /* Falcon hardware control.
  33  * Falcon is the internal codename for the SFC4000 controller that is
  34  * present in SFE400X evaluation boards
  35  */
  36
  37 /**
  38  * struct falcon_nic_data - Falcon NIC state
  39  * @next_buffer_table: First available buffer table id
  40  * @pci_dev2: The secondary PCI device if present
  41  * @i2c_data: Operations and state for I2C bit-bashing algorithm
  42  */
  43 struct falcon_nic_data {
  44         unsigned next_buffer_table;
  45         struct pci_dev *pci_dev2;
  46         struct i2c_algo_bit_data i2c_data;
  47 };
  48
  49 /**************************************************************************
  50  *
  51  * Configurable values
  52  *
  53  **************************************************************************
  54  */
  55
  56 static int disable_dma_stats;
  57
  58 /* This is set to 16 for a good reason.  In summary, if larger than
  59  * 16, the descriptor cache holds more than a default socket
  60  * buffer's worth of packets (for UDP we can only have at most one
  61  * socket buffer's worth outstanding).  This combined with the fact
  62  * that we only get 1 TX event per descriptor cache means the NIC
  63  * goes idle.
  64  */
  65 #define TX_DC_ENTRIES 16
  66 #define TX_DC_ENTRIES_ORDER 0
  67 #define TX_DC_BASE 0x130000
  68
  69 #define RX_DC_ENTRIES 64
  70 #define RX_DC_ENTRIES_ORDER 2
  71 #define RX_DC_BASE 0x100000
  72
  73 /* RX FIFO XOFF watermark
  74  *
  75  * When the amount of the RX FIFO increases used increases past this
  76  * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
  77  * This also has an effect on RX/TX arbitration
  78  */
  79 static int rx_xoff_thresh_bytes = -1;
  80 module_param(rx_xoff_thresh_bytes, int, 0644);
  81 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
  82
  83 /* RX FIFO XON watermark
  84  *
  85  * When the amount of the RX FIFO used decreases below this
  86  * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
  87  * This also has an effect on RX/TX arbitration
  88  */
  89 static int rx_xon_thresh_bytes = -1;
  90 module_param(rx_xon_thresh_bytes, int, 0644);
  91 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
  92
  93 /* TX descriptor ring size - min 512 max 4k */
  94 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
  95 #define FALCON_TXD_RING_SIZE 1024
  96 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
  97
  98 /* RX descriptor ring size - min 512 max 4k */
  99 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
 100 #define FALCON_RXD_RING_SIZE 1024
 101 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
 102
 103 /* Event queue size - max 32k */
 104 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
 105 #define FALCON_EVQ_SIZE 4096
 106 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
 107
 108 /* Max number of internal errors. After this resets will not be performed */
 109 #define FALCON_MAX_INT_ERRORS 4
 110
 111 /* Maximum period that we wait for flush events. If the flush event
 112  * doesn't arrive in this period of time then we check if the queue
 113  * was disabled anyway. */
 114 #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
 115
 116 /**************************************************************************
 117  *
 118  * Falcon constants
 119  *
 120  **************************************************************************
 121  */
 122
 123 /* DMA address mask */
 124 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
 125
 126 /* TX DMA length mask (13-bit) */
 127 #define FALCON_TX_DMA_MASK (4096 - 1)
 128
 129 /* Size and alignment of special buffers (4KB) */
 130 #define FALCON_BUF_SIZE 4096
 131
 132 /* Dummy SRAM size code */
 133 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
 134
 135 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
 136 #define PCI_EXP_DEVCAP_PWR_VAL_LBN      18
 137 #define PCI_EXP_DEVCAP_PWR_SCL_LBN      26
 138 #define PCI_EXP_DEVCTL_PAYLOAD_LBN      5
 139 #define PCI_EXP_LNKSTA_LNK_WID          0x3f0
 140 #define PCI_EXP_LNKSTA_LNK_WID_LBN      4
 141
 142 #define FALCON_IS_DUAL_FUNC(efx)                \
 143         (falcon_rev(efx) < FALCON_REV_B0)
 144
 145 /**************************************************************************
 146  *
 147  * Falcon hardware access
 148  *
 149  **************************************************************************/
 150
 151 /* Read the current event from the event queue */
 152 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
 153                                         unsigned int index)
 154 {
 155         return (((efx_qword_t *) (channel->eventq.addr)) + index);
 156 }
 157
 158 /* See if an event is present
 159  *
 160  * We check both the high and low dword of the event for all ones.  We
 161  * wrote all ones when we cleared the event, and no valid event can
 162  * have all ones in either its high or low dwords.  This approach is
 163  * robust against reordering.
 164  *
 165  * Note that using a single 64-bit comparison is incorrect; even
 166  * though the CPU read will be atomic, the DMA write may not be.
 167  */
 168 static inline int falcon_event_present(efx_qword_t *event)
 169 {
 170         return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
 171                   EFX_DWORD_IS_ALL_ONES(event->dword[1])));
 172 }
 173
 174 /**************************************************************************
 175  *
 176  * I2C bus - this is a bit-bashing interface using GPIO pins
 177  * Note that it uses the output enables to tristate the outputs
 178  * SDA is the data pin and SCL is the clock
 179  *
 180  **************************************************************************
 181  */
 182 static void falcon_setsda(void *data, int state)
 183 {
 184         struct efx_nic *efx = (struct efx_nic *)data;
 185         efx_oword_t reg;
 186
 187         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 188         EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
 189         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
 190 }
 191
 192 static void falcon_setscl(void *data, int state)
 193 {
 194         struct efx_nic *efx = (struct efx_nic *)data;
 195         efx_oword_t reg;
 196
 197         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 198         EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
 199         falcon_write(efx, &reg, GPIO_CTL_REG_KER);
 200 }
 201
 202 static int falcon_getsda(void *data)
 203 {
 204         struct efx_nic *efx = (struct efx_nic *)data;
 205         efx_oword_t reg;
 206
 207         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 208         return EFX_OWORD_FIELD(reg, GPIO3_IN);
 209 }
 210
 211 static int falcon_getscl(void *data)
 212 {
 213         struct efx_nic *efx = (struct efx_nic *)data;
 214         efx_oword_t reg;
 215
 216         falcon_read(efx, &reg, GPIO_CTL_REG_KER);
 217         return EFX_OWORD_FIELD(reg, GPIO0_IN);
 218 }
 219
 220 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
 221         .setsda         = falcon_setsda,
 222         .setscl         = falcon_setscl,
 223         .getsda         = falcon_getsda,
 224         .getscl         = falcon_getscl,
 225         .udelay         = 5,
 226         /*
 227          * This is the number of system clock ticks after which
 228          * i2c-algo-bit gives up waiting for SCL to become high.
 229          * It must be at least 2 since the first tick can happen
 230          * immediately after it starts waiting.
 231          */
 232         .timeout        = 2,
 233 };
 234
 235 /**************************************************************************
 236  *
 237  * Falcon special buffer handling
 238  * Special buffers are used for event queues and the TX and RX
 239  * descriptor rings.
 240  *
 241  *************************************************************************/
 242
 243 /*
 244  * Initialise a Falcon special buffer
 245  *
 246  * This will define a buffer (previously allocated via
 247  * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
 248  * it to be used for event queues, descriptor rings etc.
 249  */
 250 static int
 251 falcon_init_special_buffer(struct efx_nic *efx,
 252                            struct efx_special_buffer *buffer)
 253 {
 254         efx_qword_t buf_desc;
 255         int index;
 256         dma_addr_t dma_addr;
 257         int i;
 258
 259         EFX_BUG_ON_PARANOID(!buffer->addr);
 260
 261         /* Write buffer descriptors to NIC */
 262         for (i = 0; i < buffer->entries; i++) {
 263                 index = buffer->index + i;
 264                 dma_addr = buffer->dma_addr + (i * 4096);
 265                 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
 266                         index, (unsigned long long)dma_addr);
 267                 EFX_POPULATE_QWORD_4(buf_desc,
 268                                      IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
 269                                      BUF_ADR_REGION, 0,
 270                                      BUF_ADR_FBUF, (dma_addr >> 12),
 271                                      BUF_OWNER_ID_FBUF, 0);
 272                 falcon_write_sram(efx, &buf_desc, index);
 273         }
 274
 275         return 0;
 276 }
 277
 278 /* Unmaps a buffer from Falcon and clears the buffer table entries */
 279 static void
 280 falcon_fini_special_buffer(struct efx_nic *efx,
 281                            struct efx_special_buffer *buffer)
 282 {
 283         efx_oword_t buf_tbl_upd;
 284         unsigned int start = buffer->index;
 285         unsigned int end = (buffer->index + buffer->entries - 1);
 286
 287         if (!buffer->entries)
 288                 return;
 289
 290         EFX_LOG(efx, "unmapping special buffers %d-%d\n",
 291                 buffer->index, buffer->index + buffer->entries - 1);
 292
 293         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 294                              BUF_UPD_CMD, 0,
 295                              BUF_CLR_CMD, 1,
 296                              BUF_CLR_END_ID, end,
 297                              BUF_CLR_START_ID, start);
 298         falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
 299 }
 300
 301 /*
 302  * Allocate a new Falcon special buffer
 303  *
 304  * This allocates memory for a new buffer, clears it and allocates a
 305  * new buffer ID range.  It does not write into Falcon's buffer table.
 306  *
 307  * This call will allocate 4KB buffers, since Falcon can't use 8KB
 308  * buffers for event queues and descriptor rings.
 309  */
 310 static int falcon_alloc_special_buffer(struct efx_nic *efx,
 311                                        struct efx_special_buffer *buffer,
 312                                        unsigned int len)
 313 {
 314         struct falcon_nic_data *nic_data = efx->nic_data;
 315
 316         len = ALIGN(len, FALCON_BUF_SIZE);
 317
 318         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 319                                             &buffer->dma_addr);
 320         if (!buffer->addr)
 321                 return -ENOMEM;
 322         buffer->len = len;
 323         buffer->entries = len / FALCON_BUF_SIZE;
 324         BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
 325
 326         /* All zeros is a potentially valid event so memset to 0xff */
 327         memset(buffer->addr, 0xff, len);
 328
 329         /* Select new buffer ID */
 330         buffer->index = nic_data->next_buffer_table;
 331         nic_data->next_buffer_table += buffer->entries;
 332
 333         EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
 334                 "(virt %p phys %lx)\n", buffer->index,
 335                 buffer->index + buffer->entries - 1,
 336                 (unsigned long long)buffer->dma_addr, len,
 337                 buffer->addr, virt_to_phys(buffer->addr));
 338
 339         return 0;
 340 }
 341
 342 static void falcon_free_special_buffer(struct efx_nic *efx,
 343                                        struct efx_special_buffer *buffer)
 344 {
 345         if (!buffer->addr)
 346                 return;
 347
 348         EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
 349                 "(virt %p phys %lx)\n", buffer->index,
 350                 buffer->index + buffer->entries - 1,
 351                 (unsigned long long)buffer->dma_addr, buffer->len,
 352                 buffer->addr, virt_to_phys(buffer->addr));
 353
 354         pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
 355                             buffer->dma_addr);
 356         buffer->addr = NULL;
 357         buffer->entries = 0;
 358 }
 359
 360 /**************************************************************************
 361  *
 362  * Falcon generic buffer handling
 363  * These buffers are used for interrupt status and MAC stats
 364  *
 365  **************************************************************************/
 366
 367 static int falcon_alloc_buffer(struct efx_nic *efx,
 368                                struct efx_buffer *buffer, unsigned int len)
 369 {
 370         buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
 371                                             &buffer->dma_addr);
 372         if (!buffer->addr)
 373                 return -ENOMEM;
 374         buffer->len = len;
 375         memset(buffer->addr, 0, len);
 376         return 0;
 377 }
 378
 379 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
 380 {
 381         if (buffer->addr) {
 382                 pci_free_consistent(efx->pci_dev, buffer->len,
 383                                     buffer->addr, buffer->dma_addr);
 384                 buffer->addr = NULL;
 385         }
 386 }
 387
 388 /**************************************************************************
 389  *
 390  * Falcon TX path
 391  *
 392  **************************************************************************/
 393
 394 /* Returns a pointer to the specified transmit descriptor in the TX
 395  * descriptor queue belonging to the specified channel.
 396  */
 397 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
 398                                                unsigned int index)
 399 {
 400         return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
 401 }
 402
 403 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 404 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
 405 {
 406         unsigned write_ptr;
 407         efx_dword_t reg;
 408
 409         write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
 410         EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
 411         falcon_writel_page(tx_queue->efx, &reg,
 412                            TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
 413 }
 414
 415
 416 /* For each entry inserted into the software descriptor ring, create a
 417  * descriptor in the hardware TX descriptor ring (in host memory), and
 418  * write a doorbell.
 419  */
 420 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
 421 {
 422
 423         struct efx_tx_buffer *buffer;
 424         efx_qword_t *txd;
 425         unsigned write_ptr;
 426
 427         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 428
 429         do {
 430                 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
 431                 buffer = &tx_queue->buffer[write_ptr];
 432                 txd = falcon_tx_desc(tx_queue, write_ptr);
 433                 ++tx_queue->write_count;
 434
 435                 /* Create TX descriptor ring entry */
 436                 EFX_POPULATE_QWORD_5(*txd,
 437                                      TX_KER_PORT, 0,
 438                                      TX_KER_CONT, buffer->continuation,
 439                                      TX_KER_BYTE_CNT, buffer->len,
 440                                      TX_KER_BUF_REGION, 0,
 441                                      TX_KER_BUF_ADR, buffer->dma_addr);
 442         } while (tx_queue->write_count != tx_queue->insert_count);
 443
 444         wmb(); /* Ensure descriptors are written before they are fetched */
 445         falcon_notify_tx_desc(tx_queue);
 446 }
 447
 448 /* Allocate hardware resources for a TX queue */
 449 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
 450 {
 451         struct efx_nic *efx = tx_queue->efx;
 452         return falcon_alloc_special_buffer(efx, &tx_queue->txd,
 453                                            FALCON_TXD_RING_SIZE *
 454                                            sizeof(efx_qword_t));
 455 }
 456
 457 int falcon_init_tx(struct efx_tx_queue *tx_queue)
 458 {
 459         efx_oword_t tx_desc_ptr;
 460         struct efx_nic *efx = tx_queue->efx;
 461         int rc;
 462
 463         /* Pin TX descriptor ring */
 464         rc = falcon_init_special_buffer(efx, &tx_queue->txd);
 465         if (rc)
 466                 return rc;
 467
 468         /* Push TX descriptor ring to card */
 469         EFX_POPULATE_OWORD_10(tx_desc_ptr,
 470                               TX_DESCQ_EN, 1,
 471                               TX_ISCSI_DDIG_EN, 0,
 472                               TX_ISCSI_HDIG_EN, 0,
 473                               TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 474                               TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum,
 475                               TX_DESCQ_OWNER_ID, 0,
 476                               TX_DESCQ_LABEL, tx_queue->queue,
 477                               TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
 478                               TX_DESCQ_TYPE, 0,
 479                               TX_NON_IP_DROP_DIS_B0, 1);
 480
 481         if (falcon_rev(efx) >= FALCON_REV_B0) {
 482                 int csum = !(efx->net_dev->features & NETIF_F_IP_CSUM);
 483                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, csum);
 484                 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, csum);
 485         }
 486
 487         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 488                            tx_queue->queue);
 489
 490         if (falcon_rev(efx) < FALCON_REV_B0) {
 491                 efx_oword_t reg;
 492
 493                 BUG_ON(tx_queue->queue >= 128); /* HW limit */
 494
 495                 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
 496                 if (efx->net_dev->features & NETIF_F_IP_CSUM)
 497                         clear_bit_le(tx_queue->queue, (void *)&reg);
 498                 else
 499                         set_bit_le(tx_queue->queue, (void *)&reg);
 500                 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
 501         }
 502
 503         return 0;
 504 }
 505
 506 static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
 507 {
 508         struct efx_nic *efx = tx_queue->efx;
 509         struct efx_channel *channel = &efx->channel[0];
 510         efx_oword_t tx_flush_descq;
 511         unsigned int read_ptr, i;
 512
 513         /* Post a flush command */
 514         EFX_POPULATE_OWORD_2(tx_flush_descq,
 515                              TX_FLUSH_DESCQ_CMD, 1,
 516                              TX_FLUSH_DESCQ, tx_queue->queue);
 517         falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
 518         msleep(FALCON_FLUSH_TIMEOUT);
 519
 520         if (EFX_WORKAROUND_7803(efx))
 521                 return 0;
 522
 523         /* Look for a flush completed event */
 524         read_ptr = channel->eventq_read_ptr;
 525         for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
 526                 efx_qword_t *event = falcon_event(channel, read_ptr);
 527                 int ev_code, ev_sub_code, ev_queue;
 528                 if (!falcon_event_present(event))
 529                         break;
 530
 531                 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
 532                 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
 533                 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
 534                 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
 535                     (ev_queue == tx_queue->queue)) {
 536                         EFX_LOG(efx, "tx queue %d flush command succesful\n",
 537                                 tx_queue->queue);
 538                         return 0;
 539                 }
 540
 541                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
 542         }
 543
 544         if (EFX_WORKAROUND_11557(efx)) {
 545                 efx_oword_t reg;
 546                 int enabled;
 547
 548                 falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
 549                                   tx_queue->queue);
 550                 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
 551                 if (!enabled) {
 552                         EFX_LOG(efx, "tx queue %d disabled without a "
 553                                 "flush event seen\n", tx_queue->queue);
 554                         return 0;
 555                 }
 556         }
 557
 558         EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
 559         return -ETIMEDOUT;
 560 }
 561
 562 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
 563 {
 564         struct efx_nic *efx = tx_queue->efx;
 565         efx_oword_t tx_desc_ptr;
 566
 567         /* Stop the hardware using the queue */
 568         if (falcon_flush_tx_queue(tx_queue))
 569                 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
 570
 571         /* Remove TX descriptor ring from card */
 572         EFX_ZERO_OWORD(tx_desc_ptr);
 573         falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 574                            tx_queue->queue);
 575
 576         /* Unpin TX descriptor ring */
 577         falcon_fini_special_buffer(efx, &tx_queue->txd);
 578 }
 579
 580 /* Free buffers backing TX queue */
 581 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
 582 {
 583         falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 584 }
 585
 586 /**************************************************************************
 587  *
 588  * Falcon RX path
 589  *
 590  **************************************************************************/
 591
 592 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
 593 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
 594                                                unsigned int index)
 595 {
 596         return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
 597 }
 598
 599 /* This creates an entry in the RX descriptor queue */
 600 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
 601                                         unsigned index)
 602 {
 603         struct efx_rx_buffer *rx_buf;
 604         efx_qword_t *rxd;
 605
 606         rxd = falcon_rx_desc(rx_queue, index);
 607         rx_buf = efx_rx_buffer(rx_queue, index);
 608         EFX_POPULATE_QWORD_3(*rxd,
 609                              RX_KER_BUF_SIZE,
 610                              rx_buf->len -
 611                              rx_queue->efx->type->rx_buffer_padding,
 612                              RX_KER_BUF_REGION, 0,
 613                              RX_KER_BUF_ADR, rx_buf->dma_addr);
 614 }
 615
 616 /* This writes to the RX_DESC_WPTR register for the specified receive
 617  * descriptor ring.
 618  */
 619 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
 620 {
 621         efx_dword_t reg;
 622         unsigned write_ptr;
 623
 624         while (rx_queue->notified_count != rx_queue->added_count) {
 625                 falcon_build_rx_desc(rx_queue,
 626                                      rx_queue->notified_count &
 627                                      FALCON_RXD_RING_MASK);
 628                 ++rx_queue->notified_count;
 629         }
 630
 631         wmb();
 632         write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
 633         EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
 634         falcon_writel_page(rx_queue->efx, &reg,
 635                            RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
 636 }
 637
 638 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
 639 {
 640         struct efx_nic *efx = rx_queue->efx;
 641         return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
 642                                            FALCON_RXD_RING_SIZE *
 643                                            sizeof(efx_qword_t));
 644 }
 645
 646 int falcon_init_rx(struct efx_rx_queue *rx_queue)
 647 {
 648         efx_oword_t rx_desc_ptr;
 649         struct efx_nic *efx = rx_queue->efx;
 650         int rc;
 651         int is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
 652         int iscsi_digest_en = is_b0;
 653
 654         EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
 655                 rx_queue->queue, rx_queue->rxd.index,
 656                 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 657
 658         /* Pin RX descriptor ring */
 659         rc = falcon_init_special_buffer(efx, &rx_queue->rxd);
 660         if (rc)
 661                 return rc;
 662
 663         /* Push RX descriptor ring to card */
 664         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 665                               RX_ISCSI_DDIG_EN, iscsi_digest_en,
 666                               RX_ISCSI_HDIG_EN, iscsi_digest_en,
 667                               RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 668                               RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum,
 669                               RX_DESCQ_OWNER_ID, 0,
 670                               RX_DESCQ_LABEL, rx_queue->queue,
 671                               RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
 672                               RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 673                               /* For >=B0 this is scatter so disable */
 674                               RX_DESCQ_JUMBO, !is_b0,
 675                               RX_DESCQ_EN, 1);
 676         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 677                            rx_queue->queue);
 678         return 0;
 679 }
 680
 681 static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
 682 {
 683         struct efx_nic *efx = rx_queue->efx;
 684         struct efx_channel *channel = &efx->channel[0];
 685         unsigned int read_ptr, i;
 686         efx_oword_t rx_flush_descq;
 687
 688         /* Post a flush command */
 689         EFX_POPULATE_OWORD_2(rx_flush_descq,
 690                              RX_FLUSH_DESCQ_CMD, 1,
 691                              RX_FLUSH_DESCQ, rx_queue->queue);
 692         falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
 693         msleep(FALCON_FLUSH_TIMEOUT);
 694
 695         if (EFX_WORKAROUND_7803(efx))
 696                 return 0;
 697
 698         /* Look for a flush completed event */
 699         read_ptr = channel->eventq_read_ptr;
 700         for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
 701                 efx_qword_t *event = falcon_event(channel, read_ptr);
 702                 int ev_code, ev_sub_code, ev_queue, ev_failed;
 703                 if (!falcon_event_present(event))
 704                         break;
 705
 706                 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
 707                 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
 708                 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
 709                 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
 710
 711                 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
 712                     (ev_queue == rx_queue->queue)) {
 713                         if (ev_failed) {
 714                                 EFX_INFO(efx, "rx queue %d flush command "
 715                                          "failed\n", rx_queue->queue);
 716                                 return -EAGAIN;
 717                         } else {
 718                                 EFX_LOG(efx, "rx queue %d flush command "
 719                                         "succesful\n", rx_queue->queue);
 720                                 return 0;
 721                         }
 722                 }
 723
 724                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
 725         }
 726
 727         if (EFX_WORKAROUND_11557(efx)) {
 728                 efx_oword_t reg;
 729                 int enabled;
 730
 731                 falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
 732                                   rx_queue->queue);
 733                 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
 734                 if (!enabled) {
 735                         EFX_LOG(efx, "rx queue %d disabled without a "
 736                                 "flush event seen\n", rx_queue->queue);
 737                         return 0;
 738                 }
 739         }
 740
 741         EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
 742         return -ETIMEDOUT;
 743 }
 744
 745 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
 746 {
 747         efx_oword_t rx_desc_ptr;
 748         struct efx_nic *efx = rx_queue->efx;
 749         int i, rc;
 750
 751         /* Try and flush the rx queue. This may need to be repeated */
 752         for (i = 0; i < 5; i++) {
 753                 rc = falcon_flush_rx_queue(rx_queue);
 754                 if (rc == -EAGAIN)
 755                         continue;
 756                 break;
 757         }
 758         if (rc) {
 759                 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
 760                 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
 761         }
 762
 763         /* Remove RX descriptor ring from card */
 764         EFX_ZERO_OWORD(rx_desc_ptr);
 765         falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 766                            rx_queue->queue);
 767
 768         /* Unpin RX descriptor ring */
 769         falcon_fini_special_buffer(efx, &rx_queue->rxd);
 770 }
 771
 772 /* Free buffers backing RX queue */
 773 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
 774 {
 775         falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 776 }
 777
 778 /**************************************************************************
 779  *
 780  * Falcon event queue processing
 781  * Event queues are processed by per-channel tasklets.
 782  *
 783  **************************************************************************/
 784
 785 /* Update a channel's event queue's read pointer (RPTR) register
 786  *
 787  * This writes the EVQ_RPTR_REG register for the specified channel's
 788  * event queue.
 789  *
 790  * Note that EVQ_RPTR_REG contains the index of the "last read" event,
 791  * whereas channel->eventq_read_ptr contains the index of the "next to
 792  * read" event.
 793  */
 794 void falcon_eventq_read_ack(struct efx_channel *channel)
 795 {
 796         efx_dword_t reg;
 797         struct efx_nic *efx = channel->efx;
 798
 799         EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
 800         falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
 801                             channel->evqnum);
 802 }
 803
 804 /* Use HW to insert a SW defined event */
 805 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
 806 {
 807         efx_oword_t drv_ev_reg;
 808
 809         EFX_POPULATE_OWORD_2(drv_ev_reg,
 810                              DRV_EV_QID, channel->evqnum,
 811                              DRV_EV_DATA,
 812                              EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
 813         falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
 814 }
 815
 816 /* Handle a transmit completion event
 817  *
 818  * Falcon batches TX completion events; the message we receive is of
 819  * the form "complete all TX events up to this index".
 820  */
 821 static inline void falcon_handle_tx_event(struct efx_channel *channel,
 822                                           efx_qword_t *event)
 823 {
 824         unsigned int tx_ev_desc_ptr;
 825         unsigned int tx_ev_q_label;
 826         struct efx_tx_queue *tx_queue;
 827         struct efx_nic *efx = channel->efx;
 828
 829         if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
 830                 /* Transmit completion */
 831                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
 832                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
 833                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 834                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 835         } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
 836                 /* Rewrite the FIFO write pointer */
 837                 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
 838                 tx_queue = &efx->tx_queue[tx_ev_q_label];
 839
 840                 if (efx_dev_registered(efx))
 841                         netif_tx_lock(efx->net_dev);
 842                 falcon_notify_tx_desc(tx_queue);
 843                 if (efx_dev_registered(efx))
 844                         netif_tx_unlock(efx->net_dev);
 845         } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
 846                    EFX_WORKAROUND_10727(efx)) {
 847                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
 848         } else {
 849                 EFX_ERR(efx, "channel %d unexpected TX event "
 850                         EFX_QWORD_FMT"\n", channel->channel,
 851                         EFX_QWORD_VAL(*event));
 852         }
 853 }
 854
 855 /* Check received packet's destination MAC address. */
 856 static int check_dest_mac(struct efx_rx_queue *rx_queue,
 857                           const efx_qword_t *event)
 858 {
 859         struct efx_rx_buffer *rx_buf;
 860         struct efx_nic *efx = rx_queue->efx;
 861         int rx_ev_desc_ptr;
 862         struct ethhdr *eh;
 863
 864         if (efx->promiscuous)
 865                 return 1;
 866
 867         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
 868         rx_buf = efx_rx_buffer(rx_queue, rx_ev_desc_ptr);
 869         eh = (struct ethhdr *)rx_buf->data;
 870         if (memcmp(eh->h_dest, efx->net_dev->dev_addr, ETH_ALEN))
 871                 return 0;
 872         return 1;
 873 }
 874
 875 /* Detect errors included in the rx_evt_pkt_ok bit. */
 876 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 877                                     const efx_qword_t *event,
 878                                     unsigned *rx_ev_pkt_ok,
 879                                     int *discard, int byte_count)
 880 {
 881         struct efx_nic *efx = rx_queue->efx;
 882         unsigned rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 883         unsigned rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 884         unsigned rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
 885         unsigned rx_ev_pkt_type, rx_ev_other_err, rx_ev_pause_frm;
 886         unsigned rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
 887         int snap, non_ip;
 888
 889         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
 890         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
 891         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
 892         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
 893         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 894                                                  RX_EV_BUF_OWNER_ID_ERR);
 895         rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
 896         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 897                                                   RX_EV_IP_HDR_CHKSUM_ERR);
 898         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 899                                                    RX_EV_TCP_UDP_CHKSUM_ERR);
 900         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
 901         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
 902         rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
 903                           0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
 904         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
 905
 906         /* Every error apart from tobe_disc and pause_frm */
 907         rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
 908                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 909                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 910
 911         snap = (rx_ev_pkt_type == RX_EV_PKT_TYPE_LLC_DECODE) ||
 912                 (rx_ev_pkt_type == RX_EV_PKT_TYPE_VLAN_LLC_DECODE);
 913         non_ip = (rx_ev_hdr_type == RX_EV_HDR_TYPE_NON_IP_DECODE);
 914
 915         /* SFC bug 5475/8970: The Falcon XMAC incorrectly calculates the
 916          * length field of an LLC frame, which sets TOBE_DISC. We could set
 917          * PASS_LEN_ERR, but we want the MAC to filter out short frames (to
 918          * protect the RX block).
 919          *
 920          * bug5475 - LLC/SNAP: Falcon identifies SNAP packets.
 921          * bug8970 - LLC/noSNAP: Falcon does not provide an LLC flag.
 922          *                       LLC can't encapsulate IP, so by definition
 923          *                       these packets are NON_IP.
 924          *
 925          * Unicast mismatch will also cause TOBE_DISC, so the driver needs
 926          * to check this.
 927          */
 928         if (EFX_WORKAROUND_5475(efx) && rx_ev_tobe_disc && (snap || non_ip)) {
 929                 /* If all the other flags are zero then we can state the
 930                  * entire packet is ok, which will flag to the kernel not
 931                  * to recalculate checksums.
 932                  */
 933                 if (!(non_ip | rx_ev_other_err | rx_ev_pause_frm))
 934                         *rx_ev_pkt_ok = 1;
 935
 936                 rx_ev_tobe_disc = 0;
 937
 938                 /* TOBE_DISC is set for unicast mismatch.  But given that
 939                  * we can't trust TOBE_DISC here, we must validate the dest
 940                  * MAC address ourselves.
 941                  */
 942                 if (!rx_ev_mcast_pkt && !check_dest_mac(rx_queue, event))
 943                         rx_ev_tobe_disc = 1;
 944         }
 945
 946         /* Count errors that are not in MAC stats. */
 947         if (rx_ev_frm_trunc)
 948                 ++rx_queue->channel->n_rx_frm_trunc;
 949         else if (rx_ev_tobe_disc)
 950                 ++rx_queue->channel->n_rx_tobe_disc;
 951         else if (rx_ev_ip_hdr_chksum_err)
 952                 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
 953         else if (rx_ev_tcp_udp_chksum_err)
 954                 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
 955         if (rx_ev_ip_frag_err)
 956                 ++rx_queue->channel->n_rx_ip_frag_err;
 957
 958         /* The frame must be discarded if any of these are true. */
 959         *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
 960                     rx_ev_tobe_disc | rx_ev_pause_frm);
 961
 962         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 963          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 964          * to a FIFO overflow.
 965          */
 966 #ifdef EFX_ENABLE_DEBUG
 967         if (rx_ev_other_err) {
 968                 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
 969                             EFX_QWORD_FMT "%s%s%s%s%s%s%s%s%s\n",
 970                             rx_queue->queue, EFX_QWORD_VAL(*event),
 971                             rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 972                             rx_ev_ip_hdr_chksum_err ?
 973                             " [IP_HDR_CHKSUM_ERR]" : "",
 974                             rx_ev_tcp_udp_chksum_err ?
 975                             " [TCP_UDP_CHKSUM_ERR]" : "",
 976                             rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 977                             rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 978                             rx_ev_drib_nib ? " [DRIB_NIB]" : "",
 979                             rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 980                             rx_ev_pause_frm ? " [PAUSE]" : "",
 981                             snap ? " [SNAP/LLC]" : "");
 982         }
 983 #endif
 984
 985         if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
 986                      efx->phy_type == PHY_TYPE_10XPRESS))
 987                 tenxpress_crc_err(efx);
 988 }
 989
 990 /* Handle receive events that are not in-order. */
 991 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
 992                                        unsigned index)
 993 {
 994         struct efx_nic *efx = rx_queue->efx;
 995         unsigned expected, dropped;
 996
 997         expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
 998         dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
 999                    FALCON_RXD_RING_MASK);
1000         EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
1001                 dropped, index, expected);
1002
1003         efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
1004                            RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1005 }
1006
1007 /* Handle a packet received event
1008  *
1009  * Falcon silicon gives a "discard" flag if it's a unicast packet with the
1010  * wrong destination address
1011  * Also "is multicast" and "matches multicast filter" flags can be used to
1012  * discard non-matching multicast packets.
1013  */
1014 static inline int falcon_handle_rx_event(struct efx_channel *channel,
1015                                          const efx_qword_t *event)
1016 {
1017         unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt;
1018         unsigned int rx_ev_pkt_ok, rx_ev_hdr_type, rx_ev_mcast_pkt;
1019         unsigned expected_ptr;
1020         int discard = 0, checksummed;
1021         struct efx_rx_queue *rx_queue;
1022         struct efx_nic *efx = channel->efx;
1023
1024         /* Basic packet information */
1025         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
1026         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
1027         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
1028         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
1029         WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
1030
1031         rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL);
1032         rx_queue = &efx->rx_queue[rx_ev_q_label];
1033
1034         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
1035         expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
1036         if (unlikely(rx_ev_desc_ptr != expected_ptr)) {
1037                 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
1038                 return rx_ev_q_label;
1039         }
1040
1041         if (likely(rx_ev_pkt_ok)) {
1042                 /* If packet is marked as OK and packet type is TCP/IPv4 or
1043                  * UDP/IPv4, then we can rely on the hardware checksum.
1044                  */
1045                 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
1046         } else {
1047                 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
1048                                         &discard, rx_ev_byte_cnt);
1049                 checksummed = 0;
1050         }
1051
1052         /* Detect multicast packets that didn't match the filter */
1053         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
1054         if (rx_ev_mcast_pkt) {
1055                 unsigned int rx_ev_mcast_hash_match =
1056                         EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
1057
1058                 if (unlikely(!rx_ev_mcast_hash_match))
1059                         discard = 1;
1060         }
1061
1062         /* Handle received packet */
1063         efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
1064                       checksummed, discard);
1065
1066         return rx_ev_q_label;
1067 }
1068
1069 /* Global events are basically PHY events */
1070 static void falcon_handle_global_event(struct efx_channel *channel,
1071                                        efx_qword_t *event)
1072 {
1073         struct efx_nic *efx = channel->efx;
1074         int is_phy_event = 0, handled = 0;
1075
1076         /* Check for interrupt on either port.  Some boards have a
1077          * single PHY wired to the interrupt line for port 1. */
1078         if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1079             EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1080             EFX_QWORD_FIELD(*event, XG_PHY_INTR))
1081                 is_phy_event = 1;
1082
1083         if ((falcon_rev(efx) >= FALCON_REV_B0) &&
1084             EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
1085                 is_phy_event = 1;
1086
1087         if (is_phy_event) {
1088                 efx->phy_op->clear_interrupt(efx);
1089                 queue_work(efx->workqueue, &efx->reconfigure_work);
1090                 handled = 1;
1091         }
1092
1093         if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1094                 EFX_ERR(efx, "channel %d seen global RX_RESET "
1095                         "event. Resetting.\n", channel->channel);
1096
1097                 atomic_inc(&efx->rx_reset);
1098                 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1099                                    RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1100                 handled = 1;
1101         }
1102
1103         if (!handled)
1104                 EFX_ERR(efx, "channel %d unknown global event "
1105                         EFX_QWORD_FMT "\n", channel->channel,
1106                         EFX_QWORD_VAL(*event));
1107 }
1108
1109 static void falcon_handle_driver_event(struct efx_channel *channel,
1110                                        efx_qword_t *event)
1111 {
1112         struct efx_nic *efx = channel->efx;
1113         unsigned int ev_sub_code;
1114         unsigned int ev_sub_data;
1115
1116         ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1117         ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1118
1119         switch (ev_sub_code) {
1120         case TX_DESCQ_FLS_DONE_EV_DECODE:
1121                 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1122                           channel->channel, ev_sub_data);
1123                 break;
1124         case RX_DESCQ_FLS_DONE_EV_DECODE:
1125                 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1126                           channel->channel, ev_sub_data);
1127                 break;
1128         case EVQ_INIT_DONE_EV_DECODE:
1129                 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1130                         channel->channel, ev_sub_data);
1131                 break;
1132         case SRM_UPD_DONE_EV_DECODE:
1133                 EFX_TRACE(efx, "channel %d SRAM update done\n",
1134                           channel->channel);
1135                 break;
1136         case WAKE_UP_EV_DECODE:
1137                 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1138                           channel->channel, ev_sub_data);
1139                 break;
1140         case TIMER_EV_DECODE:
1141                 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1142                           channel->channel, ev_sub_data);
1143                 break;
1144         case RX_RECOVERY_EV_DECODE:
1145                 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1146                         "Resetting.\n", channel->channel);
1147                 atomic_inc(&efx->rx_reset);
1148                 efx_schedule_reset(efx,
1149                                    EFX_WORKAROUND_6555(efx) ?
1150                                    RESET_TYPE_RX_RECOVERY :
1151                                    RESET_TYPE_DISABLE);
1152                 break;
1153         case RX_DSC_ERROR_EV_DECODE:
1154                 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1155                         " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1156                 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1157                 break;
1158         case TX_DSC_ERROR_EV_DECODE:
1159                 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1160                         " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1161                 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1162                 break;
1163         default:
1164                 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1165                           "data %04x\n", channel->channel, ev_sub_code,
1166                           ev_sub_data);
1167                 break;
1168         }
1169 }
1170
1171 int falcon_process_eventq(struct efx_channel *channel, int *rx_quota)
1172 {
1173         unsigned int read_ptr;
1174         efx_qword_t event, *p_event;
1175         int ev_code;
1176         int rxq;
1177         int rxdmaqs = 0;
1178
1179         read_ptr = channel->eventq_read_ptr;
1180
1181         do {
1182                 p_event = falcon_event(channel, read_ptr);
1183                 event = *p_event;
1184
1185                 if (!falcon_event_present(&event))
1186                         /* End of events */
1187                         break;
1188
1189                 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1190                           channel->channel, EFX_QWORD_VAL(event));
1191
1192                 /* Clear this event by marking it all ones */
1193                 EFX_SET_QWORD(*p_event);
1194
1195                 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1196
1197                 switch (ev_code) {
1198                 case RX_IP_EV_DECODE:
1199                         rxq = falcon_handle_rx_event(channel, &event);
1200                         rxdmaqs |= (1 << rxq);
1201                         (*rx_quota)--;
1202                         break;
1203                 case TX_IP_EV_DECODE:
1204                         falcon_handle_tx_event(channel, &event);
1205                         break;
1206                 case DRV_GEN_EV_DECODE:
1207                         channel->eventq_magic
1208                                 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1209                         EFX_LOG(channel->efx, "channel %d received generated "
1210                                 "event "EFX_QWORD_FMT"\n", channel->channel,
1211                                 EFX_QWORD_VAL(event));
1212                         break;
1213                 case GLOBAL_EV_DECODE:
1214                         falcon_handle_global_event(channel, &event);
1215                         break;
1216                 case DRIVER_EV_DECODE:
1217                         falcon_handle_driver_event(channel, &event);
1218                         break;
1219                 default:
1220                         EFX_ERR(channel->efx, "channel %d unknown event type %d"
1221                                 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1222                                 ev_code, EFX_QWORD_VAL(event));
1223                 }
1224
1225                 /* Increment read pointer */
1226                 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1227
1228         } while (*rx_quota);
1229
1230         channel->eventq_read_ptr = read_ptr;
1231         return rxdmaqs;
1232 }
1233
1234 void falcon_set_int_moderation(struct efx_channel *channel)
1235 {
1236         efx_dword_t timer_cmd;
1237         struct efx_nic *efx = channel->efx;
1238
1239         /* Set timer register */
1240         if (channel->irq_moderation) {
1241                 /* Round to resolution supported by hardware.  The value we
1242                  * program is based at 0.  So actual interrupt moderation
1243                  * achieved is ((x + 1) * res).
1244                  */
1245                 unsigned int res = 5;
1246                 channel->irq_moderation -= (channel->irq_moderation % res);
1247                 if (channel->irq_moderation < res)
1248                         channel->irq_moderation = res;
1249                 EFX_POPULATE_DWORD_2(timer_cmd,
1250                                      TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1251                                      TIMER_VAL,
1252                                      (channel->irq_moderation / res) - 1);
1253         } else {
1254                 EFX_POPULATE_DWORD_2(timer_cmd,
1255                                      TIMER_MODE, TIMER_MODE_DIS,
1256                                      TIMER_VAL, 0);
1257         }
1258         falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1259                                   channel->evqnum);
1260
1261 }
1262
1263 /* Allocate buffer table entries for event queue */
1264 int falcon_probe_eventq(struct efx_channel *channel)
1265 {
1266         struct efx_nic *efx = channel->efx;
1267         unsigned int evq_size;
1268
1269         evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1270         return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1271 }
1272
1273 int falcon_init_eventq(struct efx_channel *channel)
1274 {
1275         efx_oword_t evq_ptr;
1276         struct efx_nic *efx = channel->efx;
1277         int rc;
1278
1279         EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1280                 channel->channel, channel->eventq.index,
1281                 channel->eventq.index + channel->eventq.entries - 1);
1282
1283         /* Pin event queue buffer */
1284         rc = falcon_init_special_buffer(efx, &channel->eventq);
1285         if (rc)
1286                 return rc;
1287
1288         /* Fill event queue with all ones (i.e. empty events) */
1289         memset(channel->eventq.addr, 0xff, channel->eventq.len);
1290
1291         /* Push event queue to card */
1292         EFX_POPULATE_OWORD_3(evq_ptr,
1293                              EVQ_EN, 1,
1294                              EVQ_SIZE, FALCON_EVQ_ORDER,
1295                              EVQ_BUF_BASE_ID, channel->eventq.index);
1296         falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1297                            channel->evqnum);
1298
1299         falcon_set_int_moderation(channel);
1300
1301         return 0;
1302 }
1303
1304 void falcon_fini_eventq(struct efx_channel *channel)
1305 {
1306         efx_oword_t eventq_ptr;
1307         struct efx_nic *efx = channel->efx;
1308
1309         /* Remove event queue from card */
1310         EFX_ZERO_OWORD(eventq_ptr);
1311         falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1312                            channel->evqnum);
1313
1314         /* Unpin event queue */
1315         falcon_fini_special_buffer(efx, &channel->eventq);
1316 }
1317
1318 /* Free buffers backing event queue */
1319 void falcon_remove_eventq(struct efx_channel *channel)
1320 {
1321         falcon_free_special_buffer(channel->efx, &channel->eventq);
1322 }
1323
1324
1325 /* Generates a test event on the event queue.  A subsequent call to
1326  * process_eventq() should pick up the event and place the value of
1327  * "magic" into channel->eventq_magic;
1328  */
1329 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1330 {
1331         efx_qword_t test_event;
1332
1333         EFX_POPULATE_QWORD_2(test_event,
1334                              EV_CODE, DRV_GEN_EV_DECODE,
1335                              EVQ_MAGIC, magic);
1336         falcon_generate_event(channel, &test_event);
1337 }
1338
1339
1340 /**************************************************************************
1341  *
1342  * Falcon hardware interrupts
1343  * The hardware interrupt handler does very little work; all the event
1344  * queue processing is carried out by per-channel tasklets.
1345  *
1346  **************************************************************************/
1347
1348 /* Enable/disable/generate Falcon interrupts */
1349 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1350                                      int force)
1351 {
1352         efx_oword_t int_en_reg_ker;
1353
1354         EFX_POPULATE_OWORD_2(int_en_reg_ker,
1355                              KER_INT_KER, force,
1356                              DRV_INT_EN_KER, enabled);
1357         falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1358 }
1359
1360 void falcon_enable_interrupts(struct efx_nic *efx)
1361 {
1362         efx_oword_t int_adr_reg_ker;
1363         struct efx_channel *channel;
1364
1365         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1366         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1367
1368         /* Program address */
1369         EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1370                              NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1371                              INT_ADR_KER, efx->irq_status.dma_addr);
1372         falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1373
1374         /* Enable interrupts */
1375         falcon_interrupts(efx, 1, 0);
1376
1377         /* Force processing of all the channels to get the EVQ RPTRs up to
1378            date */
1379         efx_for_each_channel_with_interrupt(channel, efx)
1380                 efx_schedule_channel(channel);
1381 }
1382
1383 void falcon_disable_interrupts(struct efx_nic *efx)
1384 {
1385         /* Disable interrupts */
1386         falcon_interrupts(efx, 0, 0);
1387 }
1388
1389 /* Generate a Falcon test interrupt
1390  * Interrupt must already have been enabled, otherwise nasty things
1391  * may happen.
1392  */
1393 void falcon_generate_interrupt(struct efx_nic *efx)
1394 {
1395         falcon_interrupts(efx, 1, 1);
1396 }
1397
1398 /* Acknowledge a legacy interrupt from Falcon
1399  *
1400  * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1401  *
1402  * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1403  * BIU. Interrupt acknowledge is read sensitive so must write instead
1404  * (then read to ensure the BIU collector is flushed)
1405  *
1406  * NB most hardware supports MSI interrupts
1407  */
1408 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1409 {
1410         efx_dword_t reg;
1411
1412         EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1413         falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1414         falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1415 }
1416
1417 /* Process a fatal interrupt
1418  * Disable bus mastering ASAP and schedule a reset
1419  */
1420 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1421 {
1422         struct falcon_nic_data *nic_data = efx->nic_data;
1423         efx_oword_t *int_ker = efx->irq_status.addr;
1424         efx_oword_t fatal_intr;
1425         int error, mem_perr;
1426         static int n_int_errors;
1427
1428         falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1429         error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1430
1431         EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1432                 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1433                 EFX_OWORD_VAL(fatal_intr),
1434                 error ? "disabling bus mastering" : "no recognised error");
1435         if (error == 0)
1436                 goto out;
1437
1438         /* If this is a memory parity error dump which blocks are offending */
1439         mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1440         if (mem_perr) {
1441                 efx_oword_t reg;
1442                 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1443                 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1444                         EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1445         }
1446
1447         /* Disable DMA bus mastering on both devices */
1448         pci_disable_device(efx->pci_dev);
1449         if (FALCON_IS_DUAL_FUNC(efx))
1450                 pci_disable_device(nic_data->pci_dev2);
1451
1452         if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1453                 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1454                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1455         } else {
1456                 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1457                         "NIC will be disabled\n");
1458                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1459         }
1460 out:
1461         return IRQ_HANDLED;
1462 }
1463
1464 /* Handle a legacy interrupt from Falcon
1465  * Acknowledges the interrupt and schedule event queue processing.
1466  */
1467 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1468 {
1469         struct efx_nic *efx = dev_id;
1470         efx_oword_t *int_ker = efx->irq_status.addr;
1471         struct efx_channel *channel;
1472         efx_dword_t reg;
1473         u32 queues;
1474         int syserr;
1475
1476         /* Read the ISR which also ACKs the interrupts */
1477         falcon_readl(efx, &reg, INT_ISR0_B0);
1478         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1479
1480         /* Check to see if we have a serious error condition */
1481         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1482         if (unlikely(syserr))
1483                 return falcon_fatal_interrupt(efx);
1484
1485         if (queues == 0)
1486                 return IRQ_NONE;
1487
1488         efx->last_irq_cpu = raw_smp_processor_id();
1489         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1490                   irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1491
1492         /* Schedule processing of any interrupting queues */
1493         channel = &efx->channel[0];
1494         while (queues) {
1495                 if (queues & 0x01)
1496                         efx_schedule_channel(channel);
1497                 channel++;
1498                 queues >>= 1;
1499         }
1500
1501         return IRQ_HANDLED;
1502 }
1503
1504
1505 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1506 {
1507         struct efx_nic *efx = dev_id;
1508         efx_oword_t *int_ker = efx->irq_status.addr;
1509         struct efx_channel *channel;
1510         int syserr;
1511         int queues;
1512
1513         /* Check to see if this is our interrupt.  If it isn't, we
1514          * exit without having touched the hardware.
1515          */
1516         if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1517                 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1518                           raw_smp_processor_id());
1519                 return IRQ_NONE;
1520         }
1521         efx->last_irq_cpu = raw_smp_processor_id();
1522         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1523                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1524
1525         /* Check to see if we have a serious error condition */
1526         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1527         if (unlikely(syserr))
1528                 return falcon_fatal_interrupt(efx);
1529
1530         /* Determine interrupting queues, clear interrupt status
1531          * register and acknowledge the device interrupt.
1532          */
1533         BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1534         queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1535         EFX_ZERO_OWORD(*int_ker);
1536         wmb(); /* Ensure the vector is cleared before interrupt ack */
1537         falcon_irq_ack_a1(efx);
1538
1539         /* Schedule processing of any interrupting queues */
1540         channel = &efx->channel[0];
1541         while (queues) {
1542                 if (queues & 0x01)
1543                         efx_schedule_channel(channel);
1544                 channel++;
1545                 queues >>= 1;
1546         }
1547
1548         return IRQ_HANDLED;
1549 }
1550
1551 /* Handle an MSI interrupt from Falcon
1552  *
1553  * Handle an MSI hardware interrupt.  This routine schedules event
1554  * queue processing.  No interrupt acknowledgement cycle is necessary.
1555  * Also, we never need to check that the interrupt is for us, since
1556  * MSI interrupts cannot be shared.
1557  */
1558 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1559 {
1560         struct efx_channel *channel = dev_id;
1561         struct efx_nic *efx = channel->efx;
1562         efx_oword_t *int_ker = efx->irq_status.addr;
1563         int syserr;
1564
1565         efx->last_irq_cpu = raw_smp_processor_id();
1566         EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1567                   irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1568
1569         /* Check to see if we have a serious error condition */
1570         syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1571         if (unlikely(syserr))
1572                 return falcon_fatal_interrupt(efx);
1573
1574         /* Schedule processing of the channel */
1575         efx_schedule_channel(channel);
1576
1577         return IRQ_HANDLED;
1578 }
1579
1580
1581 /* Setup RSS indirection table.
1582  * This maps from the hash value of the packet to RXQ
1583  */
1584 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1585 {
1586         int i = 0;
1587         unsigned long offset;
1588         efx_dword_t dword;
1589
1590         if (falcon_rev(efx) < FALCON_REV_B0)
1591                 return;
1592
1593         for (offset = RX_RSS_INDIR_TBL_B0;
1594              offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1595              offset += 0x10) {
1596                 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1597                                      i % efx->rss_queues);
1598                 falcon_writel(efx, &dword, offset);
1599                 i++;
1600         }
1601 }
1602
1603 /* Hook interrupt handler(s)
1604  * Try MSI and then legacy interrupts.
1605  */
1606 int falcon_init_interrupt(struct efx_nic *efx)
1607 {
1608         struct efx_channel *channel;
1609         int rc;
1610
1611         if (!EFX_INT_MODE_USE_MSI(efx)) {
1612                 irq_handler_t handler;
1613                 if (falcon_rev(efx) >= FALCON_REV_B0)
1614                         handler = falcon_legacy_interrupt_b0;
1615                 else
1616                         handler = falcon_legacy_interrupt_a1;
1617
1618                 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1619                                  efx->name, efx);
1620                 if (rc) {
1621                         EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1622                                 efx->pci_dev->irq);
1623                         goto fail1;
1624                 }
1625                 return 0;
1626         }
1627
1628         /* Hook MSI or MSI-X interrupt */
1629         efx_for_each_channel_with_interrupt(channel, efx) {
1630                 rc = request_irq(channel->irq, falcon_msi_interrupt,
1631                                  IRQF_PROBE_SHARED, /* Not shared */
1632                                  efx->name, channel);
1633                 if (rc) {
1634                         EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1635                         goto fail2;
1636                 }
1637         }
1638
1639         return 0;
1640
1641  fail2:
1642         efx_for_each_channel_with_interrupt(channel, efx)
1643                 free_irq(channel->irq, channel);
1644  fail1:
1645         return rc;
1646 }
1647
1648 void falcon_fini_interrupt(struct efx_nic *efx)
1649 {
1650         struct efx_channel *channel;
1651         efx_oword_t reg;
1652
1653         /* Disable MSI/MSI-X interrupts */
1654         efx_for_each_channel_with_interrupt(channel, efx) {
1655                 if (channel->irq)
1656                         free_irq(channel->irq, channel);
1657         }
1658
1659         /* ACK legacy interrupt */
1660         if (falcon_rev(efx) >= FALCON_REV_B0)
1661                 falcon_read(efx, &reg, INT_ISR0_B0);
1662         else
1663                 falcon_irq_ack_a1(efx);
1664
1665         /* Disable legacy interrupt */
1666         if (efx->legacy_irq)
1667                 free_irq(efx->legacy_irq, efx);
1668 }
1669
1670 /**************************************************************************
1671  *
1672  * EEPROM/flash
1673  *
1674  **************************************************************************
1675  */
1676
1677 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1678
1679 /* Wait for SPI command completion */
1680 static int falcon_spi_wait(struct efx_nic *efx)
1681 {
1682         efx_oword_t reg;
1683         int cmd_en, timer_active;
1684         int count;
1685
1686         count = 0;
1687         do {
1688                 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1689                 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1690                 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1691                 if (!cmd_en && !timer_active)
1692                         return 0;
1693                 udelay(10);
1694         } while (++count < 10000); /* wait upto 100msec */
1695         EFX_ERR(efx, "timed out waiting for SPI\n");
1696         return -ETIMEDOUT;
1697 }
1698
1699 static int
1700 falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command,
1701                 unsigned int address, unsigned int addr_len,
1702                 void *data, unsigned int len)
1703 {
1704         efx_oword_t reg;
1705         int rc;
1706
1707         BUG_ON(len > FALCON_SPI_MAX_LEN);
1708
1709         /* Check SPI not currently being accessed */
1710         rc = falcon_spi_wait(efx);
1711         if (rc)
1712                 return rc;
1713
1714         /* Program address register */
1715         EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1716         falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1717
1718         /* Issue read command */
1719         EFX_POPULATE_OWORD_7(reg,
1720                              EE_SPI_HCMD_CMD_EN, 1,
1721                              EE_SPI_HCMD_SF_SEL, device_id,
1722                              EE_SPI_HCMD_DABCNT, len,
1723                              EE_SPI_HCMD_READ, EE_SPI_READ,
1724                              EE_SPI_HCMD_DUBCNT, 0,
1725                              EE_SPI_HCMD_ADBCNT, addr_len,
1726                              EE_SPI_HCMD_ENC, command);
1727         falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1728
1729         /* Wait for read to complete */
1730         rc = falcon_spi_wait(efx);
1731         if (rc)
1732                 return rc;
1733
1734         /* Read data */
1735         falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1736         memcpy(data, &reg, len);
1737         return 0;
1738 }
1739
1740 /**************************************************************************
1741  *
1742  * MAC wrapper
1743  *
1744  **************************************************************************
1745  */
1746 void falcon_drain_tx_fifo(struct efx_nic *efx)
1747 {
1748         efx_oword_t temp;
1749         int count;
1750
1751         if ((falcon_rev(efx) < FALCON_REV_B0) ||
1752             (efx->loopback_mode != LOOPBACK_NONE))
1753                 return;
1754
1755         falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1756         /* There is no point in draining more than once */
1757         if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1758                 return;
1759
1760         /* MAC stats will fail whilst the TX fifo is draining. Serialise
1761          * the drain sequence with the statistics fetch */
1762         spin_lock(&efx->stats_lock);
1763
1764         EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1765         falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1766
1767         /* Reset the MAC and EM block. */
1768         falcon_read(efx, &temp, GLB_CTL_REG_KER);
1769         EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1770         EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1771         EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1772         falcon_write(efx, &temp, GLB_CTL_REG_KER);
1773
1774         count = 0;
1775         while (1) {
1776                 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1777                 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1778                     !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1779                     !EFX_OWORD_FIELD(temp, RST_EM)) {
1780                         EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1781                                 count);
1782                         break;
1783                 }
1784                 if (count > 20) {
1785                         EFX_ERR(efx, "MAC reset failed\n");
1786                         break;
1787                 }
1788                 count++;
1789                 udelay(10);
1790         }
1791
1792         spin_unlock(&efx->stats_lock);
1793
1794         /* If we've reset the EM block and the link is up, then
1795          * we'll have to kick the XAUI link so the PHY can recover */
1796         if (efx->link_up && EFX_WORKAROUND_5147(efx))
1797                 falcon_reset_xaui(efx);
1798 }
1799
1800 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1801 {
1802         efx_oword_t temp;
1803
1804         if (falcon_rev(efx) < FALCON_REV_B0)
1805                 return;
1806
1807         /* Isolate the MAC -> RX */
1808         falcon_read(efx, &temp, RX_CFG_REG_KER);
1809         EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1810         falcon_write(efx, &temp, RX_CFG_REG_KER);
1811
1812         if (!efx->link_up)
1813                 falcon_drain_tx_fifo(efx);
1814 }
1815
1816 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1817 {
1818         efx_oword_t reg;
1819         int link_speed;
1820         unsigned int tx_fc;
1821
1822         if (efx->link_options & GM_LPA_10000)
1823                 link_speed = 0x3;
1824         else if (efx->link_options & GM_LPA_1000)
1825                 link_speed = 0x2;
1826         else if (efx->link_options & GM_LPA_100)
1827                 link_speed = 0x1;
1828         else
1829                 link_speed = 0x0;
1830         /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1831          * as advertised.  Disable to ensure packets are not
1832          * indefinitely held and TX queue can be flushed at any point
1833          * while the link is down. */
1834         EFX_POPULATE_OWORD_5(reg,
1835                              MAC_XOFF_VAL, 0xffff /* max pause time */,
1836                              MAC_BCAD_ACPT, 1,
1837                              MAC_UC_PROM, efx->promiscuous,
1838                              MAC_LINK_STATUS, 1, /* always set */
1839                              MAC_SPEED, link_speed);
1840         /* On B0, MAC backpressure can be disabled and packets get
1841          * discarded. */
1842         if (falcon_rev(efx) >= FALCON_REV_B0) {
1843                 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1844                                     !efx->link_up);
1845         }
1846
1847         falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1848
1849         /* Restore the multicast hash registers. */
1850         falcon_set_multicast_hash(efx);
1851
1852         /* Transmission of pause frames when RX crosses the threshold is
1853          * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1854          * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1855         tx_fc = (efx->flow_control & EFX_FC_TX) ? 1 : 0;
1856         falcon_read(efx, &reg, RX_CFG_REG_KER);
1857         EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1858
1859         /* Unisolate the MAC -> RX */
1860         if (falcon_rev(efx) >= FALCON_REV_B0)
1861                 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1862         falcon_write(efx, &reg, RX_CFG_REG_KER);
1863 }
1864
1865 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1866 {
1867         efx_oword_t reg;
1868         u32 *dma_done;
1869         int i;
1870
1871         if (disable_dma_stats)
1872                 return 0;
1873
1874         /* Statistics fetch will fail if the MAC is in TX drain */
1875         if (falcon_rev(efx) >= FALCON_REV_B0) {
1876                 efx_oword_t temp;
1877                 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1878                 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1879                         return 0;
1880         }
1881
1882         dma_done = (efx->stats_buffer.addr + done_offset);
1883         *dma_done = FALCON_STATS_NOT_DONE;
1884         wmb(); /* ensure done flag is clear */
1885
1886         /* Initiate DMA transfer of stats */
1887         EFX_POPULATE_OWORD_2(reg,
1888                              MAC_STAT_DMA_CMD, 1,
1889                              MAC_STAT_DMA_ADR,
1890                              efx->stats_buffer.dma_addr);
1891         falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1892
1893         /* Wait for transfer to complete */
1894         for (i = 0; i < 400; i++) {
1895                 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1896                         return 0;
1897                 udelay(10);
1898         }
1899
1900         EFX_ERR(efx, "timed out waiting for statistics\n");
1901         return -ETIMEDOUT;
1902 }
1903
1904 /**************************************************************************
1905  *
1906  * PHY access via GMII
1907  *
1908  **************************************************************************
1909  */
1910
1911 /* Use the top bit of the MII PHY id to indicate the PHY type
1912  * (1G/10G), with the remaining bits as the actual PHY id.
1913  *
1914  * This allows us to avoid leaking information from the mii_if_info
1915  * structure into other data structures.
1916  */
1917 #define FALCON_PHY_ID_ID_WIDTH  EFX_WIDTH(MD_PRT_DEV_ADR)
1918 #define FALCON_PHY_ID_ID_MASK   ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1919 #define FALCON_PHY_ID_WIDTH     (FALCON_PHY_ID_ID_WIDTH + 1)
1920 #define FALCON_PHY_ID_MASK      ((1 << FALCON_PHY_ID_WIDTH) - 1)
1921 #define FALCON_PHY_ID_10G       (1 << (FALCON_PHY_ID_WIDTH - 1))
1922
1923
1924 /* Packing the clause 45 port and device fields into a single value */
1925 #define MD_PRT_ADR_COMP_LBN   (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1926 #define MD_PRT_ADR_COMP_WIDTH  MD_PRT_ADR_WIDTH
1927 #define MD_DEV_ADR_COMP_LBN    0
1928 #define MD_DEV_ADR_COMP_WIDTH  MD_DEV_ADR_WIDTH
1929
1930
1931 /* Wait for GMII access to complete */
1932 static int falcon_gmii_wait(struct efx_nic *efx)
1933 {
1934         efx_dword_t md_stat;
1935         int count;
1936
1937         for (count = 0; count < 1000; count++) {        /* wait upto 10ms */
1938                 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
1939                 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
1940                         if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
1941                             EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
1942                                 EFX_ERR(efx, "error from GMII access "
1943                                         EFX_DWORD_FMT"\n",
1944                                         EFX_DWORD_VAL(md_stat));
1945                                 return -EIO;
1946                         }
1947                         return 0;
1948                 }
1949                 udelay(10);
1950         }
1951         EFX_ERR(efx, "timed out waiting for GMII\n");
1952         return -ETIMEDOUT;
1953 }
1954
1955 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1956 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
1957                               int addr, int value)
1958 {
1959         struct efx_nic *efx = net_dev->priv;
1960         unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
1961         efx_oword_t reg;
1962
1963         /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1964          * chosen so that the only current user, Falcon, can take the
1965          * packed value and use them directly.
1966          * Fail to build if this assumption is broken.
1967          */
1968         BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
1969         BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
1970         BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
1971         BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
1972
1973         if (phy_id2 == PHY_ADDR_INVALID)
1974                 return;
1975
1976         /* See falcon_mdio_read for an explanation. */
1977         if (!(phy_id & FALCON_PHY_ID_10G)) {
1978                 int mmd = ffs(efx->phy_op->mmds) - 1;
1979                 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
1980                 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
1981                         & FALCON_PHY_ID_ID_MASK;
1982         }
1983
1984         EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
1985                     addr, value);
1986
1987         spin_lock_bh(&efx->phy_lock);
1988
1989         /* Check MII not currently being accessed */
1990         if (falcon_gmii_wait(efx) != 0)
1991                 goto out;
1992
1993         /* Write the address/ID register */
1994         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
1995         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
1996
1997         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
1998         falcon_write(efx, &reg, MD_ID_REG_KER);
1999
2000         /* Write data */
2001         EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2002         falcon_write(efx, &reg, MD_TXD_REG_KER);
2003
2004         EFX_POPULATE_OWORD_2(reg,
2005                              MD_WRC, 1,
2006                              MD_GC, 0);
2007         falcon_write(efx, &reg, MD_CS_REG_KER);
2008
2009         /* Wait for data to be written */
2010         if (falcon_gmii_wait(efx) != 0) {
2011                 /* Abort the write operation */
2012                 EFX_POPULATE_OWORD_2(reg,
2013                                      MD_WRC, 0,
2014                                      MD_GC, 1);
2015                 falcon_write(efx, &reg, MD_CS_REG_KER);
2016                 udelay(10);
2017         }
2018
2019  out:
2020         spin_unlock_bh(&efx->phy_lock);
2021 }
2022
2023 /* Reads a GMII register from a PHY connected to Falcon.  If no value
2024  * could be read, -1 will be returned. */
2025 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2026 {
2027         struct efx_nic *efx = net_dev->priv;
2028         unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2029         efx_oword_t reg;
2030         int value = -1;
2031
2032         if (phy_addr == PHY_ADDR_INVALID)
2033                 return -1;
2034
2035         /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2036          * but the generic Linux code does not make any distinction or have
2037          * any state for this.
2038          * We spot the case where someone tried to talk 22 to a 45 PHY and
2039          * redirect the request to the lowest numbered MMD as a clause45
2040          * request. This is enough to allow simple queries like id and link
2041          * state to succeed. TODO: We may need to do more in future.
2042          */
2043         if (!(phy_id & FALCON_PHY_ID_10G)) {
2044                 int mmd = ffs(efx->phy_op->mmds) - 1;
2045                 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2046                 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2047                         & FALCON_PHY_ID_ID_MASK;
2048         }
2049
2050         spin_lock_bh(&efx->phy_lock);
2051
2052         /* Check MII not currently being accessed */
2053         if (falcon_gmii_wait(efx) != 0)
2054                 goto out;
2055
2056         EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2057         falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2058
2059         EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2060         falcon_write(efx, &reg, MD_ID_REG_KER);
2061
2062         /* Request data to be read */
2063         EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2064         falcon_write(efx, &reg, MD_CS_REG_KER);
2065
2066         /* Wait for data to become available */
2067         value = falcon_gmii_wait(efx);
2068         if (value == 0) {
2069                 falcon_read(efx, &reg, MD_RXD_REG_KER);
2070                 value = EFX_OWORD_FIELD(reg, MD_RXD);
2071                 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2072                             phy_id, addr, value);
2073         } else {
2074                 /* Abort the read operation */
2075                 EFX_POPULATE_OWORD_2(reg,
2076                                      MD_RIC, 0,
2077                                      MD_GC, 1);
2078                 falcon_write(efx, &reg, MD_CS_REG_KER);
2079
2080                 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2081                         "error %d\n", phy_id, addr, value);
2082         }
2083
2084  out:
2085         spin_unlock_bh(&efx->phy_lock);
2086
2087         return value;
2088 }
2089
2090 static void falcon_init_mdio(struct mii_if_info *gmii)
2091 {
2092         gmii->mdio_read = falcon_mdio_read;
2093         gmii->mdio_write = falcon_mdio_write;
2094         gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2095         gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2096 }
2097
2098 static int falcon_probe_phy(struct efx_nic *efx)
2099 {
2100         switch (efx->phy_type) {
2101         case PHY_TYPE_10XPRESS:
2102                 efx->phy_op = &falcon_tenxpress_phy_ops;
2103                 break;
2104         case PHY_TYPE_XFP:
2105                 efx->phy_op = &falcon_xfp_phy_ops;
2106                 break;
2107         default:
2108                 EFX_ERR(efx, "Unknown PHY type %d\n",
2109                         efx->phy_type);
2110                 return -1;
2111         }
2112
2113         efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
2114         return 0;
2115 }
2116
2117 /* This call is responsible for hooking in the MAC and PHY operations */
2118 int falcon_probe_port(struct efx_nic *efx)
2119 {
2120         int rc;
2121
2122         /* Hook in PHY operations table */
2123         rc = falcon_probe_phy(efx);
2124         if (rc)
2125                 return rc;
2126
2127         /* Set up GMII structure for PHY */
2128         efx->mii.supports_gmii = 1;
2129         falcon_init_mdio(&efx->mii);
2130
2131         /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2132         if (falcon_rev(efx) >= FALCON_REV_B0)
2133                 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2134         else
2135                 efx->flow_control = EFX_FC_RX;
2136
2137         /* Allocate buffer for stats */
2138         rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2139                                  FALCON_MAC_STATS_SIZE);
2140         if (rc)
2141                 return rc;
2142         EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2143                 (unsigned long long)efx->stats_buffer.dma_addr,
2144                 efx->stats_buffer.addr,
2145                 virt_to_phys(efx->stats_buffer.addr));
2146
2147         return 0;
2148 }
2149
2150 void falcon_remove_port(struct efx_nic *efx)
2151 {
2152         falcon_free_buffer(efx, &efx->stats_buffer);
2153 }
2154
2155 /**************************************************************************
2156  *
2157  * Multicast filtering
2158  *
2159  **************************************************************************
2160  */
2161
2162 void falcon_set_multicast_hash(struct efx_nic *efx)
2163 {
2164         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2165
2166         /* Broadcast packets go through the multicast hash filter.
2167          * ether_crc_le() of the broadcast address is 0xbe2612ff
2168          * so we always add bit 0xff to the mask.
2169          */
2170         set_bit_le(0xff, mc_hash->byte);
2171
2172         falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2173         falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2174 }
2175
2176 /**************************************************************************
2177  *
2178  * Device reset
2179  *
2180  **************************************************************************
2181  */
2182
2183 /* Resets NIC to known state.  This routine must be called in process
2184  * context and is allowed to sleep. */
2185 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2186 {
2187         struct falcon_nic_data *nic_data = efx->nic_data;
2188         efx_oword_t glb_ctl_reg_ker;
2189         int rc;
2190
2191         EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2192
2193         /* Initiate device reset */
2194         if (method == RESET_TYPE_WORLD) {
2195                 rc = pci_save_state(efx->pci_dev);
2196                 if (rc) {
2197                         EFX_ERR(efx, "failed to backup PCI state of primary "
2198                                 "function prior to hardware reset\n");
2199                         goto fail1;
2200                 }
2201                 if (FALCON_IS_DUAL_FUNC(efx)) {
2202                         rc = pci_save_state(nic_data->pci_dev2);
2203                         if (rc) {
2204                                 EFX_ERR(efx, "failed to backup PCI state of "
2205                                         "secondary function prior to "
2206                                         "hardware reset\n");
2207                                 goto fail2;
2208                         }
2209                 }
2210
2211                 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2212                                      EXT_PHY_RST_DUR, 0x7,
2213                                      SWRST, 1);
2214         } else {
2215                 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2216                                  EXCLUDE_FROM_RESET : 0);
2217
2218                 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2219                                      EXT_PHY_RST_CTL, reset_phy,
2220                                      PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2221                                      PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2222                                      PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2223                                      EE_RST_CTL, EXCLUDE_FROM_RESET,
2224                                      EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2225                                      SWRST, 1);
2226         }
2227         falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2228
2229         EFX_LOG(efx, "waiting for hardware reset\n");
2230         schedule_timeout_uninterruptible(HZ / 20);
2231
2232         /* Restore PCI configuration if needed */
2233         if (method == RESET_TYPE_WORLD) {
2234                 if (FALCON_IS_DUAL_FUNC(efx)) {
2235                         rc = pci_restore_state(nic_data->pci_dev2);
2236                         if (rc) {
2237                                 EFX_ERR(efx, "failed to restore PCI config for "
2238                                         "the secondary function\n");
2239                                 goto fail3;
2240                         }
2241                 }
2242                 rc = pci_restore_state(efx->pci_dev);
2243                 if (rc) {
2244                         EFX_ERR(efx, "failed to restore PCI config for the "
2245                                 "primary function\n");
2246                         goto fail4;
2247                 }
2248                 EFX_LOG(efx, "successfully restored PCI config\n");
2249         }
2250
2251         /* Assert that reset complete */
2252         falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2253         if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2254                 rc = -ETIMEDOUT;
2255                 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2256                 goto fail5;
2257         }
2258         EFX_LOG(efx, "hardware reset complete\n");
2259
2260         return 0;
2261
2262         /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2263 fail2:
2264 fail3:
2265         pci_restore_state(efx->pci_dev);
2266 fail1:
2267 fail4:
2268 fail5:
2269         return rc;
2270 }
2271
2272 /* Zeroes out the SRAM contents.  This routine must be called in
2273  * process context and is allowed to sleep.
2274  */
2275 static int falcon_reset_sram(struct efx_nic *efx)
2276 {
2277         efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2278         int count;
2279
2280         /* Set the SRAM wake/sleep GPIO appropriately. */
2281         falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2282         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2283         EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2284         falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2285
2286         /* Initiate SRAM reset */
2287         EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2288                              SRAM_OOB_BT_INIT_EN, 1,
2289                              SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2290         falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2291
2292         /* Wait for SRAM reset to complete */
2293         count = 0;
2294         do {
2295                 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2296
2297                 /* SRAM reset is slow; expect around 16ms */
2298                 schedule_timeout_uninterruptible(HZ / 50);
2299
2300                 /* Check for reset complete */
2301                 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2302                 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2303                         EFX_LOG(efx, "SRAM reset complete\n");
2304
2305                         return 0;
2306                 }
2307         } while (++count < 20); /* wait upto 0.4 sec */
2308
2309         EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2310         return -ETIMEDOUT;
2311 }
2312
2313 /* Extract non-volatile configuration */
2314 static int falcon_probe_nvconfig(struct efx_nic *efx)
2315 {
2316         struct falcon_nvconfig *nvconfig;
2317         efx_oword_t nic_stat;
2318         int device_id;
2319         unsigned addr_len;
2320         size_t offset, len;
2321         int magic_num, struct_ver, board_rev;
2322         int rc;
2323
2324         /* Find the boot device. */
2325         falcon_read(efx, &nic_stat, NIC_STAT_REG);
2326         if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) {
2327                 device_id = EE_SPI_FLASH;
2328                 addr_len = 3;
2329         } else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) {
2330                 device_id = EE_SPI_EEPROM;
2331                 addr_len = 2;
2332         } else {
2333                 return -ENODEV;
2334         }
2335
2336         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2337
2338         /* Read the whole configuration structure into memory. */
2339         for (offset = 0; offset < sizeof(*nvconfig); offset += len) {
2340                 len = min(sizeof(*nvconfig) - offset,
2341                           (size_t) FALCON_SPI_MAX_LEN);
2342                 rc = falcon_spi_read(efx, device_id, SPI_READ,
2343                                      NVCONFIG_BASE + offset, addr_len,
2344                                      (char *)nvconfig + offset, len);
2345                 if (rc)
2346                         goto out;
2347         }
2348
2349         /* Read the MAC addresses */
2350         memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2351
2352         /* Read the board configuration. */
2353         magic_num = le16_to_cpu(nvconfig->board_magic_num);
2354         struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2355
2356         if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
2357                 EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
2358                         "therefore using defaults\n", magic_num, struct_ver);
2359                 efx->phy_type = PHY_TYPE_NONE;
2360                 efx->mii.phy_id = PHY_ADDR_INVALID;
2361                 board_rev = 0;
2362         } else {
2363                 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2364
2365                 efx->phy_type = v2->port0_phy_type;
2366                 efx->mii.phy_id = v2->port0_phy_addr;
2367                 board_rev = le16_to_cpu(v2->board_revision);
2368         }
2369
2370         EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2371
2372         efx_set_board_info(efx, board_rev);
2373
2374  out:
2375         kfree(nvconfig);
2376         return rc;
2377 }
2378
2379 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2380  * count, port speed).  Set workaround and feature flags accordingly.
2381  */
2382 static int falcon_probe_nic_variant(struct efx_nic *efx)
2383 {
2384         efx_oword_t altera_build;
2385
2386         falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2387         if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2388                 EFX_ERR(efx, "Falcon FPGA not supported\n");
2389                 return -ENODEV;
2390         }
2391
2392         switch (falcon_rev(efx)) {
2393         case FALCON_REV_A0:
2394         case 0xff:
2395                 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2396                 return -ENODEV;
2397
2398         case FALCON_REV_A1:{
2399                 efx_oword_t nic_stat;
2400
2401                 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2402
2403                 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2404                         EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2405                         return -ENODEV;
2406                 }
2407                 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2408                         EFX_ERR(efx, "1G mode not supported\n");
2409                         return -ENODEV;
2410                 }
2411                 break;
2412         }
2413
2414         case FALCON_REV_B0:
2415                 break;
2416
2417         default:
2418                 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2419                 return -ENODEV;
2420         }
2421
2422         return 0;
2423 }
2424
2425 int falcon_probe_nic(struct efx_nic *efx)
2426 {
2427         struct falcon_nic_data *nic_data;
2428         int rc;
2429
2430         /* Allocate storage for hardware specific data */
2431         nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2432         efx->nic_data = nic_data;
2433
2434         /* Determine number of ports etc. */
2435         rc = falcon_probe_nic_variant(efx);
2436         if (rc)
2437                 goto fail1;
2438
2439         /* Probe secondary function if expected */
2440         if (FALCON_IS_DUAL_FUNC(efx)) {
2441                 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2442
2443                 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2444                                              dev))) {
2445                         if (dev->bus == efx->pci_dev->bus &&
2446                             dev->devfn == efx->pci_dev->devfn + 1) {
2447                                 nic_data->pci_dev2 = dev;
2448                                 break;
2449                         }
2450                 }
2451                 if (!nic_data->pci_dev2) {
2452                         EFX_ERR(efx, "failed to find secondary function\n");
2453                         rc = -ENODEV;
2454                         goto fail2;
2455                 }
2456         }
2457
2458         /* Now we can reset the NIC */
2459         rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2460         if (rc) {
2461                 EFX_ERR(efx, "failed to reset NIC\n");
2462                 goto fail3;
2463         }
2464
2465         /* Allocate memory for INT_KER */
2466         rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2467         if (rc)
2468                 goto fail4;
2469         BUG_ON(efx->irq_status.dma_addr & 0x0f);
2470
2471         EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2472                 (unsigned long long)efx->irq_status.dma_addr,
2473                 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2474
2475         /* Read in the non-volatile configuration */
2476         rc = falcon_probe_nvconfig(efx);
2477         if (rc)
2478                 goto fail5;
2479
2480         /* Initialise I2C adapter */
2481         efx->i2c_adap.owner = THIS_MODULE;
2482         efx->i2c_adap.class = I2C_CLASS_HWMON;
2483         nic_data->i2c_data = falcon_i2c_bit_operations;
2484         nic_data->i2c_data.data = efx;
2485         efx->i2c_adap.algo_data = &nic_data->i2c_data;
2486         efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2487         strcpy(efx->i2c_adap.name, "SFC4000 GPIO");
2488         rc = i2c_bit_add_bus(&efx->i2c_adap);
2489         if (rc)
2490                 goto fail5;
2491
2492         return 0;
2493
2494  fail5:
2495         falcon_free_buffer(efx, &efx->irq_status);
2496  fail4:
2497  fail3:
2498         if (nic_data->pci_dev2) {
2499                 pci_dev_put(nic_data->pci_dev2);
2500                 nic_data->pci_dev2 = NULL;
2501         }
2502  fail2:
2503  fail1:
2504         kfree(efx->nic_data);
2505         return rc;
2506 }
2507
2508 /* This call performs hardware-specific global initialisation, such as
2509  * defining the descriptor cache sizes and number of RSS channels.
2510  * It does not set up any buffers, descriptor rings or event queues.
2511  */
2512 int falcon_init_nic(struct efx_nic *efx)
2513 {
2514         efx_oword_t temp;
2515         unsigned thresh;
2516         int rc;
2517
2518         /* Set up the address region register. This is only needed
2519          * for the B0 FPGA, but since we are just pushing in the
2520          * reset defaults this may as well be unconditional. */
2521         EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2522                                    ADR_REGION1, (1 << 16),
2523                                    ADR_REGION2, (2 << 16),
2524                                    ADR_REGION3, (3 << 16));
2525         falcon_write(efx, &temp, ADR_REGION_REG_KER);
2526
2527         /* Use on-chip SRAM */
2528         falcon_read(efx, &temp, NIC_STAT_REG);
2529         EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2530         falcon_write(efx, &temp, NIC_STAT_REG);
2531
2532         /* Set buffer table mode */
2533         EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2534         falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2535
2536         rc = falcon_reset_sram(efx);
2537         if (rc)
2538                 return rc;
2539
2540         /* Set positions of descriptor caches in SRAM. */
2541         EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2542         falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2543         EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2544         falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2545
2546         /* Set TX descriptor cache size. */
2547         BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2548         EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2549         falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2550
2551         /* Set RX descriptor cache size.  Set low watermark to size-8, as
2552          * this allows most efficient prefetching.
2553          */
2554         BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2555         EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2556         falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2557         EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2558         falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2559
2560         /* Clear the parity enables on the TX data fifos as
2561          * they produce false parity errors because of timing issues
2562          */
2563         if (EFX_WORKAROUND_5129(efx)) {
2564                 falcon_read(efx, &temp, SPARE_REG_KER);
2565                 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2566                 falcon_write(efx, &temp, SPARE_REG_KER);
2567         }
2568
2569         /* Enable all the genuinely fatal interrupts.  (They are still
2570          * masked by the overall interrupt mask, controlled by
2571          * falcon_interrupts()).
2572          *
2573          * Note: All other fatal interrupts are enabled
2574          */
2575         EFX_POPULATE_OWORD_3(temp,
2576                              ILL_ADR_INT_KER_EN, 1,
2577                              RBUF_OWN_INT_KER_EN, 1,
2578                              TBUF_OWN_INT_KER_EN, 1);
2579         EFX_INVERT_OWORD(temp);
2580         falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2581
2582         /* Set number of RSS queues for receive path. */
2583         falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2584         if (falcon_rev(efx) >= FALCON_REV_B0)
2585                 EFX_SET_OWORD_FIELD(temp, NUM_KER, 0);
2586         else
2587                 EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1);
2588         if (EFX_WORKAROUND_7244(efx)) {
2589                 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2590                 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2591                 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2592                 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2593         }
2594         falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2595
2596         falcon_setup_rss_indir_table(efx);
2597
2598         /* Setup RX.  Wait for descriptor is broken and must
2599          * be disabled.  RXDP recovery shouldn't be needed, but is.
2600          */
2601         falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2602         EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2603         EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2604         if (EFX_WORKAROUND_5583(efx))
2605                 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2606         falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2607
2608         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2609          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2610          */
2611         falcon_read(efx, &temp, TX_CFG2_REG_KER);
2612         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2613         EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2614         EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2615         EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2616         EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2617         /* Enable SW_EV to inherit in char driver - assume harmless here */
2618         EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2619         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2620         EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2621         /* Squash TX of packets of 16 bytes or less */
2622         if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
2623                 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2624         falcon_write(efx, &temp, TX_CFG2_REG_KER);
2625
2626         /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2627          * descriptors (which is bad).
2628          */
2629         falcon_read(efx, &temp, TX_CFG_REG_KER);
2630         EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2631         falcon_write(efx, &temp, TX_CFG_REG_KER);
2632
2633         /* RX config */
2634         falcon_read(efx, &temp, RX_CFG_REG_KER);
2635         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2636         if (EFX_WORKAROUND_7575(efx))
2637                 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2638                                         (3 * 4096) / 32);
2639         if (falcon_rev(efx) >= FALCON_REV_B0)
2640                 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2641
2642         /* RX FIFO flow control thresholds */
2643         thresh = ((rx_xon_thresh_bytes >= 0) ?
2644                   rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2645         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2646         thresh = ((rx_xoff_thresh_bytes >= 0) ?
2647                   rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2648         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2649         /* RX control FIFO thresholds [32 entries] */
2650         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 25);
2651         EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 20);
2652         falcon_write(efx, &temp, RX_CFG_REG_KER);
2653
2654         /* Set destination of both TX and RX Flush events */
2655         if (falcon_rev(efx) >= FALCON_REV_B0) {
2656                 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2657                 falcon_write(efx, &temp, DP_CTRL_REG);
2658         }
2659
2660         return 0;
2661 }
2662
2663 void falcon_remove_nic(struct efx_nic *efx)
2664 {
2665         struct falcon_nic_data *nic_data = efx->nic_data;
2666         int rc;
2667
2668         rc = i2c_del_adapter(&efx->i2c_adap);
2669         BUG_ON(rc);
2670
2671         falcon_free_buffer(efx, &efx->irq_status);
2672
2673         falcon_reset_hw(efx, RESET_TYPE_ALL);
2674
2675         /* Release the second function after the reset */
2676         if (nic_data->pci_dev2) {
2677                 pci_dev_put(nic_data->pci_dev2);
2678                 nic_data->pci_dev2 = NULL;
2679         }
2680
2681         /* Tear down the private nic state */
2682         kfree(efx->nic_data);
2683         efx->nic_data = NULL;
2684 }
2685
2686 void falcon_update_nic_stats(struct efx_nic *efx)
2687 {
2688         efx_oword_t cnt;
2689
2690         falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
2691         efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
2692 }
2693
2694 /**************************************************************************
2695  *
2696  * Revision-dependent attributes used by efx.c
2697  *
2698  **************************************************************************
2699  */
2700
2701 struct efx_nic_type falcon_a_nic_type = {
2702         .mem_bar = 2,
2703         .mem_map_size = 0x20000,
2704         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
2705         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
2706         .buf_tbl_base = BUF_TBL_KER_A1,
2707         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
2708         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
2709         .txd_ring_mask = FALCON_TXD_RING_MASK,
2710         .rxd_ring_mask = FALCON_RXD_RING_MASK,
2711         .evq_size = FALCON_EVQ_SIZE,
2712         .max_dma_mask = FALCON_DMA_MASK,
2713         .tx_dma_mask = FALCON_TX_DMA_MASK,
2714         .bug5391_mask = 0xf,
2715         .rx_xoff_thresh = 2048,
2716         .rx_xon_thresh = 512,
2717         .rx_buffer_padding = 0x24,
2718         .max_interrupt_mode = EFX_INT_MODE_MSI,
2719         .phys_addr_channels = 4,
2720 };
2721
2722 struct efx_nic_type falcon_b_nic_type = {
2723         .mem_bar = 2,
2724         /* Map everything up to and including the RSS indirection
2725          * table.  Don't map MSI-X table, MSI-X PBA since Linux
2726          * requires that they not be mapped.  */
2727         .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
2728         .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
2729         .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
2730         .buf_tbl_base = BUF_TBL_KER_B0,
2731         .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
2732         .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
2733         .txd_ring_mask = FALCON_TXD_RING_MASK,
2734         .rxd_ring_mask = FALCON_RXD_RING_MASK,
2735         .evq_size = FALCON_EVQ_SIZE,
2736         .max_dma_mask = FALCON_DMA_MASK,
2737         .tx_dma_mask = FALCON_TX_DMA_MASK,
2738         .bug5391_mask = 0,
2739         .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
2740         .rx_xon_thresh = 27648,  /* ~3*max MTU */
2741         .rx_buffer_padding = 0,
2742         .max_interrupt_mode = EFX_INT_MODE_MSIX,
2743         .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
2744                                    * interrupt handler only supports 32
2745                                    * channels */
2746 };
2747