1 /* Silan SC92031 PCI Fast Ethernet Adapter driver
3 * Based on vendor drivers:
4 * Silan Fast Ethernet Netcard Driver:
5 * MODULE_AUTHOR ("gaoyonghong");
6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
7 * MODULE_LICENSE("GPL");
8 * 8139D Fast Ethernet driver:
9 * (C) 2002 by gaoyonghong
10 * MODULE_AUTHOR ("gaoyonghong");
11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
12 * MODULE_LICENSE("GPL");
13 * Both are almost identical and seem to be based on pci-skeleton.c
15 * Rewritten for 2.6 by Cesar Eduardo Barros
18 /* Note about set_mac_address: I don't know how to change the hardware
19 * matching, so you need to enable IFF_PROMISC when using it.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/pci.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/crc32.h>
34 #define PCI_VENDOR_ID_SILAN 0x1904
35 #define PCI_DEVICE_ID_SILAN_SC92031 0x2031
36 #define PCI_DEVICE_ID_SILAN_8139D 0x8139
38 #define SC92031_NAME "sc92031"
40 /* BAR 0 is MMIO, BAR 1 is PIO */
41 #ifndef SC92031_USE_BAR
42 #define SC92031_USE_BAR 0
45 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
46 static int multicast_filter_limit = 64;
47 module_param(multicast_filter_limit, int, 0);
48 MODULE_PARM_DESC(multicast_filter_limit,
49 "Maximum number of filtered multicast addresses");
52 module_param(media, int, 0);
53 MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
54 " 0x01 = 10M half, 0x02 = 10M full,"
55 " 0x04 = 100M half, 0x08 = 100M full)");
57 /* Size of the in-memory receive ring. */
58 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
59 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
61 /* Number of Tx descriptor registers. */
64 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
65 #define MAX_ETH_FRAME_SIZE 1536
67 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
68 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
69 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
71 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
72 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
74 /* Time in jiffies before concluding the transmitter is hung. */
75 #define TX_TIMEOUT (4*HZ)
77 #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
80 #define AUTOSELECT 0x00
83 #define M100_HALF 0x04
84 #define M100_FULL 0x08
86 /* Symbolic offsets to registers. */
87 enum silan_registers {
88 Config0 = 0x00, // Config0
89 Config1 = 0x04, // Config1
90 RxBufWPtr = 0x08, // Rx buffer writer poiter
91 IntrStatus = 0x0C, // Interrupt status
92 IntrMask = 0x10, // Interrupt mask
93 RxbufAddr = 0x14, // Rx buffer start address
94 RxBufRPtr = 0x18, // Rx buffer read pointer
95 Txstatusall = 0x1C, // Transmit status of all descriptors
96 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
97 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
98 RxConfig = 0x40, // Rx configuration
99 MAC0 = 0x44, // Ethernet hardware address.
100 MAR0 = 0x4C, // Multicast filter.
101 RxStatus0 = 0x54, // Rx status
102 TxConfig = 0x5C, // Tx configuration
103 PhyCtrl = 0x60, // physical control
104 FlowCtrlConfig = 0x64, // flow control
105 Miicmd0 = 0x68, // Mii command0 register
106 Miicmd1 = 0x6C, // Mii command1 register
107 Miistatus = 0x70, // Mii status register
108 Timercnt = 0x74, // Timer counter register
109 TimerIntr = 0x78, // Timer interrupt register
110 PMConfig = 0x7C, // Power Manager configuration
111 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
112 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
113 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
119 #define MII_BMCR 0 // Basic mode control register
120 #define MII_BMSR 1 // Basic mode status register
122 #define MII_OutputStatus 24
124 #define BMCR_FULLDPLX 0x0100 // Full duplex
125 #define BMCR_ANRESTART 0x0200 // Auto negotiation restart
126 #define BMCR_ANENABLE 0x1000 // Enable auto negotiation
127 #define BMCR_SPEED100 0x2000 // Select 100Mbps
128 #define BMSR_LSTATUS 0x0004 // Link status
129 #define PHY_16_JAB_ENB 0x1000
130 #define PHY_16_PORT_ENB 0x1
132 enum IntrStatusBits {
133 LinkFail = 0x80000000,
135 TimeOut = 0x20000000,
139 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
143 TxCarrierLost = 0x20000000,
144 TxAborted = 0x10000000,
145 TxOutOfWindow = 0x08000000,
147 EarlyTxThresShift = 16,
154 RxStatesOK = 0x80000,
155 RxBadAlign = 0x40000,
156 RxHugeFrame = 0x20000,
157 RxSmallFrame = 0x10000,
160 Rx_Broadcast = 0x2000,
161 Rx_Multicast = 0x1000,
162 RxAddrMatch = 0x0800,
167 RxFullDx = 0x80000000,
169 RxSmall = 0x20000000,
172 RxAllphys = 0x04000000,
173 RxMulticast = 0x02000000,
174 RxBroadcast = 0x01000000,
175 RxLoopBack = (1 << 23) | (1 << 22),
176 LowThresholdShift = 12,
177 HighThresholdShift = 2,
181 TxFullDx = 0x80000000,
183 TxEnbPad = 0x20000000,
184 TxEnbHuge = 0x10000000,
185 TxEnbFCS = 0x08000000,
186 TxNoBackOff = 0x04000000,
187 TxEnbPrem = 0x02000000,
188 TxCareLostCrs = 0x1000000,
189 TxExdCollNum = 0xf00000,
190 TxDataRate = 0x80000,
193 enum PhyCtrlconfigbits {
194 PhyCtrlAne = 0x80000000,
195 PhyCtrlSpd100 = 0x40000000,
196 PhyCtrlSpd10 = 0x20000000,
197 PhyCtrlPhyBaseAddr = 0x1f000000,
198 PhyCtrlDux = 0x800000,
199 PhyCtrlReset = 0x400000,
202 enum FlowCtrlConfigBits {
203 FlowCtrlFullDX = 0x80000000,
204 FlowCtrlEnb = 0x40000000,
208 Cfg0_Reset = 0x80000000,
209 Cfg0_Anaoff = 0x40000000,
210 Cfg0_LDPS = 0x20000000,
214 Cfg1_EarlyRx = 1 << 31,
215 Cfg1_EarlyTx = 1 << 30,
226 Mii_Divider = 0x20000000,
227 Mii_WRITE = 0x400000,
231 Mii_Drvmod = 0x40000,
239 Mii_StatusBusy = 0x80000000,
246 PM_LANWake = 1 << 28,
247 PM_LWPTN = (1 << 27 | 1<< 26),
253 * priv->lock protects most of the fields of priv and most of the
254 * hardware registers. It does not have to protect against softirqs
255 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
256 * it also does not need to be used in ->open and ->stop while the
257 * device interrupts are off.
258 * Not having to protect against softirqs is very useful due to heavy
259 * use of mdelay() at _sc92031_reset.
260 * Functions prefixed with _sc92031_ must be called with the lock held;
261 * functions prefixed with sc92031_ must be called without the lock held.
262 * Use mmiowb() before unlocking if the hardware was written to.
265 /* Locking rules for the interrupt:
266 * - the interrupt and the tasklet never run at the same time
267 * - neither run between sc92031_disable_interrupts and
268 * sc92031_enable_interrupt
271 struct sc92031_priv {
274 void __iomem *port_base;
275 /* pci device structure */
276 struct pci_dev *pdev;
278 struct tasklet_struct tasklet;
280 /* CPU address of rx ring */
282 /* PCI address of rx ring */
283 dma_addr_t rx_ring_dma_addr;
284 /* PCI address of rx ring read pointer */
285 dma_addr_t rx_ring_tail;
287 /* tx ring write index */
289 /* tx ring read index */
291 /* CPU address of tx bounce buffer */
293 /* PCI address of tx bounce buffer */
294 dma_addr_t tx_bufs_dma_addr;
296 /* copies of some hardware registers */
303 /* copy of some flags from dev->flags */
304 unsigned int mc_flags;
306 /* for ETHTOOL_GSTATS */
310 /* for dev->get_stats */
314 /* I don't know which registers can be safely read; however, I can guess
315 * MAC0 is one of them. */
316 static inline void _sc92031_dummy_read(void __iomem *port_base)
318 ioread32(port_base + MAC0);
321 static u32 _sc92031_mii_wait(void __iomem *port_base)
327 mii_status = ioread32(port_base + Miistatus);
328 } while (mii_status & Mii_StatusBusy);
333 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
335 iowrite32(Mii_Divider, port_base + Miicmd0);
337 _sc92031_mii_wait(port_base);
339 iowrite32(cmd1, port_base + Miicmd1);
340 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
342 return _sc92031_mii_wait(port_base);
345 static void _sc92031_mii_scan(void __iomem *port_base)
347 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
350 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
352 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
355 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
357 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
360 static void sc92031_disable_interrupts(struct net_device *dev)
362 struct sc92031_priv *priv = netdev_priv(dev);
363 void __iomem *port_base = priv->port_base;
365 /* tell the tasklet/interrupt not to enable interrupts */
366 atomic_set(&priv->intr_mask, 0);
369 /* stop interrupts */
370 iowrite32(0, port_base + IntrMask);
371 _sc92031_dummy_read(port_base);
374 /* wait for any concurrent interrupt/tasklet to finish */
375 synchronize_irq(dev->irq);
376 tasklet_disable(&priv->tasklet);
379 static void sc92031_enable_interrupts(struct net_device *dev)
381 struct sc92031_priv *priv = netdev_priv(dev);
382 void __iomem *port_base = priv->port_base;
384 tasklet_enable(&priv->tasklet);
386 atomic_set(&priv->intr_mask, IntrBits);
389 iowrite32(IntrBits, port_base + IntrMask);
393 static void _sc92031_disable_tx_rx(struct net_device *dev)
395 struct sc92031_priv *priv = netdev_priv(dev);
396 void __iomem *port_base = priv->port_base;
398 priv->rx_config &= ~RxEnb;
399 priv->tx_config &= ~TxEnb;
400 iowrite32(priv->rx_config, port_base + RxConfig);
401 iowrite32(priv->tx_config, port_base + TxConfig);
404 static void _sc92031_enable_tx_rx(struct net_device *dev)
406 struct sc92031_priv *priv = netdev_priv(dev);
407 void __iomem *port_base = priv->port_base;
409 priv->rx_config |= RxEnb;
410 priv->tx_config |= TxEnb;
411 iowrite32(priv->rx_config, port_base + RxConfig);
412 iowrite32(priv->tx_config, port_base + TxConfig);
415 static void _sc92031_tx_clear(struct net_device *dev)
417 struct sc92031_priv *priv = netdev_priv(dev);
419 while (priv->tx_head - priv->tx_tail > 0) {
421 dev->stats.tx_dropped++;
423 priv->tx_head = priv->tx_tail = 0;
426 static void _sc92031_set_mar(struct net_device *dev)
428 struct sc92031_priv *priv = netdev_priv(dev);
429 void __iomem *port_base = priv->port_base;
430 u32 mar0 = 0, mar1 = 0;
432 if ((dev->flags & IFF_PROMISC)
433 || dev->mc_count > multicast_filter_limit
434 || (dev->flags & IFF_ALLMULTI))
435 mar0 = mar1 = 0xffffffff;
436 else if (dev->flags & IFF_MULTICAST) {
437 struct dev_mc_list *mc_list;
439 for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) {
443 crc = ~ether_crc(ETH_ALEN, mc_list->dmi_addr);
446 if (crc & 0x01) bit |= 0x02;
447 if (crc & 0x02) bit |= 0x01;
448 if (crc & 0x10) bit |= 0x20;
449 if (crc & 0x20) bit |= 0x10;
450 if (crc & 0x40) bit |= 0x08;
451 if (crc & 0x80) bit |= 0x04;
454 mar0 |= 0x1 << (bit - 32);
460 iowrite32(mar0, port_base + MAR0);
461 iowrite32(mar1, port_base + MAR0 + 4);
464 static void _sc92031_set_rx_config(struct net_device *dev)
466 struct sc92031_priv *priv = netdev_priv(dev);
467 void __iomem *port_base = priv->port_base;
468 unsigned int old_mc_flags;
469 u32 rx_config_bits = 0;
471 old_mc_flags = priv->mc_flags;
473 if (dev->flags & IFF_PROMISC)
474 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
475 | RxMulticast | RxAllphys;
477 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
478 rx_config_bits |= RxMulticast;
480 if (dev->flags & IFF_BROADCAST)
481 rx_config_bits |= RxBroadcast;
483 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
484 | RxMulticast | RxAllphys);
485 priv->rx_config |= rx_config_bits;
487 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
488 | IFF_MULTICAST | IFF_BROADCAST);
490 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
491 iowrite32(priv->rx_config, port_base + RxConfig);
494 static bool _sc92031_check_media(struct net_device *dev)
496 struct sc92031_priv *priv = netdev_priv(dev);
497 void __iomem *port_base = priv->port_base;
500 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
502 if (bmsr & BMSR_LSTATUS) {
503 bool speed_100, duplex_full;
504 u32 flow_ctrl_config = 0;
505 u16 output_status = _sc92031_mii_read(port_base,
507 _sc92031_mii_scan(port_base);
509 speed_100 = output_status & 0x2;
510 duplex_full = output_status & 0x4;
512 /* Initial Tx/Rx configuration */
513 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
514 priv->tx_config = 0x48800000;
516 /* NOTE: vendor driver had dead code here to enable tx padding */
519 priv->tx_config |= 0x80000;
522 _sc92031_set_rx_config(dev);
525 priv->rx_config |= RxFullDx;
526 priv->tx_config |= TxFullDx;
527 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
529 priv->rx_config &= ~RxFullDx;
530 priv->tx_config &= ~TxFullDx;
533 _sc92031_set_mar(dev);
534 _sc92031_set_rx_config(dev);
535 _sc92031_enable_tx_rx(dev);
536 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
538 netif_carrier_on(dev);
540 if (printk_ratelimit())
541 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
543 speed_100 ? "100" : "10",
544 duplex_full ? "full" : "half");
547 _sc92031_mii_scan(port_base);
549 netif_carrier_off(dev);
551 _sc92031_disable_tx_rx(dev);
553 if (printk_ratelimit())
554 printk(KERN_INFO "%s: link down\n", dev->name);
559 static void _sc92031_phy_reset(struct net_device *dev)
561 struct sc92031_priv *priv = netdev_priv(dev);
562 void __iomem *port_base = priv->port_base;
565 phy_ctrl = ioread32(port_base + PhyCtrl);
566 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
567 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
572 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
575 phy_ctrl |= PhyCtrlSpd10;
578 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
581 phy_ctrl |= PhyCtrlSpd100;
584 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
588 iowrite32(phy_ctrl, port_base + PhyCtrl);
591 phy_ctrl &= ~PhyCtrlReset;
592 iowrite32(phy_ctrl, port_base + PhyCtrl);
595 _sc92031_mii_write(port_base, MII_JAB,
596 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
597 _sc92031_mii_scan(port_base);
599 netif_carrier_off(dev);
600 netif_stop_queue(dev);
603 static void _sc92031_reset(struct net_device *dev)
605 struct sc92031_priv *priv = netdev_priv(dev);
606 void __iomem *port_base = priv->port_base;
609 iowrite32(0, port_base + PMConfig);
611 /* soft reset the chip */
612 iowrite32(Cfg0_Reset, port_base + Config0);
615 iowrite32(0, port_base + Config0);
618 /* disable interrupts */
619 iowrite32(0, port_base + IntrMask);
621 /* clear multicast address */
622 iowrite32(0, port_base + MAR0);
623 iowrite32(0, port_base + MAR0 + 4);
626 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
627 priv->rx_ring_tail = priv->rx_ring_dma_addr;
630 _sc92031_tx_clear(dev);
632 /* clear old register values */
633 priv->intr_status = 0;
634 atomic_set(&priv->intr_mask, 0);
639 /* configure rx buffer size */
640 /* NOTE: vendor driver had dead code here to enable early tx/rx */
641 iowrite32(Cfg1_Rcv64K, port_base + Config1);
643 _sc92031_phy_reset(dev);
644 _sc92031_check_media(dev);
646 /* calculate rx fifo overflow */
650 iowrite32(priv->pm_config, port_base + PMConfig);
652 /* clear intr register */
653 ioread32(port_base + IntrStatus);
656 static void _sc92031_tx_tasklet(struct net_device *dev)
658 struct sc92031_priv *priv = netdev_priv(dev);
659 void __iomem *port_base = priv->port_base;
661 unsigned old_tx_tail;
665 old_tx_tail = priv->tx_tail;
666 while (priv->tx_head - priv->tx_tail > 0) {
667 entry = priv->tx_tail % NUM_TX_DESC;
668 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
670 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
675 if (tx_status & TxStatOK) {
676 dev->stats.tx_bytes += tx_status & 0x1fff;
677 dev->stats.tx_packets++;
678 /* Note: TxCarrierLost is always asserted at 100mbps. */
679 dev->stats.collisions += (tx_status >> 22) & 0xf;
682 if (tx_status & (TxOutOfWindow | TxAborted)) {
683 dev->stats.tx_errors++;
685 if (tx_status & TxAborted)
686 dev->stats.tx_aborted_errors++;
688 if (tx_status & TxCarrierLost)
689 dev->stats.tx_carrier_errors++;
691 if (tx_status & TxOutOfWindow)
692 dev->stats.tx_window_errors++;
695 if (tx_status & TxUnderrun)
696 dev->stats.tx_fifo_errors++;
699 if (priv->tx_tail != old_tx_tail)
700 if (netif_queue_stopped(dev))
701 netif_wake_queue(dev);
704 static void _sc92031_rx_tasklet_error(struct net_device *dev,
705 u32 rx_status, unsigned rx_size)
707 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
708 dev->stats.rx_errors++;
709 dev->stats.rx_length_errors++;
712 if (!(rx_status & RxStatesOK)) {
713 dev->stats.rx_errors++;
715 if (rx_status & (RxHugeFrame | RxSmallFrame))
716 dev->stats.rx_length_errors++;
718 if (rx_status & RxBadAlign)
719 dev->stats.rx_frame_errors++;
721 if (!(rx_status & RxCRCOK))
722 dev->stats.rx_crc_errors++;
724 struct sc92031_priv *priv = netdev_priv(dev);
729 static void _sc92031_rx_tasklet(struct net_device *dev)
731 struct sc92031_priv *priv = netdev_priv(dev);
732 void __iomem *port_base = priv->port_base;
734 dma_addr_t rx_ring_head;
736 unsigned rx_ring_offset;
737 void *rx_ring = priv->rx_ring;
739 rx_ring_head = ioread32(port_base + RxBufWPtr);
742 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
743 * we need to change it to 32 bits physical address
745 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
746 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
747 if (rx_ring_head < priv->rx_ring_dma_addr)
748 rx_ring_head += RX_BUF_LEN;
750 if (rx_ring_head >= priv->rx_ring_tail)
751 rx_len = rx_ring_head - priv->rx_ring_tail;
753 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
758 if (unlikely(rx_len > RX_BUF_LEN)) {
759 if (printk_ratelimit())
760 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
765 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
769 unsigned rx_size, rx_size_align, pkt_size;
772 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
775 rx_size = rx_status >> 20;
776 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
777 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
779 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
781 if (unlikely(rx_status == 0
782 || rx_size > (MAX_ETH_FRAME_SIZE + 4)
784 || !(rx_status & RxStatesOK))) {
785 _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
789 if (unlikely(rx_size_align + 4 > rx_len)) {
790 if (printk_ratelimit())
791 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
795 rx_len -= rx_size_align + 4;
797 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
798 if (unlikely(!skb)) {
799 if (printk_ratelimit())
800 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
801 dev->name, pkt_size);
805 skb_reserve(skb, NET_IP_ALIGN);
807 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
808 memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
809 rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
810 memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
811 rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
813 memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
816 skb->protocol = eth_type_trans(skb, dev);
819 dev->stats.rx_bytes += pkt_size;
820 dev->stats.rx_packets++;
822 if (rx_status & Rx_Multicast)
823 dev->stats.multicast++;
826 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
830 priv->rx_ring_tail = rx_ring_head;
831 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
834 static void _sc92031_link_tasklet(struct net_device *dev)
836 if (_sc92031_check_media(dev))
837 netif_wake_queue(dev);
839 netif_stop_queue(dev);
840 dev->stats.tx_carrier_errors++;
844 static void sc92031_tasklet(unsigned long data)
846 struct net_device *dev = (struct net_device *)data;
847 struct sc92031_priv *priv = netdev_priv(dev);
848 void __iomem *port_base = priv->port_base;
849 u32 intr_status, intr_mask;
851 intr_status = priv->intr_status;
853 spin_lock(&priv->lock);
855 if (unlikely(!netif_running(dev)))
858 if (intr_status & TxOK)
859 _sc92031_tx_tasklet(dev);
861 if (intr_status & RxOK)
862 _sc92031_rx_tasklet(dev);
864 if (intr_status & RxOverflow)
865 dev->stats.rx_errors++;
867 if (intr_status & TimeOut) {
868 dev->stats.rx_errors++;
869 dev->stats.rx_length_errors++;
872 if (intr_status & (LinkFail | LinkOK))
873 _sc92031_link_tasklet(dev);
876 intr_mask = atomic_read(&priv->intr_mask);
879 iowrite32(intr_mask, port_base + IntrMask);
882 spin_unlock(&priv->lock);
885 static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
887 struct net_device *dev = dev_id;
888 struct sc92031_priv *priv = netdev_priv(dev);
889 void __iomem *port_base = priv->port_base;
890 u32 intr_status, intr_mask;
892 /* mask interrupts before clearing IntrStatus */
893 iowrite32(0, port_base + IntrMask);
894 _sc92031_dummy_read(port_base);
896 intr_status = ioread32(port_base + IntrStatus);
897 if (unlikely(intr_status == 0xffffffff))
898 return IRQ_NONE; // hardware has gone missing
900 intr_status &= IntrBits;
904 priv->intr_status = intr_status;
905 tasklet_schedule(&priv->tasklet);
910 intr_mask = atomic_read(&priv->intr_mask);
913 iowrite32(intr_mask, port_base + IntrMask);
919 static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
921 struct sc92031_priv *priv = netdev_priv(dev);
922 void __iomem *port_base = priv->port_base;
924 // FIXME I do not understand what is this trying to do.
925 if (netif_running(dev)) {
928 spin_lock_bh(&priv->lock);
930 /* Update the error count. */
931 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
933 if (temp == 0xffff) {
934 priv->rx_value += temp;
935 dev->stats.rx_fifo_errors = priv->rx_value;
937 dev->stats.rx_fifo_errors = temp + priv->rx_value;
939 spin_unlock_bh(&priv->lock);
945 static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
947 struct sc92031_priv *priv = netdev_priv(dev);
948 void __iomem *port_base = priv->port_base;
953 if (unlikely(skb->len > TX_BUF_SIZE)) {
954 dev->stats.tx_dropped++;
958 spin_lock(&priv->lock);
960 if (unlikely(!netif_carrier_ok(dev))) {
961 dev->stats.tx_dropped++;
965 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
967 entry = priv->tx_head++ % NUM_TX_DESC;
969 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
972 if (len < ETH_ZLEN) {
973 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
983 tx_status = 0x30000 | len;
985 tx_status = 0x50000 | len;
987 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
988 port_base + TxAddr0 + entry * 4);
989 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
992 dev->trans_start = jiffies;
994 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
995 netif_stop_queue(dev);
998 spin_unlock(&priv->lock);
1003 return NETDEV_TX_OK;
1006 static int sc92031_open(struct net_device *dev)
1009 struct sc92031_priv *priv = netdev_priv(dev);
1010 struct pci_dev *pdev = priv->pdev;
1012 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
1013 &priv->rx_ring_dma_addr);
1014 if (unlikely(!priv->rx_ring)) {
1016 goto out_alloc_rx_ring;
1019 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1020 &priv->tx_bufs_dma_addr);
1021 if (unlikely(!priv->tx_bufs)) {
1023 goto out_alloc_tx_bufs;
1025 priv->tx_head = priv->tx_tail = 0;
1027 err = request_irq(pdev->irq, sc92031_interrupt,
1028 IRQF_SHARED, dev->name, dev);
1029 if (unlikely(err < 0))
1030 goto out_request_irq;
1032 priv->pm_config = 0;
1034 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1035 spin_lock_bh(&priv->lock);
1037 _sc92031_reset(dev);
1040 spin_unlock_bh(&priv->lock);
1041 sc92031_enable_interrupts(dev);
1043 if (netif_carrier_ok(dev))
1044 netif_start_queue(dev);
1046 netif_tx_disable(dev);
1051 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1052 priv->tx_bufs_dma_addr);
1054 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1055 priv->rx_ring_dma_addr);
1060 static int sc92031_stop(struct net_device *dev)
1062 struct sc92031_priv *priv = netdev_priv(dev);
1063 struct pci_dev *pdev = priv->pdev;
1065 netif_tx_disable(dev);
1067 /* Disable interrupts, stop Tx and Rx. */
1068 sc92031_disable_interrupts(dev);
1070 spin_lock_bh(&priv->lock);
1072 _sc92031_disable_tx_rx(dev);
1073 _sc92031_tx_clear(dev);
1076 spin_unlock_bh(&priv->lock);
1078 free_irq(pdev->irq, dev);
1079 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1080 priv->tx_bufs_dma_addr);
1081 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1082 priv->rx_ring_dma_addr);
1087 static void sc92031_set_multicast_list(struct net_device *dev)
1089 struct sc92031_priv *priv = netdev_priv(dev);
1091 spin_lock_bh(&priv->lock);
1093 _sc92031_set_mar(dev);
1094 _sc92031_set_rx_config(dev);
1097 spin_unlock_bh(&priv->lock);
1100 static void sc92031_tx_timeout(struct net_device *dev)
1102 struct sc92031_priv *priv = netdev_priv(dev);
1104 /* Disable interrupts by clearing the interrupt mask.*/
1105 sc92031_disable_interrupts(dev);
1107 spin_lock(&priv->lock);
1109 priv->tx_timeouts++;
1111 _sc92031_reset(dev);
1114 spin_unlock(&priv->lock);
1116 /* enable interrupts */
1117 sc92031_enable_interrupts(dev);
1119 if (netif_carrier_ok(dev))
1120 netif_wake_queue(dev);
1123 #ifdef CONFIG_NET_POLL_CONTROLLER
1124 static void sc92031_poll_controller(struct net_device *dev)
1126 disable_irq(dev->irq);
1127 if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE)
1128 sc92031_tasklet((unsigned long)dev);
1129 enable_irq(dev->irq);
1133 static int sc92031_ethtool_get_settings(struct net_device *dev,
1134 struct ethtool_cmd *cmd)
1136 struct sc92031_priv *priv = netdev_priv(dev);
1137 void __iomem *port_base = priv->port_base;
1142 spin_lock_bh(&priv->lock);
1144 phy_address = ioread32(port_base + Miicmd1) >> 27;
1145 phy_ctrl = ioread32(port_base + PhyCtrl);
1147 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1148 _sc92031_mii_scan(port_base);
1151 spin_unlock_bh(&priv->lock);
1153 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1154 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1155 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1157 cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
1159 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1160 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1161 cmd->advertising |= ADVERTISED_Autoneg;
1163 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1164 cmd->advertising |= ADVERTISED_10baseT_Half;
1166 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1167 == (PhyCtrlSpd10 | PhyCtrlDux))
1168 cmd->advertising |= ADVERTISED_10baseT_Full;
1170 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1171 cmd->advertising |= ADVERTISED_100baseT_Half;
1173 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1174 == (PhyCtrlSpd100 | PhyCtrlDux))
1175 cmd->advertising |= ADVERTISED_100baseT_Full;
1177 if (phy_ctrl & PhyCtrlAne)
1178 cmd->advertising |= ADVERTISED_Autoneg;
1180 cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1181 cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1182 cmd->port = PORT_MII;
1183 cmd->phy_address = phy_address;
1184 cmd->transceiver = XCVR_INTERNAL;
1185 cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1190 static int sc92031_ethtool_set_settings(struct net_device *dev,
1191 struct ethtool_cmd *cmd)
1193 struct sc92031_priv *priv = netdev_priv(dev);
1194 void __iomem *port_base = priv->port_base;
1198 if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100))
1200 if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
1202 if (!(cmd->port == PORT_MII))
1204 if (!(cmd->phy_address == 0x1f))
1206 if (!(cmd->transceiver == XCVR_INTERNAL))
1208 if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
1211 if (cmd->autoneg == AUTONEG_ENABLE) {
1212 if (!(cmd->advertising & (ADVERTISED_Autoneg
1213 | ADVERTISED_100baseT_Full
1214 | ADVERTISED_100baseT_Half
1215 | ADVERTISED_10baseT_Full
1216 | ADVERTISED_10baseT_Half)))
1219 phy_ctrl = PhyCtrlAne;
1221 // FIXME: I'm not sure what the original code was trying to do
1222 if (cmd->advertising & ADVERTISED_Autoneg)
1223 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1224 if (cmd->advertising & ADVERTISED_100baseT_Full)
1225 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1226 if (cmd->advertising & ADVERTISED_100baseT_Half)
1227 phy_ctrl |= PhyCtrlSpd100;
1228 if (cmd->advertising & ADVERTISED_10baseT_Full)
1229 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1230 if (cmd->advertising & ADVERTISED_10baseT_Half)
1231 phy_ctrl |= PhyCtrlSpd10;
1233 // FIXME: Whole branch guessed
1236 if (cmd->speed == SPEED_10)
1237 phy_ctrl |= PhyCtrlSpd10;
1238 else /* cmd->speed == SPEED_100 */
1239 phy_ctrl |= PhyCtrlSpd100;
1241 if (cmd->duplex == DUPLEX_FULL)
1242 phy_ctrl |= PhyCtrlDux;
1245 spin_lock_bh(&priv->lock);
1247 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1248 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1249 | PhyCtrlSpd100 | PhyCtrlSpd10);
1250 if (phy_ctrl != old_phy_ctrl)
1251 iowrite32(phy_ctrl, port_base + PhyCtrl);
1253 spin_unlock_bh(&priv->lock);
1258 static void sc92031_ethtool_get_drvinfo(struct net_device *dev,
1259 struct ethtool_drvinfo *drvinfo)
1261 struct sc92031_priv *priv = netdev_priv(dev);
1262 struct pci_dev *pdev = priv->pdev;
1264 strcpy(drvinfo->driver, SC92031_NAME);
1265 strcpy(drvinfo->bus_info, pci_name(pdev));
1268 static void sc92031_ethtool_get_wol(struct net_device *dev,
1269 struct ethtool_wolinfo *wolinfo)
1271 struct sc92031_priv *priv = netdev_priv(dev);
1272 void __iomem *port_base = priv->port_base;
1275 spin_lock_bh(&priv->lock);
1276 pm_config = ioread32(port_base + PMConfig);
1277 spin_unlock_bh(&priv->lock);
1280 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1281 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1282 wolinfo->wolopts = 0;
1284 if (pm_config & PM_LinkUp)
1285 wolinfo->wolopts |= WAKE_PHY;
1287 if (pm_config & PM_Magic)
1288 wolinfo->wolopts |= WAKE_MAGIC;
1290 if (pm_config & PM_WakeUp)
1292 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1295 static int sc92031_ethtool_set_wol(struct net_device *dev,
1296 struct ethtool_wolinfo *wolinfo)
1298 struct sc92031_priv *priv = netdev_priv(dev);
1299 void __iomem *port_base = priv->port_base;
1302 spin_lock_bh(&priv->lock);
1304 pm_config = ioread32(port_base + PMConfig)
1305 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1307 if (wolinfo->wolopts & WAKE_PHY)
1308 pm_config |= PM_LinkUp;
1310 if (wolinfo->wolopts & WAKE_MAGIC)
1311 pm_config |= PM_Magic;
1314 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1315 pm_config |= PM_WakeUp;
1317 priv->pm_config = pm_config;
1318 iowrite32(pm_config, port_base + PMConfig);
1321 spin_unlock_bh(&priv->lock);
1326 static int sc92031_ethtool_nway_reset(struct net_device *dev)
1329 struct sc92031_priv *priv = netdev_priv(dev);
1330 void __iomem *port_base = priv->port_base;
1333 spin_lock_bh(&priv->lock);
1335 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1336 if (!(bmcr & BMCR_ANENABLE)) {
1341 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1344 _sc92031_mii_scan(port_base);
1347 spin_unlock_bh(&priv->lock);
1352 static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1357 static void sc92031_ethtool_get_strings(struct net_device *dev,
1358 u32 stringset, u8 *data)
1360 if (stringset == ETH_SS_STATS)
1361 memcpy(data, sc92031_ethtool_stats_strings,
1362 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1365 static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1369 return SILAN_STATS_NUM;
1375 static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1376 struct ethtool_stats *stats, u64 *data)
1378 struct sc92031_priv *priv = netdev_priv(dev);
1380 spin_lock_bh(&priv->lock);
1381 data[0] = priv->tx_timeouts;
1382 data[1] = priv->rx_loss;
1383 spin_unlock_bh(&priv->lock);
1386 static const struct ethtool_ops sc92031_ethtool_ops = {
1387 .get_settings = sc92031_ethtool_get_settings,
1388 .set_settings = sc92031_ethtool_set_settings,
1389 .get_drvinfo = sc92031_ethtool_get_drvinfo,
1390 .get_wol = sc92031_ethtool_get_wol,
1391 .set_wol = sc92031_ethtool_set_wol,
1392 .nway_reset = sc92031_ethtool_nway_reset,
1393 .get_link = ethtool_op_get_link,
1394 .get_strings = sc92031_ethtool_get_strings,
1395 .get_sset_count = sc92031_ethtool_get_sset_count,
1396 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
1400 static const struct net_device_ops sc92031_netdev_ops = {
1401 .ndo_get_stats = sc92031_get_stats,
1402 .ndo_start_xmit = sc92031_start_xmit,
1403 .ndo_open = sc92031_open,
1404 .ndo_stop = sc92031_stop,
1405 .ndo_set_multicast_list = sc92031_set_multicast_list,
1406 .ndo_change_mtu = eth_change_mtu,
1407 .ndo_validate_addr = eth_validate_addr,
1408 .ndo_set_mac_address = eth_mac_addr,
1409 .ndo_tx_timeout = sc92031_tx_timeout,
1410 #ifdef CONFIG_NET_POLL_CONTROLLER
1411 .ndo_poll_controller = sc92031_poll_controller,
1415 static int __devinit sc92031_probe(struct pci_dev *pdev,
1416 const struct pci_device_id *id)
1419 void __iomem* port_base;
1420 struct net_device *dev;
1421 struct sc92031_priv *priv;
1423 unsigned long base_addr;
1425 err = pci_enable_device(pdev);
1426 if (unlikely(err < 0))
1427 goto out_enable_device;
1429 pci_set_master(pdev);
1431 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1432 if (unlikely(err < 0))
1433 goto out_set_dma_mask;
1435 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1436 if (unlikely(err < 0))
1437 goto out_set_dma_mask;
1439 err = pci_request_regions(pdev, SC92031_NAME);
1440 if (unlikely(err < 0))
1441 goto out_request_regions;
1443 port_base = pci_iomap(pdev, SC92031_USE_BAR, 0);
1444 if (unlikely(!port_base)) {
1449 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1450 if (unlikely(!dev)) {
1452 goto out_alloc_etherdev;
1455 pci_set_drvdata(pdev, dev);
1456 SET_NETDEV_DEV(dev, &pdev->dev);
1458 #if SC92031_USE_BAR == 0
1459 dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR);
1460 dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR);
1461 #elif SC92031_USE_BAR == 1
1462 dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR);
1464 dev->irq = pdev->irq;
1466 /* faked with skb_copy_and_csum_dev */
1467 dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1469 dev->netdev_ops = &sc92031_netdev_ops;
1470 dev->watchdog_timeo = TX_TIMEOUT;
1471 dev->ethtool_ops = &sc92031_ethtool_ops;
1473 priv = netdev_priv(dev);
1474 spin_lock_init(&priv->lock);
1475 priv->port_base = port_base;
1477 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1478 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1479 * sc92031_open will work correctly */
1480 tasklet_disable_nosync(&priv->tasklet);
1483 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1485 mac0 = ioread32(port_base + MAC0);
1486 mac1 = ioread32(port_base + MAC0 + 4);
1487 dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24;
1488 dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16;
1489 dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8;
1490 dev->dev_addr[3] = dev->perm_addr[3] = mac0;
1491 dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8;
1492 dev->dev_addr[5] = dev->perm_addr[5] = mac1;
1494 err = register_netdev(dev);
1496 goto out_register_netdev;
1498 #if SC92031_USE_BAR == 0
1499 base_addr = dev->mem_start;
1500 #elif SC92031_USE_BAR == 1
1501 base_addr = dev->base_addr;
1503 printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1504 base_addr, dev->dev_addr, dev->irq);
1508 out_register_netdev:
1511 pci_iounmap(pdev, port_base);
1513 pci_release_regions(pdev);
1514 out_request_regions:
1516 pci_disable_device(pdev);
1521 static void __devexit sc92031_remove(struct pci_dev *pdev)
1523 struct net_device *dev = pci_get_drvdata(pdev);
1524 struct sc92031_priv *priv = netdev_priv(dev);
1525 void __iomem* port_base = priv->port_base;
1527 unregister_netdev(dev);
1529 pci_iounmap(pdev, port_base);
1530 pci_release_regions(pdev);
1531 pci_disable_device(pdev);
1534 static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1536 struct net_device *dev = pci_get_drvdata(pdev);
1537 struct sc92031_priv *priv = netdev_priv(dev);
1539 pci_save_state(pdev);
1541 if (!netif_running(dev))
1544 netif_device_detach(dev);
1546 /* Disable interrupts, stop Tx and Rx. */
1547 sc92031_disable_interrupts(dev);
1549 spin_lock_bh(&priv->lock);
1551 _sc92031_disable_tx_rx(dev);
1552 _sc92031_tx_clear(dev);
1555 spin_unlock_bh(&priv->lock);
1558 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1563 static int sc92031_resume(struct pci_dev *pdev)
1565 struct net_device *dev = pci_get_drvdata(pdev);
1566 struct sc92031_priv *priv = netdev_priv(dev);
1568 pci_restore_state(pdev);
1569 pci_set_power_state(pdev, PCI_D0);
1571 if (!netif_running(dev))
1574 /* Interrupts already disabled by sc92031_suspend */
1575 spin_lock_bh(&priv->lock);
1577 _sc92031_reset(dev);
1580 spin_unlock_bh(&priv->lock);
1581 sc92031_enable_interrupts(dev);
1583 netif_device_attach(dev);
1585 if (netif_carrier_ok(dev))
1586 netif_wake_queue(dev);
1588 netif_tx_disable(dev);
1594 static struct pci_device_id sc92031_pci_device_id_table[] __devinitdata = {
1595 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_SC92031) },
1596 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_8139D) },
1599 MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1601 static struct pci_driver sc92031_pci_driver = {
1602 .name = SC92031_NAME,
1603 .id_table = sc92031_pci_device_id_table,
1604 .probe = sc92031_probe,
1605 .remove = __devexit_p(sc92031_remove),
1606 .suspend = sc92031_suspend,
1607 .resume = sc92031_resume,
1610 static int __init sc92031_init(void)
1612 return pci_register_driver(&sc92031_pci_driver);
1615 static void __exit sc92031_exit(void)
1617 pci_unregister_driver(&sc92031_pci_driver);
1620 module_init(sc92031_init);
1621 module_exit(sc92031_exit);
1623 MODULE_LICENSE("GPL");
1624 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1625 MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");