1 /* Silan SC92031 PCI Fast Ethernet Adapter driver
3 * Based on vendor drivers:
4 * Silan Fast Ethernet Netcard Driver:
5 * MODULE_AUTHOR ("gaoyonghong");
6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
7 * MODULE_LICENSE("GPL");
8 * 8139D Fast Ethernet driver:
9 * (C) 2002 by gaoyonghong
10 * MODULE_AUTHOR ("gaoyonghong");
11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
12 * MODULE_LICENSE("GPL");
13 * Both are almost identical and seem to be based on pci-skeleton.c
15 * Rewritten for 2.6 by Cesar Eduardo Barros
18 /* Note about set_mac_address: I don't know how to change the hardware
19 * matching, so you need to enable IFF_PROMISC when using it.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/pci.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/crc32.h>
34 #define PCI_VENDOR_ID_SILAN 0x1904
35 #define PCI_DEVICE_ID_SILAN_SC92031 0x2031
36 #define PCI_DEVICE_ID_SILAN_8139D 0x8139
38 #define SC92031_NAME "sc92031"
39 #define SC92031_DESCRIPTION "Silan SC92031 PCI Fast Ethernet Adapter driver"
41 /* BAR 0 is MMIO, BAR 1 is PIO */
42 #ifndef SC92031_USE_BAR
43 #define SC92031_USE_BAR 0
46 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
47 static int multicast_filter_limit = 64;
48 module_param(multicast_filter_limit, int, 0);
49 MODULE_PARM_DESC(multicast_filter_limit,
50 "Maximum number of filtered multicast addresses");
53 module_param(media, int, 0);
54 MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
55 " 0x01 = 10M half, 0x02 = 10M full,"
56 " 0x04 = 100M half, 0x08 = 100M full)");
58 /* Size of the in-memory receive ring. */
59 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
60 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
62 /* Number of Tx descriptor registers. */
65 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
66 #define MAX_ETH_FRAME_SIZE 1536
68 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
69 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
70 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
72 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
73 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
75 /* Time in jiffies before concluding the transmitter is hung. */
76 #define TX_TIMEOUT (4*HZ)
78 #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
81 #define AUTOSELECT 0x00
84 #define M100_HALF 0x04
85 #define M100_FULL 0x08
87 /* Symbolic offsets to registers. */
88 enum silan_registers {
89 Config0 = 0x00, // Config0
90 Config1 = 0x04, // Config1
91 RxBufWPtr = 0x08, // Rx buffer writer poiter
92 IntrStatus = 0x0C, // Interrupt status
93 IntrMask = 0x10, // Interrupt mask
94 RxbufAddr = 0x14, // Rx buffer start address
95 RxBufRPtr = 0x18, // Rx buffer read pointer
96 Txstatusall = 0x1C, // Transmit status of all descriptors
97 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
98 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
99 RxConfig = 0x40, // Rx configuration
100 MAC0 = 0x44, // Ethernet hardware address.
101 MAR0 = 0x4C, // Multicast filter.
102 RxStatus0 = 0x54, // Rx status
103 TxConfig = 0x5C, // Tx configuration
104 PhyCtrl = 0x60, // physical control
105 FlowCtrlConfig = 0x64, // flow control
106 Miicmd0 = 0x68, // Mii command0 register
107 Miicmd1 = 0x6C, // Mii command1 register
108 Miistatus = 0x70, // Mii status register
109 Timercnt = 0x74, // Timer counter register
110 TimerIntr = 0x78, // Timer interrupt register
111 PMConfig = 0x7C, // Power Manager configuration
112 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
113 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
114 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
120 #define MII_BMCR 0 // Basic mode control register
121 #define MII_BMSR 1 // Basic mode status register
123 #define MII_OutputStatus 24
125 #define BMCR_FULLDPLX 0x0100 // Full duplex
126 #define BMCR_ANRESTART 0x0200 // Auto negotiation restart
127 #define BMCR_ANENABLE 0x1000 // Enable auto negotiation
128 #define BMCR_SPEED100 0x2000 // Select 100Mbps
129 #define BMSR_LSTATUS 0x0004 // Link status
130 #define PHY_16_JAB_ENB 0x1000
131 #define PHY_16_PORT_ENB 0x1
133 enum IntrStatusBits {
134 LinkFail = 0x80000000,
136 TimeOut = 0x20000000,
140 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
144 TxCarrierLost = 0x20000000,
145 TxAborted = 0x10000000,
146 TxOutOfWindow = 0x08000000,
148 EarlyTxThresShift = 16,
155 RxStatesOK = 0x80000,
156 RxBadAlign = 0x40000,
157 RxHugeFrame = 0x20000,
158 RxSmallFrame = 0x10000,
161 Rx_Broadcast = 0x2000,
162 Rx_Multicast = 0x1000,
163 RxAddrMatch = 0x0800,
168 RxFullDx = 0x80000000,
170 RxSmall = 0x20000000,
173 RxAllphys = 0x04000000,
174 RxMulticast = 0x02000000,
175 RxBroadcast = 0x01000000,
176 RxLoopBack = (1 << 23) | (1 << 22),
177 LowThresholdShift = 12,
178 HighThresholdShift = 2,
182 TxFullDx = 0x80000000,
184 TxEnbPad = 0x20000000,
185 TxEnbHuge = 0x10000000,
186 TxEnbFCS = 0x08000000,
187 TxNoBackOff = 0x04000000,
188 TxEnbPrem = 0x02000000,
189 TxCareLostCrs = 0x1000000,
190 TxExdCollNum = 0xf00000,
191 TxDataRate = 0x80000,
194 enum PhyCtrlconfigbits {
195 PhyCtrlAne = 0x80000000,
196 PhyCtrlSpd100 = 0x40000000,
197 PhyCtrlSpd10 = 0x20000000,
198 PhyCtrlPhyBaseAddr = 0x1f000000,
199 PhyCtrlDux = 0x800000,
200 PhyCtrlReset = 0x400000,
203 enum FlowCtrlConfigBits {
204 FlowCtrlFullDX = 0x80000000,
205 FlowCtrlEnb = 0x40000000,
209 Cfg0_Reset = 0x80000000,
210 Cfg0_Anaoff = 0x40000000,
211 Cfg0_LDPS = 0x20000000,
215 Cfg1_EarlyRx = 1 << 31,
216 Cfg1_EarlyTx = 1 << 30,
227 Mii_Divider = 0x20000000,
228 Mii_WRITE = 0x400000,
232 Mii_Drvmod = 0x40000,
240 Mii_StatusBusy = 0x80000000,
247 PM_LANWake = 1 << 28,
248 PM_LWPTN = (1 << 27 | 1<< 26),
254 * priv->lock protects most of the fields of priv and most of the
255 * hardware registers. It does not have to protect against softirqs
256 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
257 * it also does not need to be used in ->open and ->stop while the
258 * device interrupts are off.
259 * Not having to protect against softirqs is very useful due to heavy
260 * use of mdelay() at _sc92031_reset.
261 * Functions prefixed with _sc92031_ must be called with the lock held;
262 * functions prefixed with sc92031_ must be called without the lock held.
263 * Use mmiowb() before unlocking if the hardware was written to.
266 /* Locking rules for the interrupt:
267 * - the interrupt and the tasklet never run at the same time
268 * - neither run between sc92031_disable_interrupts and
269 * sc92031_enable_interrupt
272 struct sc92031_priv {
275 void __iomem *port_base;
276 /* pci device structure */
277 struct pci_dev *pdev;
279 struct tasklet_struct tasklet;
281 /* CPU address of rx ring */
283 /* PCI address of rx ring */
284 dma_addr_t rx_ring_dma_addr;
285 /* PCI address of rx ring read pointer */
286 dma_addr_t rx_ring_tail;
288 /* tx ring write index */
290 /* tx ring read index */
292 /* CPU address of tx bounce buffer */
294 /* PCI address of tx bounce buffer */
295 dma_addr_t tx_bufs_dma_addr;
297 /* copies of some hardware registers */
304 /* copy of some flags from dev->flags */
305 unsigned int mc_flags;
307 /* for ETHTOOL_GSTATS */
311 /* for dev->get_stats */
315 /* I don't know which registers can be safely read; however, I can guess
316 * MAC0 is one of them. */
317 static inline void _sc92031_dummy_read(void __iomem *port_base)
319 ioread32(port_base + MAC0);
322 static u32 _sc92031_mii_wait(void __iomem *port_base)
328 mii_status = ioread32(port_base + Miistatus);
329 } while (mii_status & Mii_StatusBusy);
334 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
336 iowrite32(Mii_Divider, port_base + Miicmd0);
338 _sc92031_mii_wait(port_base);
340 iowrite32(cmd1, port_base + Miicmd1);
341 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
343 return _sc92031_mii_wait(port_base);
346 static void _sc92031_mii_scan(void __iomem *port_base)
348 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
351 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
353 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
356 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
358 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
361 static void sc92031_disable_interrupts(struct net_device *dev)
363 struct sc92031_priv *priv = netdev_priv(dev);
364 void __iomem *port_base = priv->port_base;
366 /* tell the tasklet/interrupt not to enable interrupts */
367 atomic_set(&priv->intr_mask, 0);
370 /* stop interrupts */
371 iowrite32(0, port_base + IntrMask);
372 _sc92031_dummy_read(port_base);
375 /* wait for any concurrent interrupt/tasklet to finish */
376 synchronize_irq(dev->irq);
377 tasklet_disable(&priv->tasklet);
380 static void sc92031_enable_interrupts(struct net_device *dev)
382 struct sc92031_priv *priv = netdev_priv(dev);
383 void __iomem *port_base = priv->port_base;
385 tasklet_enable(&priv->tasklet);
387 atomic_set(&priv->intr_mask, IntrBits);
390 iowrite32(IntrBits, port_base + IntrMask);
394 static void _sc92031_disable_tx_rx(struct net_device *dev)
396 struct sc92031_priv *priv = netdev_priv(dev);
397 void __iomem *port_base = priv->port_base;
399 priv->rx_config &= ~RxEnb;
400 priv->tx_config &= ~TxEnb;
401 iowrite32(priv->rx_config, port_base + RxConfig);
402 iowrite32(priv->tx_config, port_base + TxConfig);
405 static void _sc92031_enable_tx_rx(struct net_device *dev)
407 struct sc92031_priv *priv = netdev_priv(dev);
408 void __iomem *port_base = priv->port_base;
410 priv->rx_config |= RxEnb;
411 priv->tx_config |= TxEnb;
412 iowrite32(priv->rx_config, port_base + RxConfig);
413 iowrite32(priv->tx_config, port_base + TxConfig);
416 static void _sc92031_tx_clear(struct net_device *dev)
418 struct sc92031_priv *priv = netdev_priv(dev);
420 while (priv->tx_head - priv->tx_tail > 0) {
422 dev->stats.tx_dropped++;
424 priv->tx_head = priv->tx_tail = 0;
427 static void _sc92031_set_mar(struct net_device *dev)
429 struct sc92031_priv *priv = netdev_priv(dev);
430 void __iomem *port_base = priv->port_base;
431 u32 mar0 = 0, mar1 = 0;
433 if ((dev->flags & IFF_PROMISC)
434 || dev->mc_count > multicast_filter_limit
435 || (dev->flags & IFF_ALLMULTI))
436 mar0 = mar1 = 0xffffffff;
437 else if (dev->flags & IFF_MULTICAST) {
438 struct dev_mc_list *mc_list;
440 for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) {
444 crc = ~ether_crc(ETH_ALEN, mc_list->dmi_addr);
447 if (crc & 0x01) bit |= 0x02;
448 if (crc & 0x02) bit |= 0x01;
449 if (crc & 0x10) bit |= 0x20;
450 if (crc & 0x20) bit |= 0x10;
451 if (crc & 0x40) bit |= 0x08;
452 if (crc & 0x80) bit |= 0x04;
455 mar0 |= 0x1 << (bit - 32);
461 iowrite32(mar0, port_base + MAR0);
462 iowrite32(mar1, port_base + MAR0 + 4);
465 static void _sc92031_set_rx_config(struct net_device *dev)
467 struct sc92031_priv *priv = netdev_priv(dev);
468 void __iomem *port_base = priv->port_base;
469 unsigned int old_mc_flags;
470 u32 rx_config_bits = 0;
472 old_mc_flags = priv->mc_flags;
474 if (dev->flags & IFF_PROMISC)
475 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
476 | RxMulticast | RxAllphys;
478 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
479 rx_config_bits |= RxMulticast;
481 if (dev->flags & IFF_BROADCAST)
482 rx_config_bits |= RxBroadcast;
484 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
485 | RxMulticast | RxAllphys);
486 priv->rx_config |= rx_config_bits;
488 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
489 | IFF_MULTICAST | IFF_BROADCAST);
491 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
492 iowrite32(priv->rx_config, port_base + RxConfig);
495 static bool _sc92031_check_media(struct net_device *dev)
497 struct sc92031_priv *priv = netdev_priv(dev);
498 void __iomem *port_base = priv->port_base;
501 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
503 if (bmsr & BMSR_LSTATUS) {
504 bool speed_100, duplex_full;
505 u32 flow_ctrl_config = 0;
506 u16 output_status = _sc92031_mii_read(port_base,
508 _sc92031_mii_scan(port_base);
510 speed_100 = output_status & 0x2;
511 duplex_full = output_status & 0x4;
513 /* Initial Tx/Rx configuration */
514 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
515 priv->tx_config = 0x48800000;
517 /* NOTE: vendor driver had dead code here to enable tx padding */
520 priv->tx_config |= 0x80000;
523 _sc92031_set_rx_config(dev);
526 priv->rx_config |= RxFullDx;
527 priv->tx_config |= TxFullDx;
528 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
530 priv->rx_config &= ~RxFullDx;
531 priv->tx_config &= ~TxFullDx;
534 _sc92031_set_mar(dev);
535 _sc92031_set_rx_config(dev);
536 _sc92031_enable_tx_rx(dev);
537 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
539 netif_carrier_on(dev);
541 if (printk_ratelimit())
542 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
544 speed_100 ? "100" : "10",
545 duplex_full ? "full" : "half");
548 _sc92031_mii_scan(port_base);
550 netif_carrier_off(dev);
552 _sc92031_disable_tx_rx(dev);
554 if (printk_ratelimit())
555 printk(KERN_INFO "%s: link down\n", dev->name);
560 static void _sc92031_phy_reset(struct net_device *dev)
562 struct sc92031_priv *priv = netdev_priv(dev);
563 void __iomem *port_base = priv->port_base;
566 phy_ctrl = ioread32(port_base + PhyCtrl);
567 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
568 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
573 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
576 phy_ctrl |= PhyCtrlSpd10;
579 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
582 phy_ctrl |= PhyCtrlSpd100;
585 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
589 iowrite32(phy_ctrl, port_base + PhyCtrl);
592 phy_ctrl &= ~PhyCtrlReset;
593 iowrite32(phy_ctrl, port_base + PhyCtrl);
596 _sc92031_mii_write(port_base, MII_JAB,
597 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
598 _sc92031_mii_scan(port_base);
600 netif_carrier_off(dev);
601 netif_stop_queue(dev);
604 static void _sc92031_reset(struct net_device *dev)
606 struct sc92031_priv *priv = netdev_priv(dev);
607 void __iomem *port_base = priv->port_base;
610 iowrite32(0, port_base + PMConfig);
612 /* soft reset the chip */
613 iowrite32(Cfg0_Reset, port_base + Config0);
616 iowrite32(0, port_base + Config0);
619 /* disable interrupts */
620 iowrite32(0, port_base + IntrMask);
622 /* clear multicast address */
623 iowrite32(0, port_base + MAR0);
624 iowrite32(0, port_base + MAR0 + 4);
627 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
628 priv->rx_ring_tail = priv->rx_ring_dma_addr;
631 _sc92031_tx_clear(dev);
633 /* clear old register values */
634 priv->intr_status = 0;
635 atomic_set(&priv->intr_mask, 0);
640 /* configure rx buffer size */
641 /* NOTE: vendor driver had dead code here to enable early tx/rx */
642 iowrite32(Cfg1_Rcv64K, port_base + Config1);
644 _sc92031_phy_reset(dev);
645 _sc92031_check_media(dev);
647 /* calculate rx fifo overflow */
651 iowrite32(priv->pm_config, port_base + PMConfig);
653 /* clear intr register */
654 ioread32(port_base + IntrStatus);
657 static void _sc92031_tx_tasklet(struct net_device *dev)
659 struct sc92031_priv *priv = netdev_priv(dev);
660 void __iomem *port_base = priv->port_base;
662 unsigned old_tx_tail;
666 old_tx_tail = priv->tx_tail;
667 while (priv->tx_head - priv->tx_tail > 0) {
668 entry = priv->tx_tail % NUM_TX_DESC;
669 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
671 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
676 if (tx_status & TxStatOK) {
677 dev->stats.tx_bytes += tx_status & 0x1fff;
678 dev->stats.tx_packets++;
679 /* Note: TxCarrierLost is always asserted at 100mbps. */
680 dev->stats.collisions += (tx_status >> 22) & 0xf;
683 if (tx_status & (TxOutOfWindow | TxAborted)) {
684 dev->stats.tx_errors++;
686 if (tx_status & TxAborted)
687 dev->stats.tx_aborted_errors++;
689 if (tx_status & TxCarrierLost)
690 dev->stats.tx_carrier_errors++;
692 if (tx_status & TxOutOfWindow)
693 dev->stats.tx_window_errors++;
696 if (tx_status & TxUnderrun)
697 dev->stats.tx_fifo_errors++;
700 if (priv->tx_tail != old_tx_tail)
701 if (netif_queue_stopped(dev))
702 netif_wake_queue(dev);
705 static void _sc92031_rx_tasklet_error(struct net_device *dev,
706 u32 rx_status, unsigned rx_size)
708 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
709 dev->stats.rx_errors++;
710 dev->stats.rx_length_errors++;
713 if (!(rx_status & RxStatesOK)) {
714 dev->stats.rx_errors++;
716 if (rx_status & (RxHugeFrame | RxSmallFrame))
717 dev->stats.rx_length_errors++;
719 if (rx_status & RxBadAlign)
720 dev->stats.rx_frame_errors++;
722 if (!(rx_status & RxCRCOK))
723 dev->stats.rx_crc_errors++;
725 struct sc92031_priv *priv = netdev_priv(dev);
730 static void _sc92031_rx_tasklet(struct net_device *dev)
732 struct sc92031_priv *priv = netdev_priv(dev);
733 void __iomem *port_base = priv->port_base;
735 dma_addr_t rx_ring_head;
737 unsigned rx_ring_offset;
738 void *rx_ring = priv->rx_ring;
740 rx_ring_head = ioread32(port_base + RxBufWPtr);
743 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
744 * we need to change it to 32 bits physical address
746 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
747 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
748 if (rx_ring_head < priv->rx_ring_dma_addr)
749 rx_ring_head += RX_BUF_LEN;
751 if (rx_ring_head >= priv->rx_ring_tail)
752 rx_len = rx_ring_head - priv->rx_ring_tail;
754 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
759 if (unlikely(rx_len > RX_BUF_LEN)) {
760 if (printk_ratelimit())
761 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
766 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
770 unsigned rx_size, rx_size_align, pkt_size;
773 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
776 rx_size = rx_status >> 20;
777 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
778 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
780 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
782 if (unlikely(rx_status == 0
783 || rx_size > (MAX_ETH_FRAME_SIZE + 4)
785 || !(rx_status & RxStatesOK))) {
786 _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
790 if (unlikely(rx_size_align + 4 > rx_len)) {
791 if (printk_ratelimit())
792 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
796 rx_len -= rx_size_align + 4;
798 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
799 if (unlikely(!skb)) {
800 if (printk_ratelimit())
801 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
802 dev->name, pkt_size);
806 skb_reserve(skb, NET_IP_ALIGN);
808 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
809 memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
810 rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
811 memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
812 rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
814 memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
817 skb->protocol = eth_type_trans(skb, dev);
820 dev->stats.rx_bytes += pkt_size;
821 dev->stats.rx_packets++;
823 if (rx_status & Rx_Multicast)
824 dev->stats.multicast++;
827 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
831 priv->rx_ring_tail = rx_ring_head;
832 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
835 static void _sc92031_link_tasklet(struct net_device *dev)
837 if (_sc92031_check_media(dev))
838 netif_wake_queue(dev);
840 netif_stop_queue(dev);
841 dev->stats.tx_carrier_errors++;
845 static void sc92031_tasklet(unsigned long data)
847 struct net_device *dev = (struct net_device *)data;
848 struct sc92031_priv *priv = netdev_priv(dev);
849 void __iomem *port_base = priv->port_base;
850 u32 intr_status, intr_mask;
852 intr_status = priv->intr_status;
854 spin_lock(&priv->lock);
856 if (unlikely(!netif_running(dev)))
859 if (intr_status & TxOK)
860 _sc92031_tx_tasklet(dev);
862 if (intr_status & RxOK)
863 _sc92031_rx_tasklet(dev);
865 if (intr_status & RxOverflow)
866 dev->stats.rx_errors++;
868 if (intr_status & TimeOut) {
869 dev->stats.rx_errors++;
870 dev->stats.rx_length_errors++;
873 if (intr_status & (LinkFail | LinkOK))
874 _sc92031_link_tasklet(dev);
877 intr_mask = atomic_read(&priv->intr_mask);
880 iowrite32(intr_mask, port_base + IntrMask);
883 spin_unlock(&priv->lock);
886 static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
888 struct net_device *dev = dev_id;
889 struct sc92031_priv *priv = netdev_priv(dev);
890 void __iomem *port_base = priv->port_base;
891 u32 intr_status, intr_mask;
893 /* mask interrupts before clearing IntrStatus */
894 iowrite32(0, port_base + IntrMask);
895 _sc92031_dummy_read(port_base);
897 intr_status = ioread32(port_base + IntrStatus);
898 if (unlikely(intr_status == 0xffffffff))
899 return IRQ_NONE; // hardware has gone missing
901 intr_status &= IntrBits;
905 priv->intr_status = intr_status;
906 tasklet_schedule(&priv->tasklet);
911 intr_mask = atomic_read(&priv->intr_mask);
914 iowrite32(intr_mask, port_base + IntrMask);
920 static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
922 struct sc92031_priv *priv = netdev_priv(dev);
923 void __iomem *port_base = priv->port_base;
925 // FIXME I do not understand what is this trying to do.
926 if (netif_running(dev)) {
929 spin_lock_bh(&priv->lock);
931 /* Update the error count. */
932 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
934 if (temp == 0xffff) {
935 priv->rx_value += temp;
936 dev->stats.rx_fifo_errors = priv->rx_value;
938 dev->stats.rx_fifo_errors = temp + priv->rx_value;
940 spin_unlock_bh(&priv->lock);
946 static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
948 struct sc92031_priv *priv = netdev_priv(dev);
949 void __iomem *port_base = priv->port_base;
954 if (unlikely(skb->len > TX_BUF_SIZE)) {
955 dev->stats.tx_dropped++;
959 spin_lock(&priv->lock);
961 if (unlikely(!netif_carrier_ok(dev))) {
962 dev->stats.tx_dropped++;
966 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
968 entry = priv->tx_head++ % NUM_TX_DESC;
970 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
973 if (len < ETH_ZLEN) {
974 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
984 tx_status = 0x30000 | len;
986 tx_status = 0x50000 | len;
988 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
989 port_base + TxAddr0 + entry * 4);
990 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
993 dev->trans_start = jiffies;
995 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
996 netif_stop_queue(dev);
999 spin_unlock(&priv->lock);
1004 return NETDEV_TX_OK;
1007 static int sc92031_open(struct net_device *dev)
1010 struct sc92031_priv *priv = netdev_priv(dev);
1011 struct pci_dev *pdev = priv->pdev;
1013 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
1014 &priv->rx_ring_dma_addr);
1015 if (unlikely(!priv->rx_ring)) {
1017 goto out_alloc_rx_ring;
1020 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1021 &priv->tx_bufs_dma_addr);
1022 if (unlikely(!priv->tx_bufs)) {
1024 goto out_alloc_tx_bufs;
1026 priv->tx_head = priv->tx_tail = 0;
1028 err = request_irq(pdev->irq, sc92031_interrupt,
1029 IRQF_SHARED, dev->name, dev);
1030 if (unlikely(err < 0))
1031 goto out_request_irq;
1033 priv->pm_config = 0;
1035 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1036 spin_lock_bh(&priv->lock);
1038 _sc92031_reset(dev);
1041 spin_unlock_bh(&priv->lock);
1042 sc92031_enable_interrupts(dev);
1044 if (netif_carrier_ok(dev))
1045 netif_start_queue(dev);
1047 netif_tx_disable(dev);
1052 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1053 priv->tx_bufs_dma_addr);
1055 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1056 priv->rx_ring_dma_addr);
1061 static int sc92031_stop(struct net_device *dev)
1063 struct sc92031_priv *priv = netdev_priv(dev);
1064 struct pci_dev *pdev = priv->pdev;
1066 netif_tx_disable(dev);
1068 /* Disable interrupts, stop Tx and Rx. */
1069 sc92031_disable_interrupts(dev);
1071 spin_lock_bh(&priv->lock);
1073 _sc92031_disable_tx_rx(dev);
1074 _sc92031_tx_clear(dev);
1077 spin_unlock_bh(&priv->lock);
1079 free_irq(pdev->irq, dev);
1080 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1081 priv->tx_bufs_dma_addr);
1082 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1083 priv->rx_ring_dma_addr);
1088 static void sc92031_set_multicast_list(struct net_device *dev)
1090 struct sc92031_priv *priv = netdev_priv(dev);
1092 spin_lock_bh(&priv->lock);
1094 _sc92031_set_mar(dev);
1095 _sc92031_set_rx_config(dev);
1098 spin_unlock_bh(&priv->lock);
1101 static void sc92031_tx_timeout(struct net_device *dev)
1103 struct sc92031_priv *priv = netdev_priv(dev);
1105 /* Disable interrupts by clearing the interrupt mask.*/
1106 sc92031_disable_interrupts(dev);
1108 spin_lock(&priv->lock);
1110 priv->tx_timeouts++;
1112 _sc92031_reset(dev);
1115 spin_unlock(&priv->lock);
1117 /* enable interrupts */
1118 sc92031_enable_interrupts(dev);
1120 if (netif_carrier_ok(dev))
1121 netif_wake_queue(dev);
1124 #ifdef CONFIG_NET_POLL_CONTROLLER
1125 static void sc92031_poll_controller(struct net_device *dev)
1127 disable_irq(dev->irq);
1128 if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE)
1129 sc92031_tasklet((unsigned long)dev);
1130 enable_irq(dev->irq);
1134 static int sc92031_ethtool_get_settings(struct net_device *dev,
1135 struct ethtool_cmd *cmd)
1137 struct sc92031_priv *priv = netdev_priv(dev);
1138 void __iomem *port_base = priv->port_base;
1143 spin_lock_bh(&priv->lock);
1145 phy_address = ioread32(port_base + Miicmd1) >> 27;
1146 phy_ctrl = ioread32(port_base + PhyCtrl);
1148 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1149 _sc92031_mii_scan(port_base);
1152 spin_unlock_bh(&priv->lock);
1154 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1155 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1156 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1158 cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
1160 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1161 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1162 cmd->advertising |= ADVERTISED_Autoneg;
1164 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1165 cmd->advertising |= ADVERTISED_10baseT_Half;
1167 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1168 == (PhyCtrlSpd10 | PhyCtrlDux))
1169 cmd->advertising |= ADVERTISED_10baseT_Full;
1171 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1172 cmd->advertising |= ADVERTISED_100baseT_Half;
1174 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1175 == (PhyCtrlSpd100 | PhyCtrlDux))
1176 cmd->advertising |= ADVERTISED_100baseT_Full;
1178 if (phy_ctrl & PhyCtrlAne)
1179 cmd->advertising |= ADVERTISED_Autoneg;
1181 cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1182 cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1183 cmd->port = PORT_MII;
1184 cmd->phy_address = phy_address;
1185 cmd->transceiver = XCVR_INTERNAL;
1186 cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1191 static int sc92031_ethtool_set_settings(struct net_device *dev,
1192 struct ethtool_cmd *cmd)
1194 struct sc92031_priv *priv = netdev_priv(dev);
1195 void __iomem *port_base = priv->port_base;
1199 if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100))
1201 if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
1203 if (!(cmd->port == PORT_MII))
1205 if (!(cmd->phy_address == 0x1f))
1207 if (!(cmd->transceiver == XCVR_INTERNAL))
1209 if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
1212 if (cmd->autoneg == AUTONEG_ENABLE) {
1213 if (!(cmd->advertising & (ADVERTISED_Autoneg
1214 | ADVERTISED_100baseT_Full
1215 | ADVERTISED_100baseT_Half
1216 | ADVERTISED_10baseT_Full
1217 | ADVERTISED_10baseT_Half)))
1220 phy_ctrl = PhyCtrlAne;
1222 // FIXME: I'm not sure what the original code was trying to do
1223 if (cmd->advertising & ADVERTISED_Autoneg)
1224 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1225 if (cmd->advertising & ADVERTISED_100baseT_Full)
1226 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1227 if (cmd->advertising & ADVERTISED_100baseT_Half)
1228 phy_ctrl |= PhyCtrlSpd100;
1229 if (cmd->advertising & ADVERTISED_10baseT_Full)
1230 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1231 if (cmd->advertising & ADVERTISED_10baseT_Half)
1232 phy_ctrl |= PhyCtrlSpd10;
1234 // FIXME: Whole branch guessed
1237 if (cmd->speed == SPEED_10)
1238 phy_ctrl |= PhyCtrlSpd10;
1239 else /* cmd->speed == SPEED_100 */
1240 phy_ctrl |= PhyCtrlSpd100;
1242 if (cmd->duplex == DUPLEX_FULL)
1243 phy_ctrl |= PhyCtrlDux;
1246 spin_lock_bh(&priv->lock);
1248 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1249 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1250 | PhyCtrlSpd100 | PhyCtrlSpd10);
1251 if (phy_ctrl != old_phy_ctrl)
1252 iowrite32(phy_ctrl, port_base + PhyCtrl);
1254 spin_unlock_bh(&priv->lock);
1259 static void sc92031_ethtool_get_drvinfo(struct net_device *dev,
1260 struct ethtool_drvinfo *drvinfo)
1262 struct sc92031_priv *priv = netdev_priv(dev);
1263 struct pci_dev *pdev = priv->pdev;
1265 strcpy(drvinfo->driver, SC92031_NAME);
1266 strcpy(drvinfo->bus_info, pci_name(pdev));
1269 static void sc92031_ethtool_get_wol(struct net_device *dev,
1270 struct ethtool_wolinfo *wolinfo)
1272 struct sc92031_priv *priv = netdev_priv(dev);
1273 void __iomem *port_base = priv->port_base;
1276 spin_lock_bh(&priv->lock);
1277 pm_config = ioread32(port_base + PMConfig);
1278 spin_unlock_bh(&priv->lock);
1281 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1282 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1283 wolinfo->wolopts = 0;
1285 if (pm_config & PM_LinkUp)
1286 wolinfo->wolopts |= WAKE_PHY;
1288 if (pm_config & PM_Magic)
1289 wolinfo->wolopts |= WAKE_MAGIC;
1291 if (pm_config & PM_WakeUp)
1293 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1296 static int sc92031_ethtool_set_wol(struct net_device *dev,
1297 struct ethtool_wolinfo *wolinfo)
1299 struct sc92031_priv *priv = netdev_priv(dev);
1300 void __iomem *port_base = priv->port_base;
1303 spin_lock_bh(&priv->lock);
1305 pm_config = ioread32(port_base + PMConfig)
1306 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1308 if (wolinfo->wolopts & WAKE_PHY)
1309 pm_config |= PM_LinkUp;
1311 if (wolinfo->wolopts & WAKE_MAGIC)
1312 pm_config |= PM_Magic;
1315 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1316 pm_config |= PM_WakeUp;
1318 priv->pm_config = pm_config;
1319 iowrite32(pm_config, port_base + PMConfig);
1322 spin_unlock_bh(&priv->lock);
1327 static int sc92031_ethtool_nway_reset(struct net_device *dev)
1330 struct sc92031_priv *priv = netdev_priv(dev);
1331 void __iomem *port_base = priv->port_base;
1334 spin_lock_bh(&priv->lock);
1336 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1337 if (!(bmcr & BMCR_ANENABLE)) {
1342 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1345 _sc92031_mii_scan(port_base);
1348 spin_unlock_bh(&priv->lock);
1353 static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1358 static void sc92031_ethtool_get_strings(struct net_device *dev,
1359 u32 stringset, u8 *data)
1361 if (stringset == ETH_SS_STATS)
1362 memcpy(data, sc92031_ethtool_stats_strings,
1363 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1366 static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1370 return SILAN_STATS_NUM;
1376 static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1377 struct ethtool_stats *stats, u64 *data)
1379 struct sc92031_priv *priv = netdev_priv(dev);
1381 spin_lock_bh(&priv->lock);
1382 data[0] = priv->tx_timeouts;
1383 data[1] = priv->rx_loss;
1384 spin_unlock_bh(&priv->lock);
1387 static const struct ethtool_ops sc92031_ethtool_ops = {
1388 .get_settings = sc92031_ethtool_get_settings,
1389 .set_settings = sc92031_ethtool_set_settings,
1390 .get_drvinfo = sc92031_ethtool_get_drvinfo,
1391 .get_wol = sc92031_ethtool_get_wol,
1392 .set_wol = sc92031_ethtool_set_wol,
1393 .nway_reset = sc92031_ethtool_nway_reset,
1394 .get_link = ethtool_op_get_link,
1395 .get_strings = sc92031_ethtool_get_strings,
1396 .get_sset_count = sc92031_ethtool_get_sset_count,
1397 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
1401 static const struct net_device_ops sc92031_netdev_ops = {
1402 .ndo_get_stats = sc92031_get_stats,
1403 .ndo_start_xmit = sc92031_start_xmit,
1404 .ndo_open = sc92031_open,
1405 .ndo_stop = sc92031_stop,
1406 .ndo_set_multicast_list = sc92031_set_multicast_list,
1407 .ndo_change_mtu = eth_change_mtu,
1408 .ndo_validate_addr = eth_validate_addr,
1409 .ndo_set_mac_address = eth_mac_addr,
1410 .ndo_tx_timeout = sc92031_tx_timeout,
1411 #ifdef CONFIG_NET_POLL_CONTROLLER
1412 .ndo_poll_controller = sc92031_poll_controller,
1416 static int __devinit sc92031_probe(struct pci_dev *pdev,
1417 const struct pci_device_id *id)
1420 void __iomem* port_base;
1421 struct net_device *dev;
1422 struct sc92031_priv *priv;
1424 unsigned long base_addr;
1426 err = pci_enable_device(pdev);
1427 if (unlikely(err < 0))
1428 goto out_enable_device;
1430 pci_set_master(pdev);
1432 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1433 if (unlikely(err < 0))
1434 goto out_set_dma_mask;
1436 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1437 if (unlikely(err < 0))
1438 goto out_set_dma_mask;
1440 err = pci_request_regions(pdev, SC92031_NAME);
1441 if (unlikely(err < 0))
1442 goto out_request_regions;
1444 port_base = pci_iomap(pdev, SC92031_USE_BAR, 0);
1445 if (unlikely(!port_base)) {
1450 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1451 if (unlikely(!dev)) {
1453 goto out_alloc_etherdev;
1456 pci_set_drvdata(pdev, dev);
1457 SET_NETDEV_DEV(dev, &pdev->dev);
1459 #if SC92031_USE_BAR == 0
1460 dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR);
1461 dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR);
1462 #elif SC92031_USE_BAR == 1
1463 dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR);
1465 dev->irq = pdev->irq;
1467 /* faked with skb_copy_and_csum_dev */
1468 dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1470 dev->netdev_ops = &sc92031_netdev_ops;
1471 dev->watchdog_timeo = TX_TIMEOUT;
1472 dev->ethtool_ops = &sc92031_ethtool_ops;
1474 priv = netdev_priv(dev);
1475 spin_lock_init(&priv->lock);
1476 priv->port_base = port_base;
1478 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1479 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1480 * sc92031_open will work correctly */
1481 tasklet_disable_nosync(&priv->tasklet);
1484 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1486 mac0 = ioread32(port_base + MAC0);
1487 mac1 = ioread32(port_base + MAC0 + 4);
1488 dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24;
1489 dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16;
1490 dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8;
1491 dev->dev_addr[3] = dev->perm_addr[3] = mac0;
1492 dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8;
1493 dev->dev_addr[5] = dev->perm_addr[5] = mac1;
1495 err = register_netdev(dev);
1497 goto out_register_netdev;
1499 #if SC92031_USE_BAR == 0
1500 base_addr = dev->mem_start;
1501 #elif SC92031_USE_BAR == 1
1502 base_addr = dev->base_addr;
1504 printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1505 base_addr, dev->dev_addr, dev->irq);
1509 out_register_netdev:
1512 pci_iounmap(pdev, port_base);
1514 pci_release_regions(pdev);
1515 out_request_regions:
1517 pci_disable_device(pdev);
1522 static void __devexit sc92031_remove(struct pci_dev *pdev)
1524 struct net_device *dev = pci_get_drvdata(pdev);
1525 struct sc92031_priv *priv = netdev_priv(dev);
1526 void __iomem* port_base = priv->port_base;
1528 unregister_netdev(dev);
1530 pci_iounmap(pdev, port_base);
1531 pci_release_regions(pdev);
1532 pci_disable_device(pdev);
1535 static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1537 struct net_device *dev = pci_get_drvdata(pdev);
1538 struct sc92031_priv *priv = netdev_priv(dev);
1540 pci_save_state(pdev);
1542 if (!netif_running(dev))
1545 netif_device_detach(dev);
1547 /* Disable interrupts, stop Tx and Rx. */
1548 sc92031_disable_interrupts(dev);
1550 spin_lock_bh(&priv->lock);
1552 _sc92031_disable_tx_rx(dev);
1553 _sc92031_tx_clear(dev);
1556 spin_unlock_bh(&priv->lock);
1559 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1564 static int sc92031_resume(struct pci_dev *pdev)
1566 struct net_device *dev = pci_get_drvdata(pdev);
1567 struct sc92031_priv *priv = netdev_priv(dev);
1569 pci_restore_state(pdev);
1570 pci_set_power_state(pdev, PCI_D0);
1572 if (!netif_running(dev))
1575 /* Interrupts already disabled by sc92031_suspend */
1576 spin_lock_bh(&priv->lock);
1578 _sc92031_reset(dev);
1581 spin_unlock_bh(&priv->lock);
1582 sc92031_enable_interrupts(dev);
1584 netif_device_attach(dev);
1586 if (netif_carrier_ok(dev))
1587 netif_wake_queue(dev);
1589 netif_tx_disable(dev);
1595 static struct pci_device_id sc92031_pci_device_id_table[] __devinitdata = {
1596 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_SC92031) },
1597 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_8139D) },
1600 MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1602 static struct pci_driver sc92031_pci_driver = {
1603 .name = SC92031_NAME,
1604 .id_table = sc92031_pci_device_id_table,
1605 .probe = sc92031_probe,
1606 .remove = __devexit_p(sc92031_remove),
1607 .suspend = sc92031_suspend,
1608 .resume = sc92031_resume,
1611 static int __init sc92031_init(void)
1613 return pci_register_driver(&sc92031_pci_driver);
1616 static void __exit sc92031_exit(void)
1618 pci_unregister_driver(&sc92031_pci_driver);
1621 module_init(sc92031_init);
1622 module_exit(sc92031_exit);
1624 MODULE_LICENSE("GPL");
1625 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1626 MODULE_DESCRIPTION(SC92031_DESCRIPTION);