1 /* Silan SC92031 PCI Fast Ethernet Adapter driver
3 * Based on vendor drivers:
4 * Silan Fast Ethernet Netcard Driver:
5 * MODULE_AUTHOR ("gaoyonghong");
6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
7 * MODULE_LICENSE("GPL");
8 * 8139D Fast Ethernet driver:
9 * (C) 2002 by gaoyonghong
10 * MODULE_AUTHOR ("gaoyonghong");
11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
12 * MODULE_LICENSE("GPL");
13 * Both are almost identical and seem to be based on pci-skeleton.c
15 * Rewritten for 2.6 by Cesar Eduardo Barros
18 /* Note about set_mac_address: I don't know how to change the hardware
19 * matching, so you need to enable IFF_PROMISC when using it.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/delay.h>
25 #include <linux/pci.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/crc32.h>
34 #define SC92031_NAME "sc92031"
36 /* BAR 0 is MMIO, BAR 1 is PIO */
37 #ifndef SC92031_USE_BAR
38 #define SC92031_USE_BAR 0
41 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
42 static int multicast_filter_limit = 64;
43 module_param(multicast_filter_limit, int, 0);
44 MODULE_PARM_DESC(multicast_filter_limit,
45 "Maximum number of filtered multicast addresses");
48 module_param(media, int, 0);
49 MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
50 " 0x01 = 10M half, 0x02 = 10M full,"
51 " 0x04 = 100M half, 0x08 = 100M full)");
53 /* Size of the in-memory receive ring. */
54 #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
55 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
57 /* Number of Tx descriptor registers. */
60 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
61 #define MAX_ETH_FRAME_SIZE 1536
63 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
64 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
65 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
67 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
68 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
70 /* Time in jiffies before concluding the transmitter is hung. */
71 #define TX_TIMEOUT (4*HZ)
73 #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
76 #define AUTOSELECT 0x00
79 #define M100_HALF 0x04
80 #define M100_FULL 0x08
82 /* Symbolic offsets to registers. */
83 enum silan_registers {
84 Config0 = 0x00, // Config0
85 Config1 = 0x04, // Config1
86 RxBufWPtr = 0x08, // Rx buffer writer poiter
87 IntrStatus = 0x0C, // Interrupt status
88 IntrMask = 0x10, // Interrupt mask
89 RxbufAddr = 0x14, // Rx buffer start address
90 RxBufRPtr = 0x18, // Rx buffer read pointer
91 Txstatusall = 0x1C, // Transmit status of all descriptors
92 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
93 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
94 RxConfig = 0x40, // Rx configuration
95 MAC0 = 0x44, // Ethernet hardware address.
96 MAR0 = 0x4C, // Multicast filter.
97 RxStatus0 = 0x54, // Rx status
98 TxConfig = 0x5C, // Tx configuration
99 PhyCtrl = 0x60, // physical control
100 FlowCtrlConfig = 0x64, // flow control
101 Miicmd0 = 0x68, // Mii command0 register
102 Miicmd1 = 0x6C, // Mii command1 register
103 Miistatus = 0x70, // Mii status register
104 Timercnt = 0x74, // Timer counter register
105 TimerIntr = 0x78, // Timer interrupt register
106 PMConfig = 0x7C, // Power Manager configuration
107 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
108 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
109 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
115 #define MII_BMCR 0 // Basic mode control register
116 #define MII_BMSR 1 // Basic mode status register
118 #define MII_OutputStatus 24
120 #define BMCR_FULLDPLX 0x0100 // Full duplex
121 #define BMCR_ANRESTART 0x0200 // Auto negotiation restart
122 #define BMCR_ANENABLE 0x1000 // Enable auto negotiation
123 #define BMCR_SPEED100 0x2000 // Select 100Mbps
124 #define BMSR_LSTATUS 0x0004 // Link status
125 #define PHY_16_JAB_ENB 0x1000
126 #define PHY_16_PORT_ENB 0x1
128 enum IntrStatusBits {
129 LinkFail = 0x80000000,
131 TimeOut = 0x20000000,
135 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
139 TxCarrierLost = 0x20000000,
140 TxAborted = 0x10000000,
141 TxOutOfWindow = 0x08000000,
143 EarlyTxThresShift = 16,
150 RxStatesOK = 0x80000,
151 RxBadAlign = 0x40000,
152 RxHugeFrame = 0x20000,
153 RxSmallFrame = 0x10000,
156 Rx_Broadcast = 0x2000,
157 Rx_Multicast = 0x1000,
158 RxAddrMatch = 0x0800,
163 RxFullDx = 0x80000000,
165 RxSmall = 0x20000000,
168 RxAllphys = 0x04000000,
169 RxMulticast = 0x02000000,
170 RxBroadcast = 0x01000000,
171 RxLoopBack = (1 << 23) | (1 << 22),
172 LowThresholdShift = 12,
173 HighThresholdShift = 2,
177 TxFullDx = 0x80000000,
179 TxEnbPad = 0x20000000,
180 TxEnbHuge = 0x10000000,
181 TxEnbFCS = 0x08000000,
182 TxNoBackOff = 0x04000000,
183 TxEnbPrem = 0x02000000,
184 TxCareLostCrs = 0x1000000,
185 TxExdCollNum = 0xf00000,
186 TxDataRate = 0x80000,
189 enum PhyCtrlconfigbits {
190 PhyCtrlAne = 0x80000000,
191 PhyCtrlSpd100 = 0x40000000,
192 PhyCtrlSpd10 = 0x20000000,
193 PhyCtrlPhyBaseAddr = 0x1f000000,
194 PhyCtrlDux = 0x800000,
195 PhyCtrlReset = 0x400000,
198 enum FlowCtrlConfigBits {
199 FlowCtrlFullDX = 0x80000000,
200 FlowCtrlEnb = 0x40000000,
204 Cfg0_Reset = 0x80000000,
205 Cfg0_Anaoff = 0x40000000,
206 Cfg0_LDPS = 0x20000000,
210 Cfg1_EarlyRx = 1 << 31,
211 Cfg1_EarlyTx = 1 << 30,
222 Mii_Divider = 0x20000000,
223 Mii_WRITE = 0x400000,
227 Mii_Drvmod = 0x40000,
235 Mii_StatusBusy = 0x80000000,
242 PM_LANWake = 1 << 28,
243 PM_LWPTN = (1 << 27 | 1<< 26),
249 * priv->lock protects most of the fields of priv and most of the
250 * hardware registers. It does not have to protect against softirqs
251 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
252 * it also does not need to be used in ->open and ->stop while the
253 * device interrupts are off.
254 * Not having to protect against softirqs is very useful due to heavy
255 * use of mdelay() at _sc92031_reset.
256 * Functions prefixed with _sc92031_ must be called with the lock held;
257 * functions prefixed with sc92031_ must be called without the lock held.
258 * Use mmiowb() before unlocking if the hardware was written to.
261 /* Locking rules for the interrupt:
262 * - the interrupt and the tasklet never run at the same time
263 * - neither run between sc92031_disable_interrupts and
264 * sc92031_enable_interrupt
267 struct sc92031_priv {
270 void __iomem *port_base;
271 /* pci device structure */
272 struct pci_dev *pdev;
274 struct tasklet_struct tasklet;
276 /* CPU address of rx ring */
278 /* PCI address of rx ring */
279 dma_addr_t rx_ring_dma_addr;
280 /* PCI address of rx ring read pointer */
281 dma_addr_t rx_ring_tail;
283 /* tx ring write index */
285 /* tx ring read index */
287 /* CPU address of tx bounce buffer */
289 /* PCI address of tx bounce buffer */
290 dma_addr_t tx_bufs_dma_addr;
292 /* copies of some hardware registers */
299 /* copy of some flags from dev->flags */
300 unsigned int mc_flags;
302 /* for ETHTOOL_GSTATS */
306 /* for dev->get_stats */
310 /* I don't know which registers can be safely read; however, I can guess
311 * MAC0 is one of them. */
312 static inline void _sc92031_dummy_read(void __iomem *port_base)
314 ioread32(port_base + MAC0);
317 static u32 _sc92031_mii_wait(void __iomem *port_base)
323 mii_status = ioread32(port_base + Miistatus);
324 } while (mii_status & Mii_StatusBusy);
329 static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
331 iowrite32(Mii_Divider, port_base + Miicmd0);
333 _sc92031_mii_wait(port_base);
335 iowrite32(cmd1, port_base + Miicmd1);
336 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
338 return _sc92031_mii_wait(port_base);
341 static void _sc92031_mii_scan(void __iomem *port_base)
343 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
346 static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
348 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
351 static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
353 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
356 static void sc92031_disable_interrupts(struct net_device *dev)
358 struct sc92031_priv *priv = netdev_priv(dev);
359 void __iomem *port_base = priv->port_base;
361 /* tell the tasklet/interrupt not to enable interrupts */
362 atomic_set(&priv->intr_mask, 0);
365 /* stop interrupts */
366 iowrite32(0, port_base + IntrMask);
367 _sc92031_dummy_read(port_base);
370 /* wait for any concurrent interrupt/tasklet to finish */
371 synchronize_irq(dev->irq);
372 tasklet_disable(&priv->tasklet);
375 static void sc92031_enable_interrupts(struct net_device *dev)
377 struct sc92031_priv *priv = netdev_priv(dev);
378 void __iomem *port_base = priv->port_base;
380 tasklet_enable(&priv->tasklet);
382 atomic_set(&priv->intr_mask, IntrBits);
385 iowrite32(IntrBits, port_base + IntrMask);
389 static void _sc92031_disable_tx_rx(struct net_device *dev)
391 struct sc92031_priv *priv = netdev_priv(dev);
392 void __iomem *port_base = priv->port_base;
394 priv->rx_config &= ~RxEnb;
395 priv->tx_config &= ~TxEnb;
396 iowrite32(priv->rx_config, port_base + RxConfig);
397 iowrite32(priv->tx_config, port_base + TxConfig);
400 static void _sc92031_enable_tx_rx(struct net_device *dev)
402 struct sc92031_priv *priv = netdev_priv(dev);
403 void __iomem *port_base = priv->port_base;
405 priv->rx_config |= RxEnb;
406 priv->tx_config |= TxEnb;
407 iowrite32(priv->rx_config, port_base + RxConfig);
408 iowrite32(priv->tx_config, port_base + TxConfig);
411 static void _sc92031_tx_clear(struct net_device *dev)
413 struct sc92031_priv *priv = netdev_priv(dev);
415 while (priv->tx_head - priv->tx_tail > 0) {
417 dev->stats.tx_dropped++;
419 priv->tx_head = priv->tx_tail = 0;
422 static void _sc92031_set_mar(struct net_device *dev)
424 struct sc92031_priv *priv = netdev_priv(dev);
425 void __iomem *port_base = priv->port_base;
426 u32 mar0 = 0, mar1 = 0;
428 if ((dev->flags & IFF_PROMISC)
429 || dev->mc_count > multicast_filter_limit
430 || (dev->flags & IFF_ALLMULTI))
431 mar0 = mar1 = 0xffffffff;
432 else if (dev->flags & IFF_MULTICAST) {
433 struct dev_mc_list *mc_list;
435 for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) {
439 crc = ~ether_crc(ETH_ALEN, mc_list->dmi_addr);
442 if (crc & 0x01) bit |= 0x02;
443 if (crc & 0x02) bit |= 0x01;
444 if (crc & 0x10) bit |= 0x20;
445 if (crc & 0x20) bit |= 0x10;
446 if (crc & 0x40) bit |= 0x08;
447 if (crc & 0x80) bit |= 0x04;
450 mar0 |= 0x1 << (bit - 32);
456 iowrite32(mar0, port_base + MAR0);
457 iowrite32(mar1, port_base + MAR0 + 4);
460 static void _sc92031_set_rx_config(struct net_device *dev)
462 struct sc92031_priv *priv = netdev_priv(dev);
463 void __iomem *port_base = priv->port_base;
464 unsigned int old_mc_flags;
465 u32 rx_config_bits = 0;
467 old_mc_flags = priv->mc_flags;
469 if (dev->flags & IFF_PROMISC)
470 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
471 | RxMulticast | RxAllphys;
473 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
474 rx_config_bits |= RxMulticast;
476 if (dev->flags & IFF_BROADCAST)
477 rx_config_bits |= RxBroadcast;
479 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
480 | RxMulticast | RxAllphys);
481 priv->rx_config |= rx_config_bits;
483 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
484 | IFF_MULTICAST | IFF_BROADCAST);
486 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
487 iowrite32(priv->rx_config, port_base + RxConfig);
490 static bool _sc92031_check_media(struct net_device *dev)
492 struct sc92031_priv *priv = netdev_priv(dev);
493 void __iomem *port_base = priv->port_base;
496 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
498 if (bmsr & BMSR_LSTATUS) {
499 bool speed_100, duplex_full;
500 u32 flow_ctrl_config = 0;
501 u16 output_status = _sc92031_mii_read(port_base,
503 _sc92031_mii_scan(port_base);
505 speed_100 = output_status & 0x2;
506 duplex_full = output_status & 0x4;
508 /* Initial Tx/Rx configuration */
509 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
510 priv->tx_config = 0x48800000;
512 /* NOTE: vendor driver had dead code here to enable tx padding */
515 priv->tx_config |= 0x80000;
518 _sc92031_set_rx_config(dev);
521 priv->rx_config |= RxFullDx;
522 priv->tx_config |= TxFullDx;
523 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
525 priv->rx_config &= ~RxFullDx;
526 priv->tx_config &= ~TxFullDx;
529 _sc92031_set_mar(dev);
530 _sc92031_set_rx_config(dev);
531 _sc92031_enable_tx_rx(dev);
532 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
534 netif_carrier_on(dev);
536 if (printk_ratelimit())
537 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
539 speed_100 ? "100" : "10",
540 duplex_full ? "full" : "half");
543 _sc92031_mii_scan(port_base);
545 netif_carrier_off(dev);
547 _sc92031_disable_tx_rx(dev);
549 if (printk_ratelimit())
550 printk(KERN_INFO "%s: link down\n", dev->name);
555 static void _sc92031_phy_reset(struct net_device *dev)
557 struct sc92031_priv *priv = netdev_priv(dev);
558 void __iomem *port_base = priv->port_base;
561 phy_ctrl = ioread32(port_base + PhyCtrl);
562 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
563 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
568 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
571 phy_ctrl |= PhyCtrlSpd10;
574 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
577 phy_ctrl |= PhyCtrlSpd100;
580 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
584 iowrite32(phy_ctrl, port_base + PhyCtrl);
587 phy_ctrl &= ~PhyCtrlReset;
588 iowrite32(phy_ctrl, port_base + PhyCtrl);
591 _sc92031_mii_write(port_base, MII_JAB,
592 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
593 _sc92031_mii_scan(port_base);
595 netif_carrier_off(dev);
596 netif_stop_queue(dev);
599 static void _sc92031_reset(struct net_device *dev)
601 struct sc92031_priv *priv = netdev_priv(dev);
602 void __iomem *port_base = priv->port_base;
605 iowrite32(0, port_base + PMConfig);
607 /* soft reset the chip */
608 iowrite32(Cfg0_Reset, port_base + Config0);
611 iowrite32(0, port_base + Config0);
614 /* disable interrupts */
615 iowrite32(0, port_base + IntrMask);
617 /* clear multicast address */
618 iowrite32(0, port_base + MAR0);
619 iowrite32(0, port_base + MAR0 + 4);
622 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
623 priv->rx_ring_tail = priv->rx_ring_dma_addr;
626 _sc92031_tx_clear(dev);
628 /* clear old register values */
629 priv->intr_status = 0;
630 atomic_set(&priv->intr_mask, 0);
635 /* configure rx buffer size */
636 /* NOTE: vendor driver had dead code here to enable early tx/rx */
637 iowrite32(Cfg1_Rcv64K, port_base + Config1);
639 _sc92031_phy_reset(dev);
640 _sc92031_check_media(dev);
642 /* calculate rx fifo overflow */
646 iowrite32(priv->pm_config, port_base + PMConfig);
648 /* clear intr register */
649 ioread32(port_base + IntrStatus);
652 static void _sc92031_tx_tasklet(struct net_device *dev)
654 struct sc92031_priv *priv = netdev_priv(dev);
655 void __iomem *port_base = priv->port_base;
657 unsigned old_tx_tail;
661 old_tx_tail = priv->tx_tail;
662 while (priv->tx_head - priv->tx_tail > 0) {
663 entry = priv->tx_tail % NUM_TX_DESC;
664 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
666 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
671 if (tx_status & TxStatOK) {
672 dev->stats.tx_bytes += tx_status & 0x1fff;
673 dev->stats.tx_packets++;
674 /* Note: TxCarrierLost is always asserted at 100mbps. */
675 dev->stats.collisions += (tx_status >> 22) & 0xf;
678 if (tx_status & (TxOutOfWindow | TxAborted)) {
679 dev->stats.tx_errors++;
681 if (tx_status & TxAborted)
682 dev->stats.tx_aborted_errors++;
684 if (tx_status & TxCarrierLost)
685 dev->stats.tx_carrier_errors++;
687 if (tx_status & TxOutOfWindow)
688 dev->stats.tx_window_errors++;
691 if (tx_status & TxUnderrun)
692 dev->stats.tx_fifo_errors++;
695 if (priv->tx_tail != old_tx_tail)
696 if (netif_queue_stopped(dev))
697 netif_wake_queue(dev);
700 static void _sc92031_rx_tasklet_error(struct net_device *dev,
701 u32 rx_status, unsigned rx_size)
703 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
704 dev->stats.rx_errors++;
705 dev->stats.rx_length_errors++;
708 if (!(rx_status & RxStatesOK)) {
709 dev->stats.rx_errors++;
711 if (rx_status & (RxHugeFrame | RxSmallFrame))
712 dev->stats.rx_length_errors++;
714 if (rx_status & RxBadAlign)
715 dev->stats.rx_frame_errors++;
717 if (!(rx_status & RxCRCOK))
718 dev->stats.rx_crc_errors++;
720 struct sc92031_priv *priv = netdev_priv(dev);
725 static void _sc92031_rx_tasklet(struct net_device *dev)
727 struct sc92031_priv *priv = netdev_priv(dev);
728 void __iomem *port_base = priv->port_base;
730 dma_addr_t rx_ring_head;
732 unsigned rx_ring_offset;
733 void *rx_ring = priv->rx_ring;
735 rx_ring_head = ioread32(port_base + RxBufWPtr);
738 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
739 * we need to change it to 32 bits physical address
741 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
742 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
743 if (rx_ring_head < priv->rx_ring_dma_addr)
744 rx_ring_head += RX_BUF_LEN;
746 if (rx_ring_head >= priv->rx_ring_tail)
747 rx_len = rx_ring_head - priv->rx_ring_tail;
749 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
754 if (unlikely(rx_len > RX_BUF_LEN)) {
755 if (printk_ratelimit())
756 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
761 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
765 unsigned rx_size, rx_size_align, pkt_size;
768 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
771 rx_size = rx_status >> 20;
772 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
773 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
775 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
777 if (unlikely(rx_status == 0
778 || rx_size > (MAX_ETH_FRAME_SIZE + 4)
780 || !(rx_status & RxStatesOK))) {
781 _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
785 if (unlikely(rx_size_align + 4 > rx_len)) {
786 if (printk_ratelimit())
787 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
791 rx_len -= rx_size_align + 4;
793 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
794 if (unlikely(!skb)) {
795 if (printk_ratelimit())
796 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
797 dev->name, pkt_size);
801 skb_reserve(skb, NET_IP_ALIGN);
803 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
804 memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
805 rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
806 memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
807 rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
809 memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
812 skb->protocol = eth_type_trans(skb, dev);
815 dev->stats.rx_bytes += pkt_size;
816 dev->stats.rx_packets++;
818 if (rx_status & Rx_Multicast)
819 dev->stats.multicast++;
822 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
826 priv->rx_ring_tail = rx_ring_head;
827 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
830 static void _sc92031_link_tasklet(struct net_device *dev)
832 if (_sc92031_check_media(dev))
833 netif_wake_queue(dev);
835 netif_stop_queue(dev);
836 dev->stats.tx_carrier_errors++;
840 static void sc92031_tasklet(unsigned long data)
842 struct net_device *dev = (struct net_device *)data;
843 struct sc92031_priv *priv = netdev_priv(dev);
844 void __iomem *port_base = priv->port_base;
845 u32 intr_status, intr_mask;
847 intr_status = priv->intr_status;
849 spin_lock(&priv->lock);
851 if (unlikely(!netif_running(dev)))
854 if (intr_status & TxOK)
855 _sc92031_tx_tasklet(dev);
857 if (intr_status & RxOK)
858 _sc92031_rx_tasklet(dev);
860 if (intr_status & RxOverflow)
861 dev->stats.rx_errors++;
863 if (intr_status & TimeOut) {
864 dev->stats.rx_errors++;
865 dev->stats.rx_length_errors++;
868 if (intr_status & (LinkFail | LinkOK))
869 _sc92031_link_tasklet(dev);
872 intr_mask = atomic_read(&priv->intr_mask);
875 iowrite32(intr_mask, port_base + IntrMask);
878 spin_unlock(&priv->lock);
881 static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
883 struct net_device *dev = dev_id;
884 struct sc92031_priv *priv = netdev_priv(dev);
885 void __iomem *port_base = priv->port_base;
886 u32 intr_status, intr_mask;
888 /* mask interrupts before clearing IntrStatus */
889 iowrite32(0, port_base + IntrMask);
890 _sc92031_dummy_read(port_base);
892 intr_status = ioread32(port_base + IntrStatus);
893 if (unlikely(intr_status == 0xffffffff))
894 return IRQ_NONE; // hardware has gone missing
896 intr_status &= IntrBits;
900 priv->intr_status = intr_status;
901 tasklet_schedule(&priv->tasklet);
906 intr_mask = atomic_read(&priv->intr_mask);
909 iowrite32(intr_mask, port_base + IntrMask);
915 static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
917 struct sc92031_priv *priv = netdev_priv(dev);
918 void __iomem *port_base = priv->port_base;
920 // FIXME I do not understand what is this trying to do.
921 if (netif_running(dev)) {
924 spin_lock_bh(&priv->lock);
926 /* Update the error count. */
927 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
929 if (temp == 0xffff) {
930 priv->rx_value += temp;
931 dev->stats.rx_fifo_errors = priv->rx_value;
933 dev->stats.rx_fifo_errors = temp + priv->rx_value;
935 spin_unlock_bh(&priv->lock);
941 static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
943 struct sc92031_priv *priv = netdev_priv(dev);
944 void __iomem *port_base = priv->port_base;
949 if (unlikely(skb->len > TX_BUF_SIZE)) {
950 dev->stats.tx_dropped++;
954 spin_lock(&priv->lock);
956 if (unlikely(!netif_carrier_ok(dev))) {
957 dev->stats.tx_dropped++;
961 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
963 entry = priv->tx_head++ % NUM_TX_DESC;
965 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
968 if (len < ETH_ZLEN) {
969 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
979 tx_status = 0x30000 | len;
981 tx_status = 0x50000 | len;
983 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
984 port_base + TxAddr0 + entry * 4);
985 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
988 dev->trans_start = jiffies;
990 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
991 netif_stop_queue(dev);
994 spin_unlock(&priv->lock);
1002 static int sc92031_open(struct net_device *dev)
1005 struct sc92031_priv *priv = netdev_priv(dev);
1006 struct pci_dev *pdev = priv->pdev;
1008 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
1009 &priv->rx_ring_dma_addr);
1010 if (unlikely(!priv->rx_ring)) {
1012 goto out_alloc_rx_ring;
1015 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1016 &priv->tx_bufs_dma_addr);
1017 if (unlikely(!priv->tx_bufs)) {
1019 goto out_alloc_tx_bufs;
1021 priv->tx_head = priv->tx_tail = 0;
1023 err = request_irq(pdev->irq, sc92031_interrupt,
1024 IRQF_SHARED, dev->name, dev);
1025 if (unlikely(err < 0))
1026 goto out_request_irq;
1028 priv->pm_config = 0;
1030 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1031 spin_lock_bh(&priv->lock);
1033 _sc92031_reset(dev);
1036 spin_unlock_bh(&priv->lock);
1037 sc92031_enable_interrupts(dev);
1039 if (netif_carrier_ok(dev))
1040 netif_start_queue(dev);
1042 netif_tx_disable(dev);
1047 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1048 priv->tx_bufs_dma_addr);
1050 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1051 priv->rx_ring_dma_addr);
1056 static int sc92031_stop(struct net_device *dev)
1058 struct sc92031_priv *priv = netdev_priv(dev);
1059 struct pci_dev *pdev = priv->pdev;
1061 netif_tx_disable(dev);
1063 /* Disable interrupts, stop Tx and Rx. */
1064 sc92031_disable_interrupts(dev);
1066 spin_lock_bh(&priv->lock);
1068 _sc92031_disable_tx_rx(dev);
1069 _sc92031_tx_clear(dev);
1072 spin_unlock_bh(&priv->lock);
1074 free_irq(pdev->irq, dev);
1075 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1076 priv->tx_bufs_dma_addr);
1077 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1078 priv->rx_ring_dma_addr);
1083 static void sc92031_set_multicast_list(struct net_device *dev)
1085 struct sc92031_priv *priv = netdev_priv(dev);
1087 spin_lock_bh(&priv->lock);
1089 _sc92031_set_mar(dev);
1090 _sc92031_set_rx_config(dev);
1093 spin_unlock_bh(&priv->lock);
1096 static void sc92031_tx_timeout(struct net_device *dev)
1098 struct sc92031_priv *priv = netdev_priv(dev);
1100 /* Disable interrupts by clearing the interrupt mask.*/
1101 sc92031_disable_interrupts(dev);
1103 spin_lock(&priv->lock);
1105 priv->tx_timeouts++;
1107 _sc92031_reset(dev);
1110 spin_unlock(&priv->lock);
1112 /* enable interrupts */
1113 sc92031_enable_interrupts(dev);
1115 if (netif_carrier_ok(dev))
1116 netif_wake_queue(dev);
1119 #ifdef CONFIG_NET_POLL_CONTROLLER
1120 static void sc92031_poll_controller(struct net_device *dev)
1122 disable_irq(dev->irq);
1123 if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE)
1124 sc92031_tasklet((unsigned long)dev);
1125 enable_irq(dev->irq);
1129 static int sc92031_ethtool_get_settings(struct net_device *dev,
1130 struct ethtool_cmd *cmd)
1132 struct sc92031_priv *priv = netdev_priv(dev);
1133 void __iomem *port_base = priv->port_base;
1138 spin_lock_bh(&priv->lock);
1140 phy_address = ioread32(port_base + Miicmd1) >> 27;
1141 phy_ctrl = ioread32(port_base + PhyCtrl);
1143 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1144 _sc92031_mii_scan(port_base);
1147 spin_unlock_bh(&priv->lock);
1149 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1150 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1151 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1153 cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
1155 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1156 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1157 cmd->advertising |= ADVERTISED_Autoneg;
1159 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1160 cmd->advertising |= ADVERTISED_10baseT_Half;
1162 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1163 == (PhyCtrlSpd10 | PhyCtrlDux))
1164 cmd->advertising |= ADVERTISED_10baseT_Full;
1166 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1167 cmd->advertising |= ADVERTISED_100baseT_Half;
1169 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1170 == (PhyCtrlSpd100 | PhyCtrlDux))
1171 cmd->advertising |= ADVERTISED_100baseT_Full;
1173 if (phy_ctrl & PhyCtrlAne)
1174 cmd->advertising |= ADVERTISED_Autoneg;
1176 cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1177 cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1178 cmd->port = PORT_MII;
1179 cmd->phy_address = phy_address;
1180 cmd->transceiver = XCVR_INTERNAL;
1181 cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1186 static int sc92031_ethtool_set_settings(struct net_device *dev,
1187 struct ethtool_cmd *cmd)
1189 struct sc92031_priv *priv = netdev_priv(dev);
1190 void __iomem *port_base = priv->port_base;
1194 if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100))
1196 if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
1198 if (!(cmd->port == PORT_MII))
1200 if (!(cmd->phy_address == 0x1f))
1202 if (!(cmd->transceiver == XCVR_INTERNAL))
1204 if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
1207 if (cmd->autoneg == AUTONEG_ENABLE) {
1208 if (!(cmd->advertising & (ADVERTISED_Autoneg
1209 | ADVERTISED_100baseT_Full
1210 | ADVERTISED_100baseT_Half
1211 | ADVERTISED_10baseT_Full
1212 | ADVERTISED_10baseT_Half)))
1215 phy_ctrl = PhyCtrlAne;
1217 // FIXME: I'm not sure what the original code was trying to do
1218 if (cmd->advertising & ADVERTISED_Autoneg)
1219 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1220 if (cmd->advertising & ADVERTISED_100baseT_Full)
1221 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1222 if (cmd->advertising & ADVERTISED_100baseT_Half)
1223 phy_ctrl |= PhyCtrlSpd100;
1224 if (cmd->advertising & ADVERTISED_10baseT_Full)
1225 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1226 if (cmd->advertising & ADVERTISED_10baseT_Half)
1227 phy_ctrl |= PhyCtrlSpd10;
1229 // FIXME: Whole branch guessed
1232 if (cmd->speed == SPEED_10)
1233 phy_ctrl |= PhyCtrlSpd10;
1234 else /* cmd->speed == SPEED_100 */
1235 phy_ctrl |= PhyCtrlSpd100;
1237 if (cmd->duplex == DUPLEX_FULL)
1238 phy_ctrl |= PhyCtrlDux;
1241 spin_lock_bh(&priv->lock);
1243 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1244 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1245 | PhyCtrlSpd100 | PhyCtrlSpd10);
1246 if (phy_ctrl != old_phy_ctrl)
1247 iowrite32(phy_ctrl, port_base + PhyCtrl);
1249 spin_unlock_bh(&priv->lock);
1254 static void sc92031_ethtool_get_drvinfo(struct net_device *dev,
1255 struct ethtool_drvinfo *drvinfo)
1257 struct sc92031_priv *priv = netdev_priv(dev);
1258 struct pci_dev *pdev = priv->pdev;
1260 strcpy(drvinfo->driver, SC92031_NAME);
1261 strcpy(drvinfo->bus_info, pci_name(pdev));
1264 static void sc92031_ethtool_get_wol(struct net_device *dev,
1265 struct ethtool_wolinfo *wolinfo)
1267 struct sc92031_priv *priv = netdev_priv(dev);
1268 void __iomem *port_base = priv->port_base;
1271 spin_lock_bh(&priv->lock);
1272 pm_config = ioread32(port_base + PMConfig);
1273 spin_unlock_bh(&priv->lock);
1276 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1277 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1278 wolinfo->wolopts = 0;
1280 if (pm_config & PM_LinkUp)
1281 wolinfo->wolopts |= WAKE_PHY;
1283 if (pm_config & PM_Magic)
1284 wolinfo->wolopts |= WAKE_MAGIC;
1286 if (pm_config & PM_WakeUp)
1288 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1291 static int sc92031_ethtool_set_wol(struct net_device *dev,
1292 struct ethtool_wolinfo *wolinfo)
1294 struct sc92031_priv *priv = netdev_priv(dev);
1295 void __iomem *port_base = priv->port_base;
1298 spin_lock_bh(&priv->lock);
1300 pm_config = ioread32(port_base + PMConfig)
1301 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1303 if (wolinfo->wolopts & WAKE_PHY)
1304 pm_config |= PM_LinkUp;
1306 if (wolinfo->wolopts & WAKE_MAGIC)
1307 pm_config |= PM_Magic;
1310 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1311 pm_config |= PM_WakeUp;
1313 priv->pm_config = pm_config;
1314 iowrite32(pm_config, port_base + PMConfig);
1317 spin_unlock_bh(&priv->lock);
1322 static int sc92031_ethtool_nway_reset(struct net_device *dev)
1325 struct sc92031_priv *priv = netdev_priv(dev);
1326 void __iomem *port_base = priv->port_base;
1329 spin_lock_bh(&priv->lock);
1331 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1332 if (!(bmcr & BMCR_ANENABLE)) {
1337 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1340 _sc92031_mii_scan(port_base);
1343 spin_unlock_bh(&priv->lock);
1348 static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1353 static void sc92031_ethtool_get_strings(struct net_device *dev,
1354 u32 stringset, u8 *data)
1356 if (stringset == ETH_SS_STATS)
1357 memcpy(data, sc92031_ethtool_stats_strings,
1358 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1361 static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1365 return SILAN_STATS_NUM;
1371 static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1372 struct ethtool_stats *stats, u64 *data)
1374 struct sc92031_priv *priv = netdev_priv(dev);
1376 spin_lock_bh(&priv->lock);
1377 data[0] = priv->tx_timeouts;
1378 data[1] = priv->rx_loss;
1379 spin_unlock_bh(&priv->lock);
1382 static const struct ethtool_ops sc92031_ethtool_ops = {
1383 .get_settings = sc92031_ethtool_get_settings,
1384 .set_settings = sc92031_ethtool_set_settings,
1385 .get_drvinfo = sc92031_ethtool_get_drvinfo,
1386 .get_wol = sc92031_ethtool_get_wol,
1387 .set_wol = sc92031_ethtool_set_wol,
1388 .nway_reset = sc92031_ethtool_nway_reset,
1389 .get_link = ethtool_op_get_link,
1390 .get_strings = sc92031_ethtool_get_strings,
1391 .get_sset_count = sc92031_ethtool_get_sset_count,
1392 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
1396 static const struct net_device_ops sc92031_netdev_ops = {
1397 .ndo_get_stats = sc92031_get_stats,
1398 .ndo_start_xmit = sc92031_start_xmit,
1399 .ndo_open = sc92031_open,
1400 .ndo_stop = sc92031_stop,
1401 .ndo_set_multicast_list = sc92031_set_multicast_list,
1402 .ndo_change_mtu = eth_change_mtu,
1403 .ndo_validate_addr = eth_validate_addr,
1404 .ndo_set_mac_address = eth_mac_addr,
1405 .ndo_tx_timeout = sc92031_tx_timeout,
1406 #ifdef CONFIG_NET_POLL_CONTROLLER
1407 .ndo_poll_controller = sc92031_poll_controller,
1411 static int __devinit sc92031_probe(struct pci_dev *pdev,
1412 const struct pci_device_id *id)
1415 void __iomem* port_base;
1416 struct net_device *dev;
1417 struct sc92031_priv *priv;
1419 unsigned long base_addr;
1421 err = pci_enable_device(pdev);
1422 if (unlikely(err < 0))
1423 goto out_enable_device;
1425 pci_set_master(pdev);
1427 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1428 if (unlikely(err < 0))
1429 goto out_set_dma_mask;
1431 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1432 if (unlikely(err < 0))
1433 goto out_set_dma_mask;
1435 err = pci_request_regions(pdev, SC92031_NAME);
1436 if (unlikely(err < 0))
1437 goto out_request_regions;
1439 port_base = pci_iomap(pdev, SC92031_USE_BAR, 0);
1440 if (unlikely(!port_base)) {
1445 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1446 if (unlikely(!dev)) {
1448 goto out_alloc_etherdev;
1451 pci_set_drvdata(pdev, dev);
1452 SET_NETDEV_DEV(dev, &pdev->dev);
1454 #if SC92031_USE_BAR == 0
1455 dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR);
1456 dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR);
1457 #elif SC92031_USE_BAR == 1
1458 dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR);
1460 dev->irq = pdev->irq;
1462 /* faked with skb_copy_and_csum_dev */
1463 dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1465 dev->netdev_ops = &sc92031_netdev_ops;
1466 dev->watchdog_timeo = TX_TIMEOUT;
1467 dev->ethtool_ops = &sc92031_ethtool_ops;
1469 priv = netdev_priv(dev);
1470 spin_lock_init(&priv->lock);
1471 priv->port_base = port_base;
1473 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1474 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1475 * sc92031_open will work correctly */
1476 tasklet_disable_nosync(&priv->tasklet);
1479 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1481 mac0 = ioread32(port_base + MAC0);
1482 mac1 = ioread32(port_base + MAC0 + 4);
1483 dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24;
1484 dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16;
1485 dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8;
1486 dev->dev_addr[3] = dev->perm_addr[3] = mac0;
1487 dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8;
1488 dev->dev_addr[5] = dev->perm_addr[5] = mac1;
1490 err = register_netdev(dev);
1492 goto out_register_netdev;
1494 #if SC92031_USE_BAR == 0
1495 base_addr = dev->mem_start;
1496 #elif SC92031_USE_BAR == 1
1497 base_addr = dev->base_addr;
1499 printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1500 base_addr, dev->dev_addr, dev->irq);
1504 out_register_netdev:
1507 pci_iounmap(pdev, port_base);
1509 pci_release_regions(pdev);
1510 out_request_regions:
1512 pci_disable_device(pdev);
1517 static void __devexit sc92031_remove(struct pci_dev *pdev)
1519 struct net_device *dev = pci_get_drvdata(pdev);
1520 struct sc92031_priv *priv = netdev_priv(dev);
1521 void __iomem* port_base = priv->port_base;
1523 unregister_netdev(dev);
1525 pci_iounmap(pdev, port_base);
1526 pci_release_regions(pdev);
1527 pci_disable_device(pdev);
1530 static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1532 struct net_device *dev = pci_get_drvdata(pdev);
1533 struct sc92031_priv *priv = netdev_priv(dev);
1535 pci_save_state(pdev);
1537 if (!netif_running(dev))
1540 netif_device_detach(dev);
1542 /* Disable interrupts, stop Tx and Rx. */
1543 sc92031_disable_interrupts(dev);
1545 spin_lock_bh(&priv->lock);
1547 _sc92031_disable_tx_rx(dev);
1548 _sc92031_tx_clear(dev);
1551 spin_unlock_bh(&priv->lock);
1554 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1559 static int sc92031_resume(struct pci_dev *pdev)
1561 struct net_device *dev = pci_get_drvdata(pdev);
1562 struct sc92031_priv *priv = netdev_priv(dev);
1564 pci_restore_state(pdev);
1565 pci_set_power_state(pdev, PCI_D0);
1567 if (!netif_running(dev))
1570 /* Interrupts already disabled by sc92031_suspend */
1571 spin_lock_bh(&priv->lock);
1573 _sc92031_reset(dev);
1576 spin_unlock_bh(&priv->lock);
1577 sc92031_enable_interrupts(dev);
1579 netif_device_attach(dev);
1581 if (netif_carrier_ok(dev))
1582 netif_wake_queue(dev);
1584 netif_tx_disable(dev);
1590 static struct pci_device_id sc92031_pci_device_id_table[] __devinitdata = {
1591 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) },
1592 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) },
1595 MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1597 static struct pci_driver sc92031_pci_driver = {
1598 .name = SC92031_NAME,
1599 .id_table = sc92031_pci_device_id_table,
1600 .probe = sc92031_probe,
1601 .remove = __devexit_p(sc92031_remove),
1602 .suspend = sc92031_suspend,
1603 .resume = sc92031_resume,
1606 static int __init sc92031_init(void)
1608 return pci_register_driver(&sc92031_pci_driver);
1611 static void __exit sc92031_exit(void)
1613 pci_unregister_driver(&sc92031_pci_driver);
1616 module_init(sc92031_init);
1617 module_exit(sc92031_exit);
1619 MODULE_LICENSE("GPL");
1620 MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1621 MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");