1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2007 Neterion Inc.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
55 ************************************************************************/
57 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
59 #include <linux/module.h>
60 #include <linux/types.h>
61 #include <linux/errno.h>
62 #include <linux/ioport.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/kernel.h>
66 #include <linux/netdevice.h>
67 #include <linux/etherdevice.h>
68 #include <linux/mdio.h>
69 #include <linux/skbuff.h>
70 #include <linux/init.h>
71 #include <linux/delay.h>
72 #include <linux/stddef.h>
73 #include <linux/ioctl.h>
74 #include <linux/timex.h>
75 #include <linux/ethtool.h>
76 #include <linux/workqueue.h>
77 #include <linux/if_vlan.h>
79 #include <linux/tcp.h>
80 #include <linux/uaccess.h>
82 #include <linux/slab.h>
85 #include <asm/system.h>
86 #include <asm/div64.h>
91 #include "s2io-regs.h"
93 #define DRV_VERSION "2.0.26.25"
95 /* S2io Driver name & version. */
96 static char s2io_driver_name[] = "Neterion";
97 static char s2io_driver_version[] = DRV_VERSION;
99 static int rxd_size[2] = {32, 48};
100 static int rxd_count[2] = {127, 85};
102 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
106 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
107 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
113 * Cards with following subsystem_id have a link state indication
114 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
115 * macro below identifies these cards given the subsystem_id.
117 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
118 (dev_type == XFRAME_I_DEVICE) ? \
119 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
120 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
122 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
123 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
125 static inline int is_s2io_card_up(const struct s2io_nic *sp)
127 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
130 /* Ethtool related variables and Macros. */
131 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
132 "Register test\t(offline)",
133 "Eeprom test\t(offline)",
134 "Link test\t(online)",
135 "RLDRAM test\t(offline)",
136 "BIST Test\t(offline)"
139 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
141 {"tmac_data_octets"},
145 {"tmac_pause_ctrl_frms"},
149 {"tmac_any_err_frms"},
150 {"tmac_ttl_less_fb_octets"},
151 {"tmac_vld_ip_octets"},
159 {"rmac_data_octets"},
160 {"rmac_fcs_err_frms"},
162 {"rmac_vld_mcst_frms"},
163 {"rmac_vld_bcst_frms"},
164 {"rmac_in_rng_len_err_frms"},
165 {"rmac_out_rng_len_err_frms"},
167 {"rmac_pause_ctrl_frms"},
168 {"rmac_unsup_ctrl_frms"},
170 {"rmac_accepted_ucst_frms"},
171 {"rmac_accepted_nucst_frms"},
172 {"rmac_discarded_frms"},
173 {"rmac_drop_events"},
174 {"rmac_ttl_less_fb_octets"},
176 {"rmac_usized_frms"},
177 {"rmac_osized_frms"},
179 {"rmac_jabber_frms"},
180 {"rmac_ttl_64_frms"},
181 {"rmac_ttl_65_127_frms"},
182 {"rmac_ttl_128_255_frms"},
183 {"rmac_ttl_256_511_frms"},
184 {"rmac_ttl_512_1023_frms"},
185 {"rmac_ttl_1024_1518_frms"},
193 {"rmac_err_drp_udp"},
194 {"rmac_xgmii_err_sym"},
212 {"rmac_xgmii_data_err_cnt"},
213 {"rmac_xgmii_ctrl_err_cnt"},
214 {"rmac_accepted_ip"},
218 {"new_rd_req_rtry_cnt"},
220 {"wr_rtry_rd_ack_cnt"},
223 {"new_wr_req_rtry_cnt"},
226 {"rd_rtry_wr_ack_cnt"},
236 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
237 {"rmac_ttl_1519_4095_frms"},
238 {"rmac_ttl_4096_8191_frms"},
239 {"rmac_ttl_8192_max_frms"},
240 {"rmac_ttl_gt_max_frms"},
241 {"rmac_osized_alt_frms"},
242 {"rmac_jabber_alt_frms"},
243 {"rmac_gt_max_alt_frms"},
245 {"rmac_len_discard"},
246 {"rmac_fcs_discard"},
249 {"rmac_red_discard"},
250 {"rmac_rts_discard"},
251 {"rmac_ingm_full_discard"},
255 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
256 {"\n DRIVER STATISTICS"},
257 {"single_bit_ecc_errs"},
258 {"double_bit_ecc_errs"},
271 {"alarm_transceiver_temp_high"},
272 {"alarm_transceiver_temp_low"},
273 {"alarm_laser_bias_current_high"},
274 {"alarm_laser_bias_current_low"},
275 {"alarm_laser_output_power_high"},
276 {"alarm_laser_output_power_low"},
277 {"warn_transceiver_temp_high"},
278 {"warn_transceiver_temp_low"},
279 {"warn_laser_bias_current_high"},
280 {"warn_laser_bias_current_low"},
281 {"warn_laser_output_power_high"},
282 {"warn_laser_output_power_low"},
283 {"lro_aggregated_pkts"},
284 {"lro_flush_both_count"},
285 {"lro_out_of_sequence_pkts"},
286 {"lro_flush_due_to_max_pkts"},
287 {"lro_avg_aggr_pkts"},
288 {"mem_alloc_fail_cnt"},
289 {"pci_map_fail_cnt"},
290 {"watchdog_timer_cnt"},
297 {"tx_tcode_buf_abort_cnt"},
298 {"tx_tcode_desc_abort_cnt"},
299 {"tx_tcode_parity_err_cnt"},
300 {"tx_tcode_link_loss_cnt"},
301 {"tx_tcode_list_proc_err_cnt"},
302 {"rx_tcode_parity_err_cnt"},
303 {"rx_tcode_abort_cnt"},
304 {"rx_tcode_parity_abort_cnt"},
305 {"rx_tcode_rda_fail_cnt"},
306 {"rx_tcode_unkn_prot_cnt"},
307 {"rx_tcode_fcs_err_cnt"},
308 {"rx_tcode_buf_size_err_cnt"},
309 {"rx_tcode_rxd_corrupt_cnt"},
310 {"rx_tcode_unkn_err_cnt"},
318 {"mac_tmac_err_cnt"},
319 {"mac_rmac_err_cnt"},
320 {"xgxs_txgxs_err_cnt"},
321 {"xgxs_rxgxs_err_cnt"},
323 {"prc_pcix_err_cnt"},
330 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
331 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
332 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
334 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
335 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
337 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
338 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
340 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
341 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
343 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
344 init_timer(&timer); \
345 timer.function = handle; \
346 timer.data = (unsigned long)arg; \
347 mod_timer(&timer, (jiffies + exp)) \
349 /* copy mac addr to def_mac_addr array */
350 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
352 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
353 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
354 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
355 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
356 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
357 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
361 static void s2io_vlan_rx_register(struct net_device *dev,
362 struct vlan_group *grp)
365 struct s2io_nic *nic = netdev_priv(dev);
366 unsigned long flags[MAX_TX_FIFOS];
367 struct config_param *config = &nic->config;
368 struct mac_info *mac_control = &nic->mac_control;
370 for (i = 0; i < config->tx_fifo_num; i++) {
371 struct fifo_info *fifo = &mac_control->fifos[i];
373 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
378 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
379 struct fifo_info *fifo = &mac_control->fifos[i];
381 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
385 /* Unregister the vlan */
386 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
389 struct s2io_nic *nic = netdev_priv(dev);
390 unsigned long flags[MAX_TX_FIFOS];
391 struct config_param *config = &nic->config;
392 struct mac_info *mac_control = &nic->mac_control;
394 for (i = 0; i < config->tx_fifo_num; i++) {
395 struct fifo_info *fifo = &mac_control->fifos[i];
397 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
401 vlan_group_set_device(nic->vlgrp, vid, NULL);
403 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
404 struct fifo_info *fifo = &mac_control->fifos[i];
406 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
411 * Constants to be programmed into the Xena's registers, to configure
416 static const u64 herc_act_dtx_cfg[] = {
418 0x8000051536750000ULL, 0x80000515367500E0ULL,
420 0x8000051536750004ULL, 0x80000515367500E4ULL,
422 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
424 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
426 0x801205150D440000ULL, 0x801205150D4400E0ULL,
428 0x801205150D440004ULL, 0x801205150D4400E4ULL,
430 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
432 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
437 static const u64 xena_dtx_cfg[] = {
439 0x8000051500000000ULL, 0x80000515000000E0ULL,
441 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
443 0x8001051500000000ULL, 0x80010515000000E0ULL,
445 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
447 0x8002051500000000ULL, 0x80020515000000E0ULL,
449 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
454 * Constants for Fixing the MacAddress problem seen mostly on
457 static const u64 fix_mac[] = {
458 0x0060000000000000ULL, 0x0060600000000000ULL,
459 0x0040600000000000ULL, 0x0000600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0060600000000000ULL,
470 0x0020600000000000ULL, 0x0000600000000000ULL,
471 0x0040600000000000ULL, 0x0060600000000000ULL,
475 MODULE_LICENSE("GPL");
476 MODULE_VERSION(DRV_VERSION);
479 /* Module Loadable parameters. */
480 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
481 S2IO_PARM_INT(rx_ring_num, 1);
482 S2IO_PARM_INT(multiq, 0);
483 S2IO_PARM_INT(rx_ring_mode, 1);
484 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
485 S2IO_PARM_INT(rmac_pause_time, 0x100);
486 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
487 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
488 S2IO_PARM_INT(shared_splits, 0);
489 S2IO_PARM_INT(tmac_util_period, 5);
490 S2IO_PARM_INT(rmac_util_period, 5);
491 S2IO_PARM_INT(l3l4hdr_size, 128);
492 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
493 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
494 /* Frequency of Rx desc syncs expressed as power of 2 */
495 S2IO_PARM_INT(rxsync_frequency, 3);
496 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
497 S2IO_PARM_INT(intr_type, 2);
498 /* Large receive offload feature */
499 static unsigned int lro_enable;
500 module_param_named(lro, lro_enable, uint, 0);
502 /* Max pkts to be aggregated by LRO at one time. If not specified,
503 * aggregation happens until we hit max IP pkt size(64K)
505 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
506 S2IO_PARM_INT(indicate_max_pkts, 0);
508 S2IO_PARM_INT(napi, 1);
509 S2IO_PARM_INT(ufo, 0);
510 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
512 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
513 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
514 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
515 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
516 static unsigned int rts_frm_len[MAX_RX_RINGS] =
517 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
519 module_param_array(tx_fifo_len, uint, NULL, 0);
520 module_param_array(rx_ring_sz, uint, NULL, 0);
521 module_param_array(rts_frm_len, uint, NULL, 0);
525 * This table lists all the devices that this driver supports.
527 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
532 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
533 PCI_ANY_ID, PCI_ANY_ID},
534 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
535 PCI_ANY_ID, PCI_ANY_ID},
539 MODULE_DEVICE_TABLE(pci, s2io_tbl);
541 static struct pci_error_handlers s2io_err_handler = {
542 .error_detected = s2io_io_error_detected,
543 .slot_reset = s2io_io_slot_reset,
544 .resume = s2io_io_resume,
547 static struct pci_driver s2io_driver = {
549 .id_table = s2io_tbl,
550 .probe = s2io_init_nic,
551 .remove = __devexit_p(s2io_rem_nic),
552 .err_handler = &s2io_err_handler,
555 /* A simplifier macro used both by init and free shared_mem Fns(). */
556 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
558 /* netqueue manipulation helper functions */
559 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
561 if (!sp->config.multiq) {
564 for (i = 0; i < sp->config.tx_fifo_num; i++)
565 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
567 netif_tx_stop_all_queues(sp->dev);
570 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
572 if (!sp->config.multiq)
573 sp->mac_control.fifos[fifo_no].queue_state =
576 netif_tx_stop_all_queues(sp->dev);
579 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
581 if (!sp->config.multiq) {
584 for (i = 0; i < sp->config.tx_fifo_num; i++)
585 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
587 netif_tx_start_all_queues(sp->dev);
590 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
592 if (!sp->config.multiq)
593 sp->mac_control.fifos[fifo_no].queue_state =
596 netif_tx_start_all_queues(sp->dev);
599 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
601 if (!sp->config.multiq) {
604 for (i = 0; i < sp->config.tx_fifo_num; i++)
605 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
607 netif_tx_wake_all_queues(sp->dev);
610 static inline void s2io_wake_tx_queue(
611 struct fifo_info *fifo, int cnt, u8 multiq)
615 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
616 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
617 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
618 if (netif_queue_stopped(fifo->dev)) {
619 fifo->queue_state = FIFO_QUEUE_START;
620 netif_wake_queue(fifo->dev);
626 * init_shared_mem - Allocation and Initialization of Memory
627 * @nic: Device private variable.
628 * Description: The function allocates all the memory areas shared
629 * between the NIC and the driver. This includes Tx descriptors,
630 * Rx descriptors and the statistics block.
633 static int init_shared_mem(struct s2io_nic *nic)
636 void *tmp_v_addr, *tmp_v_addr_next;
637 dma_addr_t tmp_p_addr, tmp_p_addr_next;
638 struct RxD_block *pre_rxd_blk = NULL;
640 int lst_size, lst_per_page;
641 struct net_device *dev = nic->dev;
644 struct config_param *config = &nic->config;
645 struct mac_info *mac_control = &nic->mac_control;
646 unsigned long long mem_allocated = 0;
648 /* Allocation and initialization of TXDLs in FIFOs */
650 for (i = 0; i < config->tx_fifo_num; i++) {
651 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
653 size += tx_cfg->fifo_len;
655 if (size > MAX_AVAILABLE_TXDS) {
657 "Too many TxDs requested: %d, max supported: %d\n",
658 size, MAX_AVAILABLE_TXDS);
663 for (i = 0; i < config->tx_fifo_num; i++) {
664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
666 size = tx_cfg->fifo_len;
668 * Legal values are from 2 to 8192
671 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
672 "Valid lengths are 2 through 8192\n",
678 lst_size = (sizeof(struct TxD) * config->max_txds);
679 lst_per_page = PAGE_SIZE / lst_size;
681 for (i = 0; i < config->tx_fifo_num; i++) {
682 struct fifo_info *fifo = &mac_control->fifos[i];
683 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 int fifo_len = tx_cfg->fifo_len;
685 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
687 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688 if (!fifo->list_info) {
689 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
692 mem_allocated += list_holder_size;
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
697 struct fifo_info *fifo = &mac_control->fifos[i];
698 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
700 fifo->tx_curr_put_info.offset = 0;
701 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->tx_curr_get_info.offset = 0;
703 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
706 fifo->max_txds = MAX_SKB_FRAGS + 2;
709 for (j = 0; j < page_num; j++) {
713 tmp_v = pci_alloc_consistent(nic->pdev,
717 "pci_alloc_consistent failed for TxDL\n");
720 /* If we got a zero DMA address(can happen on
721 * certain platforms like PPC), reallocate.
722 * Store virtual address of page we don't want,
726 mac_control->zerodma_virt_addr = tmp_v;
728 "%s: Zero DMA address for TxDL. "
729 "Virtual address %p\n",
731 tmp_v = pci_alloc_consistent(nic->pdev,
735 "pci_alloc_consistent failed for TxDL\n");
738 mem_allocated += PAGE_SIZE;
740 while (k < lst_per_page) {
741 int l = (j * lst_per_page) + k;
742 if (l == tx_cfg->fifo_len)
744 fifo->list_info[l].list_virt_addr =
745 tmp_v + (k * lst_size);
746 fifo->list_info[l].list_phy_addr =
747 tmp_p + (k * lst_size);
753 for (i = 0; i < config->tx_fifo_num; i++) {
754 struct fifo_info *fifo = &mac_control->fifos[i];
755 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
757 size = tx_cfg->fifo_len;
758 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
759 if (!fifo->ufo_in_band_v)
761 mem_allocated += (size * sizeof(u64));
764 /* Allocation and initialization of RXDs in Rings */
766 for (i = 0; i < config->rx_ring_num; i++) {
767 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
768 struct ring_info *ring = &mac_control->rings[i];
770 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
771 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
772 "multiple of RxDs per Block\n",
776 size += rx_cfg->num_rxd;
777 ring->block_count = rx_cfg->num_rxd /
778 (rxd_count[nic->rxd_mode] + 1);
779 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
781 if (nic->rxd_mode == RXD_MODE_1)
782 size = (size * (sizeof(struct RxD1)));
784 size = (size * (sizeof(struct RxD3)));
786 for (i = 0; i < config->rx_ring_num; i++) {
787 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
788 struct ring_info *ring = &mac_control->rings[i];
790 ring->rx_curr_get_info.block_index = 0;
791 ring->rx_curr_get_info.offset = 0;
792 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->rx_curr_put_info.block_index = 0;
794 ring->rx_curr_put_info.offset = 0;
795 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
798 ring->lro = lro_enable;
800 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
801 /* Allocating all the Rx blocks */
802 for (j = 0; j < blk_cnt; j++) {
803 struct rx_block_info *rx_blocks;
806 rx_blocks = &ring->rx_blocks[j];
807 size = SIZE_OF_BLOCK; /* size is always page size */
808 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
810 if (tmp_v_addr == NULL) {
812 * In case of failure, free_shared_mem()
813 * is called, which should free any
814 * memory that was alloced till the
817 rx_blocks->block_virt_addr = tmp_v_addr;
820 mem_allocated += size;
821 memset(tmp_v_addr, 0, size);
823 size = sizeof(struct rxd_info) *
824 rxd_count[nic->rxd_mode];
825 rx_blocks->block_virt_addr = tmp_v_addr;
826 rx_blocks->block_dma_addr = tmp_p_addr;
827 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
828 if (!rx_blocks->rxds)
830 mem_allocated += size;
831 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
832 rx_blocks->rxds[l].virt_addr =
833 rx_blocks->block_virt_addr +
834 (rxd_size[nic->rxd_mode] * l);
835 rx_blocks->rxds[l].dma_addr =
836 rx_blocks->block_dma_addr +
837 (rxd_size[nic->rxd_mode] * l);
840 /* Interlinking all Rx Blocks */
841 for (j = 0; j < blk_cnt; j++) {
842 int next = (j + 1) % blk_cnt;
843 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
844 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
845 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
846 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
848 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
849 pre_rxd_blk->reserved_2_pNext_RxD_block =
850 (unsigned long)tmp_v_addr_next;
851 pre_rxd_blk->pNext_RxD_Blk_physical =
852 (u64)tmp_p_addr_next;
855 if (nic->rxd_mode == RXD_MODE_3B) {
857 * Allocation of Storages for buffer addresses in 2BUFF mode
858 * and the buffers as well.
860 for (i = 0; i < config->rx_ring_num; i++) {
861 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
862 struct ring_info *ring = &mac_control->rings[i];
864 blk_cnt = rx_cfg->num_rxd /
865 (rxd_count[nic->rxd_mode] + 1);
866 size = sizeof(struct buffAdd *) * blk_cnt;
867 ring->ba = kmalloc(size, GFP_KERNEL);
870 mem_allocated += size;
871 for (j = 0; j < blk_cnt; j++) {
874 size = sizeof(struct buffAdd) *
875 (rxd_count[nic->rxd_mode] + 1);
876 ring->ba[j] = kmalloc(size, GFP_KERNEL);
879 mem_allocated += size;
880 while (k != rxd_count[nic->rxd_mode]) {
881 ba = &ring->ba[j][k];
882 size = BUF0_LEN + ALIGN_SIZE;
883 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
886 mem_allocated += size;
887 tmp = (unsigned long)ba->ba_0_org;
889 tmp &= ~((unsigned long)ALIGN_SIZE);
890 ba->ba_0 = (void *)tmp;
892 size = BUF1_LEN + ALIGN_SIZE;
893 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
896 mem_allocated += size;
897 tmp = (unsigned long)ba->ba_1_org;
899 tmp &= ~((unsigned long)ALIGN_SIZE);
900 ba->ba_1 = (void *)tmp;
907 /* Allocation and initialization of Statistics block */
908 size = sizeof(struct stat_block);
909 mac_control->stats_mem =
910 pci_alloc_consistent(nic->pdev, size,
911 &mac_control->stats_mem_phy);
913 if (!mac_control->stats_mem) {
915 * In case of failure, free_shared_mem() is called, which
916 * should free any memory that was alloced till the
921 mem_allocated += size;
922 mac_control->stats_mem_sz = size;
924 tmp_v_addr = mac_control->stats_mem;
925 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
926 memset(tmp_v_addr, 0, size);
927 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
928 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
929 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
934 * free_shared_mem - Free the allocated Memory
935 * @nic: Device private variable.
936 * Description: This function is to free all memory locations allocated by
937 * the init_shared_mem() function and return it to the kernel.
940 static void free_shared_mem(struct s2io_nic *nic)
942 int i, j, blk_cnt, size;
944 dma_addr_t tmp_p_addr;
945 int lst_size, lst_per_page;
946 struct net_device *dev;
948 struct config_param *config;
949 struct mac_info *mac_control;
950 struct stat_block *stats;
951 struct swStat *swstats;
958 config = &nic->config;
959 mac_control = &nic->mac_control;
960 stats = mac_control->stats_info;
961 swstats = &stats->sw_stat;
963 lst_size = sizeof(struct TxD) * config->max_txds;
964 lst_per_page = PAGE_SIZE / lst_size;
966 for (i = 0; i < config->tx_fifo_num; i++) {
967 struct fifo_info *fifo = &mac_control->fifos[i];
968 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
970 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
971 for (j = 0; j < page_num; j++) {
972 int mem_blks = (j * lst_per_page);
973 struct list_info_hold *fli;
975 if (!fifo->list_info)
978 fli = &fifo->list_info[mem_blks];
979 if (!fli->list_virt_addr)
981 pci_free_consistent(nic->pdev, PAGE_SIZE,
984 swstats->mem_freed += PAGE_SIZE;
986 /* If we got a zero DMA address during allocation,
989 if (mac_control->zerodma_virt_addr) {
990 pci_free_consistent(nic->pdev, PAGE_SIZE,
991 mac_control->zerodma_virt_addr,
994 "%s: Freeing TxDL with zero DMA address. "
995 "Virtual address %p\n",
996 dev->name, mac_control->zerodma_virt_addr);
997 swstats->mem_freed += PAGE_SIZE;
999 kfree(fifo->list_info);
1000 swstats->mem_freed += tx_cfg->fifo_len *
1001 sizeof(struct list_info_hold);
1004 size = SIZE_OF_BLOCK;
1005 for (i = 0; i < config->rx_ring_num; i++) {
1006 struct ring_info *ring = &mac_control->rings[i];
1008 blk_cnt = ring->block_count;
1009 for (j = 0; j < blk_cnt; j++) {
1010 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1011 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1012 if (tmp_v_addr == NULL)
1014 pci_free_consistent(nic->pdev, size,
1015 tmp_v_addr, tmp_p_addr);
1016 swstats->mem_freed += size;
1017 kfree(ring->rx_blocks[j].rxds);
1018 swstats->mem_freed += sizeof(struct rxd_info) *
1019 rxd_count[nic->rxd_mode];
1023 if (nic->rxd_mode == RXD_MODE_3B) {
1024 /* Freeing buffer storage addresses in 2BUFF mode. */
1025 for (i = 0; i < config->rx_ring_num; i++) {
1026 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1027 struct ring_info *ring = &mac_control->rings[i];
1029 blk_cnt = rx_cfg->num_rxd /
1030 (rxd_count[nic->rxd_mode] + 1);
1031 for (j = 0; j < blk_cnt; j++) {
1035 while (k != rxd_count[nic->rxd_mode]) {
1036 struct buffAdd *ba = &ring->ba[j][k];
1037 kfree(ba->ba_0_org);
1038 swstats->mem_freed +=
1039 BUF0_LEN + ALIGN_SIZE;
1040 kfree(ba->ba_1_org);
1041 swstats->mem_freed +=
1042 BUF1_LEN + ALIGN_SIZE;
1046 swstats->mem_freed += sizeof(struct buffAdd) *
1047 (rxd_count[nic->rxd_mode] + 1);
1050 swstats->mem_freed += sizeof(struct buffAdd *) *
1055 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1056 struct fifo_info *fifo = &mac_control->fifos[i];
1057 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1059 if (fifo->ufo_in_band_v) {
1060 swstats->mem_freed += tx_cfg->fifo_len *
1062 kfree(fifo->ufo_in_band_v);
1066 if (mac_control->stats_mem) {
1067 swstats->mem_freed += mac_control->stats_mem_sz;
1068 pci_free_consistent(nic->pdev,
1069 mac_control->stats_mem_sz,
1070 mac_control->stats_mem,
1071 mac_control->stats_mem_phy);
1076 * s2io_verify_pci_mode -
1079 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1081 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1082 register u64 val64 = 0;
1085 val64 = readq(&bar0->pci_mode);
1086 mode = (u8)GET_PCI_MODE(val64);
1088 if (val64 & PCI_MODE_UNKNOWN_MODE)
1089 return -1; /* Unknown PCI mode */
1093 #define NEC_VENID 0x1033
1094 #define NEC_DEVID 0x0125
1095 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1097 struct pci_dev *tdev = NULL;
1098 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1099 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1100 if (tdev->bus == s2io_pdev->bus->parent) {
1109 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1111 * s2io_print_pci_mode -
1113 static int s2io_print_pci_mode(struct s2io_nic *nic)
1115 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1116 register u64 val64 = 0;
1118 struct config_param *config = &nic->config;
1119 const char *pcimode;
1121 val64 = readq(&bar0->pci_mode);
1122 mode = (u8)GET_PCI_MODE(val64);
1124 if (val64 & PCI_MODE_UNKNOWN_MODE)
1125 return -1; /* Unknown PCI mode */
1127 config->bus_speed = bus_speed[mode];
1129 if (s2io_on_nec_bridge(nic->pdev)) {
1130 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1136 case PCI_MODE_PCI_33:
1137 pcimode = "33MHz PCI bus";
1139 case PCI_MODE_PCI_66:
1140 pcimode = "66MHz PCI bus";
1142 case PCI_MODE_PCIX_M1_66:
1143 pcimode = "66MHz PCIX(M1) bus";
1145 case PCI_MODE_PCIX_M1_100:
1146 pcimode = "100MHz PCIX(M1) bus";
1148 case PCI_MODE_PCIX_M1_133:
1149 pcimode = "133MHz PCIX(M1) bus";
1151 case PCI_MODE_PCIX_M2_66:
1152 pcimode = "133MHz PCIX(M2) bus";
1154 case PCI_MODE_PCIX_M2_100:
1155 pcimode = "200MHz PCIX(M2) bus";
1157 case PCI_MODE_PCIX_M2_133:
1158 pcimode = "266MHz PCIX(M2) bus";
1161 pcimode = "unsupported bus!";
1165 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1166 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1172 * init_tti - Initialization transmit traffic interrupt scheme
1173 * @nic: device private variable
1174 * @link: link status (UP/DOWN) used to enable/disable continuous
1175 * transmit interrupts
1176 * Description: The function configures transmit traffic interrupts
1177 * Return Value: SUCCESS on success and
1181 static int init_tti(struct s2io_nic *nic, int link)
1183 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1184 register u64 val64 = 0;
1186 struct config_param *config = &nic->config;
1188 for (i = 0; i < config->tx_fifo_num; i++) {
1190 * TTI Initialization. Default Tx timer gets us about
1191 * 250 interrupts per sec. Continuous interrupts are enabled
1194 if (nic->device_type == XFRAME_II_DEVICE) {
1195 int count = (nic->config.bus_speed * 125)/2;
1196 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1198 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1200 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1201 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1202 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1203 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1205 if (use_continuous_tx_intrs && (link == LINK_UP))
1206 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1207 writeq(val64, &bar0->tti_data1_mem);
1209 if (nic->config.intr_type == MSI_X) {
1210 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1211 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1212 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1213 TTI_DATA2_MEM_TX_UFC_D(0x300);
1215 if ((nic->config.tx_steering_type ==
1216 TX_DEFAULT_STEERING) &&
1217 (config->tx_fifo_num > 1) &&
1218 (i >= nic->udp_fifo_idx) &&
1219 (i < (nic->udp_fifo_idx +
1220 nic->total_udp_fifos)))
1221 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1222 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1223 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1224 TTI_DATA2_MEM_TX_UFC_D(0x120);
1226 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1227 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1228 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1229 TTI_DATA2_MEM_TX_UFC_D(0x80);
1232 writeq(val64, &bar0->tti_data2_mem);
1234 val64 = TTI_CMD_MEM_WE |
1235 TTI_CMD_MEM_STROBE_NEW_CMD |
1236 TTI_CMD_MEM_OFFSET(i);
1237 writeq(val64, &bar0->tti_command_mem);
1239 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1240 TTI_CMD_MEM_STROBE_NEW_CMD,
1241 S2IO_BIT_RESET) != SUCCESS)
1249 * init_nic - Initialization of hardware
1250 * @nic: device private variable
1251 * Description: The function sequentially configures every block
1252 * of the H/W from their reset values.
1253 * Return Value: SUCCESS on success and
1254 * '-1' on failure (endian settings incorrect).
1257 static int init_nic(struct s2io_nic *nic)
1259 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1260 struct net_device *dev = nic->dev;
1261 register u64 val64 = 0;
1266 unsigned long long mem_share;
1268 struct config_param *config = &nic->config;
1269 struct mac_info *mac_control = &nic->mac_control;
1271 /* to set the swapper controle on the card */
1272 if (s2io_set_swapper(nic)) {
1273 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1278 * Herc requires EOI to be removed from reset before XGXS, so..
1280 if (nic->device_type & XFRAME_II_DEVICE) {
1281 val64 = 0xA500000000ULL;
1282 writeq(val64, &bar0->sw_reset);
1284 val64 = readq(&bar0->sw_reset);
1287 /* Remove XGXS from reset state */
1289 writeq(val64, &bar0->sw_reset);
1291 val64 = readq(&bar0->sw_reset);
1293 /* Ensure that it's safe to access registers by checking
1294 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1296 if (nic->device_type == XFRAME_II_DEVICE) {
1297 for (i = 0; i < 50; i++) {
1298 val64 = readq(&bar0->adapter_status);
1299 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1307 /* Enable Receiving broadcasts */
1308 add = &bar0->mac_cfg;
1309 val64 = readq(&bar0->mac_cfg);
1310 val64 |= MAC_RMAC_BCAST_ENABLE;
1311 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1312 writel((u32)val64, add);
1313 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1314 writel((u32) (val64 >> 32), (add + 4));
1316 /* Read registers in all blocks */
1317 val64 = readq(&bar0->mac_int_mask);
1318 val64 = readq(&bar0->mc_int_mask);
1319 val64 = readq(&bar0->xgxs_int_mask);
1323 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1325 if (nic->device_type & XFRAME_II_DEVICE) {
1326 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1327 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1328 &bar0->dtx_control, UF);
1330 msleep(1); /* Necessary!! */
1334 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1335 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1336 &bar0->dtx_control, UF);
1337 val64 = readq(&bar0->dtx_control);
1342 /* Tx DMA Initialization */
1344 writeq(val64, &bar0->tx_fifo_partition_0);
1345 writeq(val64, &bar0->tx_fifo_partition_1);
1346 writeq(val64, &bar0->tx_fifo_partition_2);
1347 writeq(val64, &bar0->tx_fifo_partition_3);
1349 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1350 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1352 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1353 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1355 if (i == (config->tx_fifo_num - 1)) {
1362 writeq(val64, &bar0->tx_fifo_partition_0);
1367 writeq(val64, &bar0->tx_fifo_partition_1);
1372 writeq(val64, &bar0->tx_fifo_partition_2);
1377 writeq(val64, &bar0->tx_fifo_partition_3);
1388 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1389 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1391 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1392 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1394 val64 = readq(&bar0->tx_fifo_partition_0);
1395 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1396 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1399 * Initialization of Tx_PA_CONFIG register to ignore packet
1400 * integrity checking.
1402 val64 = readq(&bar0->tx_pa_cfg);
1403 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1404 TX_PA_CFG_IGNORE_SNAP_OUI |
1405 TX_PA_CFG_IGNORE_LLC_CTRL |
1406 TX_PA_CFG_IGNORE_L2_ERR;
1407 writeq(val64, &bar0->tx_pa_cfg);
1409 /* Rx DMA intialization. */
1411 for (i = 0; i < config->rx_ring_num; i++) {
1412 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1414 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1416 writeq(val64, &bar0->rx_queue_priority);
1419 * Allocating equal share of memory to all the
1423 if (nic->device_type & XFRAME_II_DEVICE)
1428 for (i = 0; i < config->rx_ring_num; i++) {
1431 mem_share = (mem_size / config->rx_ring_num +
1432 mem_size % config->rx_ring_num);
1433 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1436 mem_share = (mem_size / config->rx_ring_num);
1437 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1440 mem_share = (mem_size / config->rx_ring_num);
1441 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1444 mem_share = (mem_size / config->rx_ring_num);
1445 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1448 mem_share = (mem_size / config->rx_ring_num);
1449 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1452 mem_share = (mem_size / config->rx_ring_num);
1453 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1456 mem_share = (mem_size / config->rx_ring_num);
1457 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1460 mem_share = (mem_size / config->rx_ring_num);
1461 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1465 writeq(val64, &bar0->rx_queue_cfg);
1468 * Filling Tx round robin registers
1469 * as per the number of FIFOs for equal scheduling priority
1471 switch (config->tx_fifo_num) {
1474 writeq(val64, &bar0->tx_w_round_robin_0);
1475 writeq(val64, &bar0->tx_w_round_robin_1);
1476 writeq(val64, &bar0->tx_w_round_robin_2);
1477 writeq(val64, &bar0->tx_w_round_robin_3);
1478 writeq(val64, &bar0->tx_w_round_robin_4);
1481 val64 = 0x0001000100010001ULL;
1482 writeq(val64, &bar0->tx_w_round_robin_0);
1483 writeq(val64, &bar0->tx_w_round_robin_1);
1484 writeq(val64, &bar0->tx_w_round_robin_2);
1485 writeq(val64, &bar0->tx_w_round_robin_3);
1486 val64 = 0x0001000100000000ULL;
1487 writeq(val64, &bar0->tx_w_round_robin_4);
1490 val64 = 0x0001020001020001ULL;
1491 writeq(val64, &bar0->tx_w_round_robin_0);
1492 val64 = 0x0200010200010200ULL;
1493 writeq(val64, &bar0->tx_w_round_robin_1);
1494 val64 = 0x0102000102000102ULL;
1495 writeq(val64, &bar0->tx_w_round_robin_2);
1496 val64 = 0x0001020001020001ULL;
1497 writeq(val64, &bar0->tx_w_round_robin_3);
1498 val64 = 0x0200010200000000ULL;
1499 writeq(val64, &bar0->tx_w_round_robin_4);
1502 val64 = 0x0001020300010203ULL;
1503 writeq(val64, &bar0->tx_w_round_robin_0);
1504 writeq(val64, &bar0->tx_w_round_robin_1);
1505 writeq(val64, &bar0->tx_w_round_robin_2);
1506 writeq(val64, &bar0->tx_w_round_robin_3);
1507 val64 = 0x0001020300000000ULL;
1508 writeq(val64, &bar0->tx_w_round_robin_4);
1511 val64 = 0x0001020304000102ULL;
1512 writeq(val64, &bar0->tx_w_round_robin_0);
1513 val64 = 0x0304000102030400ULL;
1514 writeq(val64, &bar0->tx_w_round_robin_1);
1515 val64 = 0x0102030400010203ULL;
1516 writeq(val64, &bar0->tx_w_round_robin_2);
1517 val64 = 0x0400010203040001ULL;
1518 writeq(val64, &bar0->tx_w_round_robin_3);
1519 val64 = 0x0203040000000000ULL;
1520 writeq(val64, &bar0->tx_w_round_robin_4);
1523 val64 = 0x0001020304050001ULL;
1524 writeq(val64, &bar0->tx_w_round_robin_0);
1525 val64 = 0x0203040500010203ULL;
1526 writeq(val64, &bar0->tx_w_round_robin_1);
1527 val64 = 0x0405000102030405ULL;
1528 writeq(val64, &bar0->tx_w_round_robin_2);
1529 val64 = 0x0001020304050001ULL;
1530 writeq(val64, &bar0->tx_w_round_robin_3);
1531 val64 = 0x0203040500000000ULL;
1532 writeq(val64, &bar0->tx_w_round_robin_4);
1535 val64 = 0x0001020304050600ULL;
1536 writeq(val64, &bar0->tx_w_round_robin_0);
1537 val64 = 0x0102030405060001ULL;
1538 writeq(val64, &bar0->tx_w_round_robin_1);
1539 val64 = 0x0203040506000102ULL;
1540 writeq(val64, &bar0->tx_w_round_robin_2);
1541 val64 = 0x0304050600010203ULL;
1542 writeq(val64, &bar0->tx_w_round_robin_3);
1543 val64 = 0x0405060000000000ULL;
1544 writeq(val64, &bar0->tx_w_round_robin_4);
1547 val64 = 0x0001020304050607ULL;
1548 writeq(val64, &bar0->tx_w_round_robin_0);
1549 writeq(val64, &bar0->tx_w_round_robin_1);
1550 writeq(val64, &bar0->tx_w_round_robin_2);
1551 writeq(val64, &bar0->tx_w_round_robin_3);
1552 val64 = 0x0001020300000000ULL;
1553 writeq(val64, &bar0->tx_w_round_robin_4);
1557 /* Enable all configured Tx FIFO partitions */
1558 val64 = readq(&bar0->tx_fifo_partition_0);
1559 val64 |= (TX_FIFO_PARTITION_EN);
1560 writeq(val64, &bar0->tx_fifo_partition_0);
1562 /* Filling the Rx round robin registers as per the
1563 * number of Rings and steering based on QoS with
1566 switch (config->rx_ring_num) {
1569 writeq(val64, &bar0->rx_w_round_robin_0);
1570 writeq(val64, &bar0->rx_w_round_robin_1);
1571 writeq(val64, &bar0->rx_w_round_robin_2);
1572 writeq(val64, &bar0->rx_w_round_robin_3);
1573 writeq(val64, &bar0->rx_w_round_robin_4);
1575 val64 = 0x8080808080808080ULL;
1576 writeq(val64, &bar0->rts_qos_steering);
1579 val64 = 0x0001000100010001ULL;
1580 writeq(val64, &bar0->rx_w_round_robin_0);
1581 writeq(val64, &bar0->rx_w_round_robin_1);
1582 writeq(val64, &bar0->rx_w_round_robin_2);
1583 writeq(val64, &bar0->rx_w_round_robin_3);
1584 val64 = 0x0001000100000000ULL;
1585 writeq(val64, &bar0->rx_w_round_robin_4);
1587 val64 = 0x8080808040404040ULL;
1588 writeq(val64, &bar0->rts_qos_steering);
1591 val64 = 0x0001020001020001ULL;
1592 writeq(val64, &bar0->rx_w_round_robin_0);
1593 val64 = 0x0200010200010200ULL;
1594 writeq(val64, &bar0->rx_w_round_robin_1);
1595 val64 = 0x0102000102000102ULL;
1596 writeq(val64, &bar0->rx_w_round_robin_2);
1597 val64 = 0x0001020001020001ULL;
1598 writeq(val64, &bar0->rx_w_round_robin_3);
1599 val64 = 0x0200010200000000ULL;
1600 writeq(val64, &bar0->rx_w_round_robin_4);
1602 val64 = 0x8080804040402020ULL;
1603 writeq(val64, &bar0->rts_qos_steering);
1606 val64 = 0x0001020300010203ULL;
1607 writeq(val64, &bar0->rx_w_round_robin_0);
1608 writeq(val64, &bar0->rx_w_round_robin_1);
1609 writeq(val64, &bar0->rx_w_round_robin_2);
1610 writeq(val64, &bar0->rx_w_round_robin_3);
1611 val64 = 0x0001020300000000ULL;
1612 writeq(val64, &bar0->rx_w_round_robin_4);
1614 val64 = 0x8080404020201010ULL;
1615 writeq(val64, &bar0->rts_qos_steering);
1618 val64 = 0x0001020304000102ULL;
1619 writeq(val64, &bar0->rx_w_round_robin_0);
1620 val64 = 0x0304000102030400ULL;
1621 writeq(val64, &bar0->rx_w_round_robin_1);
1622 val64 = 0x0102030400010203ULL;
1623 writeq(val64, &bar0->rx_w_round_robin_2);
1624 val64 = 0x0400010203040001ULL;
1625 writeq(val64, &bar0->rx_w_round_robin_3);
1626 val64 = 0x0203040000000000ULL;
1627 writeq(val64, &bar0->rx_w_round_robin_4);
1629 val64 = 0x8080404020201008ULL;
1630 writeq(val64, &bar0->rts_qos_steering);
1633 val64 = 0x0001020304050001ULL;
1634 writeq(val64, &bar0->rx_w_round_robin_0);
1635 val64 = 0x0203040500010203ULL;
1636 writeq(val64, &bar0->rx_w_round_robin_1);
1637 val64 = 0x0405000102030405ULL;
1638 writeq(val64, &bar0->rx_w_round_robin_2);
1639 val64 = 0x0001020304050001ULL;
1640 writeq(val64, &bar0->rx_w_round_robin_3);
1641 val64 = 0x0203040500000000ULL;
1642 writeq(val64, &bar0->rx_w_round_robin_4);
1644 val64 = 0x8080404020100804ULL;
1645 writeq(val64, &bar0->rts_qos_steering);
1648 val64 = 0x0001020304050600ULL;
1649 writeq(val64, &bar0->rx_w_round_robin_0);
1650 val64 = 0x0102030405060001ULL;
1651 writeq(val64, &bar0->rx_w_round_robin_1);
1652 val64 = 0x0203040506000102ULL;
1653 writeq(val64, &bar0->rx_w_round_robin_2);
1654 val64 = 0x0304050600010203ULL;
1655 writeq(val64, &bar0->rx_w_round_robin_3);
1656 val64 = 0x0405060000000000ULL;
1657 writeq(val64, &bar0->rx_w_round_robin_4);
1659 val64 = 0x8080402010080402ULL;
1660 writeq(val64, &bar0->rts_qos_steering);
1663 val64 = 0x0001020304050607ULL;
1664 writeq(val64, &bar0->rx_w_round_robin_0);
1665 writeq(val64, &bar0->rx_w_round_robin_1);
1666 writeq(val64, &bar0->rx_w_round_robin_2);
1667 writeq(val64, &bar0->rx_w_round_robin_3);
1668 val64 = 0x0001020300000000ULL;
1669 writeq(val64, &bar0->rx_w_round_robin_4);
1671 val64 = 0x8040201008040201ULL;
1672 writeq(val64, &bar0->rts_qos_steering);
1678 for (i = 0; i < 8; i++)
1679 writeq(val64, &bar0->rts_frm_len_n[i]);
1681 /* Set the default rts frame length for the rings configured */
1682 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1683 for (i = 0 ; i < config->rx_ring_num ; i++)
1684 writeq(val64, &bar0->rts_frm_len_n[i]);
1686 /* Set the frame length for the configured rings
1687 * desired by the user
1689 for (i = 0; i < config->rx_ring_num; i++) {
1690 /* If rts_frm_len[i] == 0 then it is assumed that user not
1691 * specified frame length steering.
1692 * If the user provides the frame length then program
1693 * the rts_frm_len register for those values or else
1694 * leave it as it is.
1696 if (rts_frm_len[i] != 0) {
1697 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1698 &bar0->rts_frm_len_n[i]);
1702 /* Disable differentiated services steering logic */
1703 for (i = 0; i < 64; i++) {
1704 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1706 "%s: rts_ds_steer failed on codepoint %d\n",
1712 /* Program statistics memory */
1713 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1715 if (nic->device_type == XFRAME_II_DEVICE) {
1716 val64 = STAT_BC(0x320);
1717 writeq(val64, &bar0->stat_byte_cnt);
1721 * Initializing the sampling rate for the device to calculate the
1722 * bandwidth utilization.
1724 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1725 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1726 writeq(val64, &bar0->mac_link_util);
1729 * Initializing the Transmit and Receive Traffic Interrupt
1733 /* Initialize TTI */
1734 if (SUCCESS != init_tti(nic, nic->last_link_state))
1737 /* RTI Initialization */
1738 if (nic->device_type == XFRAME_II_DEVICE) {
1740 * Programmed to generate Apprx 500 Intrs per
1743 int count = (nic->config.bus_speed * 125)/4;
1744 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1746 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1747 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1748 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1749 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1750 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1752 writeq(val64, &bar0->rti_data1_mem);
1754 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1755 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1756 if (nic->config.intr_type == MSI_X)
1757 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1758 RTI_DATA2_MEM_RX_UFC_D(0x40));
1760 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1761 RTI_DATA2_MEM_RX_UFC_D(0x80));
1762 writeq(val64, &bar0->rti_data2_mem);
1764 for (i = 0; i < config->rx_ring_num; i++) {
1765 val64 = RTI_CMD_MEM_WE |
1766 RTI_CMD_MEM_STROBE_NEW_CMD |
1767 RTI_CMD_MEM_OFFSET(i);
1768 writeq(val64, &bar0->rti_command_mem);
1771 * Once the operation completes, the Strobe bit of the
1772 * command register will be reset. We poll for this
1773 * particular condition. We wait for a maximum of 500ms
1774 * for the operation to complete, if it's not complete
1775 * by then we return error.
1779 val64 = readq(&bar0->rti_command_mem);
1780 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1784 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1794 * Initializing proper values as Pause threshold into all
1795 * the 8 Queues on Rx side.
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1798 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1800 /* Disable RMAC PAD STRIPPING */
1801 add = &bar0->mac_cfg;
1802 val64 = readq(&bar0->mac_cfg);
1803 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1804 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1805 writel((u32) (val64), add);
1806 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807 writel((u32) (val64 >> 32), (add + 4));
1808 val64 = readq(&bar0->mac_cfg);
1810 /* Enable FCS stripping by adapter */
1811 add = &bar0->mac_cfg;
1812 val64 = readq(&bar0->mac_cfg);
1813 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1814 if (nic->device_type == XFRAME_II_DEVICE)
1815 writeq(val64, &bar0->mac_cfg);
1817 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1818 writel((u32) (val64), add);
1819 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1820 writel((u32) (val64 >> 32), (add + 4));
1824 * Set the time value to be inserted in the pause frame
1825 * generated by xena.
1827 val64 = readq(&bar0->rmac_pause_cfg);
1828 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1829 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1830 writeq(val64, &bar0->rmac_pause_cfg);
1833 * Set the Threshold Limit for Generating the pause frame
1834 * If the amount of data in any Queue exceeds ratio of
1835 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1836 * pause frame is generated
1839 for (i = 0; i < 4; i++) {
1840 val64 |= (((u64)0xFF00 |
1841 nic->mac_control.mc_pause_threshold_q0q3)
1844 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1847 for (i = 0; i < 4; i++) {
1848 val64 |= (((u64)0xFF00 |
1849 nic->mac_control.mc_pause_threshold_q4q7)
1852 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1855 * TxDMA will stop Read request if the number of read split has
1856 * exceeded the limit pointed by shared_splits
1858 val64 = readq(&bar0->pic_control);
1859 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1860 writeq(val64, &bar0->pic_control);
1862 if (nic->config.bus_speed == 266) {
1863 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1864 writeq(0x0, &bar0->read_retry_delay);
1865 writeq(0x0, &bar0->write_retry_delay);
1869 * Programming the Herc to split every write transaction
1870 * that does not start on an ADB to reduce disconnects.
1872 if (nic->device_type == XFRAME_II_DEVICE) {
1873 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1874 MISC_LINK_STABILITY_PRD(3);
1875 writeq(val64, &bar0->misc_control);
1876 val64 = readq(&bar0->pic_control2);
1877 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1878 writeq(val64, &bar0->pic_control2);
1880 if (strstr(nic->product_name, "CX4")) {
1881 val64 = TMAC_AVG_IPG(0x17);
1882 writeq(val64, &bar0->tmac_avg_ipg);
1887 #define LINK_UP_DOWN_INTERRUPT 1
1888 #define MAC_RMAC_ERR_TIMER 2
1890 static int s2io_link_fault_indication(struct s2io_nic *nic)
1892 if (nic->device_type == XFRAME_II_DEVICE)
1893 return LINK_UP_DOWN_INTERRUPT;
1895 return MAC_RMAC_ERR_TIMER;
1899 * do_s2io_write_bits - update alarm bits in alarm register
1900 * @value: alarm bits
1901 * @flag: interrupt status
1902 * @addr: address value
1903 * Description: update alarm bits in alarm register
1907 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1911 temp64 = readq(addr);
1913 if (flag == ENABLE_INTRS)
1914 temp64 &= ~((u64)value);
1916 temp64 |= ((u64)value);
1917 writeq(temp64, addr);
1920 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1922 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1923 register u64 gen_int_mask = 0;
1926 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1927 if (mask & TX_DMA_INTR) {
1928 gen_int_mask |= TXDMA_INT_M;
1930 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1931 TXDMA_PCC_INT | TXDMA_TTI_INT |
1932 TXDMA_LSO_INT | TXDMA_TPA_INT |
1933 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1935 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1936 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1937 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1938 &bar0->pfc_err_mask);
1940 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1941 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1942 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1944 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1945 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1946 PCC_N_SERR | PCC_6_COF_OV_ERR |
1947 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1948 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1950 flag, &bar0->pcc_err_mask);
1952 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1953 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1955 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1956 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1957 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1958 flag, &bar0->lso_err_mask);
1960 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1961 flag, &bar0->tpa_err_mask);
1963 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1966 if (mask & TX_MAC_INTR) {
1967 gen_int_mask |= TXMAC_INT_M;
1968 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1969 &bar0->mac_int_mask);
1970 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1971 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1972 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1973 flag, &bar0->mac_tmac_err_mask);
1976 if (mask & TX_XGXS_INTR) {
1977 gen_int_mask |= TXXGXS_INT_M;
1978 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1979 &bar0->xgxs_int_mask);
1980 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1981 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1982 flag, &bar0->xgxs_txgxs_err_mask);
1985 if (mask & RX_DMA_INTR) {
1986 gen_int_mask |= RXDMA_INT_M;
1987 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1988 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1989 flag, &bar0->rxdma_int_mask);
1990 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1991 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1992 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1993 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1994 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1995 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1996 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1997 &bar0->prc_pcix_err_mask);
1998 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1999 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2000 &bar0->rpa_err_mask);
2001 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
2002 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2003 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2004 RDA_FRM_ECC_SG_ERR |
2005 RDA_MISC_ERR|RDA_PCIX_ERR,
2006 flag, &bar0->rda_err_mask);
2007 do_s2io_write_bits(RTI_SM_ERR_ALARM |
2008 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2009 flag, &bar0->rti_err_mask);
2012 if (mask & RX_MAC_INTR) {
2013 gen_int_mask |= RXMAC_INT_M;
2014 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
2015 &bar0->mac_int_mask);
2016 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2017 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2018 RMAC_DOUBLE_ECC_ERR);
2019 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2020 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2021 do_s2io_write_bits(interruptible,
2022 flag, &bar0->mac_rmac_err_mask);
2025 if (mask & RX_XGXS_INTR) {
2026 gen_int_mask |= RXXGXS_INT_M;
2027 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
2028 &bar0->xgxs_int_mask);
2029 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
2030 &bar0->xgxs_rxgxs_err_mask);
2033 if (mask & MC_INTR) {
2034 gen_int_mask |= MC_INT_M;
2035 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2036 flag, &bar0->mc_int_mask);
2037 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
2038 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2039 &bar0->mc_err_mask);
2041 nic->general_int_mask = gen_int_mask;
2043 /* Remove this line when alarm interrupts are enabled */
2044 nic->general_int_mask = 0;
2048 * en_dis_able_nic_intrs - Enable or Disable the interrupts
2049 * @nic: device private variable,
2050 * @mask: A mask indicating which Intr block must be modified and,
2051 * @flag: A flag indicating whether to enable or disable the Intrs.
2052 * Description: This function will either disable or enable the interrupts
2053 * depending on the flag argument. The mask argument can be used to
2054 * enable/disable any Intr block.
2055 * Return Value: NONE.
2058 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2060 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2061 register u64 temp64 = 0, intr_mask = 0;
2063 intr_mask = nic->general_int_mask;
2065 /* Top level interrupt classification */
2066 /* PIC Interrupts */
2067 if (mask & TX_PIC_INTR) {
2068 /* Enable PIC Intrs in the general intr mask register */
2069 intr_mask |= TXPIC_INT_M;
2070 if (flag == ENABLE_INTRS) {
2072 * If Hercules adapter enable GPIO otherwise
2073 * disable all PCIX, Flash, MDIO, IIC and GPIO
2074 * interrupts for now.
2077 if (s2io_link_fault_indication(nic) ==
2078 LINK_UP_DOWN_INTERRUPT) {
2079 do_s2io_write_bits(PIC_INT_GPIO, flag,
2080 &bar0->pic_int_mask);
2081 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2082 &bar0->gpio_int_mask);
2084 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2085 } else if (flag == DISABLE_INTRS) {
2087 * Disable PIC Intrs in the general
2088 * intr mask register
2090 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2094 /* Tx traffic interrupts */
2095 if (mask & TX_TRAFFIC_INTR) {
2096 intr_mask |= TXTRAFFIC_INT_M;
2097 if (flag == ENABLE_INTRS) {
2099 * Enable all the Tx side interrupts
2100 * writing 0 Enables all 64 TX interrupt levels
2102 writeq(0x0, &bar0->tx_traffic_mask);
2103 } else if (flag == DISABLE_INTRS) {
2105 * Disable Tx Traffic Intrs in the general intr mask
2108 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2112 /* Rx traffic interrupts */
2113 if (mask & RX_TRAFFIC_INTR) {
2114 intr_mask |= RXTRAFFIC_INT_M;
2115 if (flag == ENABLE_INTRS) {
2116 /* writing 0 Enables all 8 RX interrupt levels */
2117 writeq(0x0, &bar0->rx_traffic_mask);
2118 } else if (flag == DISABLE_INTRS) {
2120 * Disable Rx Traffic Intrs in the general intr mask
2123 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2127 temp64 = readq(&bar0->general_int_mask);
2128 if (flag == ENABLE_INTRS)
2129 temp64 &= ~((u64)intr_mask);
2131 temp64 = DISABLE_ALL_INTRS;
2132 writeq(temp64, &bar0->general_int_mask);
2134 nic->general_int_mask = readq(&bar0->general_int_mask);
2138 * verify_pcc_quiescent- Checks for PCC quiescent state
2139 * Return: 1 If PCC is quiescence
2140 * 0 If PCC is not quiescence
2142 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2145 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2146 u64 val64 = readq(&bar0->adapter_status);
2148 herc = (sp->device_type == XFRAME_II_DEVICE);
2150 if (flag == false) {
2151 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2152 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2155 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2159 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2160 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2161 ADAPTER_STATUS_RMAC_PCC_IDLE))
2164 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2165 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2173 * verify_xena_quiescence - Checks whether the H/W is ready
2174 * Description: Returns whether the H/W is ready to go or not. Depending
2175 * on whether adapter enable bit was written or not the comparison
2176 * differs and the calling function passes the input argument flag to
2178 * Return: 1 If xena is quiescence
2179 * 0 If Xena is not quiescence
2182 static int verify_xena_quiescence(struct s2io_nic *sp)
2185 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2186 u64 val64 = readq(&bar0->adapter_status);
2187 mode = s2io_verify_pci_mode(sp);
2189 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2190 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2193 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2194 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2197 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2198 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2201 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2202 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2205 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2206 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2209 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2210 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2213 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2214 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2217 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2218 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2223 * In PCI 33 mode, the P_PLL is not used, and therefore,
2224 * the the P_PLL_LOCK bit in the adapter_status register will
2227 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2228 sp->device_type == XFRAME_II_DEVICE &&
2229 mode != PCI_MODE_PCI_33) {
2230 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2233 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2234 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2235 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2242 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2243 * @sp: Pointer to device specifc structure
2245 * New procedure to clear mac address reading problems on Alpha platforms
2249 static void fix_mac_address(struct s2io_nic *sp)
2251 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2255 while (fix_mac[i] != END_SIGN) {
2256 writeq(fix_mac[i++], &bar0->gpio_control);
2258 val64 = readq(&bar0->gpio_control);
2263 * start_nic - Turns the device on
2264 * @nic : device private variable.
2266 * This function actually turns the device on. Before this function is
2267 * called,all Registers are configured from their reset states
2268 * and shared memory is allocated but the NIC is still quiescent. On
2269 * calling this function, the device interrupts are cleared and the NIC is
2270 * literally switched on by writing into the adapter control register.
2272 * SUCCESS on success and -1 on failure.
2275 static int start_nic(struct s2io_nic *nic)
2277 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2278 struct net_device *dev = nic->dev;
2279 register u64 val64 = 0;
2281 struct config_param *config = &nic->config;
2282 struct mac_info *mac_control = &nic->mac_control;
2284 /* PRC Initialization and configuration */
2285 for (i = 0; i < config->rx_ring_num; i++) {
2286 struct ring_info *ring = &mac_control->rings[i];
2288 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2289 &bar0->prc_rxd0_n[i]);
2291 val64 = readq(&bar0->prc_ctrl_n[i]);
2292 if (nic->rxd_mode == RXD_MODE_1)
2293 val64 |= PRC_CTRL_RC_ENABLED;
2295 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2296 if (nic->device_type == XFRAME_II_DEVICE)
2297 val64 |= PRC_CTRL_GROUP_READS;
2298 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2299 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2300 writeq(val64, &bar0->prc_ctrl_n[i]);
2303 if (nic->rxd_mode == RXD_MODE_3B) {
2304 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2305 val64 = readq(&bar0->rx_pa_cfg);
2306 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2307 writeq(val64, &bar0->rx_pa_cfg);
2310 if (vlan_tag_strip == 0) {
2311 val64 = readq(&bar0->rx_pa_cfg);
2312 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2313 writeq(val64, &bar0->rx_pa_cfg);
2314 nic->vlan_strip_flag = 0;
2318 * Enabling MC-RLDRAM. After enabling the device, we timeout
2319 * for around 100ms, which is approximately the time required
2320 * for the device to be ready for operation.
2322 val64 = readq(&bar0->mc_rldram_mrs);
2323 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2324 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2325 val64 = readq(&bar0->mc_rldram_mrs);
2327 msleep(100); /* Delay by around 100 ms. */
2329 /* Enabling ECC Protection. */
2330 val64 = readq(&bar0->adapter_control);
2331 val64 &= ~ADAPTER_ECC_EN;
2332 writeq(val64, &bar0->adapter_control);
2335 * Verify if the device is ready to be enabled, if so enable
2338 val64 = readq(&bar0->adapter_status);
2339 if (!verify_xena_quiescence(nic)) {
2340 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2341 "Adapter status reads: 0x%llx\n",
2342 dev->name, (unsigned long long)val64);
2347 * With some switches, link might be already up at this point.
2348 * Because of this weird behavior, when we enable laser,
2349 * we may not get link. We need to handle this. We cannot
2350 * figure out which switch is misbehaving. So we are forced to
2351 * make a global change.
2354 /* Enabling Laser. */
2355 val64 = readq(&bar0->adapter_control);
2356 val64 |= ADAPTER_EOI_TX_ON;
2357 writeq(val64, &bar0->adapter_control);
2359 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2361 * Dont see link state interrupts initally on some switches,
2362 * so directly scheduling the link state task here.
2364 schedule_work(&nic->set_link_task);
2366 /* SXE-002: Initialize link and activity LED */
2367 subid = nic->pdev->subsystem_device;
2368 if (((subid & 0xFF) >= 0x07) &&
2369 (nic->device_type == XFRAME_I_DEVICE)) {
2370 val64 = readq(&bar0->gpio_control);
2371 val64 |= 0x0000800000000000ULL;
2372 writeq(val64, &bar0->gpio_control);
2373 val64 = 0x0411040400000000ULL;
2374 writeq(val64, (void __iomem *)bar0 + 0x2700);
2380 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2382 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2383 struct TxD *txdlp, int get_off)
2385 struct s2io_nic *nic = fifo_data->nic;
2386 struct sk_buff *skb;
2391 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2392 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2393 sizeof(u64), PCI_DMA_TODEVICE);
2397 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2399 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2402 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2403 skb_headlen(skb), PCI_DMA_TODEVICE);
2404 frg_cnt = skb_shinfo(skb)->nr_frags;
2407 for (j = 0; j < frg_cnt; j++, txds++) {
2408 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2409 if (!txds->Buffer_Pointer)
2411 pci_unmap_page(nic->pdev,
2412 (dma_addr_t)txds->Buffer_Pointer,
2413 frag->size, PCI_DMA_TODEVICE);
2416 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2421 * free_tx_buffers - Free all queued Tx buffers
2422 * @nic : device private variable.
2424 * Free all queued Tx buffers.
2425 * Return Value: void
2428 static void free_tx_buffers(struct s2io_nic *nic)
2430 struct net_device *dev = nic->dev;
2431 struct sk_buff *skb;
2435 struct config_param *config = &nic->config;
2436 struct mac_info *mac_control = &nic->mac_control;
2437 struct stat_block *stats = mac_control->stats_info;
2438 struct swStat *swstats = &stats->sw_stat;
2440 for (i = 0; i < config->tx_fifo_num; i++) {
2441 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2442 struct fifo_info *fifo = &mac_control->fifos[i];
2443 unsigned long flags;
2445 spin_lock_irqsave(&fifo->tx_lock, flags);
2446 for (j = 0; j < tx_cfg->fifo_len; j++) {
2447 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
2448 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2450 swstats->mem_freed += skb->truesize;
2456 "%s: forcibly freeing %d skbs on FIFO%d\n",
2458 fifo->tx_curr_get_info.offset = 0;
2459 fifo->tx_curr_put_info.offset = 0;
2460 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2465 * stop_nic - To stop the nic
2466 * @nic ; device private variable.
2468 * This function does exactly the opposite of what the start_nic()
2469 * function does. This function is called to stop the device.
2474 static void stop_nic(struct s2io_nic *nic)
2476 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2477 register u64 val64 = 0;
2480 /* Disable all interrupts */
2481 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2482 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2483 interruptible |= TX_PIC_INTR;
2484 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2486 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2487 val64 = readq(&bar0->adapter_control);
2488 val64 &= ~(ADAPTER_CNTL_EN);
2489 writeq(val64, &bar0->adapter_control);
2493 * fill_rx_buffers - Allocates the Rx side skbs
2494 * @ring_info: per ring structure
2495 * @from_card_up: If this is true, we will map the buffer to get
2496 * the dma address for buf0 and buf1 to give it to the card.
2497 * Else we will sync the already mapped buffer to give it to the card.
2499 * The function allocates Rx side skbs and puts the physical
2500 * address of these buffers into the RxD buffer pointers, so that the NIC
2501 * can DMA the received frame into these locations.
2502 * The NIC supports 3 receive modes, viz
2504 * 2. three buffer and
2505 * 3. Five buffer modes.
2506 * Each mode defines how many fragments the received frame will be split
2507 * up into by the NIC. The frame is split into L3 header, L4 Header,
2508 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2509 * is split into 3 fragments. As of now only single buffer mode is
2512 * SUCCESS on success or an appropriate -ve value on failure.
2514 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2517 struct sk_buff *skb;
2519 int off, size, block_no, block_no1;
2524 struct RxD_t *first_rxdp = NULL;
2525 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2529 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2531 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2533 block_no1 = ring->rx_curr_get_info.block_index;
2534 while (alloc_tab < alloc_cnt) {
2535 block_no = ring->rx_curr_put_info.block_index;
2537 off = ring->rx_curr_put_info.offset;
2539 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2541 rxd_index = off + 1;
2543 rxd_index += (block_no * ring->rxd_count);
2545 if ((block_no == block_no1) &&
2546 (off == ring->rx_curr_get_info.offset) &&
2547 (rxdp->Host_Control)) {
2548 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2552 if (off && (off == ring->rxd_count)) {
2553 ring->rx_curr_put_info.block_index++;
2554 if (ring->rx_curr_put_info.block_index ==
2556 ring->rx_curr_put_info.block_index = 0;
2557 block_no = ring->rx_curr_put_info.block_index;
2559 ring->rx_curr_put_info.offset = off;
2560 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2561 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2562 ring->dev->name, rxdp);
2566 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2567 ((ring->rxd_mode == RXD_MODE_3B) &&
2568 (rxdp->Control_2 & s2BIT(0)))) {
2569 ring->rx_curr_put_info.offset = off;
2572 /* calculate size of skb based on ring mode */
2574 HEADER_ETHERNET_II_802_3_SIZE +
2575 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2576 if (ring->rxd_mode == RXD_MODE_1)
2577 size += NET_IP_ALIGN;
2579 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2582 skb = dev_alloc_skb(size);
2584 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2588 first_rxdp->Control_1 |= RXD_OWN_XENA;
2590 swstats->mem_alloc_fail_cnt++;
2594 swstats->mem_allocated += skb->truesize;
2596 if (ring->rxd_mode == RXD_MODE_1) {
2597 /* 1 buffer mode - normal operation mode */
2598 rxdp1 = (struct RxD1 *)rxdp;
2599 memset(rxdp, 0, sizeof(struct RxD1));
2600 skb_reserve(skb, NET_IP_ALIGN);
2601 rxdp1->Buffer0_ptr =
2602 pci_map_single(ring->pdev, skb->data,
2603 size - NET_IP_ALIGN,
2604 PCI_DMA_FROMDEVICE);
2605 if (pci_dma_mapping_error(nic->pdev,
2606 rxdp1->Buffer0_ptr))
2607 goto pci_map_failed;
2610 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2611 rxdp->Host_Control = (unsigned long)skb;
2612 } else if (ring->rxd_mode == RXD_MODE_3B) {
2615 * 2 buffer mode provides 128
2616 * byte aligned receive buffers.
2619 rxdp3 = (struct RxD3 *)rxdp;
2620 /* save buffer pointers to avoid frequent dma mapping */
2621 Buffer0_ptr = rxdp3->Buffer0_ptr;
2622 Buffer1_ptr = rxdp3->Buffer1_ptr;
2623 memset(rxdp, 0, sizeof(struct RxD3));
2624 /* restore the buffer pointers for dma sync*/
2625 rxdp3->Buffer0_ptr = Buffer0_ptr;
2626 rxdp3->Buffer1_ptr = Buffer1_ptr;
2628 ba = &ring->ba[block_no][off];
2629 skb_reserve(skb, BUF0_LEN);
2630 tmp = (u64)(unsigned long)skb->data;
2633 skb->data = (void *) (unsigned long)tmp;
2634 skb_reset_tail_pointer(skb);
2637 rxdp3->Buffer0_ptr =
2638 pci_map_single(ring->pdev, ba->ba_0,
2640 PCI_DMA_FROMDEVICE);
2641 if (pci_dma_mapping_error(nic->pdev,
2642 rxdp3->Buffer0_ptr))
2643 goto pci_map_failed;
2645 pci_dma_sync_single_for_device(ring->pdev,
2646 (dma_addr_t)rxdp3->Buffer0_ptr,
2648 PCI_DMA_FROMDEVICE);
2650 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2651 if (ring->rxd_mode == RXD_MODE_3B) {
2652 /* Two buffer mode */
2655 * Buffer2 will have L3/L4 header plus
2658 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2661 PCI_DMA_FROMDEVICE);
2663 if (pci_dma_mapping_error(nic->pdev,
2664 rxdp3->Buffer2_ptr))
2665 goto pci_map_failed;
2668 rxdp3->Buffer1_ptr =
2669 pci_map_single(ring->pdev,
2672 PCI_DMA_FROMDEVICE);
2674 if (pci_dma_mapping_error(nic->pdev,
2675 rxdp3->Buffer1_ptr)) {
2676 pci_unmap_single(ring->pdev,
2677 (dma_addr_t)(unsigned long)
2680 PCI_DMA_FROMDEVICE);
2681 goto pci_map_failed;
2684 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2685 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2688 rxdp->Control_2 |= s2BIT(0);
2689 rxdp->Host_Control = (unsigned long) (skb);
2691 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2692 rxdp->Control_1 |= RXD_OWN_XENA;
2694 if (off == (ring->rxd_count + 1))
2696 ring->rx_curr_put_info.offset = off;
2698 rxdp->Control_2 |= SET_RXD_MARKER;
2699 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2702 first_rxdp->Control_1 |= RXD_OWN_XENA;
2706 ring->rx_bufs_left += 1;
2711 /* Transfer ownership of first descriptor to adapter just before
2712 * exiting. Before that, use memory barrier so that ownership
2713 * and other fields are seen by adapter correctly.
2717 first_rxdp->Control_1 |= RXD_OWN_XENA;
2723 swstats->pci_map_fail_cnt++;
2724 swstats->mem_freed += skb->truesize;
2725 dev_kfree_skb_irq(skb);
2729 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2731 struct net_device *dev = sp->dev;
2733 struct sk_buff *skb;
2738 struct mac_info *mac_control = &sp->mac_control;
2739 struct stat_block *stats = mac_control->stats_info;
2740 struct swStat *swstats = &stats->sw_stat;
2742 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2743 rxdp = mac_control->rings[ring_no].
2744 rx_blocks[blk].rxds[j].virt_addr;
2745 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2748 if (sp->rxd_mode == RXD_MODE_1) {
2749 rxdp1 = (struct RxD1 *)rxdp;
2750 pci_unmap_single(sp->pdev,
2751 (dma_addr_t)rxdp1->Buffer0_ptr,
2753 HEADER_ETHERNET_II_802_3_SIZE +
2754 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2755 PCI_DMA_FROMDEVICE);
2756 memset(rxdp, 0, sizeof(struct RxD1));
2757 } else if (sp->rxd_mode == RXD_MODE_3B) {
2758 rxdp3 = (struct RxD3 *)rxdp;
2759 ba = &mac_control->rings[ring_no].ba[blk][j];
2760 pci_unmap_single(sp->pdev,
2761 (dma_addr_t)rxdp3->Buffer0_ptr,
2763 PCI_DMA_FROMDEVICE);
2764 pci_unmap_single(sp->pdev,
2765 (dma_addr_t)rxdp3->Buffer1_ptr,
2767 PCI_DMA_FROMDEVICE);
2768 pci_unmap_single(sp->pdev,
2769 (dma_addr_t)rxdp3->Buffer2_ptr,
2771 PCI_DMA_FROMDEVICE);
2772 memset(rxdp, 0, sizeof(struct RxD3));
2774 swstats->mem_freed += skb->truesize;
2776 mac_control->rings[ring_no].rx_bufs_left -= 1;
2781 * free_rx_buffers - Frees all Rx buffers
2782 * @sp: device private variable.
2784 * This function will free all Rx buffers allocated by host.
2789 static void free_rx_buffers(struct s2io_nic *sp)
2791 struct net_device *dev = sp->dev;
2792 int i, blk = 0, buf_cnt = 0;
2793 struct config_param *config = &sp->config;
2794 struct mac_info *mac_control = &sp->mac_control;
2796 for (i = 0; i < config->rx_ring_num; i++) {
2797 struct ring_info *ring = &mac_control->rings[i];
2799 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2800 free_rxd_blk(sp, i, blk);
2802 ring->rx_curr_put_info.block_index = 0;
2803 ring->rx_curr_get_info.block_index = 0;
2804 ring->rx_curr_put_info.offset = 0;
2805 ring->rx_curr_get_info.offset = 0;
2806 ring->rx_bufs_left = 0;
2807 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2808 dev->name, buf_cnt, i);
2812 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2814 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2815 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2822 * s2io_poll - Rx interrupt handler for NAPI support
2823 * @napi : pointer to the napi structure.
2824 * @budget : The number of packets that were budgeted to be processed
2825 * during one pass through the 'Poll" function.
2827 * Comes into picture only if NAPI support has been incorporated. It does
2828 * the same thing that rx_intr_handler does, but not in a interrupt context
2829 * also It will process only a given number of packets.
2831 * 0 on success and 1 if there are No Rx packets to be processed.
2834 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2836 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2837 struct net_device *dev = ring->dev;
2838 int pkts_processed = 0;
2839 u8 __iomem *addr = NULL;
2841 struct s2io_nic *nic = netdev_priv(dev);
2842 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2843 int budget_org = budget;
2845 if (unlikely(!is_s2io_card_up(nic)))
2848 pkts_processed = rx_intr_handler(ring, budget);
2849 s2io_chk_rx_buffers(nic, ring);
2851 if (pkts_processed < budget_org) {
2852 napi_complete(napi);
2853 /*Re Enable MSI-Rx Vector*/
2854 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2855 addr += 7 - ring->ring_no;
2856 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2860 return pkts_processed;
2863 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2865 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2866 int pkts_processed = 0;
2867 int ring_pkts_processed, i;
2868 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2869 int budget_org = budget;
2870 struct config_param *config = &nic->config;
2871 struct mac_info *mac_control = &nic->mac_control;
2873 if (unlikely(!is_s2io_card_up(nic)))
2876 for (i = 0; i < config->rx_ring_num; i++) {
2877 struct ring_info *ring = &mac_control->rings[i];
2878 ring_pkts_processed = rx_intr_handler(ring, budget);
2879 s2io_chk_rx_buffers(nic, ring);
2880 pkts_processed += ring_pkts_processed;
2881 budget -= ring_pkts_processed;
2885 if (pkts_processed < budget_org) {
2886 napi_complete(napi);
2887 /* Re enable the Rx interrupts for the ring */
2888 writeq(0, &bar0->rx_traffic_mask);
2889 readl(&bar0->rx_traffic_mask);
2891 return pkts_processed;
2894 #ifdef CONFIG_NET_POLL_CONTROLLER
2896 * s2io_netpoll - netpoll event handler entry point
2897 * @dev : pointer to the device structure.
2899 * This function will be called by upper layer to check for events on the
2900 * interface in situations where interrupts are disabled. It is used for
2901 * specific in-kernel networking tasks, such as remote consoles and kernel
2902 * debugging over the network (example netdump in RedHat).
2904 static void s2io_netpoll(struct net_device *dev)
2906 struct s2io_nic *nic = netdev_priv(dev);
2907 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2908 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2910 struct config_param *config = &nic->config;
2911 struct mac_info *mac_control = &nic->mac_control;
2913 if (pci_channel_offline(nic->pdev))
2916 disable_irq(dev->irq);
2918 writeq(val64, &bar0->rx_traffic_int);
2919 writeq(val64, &bar0->tx_traffic_int);
2921 /* we need to free up the transmitted skbufs or else netpoll will
2922 * run out of skbs and will fail and eventually netpoll application such
2923 * as netdump will fail.
2925 for (i = 0; i < config->tx_fifo_num; i++)
2926 tx_intr_handler(&mac_control->fifos[i]);
2928 /* check for received packet and indicate up to network */
2929 for (i = 0; i < config->rx_ring_num; i++) {
2930 struct ring_info *ring = &mac_control->rings[i];
2932 rx_intr_handler(ring, 0);
2935 for (i = 0; i < config->rx_ring_num; i++) {
2936 struct ring_info *ring = &mac_control->rings[i];
2938 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2940 "%s: Out of memory in Rx Netpoll!!\n",
2945 enable_irq(dev->irq);
2950 * rx_intr_handler - Rx interrupt handler
2951 * @ring_info: per ring structure.
2952 * @budget: budget for napi processing.
2954 * If the interrupt is because of a received frame or if the
2955 * receive ring contains fresh as yet un-processed frames,this function is
2956 * called. It picks out the RxD at which place the last Rx processing had
2957 * stopped and sends the skb to the OSM's Rx handler and then increments
2960 * No. of napi packets processed.
2962 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2964 int get_block, put_block;
2965 struct rx_curr_get_info get_info, put_info;
2967 struct sk_buff *skb;
2968 int pkt_cnt = 0, napi_pkts = 0;
2973 get_info = ring_data->rx_curr_get_info;
2974 get_block = get_info.block_index;
2975 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2976 put_block = put_info.block_index;
2977 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2979 while (RXD_IS_UP2DT(rxdp)) {
2981 * If your are next to put index then it's
2982 * FIFO full condition
2984 if ((get_block == put_block) &&
2985 (get_info.offset + 1) == put_info.offset) {
2986 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2987 ring_data->dev->name);
2990 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2992 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2993 ring_data->dev->name);
2996 if (ring_data->rxd_mode == RXD_MODE_1) {
2997 rxdp1 = (struct RxD1 *)rxdp;
2998 pci_unmap_single(ring_data->pdev, (dma_addr_t)
3001 HEADER_ETHERNET_II_802_3_SIZE +
3004 PCI_DMA_FROMDEVICE);
3005 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
3006 rxdp3 = (struct RxD3 *)rxdp;
3007 pci_dma_sync_single_for_cpu(ring_data->pdev,
3008 (dma_addr_t)rxdp3->Buffer0_ptr,
3010 PCI_DMA_FROMDEVICE);
3011 pci_unmap_single(ring_data->pdev,
3012 (dma_addr_t)rxdp3->Buffer2_ptr,
3014 PCI_DMA_FROMDEVICE);
3016 prefetch(skb->data);
3017 rx_osm_handler(ring_data, rxdp);
3019 ring_data->rx_curr_get_info.offset = get_info.offset;
3020 rxdp = ring_data->rx_blocks[get_block].
3021 rxds[get_info.offset].virt_addr;
3022 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
3023 get_info.offset = 0;
3024 ring_data->rx_curr_get_info.offset = get_info.offset;
3026 if (get_block == ring_data->block_count)
3028 ring_data->rx_curr_get_info.block_index = get_block;
3029 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3032 if (ring_data->nic->config.napi) {
3039 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3042 if (ring_data->lro) {
3043 /* Clear all LRO sessions before exiting */
3044 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
3045 struct lro *lro = &ring_data->lro0_n[i];
3047 update_L3L4_header(ring_data->nic, lro);
3048 queue_rx_frame(lro->parent, lro->vlan_tag);
3049 clear_lro_session(lro);
3057 * tx_intr_handler - Transmit interrupt handler
3058 * @nic : device private variable
3060 * If an interrupt was raised to indicate DMA complete of the
3061 * Tx packet, this function is called. It identifies the last TxD
3062 * whose buffer was freed and frees all skbs whose data have already
3063 * DMA'ed into the NICs internal memory.
3068 static void tx_intr_handler(struct fifo_info *fifo_data)
3070 struct s2io_nic *nic = fifo_data->nic;
3071 struct tx_curr_get_info get_info, put_info;
3072 struct sk_buff *skb = NULL;
3075 unsigned long flags = 0;
3077 struct stat_block *stats = nic->mac_control.stats_info;
3078 struct swStat *swstats = &stats->sw_stat;
3080 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3083 get_info = fifo_data->tx_curr_get_info;
3084 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3085 txdlp = (struct TxD *)
3086 fifo_data->list_info[get_info.offset].list_virt_addr;
3087 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3088 (get_info.offset != put_info.offset) &&
3089 (txdlp->Host_Control)) {
3090 /* Check for TxD errors */
3091 if (txdlp->Control_1 & TXD_T_CODE) {
3092 unsigned long long err;
3093 err = txdlp->Control_1 & TXD_T_CODE;
3095 swstats->parity_err_cnt++;
3098 /* update t_code statistics */
3099 err_mask = err >> 48;
3102 swstats->tx_buf_abort_cnt++;
3106 swstats->tx_desc_abort_cnt++;
3110 swstats->tx_parity_err_cnt++;
3114 swstats->tx_link_loss_cnt++;
3118 swstats->tx_list_proc_err_cnt++;
3123 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3125 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3126 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3132 /* Updating the statistics block */
3133 nic->dev->stats.tx_bytes += skb->len;
3134 swstats->mem_freed += skb->truesize;
3135 dev_kfree_skb_irq(skb);
3138 if (get_info.offset == get_info.fifo_len + 1)
3139 get_info.offset = 0;
3140 txdlp = (struct TxD *)
3141 fifo_data->list_info[get_info.offset].list_virt_addr;
3142 fifo_data->tx_curr_get_info.offset = get_info.offset;
3145 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3147 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3151 * s2io_mdio_write - Function to write in to MDIO registers
3152 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3153 * @addr : address value
3154 * @value : data value
3155 * @dev : pointer to net_device structure
3157 * This function is used to write values to the MDIO registers
3160 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3161 struct net_device *dev)
3164 struct s2io_nic *sp = netdev_priv(dev);
3165 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3167 /* address transaction */
3168 val64 = MDIO_MMD_INDX_ADDR(addr) |
3169 MDIO_MMD_DEV_ADDR(mmd_type) |
3170 MDIO_MMS_PRT_ADDR(0x0);
3171 writeq(val64, &bar0->mdio_control);
3172 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3173 writeq(val64, &bar0->mdio_control);
3176 /* Data transaction */
3177 val64 = MDIO_MMD_INDX_ADDR(addr) |
3178 MDIO_MMD_DEV_ADDR(mmd_type) |
3179 MDIO_MMS_PRT_ADDR(0x0) |
3180 MDIO_MDIO_DATA(value) |
3181 MDIO_OP(MDIO_OP_WRITE_TRANS);
3182 writeq(val64, &bar0->mdio_control);
3183 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3184 writeq(val64, &bar0->mdio_control);
3187 val64 = MDIO_MMD_INDX_ADDR(addr) |
3188 MDIO_MMD_DEV_ADDR(mmd_type) |
3189 MDIO_MMS_PRT_ADDR(0x0) |
3190 MDIO_OP(MDIO_OP_READ_TRANS);
3191 writeq(val64, &bar0->mdio_control);
3192 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3193 writeq(val64, &bar0->mdio_control);
3198 * s2io_mdio_read - Function to write in to MDIO registers
3199 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3200 * @addr : address value
3201 * @dev : pointer to net_device structure
3203 * This function is used to read values to the MDIO registers
3206 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3210 struct s2io_nic *sp = netdev_priv(dev);
3211 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3213 /* address transaction */
3214 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3215 | MDIO_MMD_DEV_ADDR(mmd_type)
3216 | MDIO_MMS_PRT_ADDR(0x0));
3217 writeq(val64, &bar0->mdio_control);
3218 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3219 writeq(val64, &bar0->mdio_control);
3222 /* Data transaction */
3223 val64 = MDIO_MMD_INDX_ADDR(addr) |
3224 MDIO_MMD_DEV_ADDR(mmd_type) |
3225 MDIO_MMS_PRT_ADDR(0x0) |
3226 MDIO_OP(MDIO_OP_READ_TRANS);
3227 writeq(val64, &bar0->mdio_control);
3228 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3229 writeq(val64, &bar0->mdio_control);
3232 /* Read the value from regs */
3233 rval64 = readq(&bar0->mdio_control);
3234 rval64 = rval64 & 0xFFFF0000;
3235 rval64 = rval64 >> 16;
3240 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3241 * @counter : counter value to be updated
3242 * @flag : flag to indicate the status
3243 * @type : counter type
3245 * This function is to check the status of the xpak counters value
3249 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3255 for (i = 0; i < index; i++)
3259 *counter = *counter + 1;
3260 val64 = *regs_stat & mask;
3261 val64 = val64 >> (index * 0x2);
3267 "Take Xframe NIC out of service.\n");
3269 "Excessive temperatures may result in premature transceiver failure.\n");
3273 "Take Xframe NIC out of service.\n");
3275 "Excessive bias currents may indicate imminent laser diode failure.\n");
3279 "Take Xframe NIC out of service.\n");
3281 "Excessive laser output power may saturate far-end receiver.\n");
3285 "Incorrect XPAK Alarm type\n");
3289 val64 = val64 << (index * 0x2);
3290 *regs_stat = (*regs_stat & (~mask)) | (val64);
3293 *regs_stat = *regs_stat & (~mask);
3298 * s2io_updt_xpak_counter - Function to update the xpak counters
3299 * @dev : pointer to net_device struct
3301 * This function is to upate the status of the xpak counters value
3304 static void s2io_updt_xpak_counter(struct net_device *dev)
3312 struct s2io_nic *sp = netdev_priv(dev);
3313 struct stat_block *stats = sp->mac_control.stats_info;
3314 struct xpakStat *xstats = &stats->xpak_stat;
3316 /* Check the communication with the MDIO slave */
3319 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3320 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3322 "ERR: MDIO slave access failed - Returned %llx\n",
3323 (unsigned long long)val64);
3327 /* Check for the expected value of control reg 1 */
3328 if (val64 != MDIO_CTRL1_SPEED10G) {
3329 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3330 "Returned: %llx- Expected: 0x%x\n",
3331 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3335 /* Loading the DOM register to MDIO register */
3337 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3338 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3340 /* Reading the Alarm flags */
3343 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3345 flag = CHECKBIT(val64, 0x7);
3347 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3348 &xstats->xpak_regs_stat,
3351 if (CHECKBIT(val64, 0x6))
3352 xstats->alarm_transceiver_temp_low++;
3354 flag = CHECKBIT(val64, 0x3);
3356 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3357 &xstats->xpak_regs_stat,
3360 if (CHECKBIT(val64, 0x2))
3361 xstats->alarm_laser_bias_current_low++;
3363 flag = CHECKBIT(val64, 0x1);
3365 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3366 &xstats->xpak_regs_stat,
3369 if (CHECKBIT(val64, 0x0))
3370 xstats->alarm_laser_output_power_low++;
3372 /* Reading the Warning flags */
3375 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3377 if (CHECKBIT(val64, 0x7))
3378 xstats->warn_transceiver_temp_high++;
3380 if (CHECKBIT(val64, 0x6))
3381 xstats->warn_transceiver_temp_low++;
3383 if (CHECKBIT(val64, 0x3))
3384 xstats->warn_laser_bias_current_high++;
3386 if (CHECKBIT(val64, 0x2))
3387 xstats->warn_laser_bias_current_low++;
3389 if (CHECKBIT(val64, 0x1))
3390 xstats->warn_laser_output_power_high++;
3392 if (CHECKBIT(val64, 0x0))
3393 xstats->warn_laser_output_power_low++;
3397 * wait_for_cmd_complete - waits for a command to complete.
3398 * @sp : private member of the device structure, which is a pointer to the
3399 * s2io_nic structure.
3400 * Description: Function that waits for a command to Write into RMAC
3401 * ADDR DATA registers to be completed and returns either success or
3402 * error depending on whether the command was complete or not.
3404 * SUCCESS on success and FAILURE on failure.
3407 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3410 int ret = FAILURE, cnt = 0, delay = 1;
3413 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3417 val64 = readq(addr);
3418 if (bit_state == S2IO_BIT_RESET) {
3419 if (!(val64 & busy_bit)) {
3424 if (val64 & busy_bit) {
3441 * check_pci_device_id - Checks if the device id is supported
3443 * Description: Function to check if the pci device id is supported by driver.
3444 * Return value: Actual device id if supported else PCI_ANY_ID
3446 static u16 check_pci_device_id(u16 id)
3449 case PCI_DEVICE_ID_HERC_WIN:
3450 case PCI_DEVICE_ID_HERC_UNI:
3451 return XFRAME_II_DEVICE;
3452 case PCI_DEVICE_ID_S2IO_UNI:
3453 case PCI_DEVICE_ID_S2IO_WIN:
3454 return XFRAME_I_DEVICE;
3461 * s2io_reset - Resets the card.
3462 * @sp : private member of the device structure.
3463 * Description: Function to Reset the card. This function then also
3464 * restores the previously saved PCI configuration space registers as
3465 * the card reset also resets the configuration space.
3470 static void s2io_reset(struct s2io_nic *sp)
3472 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3477 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3478 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3479 struct stat_block *stats;
3480 struct swStat *swstats;
3482 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3483 __func__, pci_name(sp->pdev));
3485 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3486 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3488 val64 = SW_RESET_ALL;
3489 writeq(val64, &bar0->sw_reset);
3490 if (strstr(sp->product_name, "CX4"))
3493 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3495 /* Restore the PCI state saved during initialization. */
3496 pci_restore_state(sp->pdev);
3497 pci_save_state(sp->pdev);
3498 pci_read_config_word(sp->pdev, 0x2, &val16);
3499 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3504 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3505 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3507 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3511 /* Set swapper to enable I/O register access */
3512 s2io_set_swapper(sp);
3514 /* restore mac_addr entries */
3515 do_s2io_restore_unicast_mc(sp);
3517 /* Restore the MSIX table entries from local variables */
3518 restore_xmsi_data(sp);
3520 /* Clear certain PCI/PCI-X fields after reset */
3521 if (sp->device_type == XFRAME_II_DEVICE) {
3522 /* Clear "detected parity error" bit */
3523 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3525 /* Clearing PCIX Ecc status register */
3526 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3528 /* Clearing PCI_STATUS error reflected here */
3529 writeq(s2BIT(62), &bar0->txpic_int_reg);
3532 /* Reset device statistics maintained by OS */
3533 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3535 stats = sp->mac_control.stats_info;
3536 swstats = &stats->sw_stat;
3538 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3539 up_cnt = swstats->link_up_cnt;
3540 down_cnt = swstats->link_down_cnt;
3541 up_time = swstats->link_up_time;
3542 down_time = swstats->link_down_time;
3543 reset_cnt = swstats->soft_reset_cnt;
3544 mem_alloc_cnt = swstats->mem_allocated;
3545 mem_free_cnt = swstats->mem_freed;
3546 watchdog_cnt = swstats->watchdog_timer_cnt;
3548 memset(stats, 0, sizeof(struct stat_block));
3550 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3551 swstats->link_up_cnt = up_cnt;
3552 swstats->link_down_cnt = down_cnt;
3553 swstats->link_up_time = up_time;
3554 swstats->link_down_time = down_time;
3555 swstats->soft_reset_cnt = reset_cnt;
3556 swstats->mem_allocated = mem_alloc_cnt;
3557 swstats->mem_freed = mem_free_cnt;
3558 swstats->watchdog_timer_cnt = watchdog_cnt;
3560 /* SXE-002: Configure link and activity LED to turn it off */
3561 subid = sp->pdev->subsystem_device;
3562 if (((subid & 0xFF) >= 0x07) &&
3563 (sp->device_type == XFRAME_I_DEVICE)) {
3564 val64 = readq(&bar0->gpio_control);
3565 val64 |= 0x0000800000000000ULL;
3566 writeq(val64, &bar0->gpio_control);
3567 val64 = 0x0411040400000000ULL;
3568 writeq(val64, (void __iomem *)bar0 + 0x2700);
3572 * Clear spurious ECC interrupts that would have occured on
3573 * XFRAME II cards after reset.
3575 if (sp->device_type == XFRAME_II_DEVICE) {
3576 val64 = readq(&bar0->pcc_err_reg);
3577 writeq(val64, &bar0->pcc_err_reg);
3580 sp->device_enabled_once = false;
3584 * s2io_set_swapper - to set the swapper controle on the card
3585 * @sp : private member of the device structure,
3586 * pointer to the s2io_nic structure.
3587 * Description: Function to set the swapper control on the card
3588 * correctly depending on the 'endianness' of the system.
3590 * SUCCESS on success and FAILURE on failure.
3593 static int s2io_set_swapper(struct s2io_nic *sp)
3595 struct net_device *dev = sp->dev;
3596 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3597 u64 val64, valt, valr;
3600 * Set proper endian settings and verify the same by reading
3601 * the PIF Feed-back register.
3604 val64 = readq(&bar0->pif_rd_swapper_fb);
3605 if (val64 != 0x0123456789ABCDEFULL) {
3607 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3608 0x8100008181000081ULL, /* FE=1, SE=0 */
3609 0x4200004242000042ULL, /* FE=0, SE=1 */
3610 0}; /* FE=0, SE=0 */
3613 writeq(value[i], &bar0->swapper_ctrl);
3614 val64 = readq(&bar0->pif_rd_swapper_fb);
3615 if (val64 == 0x0123456789ABCDEFULL)
3620 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3621 "feedback read %llx\n",
3622 dev->name, (unsigned long long)val64);
3627 valr = readq(&bar0->swapper_ctrl);
3630 valt = 0x0123456789ABCDEFULL;
3631 writeq(valt, &bar0->xmsi_address);
3632 val64 = readq(&bar0->xmsi_address);
3634 if (val64 != valt) {
3636 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3637 0x0081810000818100ULL, /* FE=1, SE=0 */
3638 0x0042420000424200ULL, /* FE=0, SE=1 */
3639 0}; /* FE=0, SE=0 */
3642 writeq((value[i] | valr), &bar0->swapper_ctrl);
3643 writeq(valt, &bar0->xmsi_address);
3644 val64 = readq(&bar0->xmsi_address);
3650 unsigned long long x = val64;
3652 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3656 val64 = readq(&bar0->swapper_ctrl);
3657 val64 &= 0xFFFF000000000000ULL;
3661 * The device by default set to a big endian format, so a
3662 * big endian driver need not set anything.
3664 val64 |= (SWAPPER_CTRL_TXP_FE |
3665 SWAPPER_CTRL_TXP_SE |
3666 SWAPPER_CTRL_TXD_R_FE |
3667 SWAPPER_CTRL_TXD_W_FE |
3668 SWAPPER_CTRL_TXF_R_FE |
3669 SWAPPER_CTRL_RXD_R_FE |
3670 SWAPPER_CTRL_RXD_W_FE |
3671 SWAPPER_CTRL_RXF_W_FE |
3672 SWAPPER_CTRL_XMSI_FE |
3673 SWAPPER_CTRL_STATS_FE |
3674 SWAPPER_CTRL_STATS_SE);
3675 if (sp->config.intr_type == INTA)
3676 val64 |= SWAPPER_CTRL_XMSI_SE;
3677 writeq(val64, &bar0->swapper_ctrl);
3680 * Initially we enable all bits to make it accessible by the
3681 * driver, then we selectively enable only those bits that
3684 val64 |= (SWAPPER_CTRL_TXP_FE |
3685 SWAPPER_CTRL_TXP_SE |
3686 SWAPPER_CTRL_TXD_R_FE |
3687 SWAPPER_CTRL_TXD_R_SE |
3688 SWAPPER_CTRL_TXD_W_FE |
3689 SWAPPER_CTRL_TXD_W_SE |
3690 SWAPPER_CTRL_TXF_R_FE |
3691 SWAPPER_CTRL_RXD_R_FE |
3692 SWAPPER_CTRL_RXD_R_SE |
3693 SWAPPER_CTRL_RXD_W_FE |
3694 SWAPPER_CTRL_RXD_W_SE |
3695 SWAPPER_CTRL_RXF_W_FE |
3696 SWAPPER_CTRL_XMSI_FE |
3697 SWAPPER_CTRL_STATS_FE |
3698 SWAPPER_CTRL_STATS_SE);
3699 if (sp->config.intr_type == INTA)
3700 val64 |= SWAPPER_CTRL_XMSI_SE;
3701 writeq(val64, &bar0->swapper_ctrl);
3703 val64 = readq(&bar0->swapper_ctrl);
3706 * Verifying if endian settings are accurate by reading a
3707 * feedback register.
3709 val64 = readq(&bar0->pif_rd_swapper_fb);
3710 if (val64 != 0x0123456789ABCDEFULL) {
3711 /* Endian settings are incorrect, calls for another dekko. */
3713 "%s: Endian settings are wrong, feedback read %llx\n",
3714 dev->name, (unsigned long long)val64);
3721 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3723 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3725 int ret = 0, cnt = 0;
3728 val64 = readq(&bar0->xmsi_access);
3729 if (!(val64 & s2BIT(15)))
3735 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3742 static void restore_xmsi_data(struct s2io_nic *nic)
3744 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3748 if (nic->device_type == XFRAME_I_DEVICE)
3751 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3752 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3753 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3754 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3755 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3756 writeq(val64, &bar0->xmsi_access);
3757 if (wait_for_msix_trans(nic, msix_index)) {
3758 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3759 __func__, msix_index);
3765 static void store_xmsi_data(struct s2io_nic *nic)
3767 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3768 u64 val64, addr, data;
3771 if (nic->device_type == XFRAME_I_DEVICE)
3774 /* Store and display */
3775 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3776 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3777 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3778 writeq(val64, &bar0->xmsi_access);
3779 if (wait_for_msix_trans(nic, msix_index)) {
3780 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3781 __func__, msix_index);
3784 addr = readq(&bar0->xmsi_address);
3785 data = readq(&bar0->xmsi_data);
3787 nic->msix_info[i].addr = addr;
3788 nic->msix_info[i].data = data;
3793 static int s2io_enable_msi_x(struct s2io_nic *nic)
3795 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3797 u16 msi_control; /* Temp variable */
3798 int ret, i, j, msix_indx = 1;
3800 struct stat_block *stats = nic->mac_control.stats_info;
3801 struct swStat *swstats = &stats->sw_stat;
3803 size = nic->num_entries * sizeof(struct msix_entry);
3804 nic->entries = kzalloc(size, GFP_KERNEL);
3805 if (!nic->entries) {
3806 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3808 swstats->mem_alloc_fail_cnt++;
3811 swstats->mem_allocated += size;
3813 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3814 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3815 if (!nic->s2io_entries) {
3816 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3818 swstats->mem_alloc_fail_cnt++;
3819 kfree(nic->entries);
3821 += (nic->num_entries * sizeof(struct msix_entry));
3824 swstats->mem_allocated += size;
3826 nic->entries[0].entry = 0;
3827 nic->s2io_entries[0].entry = 0;
3828 nic->s2io_entries[0].in_use = MSIX_FLG;
3829 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3830 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3832 for (i = 1; i < nic->num_entries; i++) {
3833 nic->entries[i].entry = ((i - 1) * 8) + 1;
3834 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3835 nic->s2io_entries[i].arg = NULL;
3836 nic->s2io_entries[i].in_use = 0;
3839 rx_mat = readq(&bar0->rx_mat);
3840 for (j = 0; j < nic->config.rx_ring_num; j++) {
3841 rx_mat |= RX_MAT_SET(j, msix_indx);
3842 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3843 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3844 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3847 writeq(rx_mat, &bar0->rx_mat);
3848 readq(&bar0->rx_mat);
3850 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3851 /* We fail init if error or we get less vectors than min required */
3853 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3854 kfree(nic->entries);
3855 swstats->mem_freed += nic->num_entries *
3856 sizeof(struct msix_entry);
3857 kfree(nic->s2io_entries);
3858 swstats->mem_freed += nic->num_entries *
3859 sizeof(struct s2io_msix_entry);
3860 nic->entries = NULL;
3861 nic->s2io_entries = NULL;
3866 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3867 * in the herc NIC. (Temp change, needs to be removed later)
3869 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3870 msi_control |= 0x1; /* Enable MSI */
3871 pci_write_config_word(nic->pdev, 0x42, msi_control);
3876 /* Handle software interrupt used during MSI(X) test */
3877 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3879 struct s2io_nic *sp = dev_id;
3881 sp->msi_detected = 1;
3882 wake_up(&sp->msi_wait);
3887 /* Test interrupt path by forcing a a software IRQ */
3888 static int s2io_test_msi(struct s2io_nic *sp)
3890 struct pci_dev *pdev = sp->pdev;
3891 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3895 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3898 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3899 sp->dev->name, pci_name(pdev), pdev->irq);
3903 init_waitqueue_head(&sp->msi_wait);
3904 sp->msi_detected = 0;
3906 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3907 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3908 val64 |= SCHED_INT_CTRL_TIMER_EN;
3909 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3910 writeq(val64, &bar0->scheduled_int_ctrl);
3912 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3914 if (!sp->msi_detected) {
3915 /* MSI(X) test failed, go back to INTx mode */
3916 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3917 "using MSI(X) during test\n",
3918 sp->dev->name, pci_name(pdev));
3923 free_irq(sp->entries[1].vector, sp);
3925 writeq(saved64, &bar0->scheduled_int_ctrl);
3930 static void remove_msix_isr(struct s2io_nic *sp)
3935 for (i = 0; i < sp->num_entries; i++) {
3936 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3937 int vector = sp->entries[i].vector;
3938 void *arg = sp->s2io_entries[i].arg;
3939 free_irq(vector, arg);
3944 kfree(sp->s2io_entries);
3946 sp->s2io_entries = NULL;
3948 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3949 msi_control &= 0xFFFE; /* Disable MSI */
3950 pci_write_config_word(sp->pdev, 0x42, msi_control);
3952 pci_disable_msix(sp->pdev);
3955 static void remove_inta_isr(struct s2io_nic *sp)
3957 struct net_device *dev = sp->dev;
3959 free_irq(sp->pdev->irq, dev);
3962 /* ********************************************************* *
3963 * Functions defined below concern the OS part of the driver *
3964 * ********************************************************* */
3967 * s2io_open - open entry point of the driver
3968 * @dev : pointer to the device structure.
3970 * This function is the open entry point of the driver. It mainly calls a
3971 * function to allocate Rx buffers and inserts them into the buffer
3972 * descriptors and then enables the Rx part of the NIC.
3974 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3978 static int s2io_open(struct net_device *dev)
3980 struct s2io_nic *sp = netdev_priv(dev);
3981 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3985 * Make sure you have link off by default every time
3986 * Nic is initialized
3988 netif_carrier_off(dev);
3989 sp->last_link_state = 0;
3991 /* Initialize H/W and enable interrupts */
3992 err = s2io_card_up(sp);
3994 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3996 goto hw_init_failed;
3999 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
4000 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
4003 goto hw_init_failed;
4005 s2io_start_all_tx_queue(sp);
4009 if (sp->config.intr_type == MSI_X) {
4012 swstats->mem_freed += sp->num_entries *
4013 sizeof(struct msix_entry);
4015 if (sp->s2io_entries) {
4016 kfree(sp->s2io_entries);
4017 swstats->mem_freed += sp->num_entries *
4018 sizeof(struct s2io_msix_entry);
4025 * s2io_close -close entry point of the driver
4026 * @dev : device pointer.
4028 * This is the stop entry point of the driver. It needs to undo exactly
4029 * whatever was done by the open entry point,thus it's usually referred to
4030 * as the close function.Among other things this function mainly stops the
4031 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4033 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4037 static int s2io_close(struct net_device *dev)
4039 struct s2io_nic *sp = netdev_priv(dev);
4040 struct config_param *config = &sp->config;
4044 /* Return if the device is already closed *
4045 * Can happen when s2io_card_up failed in change_mtu *
4047 if (!is_s2io_card_up(sp))
4050 s2io_stop_all_tx_queue(sp);
4051 /* delete all populated mac entries */
4052 for (offset = 1; offset < config->max_mc_addr; offset++) {
4053 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4054 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4055 do_s2io_delete_unicast_mc(sp, tmp64);
4064 * s2io_xmit - Tx entry point of te driver
4065 * @skb : the socket buffer containing the Tx data.
4066 * @dev : device pointer.
4068 * This function is the Tx entry point of the driver. S2IO NIC supports
4069 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4070 * NOTE: when device cant queue the pkt,just the trans_start variable will
4073 * 0 on success & 1 on failure.
4076 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4078 struct s2io_nic *sp = netdev_priv(dev);
4079 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4082 struct TxFIFO_element __iomem *tx_fifo;
4083 unsigned long flags = 0;
4085 struct fifo_info *fifo = NULL;
4086 int do_spin_lock = 1;
4088 int enable_per_list_interrupt = 0;
4089 struct config_param *config = &sp->config;
4090 struct mac_info *mac_control = &sp->mac_control;
4091 struct stat_block *stats = mac_control->stats_info;
4092 struct swStat *swstats = &stats->sw_stat;
4094 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4096 if (unlikely(skb->len <= 0)) {
4097 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4098 dev_kfree_skb_any(skb);
4099 return NETDEV_TX_OK;
4102 if (!is_s2io_card_up(sp)) {
4103 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4106 return NETDEV_TX_OK;
4110 if (sp->vlgrp && vlan_tx_tag_present(skb))
4111 vlan_tag = vlan_tx_tag_get(skb);
4112 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4113 if (skb->protocol == htons(ETH_P_IP)) {
4118 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4119 th = (struct tcphdr *)(((unsigned char *)ip) +
4122 if (ip->protocol == IPPROTO_TCP) {
4123 queue_len = sp->total_tcp_fifos;
4124 queue = (ntohs(th->source) +
4126 sp->fifo_selector[queue_len - 1];
4127 if (queue >= queue_len)
4128 queue = queue_len - 1;
4129 } else if (ip->protocol == IPPROTO_UDP) {
4130 queue_len = sp->total_udp_fifos;
4131 queue = (ntohs(th->source) +
4133 sp->fifo_selector[queue_len - 1];
4134 if (queue >= queue_len)
4135 queue = queue_len - 1;
4136 queue += sp->udp_fifo_idx;
4137 if (skb->len > 1024)
4138 enable_per_list_interrupt = 1;
4143 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4144 /* get fifo number based on skb->priority value */
4145 queue = config->fifo_mapping
4146 [skb->priority & (MAX_TX_FIFOS - 1)];
4147 fifo = &mac_control->fifos[queue];
4150 spin_lock_irqsave(&fifo->tx_lock, flags);
4152 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4153 return NETDEV_TX_LOCKED;
4156 if (sp->config.multiq) {
4157 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4158 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4159 return NETDEV_TX_BUSY;
4161 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4162 if (netif_queue_stopped(dev)) {
4163 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4164 return NETDEV_TX_BUSY;
4168 put_off = (u16)fifo->tx_curr_put_info.offset;
4169 get_off = (u16)fifo->tx_curr_get_info.offset;
4170 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
4172 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4173 /* Avoid "put" pointer going beyond "get" pointer */
4174 if (txdp->Host_Control ||
4175 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4176 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4177 s2io_stop_tx_queue(sp, fifo->fifo_no);
4179 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4180 return NETDEV_TX_OK;
4183 offload_type = s2io_offload_type(skb);
4184 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4185 txdp->Control_1 |= TXD_TCP_LSO_EN;
4186 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4188 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4189 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4193 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4194 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4195 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4196 if (enable_per_list_interrupt)
4197 if (put_off & (queue_len >> 5))
4198 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4200 txdp->Control_2 |= TXD_VLAN_ENABLE;
4201 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4204 frg_len = skb_headlen(skb);
4205 if (offload_type == SKB_GSO_UDP) {
4208 ufo_size = s2io_udp_mss(skb);
4210 txdp->Control_1 |= TXD_UFO_EN;
4211 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4212 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4214 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4215 fifo->ufo_in_band_v[put_off] =
4216 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4218 fifo->ufo_in_band_v[put_off] =
4219 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4221 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4222 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4223 fifo->ufo_in_band_v,
4226 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4227 goto pci_map_failed;
4231 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4232 frg_len, PCI_DMA_TODEVICE);
4233 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4234 goto pci_map_failed;
4236 txdp->Host_Control = (unsigned long)skb;
4237 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4238 if (offload_type == SKB_GSO_UDP)
4239 txdp->Control_1 |= TXD_UFO_EN;
4241 frg_cnt = skb_shinfo(skb)->nr_frags;
4242 /* For fragmented SKB. */
4243 for (i = 0; i < frg_cnt; i++) {
4244 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4245 /* A '0' length fragment will be ignored */
4249 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4253 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4254 if (offload_type == SKB_GSO_UDP)
4255 txdp->Control_1 |= TXD_UFO_EN;
4257 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4259 if (offload_type == SKB_GSO_UDP)
4260 frg_cnt++; /* as Txd0 was used for inband header */
4262 tx_fifo = mac_control->tx_FIFO_start[queue];
4263 val64 = fifo->list_info[put_off].list_phy_addr;
4264 writeq(val64, &tx_fifo->TxDL_Pointer);
4266 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4269 val64 |= TX_FIFO_SPECIAL_FUNC;
4271 writeq(val64, &tx_fifo->List_Control);
4276 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4278 fifo->tx_curr_put_info.offset = put_off;
4280 /* Avoid "put" pointer going beyond "get" pointer */
4281 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4282 swstats->fifo_full_cnt++;
4284 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4286 s2io_stop_tx_queue(sp, fifo->fifo_no);
4288 swstats->mem_allocated += skb->truesize;
4289 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4291 if (sp->config.intr_type == MSI_X)
4292 tx_intr_handler(fifo);
4294 return NETDEV_TX_OK;
4297 swstats->pci_map_fail_cnt++;
4298 s2io_stop_tx_queue(sp, fifo->fifo_no);
4299 swstats->mem_freed += skb->truesize;
4301 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4302 return NETDEV_TX_OK;
4306 s2io_alarm_handle(unsigned long data)
4308 struct s2io_nic *sp = (struct s2io_nic *)data;
4309 struct net_device *dev = sp->dev;
4311 s2io_handle_errors(dev);
4312 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4315 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4317 struct ring_info *ring = (struct ring_info *)dev_id;
4318 struct s2io_nic *sp = ring->nic;
4319 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4321 if (unlikely(!is_s2io_card_up(sp)))
4324 if (sp->config.napi) {
4325 u8 __iomem *addr = NULL;
4328 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4329 addr += (7 - ring->ring_no);
4330 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4333 napi_schedule(&ring->napi);
4335 rx_intr_handler(ring, 0);
4336 s2io_chk_rx_buffers(sp, ring);
4342 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4345 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4346 struct s2io_nic *sp = fifos->nic;
4347 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4348 struct config_param *config = &sp->config;
4351 if (unlikely(!is_s2io_card_up(sp)))
4354 reason = readq(&bar0->general_int_status);
4355 if (unlikely(reason == S2IO_MINUS_ONE))
4356 /* Nothing much can be done. Get out */
4359 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4360 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4362 if (reason & GEN_INTR_TXPIC)
4363 s2io_txpic_intr_handle(sp);
4365 if (reason & GEN_INTR_TXTRAFFIC)
4366 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4368 for (i = 0; i < config->tx_fifo_num; i++)
4369 tx_intr_handler(&fifos[i]);
4371 writeq(sp->general_int_mask, &bar0->general_int_mask);
4372 readl(&bar0->general_int_status);
4375 /* The interrupt was not raised by us */
4379 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4381 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4384 val64 = readq(&bar0->pic_int_status);
4385 if (val64 & PIC_INT_GPIO) {
4386 val64 = readq(&bar0->gpio_int_reg);
4387 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4388 (val64 & GPIO_INT_REG_LINK_UP)) {
4390 * This is unstable state so clear both up/down
4391 * interrupt and adapter to re-evaluate the link state.
4393 val64 |= GPIO_INT_REG_LINK_DOWN;
4394 val64 |= GPIO_INT_REG_LINK_UP;
4395 writeq(val64, &bar0->gpio_int_reg);
4396 val64 = readq(&bar0->gpio_int_mask);
4397 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4398 GPIO_INT_MASK_LINK_DOWN);
4399 writeq(val64, &bar0->gpio_int_mask);
4400 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4401 val64 = readq(&bar0->adapter_status);
4402 /* Enable Adapter */
4403 val64 = readq(&bar0->adapter_control);
4404 val64 |= ADAPTER_CNTL_EN;
4405 writeq(val64, &bar0->adapter_control);
4406 val64 |= ADAPTER_LED_ON;
4407 writeq(val64, &bar0->adapter_control);
4408 if (!sp->device_enabled_once)
4409 sp->device_enabled_once = 1;
4411 s2io_link(sp, LINK_UP);
4413 * unmask link down interrupt and mask link-up
4416 val64 = readq(&bar0->gpio_int_mask);
4417 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4418 val64 |= GPIO_INT_MASK_LINK_UP;
4419 writeq(val64, &bar0->gpio_int_mask);
4421 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4422 val64 = readq(&bar0->adapter_status);
4423 s2io_link(sp, LINK_DOWN);
4424 /* Link is down so unmaks link up interrupt */
4425 val64 = readq(&bar0->gpio_int_mask);
4426 val64 &= ~GPIO_INT_MASK_LINK_UP;
4427 val64 |= GPIO_INT_MASK_LINK_DOWN;
4428 writeq(val64, &bar0->gpio_int_mask);
4431 val64 = readq(&bar0->adapter_control);
4432 val64 = val64 & (~ADAPTER_LED_ON);
4433 writeq(val64, &bar0->adapter_control);
4436 val64 = readq(&bar0->gpio_int_mask);
4440 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4441 * @value: alarm bits
4442 * @addr: address value
4443 * @cnt: counter variable
4444 * Description: Check for alarm and increment the counter
4446 * 1 - if alarm bit set
4447 * 0 - if alarm bit is not set
4449 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4450 unsigned long long *cnt)
4453 val64 = readq(addr);
4454 if (val64 & value) {
4455 writeq(val64, addr);
4464 * s2io_handle_errors - Xframe error indication handler
4465 * @nic: device private variable
4466 * Description: Handle alarms such as loss of link, single or
4467 * double ECC errors, critical and serious errors.
4471 static void s2io_handle_errors(void *dev_id)
4473 struct net_device *dev = (struct net_device *)dev_id;
4474 struct s2io_nic *sp = netdev_priv(dev);
4475 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4476 u64 temp64 = 0, val64 = 0;
4479 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4480 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4482 if (!is_s2io_card_up(sp))
4485 if (pci_channel_offline(sp->pdev))
4488 memset(&sw_stat->ring_full_cnt, 0,
4489 sizeof(sw_stat->ring_full_cnt));
4491 /* Handling the XPAK counters update */
4492 if (stats->xpak_timer_count < 72000) {
4493 /* waiting for an hour */
4494 stats->xpak_timer_count++;
4496 s2io_updt_xpak_counter(dev);
4497 /* reset the count to zero */
4498 stats->xpak_timer_count = 0;
4501 /* Handling link status change error Intr */
4502 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4503 val64 = readq(&bar0->mac_rmac_err_reg);
4504 writeq(val64, &bar0->mac_rmac_err_reg);
4505 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4506 schedule_work(&sp->set_link_task);
4509 /* In case of a serious error, the device will be Reset. */
4510 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4511 &sw_stat->serious_err_cnt))
4514 /* Check for data parity error */
4515 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4516 &sw_stat->parity_err_cnt))
4519 /* Check for ring full counter */
4520 if (sp->device_type == XFRAME_II_DEVICE) {
4521 val64 = readq(&bar0->ring_bump_counter1);
4522 for (i = 0; i < 4; i++) {
4523 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4524 temp64 >>= 64 - ((i+1)*16);
4525 sw_stat->ring_full_cnt[i] += temp64;
4528 val64 = readq(&bar0->ring_bump_counter2);
4529 for (i = 0; i < 4; i++) {
4530 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4531 temp64 >>= 64 - ((i+1)*16);
4532 sw_stat->ring_full_cnt[i+4] += temp64;
4536 val64 = readq(&bar0->txdma_int_status);
4537 /*check for pfc_err*/
4538 if (val64 & TXDMA_PFC_INT) {
4539 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4540 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4543 &sw_stat->pfc_err_cnt))
4545 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4547 &sw_stat->pfc_err_cnt);
4550 /*check for tda_err*/
4551 if (val64 & TXDMA_TDA_INT) {
4552 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4556 &sw_stat->tda_err_cnt))
4558 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4560 &sw_stat->tda_err_cnt);
4562 /*check for pcc_err*/
4563 if (val64 & TXDMA_PCC_INT) {
4564 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4565 PCC_N_SERR | PCC_6_COF_OV_ERR |
4566 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4567 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4570 &sw_stat->pcc_err_cnt))
4572 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4574 &sw_stat->pcc_err_cnt);
4577 /*check for tti_err*/
4578 if (val64 & TXDMA_TTI_INT) {
4579 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4581 &sw_stat->tti_err_cnt))
4583 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4585 &sw_stat->tti_err_cnt);
4588 /*check for lso_err*/
4589 if (val64 & TXDMA_LSO_INT) {
4590 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4591 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4593 &sw_stat->lso_err_cnt))
4595 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4597 &sw_stat->lso_err_cnt);
4600 /*check for tpa_err*/
4601 if (val64 & TXDMA_TPA_INT) {
4602 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4604 &sw_stat->tpa_err_cnt))
4606 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4608 &sw_stat->tpa_err_cnt);
4611 /*check for sm_err*/
4612 if (val64 & TXDMA_SM_INT) {
4613 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4615 &sw_stat->sm_err_cnt))
4619 val64 = readq(&bar0->mac_int_status);
4620 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4621 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4622 &bar0->mac_tmac_err_reg,
4623 &sw_stat->mac_tmac_err_cnt))
4625 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4626 TMAC_DESC_ECC_SG_ERR |
4627 TMAC_DESC_ECC_DB_ERR,
4628 &bar0->mac_tmac_err_reg,
4629 &sw_stat->mac_tmac_err_cnt);
4632 val64 = readq(&bar0->xgxs_int_status);
4633 if (val64 & XGXS_INT_STATUS_TXGXS) {
4634 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4635 &bar0->xgxs_txgxs_err_reg,
4636 &sw_stat->xgxs_txgxs_err_cnt))
4638 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4639 &bar0->xgxs_txgxs_err_reg,
4640 &sw_stat->xgxs_txgxs_err_cnt);
4643 val64 = readq(&bar0->rxdma_int_status);
4644 if (val64 & RXDMA_INT_RC_INT_M) {
4645 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4647 RC_PRCn_SM_ERR_ALARM |
4648 RC_FTC_SM_ERR_ALARM,
4650 &sw_stat->rc_err_cnt))
4652 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4654 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4655 &sw_stat->rc_err_cnt);
4656 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4659 &bar0->prc_pcix_err_reg,
4660 &sw_stat->prc_pcix_err_cnt))
4662 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4665 &bar0->prc_pcix_err_reg,
4666 &sw_stat->prc_pcix_err_cnt);
4669 if (val64 & RXDMA_INT_RPA_INT_M) {
4670 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4672 &sw_stat->rpa_err_cnt))
4674 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4676 &sw_stat->rpa_err_cnt);
4679 if (val64 & RXDMA_INT_RDA_INT_M) {
4680 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4681 RDA_FRM_ECC_DB_N_AERR |
4684 RDA_RXD_ECC_DB_SERR,
4686 &sw_stat->rda_err_cnt))
4688 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4689 RDA_FRM_ECC_SG_ERR |
4693 &sw_stat->rda_err_cnt);
4696 if (val64 & RXDMA_INT_RTI_INT_M) {
4697 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4699 &sw_stat->rti_err_cnt))
4701 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4703 &sw_stat->rti_err_cnt);
4706 val64 = readq(&bar0->mac_int_status);
4707 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4708 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4709 &bar0->mac_rmac_err_reg,
4710 &sw_stat->mac_rmac_err_cnt))
4712 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4713 RMAC_SINGLE_ECC_ERR |
4714 RMAC_DOUBLE_ECC_ERR,
4715 &bar0->mac_rmac_err_reg,
4716 &sw_stat->mac_rmac_err_cnt);
4719 val64 = readq(&bar0->xgxs_int_status);
4720 if (val64 & XGXS_INT_STATUS_RXGXS) {
4721 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4722 &bar0->xgxs_rxgxs_err_reg,
4723 &sw_stat->xgxs_rxgxs_err_cnt))
4727 val64 = readq(&bar0->mc_int_status);
4728 if (val64 & MC_INT_STATUS_MC_INT) {
4729 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4731 &sw_stat->mc_err_cnt))
4734 /* Handling Ecc errors */
4735 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4736 writeq(val64, &bar0->mc_err_reg);
4737 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4738 sw_stat->double_ecc_errs++;
4739 if (sp->device_type != XFRAME_II_DEVICE) {
4741 * Reset XframeI only if critical error
4744 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4745 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4749 sw_stat->single_ecc_errs++;
4755 s2io_stop_all_tx_queue(sp);
4756 schedule_work(&sp->rst_timer_task);
4757 sw_stat->soft_reset_cnt++;
4761 * s2io_isr - ISR handler of the device .
4762 * @irq: the irq of the device.
4763 * @dev_id: a void pointer to the dev structure of the NIC.
4764 * Description: This function is the ISR handler of the device. It
4765 * identifies the reason for the interrupt and calls the relevant
4766 * service routines. As a contongency measure, this ISR allocates the
4767 * recv buffers, if their numbers are below the panic value which is
4768 * presently set to 25% of the original number of rcv buffers allocated.
4770 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4771 * IRQ_NONE: will be returned if interrupt is not from our device
4773 static irqreturn_t s2io_isr(int irq, void *dev_id)
4775 struct net_device *dev = (struct net_device *)dev_id;
4776 struct s2io_nic *sp = netdev_priv(dev);
4777 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4780 struct mac_info *mac_control;
4781 struct config_param *config;
4783 /* Pretend we handled any irq's from a disconnected card */
4784 if (pci_channel_offline(sp->pdev))
4787 if (!is_s2io_card_up(sp))
4790 config = &sp->config;
4791 mac_control = &sp->mac_control;
4794 * Identify the cause for interrupt and call the appropriate
4795 * interrupt handler. Causes for the interrupt could be;
4800 reason = readq(&bar0->general_int_status);
4802 if (unlikely(reason == S2IO_MINUS_ONE))
4803 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4806 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4807 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4810 if (reason & GEN_INTR_RXTRAFFIC) {
4811 napi_schedule(&sp->napi);
4812 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4813 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4814 readl(&bar0->rx_traffic_int);
4818 * rx_traffic_int reg is an R1 register, writing all 1's
4819 * will ensure that the actual interrupt causing bit
4820 * get's cleared and hence a read can be avoided.
4822 if (reason & GEN_INTR_RXTRAFFIC)
4823 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4825 for (i = 0; i < config->rx_ring_num; i++) {
4826 struct ring_info *ring = &mac_control->rings[i];
4828 rx_intr_handler(ring, 0);
4833 * tx_traffic_int reg is an R1 register, writing all 1's
4834 * will ensure that the actual interrupt causing bit get's
4835 * cleared and hence a read can be avoided.
4837 if (reason & GEN_INTR_TXTRAFFIC)
4838 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4840 for (i = 0; i < config->tx_fifo_num; i++)
4841 tx_intr_handler(&mac_control->fifos[i]);
4843 if (reason & GEN_INTR_TXPIC)
4844 s2io_txpic_intr_handle(sp);
4847 * Reallocate the buffers from the interrupt handler itself.
4849 if (!config->napi) {
4850 for (i = 0; i < config->rx_ring_num; i++) {
4851 struct ring_info *ring = &mac_control->rings[i];
4853 s2io_chk_rx_buffers(sp, ring);
4856 writeq(sp->general_int_mask, &bar0->general_int_mask);
4857 readl(&bar0->general_int_status);
4861 } else if (!reason) {
4862 /* The interrupt was not raised by us */
4872 static void s2io_updt_stats(struct s2io_nic *sp)
4874 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4878 if (is_s2io_card_up(sp)) {
4879 /* Apprx 30us on a 133 MHz bus */
4880 val64 = SET_UPDT_CLICKS(10) |
4881 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4882 writeq(val64, &bar0->stat_cfg);
4885 val64 = readq(&bar0->stat_cfg);
4886 if (!(val64 & s2BIT(0)))
4890 break; /* Updt failed */
4896 * s2io_get_stats - Updates the device statistics structure.
4897 * @dev : pointer to the device structure.
4899 * This function updates the device statistics structure in the s2io_nic
4900 * structure and returns a pointer to the same.
4902 * pointer to the updated net_device_stats structure.
4905 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4907 struct s2io_nic *sp = netdev_priv(dev);
4908 struct config_param *config = &sp->config;
4909 struct mac_info *mac_control = &sp->mac_control;
4910 struct stat_block *stats = mac_control->stats_info;
4913 /* Configure Stats for immediate updt */
4914 s2io_updt_stats(sp);
4916 /* Using sp->stats as a staging area, because reset (due to mtu
4917 change, for example) will clear some hardware counters */
4918 dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
4919 sp->stats.tx_packets;
4920 sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4922 dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
4923 sp->stats.tx_errors;
4924 sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4926 dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
4927 sp->stats.rx_errors;
4928 sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4930 dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
4931 sp->stats.multicast;
4932 sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4934 dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
4935 sp->stats.rx_length_errors;
4936 sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
4938 /* collect per-ring rx_packets and rx_bytes */
4939 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
4940 for (i = 0; i < config->rx_ring_num; i++) {
4941 struct ring_info *ring = &mac_control->rings[i];
4943 dev->stats.rx_packets += ring->rx_packets;
4944 dev->stats.rx_bytes += ring->rx_bytes;
4951 * s2io_set_multicast - entry point for multicast address enable/disable.
4952 * @dev : pointer to the device structure
4954 * This function is a driver entry point which gets called by the kernel
4955 * whenever multicast addresses must be enabled/disabled. This also gets
4956 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4957 * determine, if multicast address must be enabled or if promiscuous mode
4958 * is to be disabled etc.
4963 static void s2io_set_multicast(struct net_device *dev)
4966 struct netdev_hw_addr *ha;
4967 struct s2io_nic *sp = netdev_priv(dev);
4968 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4969 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4971 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4973 struct config_param *config = &sp->config;
4975 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4976 /* Enable all Multicast addresses */
4977 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4978 &bar0->rmac_addr_data0_mem);
4979 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4980 &bar0->rmac_addr_data1_mem);
4981 val64 = RMAC_ADDR_CMD_MEM_WE |
4982 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4983 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4984 writeq(val64, &bar0->rmac_addr_cmd_mem);
4985 /* Wait till command completes */
4986 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4987 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4991 sp->all_multi_pos = config->max_mc_addr - 1;
4992 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4993 /* Disable all Multicast addresses */
4994 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4995 &bar0->rmac_addr_data0_mem);
4996 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4997 &bar0->rmac_addr_data1_mem);
4998 val64 = RMAC_ADDR_CMD_MEM_WE |
4999 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5000 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
5001 writeq(val64, &bar0->rmac_addr_cmd_mem);
5002 /* Wait till command completes */
5003 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5004 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5008 sp->all_multi_pos = 0;
5011 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5012 /* Put the NIC into promiscuous mode */
5013 add = &bar0->mac_cfg;
5014 val64 = readq(&bar0->mac_cfg);
5015 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5017 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5018 writel((u32)val64, add);
5019 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5020 writel((u32) (val64 >> 32), (add + 4));
5022 if (vlan_tag_strip != 1) {
5023 val64 = readq(&bar0->rx_pa_cfg);
5024 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5025 writeq(val64, &bar0->rx_pa_cfg);
5026 sp->vlan_strip_flag = 0;
5029 val64 = readq(&bar0->mac_cfg);
5030 sp->promisc_flg = 1;
5031 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5033 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5034 /* Remove the NIC from promiscuous mode */
5035 add = &bar0->mac_cfg;
5036 val64 = readq(&bar0->mac_cfg);
5037 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5039 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5040 writel((u32)val64, add);
5041 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5042 writel((u32) (val64 >> 32), (add + 4));
5044 if (vlan_tag_strip != 0) {
5045 val64 = readq(&bar0->rx_pa_cfg);
5046 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5047 writeq(val64, &bar0->rx_pa_cfg);
5048 sp->vlan_strip_flag = 1;
5051 val64 = readq(&bar0->mac_cfg);
5052 sp->promisc_flg = 0;
5053 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5056 /* Update individual M_CAST address list */
5057 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5058 if (netdev_mc_count(dev) >
5059 (config->max_mc_addr - config->max_mac_addr)) {
5061 "%s: No more Rx filters can be added - "
5062 "please enable ALL_MULTI instead\n",
5067 prev_cnt = sp->mc_addr_count;
5068 sp->mc_addr_count = netdev_mc_count(dev);
5070 /* Clear out the previous list of Mc in the H/W. */
5071 for (i = 0; i < prev_cnt; i++) {
5072 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5073 &bar0->rmac_addr_data0_mem);
5074 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5075 &bar0->rmac_addr_data1_mem);
5076 val64 = RMAC_ADDR_CMD_MEM_WE |
5077 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5078 RMAC_ADDR_CMD_MEM_OFFSET
5079 (config->mc_start_offset + i);
5080 writeq(val64, &bar0->rmac_addr_cmd_mem);
5082 /* Wait for command completes */
5083 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5084 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5087 "%s: Adding Multicasts failed\n",
5093 /* Create the new Rx filter list and update the same in H/W. */
5095 netdev_for_each_mc_addr(ha, dev) {
5096 memcpy(sp->usr_addrs[i].addr, ha->addr,
5099 for (j = 0; j < ETH_ALEN; j++) {
5100 mac_addr |= ha->addr[j];
5104 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5105 &bar0->rmac_addr_data0_mem);
5106 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5107 &bar0->rmac_addr_data1_mem);
5108 val64 = RMAC_ADDR_CMD_MEM_WE |
5109 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5110 RMAC_ADDR_CMD_MEM_OFFSET
5111 (i + config->mc_start_offset);
5112 writeq(val64, &bar0->rmac_addr_cmd_mem);
5114 /* Wait for command completes */
5115 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5116 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5119 "%s: Adding Multicasts failed\n",
5128 /* read from CAM unicast & multicast addresses and store it in
5129 * def_mac_addr structure
5131 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5135 struct config_param *config = &sp->config;
5137 /* store unicast & multicast mac addresses */
5138 for (offset = 0; offset < config->max_mc_addr; offset++) {
5139 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5140 /* if read fails disable the entry */
5141 if (mac_addr == FAILURE)
5142 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5143 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5147 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5148 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5151 struct config_param *config = &sp->config;
5152 /* restore unicast mac address */
5153 for (offset = 0; offset < config->max_mac_addr; offset++)
5154 do_s2io_prog_unicast(sp->dev,
5155 sp->def_mac_addr[offset].mac_addr);
5157 /* restore multicast mac address */
5158 for (offset = config->mc_start_offset;
5159 offset < config->max_mc_addr; offset++)
5160 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5163 /* add a multicast MAC address to CAM */
5164 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5168 struct config_param *config = &sp->config;
5170 for (i = 0; i < ETH_ALEN; i++) {
5172 mac_addr |= addr[i];
5174 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5177 /* check if the multicast mac already preset in CAM */
5178 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5180 tmp64 = do_s2io_read_unicast_mc(sp, i);
5181 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5184 if (tmp64 == mac_addr)
5187 if (i == config->max_mc_addr) {
5189 "CAM full no space left for multicast MAC\n");
5192 /* Update the internal structure with this new mac address */
5193 do_s2io_copy_mac_addr(sp, i, mac_addr);
5195 return do_s2io_add_mac(sp, mac_addr, i);
5198 /* add MAC address to CAM */
5199 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5204 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5205 &bar0->rmac_addr_data0_mem);
5207 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5208 RMAC_ADDR_CMD_MEM_OFFSET(off);
5209 writeq(val64, &bar0->rmac_addr_cmd_mem);
5211 /* Wait till command completes */
5212 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5213 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5215 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5220 /* deletes a specified unicast/multicast mac entry from CAM */
5221 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5224 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5225 struct config_param *config = &sp->config;
5228 offset < config->max_mc_addr; offset++) {
5229 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5230 if (tmp64 == addr) {
5231 /* disable the entry by writing 0xffffffffffffULL */
5232 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5234 /* store the new mac list from CAM */
5235 do_s2io_store_unicast_mc(sp);
5239 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5240 (unsigned long long)addr);
5244 /* read mac entries from CAM */
5245 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5247 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5248 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5251 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5252 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5253 writeq(val64, &bar0->rmac_addr_cmd_mem);
5255 /* Wait till command completes */
5256 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5257 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5259 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5262 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5268 * s2io_set_mac_addr driver entry point
5271 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5273 struct sockaddr *addr = p;
5275 if (!is_valid_ether_addr(addr->sa_data))
5278 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5280 /* store the MAC address in CAM */
5281 return do_s2io_prog_unicast(dev, dev->dev_addr);
5284 * do_s2io_prog_unicast - Programs the Xframe mac address
5285 * @dev : pointer to the device structure.
5286 * @addr: a uchar pointer to the new mac address which is to be set.
5287 * Description : This procedure will program the Xframe to receive
5288 * frames with new Mac Address
5289 * Return value: SUCCESS on success and an appropriate (-)ve integer
5290 * as defined in errno.h file on failure.
5293 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5295 struct s2io_nic *sp = netdev_priv(dev);
5296 register u64 mac_addr = 0, perm_addr = 0;
5299 struct config_param *config = &sp->config;
5302 * Set the new MAC address as the new unicast filter and reflect this
5303 * change on the device address registered with the OS. It will be
5306 for (i = 0; i < ETH_ALEN; i++) {
5308 mac_addr |= addr[i];
5310 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5313 /* check if the dev_addr is different than perm_addr */
5314 if (mac_addr == perm_addr)
5317 /* check if the mac already preset in CAM */
5318 for (i = 1; i < config->max_mac_addr; i++) {
5319 tmp64 = do_s2io_read_unicast_mc(sp, i);
5320 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5323 if (tmp64 == mac_addr) {
5325 "MAC addr:0x%llx already present in CAM\n",
5326 (unsigned long long)mac_addr);
5330 if (i == config->max_mac_addr) {
5331 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5334 /* Update the internal structure with this new mac address */
5335 do_s2io_copy_mac_addr(sp, i, mac_addr);
5337 return do_s2io_add_mac(sp, mac_addr, i);
5341 * s2io_ethtool_sset - Sets different link parameters.
5342 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5343 * @info: pointer to the structure with parameters given by ethtool to set
5346 * The function sets different link parameters provided by the user onto
5352 static int s2io_ethtool_sset(struct net_device *dev,
5353 struct ethtool_cmd *info)
5355 struct s2io_nic *sp = netdev_priv(dev);
5356 if ((info->autoneg == AUTONEG_ENABLE) ||
5357 (info->speed != SPEED_10000) ||
5358 (info->duplex != DUPLEX_FULL))
5361 s2io_close(sp->dev);
5369 * s2io_ethtol_gset - Return link specific information.
5370 * @sp : private member of the device structure, pointer to the
5371 * s2io_nic structure.
5372 * @info : pointer to the structure with parameters given by ethtool
5373 * to return link information.
5375 * Returns link specific information like speed, duplex etc.. to ethtool.
5377 * return 0 on success.
5380 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5382 struct s2io_nic *sp = netdev_priv(dev);
5383 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5384 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5385 info->port = PORT_FIBRE;
5387 /* info->transceiver */
5388 info->transceiver = XCVR_EXTERNAL;
5390 if (netif_carrier_ok(sp->dev)) {
5391 info->speed = 10000;
5392 info->duplex = DUPLEX_FULL;
5398 info->autoneg = AUTONEG_DISABLE;
5403 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5404 * @sp : private member of the device structure, which is a pointer to the
5405 * s2io_nic structure.
5406 * @info : pointer to the structure with parameters given by ethtool to
5407 * return driver information.
5409 * Returns driver specefic information like name, version etc.. to ethtool.
5414 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5415 struct ethtool_drvinfo *info)
5417 struct s2io_nic *sp = netdev_priv(dev);
5419 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5420 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5421 strncpy(info->fw_version, "", sizeof(info->fw_version));
5422 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5423 info->regdump_len = XENA_REG_SPACE;
5424 info->eedump_len = XENA_EEPROM_SPACE;
5428 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5429 * @sp: private member of the device structure, which is a pointer to the
5430 * s2io_nic structure.
5431 * @regs : pointer to the structure with parameters given by ethtool for
5432 * dumping the registers.
5433 * @reg_space: The input argumnet into which all the registers are dumped.
5435 * Dumps the entire register space of xFrame NIC into the user given
5441 static void s2io_ethtool_gregs(struct net_device *dev,
5442 struct ethtool_regs *regs, void *space)
5446 u8 *reg_space = (u8 *)space;
5447 struct s2io_nic *sp = netdev_priv(dev);
5449 regs->len = XENA_REG_SPACE;
5450 regs->version = sp->pdev->subsystem_device;
5452 for (i = 0; i < regs->len; i += 8) {
5453 reg = readq(sp->bar0 + i);
5454 memcpy((reg_space + i), ®, 8);
5459 * s2io_phy_id - timer function that alternates adapter LED.
5460 * @data : address of the private member of the device structure, which
5461 * is a pointer to the s2io_nic structure, provided as an u32.
5462 * Description: This is actually the timer function that alternates the
5463 * adapter LED bit of the adapter control bit to set/reset every time on
5464 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
5465 * once every second.
5467 static void s2io_phy_id(unsigned long data)
5469 struct s2io_nic *sp = (struct s2io_nic *)data;
5470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5474 subid = sp->pdev->subsystem_device;
5475 if ((sp->device_type == XFRAME_II_DEVICE) ||
5476 ((subid & 0xFF) >= 0x07)) {
5477 val64 = readq(&bar0->gpio_control);
5478 val64 ^= GPIO_CTRL_GPIO_0;
5479 writeq(val64, &bar0->gpio_control);
5481 val64 = readq(&bar0->adapter_control);
5482 val64 ^= ADAPTER_LED_ON;
5483 writeq(val64, &bar0->adapter_control);
5486 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5490 * s2io_ethtool_idnic - To physically identify the nic on the system.
5491 * @sp : private member of the device structure, which is a pointer to the
5492 * s2io_nic structure.
5493 * @id : pointer to the structure with identification parameters given by
5495 * Description: Used to physically identify the NIC on the system.
5496 * The Link LED will blink for a time specified by the user for
5498 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5499 * identification is possible only if it's link is up.
5501 * int , returns 0 on success
5504 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5506 u64 val64 = 0, last_gpio_ctrl_val;
5507 struct s2io_nic *sp = netdev_priv(dev);
5508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5511 subid = sp->pdev->subsystem_device;
5512 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5513 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5514 val64 = readq(&bar0->adapter_control);
5515 if (!(val64 & ADAPTER_CNTL_EN)) {
5516 pr_err("Adapter Link down, cannot blink LED\n");
5520 if (sp->id_timer.function == NULL) {
5521 init_timer(&sp->id_timer);
5522 sp->id_timer.function = s2io_phy_id;
5523 sp->id_timer.data = (unsigned long)sp;
5525 mod_timer(&sp->id_timer, jiffies);
5527 msleep_interruptible(data * HZ);
5529 msleep_interruptible(MAX_FLICKER_TIME);
5530 del_timer_sync(&sp->id_timer);
5532 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
5533 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5534 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5540 static void s2io_ethtool_gringparam(struct net_device *dev,
5541 struct ethtool_ringparam *ering)
5543 struct s2io_nic *sp = netdev_priv(dev);
5544 int i, tx_desc_count = 0, rx_desc_count = 0;
5546 if (sp->rxd_mode == RXD_MODE_1)
5547 ering->rx_max_pending = MAX_RX_DESC_1;
5548 else if (sp->rxd_mode == RXD_MODE_3B)
5549 ering->rx_max_pending = MAX_RX_DESC_2;
5551 ering->tx_max_pending = MAX_TX_DESC;
5552 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
5553 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5555 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5556 ering->tx_pending = tx_desc_count;
5558 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
5559 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5561 ering->rx_pending = rx_desc_count;
5563 ering->rx_mini_max_pending = 0;
5564 ering->rx_mini_pending = 0;
5565 if (sp->rxd_mode == RXD_MODE_1)
5566 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5567 else if (sp->rxd_mode == RXD_MODE_3B)
5568 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5569 ering->rx_jumbo_pending = rx_desc_count;
5573 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5574 * @sp : private member of the device structure, which is a pointer to the
5575 * s2io_nic structure.
5576 * @ep : pointer to the structure with pause parameters given by ethtool.
5578 * Returns the Pause frame generation and reception capability of the NIC.
5582 static void s2io_ethtool_getpause_data(struct net_device *dev,
5583 struct ethtool_pauseparam *ep)
5586 struct s2io_nic *sp = netdev_priv(dev);
5587 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5589 val64 = readq(&bar0->rmac_pause_cfg);
5590 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5591 ep->tx_pause = true;
5592 if (val64 & RMAC_PAUSE_RX_ENABLE)
5593 ep->rx_pause = true;
5594 ep->autoneg = false;
5598 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5599 * @sp : private member of the device structure, which is a pointer to the
5600 * s2io_nic structure.
5601 * @ep : pointer to the structure with pause parameters given by ethtool.
5603 * It can be used to set or reset Pause frame generation or reception
5604 * support of the NIC.
5606 * int, returns 0 on Success
5609 static int s2io_ethtool_setpause_data(struct net_device *dev,
5610 struct ethtool_pauseparam *ep)
5613 struct s2io_nic *sp = netdev_priv(dev);
5614 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5616 val64 = readq(&bar0->rmac_pause_cfg);
5618 val64 |= RMAC_PAUSE_GEN_ENABLE;
5620 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5622 val64 |= RMAC_PAUSE_RX_ENABLE;
5624 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5625 writeq(val64, &bar0->rmac_pause_cfg);
5630 * read_eeprom - reads 4 bytes of data from user given offset.
5631 * @sp : private member of the device structure, which is a pointer to the
5632 * s2io_nic structure.
5633 * @off : offset at which the data must be written
5634 * @data : Its an output parameter where the data read at the given
5637 * Will read 4 bytes of data from the user given offset and return the
5639 * NOTE: Will allow to read only part of the EEPROM visible through the
5642 * -1 on failure and 0 on success.
5645 #define S2IO_DEV_ID 5
5646 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5651 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5653 if (sp->device_type == XFRAME_I_DEVICE) {
5654 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5655 I2C_CONTROL_ADDR(off) |
5656 I2C_CONTROL_BYTE_CNT(0x3) |
5658 I2C_CONTROL_CNTL_START;
5659 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5661 while (exit_cnt < 5) {
5662 val64 = readq(&bar0->i2c_control);
5663 if (I2C_CONTROL_CNTL_END(val64)) {
5664 *data = I2C_CONTROL_GET_DATA(val64);
5673 if (sp->device_type == XFRAME_II_DEVICE) {
5674 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5675 SPI_CONTROL_BYTECNT(0x3) |
5676 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5677 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5678 val64 |= SPI_CONTROL_REQ;
5679 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5680 while (exit_cnt < 5) {
5681 val64 = readq(&bar0->spi_control);
5682 if (val64 & SPI_CONTROL_NACK) {
5685 } else if (val64 & SPI_CONTROL_DONE) {
5686 *data = readq(&bar0->spi_data);
5699 * write_eeprom - actually writes the relevant part of the data value.
5700 * @sp : private member of the device structure, which is a pointer to the
5701 * s2io_nic structure.
5702 * @off : offset at which the data must be written
5703 * @data : The data that is to be written
5704 * @cnt : Number of bytes of the data that are actually to be written into
5705 * the Eeprom. (max of 3)
5707 * Actually writes the relevant part of the data value into the Eeprom
5708 * through the I2C bus.
5710 * 0 on success, -1 on failure.
5713 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5715 int exit_cnt = 0, ret = -1;
5717 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5719 if (sp->device_type == XFRAME_I_DEVICE) {
5720 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5721 I2C_CONTROL_ADDR(off) |
5722 I2C_CONTROL_BYTE_CNT(cnt) |
5723 I2C_CONTROL_SET_DATA((u32)data) |
5724 I2C_CONTROL_CNTL_START;
5725 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5727 while (exit_cnt < 5) {
5728 val64 = readq(&bar0->i2c_control);
5729 if (I2C_CONTROL_CNTL_END(val64)) {
5730 if (!(val64 & I2C_CONTROL_NACK))
5739 if (sp->device_type == XFRAME_II_DEVICE) {
5740 int write_cnt = (cnt == 8) ? 0 : cnt;
5741 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5743 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5744 SPI_CONTROL_BYTECNT(write_cnt) |
5745 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5746 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5747 val64 |= SPI_CONTROL_REQ;
5748 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5749 while (exit_cnt < 5) {
5750 val64 = readq(&bar0->spi_control);
5751 if (val64 & SPI_CONTROL_NACK) {
5754 } else if (val64 & SPI_CONTROL_DONE) {
5764 static void s2io_vpd_read(struct s2io_nic *nic)
5768 int i = 0, cnt, fail = 0;
5769 int vpd_addr = 0x80;
5770 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5772 if (nic->device_type == XFRAME_II_DEVICE) {
5773 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5776 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5779 strcpy(nic->serial_num, "NOT AVAILABLE");
5781 vpd_data = kmalloc(256, GFP_KERNEL);
5783 swstats->mem_alloc_fail_cnt++;
5786 swstats->mem_allocated += 256;
5788 for (i = 0; i < 256; i += 4) {
5789 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5790 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5791 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5792 for (cnt = 0; cnt < 5; cnt++) {
5794 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5799 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5803 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5804 (u32 *)&vpd_data[i]);
5808 /* read serial number of adapter */
5809 for (cnt = 0; cnt < 256; cnt++) {
5810 if ((vpd_data[cnt] == 'S') &&
5811 (vpd_data[cnt+1] == 'N') &&
5812 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5813 memset(nic->serial_num, 0, VPD_STRING_LEN);
5814 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5821 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN))
5822 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5824 swstats->mem_freed += 256;
5828 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5829 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5830 * @eeprom : pointer to the user level structure provided by ethtool,
5831 * containing all relevant information.
5832 * @data_buf : user defined value to be written into Eeprom.
5833 * Description: Reads the values stored in the Eeprom at given offset
5834 * for a given length. Stores these values int the input argument data
5835 * buffer 'data_buf' and returns these to the caller (ethtool.)
5840 static int s2io_ethtool_geeprom(struct net_device *dev,
5841 struct ethtool_eeprom *eeprom, u8 * data_buf)
5845 struct s2io_nic *sp = netdev_priv(dev);
5847 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5849 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5850 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5852 for (i = 0; i < eeprom->len; i += 4) {
5853 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5854 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5858 memcpy((data_buf + i), &valid, 4);
5864 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5865 * @sp : private member of the device structure, which is a pointer to the
5866 * s2io_nic structure.
5867 * @eeprom : pointer to the user level structure provided by ethtool,
5868 * containing all relevant information.
5869 * @data_buf ; user defined value to be written into Eeprom.
5871 * Tries to write the user provided value in the Eeprom, at the offset
5872 * given by the user.
5874 * 0 on success, -EFAULT on failure.
5877 static int s2io_ethtool_seeprom(struct net_device *dev,
5878 struct ethtool_eeprom *eeprom,
5881 int len = eeprom->len, cnt = 0;
5882 u64 valid = 0, data;
5883 struct s2io_nic *sp = netdev_priv(dev);
5885 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5887 "ETHTOOL_WRITE_EEPROM Err: "
5888 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5889 (sp->pdev->vendor | (sp->pdev->device << 16)),
5895 data = (u32)data_buf[cnt] & 0x000000FF;
5897 valid = (u32)(data << 24);
5901 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5903 "ETHTOOL_WRITE_EEPROM Err: "
5904 "Cannot write into the specified offset\n");
5915 * s2io_register_test - reads and writes into all clock domains.
5916 * @sp : private member of the device structure, which is a pointer to the
5917 * s2io_nic structure.
5918 * @data : variable that returns the result of each of the test conducted b
5921 * Read and write into all clock domains. The NIC has 3 clock domains,
5922 * see that registers in all the three regions are accessible.
5927 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5929 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5930 u64 val64 = 0, exp_val;
5933 val64 = readq(&bar0->pif_rd_swapper_fb);
5934 if (val64 != 0x123456789abcdefULL) {
5936 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5939 val64 = readq(&bar0->rmac_pause_cfg);
5940 if (val64 != 0xc000ffff00000000ULL) {
5942 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5945 val64 = readq(&bar0->rx_queue_cfg);
5946 if (sp->device_type == XFRAME_II_DEVICE)
5947 exp_val = 0x0404040404040404ULL;
5949 exp_val = 0x0808080808080808ULL;
5950 if (val64 != exp_val) {
5952 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5955 val64 = readq(&bar0->xgxs_efifo_cfg);
5956 if (val64 != 0x000000001923141EULL) {
5958 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5961 val64 = 0x5A5A5A5A5A5A5A5AULL;
5962 writeq(val64, &bar0->xmsi_data);
5963 val64 = readq(&bar0->xmsi_data);
5964 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5966 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5969 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5970 writeq(val64, &bar0->xmsi_data);
5971 val64 = readq(&bar0->xmsi_data);
5972 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5974 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5982 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5983 * @sp : private member of the device structure, which is a pointer to the
5984 * s2io_nic structure.
5985 * @data:variable that returns the result of each of the test conducted by
5988 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5994 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5997 u64 ret_data, org_4F0, org_7F0;
5998 u8 saved_4F0 = 0, saved_7F0 = 0;
5999 struct net_device *dev = sp->dev;
6001 /* Test Write Error at offset 0 */
6002 /* Note that SPI interface allows write access to all areas
6003 * of EEPROM. Hence doing all negative testing only for Xframe I.
6005 if (sp->device_type == XFRAME_I_DEVICE)
6006 if (!write_eeprom(sp, 0, 0, 3))
6009 /* Save current values at offsets 0x4F0 and 0x7F0 */
6010 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6012 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6015 /* Test Write at offset 4f0 */
6016 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
6018 if (read_eeprom(sp, 0x4F0, &ret_data))
6021 if (ret_data != 0x012345) {
6022 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
6023 "Data written %llx Data read %llx\n",
6024 dev->name, (unsigned long long)0x12345,
6025 (unsigned long long)ret_data);
6029 /* Reset the EEPROM data go FFFF */
6030 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6032 /* Test Write Request Error at offset 0x7c */
6033 if (sp->device_type == XFRAME_I_DEVICE)
6034 if (!write_eeprom(sp, 0x07C, 0, 3))
6037 /* Test Write Request at offset 0x7f0 */
6038 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6040 if (read_eeprom(sp, 0x7F0, &ret_data))
6043 if (ret_data != 0x012345) {
6044 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6045 "Data written %llx Data read %llx\n",
6046 dev->name, (unsigned long long)0x12345,
6047 (unsigned long long)ret_data);
6051 /* Reset the EEPROM data go FFFF */
6052 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6054 if (sp->device_type == XFRAME_I_DEVICE) {
6055 /* Test Write Error at offset 0x80 */
6056 if (!write_eeprom(sp, 0x080, 0, 3))
6059 /* Test Write Error at offset 0xfc */
6060 if (!write_eeprom(sp, 0x0FC, 0, 3))
6063 /* Test Write Error at offset 0x100 */
6064 if (!write_eeprom(sp, 0x100, 0, 3))
6067 /* Test Write Error at offset 4ec */
6068 if (!write_eeprom(sp, 0x4EC, 0, 3))
6072 /* Restore values at offsets 0x4F0 and 0x7F0 */
6074 write_eeprom(sp, 0x4F0, org_4F0, 3);
6076 write_eeprom(sp, 0x7F0, org_7F0, 3);
6083 * s2io_bist_test - invokes the MemBist test of the card .
6084 * @sp : private member of the device structure, which is a pointer to the
6085 * s2io_nic structure.
6086 * @data:variable that returns the result of each of the test conducted by
6089 * This invokes the MemBist test of the card. We give around
6090 * 2 secs time for the Test to complete. If it's still not complete
6091 * within this peiod, we consider that the test failed.
6093 * 0 on success and -1 on failure.
6096 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6099 int cnt = 0, ret = -1;
6101 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6102 bist |= PCI_BIST_START;
6103 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6106 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6107 if (!(bist & PCI_BIST_START)) {
6108 *data = (bist & PCI_BIST_CODE_MASK);
6120 * s2io-link_test - verifies the link state of the nic
6121 * @sp ; private member of the device structure, which is a pointer to the
6122 * s2io_nic structure.
6123 * @data: variable that returns the result of each of the test conducted by
6126 * The function verifies the link state of the NIC and updates the input
6127 * argument 'data' appropriately.
6132 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6134 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6137 val64 = readq(&bar0->adapter_status);
6138 if (!(LINK_IS_UP(val64)))
6147 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6148 * @sp - private member of the device structure, which is a pointer to the
6149 * s2io_nic structure.
6150 * @data - variable that returns the result of each of the test
6151 * conducted by the driver.
6153 * This is one of the offline test that tests the read and write
6154 * access to the RldRam chip on the NIC.
6159 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6161 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6163 int cnt, iteration = 0, test_fail = 0;
6165 val64 = readq(&bar0->adapter_control);
6166 val64 &= ~ADAPTER_ECC_EN;
6167 writeq(val64, &bar0->adapter_control);
6169 val64 = readq(&bar0->mc_rldram_test_ctrl);
6170 val64 |= MC_RLDRAM_TEST_MODE;
6171 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6173 val64 = readq(&bar0->mc_rldram_mrs);
6174 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6175 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6177 val64 |= MC_RLDRAM_MRS_ENABLE;
6178 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6180 while (iteration < 2) {
6181 val64 = 0x55555555aaaa0000ULL;
6183 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6184 writeq(val64, &bar0->mc_rldram_test_d0);
6186 val64 = 0xaaaa5a5555550000ULL;
6188 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6189 writeq(val64, &bar0->mc_rldram_test_d1);
6191 val64 = 0x55aaaaaaaa5a0000ULL;
6193 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6194 writeq(val64, &bar0->mc_rldram_test_d2);
6196 val64 = (u64) (0x0000003ffffe0100ULL);
6197 writeq(val64, &bar0->mc_rldram_test_add);
6199 val64 = MC_RLDRAM_TEST_MODE |
6200 MC_RLDRAM_TEST_WRITE |
6202 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6204 for (cnt = 0; cnt < 5; cnt++) {
6205 val64 = readq(&bar0->mc_rldram_test_ctrl);
6206 if (val64 & MC_RLDRAM_TEST_DONE)
6214 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6215 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6217 for (cnt = 0; cnt < 5; cnt++) {
6218 val64 = readq(&bar0->mc_rldram_test_ctrl);
6219 if (val64 & MC_RLDRAM_TEST_DONE)
6227 val64 = readq(&bar0->mc_rldram_test_ctrl);
6228 if (!(val64 & MC_RLDRAM_TEST_PASS))
6236 /* Bring the adapter out of test mode */
6237 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6243 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6244 * @sp : private member of the device structure, which is a pointer to the
6245 * s2io_nic structure.
6246 * @ethtest : pointer to a ethtool command specific structure that will be
6247 * returned to the user.
6248 * @data : variable that returns the result of each of the test
6249 * conducted by the driver.
6251 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6252 * the health of the card.
6257 static void s2io_ethtool_test(struct net_device *dev,
6258 struct ethtool_test *ethtest,
6261 struct s2io_nic *sp = netdev_priv(dev);
6262 int orig_state = netif_running(sp->dev);
6264 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6265 /* Offline Tests. */
6267 s2io_close(sp->dev);
6269 if (s2io_register_test(sp, &data[0]))
6270 ethtest->flags |= ETH_TEST_FL_FAILED;
6274 if (s2io_rldram_test(sp, &data[3]))
6275 ethtest->flags |= ETH_TEST_FL_FAILED;
6279 if (s2io_eeprom_test(sp, &data[1]))
6280 ethtest->flags |= ETH_TEST_FL_FAILED;
6282 if (s2io_bist_test(sp, &data[4]))
6283 ethtest->flags |= ETH_TEST_FL_FAILED;
6292 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6301 if (s2io_link_test(sp, &data[2]))
6302 ethtest->flags |= ETH_TEST_FL_FAILED;
6311 static void s2io_get_ethtool_stats(struct net_device *dev,
6312 struct ethtool_stats *estats,
6316 struct s2io_nic *sp = netdev_priv(dev);
6317 struct stat_block *stats = sp->mac_control.stats_info;
6318 struct swStat *swstats = &stats->sw_stat;
6319 struct xpakStat *xstats = &stats->xpak_stat;
6321 s2io_updt_stats(sp);
6323 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6324 le32_to_cpu(stats->tmac_frms);
6326 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6327 le32_to_cpu(stats->tmac_data_octets);
6328 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6330 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6331 le32_to_cpu(stats->tmac_mcst_frms);
6333 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6334 le32_to_cpu(stats->tmac_bcst_frms);
6335 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6337 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6338 le32_to_cpu(stats->tmac_ttl_octets);
6340 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6341 le32_to_cpu(stats->tmac_ucst_frms);
6343 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6344 le32_to_cpu(stats->tmac_nucst_frms);
6346 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6347 le32_to_cpu(stats->tmac_any_err_frms);
6348 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6349 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6351 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6352 le32_to_cpu(stats->tmac_vld_ip);
6354 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6355 le32_to_cpu(stats->tmac_drop_ip);
6357 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6358 le32_to_cpu(stats->tmac_icmp);
6360 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6361 le32_to_cpu(stats->tmac_rst_tcp);
6362 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6363 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6364 le32_to_cpu(stats->tmac_udp);
6366 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6367 le32_to_cpu(stats->rmac_vld_frms);
6369 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6370 le32_to_cpu(stats->rmac_data_octets);
6371 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6372 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6374 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6375 le32_to_cpu(stats->rmac_vld_mcst_frms);
6377 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6378 le32_to_cpu(stats->rmac_vld_bcst_frms);
6379 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6380 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6381 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6382 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6383 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6385 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6386 le32_to_cpu(stats->rmac_ttl_octets);
6388 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6389 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6391 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6392 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6394 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6395 le32_to_cpu(stats->rmac_discarded_frms);
6397 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6398 << 32 | le32_to_cpu(stats->rmac_drop_events);
6399 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6400 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6402 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6403 le32_to_cpu(stats->rmac_usized_frms);
6405 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6406 le32_to_cpu(stats->rmac_osized_frms);
6408 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6409 le32_to_cpu(stats->rmac_frag_frms);
6411 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6412 le32_to_cpu(stats->rmac_jabber_frms);
6413 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6418 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6420 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6421 le32_to_cpu(stats->rmac_ip);
6422 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6423 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6425 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6426 le32_to_cpu(stats->rmac_drop_ip);
6428 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6429 le32_to_cpu(stats->rmac_icmp);
6430 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6432 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6433 le32_to_cpu(stats->rmac_udp);
6435 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6436 le32_to_cpu(stats->rmac_err_drp_udp);
6437 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6438 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6439 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6440 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6446 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6447 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6448 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6449 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6450 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6451 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6452 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6453 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6455 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6456 le32_to_cpu(stats->rmac_pause_cnt);
6457 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6458 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6460 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6461 le32_to_cpu(stats->rmac_accepted_ip);
6462 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6463 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6464 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6465 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6467 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6468 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6469 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6470 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6471 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6472 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6473 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6474 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6477 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6480 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6482 /* Enhanced statistics exist only for Hercules */
6483 if (sp->device_type == XFRAME_II_DEVICE) {
6485 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6487 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6489 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6490 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6491 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6492 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6493 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6494 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6495 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6496 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6497 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6498 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6499 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6500 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6501 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6502 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6506 tmp_stats[i++] = swstats->single_ecc_errs;
6507 tmp_stats[i++] = swstats->double_ecc_errs;
6508 tmp_stats[i++] = swstats->parity_err_cnt;
6509 tmp_stats[i++] = swstats->serious_err_cnt;
6510 tmp_stats[i++] = swstats->soft_reset_cnt;
6511 tmp_stats[i++] = swstats->fifo_full_cnt;
6512 for (k = 0; k < MAX_RX_RINGS; k++)
6513 tmp_stats[i++] = swstats->ring_full_cnt[k];
6514 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6515 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6516 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6517 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6518 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6519 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6520 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6521 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6522 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6523 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6524 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6525 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6526 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6527 tmp_stats[i++] = swstats->sending_both;
6528 tmp_stats[i++] = swstats->outof_sequence_pkts;
6529 tmp_stats[i++] = swstats->flush_max_pkts;
6530 if (swstats->num_aggregations) {
6531 u64 tmp = swstats->sum_avg_pkts_aggregated;
6534 * Since 64-bit divide does not work on all platforms,
6535 * do repeated subtraction.
6537 while (tmp >= swstats->num_aggregations) {
6538 tmp -= swstats->num_aggregations;
6541 tmp_stats[i++] = count;
6544 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6545 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6546 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6547 tmp_stats[i++] = swstats->mem_allocated;
6548 tmp_stats[i++] = swstats->mem_freed;
6549 tmp_stats[i++] = swstats->link_up_cnt;
6550 tmp_stats[i++] = swstats->link_down_cnt;
6551 tmp_stats[i++] = swstats->link_up_time;
6552 tmp_stats[i++] = swstats->link_down_time;
6554 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6555 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6556 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6557 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6558 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6560 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6561 tmp_stats[i++] = swstats->rx_abort_cnt;
6562 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6563 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6564 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6565 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6566 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6567 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6568 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6569 tmp_stats[i++] = swstats->tda_err_cnt;
6570 tmp_stats[i++] = swstats->pfc_err_cnt;
6571 tmp_stats[i++] = swstats->pcc_err_cnt;
6572 tmp_stats[i++] = swstats->tti_err_cnt;
6573 tmp_stats[i++] = swstats->tpa_err_cnt;
6574 tmp_stats[i++] = swstats->sm_err_cnt;
6575 tmp_stats[i++] = swstats->lso_err_cnt;
6576 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6577 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6578 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6579 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6580 tmp_stats[i++] = swstats->rc_err_cnt;
6581 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6582 tmp_stats[i++] = swstats->rpa_err_cnt;
6583 tmp_stats[i++] = swstats->rda_err_cnt;
6584 tmp_stats[i++] = swstats->rti_err_cnt;
6585 tmp_stats[i++] = swstats->mc_err_cnt;
6588 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6590 return XENA_REG_SPACE;
6594 static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
6596 struct s2io_nic *sp = netdev_priv(dev);
6601 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
6603 struct s2io_nic *sp = netdev_priv(dev);
6613 static int s2io_get_eeprom_len(struct net_device *dev)
6615 return XENA_EEPROM_SPACE;
6618 static int s2io_get_sset_count(struct net_device *dev, int sset)
6620 struct s2io_nic *sp = netdev_priv(dev);
6624 return S2IO_TEST_LEN;
6626 switch (sp->device_type) {
6627 case XFRAME_I_DEVICE:
6628 return XFRAME_I_STAT_LEN;
6629 case XFRAME_II_DEVICE:
6630 return XFRAME_II_STAT_LEN;
6639 static void s2io_ethtool_get_strings(struct net_device *dev,
6640 u32 stringset, u8 *data)
6643 struct s2io_nic *sp = netdev_priv(dev);
6645 switch (stringset) {
6647 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6650 stat_size = sizeof(ethtool_xena_stats_keys);
6651 memcpy(data, ðtool_xena_stats_keys, stat_size);
6652 if (sp->device_type == XFRAME_II_DEVICE) {
6653 memcpy(data + stat_size,
6654 ðtool_enhanced_stats_keys,
6655 sizeof(ethtool_enhanced_stats_keys));
6656 stat_size += sizeof(ethtool_enhanced_stats_keys);
6659 memcpy(data + stat_size, ðtool_driver_stats_keys,
6660 sizeof(ethtool_driver_stats_keys));
6664 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
6667 dev->features |= NETIF_F_IP_CSUM;
6669 dev->features &= ~NETIF_F_IP_CSUM;
6674 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6676 return (dev->features & NETIF_F_TSO) != 0;
6678 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6681 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6683 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6688 static const struct ethtool_ops netdev_ethtool_ops = {
6689 .get_settings = s2io_ethtool_gset,
6690 .set_settings = s2io_ethtool_sset,
6691 .get_drvinfo = s2io_ethtool_gdrvinfo,
6692 .get_regs_len = s2io_ethtool_get_regs_len,
6693 .get_regs = s2io_ethtool_gregs,
6694 .get_link = ethtool_op_get_link,
6695 .get_eeprom_len = s2io_get_eeprom_len,
6696 .get_eeprom = s2io_ethtool_geeprom,
6697 .set_eeprom = s2io_ethtool_seeprom,
6698 .get_ringparam = s2io_ethtool_gringparam,
6699 .get_pauseparam = s2io_ethtool_getpause_data,
6700 .set_pauseparam = s2io_ethtool_setpause_data,
6701 .get_rx_csum = s2io_ethtool_get_rx_csum,
6702 .set_rx_csum = s2io_ethtool_set_rx_csum,
6703 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
6704 .set_sg = ethtool_op_set_sg,
6705 .get_tso = s2io_ethtool_op_get_tso,
6706 .set_tso = s2io_ethtool_op_set_tso,
6707 .set_ufo = ethtool_op_set_ufo,
6708 .self_test = s2io_ethtool_test,
6709 .get_strings = s2io_ethtool_get_strings,
6710 .phys_id = s2io_ethtool_idnic,
6711 .get_ethtool_stats = s2io_get_ethtool_stats,
6712 .get_sset_count = s2io_get_sset_count,
6716 * s2io_ioctl - Entry point for the Ioctl
6717 * @dev : Device pointer.
6718 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6719 * a proprietary structure used to pass information to the driver.
6720 * @cmd : This is used to distinguish between the different commands that
6721 * can be passed to the IOCTL functions.
6723 * Currently there are no special functionality supported in IOCTL, hence
6724 * function always return EOPNOTSUPPORTED
6727 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6733 * s2io_change_mtu - entry point to change MTU size for the device.
6734 * @dev : device pointer.
6735 * @new_mtu : the new MTU size for the device.
6736 * Description: A driver entry point to change MTU size for the device.
6737 * Before changing the MTU the device must be stopped.
6739 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6743 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6745 struct s2io_nic *sp = netdev_priv(dev);
6748 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6749 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6754 if (netif_running(dev)) {
6755 s2io_stop_all_tx_queue(sp);
6757 ret = s2io_card_up(sp);
6759 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6763 s2io_wake_all_tx_queue(sp);
6764 } else { /* Device is down */
6765 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6766 u64 val64 = new_mtu;
6768 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6775 * s2io_set_link - Set the LInk status
6776 * @data: long pointer to device private structue
6777 * Description: Sets the link status for the adapter
6780 static void s2io_set_link(struct work_struct *work)
6782 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6784 struct net_device *dev = nic->dev;
6785 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6791 if (!netif_running(dev))
6794 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6795 /* The card is being reset, no point doing anything */
6799 subid = nic->pdev->subsystem_device;
6800 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6802 * Allow a small delay for the NICs self initiated
6803 * cleanup to complete.
6808 val64 = readq(&bar0->adapter_status);
6809 if (LINK_IS_UP(val64)) {
6810 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6811 if (verify_xena_quiescence(nic)) {
6812 val64 = readq(&bar0->adapter_control);
6813 val64 |= ADAPTER_CNTL_EN;
6814 writeq(val64, &bar0->adapter_control);
6815 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6816 nic->device_type, subid)) {
6817 val64 = readq(&bar0->gpio_control);
6818 val64 |= GPIO_CTRL_GPIO_0;
6819 writeq(val64, &bar0->gpio_control);
6820 val64 = readq(&bar0->gpio_control);
6822 val64 |= ADAPTER_LED_ON;
6823 writeq(val64, &bar0->adapter_control);
6825 nic->device_enabled_once = true;
6828 "%s: Error: device is not Quiescent\n",
6830 s2io_stop_all_tx_queue(nic);
6833 val64 = readq(&bar0->adapter_control);
6834 val64 |= ADAPTER_LED_ON;
6835 writeq(val64, &bar0->adapter_control);
6836 s2io_link(nic, LINK_UP);
6838 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6840 val64 = readq(&bar0->gpio_control);
6841 val64 &= ~GPIO_CTRL_GPIO_0;
6842 writeq(val64, &bar0->gpio_control);
6843 val64 = readq(&bar0->gpio_control);
6846 val64 = readq(&bar0->adapter_control);
6847 val64 = val64 & (~ADAPTER_LED_ON);
6848 writeq(val64, &bar0->adapter_control);
6849 s2io_link(nic, LINK_DOWN);
6851 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6857 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6859 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6860 u64 *temp2, int size)
6862 struct net_device *dev = sp->dev;
6863 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6865 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6866 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6869 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6871 * As Rx frame are not going to be processed,
6872 * using same mapped address for the Rxd
6875 rxdp1->Buffer0_ptr = *temp0;
6877 *skb = dev_alloc_skb(size);
6880 "%s: Out of memory to allocate %s\n",
6881 dev->name, "1 buf mode SKBs");
6882 stats->mem_alloc_fail_cnt++;
6885 stats->mem_allocated += (*skb)->truesize;
6886 /* storing the mapped addr in a temp variable
6887 * such it will be used for next rxd whose
6888 * Host Control is NULL
6890 rxdp1->Buffer0_ptr = *temp0 =
6891 pci_map_single(sp->pdev, (*skb)->data,
6892 size - NET_IP_ALIGN,
6893 PCI_DMA_FROMDEVICE);
6894 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6895 goto memalloc_failed;
6896 rxdp->Host_Control = (unsigned long) (*skb);
6898 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6899 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6900 /* Two buffer Mode */
6902 rxdp3->Buffer2_ptr = *temp2;
6903 rxdp3->Buffer0_ptr = *temp0;
6904 rxdp3->Buffer1_ptr = *temp1;
6906 *skb = dev_alloc_skb(size);
6909 "%s: Out of memory to allocate %s\n",
6912 stats->mem_alloc_fail_cnt++;
6915 stats->mem_allocated += (*skb)->truesize;
6916 rxdp3->Buffer2_ptr = *temp2 =
6917 pci_map_single(sp->pdev, (*skb)->data,
6919 PCI_DMA_FROMDEVICE);
6920 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6921 goto memalloc_failed;
6922 rxdp3->Buffer0_ptr = *temp0 =
6923 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6924 PCI_DMA_FROMDEVICE);
6925 if (pci_dma_mapping_error(sp->pdev,
6926 rxdp3->Buffer0_ptr)) {
6927 pci_unmap_single(sp->pdev,
6928 (dma_addr_t)rxdp3->Buffer2_ptr,
6930 PCI_DMA_FROMDEVICE);
6931 goto memalloc_failed;
6933 rxdp->Host_Control = (unsigned long) (*skb);
6935 /* Buffer-1 will be dummy buffer not used */
6936 rxdp3->Buffer1_ptr = *temp1 =
6937 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6938 PCI_DMA_FROMDEVICE);
6939 if (pci_dma_mapping_error(sp->pdev,
6940 rxdp3->Buffer1_ptr)) {
6941 pci_unmap_single(sp->pdev,
6942 (dma_addr_t)rxdp3->Buffer0_ptr,
6943 BUF0_LEN, PCI_DMA_FROMDEVICE);
6944 pci_unmap_single(sp->pdev,
6945 (dma_addr_t)rxdp3->Buffer2_ptr,
6947 PCI_DMA_FROMDEVICE);
6948 goto memalloc_failed;
6955 stats->pci_map_fail_cnt++;
6956 stats->mem_freed += (*skb)->truesize;
6957 dev_kfree_skb(*skb);
6961 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6964 struct net_device *dev = sp->dev;
6965 if (sp->rxd_mode == RXD_MODE_1) {
6966 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6967 } else if (sp->rxd_mode == RXD_MODE_3B) {
6968 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6969 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6970 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6974 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6976 int i, j, k, blk_cnt = 0, size;
6977 struct config_param *config = &sp->config;
6978 struct mac_info *mac_control = &sp->mac_control;
6979 struct net_device *dev = sp->dev;
6980 struct RxD_t *rxdp = NULL;
6981 struct sk_buff *skb = NULL;
6982 struct buffAdd *ba = NULL;
6983 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6985 /* Calculate the size based on ring mode */
6986 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6987 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6988 if (sp->rxd_mode == RXD_MODE_1)
6989 size += NET_IP_ALIGN;
6990 else if (sp->rxd_mode == RXD_MODE_3B)
6991 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6993 for (i = 0; i < config->rx_ring_num; i++) {
6994 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6995 struct ring_info *ring = &mac_control->rings[i];
6997 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6999 for (j = 0; j < blk_cnt; j++) {
7000 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
7001 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7002 if (sp->rxd_mode == RXD_MODE_3B)
7003 ba = &ring->ba[j][k];
7004 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7012 set_rxd_buffer_size(sp, rxdp, size);
7014 /* flip the Ownership bit to Hardware */
7015 rxdp->Control_1 |= RXD_OWN_XENA;
7023 static int s2io_add_isr(struct s2io_nic *sp)
7026 struct net_device *dev = sp->dev;
7029 if (sp->config.intr_type == MSI_X)
7030 ret = s2io_enable_msi_x(sp);
7032 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
7033 sp->config.intr_type = INTA;
7037 * Store the values of the MSIX table in
7038 * the struct s2io_nic structure
7040 store_xmsi_data(sp);
7042 /* After proper initialization of H/W, register ISR */
7043 if (sp->config.intr_type == MSI_X) {
7044 int i, msix_rx_cnt = 0;
7046 for (i = 0; i < sp->num_entries; i++) {
7047 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7048 if (sp->s2io_entries[i].type ==
7050 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7052 err = request_irq(sp->entries[i].vector,
7053 s2io_msix_ring_handle,
7056 sp->s2io_entries[i].arg);
7057 } else if (sp->s2io_entries[i].type ==
7059 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7061 err = request_irq(sp->entries[i].vector,
7062 s2io_msix_fifo_handle,
7065 sp->s2io_entries[i].arg);
7068 /* if either data or addr is zero print it. */
7069 if (!(sp->msix_info[i].addr &&
7070 sp->msix_info[i].data)) {
7072 "%s @Addr:0x%llx Data:0x%llx\n",
7074 (unsigned long long)
7075 sp->msix_info[i].addr,
7076 (unsigned long long)
7077 ntohl(sp->msix_info[i].data));
7081 remove_msix_isr(sp);
7084 "%s:MSI-X-%d registration "
7085 "failed\n", dev->name, i);
7088 "%s: Defaulting to INTA\n",
7090 sp->config.intr_type = INTA;
7093 sp->s2io_entries[i].in_use =
7094 MSIX_REGISTERED_SUCCESS;
7098 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7100 "MSI-X-TX entries enabled through alarm vector\n");
7103 if (sp->config.intr_type == INTA) {
7104 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7107 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7115 static void s2io_rem_isr(struct s2io_nic *sp)
7117 if (sp->config.intr_type == MSI_X)
7118 remove_msix_isr(sp);
7120 remove_inta_isr(sp);
7123 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7126 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7127 register u64 val64 = 0;
7128 struct config_param *config;
7129 config = &sp->config;
7131 if (!is_s2io_card_up(sp))
7134 del_timer_sync(&sp->alarm_timer);
7135 /* If s2io_set_link task is executing, wait till it completes. */
7136 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7138 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7141 if (sp->config.napi) {
7143 if (config->intr_type == MSI_X) {
7144 for (; off < sp->config.rx_ring_num; off++)
7145 napi_disable(&sp->mac_control.rings[off].napi);
7148 napi_disable(&sp->napi);
7151 /* disable Tx and Rx traffic on the NIC */
7157 /* stop the tx queue, indicate link down */
7158 s2io_link(sp, LINK_DOWN);
7160 /* Check if the device is Quiescent and then Reset the NIC */
7162 /* As per the HW requirement we need to replenish the
7163 * receive buffer to avoid the ring bump. Since there is
7164 * no intention of processing the Rx frame at this pointwe are
7165 * just settting the ownership bit of rxd in Each Rx
7166 * ring to HW and set the appropriate buffer size
7167 * based on the ring mode
7169 rxd_owner_bit_reset(sp);
7171 val64 = readq(&bar0->adapter_status);
7172 if (verify_xena_quiescence(sp)) {
7173 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7180 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7181 "adapter status reads 0x%llx\n",
7182 (unsigned long long)val64);
7189 /* Free all Tx buffers */
7190 free_tx_buffers(sp);
7192 /* Free all Rx buffers */
7193 free_rx_buffers(sp);
7195 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7198 static void s2io_card_down(struct s2io_nic *sp)
7200 do_s2io_card_down(sp, 1);
7203 static int s2io_card_up(struct s2io_nic *sp)
7206 struct config_param *config;
7207 struct mac_info *mac_control;
7208 struct net_device *dev = (struct net_device *)sp->dev;
7211 /* Initialize the H/W I/O registers */
7214 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7222 * Initializing the Rx buffers. For now we are considering only 1
7223 * Rx ring and initializing buffers into 30 Rx blocks
7225 config = &sp->config;
7226 mac_control = &sp->mac_control;
7228 for (i = 0; i < config->rx_ring_num; i++) {
7229 struct ring_info *ring = &mac_control->rings[i];
7231 ring->mtu = dev->mtu;
7232 ret = fill_rx_buffers(sp, ring, 1);
7234 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7237 free_rx_buffers(sp);
7240 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7241 ring->rx_bufs_left);
7244 /* Initialise napi */
7246 if (config->intr_type == MSI_X) {
7247 for (i = 0; i < sp->config.rx_ring_num; i++)
7248 napi_enable(&sp->mac_control.rings[i].napi);
7250 napi_enable(&sp->napi);
7254 /* Maintain the state prior to the open */
7255 if (sp->promisc_flg)
7256 sp->promisc_flg = 0;
7257 if (sp->m_cast_flg) {
7259 sp->all_multi_pos = 0;
7262 /* Setting its receive mode */
7263 s2io_set_multicast(dev);
7266 /* Initialize max aggregatable pkts per session based on MTU */
7267 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7268 /* Check if we can use (if specified) user provided value */
7269 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7270 sp->lro_max_aggr_per_sess = lro_max_pkts;
7273 /* Enable Rx Traffic and interrupts on the NIC */
7274 if (start_nic(sp)) {
7275 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7277 free_rx_buffers(sp);
7281 /* Add interrupt service routine */
7282 if (s2io_add_isr(sp) != 0) {
7283 if (sp->config.intr_type == MSI_X)
7286 free_rx_buffers(sp);
7290 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7292 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7294 /* Enable select interrupts */
7295 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7296 if (sp->config.intr_type != INTA) {
7297 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7298 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7300 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7301 interruptible |= TX_PIC_INTR;
7302 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7309 * s2io_restart_nic - Resets the NIC.
7310 * @data : long pointer to the device private structure
7312 * This function is scheduled to be run by the s2io_tx_watchdog
7313 * function after 0.5 secs to reset the NIC. The idea is to reduce
7314 * the run time of the watch dog routine which is run holding a
7318 static void s2io_restart_nic(struct work_struct *work)
7320 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7321 struct net_device *dev = sp->dev;
7325 if (!netif_running(dev))
7329 if (s2io_card_up(sp)) {
7330 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7332 s2io_wake_all_tx_queue(sp);
7333 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7339 * s2io_tx_watchdog - Watchdog for transmit side.
7340 * @dev : Pointer to net device structure
7342 * This function is triggered if the Tx Queue is stopped
7343 * for a pre-defined amount of time when the Interface is still up.
7344 * If the Interface is jammed in such a situation, the hardware is
7345 * reset (by s2io_close) and restarted again (by s2io_open) to
7346 * overcome any problem that might have been caused in the hardware.
7351 static void s2io_tx_watchdog(struct net_device *dev)
7353 struct s2io_nic *sp = netdev_priv(dev);
7354 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7356 if (netif_carrier_ok(dev)) {
7357 swstats->watchdog_timer_cnt++;
7358 schedule_work(&sp->rst_timer_task);
7359 swstats->soft_reset_cnt++;
7364 * rx_osm_handler - To perform some OS related operations on SKB.
7365 * @sp: private member of the device structure,pointer to s2io_nic structure.
7366 * @skb : the socket buffer pointer.
7367 * @len : length of the packet
7368 * @cksum : FCS checksum of the frame.
7369 * @ring_no : the ring from which this RxD was extracted.
7371 * This function is called by the Rx interrupt serivce routine to perform
7372 * some OS related operations on the SKB before passing it to the upper
7373 * layers. It mainly checks if the checksum is OK, if so adds it to the
7374 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7375 * to the upper layer. If the checksum is wrong, it increments the Rx
7376 * packet error count, frees the SKB and returns error.
7378 * SUCCESS on success and -1 on failure.
7380 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7382 struct s2io_nic *sp = ring_data->nic;
7383 struct net_device *dev = (struct net_device *)ring_data->dev;
7384 struct sk_buff *skb = (struct sk_buff *)
7385 ((unsigned long)rxdp->Host_Control);
7386 int ring_no = ring_data->ring_no;
7387 u16 l3_csum, l4_csum;
7388 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7389 struct lro *uninitialized_var(lro);
7391 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7396 /* Check for parity error */
7398 swstats->parity_err_cnt++;
7400 err_mask = err >> 48;
7403 swstats->rx_parity_err_cnt++;
7407 swstats->rx_abort_cnt++;
7411 swstats->rx_parity_abort_cnt++;
7415 swstats->rx_rda_fail_cnt++;
7419 swstats->rx_unkn_prot_cnt++;
7423 swstats->rx_fcs_err_cnt++;
7427 swstats->rx_buf_size_err_cnt++;
7431 swstats->rx_rxd_corrupt_cnt++;
7435 swstats->rx_unkn_err_cnt++;
7439 * Drop the packet if bad transfer code. Exception being
7440 * 0x5, which could be due to unsupported IPv6 extension header.
7441 * In this case, we let stack handle the packet.
7442 * Note that in this case, since checksum will be incorrect,
7443 * stack will validate the same.
7445 if (err_mask != 0x5) {
7446 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7447 dev->name, err_mask);
7448 dev->stats.rx_crc_errors++;
7452 ring_data->rx_bufs_left -= 1;
7453 rxdp->Host_Control = 0;
7458 /* Updating statistics */
7459 ring_data->rx_packets++;
7460 rxdp->Host_Control = 0;
7461 if (sp->rxd_mode == RXD_MODE_1) {
7462 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7464 ring_data->rx_bytes += len;
7467 } else if (sp->rxd_mode == RXD_MODE_3B) {
7468 int get_block = ring_data->rx_curr_get_info.block_index;
7469 int get_off = ring_data->rx_curr_get_info.offset;
7470 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7471 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7472 unsigned char *buff = skb_push(skb, buf0_len);
7474 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7475 ring_data->rx_bytes += buf0_len + buf2_len;
7476 memcpy(buff, ba->ba_0, buf0_len);
7477 skb_put(skb, buf2_len);
7480 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7481 ((!ring_data->lro) ||
7482 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7484 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7485 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7486 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7488 * NIC verifies if the Checksum of the received
7489 * frame is Ok or not and accordingly returns
7490 * a flag in the RxD.
7492 skb->ip_summed = CHECKSUM_UNNECESSARY;
7493 if (ring_data->lro) {
7498 ret = s2io_club_tcp_session(ring_data,
7503 case 3: /* Begin anew */
7506 case 1: /* Aggregate */
7507 lro_append_pkt(sp, lro, skb, tcp_len);
7509 case 4: /* Flush session */
7510 lro_append_pkt(sp, lro, skb, tcp_len);
7511 queue_rx_frame(lro->parent,
7513 clear_lro_session(lro);
7514 swstats->flush_max_pkts++;
7516 case 2: /* Flush both */
7517 lro->parent->data_len = lro->frags_len;
7518 swstats->sending_both++;
7519 queue_rx_frame(lro->parent,
7521 clear_lro_session(lro);
7523 case 0: /* sessions exceeded */
7524 case -1: /* non-TCP or not L2 aggregatable */
7526 * First pkt in session not
7527 * L3/L4 aggregatable
7532 "%s: Samadhana!!\n",
7539 * Packet with erroneous checksum, let the
7540 * upper layers deal with it.
7542 skb->ip_summed = CHECKSUM_NONE;
7545 skb->ip_summed = CHECKSUM_NONE;
7547 swstats->mem_freed += skb->truesize;
7549 skb_record_rx_queue(skb, ring_no);
7550 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7552 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7557 * s2io_link - stops/starts the Tx queue.
7558 * @sp : private member of the device structure, which is a pointer to the
7559 * s2io_nic structure.
7560 * @link : inidicates whether link is UP/DOWN.
7562 * This function stops/starts the Tx queue depending on whether the link
7563 * status of the NIC is is down or up. This is called by the Alarm
7564 * interrupt handler whenever a link change interrupt comes up.
7569 static void s2io_link(struct s2io_nic *sp, int link)
7571 struct net_device *dev = (struct net_device *)sp->dev;
7572 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7574 if (link != sp->last_link_state) {
7576 if (link == LINK_DOWN) {
7577 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7578 s2io_stop_all_tx_queue(sp);
7579 netif_carrier_off(dev);
7580 if (swstats->link_up_cnt)
7581 swstats->link_up_time =
7582 jiffies - sp->start_time;
7583 swstats->link_down_cnt++;
7585 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7586 if (swstats->link_down_cnt)
7587 swstats->link_down_time =
7588 jiffies - sp->start_time;
7589 swstats->link_up_cnt++;
7590 netif_carrier_on(dev);
7591 s2io_wake_all_tx_queue(sp);
7594 sp->last_link_state = link;
7595 sp->start_time = jiffies;
7599 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7600 * @sp : private member of the device structure, which is a pointer to the
7601 * s2io_nic structure.
7603 * This function initializes a few of the PCI and PCI-X configuration registers
7604 * with recommended values.
7609 static void s2io_init_pci(struct s2io_nic *sp)
7611 u16 pci_cmd = 0, pcix_cmd = 0;
7613 /* Enable Data Parity Error Recovery in PCI-X command register. */
7614 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7616 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7618 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7621 /* Set the PErr Response bit in PCI command register. */
7622 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7623 pci_write_config_word(sp->pdev, PCI_COMMAND,
7624 (pci_cmd | PCI_COMMAND_PARITY));
7625 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7628 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7631 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7632 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7633 "(%d) not supported\n", tx_fifo_num);
7635 if (tx_fifo_num < 1)
7638 tx_fifo_num = MAX_TX_FIFOS;
7640 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7644 *dev_multiq = multiq;
7646 if (tx_steering_type && (1 == tx_fifo_num)) {
7647 if (tx_steering_type != TX_DEFAULT_STEERING)
7649 "Tx steering is not supported with "
7650 "one fifo. Disabling Tx steering.\n");
7651 tx_steering_type = NO_STEERING;
7654 if ((tx_steering_type < NO_STEERING) ||
7655 (tx_steering_type > TX_DEFAULT_STEERING)) {
7657 "Requested transmit steering not supported\n");
7658 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7659 tx_steering_type = NO_STEERING;
7662 if (rx_ring_num > MAX_RX_RINGS) {
7664 "Requested number of rx rings not supported\n");
7665 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7667 rx_ring_num = MAX_RX_RINGS;
7670 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7671 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7672 "Defaulting to INTA\n");
7673 *dev_intr_type = INTA;
7676 if ((*dev_intr_type == MSI_X) &&
7677 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7678 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7679 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7680 "Defaulting to INTA\n");
7681 *dev_intr_type = INTA;
7684 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7685 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7686 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7693 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7694 * or Traffic class respectively.
7695 * @nic: device private variable
7696 * Description: The function configures the receive steering to
7697 * desired receive ring.
7698 * Return Value: SUCCESS on success and
7699 * '-1' on failure (endian settings incorrect).
7701 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7703 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7704 register u64 val64 = 0;
7706 if (ds_codepoint > 63)
7709 val64 = RTS_DS_MEM_DATA(ring);
7710 writeq(val64, &bar0->rts_ds_mem_data);
7712 val64 = RTS_DS_MEM_CTRL_WE |
7713 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7714 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7716 writeq(val64, &bar0->rts_ds_mem_ctrl);
7718 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7719 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7723 static const struct net_device_ops s2io_netdev_ops = {
7724 .ndo_open = s2io_open,
7725 .ndo_stop = s2io_close,
7726 .ndo_get_stats = s2io_get_stats,
7727 .ndo_start_xmit = s2io_xmit,
7728 .ndo_validate_addr = eth_validate_addr,
7729 .ndo_set_multicast_list = s2io_set_multicast,
7730 .ndo_do_ioctl = s2io_ioctl,
7731 .ndo_set_mac_address = s2io_set_mac_addr,
7732 .ndo_change_mtu = s2io_change_mtu,
7733 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7734 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7735 .ndo_tx_timeout = s2io_tx_watchdog,
7736 #ifdef CONFIG_NET_POLL_CONTROLLER
7737 .ndo_poll_controller = s2io_netpoll,
7742 * s2io_init_nic - Initialization of the adapter .
7743 * @pdev : structure containing the PCI related information of the device.
7744 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7746 * The function initializes an adapter identified by the pci_dec structure.
7747 * All OS related initialization including memory and device structure and
7748 * initlaization of the device private variable is done. Also the swapper
7749 * control register is initialized to enable read and write into the I/O
7750 * registers of the device.
7752 * returns 0 on success and negative on failure.
7755 static int __devinit
7756 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7758 struct s2io_nic *sp;
7759 struct net_device *dev;
7761 int dma_flag = false;
7762 u32 mac_up, mac_down;
7763 u64 val64 = 0, tmp64 = 0;
7764 struct XENA_dev_config __iomem *bar0 = NULL;
7766 struct config_param *config;
7767 struct mac_info *mac_control;
7769 u8 dev_intr_type = intr_type;
7772 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7776 ret = pci_enable_device(pdev);
7779 "%s: pci_enable_device failed\n", __func__);
7783 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7784 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7786 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7788 "Unable to obtain 64bit DMA "
7789 "for consistent allocations\n");
7790 pci_disable_device(pdev);
7793 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7794 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7796 pci_disable_device(pdev);
7799 ret = pci_request_regions(pdev, s2io_driver_name);
7801 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7803 pci_disable_device(pdev);
7807 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7809 dev = alloc_etherdev(sizeof(struct s2io_nic));
7811 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7812 pci_disable_device(pdev);
7813 pci_release_regions(pdev);
7817 pci_set_master(pdev);
7818 pci_set_drvdata(pdev, dev);
7819 SET_NETDEV_DEV(dev, &pdev->dev);
7821 /* Private member variable initialized to s2io NIC structure */
7822 sp = netdev_priv(dev);
7823 memset(sp, 0, sizeof(struct s2io_nic));
7826 sp->high_dma_flag = dma_flag;
7827 sp->device_enabled_once = false;
7828 if (rx_ring_mode == 1)
7829 sp->rxd_mode = RXD_MODE_1;
7830 if (rx_ring_mode == 2)
7831 sp->rxd_mode = RXD_MODE_3B;
7833 sp->config.intr_type = dev_intr_type;
7835 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7836 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7837 sp->device_type = XFRAME_II_DEVICE;
7839 sp->device_type = XFRAME_I_DEVICE;
7841 sp->lro = lro_enable;
7843 /* Initialize some PCI/PCI-X fields of the NIC. */
7847 * Setting the device configuration parameters.
7848 * Most of these parameters can be specified by the user during
7849 * module insertion as they are module loadable parameters. If
7850 * these parameters are not not specified during load time, they
7851 * are initialized with default values.
7853 config = &sp->config;
7854 mac_control = &sp->mac_control;
7856 config->napi = napi;
7857 config->tx_steering_type = tx_steering_type;
7859 /* Tx side parameters. */
7860 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7861 config->tx_fifo_num = MAX_TX_FIFOS;
7863 config->tx_fifo_num = tx_fifo_num;
7865 /* Initialize the fifos used for tx steering */
7866 if (config->tx_fifo_num < 5) {
7867 if (config->tx_fifo_num == 1)
7868 sp->total_tcp_fifos = 1;
7870 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7871 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7872 sp->total_udp_fifos = 1;
7873 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7875 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7876 FIFO_OTHER_MAX_NUM);
7877 sp->udp_fifo_idx = sp->total_tcp_fifos;
7878 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7879 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7882 config->multiq = dev_multiq;
7883 for (i = 0; i < config->tx_fifo_num; i++) {
7884 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7886 tx_cfg->fifo_len = tx_fifo_len[i];
7887 tx_cfg->fifo_priority = i;
7890 /* mapping the QoS priority to the configured fifos */
7891 for (i = 0; i < MAX_TX_FIFOS; i++)
7892 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7894 /* map the hashing selector table to the configured fifos */
7895 for (i = 0; i < config->tx_fifo_num; i++)
7896 sp->fifo_selector[i] = fifo_selector[i];
7899 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7900 for (i = 0; i < config->tx_fifo_num; i++) {
7901 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7903 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7904 if (tx_cfg->fifo_len < 65) {
7905 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7909 /* + 2 because one Txd for skb->data and one Txd for UFO */
7910 config->max_txds = MAX_SKB_FRAGS + 2;
7912 /* Rx side parameters. */
7913 config->rx_ring_num = rx_ring_num;
7914 for (i = 0; i < config->rx_ring_num; i++) {
7915 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7916 struct ring_info *ring = &mac_control->rings[i];
7918 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7919 rx_cfg->ring_priority = i;
7920 ring->rx_bufs_left = 0;
7921 ring->rxd_mode = sp->rxd_mode;
7922 ring->rxd_count = rxd_count[sp->rxd_mode];
7923 ring->pdev = sp->pdev;
7924 ring->dev = sp->dev;
7927 for (i = 0; i < rx_ring_num; i++) {
7928 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7930 rx_cfg->ring_org = RING_ORG_BUFF1;
7931 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7934 /* Setting Mac Control parameters */
7935 mac_control->rmac_pause_time = rmac_pause_time;
7936 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7937 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7940 /* initialize the shared memory used by the NIC and the host */
7941 if (init_shared_mem(sp)) {
7942 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7944 goto mem_alloc_failed;
7947 sp->bar0 = pci_ioremap_bar(pdev, 0);
7949 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7952 goto bar0_remap_failed;
7955 sp->bar1 = pci_ioremap_bar(pdev, 2);
7957 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7960 goto bar1_remap_failed;
7963 dev->irq = pdev->irq;
7964 dev->base_addr = (unsigned long)sp->bar0;
7966 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7967 for (j = 0; j < MAX_TX_FIFOS; j++) {
7968 mac_control->tx_FIFO_start[j] =
7969 (struct TxFIFO_element __iomem *)
7970 (sp->bar1 + (j * 0x00020000));
7973 /* Driver entry points */
7974 dev->netdev_ops = &s2io_netdev_ops;
7975 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7976 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7978 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7979 if (sp->high_dma_flag == true)
7980 dev->features |= NETIF_F_HIGHDMA;
7981 dev->features |= NETIF_F_TSO;
7982 dev->features |= NETIF_F_TSO6;
7983 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
7984 dev->features |= NETIF_F_UFO;
7985 dev->features |= NETIF_F_HW_CSUM;
7987 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7988 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7989 INIT_WORK(&sp->set_link_task, s2io_set_link);
7991 pci_save_state(sp->pdev);
7993 /* Setting swapper control on the NIC, for proper reset operation */
7994 if (s2io_set_swapper(sp)) {
7995 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7998 goto set_swap_failed;
8001 /* Verify if the Herc works on the slot its placed into */
8002 if (sp->device_type & XFRAME_II_DEVICE) {
8003 mode = s2io_verify_pci_mode(sp);
8005 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8008 goto set_swap_failed;
8012 if (sp->config.intr_type == MSI_X) {
8013 sp->num_entries = config->rx_ring_num + 1;
8014 ret = s2io_enable_msi_x(sp);
8017 ret = s2io_test_msi(sp);
8018 /* rollback MSI-X, will re-enable during add_isr() */
8019 remove_msix_isr(sp);
8024 "MSI-X requested but failed to enable\n");
8025 sp->config.intr_type = INTA;
8029 if (config->intr_type == MSI_X) {
8030 for (i = 0; i < config->rx_ring_num ; i++) {
8031 struct ring_info *ring = &mac_control->rings[i];
8033 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8036 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8039 /* Not needed for Herc */
8040 if (sp->device_type & XFRAME_I_DEVICE) {
8042 * Fix for all "FFs" MAC address problems observed on
8045 fix_mac_address(sp);
8050 * MAC address initialization.
8051 * For now only one mac address will be read and used.
8054 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8055 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8056 writeq(val64, &bar0->rmac_addr_cmd_mem);
8057 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8058 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8060 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8061 mac_down = (u32)tmp64;
8062 mac_up = (u32) (tmp64 >> 32);
8064 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8065 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8066 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8067 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8068 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8069 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8071 /* Set the factory defined MAC address initially */
8072 dev->addr_len = ETH_ALEN;
8073 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8074 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8076 /* initialize number of multicast & unicast MAC entries variables */
8077 if (sp->device_type == XFRAME_I_DEVICE) {
8078 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8079 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8080 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8081 } else if (sp->device_type == XFRAME_II_DEVICE) {
8082 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8083 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8084 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8087 /* store mac addresses from CAM to s2io_nic structure */
8088 do_s2io_store_unicast_mc(sp);
8090 /* Configure MSIX vector for number of rings configured plus one */
8091 if ((sp->device_type == XFRAME_II_DEVICE) &&
8092 (config->intr_type == MSI_X))
8093 sp->num_entries = config->rx_ring_num + 1;
8095 /* Store the values of the MSIX table in the s2io_nic structure */
8096 store_xmsi_data(sp);
8097 /* reset Nic and bring it to known state */
8101 * Initialize link state flags
8102 * and the card state parameter
8106 /* Initialize spinlocks */
8107 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8108 struct fifo_info *fifo = &mac_control->fifos[i];
8110 spin_lock_init(&fifo->tx_lock);
8114 * SXE-002: Configure link and activity LED to init state
8117 subid = sp->pdev->subsystem_device;
8118 if ((subid & 0xFF) >= 0x07) {
8119 val64 = readq(&bar0->gpio_control);
8120 val64 |= 0x0000800000000000ULL;
8121 writeq(val64, &bar0->gpio_control);
8122 val64 = 0x0411040400000000ULL;
8123 writeq(val64, (void __iomem *)bar0 + 0x2700);
8124 val64 = readq(&bar0->gpio_control);
8127 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8129 if (register_netdev(dev)) {
8130 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8132 goto register_failed;
8135 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
8136 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8137 sp->product_name, pdev->revision);
8138 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8139 s2io_driver_version);
8140 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8141 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8142 if (sp->device_type & XFRAME_II_DEVICE) {
8143 mode = s2io_print_pci_mode(sp);
8146 unregister_netdev(dev);
8147 goto set_swap_failed;
8150 switch (sp->rxd_mode) {
8152 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8156 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8161 switch (sp->config.napi) {
8163 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8166 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8170 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8171 sp->config.tx_fifo_num);
8173 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8174 sp->config.rx_ring_num);
8176 switch (sp->config.intr_type) {
8178 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8181 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8184 if (sp->config.multiq) {
8185 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8186 struct fifo_info *fifo = &mac_control->fifos[i];
8188 fifo->multiq = config->multiq;
8190 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8193 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8196 switch (sp->config.tx_steering_type) {
8198 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8201 case TX_PRIORITY_STEERING:
8203 "%s: Priority steering enabled for transmit\n",
8206 case TX_DEFAULT_STEERING:
8208 "%s: Default steering enabled for transmit\n",
8213 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8217 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8219 /* Initialize device name */
8220 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8223 sp->vlan_strip_flag = 1;
8225 sp->vlan_strip_flag = 0;
8228 * Make Link state as off at this point, when the Link change
8229 * interrupt comes the state will be automatically changed to
8232 netif_carrier_off(dev);
8243 free_shared_mem(sp);
8244 pci_disable_device(pdev);
8245 pci_release_regions(pdev);
8246 pci_set_drvdata(pdev, NULL);
8253 * s2io_rem_nic - Free the PCI device
8254 * @pdev: structure containing the PCI related information of the device.
8255 * Description: This function is called by the Pci subsystem to release a
8256 * PCI device and free up all resource held up by the device. This could
8257 * be in response to a Hot plug event or when the driver is to be removed
8261 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8263 struct net_device *dev =
8264 (struct net_device *)pci_get_drvdata(pdev);
8265 struct s2io_nic *sp;
8268 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8272 flush_scheduled_work();
8274 sp = netdev_priv(dev);
8275 unregister_netdev(dev);
8277 free_shared_mem(sp);
8280 pci_release_regions(pdev);
8281 pci_set_drvdata(pdev, NULL);
8283 pci_disable_device(pdev);
8287 * s2io_starter - Entry point for the driver
8288 * Description: This function is the entry point for the driver. It verifies
8289 * the module loadable parameters and initializes PCI configuration space.
8292 static int __init s2io_starter(void)
8294 return pci_register_driver(&s2io_driver);
8298 * s2io_closer - Cleanup routine for the driver
8299 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8302 static __exit void s2io_closer(void)
8304 pci_unregister_driver(&s2io_driver);
8305 DBG_PRINT(INIT_DBG, "cleanup done\n");
8308 module_init(s2io_starter);
8309 module_exit(s2io_closer);
8311 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8312 struct tcphdr **tcp, struct RxD_t *rxdp,
8313 struct s2io_nic *sp)
8316 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8318 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8320 "%s: Non-TCP frames not supported for LRO\n",
8325 /* Checking for DIX type or DIX type with VLAN */
8326 if ((l2_type == 0) || (l2_type == 4)) {
8327 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8329 * If vlan stripping is disabled and the frame is VLAN tagged,
8330 * shift the offset by the VLAN header size bytes.
8332 if ((!sp->vlan_strip_flag) &&
8333 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8334 ip_off += HEADER_VLAN_SIZE;
8336 /* LLC, SNAP etc are considered non-mergeable */
8340 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8341 ip_len = (u8)((*ip)->ihl);
8343 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8348 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8351 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8352 if ((lro->iph->saddr != ip->saddr) ||
8353 (lro->iph->daddr != ip->daddr) ||
8354 (lro->tcph->source != tcp->source) ||
8355 (lro->tcph->dest != tcp->dest))
8360 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8362 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8365 static void initiate_new_session(struct lro *lro, u8 *l2h,
8366 struct iphdr *ip, struct tcphdr *tcp,
8367 u32 tcp_pyld_len, u16 vlan_tag)
8369 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8373 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8374 lro->tcp_ack = tcp->ack_seq;
8376 lro->total_len = ntohs(ip->tot_len);
8378 lro->vlan_tag = vlan_tag;
8380 * Check if we saw TCP timestamp.
8381 * Other consistency checks have already been done.
8383 if (tcp->doff == 8) {
8385 ptr = (__be32 *)(tcp+1);
8387 lro->cur_tsval = ntohl(*(ptr+1));
8388 lro->cur_tsecr = *(ptr+2);
8393 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8395 struct iphdr *ip = lro->iph;
8396 struct tcphdr *tcp = lro->tcph;
8398 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8400 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8402 /* Update L3 header */
8403 ip->tot_len = htons(lro->total_len);
8405 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8408 /* Update L4 header */
8409 tcp->ack_seq = lro->tcp_ack;
8410 tcp->window = lro->window;
8412 /* Update tsecr field if this session has timestamps enabled */
8414 __be32 *ptr = (__be32 *)(tcp + 1);
8415 *(ptr+2) = lro->cur_tsecr;
8418 /* Update counters required for calculation of
8419 * average no. of packets aggregated.
8421 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8422 swstats->num_aggregations++;
8425 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8426 struct tcphdr *tcp, u32 l4_pyld)
8428 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8429 lro->total_len += l4_pyld;
8430 lro->frags_len += l4_pyld;
8431 lro->tcp_next_seq += l4_pyld;
8434 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8435 lro->tcp_ack = tcp->ack_seq;
8436 lro->window = tcp->window;
8440 /* Update tsecr and tsval from this packet */
8441 ptr = (__be32 *)(tcp+1);
8442 lro->cur_tsval = ntohl(*(ptr+1));
8443 lro->cur_tsecr = *(ptr + 2);
8447 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8448 struct tcphdr *tcp, u32 tcp_pyld_len)
8452 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8454 if (!tcp_pyld_len) {
8455 /* Runt frame or a pure ack */
8459 if (ip->ihl != 5) /* IP has options */
8462 /* If we see CE codepoint in IP header, packet is not mergeable */
8463 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8466 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8467 if (tcp->urg || tcp->psh || tcp->rst ||
8468 tcp->syn || tcp->fin ||
8469 tcp->ece || tcp->cwr || !tcp->ack) {
8471 * Currently recognize only the ack control word and
8472 * any other control field being set would result in
8473 * flushing the LRO session
8479 * Allow only one TCP timestamp option. Don't aggregate if
8480 * any other options are detected.
8482 if (tcp->doff != 5 && tcp->doff != 8)
8485 if (tcp->doff == 8) {
8486 ptr = (u8 *)(tcp + 1);
8487 while (*ptr == TCPOPT_NOP)
8489 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8492 /* Ensure timestamp value increases monotonically */
8494 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8497 /* timestamp echo reply should be non-zero */
8498 if (*((__be32 *)(ptr+6)) == 0)
8505 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8506 u8 **tcp, u32 *tcp_len, struct lro **lro,
8507 struct RxD_t *rxdp, struct s2io_nic *sp)
8510 struct tcphdr *tcph;
8513 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8515 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8520 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8522 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8523 tcph = (struct tcphdr *)*tcp;
8524 *tcp_len = get_l4_pyld_length(ip, tcph);
8525 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8526 struct lro *l_lro = &ring_data->lro0_n[i];
8527 if (l_lro->in_use) {
8528 if (check_for_socket_match(l_lro, ip, tcph))
8530 /* Sock pair matched */
8533 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8534 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8535 "expected 0x%x, actual 0x%x\n",
8537 (*lro)->tcp_next_seq,
8540 swstats->outof_sequence_pkts++;
8545 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8547 ret = 1; /* Aggregate */
8549 ret = 2; /* Flush both */
8555 /* Before searching for available LRO objects,
8556 * check if the pkt is L3/L4 aggregatable. If not
8557 * don't create new LRO session. Just send this
8560 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8563 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8564 struct lro *l_lro = &ring_data->lro0_n[i];
8565 if (!(l_lro->in_use)) {
8567 ret = 3; /* Begin anew */
8573 if (ret == 0) { /* sessions exceeded */
8574 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8582 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8586 update_L3L4_header(sp, *lro);
8589 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8590 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8591 update_L3L4_header(sp, *lro);
8592 ret = 4; /* Flush the LRO */
8596 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8603 static void clear_lro_session(struct lro *lro)
8605 static u16 lro_struct_size = sizeof(struct lro);
8607 memset(lro, 0, lro_struct_size);
8610 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8612 struct net_device *dev = skb->dev;
8613 struct s2io_nic *sp = netdev_priv(dev);
8615 skb->protocol = eth_type_trans(skb, dev);
8616 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
8617 /* Queueing the vlan frame to the upper layer */
8618 if (sp->config.napi)
8619 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8621 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8623 if (sp->config.napi)
8624 netif_receive_skb(skb);
8630 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8631 struct sk_buff *skb, u32 tcp_len)
8633 struct sk_buff *first = lro->parent;
8634 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8636 first->len += tcp_len;
8637 first->data_len = lro->frags_len;
8638 skb_pull(skb, (skb->len - tcp_len));
8639 if (skb_shinfo(first)->frag_list)
8640 lro->last_frag->next = skb;
8642 skb_shinfo(first)->frag_list = skb;
8643 first->truesize += skb->truesize;
8644 lro->last_frag = skb;
8645 swstats->clubbed_frms_cnt++;
8649 * s2io_io_error_detected - called when PCI error is detected
8650 * @pdev: Pointer to PCI device
8651 * @state: The current pci connection state
8653 * This function is called after a PCI bus error affecting
8654 * this device has been detected.
8656 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8657 pci_channel_state_t state)
8659 struct net_device *netdev = pci_get_drvdata(pdev);
8660 struct s2io_nic *sp = netdev_priv(netdev);
8662 netif_device_detach(netdev);
8664 if (state == pci_channel_io_perm_failure)
8665 return PCI_ERS_RESULT_DISCONNECT;
8667 if (netif_running(netdev)) {
8668 /* Bring down the card, while avoiding PCI I/O */
8669 do_s2io_card_down(sp, 0);
8671 pci_disable_device(pdev);
8673 return PCI_ERS_RESULT_NEED_RESET;
8677 * s2io_io_slot_reset - called after the pci bus has been reset.
8678 * @pdev: Pointer to PCI device
8680 * Restart the card from scratch, as if from a cold-boot.
8681 * At this point, the card has exprienced a hard reset,
8682 * followed by fixups by BIOS, and has its config space
8683 * set up identically to what it was at cold boot.
8685 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8687 struct net_device *netdev = pci_get_drvdata(pdev);
8688 struct s2io_nic *sp = netdev_priv(netdev);
8690 if (pci_enable_device(pdev)) {
8691 pr_err("Cannot re-enable PCI device after reset.\n");
8692 return PCI_ERS_RESULT_DISCONNECT;
8695 pci_set_master(pdev);
8698 return PCI_ERS_RESULT_RECOVERED;
8702 * s2io_io_resume - called when traffic can start flowing again.
8703 * @pdev: Pointer to PCI device
8705 * This callback is called when the error recovery driver tells
8706 * us that its OK to resume normal operation.
8708 static void s2io_io_resume(struct pci_dev *pdev)
8710 struct net_device *netdev = pci_get_drvdata(pdev);
8711 struct s2io_nic *sp = netdev_priv(netdev);
8713 if (netif_running(netdev)) {
8714 if (s2io_card_up(sp)) {
8715 pr_err("Can't bring device back up after reset.\n");
8719 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8721 pr_err("Can't restore mac addr after reset.\n");
8726 netif_device_attach(netdev);
8727 netif_tx_wake_all_queues(netdev);
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