1 /************************************************************************
2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3 * Copyright(c) 2002-2010 Exar Corp.
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
21 * Francois Romieu : For pointing out all code part that were
22 * deprecated and also styling related comments.
23 * Grant Grundler : For helping me get rid of some Architecture
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
27 * The module loadable parameters that are supported by the driver and a brief
28 * explanation of all the variables.
30 * rx_ring_num : This can be used to program the number of receive rings used
32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
38 * Tx descriptors that can be associated with each corresponding FIFO.
39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40 * 2(MSI_X). Default value is '2(MSI_X)'
41 * lro_max_pkts: This parameter defines maximum number of packets can be
42 * aggregated as a single large packet
43 * napi: This parameter used to enable/disable NAPI (polling Rx)
44 * Possible values '1' for enable and '0' for disable. Default is '1'
45 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
46 * Possible values '1' for enable and '0' for disable. Default is '0'
47 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
48 * Possible values '1' for enable , '0' for disable.
49 * Default is '2' - which means disable in promisc mode
50 * and enable in non-promiscuous mode.
51 * multiq: This parameter used to enable/disable MULTIQUEUE support.
52 * Possible values '1' for enable and '0' for disable. Default is '0'
53 ************************************************************************/
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
57 #include <linux/module.h>
58 #include <linux/types.h>
59 #include <linux/errno.h>
60 #include <linux/ioport.h>
61 #include <linux/pci.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/kernel.h>
64 #include <linux/netdevice.h>
65 #include <linux/etherdevice.h>
66 #include <linux/mdio.h>
67 #include <linux/skbuff.h>
68 #include <linux/init.h>
69 #include <linux/delay.h>
70 #include <linux/stddef.h>
71 #include <linux/ioctl.h>
72 #include <linux/timex.h>
73 #include <linux/ethtool.h>
74 #include <linux/workqueue.h>
75 #include <linux/if_vlan.h>
77 #include <linux/tcp.h>
78 #include <linux/uaccess.h>
80 #include <linux/slab.h>
81 #include <linux/prefetch.h>
84 #include <asm/system.h>
85 #include <asm/div64.h>
90 #include "s2io-regs.h"
92 #define DRV_VERSION "2.0.26.28"
94 /* S2io Driver name & version. */
95 static const char s2io_driver_name[] = "Neterion";
96 static const char s2io_driver_version[] = DRV_VERSION;
98 static const int rxd_size[2] = {32, 48};
99 static const int rxd_count[2] = {127, 85};
101 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
105 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
106 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
112 * Cards with following subsystem_id have a link state indication
113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114 * macro below identifies these cards given the subsystem_id.
116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
117 (dev_type == XFRAME_I_DEVICE) ? \
118 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
119 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
124 static inline int is_s2io_card_up(const struct s2io_nic *sp)
126 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
129 /* Ethtool related variables and Macros. */
130 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
131 "Register test\t(offline)",
132 "Eeprom test\t(offline)",
133 "Link test\t(online)",
134 "RLDRAM test\t(offline)",
135 "BIST Test\t(offline)"
138 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
140 {"tmac_data_octets"},
144 {"tmac_pause_ctrl_frms"},
148 {"tmac_any_err_frms"},
149 {"tmac_ttl_less_fb_octets"},
150 {"tmac_vld_ip_octets"},
158 {"rmac_data_octets"},
159 {"rmac_fcs_err_frms"},
161 {"rmac_vld_mcst_frms"},
162 {"rmac_vld_bcst_frms"},
163 {"rmac_in_rng_len_err_frms"},
164 {"rmac_out_rng_len_err_frms"},
166 {"rmac_pause_ctrl_frms"},
167 {"rmac_unsup_ctrl_frms"},
169 {"rmac_accepted_ucst_frms"},
170 {"rmac_accepted_nucst_frms"},
171 {"rmac_discarded_frms"},
172 {"rmac_drop_events"},
173 {"rmac_ttl_less_fb_octets"},
175 {"rmac_usized_frms"},
176 {"rmac_osized_frms"},
178 {"rmac_jabber_frms"},
179 {"rmac_ttl_64_frms"},
180 {"rmac_ttl_65_127_frms"},
181 {"rmac_ttl_128_255_frms"},
182 {"rmac_ttl_256_511_frms"},
183 {"rmac_ttl_512_1023_frms"},
184 {"rmac_ttl_1024_1518_frms"},
192 {"rmac_err_drp_udp"},
193 {"rmac_xgmii_err_sym"},
211 {"rmac_xgmii_data_err_cnt"},
212 {"rmac_xgmii_ctrl_err_cnt"},
213 {"rmac_accepted_ip"},
217 {"new_rd_req_rtry_cnt"},
219 {"wr_rtry_rd_ack_cnt"},
222 {"new_wr_req_rtry_cnt"},
225 {"rd_rtry_wr_ack_cnt"},
235 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
236 {"rmac_ttl_1519_4095_frms"},
237 {"rmac_ttl_4096_8191_frms"},
238 {"rmac_ttl_8192_max_frms"},
239 {"rmac_ttl_gt_max_frms"},
240 {"rmac_osized_alt_frms"},
241 {"rmac_jabber_alt_frms"},
242 {"rmac_gt_max_alt_frms"},
244 {"rmac_len_discard"},
245 {"rmac_fcs_discard"},
248 {"rmac_red_discard"},
249 {"rmac_rts_discard"},
250 {"rmac_ingm_full_discard"},
254 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
255 {"\n DRIVER STATISTICS"},
256 {"single_bit_ecc_errs"},
257 {"double_bit_ecc_errs"},
270 {"alarm_transceiver_temp_high"},
271 {"alarm_transceiver_temp_low"},
272 {"alarm_laser_bias_current_high"},
273 {"alarm_laser_bias_current_low"},
274 {"alarm_laser_output_power_high"},
275 {"alarm_laser_output_power_low"},
276 {"warn_transceiver_temp_high"},
277 {"warn_transceiver_temp_low"},
278 {"warn_laser_bias_current_high"},
279 {"warn_laser_bias_current_low"},
280 {"warn_laser_output_power_high"},
281 {"warn_laser_output_power_low"},
282 {"lro_aggregated_pkts"},
283 {"lro_flush_both_count"},
284 {"lro_out_of_sequence_pkts"},
285 {"lro_flush_due_to_max_pkts"},
286 {"lro_avg_aggr_pkts"},
287 {"mem_alloc_fail_cnt"},
288 {"pci_map_fail_cnt"},
289 {"watchdog_timer_cnt"},
296 {"tx_tcode_buf_abort_cnt"},
297 {"tx_tcode_desc_abort_cnt"},
298 {"tx_tcode_parity_err_cnt"},
299 {"tx_tcode_link_loss_cnt"},
300 {"tx_tcode_list_proc_err_cnt"},
301 {"rx_tcode_parity_err_cnt"},
302 {"rx_tcode_abort_cnt"},
303 {"rx_tcode_parity_abort_cnt"},
304 {"rx_tcode_rda_fail_cnt"},
305 {"rx_tcode_unkn_prot_cnt"},
306 {"rx_tcode_fcs_err_cnt"},
307 {"rx_tcode_buf_size_err_cnt"},
308 {"rx_tcode_rxd_corrupt_cnt"},
309 {"rx_tcode_unkn_err_cnt"},
317 {"mac_tmac_err_cnt"},
318 {"mac_rmac_err_cnt"},
319 {"xgxs_txgxs_err_cnt"},
320 {"xgxs_rxgxs_err_cnt"},
322 {"prc_pcix_err_cnt"},
329 #define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
330 #define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
331 #define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
339 #define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
340 #define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
342 #define S2IO_TIMER_CONF(timer, handle, arg, exp) \
343 init_timer(&timer); \
344 timer.function = handle; \
345 timer.data = (unsigned long)arg; \
346 mod_timer(&timer, (jiffies + exp)) \
348 /* copy mac addr to def_mac_addr array */
349 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
351 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
360 * Constants to be programmed into the Xena's registers, to configure
365 static const u64 herc_act_dtx_cfg[] = {
367 0x8000051536750000ULL, 0x80000515367500E0ULL,
369 0x8000051536750004ULL, 0x80000515367500E4ULL,
371 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
373 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
375 0x801205150D440000ULL, 0x801205150D4400E0ULL,
377 0x801205150D440004ULL, 0x801205150D4400E4ULL,
379 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
381 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
386 static const u64 xena_dtx_cfg[] = {
388 0x8000051500000000ULL, 0x80000515000000E0ULL,
390 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
392 0x8001051500000000ULL, 0x80010515000000E0ULL,
394 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
396 0x8002051500000000ULL, 0x80020515000000E0ULL,
398 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
403 * Constants for Fixing the MacAddress problem seen mostly on
406 static const u64 fix_mac[] = {
407 0x0060000000000000ULL, 0x0060600000000000ULL,
408 0x0040600000000000ULL, 0x0000600000000000ULL,
409 0x0020600000000000ULL, 0x0060600000000000ULL,
410 0x0020600000000000ULL, 0x0060600000000000ULL,
411 0x0020600000000000ULL, 0x0060600000000000ULL,
412 0x0020600000000000ULL, 0x0060600000000000ULL,
413 0x0020600000000000ULL, 0x0060600000000000ULL,
414 0x0020600000000000ULL, 0x0060600000000000ULL,
415 0x0020600000000000ULL, 0x0060600000000000ULL,
416 0x0020600000000000ULL, 0x0060600000000000ULL,
417 0x0020600000000000ULL, 0x0060600000000000ULL,
418 0x0020600000000000ULL, 0x0060600000000000ULL,
419 0x0020600000000000ULL, 0x0000600000000000ULL,
420 0x0040600000000000ULL, 0x0060600000000000ULL,
424 MODULE_LICENSE("GPL");
425 MODULE_VERSION(DRV_VERSION);
428 /* Module Loadable parameters. */
429 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
430 S2IO_PARM_INT(rx_ring_num, 1);
431 S2IO_PARM_INT(multiq, 0);
432 S2IO_PARM_INT(rx_ring_mode, 1);
433 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
434 S2IO_PARM_INT(rmac_pause_time, 0x100);
435 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
436 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
437 S2IO_PARM_INT(shared_splits, 0);
438 S2IO_PARM_INT(tmac_util_period, 5);
439 S2IO_PARM_INT(rmac_util_period, 5);
440 S2IO_PARM_INT(l3l4hdr_size, 128);
441 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
442 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
443 /* Frequency of Rx desc syncs expressed as power of 2 */
444 S2IO_PARM_INT(rxsync_frequency, 3);
445 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
446 S2IO_PARM_INT(intr_type, 2);
447 /* Large receive offload feature */
449 /* Max pkts to be aggregated by LRO at one time. If not specified,
450 * aggregation happens until we hit max IP pkt size(64K)
452 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
453 S2IO_PARM_INT(indicate_max_pkts, 0);
455 S2IO_PARM_INT(napi, 1);
456 S2IO_PARM_INT(ufo, 0);
457 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
459 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
460 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
461 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
462 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
463 static unsigned int rts_frm_len[MAX_RX_RINGS] =
464 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
466 module_param_array(tx_fifo_len, uint, NULL, 0);
467 module_param_array(rx_ring_sz, uint, NULL, 0);
468 module_param_array(rts_frm_len, uint, NULL, 0);
472 * This table lists all the devices that this driver supports.
474 static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
475 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
476 PCI_ANY_ID, PCI_ANY_ID},
477 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
478 PCI_ANY_ID, PCI_ANY_ID},
479 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
480 PCI_ANY_ID, PCI_ANY_ID},
481 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
482 PCI_ANY_ID, PCI_ANY_ID},
486 MODULE_DEVICE_TABLE(pci, s2io_tbl);
488 static struct pci_error_handlers s2io_err_handler = {
489 .error_detected = s2io_io_error_detected,
490 .slot_reset = s2io_io_slot_reset,
491 .resume = s2io_io_resume,
494 static struct pci_driver s2io_driver = {
496 .id_table = s2io_tbl,
497 .probe = s2io_init_nic,
498 .remove = __devexit_p(s2io_rem_nic),
499 .err_handler = &s2io_err_handler,
502 /* A simplifier macro used both by init and free shared_mem Fns(). */
503 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
505 /* netqueue manipulation helper functions */
506 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
508 if (!sp->config.multiq) {
511 for (i = 0; i < sp->config.tx_fifo_num; i++)
512 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
514 netif_tx_stop_all_queues(sp->dev);
517 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
519 if (!sp->config.multiq)
520 sp->mac_control.fifos[fifo_no].queue_state =
523 netif_tx_stop_all_queues(sp->dev);
526 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
528 if (!sp->config.multiq) {
531 for (i = 0; i < sp->config.tx_fifo_num; i++)
532 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
534 netif_tx_start_all_queues(sp->dev);
537 static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
539 if (!sp->config.multiq)
540 sp->mac_control.fifos[fifo_no].queue_state =
543 netif_tx_start_all_queues(sp->dev);
546 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
548 if (!sp->config.multiq) {
551 for (i = 0; i < sp->config.tx_fifo_num; i++)
552 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
554 netif_tx_wake_all_queues(sp->dev);
557 static inline void s2io_wake_tx_queue(
558 struct fifo_info *fifo, int cnt, u8 multiq)
562 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
563 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
564 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
565 if (netif_queue_stopped(fifo->dev)) {
566 fifo->queue_state = FIFO_QUEUE_START;
567 netif_wake_queue(fifo->dev);
573 * init_shared_mem - Allocation and Initialization of Memory
574 * @nic: Device private variable.
575 * Description: The function allocates all the memory areas shared
576 * between the NIC and the driver. This includes Tx descriptors,
577 * Rx descriptors and the statistics block.
580 static int init_shared_mem(struct s2io_nic *nic)
583 void *tmp_v_addr, *tmp_v_addr_next;
584 dma_addr_t tmp_p_addr, tmp_p_addr_next;
585 struct RxD_block *pre_rxd_blk = NULL;
587 int lst_size, lst_per_page;
588 struct net_device *dev = nic->dev;
591 struct config_param *config = &nic->config;
592 struct mac_info *mac_control = &nic->mac_control;
593 unsigned long long mem_allocated = 0;
595 /* Allocation and initialization of TXDLs in FIFOs */
597 for (i = 0; i < config->tx_fifo_num; i++) {
598 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
600 size += tx_cfg->fifo_len;
602 if (size > MAX_AVAILABLE_TXDS) {
604 "Too many TxDs requested: %d, max supported: %d\n",
605 size, MAX_AVAILABLE_TXDS);
610 for (i = 0; i < config->tx_fifo_num; i++) {
611 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
613 size = tx_cfg->fifo_len;
615 * Legal values are from 2 to 8192
618 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
619 "Valid lengths are 2 through 8192\n",
625 lst_size = (sizeof(struct TxD) * config->max_txds);
626 lst_per_page = PAGE_SIZE / lst_size;
628 for (i = 0; i < config->tx_fifo_num; i++) {
629 struct fifo_info *fifo = &mac_control->fifos[i];
630 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
631 int fifo_len = tx_cfg->fifo_len;
632 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
634 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
635 if (!fifo->list_info) {
636 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
639 mem_allocated += list_holder_size;
641 for (i = 0; i < config->tx_fifo_num; i++) {
642 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
644 struct fifo_info *fifo = &mac_control->fifos[i];
645 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
647 fifo->tx_curr_put_info.offset = 0;
648 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
649 fifo->tx_curr_get_info.offset = 0;
650 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
653 fifo->max_txds = MAX_SKB_FRAGS + 2;
656 for (j = 0; j < page_num; j++) {
660 tmp_v = pci_alloc_consistent(nic->pdev,
664 "pci_alloc_consistent failed for TxDL\n");
667 /* If we got a zero DMA address(can happen on
668 * certain platforms like PPC), reallocate.
669 * Store virtual address of page we don't want,
673 mac_control->zerodma_virt_addr = tmp_v;
675 "%s: Zero DMA address for TxDL. "
676 "Virtual address %p\n",
678 tmp_v = pci_alloc_consistent(nic->pdev,
682 "pci_alloc_consistent failed for TxDL\n");
685 mem_allocated += PAGE_SIZE;
687 while (k < lst_per_page) {
688 int l = (j * lst_per_page) + k;
689 if (l == tx_cfg->fifo_len)
691 fifo->list_info[l].list_virt_addr =
692 tmp_v + (k * lst_size);
693 fifo->list_info[l].list_phy_addr =
694 tmp_p + (k * lst_size);
700 for (i = 0; i < config->tx_fifo_num; i++) {
701 struct fifo_info *fifo = &mac_control->fifos[i];
702 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
704 size = tx_cfg->fifo_len;
705 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
706 if (!fifo->ufo_in_band_v)
708 mem_allocated += (size * sizeof(u64));
711 /* Allocation and initialization of RXDs in Rings */
713 for (i = 0; i < config->rx_ring_num; i++) {
714 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
715 struct ring_info *ring = &mac_control->rings[i];
717 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
718 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
719 "multiple of RxDs per Block\n",
723 size += rx_cfg->num_rxd;
724 ring->block_count = rx_cfg->num_rxd /
725 (rxd_count[nic->rxd_mode] + 1);
726 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
728 if (nic->rxd_mode == RXD_MODE_1)
729 size = (size * (sizeof(struct RxD1)));
731 size = (size * (sizeof(struct RxD3)));
733 for (i = 0; i < config->rx_ring_num; i++) {
734 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
735 struct ring_info *ring = &mac_control->rings[i];
737 ring->rx_curr_get_info.block_index = 0;
738 ring->rx_curr_get_info.offset = 0;
739 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
740 ring->rx_curr_put_info.block_index = 0;
741 ring->rx_curr_put_info.offset = 0;
742 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
746 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
747 /* Allocating all the Rx blocks */
748 for (j = 0; j < blk_cnt; j++) {
749 struct rx_block_info *rx_blocks;
752 rx_blocks = &ring->rx_blocks[j];
753 size = SIZE_OF_BLOCK; /* size is always page size */
754 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
756 if (tmp_v_addr == NULL) {
758 * In case of failure, free_shared_mem()
759 * is called, which should free any
760 * memory that was alloced till the
763 rx_blocks->block_virt_addr = tmp_v_addr;
766 mem_allocated += size;
767 memset(tmp_v_addr, 0, size);
769 size = sizeof(struct rxd_info) *
770 rxd_count[nic->rxd_mode];
771 rx_blocks->block_virt_addr = tmp_v_addr;
772 rx_blocks->block_dma_addr = tmp_p_addr;
773 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
774 if (!rx_blocks->rxds)
776 mem_allocated += size;
777 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
778 rx_blocks->rxds[l].virt_addr =
779 rx_blocks->block_virt_addr +
780 (rxd_size[nic->rxd_mode] * l);
781 rx_blocks->rxds[l].dma_addr =
782 rx_blocks->block_dma_addr +
783 (rxd_size[nic->rxd_mode] * l);
786 /* Interlinking all Rx Blocks */
787 for (j = 0; j < blk_cnt; j++) {
788 int next = (j + 1) % blk_cnt;
789 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
790 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
791 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
792 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
794 pre_rxd_blk = tmp_v_addr;
795 pre_rxd_blk->reserved_2_pNext_RxD_block =
796 (unsigned long)tmp_v_addr_next;
797 pre_rxd_blk->pNext_RxD_Blk_physical =
798 (u64)tmp_p_addr_next;
801 if (nic->rxd_mode == RXD_MODE_3B) {
803 * Allocation of Storages for buffer addresses in 2BUFF mode
804 * and the buffers as well.
806 for (i = 0; i < config->rx_ring_num; i++) {
807 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
808 struct ring_info *ring = &mac_control->rings[i];
810 blk_cnt = rx_cfg->num_rxd /
811 (rxd_count[nic->rxd_mode] + 1);
812 size = sizeof(struct buffAdd *) * blk_cnt;
813 ring->ba = kmalloc(size, GFP_KERNEL);
816 mem_allocated += size;
817 for (j = 0; j < blk_cnt; j++) {
820 size = sizeof(struct buffAdd) *
821 (rxd_count[nic->rxd_mode] + 1);
822 ring->ba[j] = kmalloc(size, GFP_KERNEL);
825 mem_allocated += size;
826 while (k != rxd_count[nic->rxd_mode]) {
827 ba = &ring->ba[j][k];
828 size = BUF0_LEN + ALIGN_SIZE;
829 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
832 mem_allocated += size;
833 tmp = (unsigned long)ba->ba_0_org;
835 tmp &= ~((unsigned long)ALIGN_SIZE);
836 ba->ba_0 = (void *)tmp;
838 size = BUF1_LEN + ALIGN_SIZE;
839 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
842 mem_allocated += size;
843 tmp = (unsigned long)ba->ba_1_org;
845 tmp &= ~((unsigned long)ALIGN_SIZE);
846 ba->ba_1 = (void *)tmp;
853 /* Allocation and initialization of Statistics block */
854 size = sizeof(struct stat_block);
855 mac_control->stats_mem =
856 pci_alloc_consistent(nic->pdev, size,
857 &mac_control->stats_mem_phy);
859 if (!mac_control->stats_mem) {
861 * In case of failure, free_shared_mem() is called, which
862 * should free any memory that was alloced till the
867 mem_allocated += size;
868 mac_control->stats_mem_sz = size;
870 tmp_v_addr = mac_control->stats_mem;
871 mac_control->stats_info = tmp_v_addr;
872 memset(tmp_v_addr, 0, size);
873 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
874 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
875 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
880 * free_shared_mem - Free the allocated Memory
881 * @nic: Device private variable.
882 * Description: This function is to free all memory locations allocated by
883 * the init_shared_mem() function and return it to the kernel.
886 static void free_shared_mem(struct s2io_nic *nic)
888 int i, j, blk_cnt, size;
890 dma_addr_t tmp_p_addr;
891 int lst_size, lst_per_page;
892 struct net_device *dev;
894 struct config_param *config;
895 struct mac_info *mac_control;
896 struct stat_block *stats;
897 struct swStat *swstats;
904 config = &nic->config;
905 mac_control = &nic->mac_control;
906 stats = mac_control->stats_info;
907 swstats = &stats->sw_stat;
909 lst_size = sizeof(struct TxD) * config->max_txds;
910 lst_per_page = PAGE_SIZE / lst_size;
912 for (i = 0; i < config->tx_fifo_num; i++) {
913 struct fifo_info *fifo = &mac_control->fifos[i];
914 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
916 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
917 for (j = 0; j < page_num; j++) {
918 int mem_blks = (j * lst_per_page);
919 struct list_info_hold *fli;
921 if (!fifo->list_info)
924 fli = &fifo->list_info[mem_blks];
925 if (!fli->list_virt_addr)
927 pci_free_consistent(nic->pdev, PAGE_SIZE,
930 swstats->mem_freed += PAGE_SIZE;
932 /* If we got a zero DMA address during allocation,
935 if (mac_control->zerodma_virt_addr) {
936 pci_free_consistent(nic->pdev, PAGE_SIZE,
937 mac_control->zerodma_virt_addr,
940 "%s: Freeing TxDL with zero DMA address. "
941 "Virtual address %p\n",
942 dev->name, mac_control->zerodma_virt_addr);
943 swstats->mem_freed += PAGE_SIZE;
945 kfree(fifo->list_info);
946 swstats->mem_freed += tx_cfg->fifo_len *
947 sizeof(struct list_info_hold);
950 size = SIZE_OF_BLOCK;
951 for (i = 0; i < config->rx_ring_num; i++) {
952 struct ring_info *ring = &mac_control->rings[i];
954 blk_cnt = ring->block_count;
955 for (j = 0; j < blk_cnt; j++) {
956 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
957 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
958 if (tmp_v_addr == NULL)
960 pci_free_consistent(nic->pdev, size,
961 tmp_v_addr, tmp_p_addr);
962 swstats->mem_freed += size;
963 kfree(ring->rx_blocks[j].rxds);
964 swstats->mem_freed += sizeof(struct rxd_info) *
965 rxd_count[nic->rxd_mode];
969 if (nic->rxd_mode == RXD_MODE_3B) {
970 /* Freeing buffer storage addresses in 2BUFF mode. */
971 for (i = 0; i < config->rx_ring_num; i++) {
972 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
973 struct ring_info *ring = &mac_control->rings[i];
975 blk_cnt = rx_cfg->num_rxd /
976 (rxd_count[nic->rxd_mode] + 1);
977 for (j = 0; j < blk_cnt; j++) {
981 while (k != rxd_count[nic->rxd_mode]) {
982 struct buffAdd *ba = &ring->ba[j][k];
984 swstats->mem_freed +=
985 BUF0_LEN + ALIGN_SIZE;
987 swstats->mem_freed +=
988 BUF1_LEN + ALIGN_SIZE;
992 swstats->mem_freed += sizeof(struct buffAdd) *
993 (rxd_count[nic->rxd_mode] + 1);
996 swstats->mem_freed += sizeof(struct buffAdd *) *
1001 for (i = 0; i < nic->config.tx_fifo_num; i++) {
1002 struct fifo_info *fifo = &mac_control->fifos[i];
1003 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1005 if (fifo->ufo_in_band_v) {
1006 swstats->mem_freed += tx_cfg->fifo_len *
1008 kfree(fifo->ufo_in_band_v);
1012 if (mac_control->stats_mem) {
1013 swstats->mem_freed += mac_control->stats_mem_sz;
1014 pci_free_consistent(nic->pdev,
1015 mac_control->stats_mem_sz,
1016 mac_control->stats_mem,
1017 mac_control->stats_mem_phy);
1022 * s2io_verify_pci_mode -
1025 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1027 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1028 register u64 val64 = 0;
1031 val64 = readq(&bar0->pci_mode);
1032 mode = (u8)GET_PCI_MODE(val64);
1034 if (val64 & PCI_MODE_UNKNOWN_MODE)
1035 return -1; /* Unknown PCI mode */
1039 #define NEC_VENID 0x1033
1040 #define NEC_DEVID 0x0125
1041 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1043 struct pci_dev *tdev = NULL;
1044 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1045 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1046 if (tdev->bus == s2io_pdev->bus->parent) {
1055 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1057 * s2io_print_pci_mode -
1059 static int s2io_print_pci_mode(struct s2io_nic *nic)
1061 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1062 register u64 val64 = 0;
1064 struct config_param *config = &nic->config;
1065 const char *pcimode;
1067 val64 = readq(&bar0->pci_mode);
1068 mode = (u8)GET_PCI_MODE(val64);
1070 if (val64 & PCI_MODE_UNKNOWN_MODE)
1071 return -1; /* Unknown PCI mode */
1073 config->bus_speed = bus_speed[mode];
1075 if (s2io_on_nec_bridge(nic->pdev)) {
1076 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1082 case PCI_MODE_PCI_33:
1083 pcimode = "33MHz PCI bus";
1085 case PCI_MODE_PCI_66:
1086 pcimode = "66MHz PCI bus";
1088 case PCI_MODE_PCIX_M1_66:
1089 pcimode = "66MHz PCIX(M1) bus";
1091 case PCI_MODE_PCIX_M1_100:
1092 pcimode = "100MHz PCIX(M1) bus";
1094 case PCI_MODE_PCIX_M1_133:
1095 pcimode = "133MHz PCIX(M1) bus";
1097 case PCI_MODE_PCIX_M2_66:
1098 pcimode = "133MHz PCIX(M2) bus";
1100 case PCI_MODE_PCIX_M2_100:
1101 pcimode = "200MHz PCIX(M2) bus";
1103 case PCI_MODE_PCIX_M2_133:
1104 pcimode = "266MHz PCIX(M2) bus";
1107 pcimode = "unsupported bus!";
1111 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1112 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1118 * init_tti - Initialization transmit traffic interrupt scheme
1119 * @nic: device private variable
1120 * @link: link status (UP/DOWN) used to enable/disable continuous
1121 * transmit interrupts
1122 * Description: The function configures transmit traffic interrupts
1123 * Return Value: SUCCESS on success and
1127 static int init_tti(struct s2io_nic *nic, int link)
1129 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1130 register u64 val64 = 0;
1132 struct config_param *config = &nic->config;
1134 for (i = 0; i < config->tx_fifo_num; i++) {
1136 * TTI Initialization. Default Tx timer gets us about
1137 * 250 interrupts per sec. Continuous interrupts are enabled
1140 if (nic->device_type == XFRAME_II_DEVICE) {
1141 int count = (nic->config.bus_speed * 125)/2;
1142 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1144 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1146 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1147 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1148 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1149 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1151 if (use_continuous_tx_intrs && (link == LINK_UP))
1152 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1153 writeq(val64, &bar0->tti_data1_mem);
1155 if (nic->config.intr_type == MSI_X) {
1156 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1157 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1158 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1159 TTI_DATA2_MEM_TX_UFC_D(0x300);
1161 if ((nic->config.tx_steering_type ==
1162 TX_DEFAULT_STEERING) &&
1163 (config->tx_fifo_num > 1) &&
1164 (i >= nic->udp_fifo_idx) &&
1165 (i < (nic->udp_fifo_idx +
1166 nic->total_udp_fifos)))
1167 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1168 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1169 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1170 TTI_DATA2_MEM_TX_UFC_D(0x120);
1172 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1173 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1174 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1175 TTI_DATA2_MEM_TX_UFC_D(0x80);
1178 writeq(val64, &bar0->tti_data2_mem);
1180 val64 = TTI_CMD_MEM_WE |
1181 TTI_CMD_MEM_STROBE_NEW_CMD |
1182 TTI_CMD_MEM_OFFSET(i);
1183 writeq(val64, &bar0->tti_command_mem);
1185 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1186 TTI_CMD_MEM_STROBE_NEW_CMD,
1187 S2IO_BIT_RESET) != SUCCESS)
1195 * init_nic - Initialization of hardware
1196 * @nic: device private variable
1197 * Description: The function sequentially configures every block
1198 * of the H/W from their reset values.
1199 * Return Value: SUCCESS on success and
1200 * '-1' on failure (endian settings incorrect).
1203 static int init_nic(struct s2io_nic *nic)
1205 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1206 struct net_device *dev = nic->dev;
1207 register u64 val64 = 0;
1212 unsigned long long mem_share;
1214 struct config_param *config = &nic->config;
1215 struct mac_info *mac_control = &nic->mac_control;
1217 /* to set the swapper controle on the card */
1218 if (s2io_set_swapper(nic)) {
1219 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1224 * Herc requires EOI to be removed from reset before XGXS, so..
1226 if (nic->device_type & XFRAME_II_DEVICE) {
1227 val64 = 0xA500000000ULL;
1228 writeq(val64, &bar0->sw_reset);
1230 val64 = readq(&bar0->sw_reset);
1233 /* Remove XGXS from reset state */
1235 writeq(val64, &bar0->sw_reset);
1237 val64 = readq(&bar0->sw_reset);
1239 /* Ensure that it's safe to access registers by checking
1240 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1242 if (nic->device_type == XFRAME_II_DEVICE) {
1243 for (i = 0; i < 50; i++) {
1244 val64 = readq(&bar0->adapter_status);
1245 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1253 /* Enable Receiving broadcasts */
1254 add = &bar0->mac_cfg;
1255 val64 = readq(&bar0->mac_cfg);
1256 val64 |= MAC_RMAC_BCAST_ENABLE;
1257 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1258 writel((u32)val64, add);
1259 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1260 writel((u32) (val64 >> 32), (add + 4));
1262 /* Read registers in all blocks */
1263 val64 = readq(&bar0->mac_int_mask);
1264 val64 = readq(&bar0->mc_int_mask);
1265 val64 = readq(&bar0->xgxs_int_mask);
1269 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1271 if (nic->device_type & XFRAME_II_DEVICE) {
1272 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1273 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1274 &bar0->dtx_control, UF);
1276 msleep(1); /* Necessary!! */
1280 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1281 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1282 &bar0->dtx_control, UF);
1283 val64 = readq(&bar0->dtx_control);
1288 /* Tx DMA Initialization */
1290 writeq(val64, &bar0->tx_fifo_partition_0);
1291 writeq(val64, &bar0->tx_fifo_partition_1);
1292 writeq(val64, &bar0->tx_fifo_partition_2);
1293 writeq(val64, &bar0->tx_fifo_partition_3);
1295 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1296 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1298 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1299 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1301 if (i == (config->tx_fifo_num - 1)) {
1308 writeq(val64, &bar0->tx_fifo_partition_0);
1313 writeq(val64, &bar0->tx_fifo_partition_1);
1318 writeq(val64, &bar0->tx_fifo_partition_2);
1323 writeq(val64, &bar0->tx_fifo_partition_3);
1334 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1335 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1337 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1338 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1340 val64 = readq(&bar0->tx_fifo_partition_0);
1341 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1342 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1345 * Initialization of Tx_PA_CONFIG register to ignore packet
1346 * integrity checking.
1348 val64 = readq(&bar0->tx_pa_cfg);
1349 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1350 TX_PA_CFG_IGNORE_SNAP_OUI |
1351 TX_PA_CFG_IGNORE_LLC_CTRL |
1352 TX_PA_CFG_IGNORE_L2_ERR;
1353 writeq(val64, &bar0->tx_pa_cfg);
1355 /* Rx DMA intialization. */
1357 for (i = 0; i < config->rx_ring_num; i++) {
1358 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1360 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1362 writeq(val64, &bar0->rx_queue_priority);
1365 * Allocating equal share of memory to all the
1369 if (nic->device_type & XFRAME_II_DEVICE)
1374 for (i = 0; i < config->rx_ring_num; i++) {
1377 mem_share = (mem_size / config->rx_ring_num +
1378 mem_size % config->rx_ring_num);
1379 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1382 mem_share = (mem_size / config->rx_ring_num);
1383 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1386 mem_share = (mem_size / config->rx_ring_num);
1387 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1390 mem_share = (mem_size / config->rx_ring_num);
1391 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1394 mem_share = (mem_size / config->rx_ring_num);
1395 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1398 mem_share = (mem_size / config->rx_ring_num);
1399 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1402 mem_share = (mem_size / config->rx_ring_num);
1403 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1406 mem_share = (mem_size / config->rx_ring_num);
1407 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1411 writeq(val64, &bar0->rx_queue_cfg);
1414 * Filling Tx round robin registers
1415 * as per the number of FIFOs for equal scheduling priority
1417 switch (config->tx_fifo_num) {
1420 writeq(val64, &bar0->tx_w_round_robin_0);
1421 writeq(val64, &bar0->tx_w_round_robin_1);
1422 writeq(val64, &bar0->tx_w_round_robin_2);
1423 writeq(val64, &bar0->tx_w_round_robin_3);
1424 writeq(val64, &bar0->tx_w_round_robin_4);
1427 val64 = 0x0001000100010001ULL;
1428 writeq(val64, &bar0->tx_w_round_robin_0);
1429 writeq(val64, &bar0->tx_w_round_robin_1);
1430 writeq(val64, &bar0->tx_w_round_robin_2);
1431 writeq(val64, &bar0->tx_w_round_robin_3);
1432 val64 = 0x0001000100000000ULL;
1433 writeq(val64, &bar0->tx_w_round_robin_4);
1436 val64 = 0x0001020001020001ULL;
1437 writeq(val64, &bar0->tx_w_round_robin_0);
1438 val64 = 0x0200010200010200ULL;
1439 writeq(val64, &bar0->tx_w_round_robin_1);
1440 val64 = 0x0102000102000102ULL;
1441 writeq(val64, &bar0->tx_w_round_robin_2);
1442 val64 = 0x0001020001020001ULL;
1443 writeq(val64, &bar0->tx_w_round_robin_3);
1444 val64 = 0x0200010200000000ULL;
1445 writeq(val64, &bar0->tx_w_round_robin_4);
1448 val64 = 0x0001020300010203ULL;
1449 writeq(val64, &bar0->tx_w_round_robin_0);
1450 writeq(val64, &bar0->tx_w_round_robin_1);
1451 writeq(val64, &bar0->tx_w_round_robin_2);
1452 writeq(val64, &bar0->tx_w_round_robin_3);
1453 val64 = 0x0001020300000000ULL;
1454 writeq(val64, &bar0->tx_w_round_robin_4);
1457 val64 = 0x0001020304000102ULL;
1458 writeq(val64, &bar0->tx_w_round_robin_0);
1459 val64 = 0x0304000102030400ULL;
1460 writeq(val64, &bar0->tx_w_round_robin_1);
1461 val64 = 0x0102030400010203ULL;
1462 writeq(val64, &bar0->tx_w_round_robin_2);
1463 val64 = 0x0400010203040001ULL;
1464 writeq(val64, &bar0->tx_w_round_robin_3);
1465 val64 = 0x0203040000000000ULL;
1466 writeq(val64, &bar0->tx_w_round_robin_4);
1469 val64 = 0x0001020304050001ULL;
1470 writeq(val64, &bar0->tx_w_round_robin_0);
1471 val64 = 0x0203040500010203ULL;
1472 writeq(val64, &bar0->tx_w_round_robin_1);
1473 val64 = 0x0405000102030405ULL;
1474 writeq(val64, &bar0->tx_w_round_robin_2);
1475 val64 = 0x0001020304050001ULL;
1476 writeq(val64, &bar0->tx_w_round_robin_3);
1477 val64 = 0x0203040500000000ULL;
1478 writeq(val64, &bar0->tx_w_round_robin_4);
1481 val64 = 0x0001020304050600ULL;
1482 writeq(val64, &bar0->tx_w_round_robin_0);
1483 val64 = 0x0102030405060001ULL;
1484 writeq(val64, &bar0->tx_w_round_robin_1);
1485 val64 = 0x0203040506000102ULL;
1486 writeq(val64, &bar0->tx_w_round_robin_2);
1487 val64 = 0x0304050600010203ULL;
1488 writeq(val64, &bar0->tx_w_round_robin_3);
1489 val64 = 0x0405060000000000ULL;
1490 writeq(val64, &bar0->tx_w_round_robin_4);
1493 val64 = 0x0001020304050607ULL;
1494 writeq(val64, &bar0->tx_w_round_robin_0);
1495 writeq(val64, &bar0->tx_w_round_robin_1);
1496 writeq(val64, &bar0->tx_w_round_robin_2);
1497 writeq(val64, &bar0->tx_w_round_robin_3);
1498 val64 = 0x0001020300000000ULL;
1499 writeq(val64, &bar0->tx_w_round_robin_4);
1503 /* Enable all configured Tx FIFO partitions */
1504 val64 = readq(&bar0->tx_fifo_partition_0);
1505 val64 |= (TX_FIFO_PARTITION_EN);
1506 writeq(val64, &bar0->tx_fifo_partition_0);
1508 /* Filling the Rx round robin registers as per the
1509 * number of Rings and steering based on QoS with
1512 switch (config->rx_ring_num) {
1515 writeq(val64, &bar0->rx_w_round_robin_0);
1516 writeq(val64, &bar0->rx_w_round_robin_1);
1517 writeq(val64, &bar0->rx_w_round_robin_2);
1518 writeq(val64, &bar0->rx_w_round_robin_3);
1519 writeq(val64, &bar0->rx_w_round_robin_4);
1521 val64 = 0x8080808080808080ULL;
1522 writeq(val64, &bar0->rts_qos_steering);
1525 val64 = 0x0001000100010001ULL;
1526 writeq(val64, &bar0->rx_w_round_robin_0);
1527 writeq(val64, &bar0->rx_w_round_robin_1);
1528 writeq(val64, &bar0->rx_w_round_robin_2);
1529 writeq(val64, &bar0->rx_w_round_robin_3);
1530 val64 = 0x0001000100000000ULL;
1531 writeq(val64, &bar0->rx_w_round_robin_4);
1533 val64 = 0x8080808040404040ULL;
1534 writeq(val64, &bar0->rts_qos_steering);
1537 val64 = 0x0001020001020001ULL;
1538 writeq(val64, &bar0->rx_w_round_robin_0);
1539 val64 = 0x0200010200010200ULL;
1540 writeq(val64, &bar0->rx_w_round_robin_1);
1541 val64 = 0x0102000102000102ULL;
1542 writeq(val64, &bar0->rx_w_round_robin_2);
1543 val64 = 0x0001020001020001ULL;
1544 writeq(val64, &bar0->rx_w_round_robin_3);
1545 val64 = 0x0200010200000000ULL;
1546 writeq(val64, &bar0->rx_w_round_robin_4);
1548 val64 = 0x8080804040402020ULL;
1549 writeq(val64, &bar0->rts_qos_steering);
1552 val64 = 0x0001020300010203ULL;
1553 writeq(val64, &bar0->rx_w_round_robin_0);
1554 writeq(val64, &bar0->rx_w_round_robin_1);
1555 writeq(val64, &bar0->rx_w_round_robin_2);
1556 writeq(val64, &bar0->rx_w_round_robin_3);
1557 val64 = 0x0001020300000000ULL;
1558 writeq(val64, &bar0->rx_w_round_robin_4);
1560 val64 = 0x8080404020201010ULL;
1561 writeq(val64, &bar0->rts_qos_steering);
1564 val64 = 0x0001020304000102ULL;
1565 writeq(val64, &bar0->rx_w_round_robin_0);
1566 val64 = 0x0304000102030400ULL;
1567 writeq(val64, &bar0->rx_w_round_robin_1);
1568 val64 = 0x0102030400010203ULL;
1569 writeq(val64, &bar0->rx_w_round_robin_2);
1570 val64 = 0x0400010203040001ULL;
1571 writeq(val64, &bar0->rx_w_round_robin_3);
1572 val64 = 0x0203040000000000ULL;
1573 writeq(val64, &bar0->rx_w_round_robin_4);
1575 val64 = 0x8080404020201008ULL;
1576 writeq(val64, &bar0->rts_qos_steering);
1579 val64 = 0x0001020304050001ULL;
1580 writeq(val64, &bar0->rx_w_round_robin_0);
1581 val64 = 0x0203040500010203ULL;
1582 writeq(val64, &bar0->rx_w_round_robin_1);
1583 val64 = 0x0405000102030405ULL;
1584 writeq(val64, &bar0->rx_w_round_robin_2);
1585 val64 = 0x0001020304050001ULL;
1586 writeq(val64, &bar0->rx_w_round_robin_3);
1587 val64 = 0x0203040500000000ULL;
1588 writeq(val64, &bar0->rx_w_round_robin_4);
1590 val64 = 0x8080404020100804ULL;
1591 writeq(val64, &bar0->rts_qos_steering);
1594 val64 = 0x0001020304050600ULL;
1595 writeq(val64, &bar0->rx_w_round_robin_0);
1596 val64 = 0x0102030405060001ULL;
1597 writeq(val64, &bar0->rx_w_round_robin_1);
1598 val64 = 0x0203040506000102ULL;
1599 writeq(val64, &bar0->rx_w_round_robin_2);
1600 val64 = 0x0304050600010203ULL;
1601 writeq(val64, &bar0->rx_w_round_robin_3);
1602 val64 = 0x0405060000000000ULL;
1603 writeq(val64, &bar0->rx_w_round_robin_4);
1605 val64 = 0x8080402010080402ULL;
1606 writeq(val64, &bar0->rts_qos_steering);
1609 val64 = 0x0001020304050607ULL;
1610 writeq(val64, &bar0->rx_w_round_robin_0);
1611 writeq(val64, &bar0->rx_w_round_robin_1);
1612 writeq(val64, &bar0->rx_w_round_robin_2);
1613 writeq(val64, &bar0->rx_w_round_robin_3);
1614 val64 = 0x0001020300000000ULL;
1615 writeq(val64, &bar0->rx_w_round_robin_4);
1617 val64 = 0x8040201008040201ULL;
1618 writeq(val64, &bar0->rts_qos_steering);
1624 for (i = 0; i < 8; i++)
1625 writeq(val64, &bar0->rts_frm_len_n[i]);
1627 /* Set the default rts frame length for the rings configured */
1628 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1629 for (i = 0 ; i < config->rx_ring_num ; i++)
1630 writeq(val64, &bar0->rts_frm_len_n[i]);
1632 /* Set the frame length for the configured rings
1633 * desired by the user
1635 for (i = 0; i < config->rx_ring_num; i++) {
1636 /* If rts_frm_len[i] == 0 then it is assumed that user not
1637 * specified frame length steering.
1638 * If the user provides the frame length then program
1639 * the rts_frm_len register for those values or else
1640 * leave it as it is.
1642 if (rts_frm_len[i] != 0) {
1643 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1644 &bar0->rts_frm_len_n[i]);
1648 /* Disable differentiated services steering logic */
1649 for (i = 0; i < 64; i++) {
1650 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1652 "%s: rts_ds_steer failed on codepoint %d\n",
1658 /* Program statistics memory */
1659 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1661 if (nic->device_type == XFRAME_II_DEVICE) {
1662 val64 = STAT_BC(0x320);
1663 writeq(val64, &bar0->stat_byte_cnt);
1667 * Initializing the sampling rate for the device to calculate the
1668 * bandwidth utilization.
1670 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1671 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1672 writeq(val64, &bar0->mac_link_util);
1675 * Initializing the Transmit and Receive Traffic Interrupt
1679 /* Initialize TTI */
1680 if (SUCCESS != init_tti(nic, nic->last_link_state))
1683 /* RTI Initialization */
1684 if (nic->device_type == XFRAME_II_DEVICE) {
1686 * Programmed to generate Apprx 500 Intrs per
1689 int count = (nic->config.bus_speed * 125)/4;
1690 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1692 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1693 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1694 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1695 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1696 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1698 writeq(val64, &bar0->rti_data1_mem);
1700 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1701 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1702 if (nic->config.intr_type == MSI_X)
1703 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1704 RTI_DATA2_MEM_RX_UFC_D(0x40));
1706 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1707 RTI_DATA2_MEM_RX_UFC_D(0x80));
1708 writeq(val64, &bar0->rti_data2_mem);
1710 for (i = 0; i < config->rx_ring_num; i++) {
1711 val64 = RTI_CMD_MEM_WE |
1712 RTI_CMD_MEM_STROBE_NEW_CMD |
1713 RTI_CMD_MEM_OFFSET(i);
1714 writeq(val64, &bar0->rti_command_mem);
1717 * Once the operation completes, the Strobe bit of the
1718 * command register will be reset. We poll for this
1719 * particular condition. We wait for a maximum of 500ms
1720 * for the operation to complete, if it's not complete
1721 * by then we return error.
1725 val64 = readq(&bar0->rti_command_mem);
1726 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1730 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1740 * Initializing proper values as Pause threshold into all
1741 * the 8 Queues on Rx side.
1743 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1744 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1746 /* Disable RMAC PAD STRIPPING */
1747 add = &bar0->mac_cfg;
1748 val64 = readq(&bar0->mac_cfg);
1749 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1750 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1751 writel((u32) (val64), add);
1752 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1753 writel((u32) (val64 >> 32), (add + 4));
1754 val64 = readq(&bar0->mac_cfg);
1756 /* Enable FCS stripping by adapter */
1757 add = &bar0->mac_cfg;
1758 val64 = readq(&bar0->mac_cfg);
1759 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1760 if (nic->device_type == XFRAME_II_DEVICE)
1761 writeq(val64, &bar0->mac_cfg);
1763 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1764 writel((u32) (val64), add);
1765 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1766 writel((u32) (val64 >> 32), (add + 4));
1770 * Set the time value to be inserted in the pause frame
1771 * generated by xena.
1773 val64 = readq(&bar0->rmac_pause_cfg);
1774 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1775 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1776 writeq(val64, &bar0->rmac_pause_cfg);
1779 * Set the Threshold Limit for Generating the pause frame
1780 * If the amount of data in any Queue exceeds ratio of
1781 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1782 * pause frame is generated
1785 for (i = 0; i < 4; i++) {
1786 val64 |= (((u64)0xFF00 |
1787 nic->mac_control.mc_pause_threshold_q0q3)
1790 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1793 for (i = 0; i < 4; i++) {
1794 val64 |= (((u64)0xFF00 |
1795 nic->mac_control.mc_pause_threshold_q4q7)
1798 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1801 * TxDMA will stop Read request if the number of read split has
1802 * exceeded the limit pointed by shared_splits
1804 val64 = readq(&bar0->pic_control);
1805 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1806 writeq(val64, &bar0->pic_control);
1808 if (nic->config.bus_speed == 266) {
1809 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1810 writeq(0x0, &bar0->read_retry_delay);
1811 writeq(0x0, &bar0->write_retry_delay);
1815 * Programming the Herc to split every write transaction
1816 * that does not start on an ADB to reduce disconnects.
1818 if (nic->device_type == XFRAME_II_DEVICE) {
1819 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1820 MISC_LINK_STABILITY_PRD(3);
1821 writeq(val64, &bar0->misc_control);
1822 val64 = readq(&bar0->pic_control2);
1823 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1824 writeq(val64, &bar0->pic_control2);
1826 if (strstr(nic->product_name, "CX4")) {
1827 val64 = TMAC_AVG_IPG(0x17);
1828 writeq(val64, &bar0->tmac_avg_ipg);
1833 #define LINK_UP_DOWN_INTERRUPT 1
1834 #define MAC_RMAC_ERR_TIMER 2
1836 static int s2io_link_fault_indication(struct s2io_nic *nic)
1838 if (nic->device_type == XFRAME_II_DEVICE)
1839 return LINK_UP_DOWN_INTERRUPT;
1841 return MAC_RMAC_ERR_TIMER;
1845 * do_s2io_write_bits - update alarm bits in alarm register
1846 * @value: alarm bits
1847 * @flag: interrupt status
1848 * @addr: address value
1849 * Description: update alarm bits in alarm register
1853 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1857 temp64 = readq(addr);
1859 if (flag == ENABLE_INTRS)
1860 temp64 &= ~((u64)value);
1862 temp64 |= ((u64)value);
1863 writeq(temp64, addr);
1866 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1868 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1869 register u64 gen_int_mask = 0;
1872 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1873 if (mask & TX_DMA_INTR) {
1874 gen_int_mask |= TXDMA_INT_M;
1876 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1877 TXDMA_PCC_INT | TXDMA_TTI_INT |
1878 TXDMA_LSO_INT | TXDMA_TPA_INT |
1879 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1881 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1882 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1883 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1884 &bar0->pfc_err_mask);
1886 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1887 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1888 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1890 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1891 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1892 PCC_N_SERR | PCC_6_COF_OV_ERR |
1893 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1894 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1896 flag, &bar0->pcc_err_mask);
1898 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1899 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1901 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1902 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1903 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1904 flag, &bar0->lso_err_mask);
1906 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1907 flag, &bar0->tpa_err_mask);
1909 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1912 if (mask & TX_MAC_INTR) {
1913 gen_int_mask |= TXMAC_INT_M;
1914 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1915 &bar0->mac_int_mask);
1916 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1917 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1918 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1919 flag, &bar0->mac_tmac_err_mask);
1922 if (mask & TX_XGXS_INTR) {
1923 gen_int_mask |= TXXGXS_INT_M;
1924 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1925 &bar0->xgxs_int_mask);
1926 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1927 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1928 flag, &bar0->xgxs_txgxs_err_mask);
1931 if (mask & RX_DMA_INTR) {
1932 gen_int_mask |= RXDMA_INT_M;
1933 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1934 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1935 flag, &bar0->rxdma_int_mask);
1936 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1937 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1938 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1939 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1940 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1941 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1942 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1943 &bar0->prc_pcix_err_mask);
1944 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1945 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1946 &bar0->rpa_err_mask);
1947 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1948 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1949 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1950 RDA_FRM_ECC_SG_ERR |
1951 RDA_MISC_ERR|RDA_PCIX_ERR,
1952 flag, &bar0->rda_err_mask);
1953 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1954 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1955 flag, &bar0->rti_err_mask);
1958 if (mask & RX_MAC_INTR) {
1959 gen_int_mask |= RXMAC_INT_M;
1960 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1961 &bar0->mac_int_mask);
1962 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1963 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1964 RMAC_DOUBLE_ECC_ERR);
1965 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
1966 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
1967 do_s2io_write_bits(interruptible,
1968 flag, &bar0->mac_rmac_err_mask);
1971 if (mask & RX_XGXS_INTR) {
1972 gen_int_mask |= RXXGXS_INT_M;
1973 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1974 &bar0->xgxs_int_mask);
1975 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1976 &bar0->xgxs_rxgxs_err_mask);
1979 if (mask & MC_INTR) {
1980 gen_int_mask |= MC_INT_M;
1981 do_s2io_write_bits(MC_INT_MASK_MC_INT,
1982 flag, &bar0->mc_int_mask);
1983 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1984 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1985 &bar0->mc_err_mask);
1987 nic->general_int_mask = gen_int_mask;
1989 /* Remove this line when alarm interrupts are enabled */
1990 nic->general_int_mask = 0;
1994 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1995 * @nic: device private variable,
1996 * @mask: A mask indicating which Intr block must be modified and,
1997 * @flag: A flag indicating whether to enable or disable the Intrs.
1998 * Description: This function will either disable or enable the interrupts
1999 * depending on the flag argument. The mask argument can be used to
2000 * enable/disable any Intr block.
2001 * Return Value: NONE.
2004 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2006 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2007 register u64 temp64 = 0, intr_mask = 0;
2009 intr_mask = nic->general_int_mask;
2011 /* Top level interrupt classification */
2012 /* PIC Interrupts */
2013 if (mask & TX_PIC_INTR) {
2014 /* Enable PIC Intrs in the general intr mask register */
2015 intr_mask |= TXPIC_INT_M;
2016 if (flag == ENABLE_INTRS) {
2018 * If Hercules adapter enable GPIO otherwise
2019 * disable all PCIX, Flash, MDIO, IIC and GPIO
2020 * interrupts for now.
2023 if (s2io_link_fault_indication(nic) ==
2024 LINK_UP_DOWN_INTERRUPT) {
2025 do_s2io_write_bits(PIC_INT_GPIO, flag,
2026 &bar0->pic_int_mask);
2027 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2028 &bar0->gpio_int_mask);
2030 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2031 } else if (flag == DISABLE_INTRS) {
2033 * Disable PIC Intrs in the general
2034 * intr mask register
2036 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2040 /* Tx traffic interrupts */
2041 if (mask & TX_TRAFFIC_INTR) {
2042 intr_mask |= TXTRAFFIC_INT_M;
2043 if (flag == ENABLE_INTRS) {
2045 * Enable all the Tx side interrupts
2046 * writing 0 Enables all 64 TX interrupt levels
2048 writeq(0x0, &bar0->tx_traffic_mask);
2049 } else if (flag == DISABLE_INTRS) {
2051 * Disable Tx Traffic Intrs in the general intr mask
2054 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2058 /* Rx traffic interrupts */
2059 if (mask & RX_TRAFFIC_INTR) {
2060 intr_mask |= RXTRAFFIC_INT_M;
2061 if (flag == ENABLE_INTRS) {
2062 /* writing 0 Enables all 8 RX interrupt levels */
2063 writeq(0x0, &bar0->rx_traffic_mask);
2064 } else if (flag == DISABLE_INTRS) {
2066 * Disable Rx Traffic Intrs in the general intr mask
2069 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2073 temp64 = readq(&bar0->general_int_mask);
2074 if (flag == ENABLE_INTRS)
2075 temp64 &= ~((u64)intr_mask);
2077 temp64 = DISABLE_ALL_INTRS;
2078 writeq(temp64, &bar0->general_int_mask);
2080 nic->general_int_mask = readq(&bar0->general_int_mask);
2084 * verify_pcc_quiescent- Checks for PCC quiescent state
2085 * Return: 1 If PCC is quiescence
2086 * 0 If PCC is not quiescence
2088 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2091 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2092 u64 val64 = readq(&bar0->adapter_status);
2094 herc = (sp->device_type == XFRAME_II_DEVICE);
2096 if (flag == false) {
2097 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2098 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2101 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2105 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2106 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2107 ADAPTER_STATUS_RMAC_PCC_IDLE))
2110 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2111 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2119 * verify_xena_quiescence - Checks whether the H/W is ready
2120 * Description: Returns whether the H/W is ready to go or not. Depending
2121 * on whether adapter enable bit was written or not the comparison
2122 * differs and the calling function passes the input argument flag to
2124 * Return: 1 If xena is quiescence
2125 * 0 If Xena is not quiescence
2128 static int verify_xena_quiescence(struct s2io_nic *sp)
2131 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2132 u64 val64 = readq(&bar0->adapter_status);
2133 mode = s2io_verify_pci_mode(sp);
2135 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2136 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2139 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2140 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2143 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2144 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2147 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2148 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2151 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2152 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2155 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2156 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2159 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2160 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2163 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2164 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2169 * In PCI 33 mode, the P_PLL is not used, and therefore,
2170 * the the P_PLL_LOCK bit in the adapter_status register will
2173 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2174 sp->device_type == XFRAME_II_DEVICE &&
2175 mode != PCI_MODE_PCI_33) {
2176 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2179 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2180 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2181 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2188 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2189 * @sp: Pointer to device specifc structure
2191 * New procedure to clear mac address reading problems on Alpha platforms
2195 static void fix_mac_address(struct s2io_nic *sp)
2197 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2200 while (fix_mac[i] != END_SIGN) {
2201 writeq(fix_mac[i++], &bar0->gpio_control);
2203 (void) readq(&bar0->gpio_control);
2208 * start_nic - Turns the device on
2209 * @nic : device private variable.
2211 * This function actually turns the device on. Before this function is
2212 * called,all Registers are configured from their reset states
2213 * and shared memory is allocated but the NIC is still quiescent. On
2214 * calling this function, the device interrupts are cleared and the NIC is
2215 * literally switched on by writing into the adapter control register.
2217 * SUCCESS on success and -1 on failure.
2220 static int start_nic(struct s2io_nic *nic)
2222 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2223 struct net_device *dev = nic->dev;
2224 register u64 val64 = 0;
2226 struct config_param *config = &nic->config;
2227 struct mac_info *mac_control = &nic->mac_control;
2229 /* PRC Initialization and configuration */
2230 for (i = 0; i < config->rx_ring_num; i++) {
2231 struct ring_info *ring = &mac_control->rings[i];
2233 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2234 &bar0->prc_rxd0_n[i]);
2236 val64 = readq(&bar0->prc_ctrl_n[i]);
2237 if (nic->rxd_mode == RXD_MODE_1)
2238 val64 |= PRC_CTRL_RC_ENABLED;
2240 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2241 if (nic->device_type == XFRAME_II_DEVICE)
2242 val64 |= PRC_CTRL_GROUP_READS;
2243 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2244 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2245 writeq(val64, &bar0->prc_ctrl_n[i]);
2248 if (nic->rxd_mode == RXD_MODE_3B) {
2249 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2250 val64 = readq(&bar0->rx_pa_cfg);
2251 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2252 writeq(val64, &bar0->rx_pa_cfg);
2255 if (vlan_tag_strip == 0) {
2256 val64 = readq(&bar0->rx_pa_cfg);
2257 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2258 writeq(val64, &bar0->rx_pa_cfg);
2259 nic->vlan_strip_flag = 0;
2263 * Enabling MC-RLDRAM. After enabling the device, we timeout
2264 * for around 100ms, which is approximately the time required
2265 * for the device to be ready for operation.
2267 val64 = readq(&bar0->mc_rldram_mrs);
2268 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2269 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2270 val64 = readq(&bar0->mc_rldram_mrs);
2272 msleep(100); /* Delay by around 100 ms. */
2274 /* Enabling ECC Protection. */
2275 val64 = readq(&bar0->adapter_control);
2276 val64 &= ~ADAPTER_ECC_EN;
2277 writeq(val64, &bar0->adapter_control);
2280 * Verify if the device is ready to be enabled, if so enable
2283 val64 = readq(&bar0->adapter_status);
2284 if (!verify_xena_quiescence(nic)) {
2285 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2286 "Adapter status reads: 0x%llx\n",
2287 dev->name, (unsigned long long)val64);
2292 * With some switches, link might be already up at this point.
2293 * Because of this weird behavior, when we enable laser,
2294 * we may not get link. We need to handle this. We cannot
2295 * figure out which switch is misbehaving. So we are forced to
2296 * make a global change.
2299 /* Enabling Laser. */
2300 val64 = readq(&bar0->adapter_control);
2301 val64 |= ADAPTER_EOI_TX_ON;
2302 writeq(val64, &bar0->adapter_control);
2304 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2306 * Dont see link state interrupts initially on some switches,
2307 * so directly scheduling the link state task here.
2309 schedule_work(&nic->set_link_task);
2311 /* SXE-002: Initialize link and activity LED */
2312 subid = nic->pdev->subsystem_device;
2313 if (((subid & 0xFF) >= 0x07) &&
2314 (nic->device_type == XFRAME_I_DEVICE)) {
2315 val64 = readq(&bar0->gpio_control);
2316 val64 |= 0x0000800000000000ULL;
2317 writeq(val64, &bar0->gpio_control);
2318 val64 = 0x0411040400000000ULL;
2319 writeq(val64, (void __iomem *)bar0 + 0x2700);
2325 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2327 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2328 struct TxD *txdlp, int get_off)
2330 struct s2io_nic *nic = fifo_data->nic;
2331 struct sk_buff *skb;
2336 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2337 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2338 sizeof(u64), PCI_DMA_TODEVICE);
2342 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2344 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2347 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2348 skb_headlen(skb), PCI_DMA_TODEVICE);
2349 frg_cnt = skb_shinfo(skb)->nr_frags;
2352 for (j = 0; j < frg_cnt; j++, txds++) {
2353 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2354 if (!txds->Buffer_Pointer)
2356 pci_unmap_page(nic->pdev,
2357 (dma_addr_t)txds->Buffer_Pointer,
2358 frag->size, PCI_DMA_TODEVICE);
2361 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2366 * free_tx_buffers - Free all queued Tx buffers
2367 * @nic : device private variable.
2369 * Free all queued Tx buffers.
2370 * Return Value: void
2373 static void free_tx_buffers(struct s2io_nic *nic)
2375 struct net_device *dev = nic->dev;
2376 struct sk_buff *skb;
2380 struct config_param *config = &nic->config;
2381 struct mac_info *mac_control = &nic->mac_control;
2382 struct stat_block *stats = mac_control->stats_info;
2383 struct swStat *swstats = &stats->sw_stat;
2385 for (i = 0; i < config->tx_fifo_num; i++) {
2386 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2387 struct fifo_info *fifo = &mac_control->fifos[i];
2388 unsigned long flags;
2390 spin_lock_irqsave(&fifo->tx_lock, flags);
2391 for (j = 0; j < tx_cfg->fifo_len; j++) {
2392 txdp = fifo->list_info[j].list_virt_addr;
2393 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2395 swstats->mem_freed += skb->truesize;
2401 "%s: forcibly freeing %d skbs on FIFO%d\n",
2403 fifo->tx_curr_get_info.offset = 0;
2404 fifo->tx_curr_put_info.offset = 0;
2405 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2410 * stop_nic - To stop the nic
2411 * @nic ; device private variable.
2413 * This function does exactly the opposite of what the start_nic()
2414 * function does. This function is called to stop the device.
2419 static void stop_nic(struct s2io_nic *nic)
2421 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2422 register u64 val64 = 0;
2425 /* Disable all interrupts */
2426 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2427 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2428 interruptible |= TX_PIC_INTR;
2429 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2431 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2432 val64 = readq(&bar0->adapter_control);
2433 val64 &= ~(ADAPTER_CNTL_EN);
2434 writeq(val64, &bar0->adapter_control);
2438 * fill_rx_buffers - Allocates the Rx side skbs
2439 * @ring_info: per ring structure
2440 * @from_card_up: If this is true, we will map the buffer to get
2441 * the dma address for buf0 and buf1 to give it to the card.
2442 * Else we will sync the already mapped buffer to give it to the card.
2444 * The function allocates Rx side skbs and puts the physical
2445 * address of these buffers into the RxD buffer pointers, so that the NIC
2446 * can DMA the received frame into these locations.
2447 * The NIC supports 3 receive modes, viz
2449 * 2. three buffer and
2450 * 3. Five buffer modes.
2451 * Each mode defines how many fragments the received frame will be split
2452 * up into by the NIC. The frame is split into L3 header, L4 Header,
2453 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2454 * is split into 3 fragments. As of now only single buffer mode is
2457 * SUCCESS on success or an appropriate -ve value on failure.
2459 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2462 struct sk_buff *skb;
2464 int off, size, block_no, block_no1;
2469 struct RxD_t *first_rxdp = NULL;
2470 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2474 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2476 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2478 block_no1 = ring->rx_curr_get_info.block_index;
2479 while (alloc_tab < alloc_cnt) {
2480 block_no = ring->rx_curr_put_info.block_index;
2482 off = ring->rx_curr_put_info.offset;
2484 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2486 rxd_index = off + 1;
2488 rxd_index += (block_no * ring->rxd_count);
2490 if ((block_no == block_no1) &&
2491 (off == ring->rx_curr_get_info.offset) &&
2492 (rxdp->Host_Control)) {
2493 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2497 if (off && (off == ring->rxd_count)) {
2498 ring->rx_curr_put_info.block_index++;
2499 if (ring->rx_curr_put_info.block_index ==
2501 ring->rx_curr_put_info.block_index = 0;
2502 block_no = ring->rx_curr_put_info.block_index;
2504 ring->rx_curr_put_info.offset = off;
2505 rxdp = ring->rx_blocks[block_no].block_virt_addr;
2506 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2507 ring->dev->name, rxdp);
2511 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2512 ((ring->rxd_mode == RXD_MODE_3B) &&
2513 (rxdp->Control_2 & s2BIT(0)))) {
2514 ring->rx_curr_put_info.offset = off;
2517 /* calculate size of skb based on ring mode */
2519 HEADER_ETHERNET_II_802_3_SIZE +
2520 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2521 if (ring->rxd_mode == RXD_MODE_1)
2522 size += NET_IP_ALIGN;
2524 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2527 skb = dev_alloc_skb(size);
2529 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2533 first_rxdp->Control_1 |= RXD_OWN_XENA;
2535 swstats->mem_alloc_fail_cnt++;
2539 swstats->mem_allocated += skb->truesize;
2541 if (ring->rxd_mode == RXD_MODE_1) {
2542 /* 1 buffer mode - normal operation mode */
2543 rxdp1 = (struct RxD1 *)rxdp;
2544 memset(rxdp, 0, sizeof(struct RxD1));
2545 skb_reserve(skb, NET_IP_ALIGN);
2546 rxdp1->Buffer0_ptr =
2547 pci_map_single(ring->pdev, skb->data,
2548 size - NET_IP_ALIGN,
2549 PCI_DMA_FROMDEVICE);
2550 if (pci_dma_mapping_error(nic->pdev,
2551 rxdp1->Buffer0_ptr))
2552 goto pci_map_failed;
2555 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2556 rxdp->Host_Control = (unsigned long)skb;
2557 } else if (ring->rxd_mode == RXD_MODE_3B) {
2560 * 2 buffer mode provides 128
2561 * byte aligned receive buffers.
2564 rxdp3 = (struct RxD3 *)rxdp;
2565 /* save buffer pointers to avoid frequent dma mapping */
2566 Buffer0_ptr = rxdp3->Buffer0_ptr;
2567 Buffer1_ptr = rxdp3->Buffer1_ptr;
2568 memset(rxdp, 0, sizeof(struct RxD3));
2569 /* restore the buffer pointers for dma sync*/
2570 rxdp3->Buffer0_ptr = Buffer0_ptr;
2571 rxdp3->Buffer1_ptr = Buffer1_ptr;
2573 ba = &ring->ba[block_no][off];
2574 skb_reserve(skb, BUF0_LEN);
2575 tmp = (u64)(unsigned long)skb->data;
2578 skb->data = (void *) (unsigned long)tmp;
2579 skb_reset_tail_pointer(skb);
2582 rxdp3->Buffer0_ptr =
2583 pci_map_single(ring->pdev, ba->ba_0,
2585 PCI_DMA_FROMDEVICE);
2586 if (pci_dma_mapping_error(nic->pdev,
2587 rxdp3->Buffer0_ptr))
2588 goto pci_map_failed;
2590 pci_dma_sync_single_for_device(ring->pdev,
2591 (dma_addr_t)rxdp3->Buffer0_ptr,
2593 PCI_DMA_FROMDEVICE);
2595 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2596 if (ring->rxd_mode == RXD_MODE_3B) {
2597 /* Two buffer mode */
2600 * Buffer2 will have L3/L4 header plus
2603 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2606 PCI_DMA_FROMDEVICE);
2608 if (pci_dma_mapping_error(nic->pdev,
2609 rxdp3->Buffer2_ptr))
2610 goto pci_map_failed;
2613 rxdp3->Buffer1_ptr =
2614 pci_map_single(ring->pdev,
2617 PCI_DMA_FROMDEVICE);
2619 if (pci_dma_mapping_error(nic->pdev,
2620 rxdp3->Buffer1_ptr)) {
2621 pci_unmap_single(ring->pdev,
2622 (dma_addr_t)(unsigned long)
2625 PCI_DMA_FROMDEVICE);
2626 goto pci_map_failed;
2629 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2630 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2633 rxdp->Control_2 |= s2BIT(0);
2634 rxdp->Host_Control = (unsigned long) (skb);
2636 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2637 rxdp->Control_1 |= RXD_OWN_XENA;
2639 if (off == (ring->rxd_count + 1))
2641 ring->rx_curr_put_info.offset = off;
2643 rxdp->Control_2 |= SET_RXD_MARKER;
2644 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2647 first_rxdp->Control_1 |= RXD_OWN_XENA;
2651 ring->rx_bufs_left += 1;
2656 /* Transfer ownership of first descriptor to adapter just before
2657 * exiting. Before that, use memory barrier so that ownership
2658 * and other fields are seen by adapter correctly.
2662 first_rxdp->Control_1 |= RXD_OWN_XENA;
2668 swstats->pci_map_fail_cnt++;
2669 swstats->mem_freed += skb->truesize;
2670 dev_kfree_skb_irq(skb);
2674 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2676 struct net_device *dev = sp->dev;
2678 struct sk_buff *skb;
2682 struct mac_info *mac_control = &sp->mac_control;
2683 struct stat_block *stats = mac_control->stats_info;
2684 struct swStat *swstats = &stats->sw_stat;
2686 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2687 rxdp = mac_control->rings[ring_no].
2688 rx_blocks[blk].rxds[j].virt_addr;
2689 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2692 if (sp->rxd_mode == RXD_MODE_1) {
2693 rxdp1 = (struct RxD1 *)rxdp;
2694 pci_unmap_single(sp->pdev,
2695 (dma_addr_t)rxdp1->Buffer0_ptr,
2697 HEADER_ETHERNET_II_802_3_SIZE +
2698 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2699 PCI_DMA_FROMDEVICE);
2700 memset(rxdp, 0, sizeof(struct RxD1));
2701 } else if (sp->rxd_mode == RXD_MODE_3B) {
2702 rxdp3 = (struct RxD3 *)rxdp;
2703 pci_unmap_single(sp->pdev,
2704 (dma_addr_t)rxdp3->Buffer0_ptr,
2706 PCI_DMA_FROMDEVICE);
2707 pci_unmap_single(sp->pdev,
2708 (dma_addr_t)rxdp3->Buffer1_ptr,
2710 PCI_DMA_FROMDEVICE);
2711 pci_unmap_single(sp->pdev,
2712 (dma_addr_t)rxdp3->Buffer2_ptr,
2714 PCI_DMA_FROMDEVICE);
2715 memset(rxdp, 0, sizeof(struct RxD3));
2717 swstats->mem_freed += skb->truesize;
2719 mac_control->rings[ring_no].rx_bufs_left -= 1;
2724 * free_rx_buffers - Frees all Rx buffers
2725 * @sp: device private variable.
2727 * This function will free all Rx buffers allocated by host.
2732 static void free_rx_buffers(struct s2io_nic *sp)
2734 struct net_device *dev = sp->dev;
2735 int i, blk = 0, buf_cnt = 0;
2736 struct config_param *config = &sp->config;
2737 struct mac_info *mac_control = &sp->mac_control;
2739 for (i = 0; i < config->rx_ring_num; i++) {
2740 struct ring_info *ring = &mac_control->rings[i];
2742 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2743 free_rxd_blk(sp, i, blk);
2745 ring->rx_curr_put_info.block_index = 0;
2746 ring->rx_curr_get_info.block_index = 0;
2747 ring->rx_curr_put_info.offset = 0;
2748 ring->rx_curr_get_info.offset = 0;
2749 ring->rx_bufs_left = 0;
2750 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2751 dev->name, buf_cnt, i);
2755 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2757 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2758 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2765 * s2io_poll - Rx interrupt handler for NAPI support
2766 * @napi : pointer to the napi structure.
2767 * @budget : The number of packets that were budgeted to be processed
2768 * during one pass through the 'Poll" function.
2770 * Comes into picture only if NAPI support has been incorporated. It does
2771 * the same thing that rx_intr_handler does, but not in a interrupt context
2772 * also It will process only a given number of packets.
2774 * 0 on success and 1 if there are No Rx packets to be processed.
2777 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2779 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2780 struct net_device *dev = ring->dev;
2781 int pkts_processed = 0;
2782 u8 __iomem *addr = NULL;
2784 struct s2io_nic *nic = netdev_priv(dev);
2785 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2786 int budget_org = budget;
2788 if (unlikely(!is_s2io_card_up(nic)))
2791 pkts_processed = rx_intr_handler(ring, budget);
2792 s2io_chk_rx_buffers(nic, ring);
2794 if (pkts_processed < budget_org) {
2795 napi_complete(napi);
2796 /*Re Enable MSI-Rx Vector*/
2797 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2798 addr += 7 - ring->ring_no;
2799 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2803 return pkts_processed;
2806 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2808 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2809 int pkts_processed = 0;
2810 int ring_pkts_processed, i;
2811 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2812 int budget_org = budget;
2813 struct config_param *config = &nic->config;
2814 struct mac_info *mac_control = &nic->mac_control;
2816 if (unlikely(!is_s2io_card_up(nic)))
2819 for (i = 0; i < config->rx_ring_num; i++) {
2820 struct ring_info *ring = &mac_control->rings[i];
2821 ring_pkts_processed = rx_intr_handler(ring, budget);
2822 s2io_chk_rx_buffers(nic, ring);
2823 pkts_processed += ring_pkts_processed;
2824 budget -= ring_pkts_processed;
2828 if (pkts_processed < budget_org) {
2829 napi_complete(napi);
2830 /* Re enable the Rx interrupts for the ring */
2831 writeq(0, &bar0->rx_traffic_mask);
2832 readl(&bar0->rx_traffic_mask);
2834 return pkts_processed;
2837 #ifdef CONFIG_NET_POLL_CONTROLLER
2839 * s2io_netpoll - netpoll event handler entry point
2840 * @dev : pointer to the device structure.
2842 * This function will be called by upper layer to check for events on the
2843 * interface in situations where interrupts are disabled. It is used for
2844 * specific in-kernel networking tasks, such as remote consoles and kernel
2845 * debugging over the network (example netdump in RedHat).
2847 static void s2io_netpoll(struct net_device *dev)
2849 struct s2io_nic *nic = netdev_priv(dev);
2850 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2851 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2853 struct config_param *config = &nic->config;
2854 struct mac_info *mac_control = &nic->mac_control;
2856 if (pci_channel_offline(nic->pdev))
2859 disable_irq(dev->irq);
2861 writeq(val64, &bar0->rx_traffic_int);
2862 writeq(val64, &bar0->tx_traffic_int);
2864 /* we need to free up the transmitted skbufs or else netpoll will
2865 * run out of skbs and will fail and eventually netpoll application such
2866 * as netdump will fail.
2868 for (i = 0; i < config->tx_fifo_num; i++)
2869 tx_intr_handler(&mac_control->fifos[i]);
2871 /* check for received packet and indicate up to network */
2872 for (i = 0; i < config->rx_ring_num; i++) {
2873 struct ring_info *ring = &mac_control->rings[i];
2875 rx_intr_handler(ring, 0);
2878 for (i = 0; i < config->rx_ring_num; i++) {
2879 struct ring_info *ring = &mac_control->rings[i];
2881 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2883 "%s: Out of memory in Rx Netpoll!!\n",
2888 enable_irq(dev->irq);
2893 * rx_intr_handler - Rx interrupt handler
2894 * @ring_info: per ring structure.
2895 * @budget: budget for napi processing.
2897 * If the interrupt is because of a received frame or if the
2898 * receive ring contains fresh as yet un-processed frames,this function is
2899 * called. It picks out the RxD at which place the last Rx processing had
2900 * stopped and sends the skb to the OSM's Rx handler and then increments
2903 * No. of napi packets processed.
2905 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2907 int get_block, put_block;
2908 struct rx_curr_get_info get_info, put_info;
2910 struct sk_buff *skb;
2911 int pkt_cnt = 0, napi_pkts = 0;
2916 get_info = ring_data->rx_curr_get_info;
2917 get_block = get_info.block_index;
2918 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2919 put_block = put_info.block_index;
2920 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2922 while (RXD_IS_UP2DT(rxdp)) {
2924 * If your are next to put index then it's
2925 * FIFO full condition
2927 if ((get_block == put_block) &&
2928 (get_info.offset + 1) == put_info.offset) {
2929 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2930 ring_data->dev->name);
2933 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2935 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2936 ring_data->dev->name);
2939 if (ring_data->rxd_mode == RXD_MODE_1) {
2940 rxdp1 = (struct RxD1 *)rxdp;
2941 pci_unmap_single(ring_data->pdev, (dma_addr_t)
2944 HEADER_ETHERNET_II_802_3_SIZE +
2947 PCI_DMA_FROMDEVICE);
2948 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
2949 rxdp3 = (struct RxD3 *)rxdp;
2950 pci_dma_sync_single_for_cpu(ring_data->pdev,
2951 (dma_addr_t)rxdp3->Buffer0_ptr,
2953 PCI_DMA_FROMDEVICE);
2954 pci_unmap_single(ring_data->pdev,
2955 (dma_addr_t)rxdp3->Buffer2_ptr,
2957 PCI_DMA_FROMDEVICE);
2959 prefetch(skb->data);
2960 rx_osm_handler(ring_data, rxdp);
2962 ring_data->rx_curr_get_info.offset = get_info.offset;
2963 rxdp = ring_data->rx_blocks[get_block].
2964 rxds[get_info.offset].virt_addr;
2965 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
2966 get_info.offset = 0;
2967 ring_data->rx_curr_get_info.offset = get_info.offset;
2969 if (get_block == ring_data->block_count)
2971 ring_data->rx_curr_get_info.block_index = get_block;
2972 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2975 if (ring_data->nic->config.napi) {
2982 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2985 if (ring_data->lro) {
2986 /* Clear all LRO sessions before exiting */
2987 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
2988 struct lro *lro = &ring_data->lro0_n[i];
2990 update_L3L4_header(ring_data->nic, lro);
2991 queue_rx_frame(lro->parent, lro->vlan_tag);
2992 clear_lro_session(lro);
3000 * tx_intr_handler - Transmit interrupt handler
3001 * @nic : device private variable
3003 * If an interrupt was raised to indicate DMA complete of the
3004 * Tx packet, this function is called. It identifies the last TxD
3005 * whose buffer was freed and frees all skbs whose data have already
3006 * DMA'ed into the NICs internal memory.
3011 static void tx_intr_handler(struct fifo_info *fifo_data)
3013 struct s2io_nic *nic = fifo_data->nic;
3014 struct tx_curr_get_info get_info, put_info;
3015 struct sk_buff *skb = NULL;
3018 unsigned long flags = 0;
3020 struct stat_block *stats = nic->mac_control.stats_info;
3021 struct swStat *swstats = &stats->sw_stat;
3023 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3026 get_info = fifo_data->tx_curr_get_info;
3027 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3028 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3029 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3030 (get_info.offset != put_info.offset) &&
3031 (txdlp->Host_Control)) {
3032 /* Check for TxD errors */
3033 if (txdlp->Control_1 & TXD_T_CODE) {
3034 unsigned long long err;
3035 err = txdlp->Control_1 & TXD_T_CODE;
3037 swstats->parity_err_cnt++;
3040 /* update t_code statistics */
3041 err_mask = err >> 48;
3044 swstats->tx_buf_abort_cnt++;
3048 swstats->tx_desc_abort_cnt++;
3052 swstats->tx_parity_err_cnt++;
3056 swstats->tx_link_loss_cnt++;
3060 swstats->tx_list_proc_err_cnt++;
3065 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3067 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3068 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3074 /* Updating the statistics block */
3075 swstats->mem_freed += skb->truesize;
3076 dev_kfree_skb_irq(skb);
3079 if (get_info.offset == get_info.fifo_len + 1)
3080 get_info.offset = 0;
3081 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3082 fifo_data->tx_curr_get_info.offset = get_info.offset;
3085 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3087 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3091 * s2io_mdio_write - Function to write in to MDIO registers
3092 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3093 * @addr : address value
3094 * @value : data value
3095 * @dev : pointer to net_device structure
3097 * This function is used to write values to the MDIO registers
3100 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3101 struct net_device *dev)
3104 struct s2io_nic *sp = netdev_priv(dev);
3105 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3107 /* address transaction */
3108 val64 = MDIO_MMD_INDX_ADDR(addr) |
3109 MDIO_MMD_DEV_ADDR(mmd_type) |
3110 MDIO_MMS_PRT_ADDR(0x0);
3111 writeq(val64, &bar0->mdio_control);
3112 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3113 writeq(val64, &bar0->mdio_control);
3116 /* Data transaction */
3117 val64 = MDIO_MMD_INDX_ADDR(addr) |
3118 MDIO_MMD_DEV_ADDR(mmd_type) |
3119 MDIO_MMS_PRT_ADDR(0x0) |
3120 MDIO_MDIO_DATA(value) |
3121 MDIO_OP(MDIO_OP_WRITE_TRANS);
3122 writeq(val64, &bar0->mdio_control);
3123 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3124 writeq(val64, &bar0->mdio_control);
3127 val64 = MDIO_MMD_INDX_ADDR(addr) |
3128 MDIO_MMD_DEV_ADDR(mmd_type) |
3129 MDIO_MMS_PRT_ADDR(0x0) |
3130 MDIO_OP(MDIO_OP_READ_TRANS);
3131 writeq(val64, &bar0->mdio_control);
3132 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3133 writeq(val64, &bar0->mdio_control);
3138 * s2io_mdio_read - Function to write in to MDIO registers
3139 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3140 * @addr : address value
3141 * @dev : pointer to net_device structure
3143 * This function is used to read values to the MDIO registers
3146 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3150 struct s2io_nic *sp = netdev_priv(dev);
3151 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3153 /* address transaction */
3154 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3155 | MDIO_MMD_DEV_ADDR(mmd_type)
3156 | MDIO_MMS_PRT_ADDR(0x0));
3157 writeq(val64, &bar0->mdio_control);
3158 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3159 writeq(val64, &bar0->mdio_control);
3162 /* Data transaction */
3163 val64 = MDIO_MMD_INDX_ADDR(addr) |
3164 MDIO_MMD_DEV_ADDR(mmd_type) |
3165 MDIO_MMS_PRT_ADDR(0x0) |
3166 MDIO_OP(MDIO_OP_READ_TRANS);
3167 writeq(val64, &bar0->mdio_control);
3168 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3169 writeq(val64, &bar0->mdio_control);
3172 /* Read the value from regs */
3173 rval64 = readq(&bar0->mdio_control);
3174 rval64 = rval64 & 0xFFFF0000;
3175 rval64 = rval64 >> 16;
3180 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3181 * @counter : counter value to be updated
3182 * @flag : flag to indicate the status
3183 * @type : counter type
3185 * This function is to check the status of the xpak counters value
3189 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3195 for (i = 0; i < index; i++)
3199 *counter = *counter + 1;
3200 val64 = *regs_stat & mask;
3201 val64 = val64 >> (index * 0x2);
3207 "Take Xframe NIC out of service.\n");
3209 "Excessive temperatures may result in premature transceiver failure.\n");
3213 "Take Xframe NIC out of service.\n");
3215 "Excessive bias currents may indicate imminent laser diode failure.\n");
3219 "Take Xframe NIC out of service.\n");
3221 "Excessive laser output power may saturate far-end receiver.\n");
3225 "Incorrect XPAK Alarm type\n");
3229 val64 = val64 << (index * 0x2);
3230 *regs_stat = (*regs_stat & (~mask)) | (val64);
3233 *regs_stat = *regs_stat & (~mask);
3238 * s2io_updt_xpak_counter - Function to update the xpak counters
3239 * @dev : pointer to net_device struct
3241 * This function is to upate the status of the xpak counters value
3244 static void s2io_updt_xpak_counter(struct net_device *dev)
3252 struct s2io_nic *sp = netdev_priv(dev);
3253 struct stat_block *stats = sp->mac_control.stats_info;
3254 struct xpakStat *xstats = &stats->xpak_stat;
3256 /* Check the communication with the MDIO slave */
3259 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3260 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3262 "ERR: MDIO slave access failed - Returned %llx\n",
3263 (unsigned long long)val64);
3267 /* Check for the expected value of control reg 1 */
3268 if (val64 != MDIO_CTRL1_SPEED10G) {
3269 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3270 "Returned: %llx- Expected: 0x%x\n",
3271 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3275 /* Loading the DOM register to MDIO register */
3277 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3278 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3280 /* Reading the Alarm flags */
3283 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3285 flag = CHECKBIT(val64, 0x7);
3287 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3288 &xstats->xpak_regs_stat,
3291 if (CHECKBIT(val64, 0x6))
3292 xstats->alarm_transceiver_temp_low++;
3294 flag = CHECKBIT(val64, 0x3);
3296 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3297 &xstats->xpak_regs_stat,
3300 if (CHECKBIT(val64, 0x2))
3301 xstats->alarm_laser_bias_current_low++;
3303 flag = CHECKBIT(val64, 0x1);
3305 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3306 &xstats->xpak_regs_stat,
3309 if (CHECKBIT(val64, 0x0))
3310 xstats->alarm_laser_output_power_low++;
3312 /* Reading the Warning flags */
3315 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3317 if (CHECKBIT(val64, 0x7))
3318 xstats->warn_transceiver_temp_high++;
3320 if (CHECKBIT(val64, 0x6))
3321 xstats->warn_transceiver_temp_low++;
3323 if (CHECKBIT(val64, 0x3))
3324 xstats->warn_laser_bias_current_high++;
3326 if (CHECKBIT(val64, 0x2))
3327 xstats->warn_laser_bias_current_low++;
3329 if (CHECKBIT(val64, 0x1))
3330 xstats->warn_laser_output_power_high++;
3332 if (CHECKBIT(val64, 0x0))
3333 xstats->warn_laser_output_power_low++;
3337 * wait_for_cmd_complete - waits for a command to complete.
3338 * @sp : private member of the device structure, which is a pointer to the
3339 * s2io_nic structure.
3340 * Description: Function that waits for a command to Write into RMAC
3341 * ADDR DATA registers to be completed and returns either success or
3342 * error depending on whether the command was complete or not.
3344 * SUCCESS on success and FAILURE on failure.
3347 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3350 int ret = FAILURE, cnt = 0, delay = 1;
3353 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3357 val64 = readq(addr);
3358 if (bit_state == S2IO_BIT_RESET) {
3359 if (!(val64 & busy_bit)) {
3364 if (val64 & busy_bit) {
3381 * check_pci_device_id - Checks if the device id is supported
3383 * Description: Function to check if the pci device id is supported by driver.
3384 * Return value: Actual device id if supported else PCI_ANY_ID
3386 static u16 check_pci_device_id(u16 id)
3389 case PCI_DEVICE_ID_HERC_WIN:
3390 case PCI_DEVICE_ID_HERC_UNI:
3391 return XFRAME_II_DEVICE;
3392 case PCI_DEVICE_ID_S2IO_UNI:
3393 case PCI_DEVICE_ID_S2IO_WIN:
3394 return XFRAME_I_DEVICE;
3401 * s2io_reset - Resets the card.
3402 * @sp : private member of the device structure.
3403 * Description: Function to Reset the card. This function then also
3404 * restores the previously saved PCI configuration space registers as
3405 * the card reset also resets the configuration space.
3410 static void s2io_reset(struct s2io_nic *sp)
3412 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3417 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3418 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3419 struct stat_block *stats;
3420 struct swStat *swstats;
3422 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3423 __func__, pci_name(sp->pdev));
3425 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3426 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3428 val64 = SW_RESET_ALL;
3429 writeq(val64, &bar0->sw_reset);
3430 if (strstr(sp->product_name, "CX4"))
3433 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3435 /* Restore the PCI state saved during initialization. */
3436 pci_restore_state(sp->pdev);
3437 pci_save_state(sp->pdev);
3438 pci_read_config_word(sp->pdev, 0x2, &val16);
3439 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3444 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3445 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3447 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3451 /* Set swapper to enable I/O register access */
3452 s2io_set_swapper(sp);
3454 /* restore mac_addr entries */
3455 do_s2io_restore_unicast_mc(sp);
3457 /* Restore the MSIX table entries from local variables */
3458 restore_xmsi_data(sp);
3460 /* Clear certain PCI/PCI-X fields after reset */
3461 if (sp->device_type == XFRAME_II_DEVICE) {
3462 /* Clear "detected parity error" bit */
3463 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3465 /* Clearing PCIX Ecc status register */
3466 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3468 /* Clearing PCI_STATUS error reflected here */
3469 writeq(s2BIT(62), &bar0->txpic_int_reg);
3472 /* Reset device statistics maintained by OS */
3473 memset(&sp->stats, 0, sizeof(struct net_device_stats));
3475 stats = sp->mac_control.stats_info;
3476 swstats = &stats->sw_stat;
3478 /* save link up/down time/cnt, reset/memory/watchdog cnt */
3479 up_cnt = swstats->link_up_cnt;
3480 down_cnt = swstats->link_down_cnt;
3481 up_time = swstats->link_up_time;
3482 down_time = swstats->link_down_time;
3483 reset_cnt = swstats->soft_reset_cnt;
3484 mem_alloc_cnt = swstats->mem_allocated;
3485 mem_free_cnt = swstats->mem_freed;
3486 watchdog_cnt = swstats->watchdog_timer_cnt;
3488 memset(stats, 0, sizeof(struct stat_block));
3490 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3491 swstats->link_up_cnt = up_cnt;
3492 swstats->link_down_cnt = down_cnt;
3493 swstats->link_up_time = up_time;
3494 swstats->link_down_time = down_time;
3495 swstats->soft_reset_cnt = reset_cnt;
3496 swstats->mem_allocated = mem_alloc_cnt;
3497 swstats->mem_freed = mem_free_cnt;
3498 swstats->watchdog_timer_cnt = watchdog_cnt;
3500 /* SXE-002: Configure link and activity LED to turn it off */
3501 subid = sp->pdev->subsystem_device;
3502 if (((subid & 0xFF) >= 0x07) &&
3503 (sp->device_type == XFRAME_I_DEVICE)) {
3504 val64 = readq(&bar0->gpio_control);
3505 val64 |= 0x0000800000000000ULL;
3506 writeq(val64, &bar0->gpio_control);
3507 val64 = 0x0411040400000000ULL;
3508 writeq(val64, (void __iomem *)bar0 + 0x2700);
3512 * Clear spurious ECC interrupts that would have occurred on
3513 * XFRAME II cards after reset.
3515 if (sp->device_type == XFRAME_II_DEVICE) {
3516 val64 = readq(&bar0->pcc_err_reg);
3517 writeq(val64, &bar0->pcc_err_reg);
3520 sp->device_enabled_once = false;
3524 * s2io_set_swapper - to set the swapper controle on the card
3525 * @sp : private member of the device structure,
3526 * pointer to the s2io_nic structure.
3527 * Description: Function to set the swapper control on the card
3528 * correctly depending on the 'endianness' of the system.
3530 * SUCCESS on success and FAILURE on failure.
3533 static int s2io_set_swapper(struct s2io_nic *sp)
3535 struct net_device *dev = sp->dev;
3536 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3537 u64 val64, valt, valr;
3540 * Set proper endian settings and verify the same by reading
3541 * the PIF Feed-back register.
3544 val64 = readq(&bar0->pif_rd_swapper_fb);
3545 if (val64 != 0x0123456789ABCDEFULL) {
3547 static const u64 value[] = {
3548 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3549 0x8100008181000081ULL, /* FE=1, SE=0 */
3550 0x4200004242000042ULL, /* FE=0, SE=1 */
3555 writeq(value[i], &bar0->swapper_ctrl);
3556 val64 = readq(&bar0->pif_rd_swapper_fb);
3557 if (val64 == 0x0123456789ABCDEFULL)
3562 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3563 "feedback read %llx\n",
3564 dev->name, (unsigned long long)val64);
3569 valr = readq(&bar0->swapper_ctrl);
3572 valt = 0x0123456789ABCDEFULL;
3573 writeq(valt, &bar0->xmsi_address);
3574 val64 = readq(&bar0->xmsi_address);
3576 if (val64 != valt) {
3578 static const u64 value[] = {
3579 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3580 0x0081810000818100ULL, /* FE=1, SE=0 */
3581 0x0042420000424200ULL, /* FE=0, SE=1 */
3586 writeq((value[i] | valr), &bar0->swapper_ctrl);
3587 writeq(valt, &bar0->xmsi_address);
3588 val64 = readq(&bar0->xmsi_address);
3594 unsigned long long x = val64;
3596 "Write failed, Xmsi_addr reads:0x%llx\n", x);
3600 val64 = readq(&bar0->swapper_ctrl);
3601 val64 &= 0xFFFF000000000000ULL;
3605 * The device by default set to a big endian format, so a
3606 * big endian driver need not set anything.
3608 val64 |= (SWAPPER_CTRL_TXP_FE |
3609 SWAPPER_CTRL_TXP_SE |
3610 SWAPPER_CTRL_TXD_R_FE |
3611 SWAPPER_CTRL_TXD_W_FE |
3612 SWAPPER_CTRL_TXF_R_FE |
3613 SWAPPER_CTRL_RXD_R_FE |
3614 SWAPPER_CTRL_RXD_W_FE |
3615 SWAPPER_CTRL_RXF_W_FE |
3616 SWAPPER_CTRL_XMSI_FE |
3617 SWAPPER_CTRL_STATS_FE |
3618 SWAPPER_CTRL_STATS_SE);
3619 if (sp->config.intr_type == INTA)
3620 val64 |= SWAPPER_CTRL_XMSI_SE;
3621 writeq(val64, &bar0->swapper_ctrl);
3624 * Initially we enable all bits to make it accessible by the
3625 * driver, then we selectively enable only those bits that
3628 val64 |= (SWAPPER_CTRL_TXP_FE |
3629 SWAPPER_CTRL_TXP_SE |
3630 SWAPPER_CTRL_TXD_R_FE |
3631 SWAPPER_CTRL_TXD_R_SE |
3632 SWAPPER_CTRL_TXD_W_FE |
3633 SWAPPER_CTRL_TXD_W_SE |
3634 SWAPPER_CTRL_TXF_R_FE |
3635 SWAPPER_CTRL_RXD_R_FE |
3636 SWAPPER_CTRL_RXD_R_SE |
3637 SWAPPER_CTRL_RXD_W_FE |
3638 SWAPPER_CTRL_RXD_W_SE |
3639 SWAPPER_CTRL_RXF_W_FE |
3640 SWAPPER_CTRL_XMSI_FE |
3641 SWAPPER_CTRL_STATS_FE |
3642 SWAPPER_CTRL_STATS_SE);
3643 if (sp->config.intr_type == INTA)
3644 val64 |= SWAPPER_CTRL_XMSI_SE;
3645 writeq(val64, &bar0->swapper_ctrl);
3647 val64 = readq(&bar0->swapper_ctrl);
3650 * Verifying if endian settings are accurate by reading a
3651 * feedback register.
3653 val64 = readq(&bar0->pif_rd_swapper_fb);
3654 if (val64 != 0x0123456789ABCDEFULL) {
3655 /* Endian settings are incorrect, calls for another dekko. */
3657 "%s: Endian settings are wrong, feedback read %llx\n",
3658 dev->name, (unsigned long long)val64);
3665 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3667 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3669 int ret = 0, cnt = 0;
3672 val64 = readq(&bar0->xmsi_access);
3673 if (!(val64 & s2BIT(15)))
3679 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3686 static void restore_xmsi_data(struct s2io_nic *nic)
3688 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3692 if (nic->device_type == XFRAME_I_DEVICE)
3695 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3696 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3697 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3698 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3699 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3700 writeq(val64, &bar0->xmsi_access);
3701 if (wait_for_msix_trans(nic, msix_index)) {
3702 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3703 __func__, msix_index);
3709 static void store_xmsi_data(struct s2io_nic *nic)
3711 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3712 u64 val64, addr, data;
3715 if (nic->device_type == XFRAME_I_DEVICE)
3718 /* Store and display */
3719 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3720 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3721 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3722 writeq(val64, &bar0->xmsi_access);
3723 if (wait_for_msix_trans(nic, msix_index)) {
3724 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3725 __func__, msix_index);
3728 addr = readq(&bar0->xmsi_address);
3729 data = readq(&bar0->xmsi_data);
3731 nic->msix_info[i].addr = addr;
3732 nic->msix_info[i].data = data;
3737 static int s2io_enable_msi_x(struct s2io_nic *nic)
3739 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3741 u16 msi_control; /* Temp variable */
3742 int ret, i, j, msix_indx = 1;
3744 struct stat_block *stats = nic->mac_control.stats_info;
3745 struct swStat *swstats = &stats->sw_stat;
3747 size = nic->num_entries * sizeof(struct msix_entry);
3748 nic->entries = kzalloc(size, GFP_KERNEL);
3749 if (!nic->entries) {
3750 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3752 swstats->mem_alloc_fail_cnt++;
3755 swstats->mem_allocated += size;
3757 size = nic->num_entries * sizeof(struct s2io_msix_entry);
3758 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3759 if (!nic->s2io_entries) {
3760 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3762 swstats->mem_alloc_fail_cnt++;
3763 kfree(nic->entries);
3765 += (nic->num_entries * sizeof(struct msix_entry));
3768 swstats->mem_allocated += size;
3770 nic->entries[0].entry = 0;
3771 nic->s2io_entries[0].entry = 0;
3772 nic->s2io_entries[0].in_use = MSIX_FLG;
3773 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3774 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3776 for (i = 1; i < nic->num_entries; i++) {
3777 nic->entries[i].entry = ((i - 1) * 8) + 1;
3778 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3779 nic->s2io_entries[i].arg = NULL;
3780 nic->s2io_entries[i].in_use = 0;
3783 rx_mat = readq(&bar0->rx_mat);
3784 for (j = 0; j < nic->config.rx_ring_num; j++) {
3785 rx_mat |= RX_MAT_SET(j, msix_indx);
3786 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3787 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3788 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3791 writeq(rx_mat, &bar0->rx_mat);
3792 readq(&bar0->rx_mat);
3794 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
3795 /* We fail init if error or we get less vectors than min required */
3797 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3798 kfree(nic->entries);
3799 swstats->mem_freed += nic->num_entries *
3800 sizeof(struct msix_entry);
3801 kfree(nic->s2io_entries);
3802 swstats->mem_freed += nic->num_entries *
3803 sizeof(struct s2io_msix_entry);
3804 nic->entries = NULL;
3805 nic->s2io_entries = NULL;
3810 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3811 * in the herc NIC. (Temp change, needs to be removed later)
3813 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3814 msi_control |= 0x1; /* Enable MSI */
3815 pci_write_config_word(nic->pdev, 0x42, msi_control);
3820 /* Handle software interrupt used during MSI(X) test */
3821 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3823 struct s2io_nic *sp = dev_id;
3825 sp->msi_detected = 1;
3826 wake_up(&sp->msi_wait);
3831 /* Test interrupt path by forcing a a software IRQ */
3832 static int s2io_test_msi(struct s2io_nic *sp)
3834 struct pci_dev *pdev = sp->pdev;
3835 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3839 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3842 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3843 sp->dev->name, pci_name(pdev), pdev->irq);
3847 init_waitqueue_head(&sp->msi_wait);
3848 sp->msi_detected = 0;
3850 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3851 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3852 val64 |= SCHED_INT_CTRL_TIMER_EN;
3853 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3854 writeq(val64, &bar0->scheduled_int_ctrl);
3856 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3858 if (!sp->msi_detected) {
3859 /* MSI(X) test failed, go back to INTx mode */
3860 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3861 "using MSI(X) during test\n",
3862 sp->dev->name, pci_name(pdev));
3867 free_irq(sp->entries[1].vector, sp);
3869 writeq(saved64, &bar0->scheduled_int_ctrl);
3874 static void remove_msix_isr(struct s2io_nic *sp)
3879 for (i = 0; i < sp->num_entries; i++) {
3880 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3881 int vector = sp->entries[i].vector;
3882 void *arg = sp->s2io_entries[i].arg;
3883 free_irq(vector, arg);
3888 kfree(sp->s2io_entries);
3890 sp->s2io_entries = NULL;
3892 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3893 msi_control &= 0xFFFE; /* Disable MSI */
3894 pci_write_config_word(sp->pdev, 0x42, msi_control);
3896 pci_disable_msix(sp->pdev);
3899 static void remove_inta_isr(struct s2io_nic *sp)
3901 struct net_device *dev = sp->dev;
3903 free_irq(sp->pdev->irq, dev);
3906 /* ********************************************************* *
3907 * Functions defined below concern the OS part of the driver *
3908 * ********************************************************* */
3911 * s2io_open - open entry point of the driver
3912 * @dev : pointer to the device structure.
3914 * This function is the open entry point of the driver. It mainly calls a
3915 * function to allocate Rx buffers and inserts them into the buffer
3916 * descriptors and then enables the Rx part of the NIC.
3918 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3922 static int s2io_open(struct net_device *dev)
3924 struct s2io_nic *sp = netdev_priv(dev);
3925 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3929 * Make sure you have link off by default every time
3930 * Nic is initialized
3932 netif_carrier_off(dev);
3933 sp->last_link_state = 0;
3935 /* Initialize H/W and enable interrupts */
3936 err = s2io_card_up(sp);
3938 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3940 goto hw_init_failed;
3943 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3944 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3947 goto hw_init_failed;
3949 s2io_start_all_tx_queue(sp);
3953 if (sp->config.intr_type == MSI_X) {
3956 swstats->mem_freed += sp->num_entries *
3957 sizeof(struct msix_entry);
3959 if (sp->s2io_entries) {
3960 kfree(sp->s2io_entries);
3961 swstats->mem_freed += sp->num_entries *
3962 sizeof(struct s2io_msix_entry);
3969 * s2io_close -close entry point of the driver
3970 * @dev : device pointer.
3972 * This is the stop entry point of the driver. It needs to undo exactly
3973 * whatever was done by the open entry point,thus it's usually referred to
3974 * as the close function.Among other things this function mainly stops the
3975 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3977 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3981 static int s2io_close(struct net_device *dev)
3983 struct s2io_nic *sp = netdev_priv(dev);
3984 struct config_param *config = &sp->config;
3988 /* Return if the device is already closed *
3989 * Can happen when s2io_card_up failed in change_mtu *
3991 if (!is_s2io_card_up(sp))
3994 s2io_stop_all_tx_queue(sp);
3995 /* delete all populated mac entries */
3996 for (offset = 1; offset < config->max_mc_addr; offset++) {
3997 tmp64 = do_s2io_read_unicast_mc(sp, offset);
3998 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3999 do_s2io_delete_unicast_mc(sp, tmp64);
4008 * s2io_xmit - Tx entry point of te driver
4009 * @skb : the socket buffer containing the Tx data.
4010 * @dev : device pointer.
4012 * This function is the Tx entry point of the driver. S2IO NIC supports
4013 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4014 * NOTE: when device can't queue the pkt,just the trans_start variable will
4017 * 0 on success & 1 on failure.
4020 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4022 struct s2io_nic *sp = netdev_priv(dev);
4023 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4026 struct TxFIFO_element __iomem *tx_fifo;
4027 unsigned long flags = 0;
4029 struct fifo_info *fifo = NULL;
4030 int do_spin_lock = 1;
4032 int enable_per_list_interrupt = 0;
4033 struct config_param *config = &sp->config;
4034 struct mac_info *mac_control = &sp->mac_control;
4035 struct stat_block *stats = mac_control->stats_info;
4036 struct swStat *swstats = &stats->sw_stat;
4038 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4040 if (unlikely(skb->len <= 0)) {
4041 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4042 dev_kfree_skb_any(skb);
4043 return NETDEV_TX_OK;
4046 if (!is_s2io_card_up(sp)) {
4047 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4050 return NETDEV_TX_OK;
4054 if (vlan_tx_tag_present(skb))
4055 vlan_tag = vlan_tx_tag_get(skb);
4056 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4057 if (skb->protocol == htons(ETH_P_IP)) {
4062 if (!ip_is_fragment(ip)) {
4063 th = (struct tcphdr *)(((unsigned char *)ip) +
4066 if (ip->protocol == IPPROTO_TCP) {
4067 queue_len = sp->total_tcp_fifos;
4068 queue = (ntohs(th->source) +
4070 sp->fifo_selector[queue_len - 1];
4071 if (queue >= queue_len)
4072 queue = queue_len - 1;
4073 } else if (ip->protocol == IPPROTO_UDP) {
4074 queue_len = sp->total_udp_fifos;
4075 queue = (ntohs(th->source) +
4077 sp->fifo_selector[queue_len - 1];
4078 if (queue >= queue_len)
4079 queue = queue_len - 1;
4080 queue += sp->udp_fifo_idx;
4081 if (skb->len > 1024)
4082 enable_per_list_interrupt = 1;
4087 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4088 /* get fifo number based on skb->priority value */
4089 queue = config->fifo_mapping
4090 [skb->priority & (MAX_TX_FIFOS - 1)];
4091 fifo = &mac_control->fifos[queue];
4094 spin_lock_irqsave(&fifo->tx_lock, flags);
4096 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4097 return NETDEV_TX_LOCKED;
4100 if (sp->config.multiq) {
4101 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4102 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4103 return NETDEV_TX_BUSY;
4105 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4106 if (netif_queue_stopped(dev)) {
4107 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4108 return NETDEV_TX_BUSY;
4112 put_off = (u16)fifo->tx_curr_put_info.offset;
4113 get_off = (u16)fifo->tx_curr_get_info.offset;
4114 txdp = fifo->list_info[put_off].list_virt_addr;
4116 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4117 /* Avoid "put" pointer going beyond "get" pointer */
4118 if (txdp->Host_Control ||
4119 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4120 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4121 s2io_stop_tx_queue(sp, fifo->fifo_no);
4123 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4124 return NETDEV_TX_OK;
4127 offload_type = s2io_offload_type(skb);
4128 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4129 txdp->Control_1 |= TXD_TCP_LSO_EN;
4130 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4132 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4133 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4137 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4138 txdp->Control_1 |= TXD_LIST_OWN_XENA;
4139 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4140 if (enable_per_list_interrupt)
4141 if (put_off & (queue_len >> 5))
4142 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4144 txdp->Control_2 |= TXD_VLAN_ENABLE;
4145 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4148 frg_len = skb_headlen(skb);
4149 if (offload_type == SKB_GSO_UDP) {
4152 ufo_size = s2io_udp_mss(skb);
4154 txdp->Control_1 |= TXD_UFO_EN;
4155 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4156 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4158 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4159 fifo->ufo_in_band_v[put_off] =
4160 (__force u64)skb_shinfo(skb)->ip6_frag_id;
4162 fifo->ufo_in_band_v[put_off] =
4163 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4165 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4166 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4167 fifo->ufo_in_band_v,
4170 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4171 goto pci_map_failed;
4175 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4176 frg_len, PCI_DMA_TODEVICE);
4177 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4178 goto pci_map_failed;
4180 txdp->Host_Control = (unsigned long)skb;
4181 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4182 if (offload_type == SKB_GSO_UDP)
4183 txdp->Control_1 |= TXD_UFO_EN;
4185 frg_cnt = skb_shinfo(skb)->nr_frags;
4186 /* For fragmented SKB. */
4187 for (i = 0; i < frg_cnt; i++) {
4188 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4189 /* A '0' length fragment will be ignored */
4193 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4197 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
4198 if (offload_type == SKB_GSO_UDP)
4199 txdp->Control_1 |= TXD_UFO_EN;
4201 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4203 if (offload_type == SKB_GSO_UDP)
4204 frg_cnt++; /* as Txd0 was used for inband header */
4206 tx_fifo = mac_control->tx_FIFO_start[queue];
4207 val64 = fifo->list_info[put_off].list_phy_addr;
4208 writeq(val64, &tx_fifo->TxDL_Pointer);
4210 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4213 val64 |= TX_FIFO_SPECIAL_FUNC;
4215 writeq(val64, &tx_fifo->List_Control);
4220 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4222 fifo->tx_curr_put_info.offset = put_off;
4224 /* Avoid "put" pointer going beyond "get" pointer */
4225 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4226 swstats->fifo_full_cnt++;
4228 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4230 s2io_stop_tx_queue(sp, fifo->fifo_no);
4232 swstats->mem_allocated += skb->truesize;
4233 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4235 if (sp->config.intr_type == MSI_X)
4236 tx_intr_handler(fifo);
4238 return NETDEV_TX_OK;
4241 swstats->pci_map_fail_cnt++;
4242 s2io_stop_tx_queue(sp, fifo->fifo_no);
4243 swstats->mem_freed += skb->truesize;
4245 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4246 return NETDEV_TX_OK;
4250 s2io_alarm_handle(unsigned long data)
4252 struct s2io_nic *sp = (struct s2io_nic *)data;
4253 struct net_device *dev = sp->dev;
4255 s2io_handle_errors(dev);
4256 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4259 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4261 struct ring_info *ring = (struct ring_info *)dev_id;
4262 struct s2io_nic *sp = ring->nic;
4263 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4265 if (unlikely(!is_s2io_card_up(sp)))
4268 if (sp->config.napi) {
4269 u8 __iomem *addr = NULL;
4272 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4273 addr += (7 - ring->ring_no);
4274 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4277 napi_schedule(&ring->napi);
4279 rx_intr_handler(ring, 0);
4280 s2io_chk_rx_buffers(sp, ring);
4286 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4289 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4290 struct s2io_nic *sp = fifos->nic;
4291 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4292 struct config_param *config = &sp->config;
4295 if (unlikely(!is_s2io_card_up(sp)))
4298 reason = readq(&bar0->general_int_status);
4299 if (unlikely(reason == S2IO_MINUS_ONE))
4300 /* Nothing much can be done. Get out */
4303 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4304 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4306 if (reason & GEN_INTR_TXPIC)
4307 s2io_txpic_intr_handle(sp);
4309 if (reason & GEN_INTR_TXTRAFFIC)
4310 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4312 for (i = 0; i < config->tx_fifo_num; i++)
4313 tx_intr_handler(&fifos[i]);
4315 writeq(sp->general_int_mask, &bar0->general_int_mask);
4316 readl(&bar0->general_int_status);
4319 /* The interrupt was not raised by us */
4323 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4325 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4328 val64 = readq(&bar0->pic_int_status);
4329 if (val64 & PIC_INT_GPIO) {
4330 val64 = readq(&bar0->gpio_int_reg);
4331 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4332 (val64 & GPIO_INT_REG_LINK_UP)) {
4334 * This is unstable state so clear both up/down
4335 * interrupt and adapter to re-evaluate the link state.
4337 val64 |= GPIO_INT_REG_LINK_DOWN;
4338 val64 |= GPIO_INT_REG_LINK_UP;
4339 writeq(val64, &bar0->gpio_int_reg);
4340 val64 = readq(&bar0->gpio_int_mask);
4341 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4342 GPIO_INT_MASK_LINK_DOWN);
4343 writeq(val64, &bar0->gpio_int_mask);
4344 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4345 val64 = readq(&bar0->adapter_status);
4346 /* Enable Adapter */
4347 val64 = readq(&bar0->adapter_control);
4348 val64 |= ADAPTER_CNTL_EN;
4349 writeq(val64, &bar0->adapter_control);
4350 val64 |= ADAPTER_LED_ON;
4351 writeq(val64, &bar0->adapter_control);
4352 if (!sp->device_enabled_once)
4353 sp->device_enabled_once = 1;
4355 s2io_link(sp, LINK_UP);
4357 * unmask link down interrupt and mask link-up
4360 val64 = readq(&bar0->gpio_int_mask);
4361 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4362 val64 |= GPIO_INT_MASK_LINK_UP;
4363 writeq(val64, &bar0->gpio_int_mask);
4365 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4366 val64 = readq(&bar0->adapter_status);
4367 s2io_link(sp, LINK_DOWN);
4368 /* Link is down so unmaks link up interrupt */
4369 val64 = readq(&bar0->gpio_int_mask);
4370 val64 &= ~GPIO_INT_MASK_LINK_UP;
4371 val64 |= GPIO_INT_MASK_LINK_DOWN;
4372 writeq(val64, &bar0->gpio_int_mask);
4375 val64 = readq(&bar0->adapter_control);
4376 val64 = val64 & (~ADAPTER_LED_ON);
4377 writeq(val64, &bar0->adapter_control);
4380 val64 = readq(&bar0->gpio_int_mask);
4384 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4385 * @value: alarm bits
4386 * @addr: address value
4387 * @cnt: counter variable
4388 * Description: Check for alarm and increment the counter
4390 * 1 - if alarm bit set
4391 * 0 - if alarm bit is not set
4393 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4394 unsigned long long *cnt)
4397 val64 = readq(addr);
4398 if (val64 & value) {
4399 writeq(val64, addr);
4408 * s2io_handle_errors - Xframe error indication handler
4409 * @nic: device private variable
4410 * Description: Handle alarms such as loss of link, single or
4411 * double ECC errors, critical and serious errors.
4415 static void s2io_handle_errors(void *dev_id)
4417 struct net_device *dev = (struct net_device *)dev_id;
4418 struct s2io_nic *sp = netdev_priv(dev);
4419 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4420 u64 temp64 = 0, val64 = 0;
4423 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4424 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4426 if (!is_s2io_card_up(sp))
4429 if (pci_channel_offline(sp->pdev))
4432 memset(&sw_stat->ring_full_cnt, 0,
4433 sizeof(sw_stat->ring_full_cnt));
4435 /* Handling the XPAK counters update */
4436 if (stats->xpak_timer_count < 72000) {
4437 /* waiting for an hour */
4438 stats->xpak_timer_count++;
4440 s2io_updt_xpak_counter(dev);
4441 /* reset the count to zero */
4442 stats->xpak_timer_count = 0;
4445 /* Handling link status change error Intr */
4446 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4447 val64 = readq(&bar0->mac_rmac_err_reg);
4448 writeq(val64, &bar0->mac_rmac_err_reg);
4449 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4450 schedule_work(&sp->set_link_task);
4453 /* In case of a serious error, the device will be Reset. */
4454 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4455 &sw_stat->serious_err_cnt))
4458 /* Check for data parity error */
4459 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4460 &sw_stat->parity_err_cnt))
4463 /* Check for ring full counter */
4464 if (sp->device_type == XFRAME_II_DEVICE) {
4465 val64 = readq(&bar0->ring_bump_counter1);
4466 for (i = 0; i < 4; i++) {
4467 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4468 temp64 >>= 64 - ((i+1)*16);
4469 sw_stat->ring_full_cnt[i] += temp64;
4472 val64 = readq(&bar0->ring_bump_counter2);
4473 for (i = 0; i < 4; i++) {
4474 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4475 temp64 >>= 64 - ((i+1)*16);
4476 sw_stat->ring_full_cnt[i+4] += temp64;
4480 val64 = readq(&bar0->txdma_int_status);
4481 /*check for pfc_err*/
4482 if (val64 & TXDMA_PFC_INT) {
4483 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4484 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4487 &sw_stat->pfc_err_cnt))
4489 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4491 &sw_stat->pfc_err_cnt);
4494 /*check for tda_err*/
4495 if (val64 & TXDMA_TDA_INT) {
4496 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4500 &sw_stat->tda_err_cnt))
4502 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4504 &sw_stat->tda_err_cnt);
4506 /*check for pcc_err*/
4507 if (val64 & TXDMA_PCC_INT) {
4508 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4509 PCC_N_SERR | PCC_6_COF_OV_ERR |
4510 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4511 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4514 &sw_stat->pcc_err_cnt))
4516 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4518 &sw_stat->pcc_err_cnt);
4521 /*check for tti_err*/
4522 if (val64 & TXDMA_TTI_INT) {
4523 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4525 &sw_stat->tti_err_cnt))
4527 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4529 &sw_stat->tti_err_cnt);
4532 /*check for lso_err*/
4533 if (val64 & TXDMA_LSO_INT) {
4534 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4535 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4537 &sw_stat->lso_err_cnt))
4539 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4541 &sw_stat->lso_err_cnt);
4544 /*check for tpa_err*/
4545 if (val64 & TXDMA_TPA_INT) {
4546 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4548 &sw_stat->tpa_err_cnt))
4550 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4552 &sw_stat->tpa_err_cnt);
4555 /*check for sm_err*/
4556 if (val64 & TXDMA_SM_INT) {
4557 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4559 &sw_stat->sm_err_cnt))
4563 val64 = readq(&bar0->mac_int_status);
4564 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4565 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4566 &bar0->mac_tmac_err_reg,
4567 &sw_stat->mac_tmac_err_cnt))
4569 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4570 TMAC_DESC_ECC_SG_ERR |
4571 TMAC_DESC_ECC_DB_ERR,
4572 &bar0->mac_tmac_err_reg,
4573 &sw_stat->mac_tmac_err_cnt);
4576 val64 = readq(&bar0->xgxs_int_status);
4577 if (val64 & XGXS_INT_STATUS_TXGXS) {
4578 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4579 &bar0->xgxs_txgxs_err_reg,
4580 &sw_stat->xgxs_txgxs_err_cnt))
4582 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4583 &bar0->xgxs_txgxs_err_reg,
4584 &sw_stat->xgxs_txgxs_err_cnt);
4587 val64 = readq(&bar0->rxdma_int_status);
4588 if (val64 & RXDMA_INT_RC_INT_M) {
4589 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4591 RC_PRCn_SM_ERR_ALARM |
4592 RC_FTC_SM_ERR_ALARM,
4594 &sw_stat->rc_err_cnt))
4596 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4598 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4599 &sw_stat->rc_err_cnt);
4600 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4603 &bar0->prc_pcix_err_reg,
4604 &sw_stat->prc_pcix_err_cnt))
4606 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4609 &bar0->prc_pcix_err_reg,
4610 &sw_stat->prc_pcix_err_cnt);
4613 if (val64 & RXDMA_INT_RPA_INT_M) {
4614 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4616 &sw_stat->rpa_err_cnt))
4618 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4620 &sw_stat->rpa_err_cnt);
4623 if (val64 & RXDMA_INT_RDA_INT_M) {
4624 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4625 RDA_FRM_ECC_DB_N_AERR |
4628 RDA_RXD_ECC_DB_SERR,
4630 &sw_stat->rda_err_cnt))
4632 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4633 RDA_FRM_ECC_SG_ERR |
4637 &sw_stat->rda_err_cnt);
4640 if (val64 & RXDMA_INT_RTI_INT_M) {
4641 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4643 &sw_stat->rti_err_cnt))
4645 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4647 &sw_stat->rti_err_cnt);
4650 val64 = readq(&bar0->mac_int_status);
4651 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4652 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4653 &bar0->mac_rmac_err_reg,
4654 &sw_stat->mac_rmac_err_cnt))
4656 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4657 RMAC_SINGLE_ECC_ERR |
4658 RMAC_DOUBLE_ECC_ERR,
4659 &bar0->mac_rmac_err_reg,
4660 &sw_stat->mac_rmac_err_cnt);
4663 val64 = readq(&bar0->xgxs_int_status);
4664 if (val64 & XGXS_INT_STATUS_RXGXS) {
4665 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4666 &bar0->xgxs_rxgxs_err_reg,
4667 &sw_stat->xgxs_rxgxs_err_cnt))
4671 val64 = readq(&bar0->mc_int_status);
4672 if (val64 & MC_INT_STATUS_MC_INT) {
4673 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4675 &sw_stat->mc_err_cnt))
4678 /* Handling Ecc errors */
4679 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4680 writeq(val64, &bar0->mc_err_reg);
4681 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4682 sw_stat->double_ecc_errs++;
4683 if (sp->device_type != XFRAME_II_DEVICE) {
4685 * Reset XframeI only if critical error
4688 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4689 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4693 sw_stat->single_ecc_errs++;
4699 s2io_stop_all_tx_queue(sp);
4700 schedule_work(&sp->rst_timer_task);
4701 sw_stat->soft_reset_cnt++;
4705 * s2io_isr - ISR handler of the device .
4706 * @irq: the irq of the device.
4707 * @dev_id: a void pointer to the dev structure of the NIC.
4708 * Description: This function is the ISR handler of the device. It
4709 * identifies the reason for the interrupt and calls the relevant
4710 * service routines. As a contongency measure, this ISR allocates the
4711 * recv buffers, if their numbers are below the panic value which is
4712 * presently set to 25% of the original number of rcv buffers allocated.
4714 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
4715 * IRQ_NONE: will be returned if interrupt is not from our device
4717 static irqreturn_t s2io_isr(int irq, void *dev_id)
4719 struct net_device *dev = (struct net_device *)dev_id;
4720 struct s2io_nic *sp = netdev_priv(dev);
4721 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4724 struct mac_info *mac_control;
4725 struct config_param *config;
4727 /* Pretend we handled any irq's from a disconnected card */
4728 if (pci_channel_offline(sp->pdev))
4731 if (!is_s2io_card_up(sp))
4734 config = &sp->config;
4735 mac_control = &sp->mac_control;
4738 * Identify the cause for interrupt and call the appropriate
4739 * interrupt handler. Causes for the interrupt could be;
4744 reason = readq(&bar0->general_int_status);
4746 if (unlikely(reason == S2IO_MINUS_ONE))
4747 return IRQ_HANDLED; /* Nothing much can be done. Get out */
4750 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4751 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4754 if (reason & GEN_INTR_RXTRAFFIC) {
4755 napi_schedule(&sp->napi);
4756 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4757 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4758 readl(&bar0->rx_traffic_int);
4762 * rx_traffic_int reg is an R1 register, writing all 1's
4763 * will ensure that the actual interrupt causing bit
4764 * get's cleared and hence a read can be avoided.
4766 if (reason & GEN_INTR_RXTRAFFIC)
4767 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4769 for (i = 0; i < config->rx_ring_num; i++) {
4770 struct ring_info *ring = &mac_control->rings[i];
4772 rx_intr_handler(ring, 0);
4777 * tx_traffic_int reg is an R1 register, writing all 1's
4778 * will ensure that the actual interrupt causing bit get's
4779 * cleared and hence a read can be avoided.
4781 if (reason & GEN_INTR_TXTRAFFIC)
4782 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4784 for (i = 0; i < config->tx_fifo_num; i++)
4785 tx_intr_handler(&mac_control->fifos[i]);
4787 if (reason & GEN_INTR_TXPIC)
4788 s2io_txpic_intr_handle(sp);
4791 * Reallocate the buffers from the interrupt handler itself.
4793 if (!config->napi) {
4794 for (i = 0; i < config->rx_ring_num; i++) {
4795 struct ring_info *ring = &mac_control->rings[i];
4797 s2io_chk_rx_buffers(sp, ring);
4800 writeq(sp->general_int_mask, &bar0->general_int_mask);
4801 readl(&bar0->general_int_status);
4805 } else if (!reason) {
4806 /* The interrupt was not raised by us */
4816 static void s2io_updt_stats(struct s2io_nic *sp)
4818 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4822 if (is_s2io_card_up(sp)) {
4823 /* Apprx 30us on a 133 MHz bus */
4824 val64 = SET_UPDT_CLICKS(10) |
4825 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4826 writeq(val64, &bar0->stat_cfg);
4829 val64 = readq(&bar0->stat_cfg);
4830 if (!(val64 & s2BIT(0)))
4834 break; /* Updt failed */
4840 * s2io_get_stats - Updates the device statistics structure.
4841 * @dev : pointer to the device structure.
4843 * This function updates the device statistics structure in the s2io_nic
4844 * structure and returns a pointer to the same.
4846 * pointer to the updated net_device_stats structure.
4848 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4850 struct s2io_nic *sp = netdev_priv(dev);
4851 struct mac_info *mac_control = &sp->mac_control;
4852 struct stat_block *stats = mac_control->stats_info;
4855 /* Configure Stats for immediate updt */
4856 s2io_updt_stats(sp);
4858 /* A device reset will cause the on-adapter statistics to be zero'ed.
4859 * This can be done while running by changing the MTU. To prevent the
4860 * system from having the stats zero'ed, the driver keeps a copy of the
4861 * last update to the system (which is also zero'ed on reset). This
4862 * enables the driver to accurately know the delta between the last
4863 * update and the current update.
4865 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4866 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4867 sp->stats.rx_packets += delta;
4868 dev->stats.rx_packets += delta;
4870 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4871 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4872 sp->stats.tx_packets += delta;
4873 dev->stats.tx_packets += delta;
4875 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4876 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4877 sp->stats.rx_bytes += delta;
4878 dev->stats.rx_bytes += delta;
4880 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4881 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4882 sp->stats.tx_bytes += delta;
4883 dev->stats.tx_bytes += delta;
4885 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4886 sp->stats.rx_errors += delta;
4887 dev->stats.rx_errors += delta;
4889 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4890 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4891 sp->stats.tx_errors += delta;
4892 dev->stats.tx_errors += delta;
4894 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4895 sp->stats.rx_dropped += delta;
4896 dev->stats.rx_dropped += delta;
4898 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4899 sp->stats.tx_dropped += delta;
4900 dev->stats.tx_dropped += delta;
4902 /* The adapter MAC interprets pause frames as multicast packets, but
4903 * does not pass them up. This erroneously increases the multicast
4904 * packet count and needs to be deducted when the multicast frame count
4907 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4908 le32_to_cpu(stats->rmac_vld_mcst_frms);
4909 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4910 delta -= sp->stats.multicast;
4911 sp->stats.multicast += delta;
4912 dev->stats.multicast += delta;
4914 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4915 le32_to_cpu(stats->rmac_usized_frms)) +
4916 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4917 sp->stats.rx_length_errors += delta;
4918 dev->stats.rx_length_errors += delta;
4920 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4921 sp->stats.rx_crc_errors += delta;
4922 dev->stats.rx_crc_errors += delta;
4928 * s2io_set_multicast - entry point for multicast address enable/disable.
4929 * @dev : pointer to the device structure
4931 * This function is a driver entry point which gets called by the kernel
4932 * whenever multicast addresses must be enabled/disabled. This also gets
4933 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4934 * determine, if multicast address must be enabled or if promiscuous mode
4935 * is to be disabled etc.
4940 static void s2io_set_multicast(struct net_device *dev)
4943 struct netdev_hw_addr *ha;
4944 struct s2io_nic *sp = netdev_priv(dev);
4945 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4946 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4948 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4950 struct config_param *config = &sp->config;
4952 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4953 /* Enable all Multicast addresses */
4954 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4955 &bar0->rmac_addr_data0_mem);
4956 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4957 &bar0->rmac_addr_data1_mem);
4958 val64 = RMAC_ADDR_CMD_MEM_WE |
4959 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4960 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4961 writeq(val64, &bar0->rmac_addr_cmd_mem);
4962 /* Wait till command completes */
4963 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4964 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4968 sp->all_multi_pos = config->max_mc_addr - 1;
4969 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4970 /* Disable all Multicast addresses */
4971 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4972 &bar0->rmac_addr_data0_mem);
4973 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4974 &bar0->rmac_addr_data1_mem);
4975 val64 = RMAC_ADDR_CMD_MEM_WE |
4976 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4977 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4978 writeq(val64, &bar0->rmac_addr_cmd_mem);
4979 /* Wait till command completes */
4980 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4981 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4985 sp->all_multi_pos = 0;
4988 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4989 /* Put the NIC into promiscuous mode */
4990 add = &bar0->mac_cfg;
4991 val64 = readq(&bar0->mac_cfg);
4992 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4994 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4995 writel((u32)val64, add);
4996 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4997 writel((u32) (val64 >> 32), (add + 4));
4999 if (vlan_tag_strip != 1) {
5000 val64 = readq(&bar0->rx_pa_cfg);
5001 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5002 writeq(val64, &bar0->rx_pa_cfg);
5003 sp->vlan_strip_flag = 0;
5006 val64 = readq(&bar0->mac_cfg);
5007 sp->promisc_flg = 1;
5008 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
5010 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5011 /* Remove the NIC from promiscuous mode */
5012 add = &bar0->mac_cfg;
5013 val64 = readq(&bar0->mac_cfg);
5014 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5016 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5017 writel((u32)val64, add);
5018 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5019 writel((u32) (val64 >> 32), (add + 4));
5021 if (vlan_tag_strip != 0) {
5022 val64 = readq(&bar0->rx_pa_cfg);
5023 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5024 writeq(val64, &bar0->rx_pa_cfg);
5025 sp->vlan_strip_flag = 1;
5028 val64 = readq(&bar0->mac_cfg);
5029 sp->promisc_flg = 0;
5030 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5033 /* Update individual M_CAST address list */
5034 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5035 if (netdev_mc_count(dev) >
5036 (config->max_mc_addr - config->max_mac_addr)) {
5038 "%s: No more Rx filters can be added - "
5039 "please enable ALL_MULTI instead\n",
5044 prev_cnt = sp->mc_addr_count;
5045 sp->mc_addr_count = netdev_mc_count(dev);
5047 /* Clear out the previous list of Mc in the H/W. */
5048 for (i = 0; i < prev_cnt; i++) {
5049 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5050 &bar0->rmac_addr_data0_mem);
5051 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5052 &bar0->rmac_addr_data1_mem);
5053 val64 = RMAC_ADDR_CMD_MEM_WE |
5054 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5055 RMAC_ADDR_CMD_MEM_OFFSET
5056 (config->mc_start_offset + i);
5057 writeq(val64, &bar0->rmac_addr_cmd_mem);
5059 /* Wait for command completes */
5060 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5061 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5064 "%s: Adding Multicasts failed\n",
5070 /* Create the new Rx filter list and update the same in H/W. */
5072 netdev_for_each_mc_addr(ha, dev) {
5074 for (j = 0; j < ETH_ALEN; j++) {
5075 mac_addr |= ha->addr[j];
5079 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5080 &bar0->rmac_addr_data0_mem);
5081 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5082 &bar0->rmac_addr_data1_mem);
5083 val64 = RMAC_ADDR_CMD_MEM_WE |
5084 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5085 RMAC_ADDR_CMD_MEM_OFFSET
5086 (i + config->mc_start_offset);
5087 writeq(val64, &bar0->rmac_addr_cmd_mem);
5089 /* Wait for command completes */
5090 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5091 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5094 "%s: Adding Multicasts failed\n",
5103 /* read from CAM unicast & multicast addresses and store it in
5104 * def_mac_addr structure
5106 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5110 struct config_param *config = &sp->config;
5112 /* store unicast & multicast mac addresses */
5113 for (offset = 0; offset < config->max_mc_addr; offset++) {
5114 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5115 /* if read fails disable the entry */
5116 if (mac_addr == FAILURE)
5117 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5118 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5122 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5123 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5126 struct config_param *config = &sp->config;
5127 /* restore unicast mac address */
5128 for (offset = 0; offset < config->max_mac_addr; offset++)
5129 do_s2io_prog_unicast(sp->dev,
5130 sp->def_mac_addr[offset].mac_addr);
5132 /* restore multicast mac address */
5133 for (offset = config->mc_start_offset;
5134 offset < config->max_mc_addr; offset++)
5135 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5138 /* add a multicast MAC address to CAM */
5139 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5143 struct config_param *config = &sp->config;
5145 for (i = 0; i < ETH_ALEN; i++) {
5147 mac_addr |= addr[i];
5149 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5152 /* check if the multicast mac already preset in CAM */
5153 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5155 tmp64 = do_s2io_read_unicast_mc(sp, i);
5156 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5159 if (tmp64 == mac_addr)
5162 if (i == config->max_mc_addr) {
5164 "CAM full no space left for multicast MAC\n");
5167 /* Update the internal structure with this new mac address */
5168 do_s2io_copy_mac_addr(sp, i, mac_addr);
5170 return do_s2io_add_mac(sp, mac_addr, i);
5173 /* add MAC address to CAM */
5174 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5177 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5179 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5180 &bar0->rmac_addr_data0_mem);
5182 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5183 RMAC_ADDR_CMD_MEM_OFFSET(off);
5184 writeq(val64, &bar0->rmac_addr_cmd_mem);
5186 /* Wait till command completes */
5187 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5188 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5190 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5195 /* deletes a specified unicast/multicast mac entry from CAM */
5196 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5199 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5200 struct config_param *config = &sp->config;
5203 offset < config->max_mc_addr; offset++) {
5204 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5205 if (tmp64 == addr) {
5206 /* disable the entry by writing 0xffffffffffffULL */
5207 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5209 /* store the new mac list from CAM */
5210 do_s2io_store_unicast_mc(sp);
5214 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5215 (unsigned long long)addr);
5219 /* read mac entries from CAM */
5220 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5222 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5223 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5226 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5227 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5228 writeq(val64, &bar0->rmac_addr_cmd_mem);
5230 /* Wait till command completes */
5231 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5232 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5234 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5237 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5243 * s2io_set_mac_addr driver entry point
5246 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5248 struct sockaddr *addr = p;
5250 if (!is_valid_ether_addr(addr->sa_data))
5253 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5255 /* store the MAC address in CAM */
5256 return do_s2io_prog_unicast(dev, dev->dev_addr);
5259 * do_s2io_prog_unicast - Programs the Xframe mac address
5260 * @dev : pointer to the device structure.
5261 * @addr: a uchar pointer to the new mac address which is to be set.
5262 * Description : This procedure will program the Xframe to receive
5263 * frames with new Mac Address
5264 * Return value: SUCCESS on success and an appropriate (-)ve integer
5265 * as defined in errno.h file on failure.
5268 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5270 struct s2io_nic *sp = netdev_priv(dev);
5271 register u64 mac_addr = 0, perm_addr = 0;
5274 struct config_param *config = &sp->config;
5277 * Set the new MAC address as the new unicast filter and reflect this
5278 * change on the device address registered with the OS. It will be
5281 for (i = 0; i < ETH_ALEN; i++) {
5283 mac_addr |= addr[i];
5285 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5288 /* check if the dev_addr is different than perm_addr */
5289 if (mac_addr == perm_addr)
5292 /* check if the mac already preset in CAM */
5293 for (i = 1; i < config->max_mac_addr; i++) {
5294 tmp64 = do_s2io_read_unicast_mc(sp, i);
5295 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5298 if (tmp64 == mac_addr) {
5300 "MAC addr:0x%llx already present in CAM\n",
5301 (unsigned long long)mac_addr);
5305 if (i == config->max_mac_addr) {
5306 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5309 /* Update the internal structure with this new mac address */
5310 do_s2io_copy_mac_addr(sp, i, mac_addr);
5312 return do_s2io_add_mac(sp, mac_addr, i);
5316 * s2io_ethtool_sset - Sets different link parameters.
5317 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5318 * @info: pointer to the structure with parameters given by ethtool to set
5321 * The function sets different link parameters provided by the user onto
5327 static int s2io_ethtool_sset(struct net_device *dev,
5328 struct ethtool_cmd *info)
5330 struct s2io_nic *sp = netdev_priv(dev);
5331 if ((info->autoneg == AUTONEG_ENABLE) ||
5332 (ethtool_cmd_speed(info) != SPEED_10000) ||
5333 (info->duplex != DUPLEX_FULL))
5336 s2io_close(sp->dev);
5344 * s2io_ethtol_gset - Return link specific information.
5345 * @sp : private member of the device structure, pointer to the
5346 * s2io_nic structure.
5347 * @info : pointer to the structure with parameters given by ethtool
5348 * to return link information.
5350 * Returns link specific information like speed, duplex etc.. to ethtool.
5352 * return 0 on success.
5355 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5357 struct s2io_nic *sp = netdev_priv(dev);
5358 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5359 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5360 info->port = PORT_FIBRE;
5362 /* info->transceiver */
5363 info->transceiver = XCVR_EXTERNAL;
5365 if (netif_carrier_ok(sp->dev)) {
5366 ethtool_cmd_speed_set(info, SPEED_10000);
5367 info->duplex = DUPLEX_FULL;
5369 ethtool_cmd_speed_set(info, -1);
5373 info->autoneg = AUTONEG_DISABLE;
5378 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5379 * @sp : private member of the device structure, which is a pointer to the
5380 * s2io_nic structure.
5381 * @info : pointer to the structure with parameters given by ethtool to
5382 * return driver information.
5384 * Returns driver specefic information like name, version etc.. to ethtool.
5389 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5390 struct ethtool_drvinfo *info)
5392 struct s2io_nic *sp = netdev_priv(dev);
5394 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5395 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5396 strncpy(info->fw_version, "", sizeof(info->fw_version));
5397 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5398 info->regdump_len = XENA_REG_SPACE;
5399 info->eedump_len = XENA_EEPROM_SPACE;
5403 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5404 * @sp: private member of the device structure, which is a pointer to the
5405 * s2io_nic structure.
5406 * @regs : pointer to the structure with parameters given by ethtool for
5407 * dumping the registers.
5408 * @reg_space: The input argumnet into which all the registers are dumped.
5410 * Dumps the entire register space of xFrame NIC into the user given
5416 static void s2io_ethtool_gregs(struct net_device *dev,
5417 struct ethtool_regs *regs, void *space)
5421 u8 *reg_space = (u8 *)space;
5422 struct s2io_nic *sp = netdev_priv(dev);
5424 regs->len = XENA_REG_SPACE;
5425 regs->version = sp->pdev->subsystem_device;
5427 for (i = 0; i < regs->len; i += 8) {
5428 reg = readq(sp->bar0 + i);
5429 memcpy((reg_space + i), ®, 8);
5434 * s2io_set_led - control NIC led
5436 static void s2io_set_led(struct s2io_nic *sp, bool on)
5438 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5439 u16 subid = sp->pdev->subsystem_device;
5442 if ((sp->device_type == XFRAME_II_DEVICE) ||
5443 ((subid & 0xFF) >= 0x07)) {
5444 val64 = readq(&bar0->gpio_control);
5446 val64 |= GPIO_CTRL_GPIO_0;
5448 val64 &= ~GPIO_CTRL_GPIO_0;
5450 writeq(val64, &bar0->gpio_control);
5452 val64 = readq(&bar0->adapter_control);
5454 val64 |= ADAPTER_LED_ON;
5456 val64 &= ~ADAPTER_LED_ON;
5458 writeq(val64, &bar0->adapter_control);
5464 * s2io_ethtool_set_led - To physically identify the nic on the system.
5465 * @dev : network device
5466 * @state: led setting
5468 * Description: Used to physically identify the NIC on the system.
5469 * The Link LED will blink for a time specified by the user for
5471 * NOTE: The Link has to be Up to be able to blink the LED. Hence
5472 * identification is possible only if it's link is up.
5475 static int s2io_ethtool_set_led(struct net_device *dev,
5476 enum ethtool_phys_id_state state)
5478 struct s2io_nic *sp = netdev_priv(dev);
5479 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5480 u16 subid = sp->pdev->subsystem_device;
5482 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5483 u64 val64 = readq(&bar0->adapter_control);
5484 if (!(val64 & ADAPTER_CNTL_EN)) {
5485 pr_err("Adapter Link down, cannot blink LED\n");
5491 case ETHTOOL_ID_ACTIVE:
5492 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5493 return 1; /* cycle on/off once per second */
5496 s2io_set_led(sp, true);
5499 case ETHTOOL_ID_OFF:
5500 s2io_set_led(sp, false);
5503 case ETHTOOL_ID_INACTIVE:
5504 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5505 writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5511 static void s2io_ethtool_gringparam(struct net_device *dev,
5512 struct ethtool_ringparam *ering)
5514 struct s2io_nic *sp = netdev_priv(dev);
5515 int i, tx_desc_count = 0, rx_desc_count = 0;
5517 if (sp->rxd_mode == RXD_MODE_1) {
5518 ering->rx_max_pending = MAX_RX_DESC_1;
5519 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5521 ering->rx_max_pending = MAX_RX_DESC_2;
5522 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5525 ering->rx_mini_max_pending = 0;
5526 ering->tx_max_pending = MAX_TX_DESC;
5528 for (i = 0; i < sp->config.rx_ring_num; i++)
5529 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5530 ering->rx_pending = rx_desc_count;
5531 ering->rx_jumbo_pending = rx_desc_count;
5532 ering->rx_mini_pending = 0;
5534 for (i = 0; i < sp->config.tx_fifo_num; i++)
5535 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5536 ering->tx_pending = tx_desc_count;
5537 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5541 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5542 * @sp : private member of the device structure, which is a pointer to the
5543 * s2io_nic structure.
5544 * @ep : pointer to the structure with pause parameters given by ethtool.
5546 * Returns the Pause frame generation and reception capability of the NIC.
5550 static void s2io_ethtool_getpause_data(struct net_device *dev,
5551 struct ethtool_pauseparam *ep)
5554 struct s2io_nic *sp = netdev_priv(dev);
5555 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5557 val64 = readq(&bar0->rmac_pause_cfg);
5558 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5559 ep->tx_pause = true;
5560 if (val64 & RMAC_PAUSE_RX_ENABLE)
5561 ep->rx_pause = true;
5562 ep->autoneg = false;
5566 * s2io_ethtool_setpause_data - set/reset pause frame generation.
5567 * @sp : private member of the device structure, which is a pointer to the
5568 * s2io_nic structure.
5569 * @ep : pointer to the structure with pause parameters given by ethtool.
5571 * It can be used to set or reset Pause frame generation or reception
5572 * support of the NIC.
5574 * int, returns 0 on Success
5577 static int s2io_ethtool_setpause_data(struct net_device *dev,
5578 struct ethtool_pauseparam *ep)
5581 struct s2io_nic *sp = netdev_priv(dev);
5582 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5584 val64 = readq(&bar0->rmac_pause_cfg);
5586 val64 |= RMAC_PAUSE_GEN_ENABLE;
5588 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5590 val64 |= RMAC_PAUSE_RX_ENABLE;
5592 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5593 writeq(val64, &bar0->rmac_pause_cfg);
5598 * read_eeprom - reads 4 bytes of data from user given offset.
5599 * @sp : private member of the device structure, which is a pointer to the
5600 * s2io_nic structure.
5601 * @off : offset at which the data must be written
5602 * @data : Its an output parameter where the data read at the given
5605 * Will read 4 bytes of data from the user given offset and return the
5607 * NOTE: Will allow to read only part of the EEPROM visible through the
5610 * -1 on failure and 0 on success.
5613 #define S2IO_DEV_ID 5
5614 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5619 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5621 if (sp->device_type == XFRAME_I_DEVICE) {
5622 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5623 I2C_CONTROL_ADDR(off) |
5624 I2C_CONTROL_BYTE_CNT(0x3) |
5626 I2C_CONTROL_CNTL_START;
5627 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5629 while (exit_cnt < 5) {
5630 val64 = readq(&bar0->i2c_control);
5631 if (I2C_CONTROL_CNTL_END(val64)) {
5632 *data = I2C_CONTROL_GET_DATA(val64);
5641 if (sp->device_type == XFRAME_II_DEVICE) {
5642 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5643 SPI_CONTROL_BYTECNT(0x3) |
5644 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5645 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5646 val64 |= SPI_CONTROL_REQ;
5647 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5648 while (exit_cnt < 5) {
5649 val64 = readq(&bar0->spi_control);
5650 if (val64 & SPI_CONTROL_NACK) {
5653 } else if (val64 & SPI_CONTROL_DONE) {
5654 *data = readq(&bar0->spi_data);
5667 * write_eeprom - actually writes the relevant part of the data value.
5668 * @sp : private member of the device structure, which is a pointer to the
5669 * s2io_nic structure.
5670 * @off : offset at which the data must be written
5671 * @data : The data that is to be written
5672 * @cnt : Number of bytes of the data that are actually to be written into
5673 * the Eeprom. (max of 3)
5675 * Actually writes the relevant part of the data value into the Eeprom
5676 * through the I2C bus.
5678 * 0 on success, -1 on failure.
5681 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5683 int exit_cnt = 0, ret = -1;
5685 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5687 if (sp->device_type == XFRAME_I_DEVICE) {
5688 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5689 I2C_CONTROL_ADDR(off) |
5690 I2C_CONTROL_BYTE_CNT(cnt) |
5691 I2C_CONTROL_SET_DATA((u32)data) |
5692 I2C_CONTROL_CNTL_START;
5693 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5695 while (exit_cnt < 5) {
5696 val64 = readq(&bar0->i2c_control);
5697 if (I2C_CONTROL_CNTL_END(val64)) {
5698 if (!(val64 & I2C_CONTROL_NACK))
5707 if (sp->device_type == XFRAME_II_DEVICE) {
5708 int write_cnt = (cnt == 8) ? 0 : cnt;
5709 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5711 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5712 SPI_CONTROL_BYTECNT(write_cnt) |
5713 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5714 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5715 val64 |= SPI_CONTROL_REQ;
5716 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5717 while (exit_cnt < 5) {
5718 val64 = readq(&bar0->spi_control);
5719 if (val64 & SPI_CONTROL_NACK) {
5722 } else if (val64 & SPI_CONTROL_DONE) {
5732 static void s2io_vpd_read(struct s2io_nic *nic)
5736 int i = 0, cnt, len, fail = 0;
5737 int vpd_addr = 0x80;
5738 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5740 if (nic->device_type == XFRAME_II_DEVICE) {
5741 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5744 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5747 strcpy(nic->serial_num, "NOT AVAILABLE");
5749 vpd_data = kmalloc(256, GFP_KERNEL);
5751 swstats->mem_alloc_fail_cnt++;
5754 swstats->mem_allocated += 256;
5756 for (i = 0; i < 256; i += 4) {
5757 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5758 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5759 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5760 for (cnt = 0; cnt < 5; cnt++) {
5762 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5767 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5771 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5772 (u32 *)&vpd_data[i]);
5776 /* read serial number of adapter */
5777 for (cnt = 0; cnt < 252; cnt++) {
5778 if ((vpd_data[cnt] == 'S') &&
5779 (vpd_data[cnt+1] == 'N')) {
5780 len = vpd_data[cnt+2];
5781 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5782 memcpy(nic->serial_num,
5785 memset(nic->serial_num+len,
5787 VPD_STRING_LEN-len);
5794 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5796 memcpy(nic->product_name, &vpd_data[3], len);
5797 nic->product_name[len] = 0;
5800 swstats->mem_freed += 256;
5804 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5805 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5806 * @eeprom : pointer to the user level structure provided by ethtool,
5807 * containing all relevant information.
5808 * @data_buf : user defined value to be written into Eeprom.
5809 * Description: Reads the values stored in the Eeprom at given offset
5810 * for a given length. Stores these values int the input argument data
5811 * buffer 'data_buf' and returns these to the caller (ethtool.)
5816 static int s2io_ethtool_geeprom(struct net_device *dev,
5817 struct ethtool_eeprom *eeprom, u8 * data_buf)
5821 struct s2io_nic *sp = netdev_priv(dev);
5823 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5825 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5826 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5828 for (i = 0; i < eeprom->len; i += 4) {
5829 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5830 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5834 memcpy((data_buf + i), &valid, 4);
5840 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5841 * @sp : private member of the device structure, which is a pointer to the
5842 * s2io_nic structure.
5843 * @eeprom : pointer to the user level structure provided by ethtool,
5844 * containing all relevant information.
5845 * @data_buf ; user defined value to be written into Eeprom.
5847 * Tries to write the user provided value in the Eeprom, at the offset
5848 * given by the user.
5850 * 0 on success, -EFAULT on failure.
5853 static int s2io_ethtool_seeprom(struct net_device *dev,
5854 struct ethtool_eeprom *eeprom,
5857 int len = eeprom->len, cnt = 0;
5858 u64 valid = 0, data;
5859 struct s2io_nic *sp = netdev_priv(dev);
5861 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5863 "ETHTOOL_WRITE_EEPROM Err: "
5864 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5865 (sp->pdev->vendor | (sp->pdev->device << 16)),
5871 data = (u32)data_buf[cnt] & 0x000000FF;
5873 valid = (u32)(data << 24);
5877 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5879 "ETHTOOL_WRITE_EEPROM Err: "
5880 "Cannot write into the specified offset\n");
5891 * s2io_register_test - reads and writes into all clock domains.
5892 * @sp : private member of the device structure, which is a pointer to the
5893 * s2io_nic structure.
5894 * @data : variable that returns the result of each of the test conducted b
5897 * Read and write into all clock domains. The NIC has 3 clock domains,
5898 * see that registers in all the three regions are accessible.
5903 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5905 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5906 u64 val64 = 0, exp_val;
5909 val64 = readq(&bar0->pif_rd_swapper_fb);
5910 if (val64 != 0x123456789abcdefULL) {
5912 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5915 val64 = readq(&bar0->rmac_pause_cfg);
5916 if (val64 != 0xc000ffff00000000ULL) {
5918 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5921 val64 = readq(&bar0->rx_queue_cfg);
5922 if (sp->device_type == XFRAME_II_DEVICE)
5923 exp_val = 0x0404040404040404ULL;
5925 exp_val = 0x0808080808080808ULL;
5926 if (val64 != exp_val) {
5928 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5931 val64 = readq(&bar0->xgxs_efifo_cfg);
5932 if (val64 != 0x000000001923141EULL) {
5934 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5937 val64 = 0x5A5A5A5A5A5A5A5AULL;
5938 writeq(val64, &bar0->xmsi_data);
5939 val64 = readq(&bar0->xmsi_data);
5940 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5942 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5945 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5946 writeq(val64, &bar0->xmsi_data);
5947 val64 = readq(&bar0->xmsi_data);
5948 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5950 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5958 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5959 * @sp : private member of the device structure, which is a pointer to the
5960 * s2io_nic structure.
5961 * @data:variable that returns the result of each of the test conducted by
5964 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5970 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5973 u64 ret_data, org_4F0, org_7F0;
5974 u8 saved_4F0 = 0, saved_7F0 = 0;
5975 struct net_device *dev = sp->dev;
5977 /* Test Write Error at offset 0 */
5978 /* Note that SPI interface allows write access to all areas
5979 * of EEPROM. Hence doing all negative testing only for Xframe I.
5981 if (sp->device_type == XFRAME_I_DEVICE)
5982 if (!write_eeprom(sp, 0, 0, 3))
5985 /* Save current values at offsets 0x4F0 and 0x7F0 */
5986 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5988 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5991 /* Test Write at offset 4f0 */
5992 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5994 if (read_eeprom(sp, 0x4F0, &ret_data))
5997 if (ret_data != 0x012345) {
5998 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5999 "Data written %llx Data read %llx\n",
6000 dev->name, (unsigned long long)0x12345,
6001 (unsigned long long)ret_data);
6005 /* Reset the EEPROM data go FFFF */
6006 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
6008 /* Test Write Request Error at offset 0x7c */
6009 if (sp->device_type == XFRAME_I_DEVICE)
6010 if (!write_eeprom(sp, 0x07C, 0, 3))
6013 /* Test Write Request at offset 0x7f0 */
6014 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
6016 if (read_eeprom(sp, 0x7F0, &ret_data))
6019 if (ret_data != 0x012345) {
6020 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6021 "Data written %llx Data read %llx\n",
6022 dev->name, (unsigned long long)0x12345,
6023 (unsigned long long)ret_data);
6027 /* Reset the EEPROM data go FFFF */
6028 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6030 if (sp->device_type == XFRAME_I_DEVICE) {
6031 /* Test Write Error at offset 0x80 */
6032 if (!write_eeprom(sp, 0x080, 0, 3))
6035 /* Test Write Error at offset 0xfc */
6036 if (!write_eeprom(sp, 0x0FC, 0, 3))
6039 /* Test Write Error at offset 0x100 */
6040 if (!write_eeprom(sp, 0x100, 0, 3))
6043 /* Test Write Error at offset 4ec */
6044 if (!write_eeprom(sp, 0x4EC, 0, 3))
6048 /* Restore values at offsets 0x4F0 and 0x7F0 */
6050 write_eeprom(sp, 0x4F0, org_4F0, 3);
6052 write_eeprom(sp, 0x7F0, org_7F0, 3);
6059 * s2io_bist_test - invokes the MemBist test of the card .
6060 * @sp : private member of the device structure, which is a pointer to the
6061 * s2io_nic structure.
6062 * @data:variable that returns the result of each of the test conducted by
6065 * This invokes the MemBist test of the card. We give around
6066 * 2 secs time for the Test to complete. If it's still not complete
6067 * within this peiod, we consider that the test failed.
6069 * 0 on success and -1 on failure.
6072 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6075 int cnt = 0, ret = -1;
6077 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6078 bist |= PCI_BIST_START;
6079 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6082 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6083 if (!(bist & PCI_BIST_START)) {
6084 *data = (bist & PCI_BIST_CODE_MASK);
6096 * s2io-link_test - verifies the link state of the nic
6097 * @sp ; private member of the device structure, which is a pointer to the
6098 * s2io_nic structure.
6099 * @data: variable that returns the result of each of the test conducted by
6102 * The function verifies the link state of the NIC and updates the input
6103 * argument 'data' appropriately.
6108 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6110 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6113 val64 = readq(&bar0->adapter_status);
6114 if (!(LINK_IS_UP(val64)))
6123 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6124 * @sp - private member of the device structure, which is a pointer to the
6125 * s2io_nic structure.
6126 * @data - variable that returns the result of each of the test
6127 * conducted by the driver.
6129 * This is one of the offline test that tests the read and write
6130 * access to the RldRam chip on the NIC.
6135 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6137 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6139 int cnt, iteration = 0, test_fail = 0;
6141 val64 = readq(&bar0->adapter_control);
6142 val64 &= ~ADAPTER_ECC_EN;
6143 writeq(val64, &bar0->adapter_control);
6145 val64 = readq(&bar0->mc_rldram_test_ctrl);
6146 val64 |= MC_RLDRAM_TEST_MODE;
6147 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6149 val64 = readq(&bar0->mc_rldram_mrs);
6150 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6151 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6153 val64 |= MC_RLDRAM_MRS_ENABLE;
6154 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6156 while (iteration < 2) {
6157 val64 = 0x55555555aaaa0000ULL;
6159 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6160 writeq(val64, &bar0->mc_rldram_test_d0);
6162 val64 = 0xaaaa5a5555550000ULL;
6164 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6165 writeq(val64, &bar0->mc_rldram_test_d1);
6167 val64 = 0x55aaaaaaaa5a0000ULL;
6169 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6170 writeq(val64, &bar0->mc_rldram_test_d2);
6172 val64 = (u64) (0x0000003ffffe0100ULL);
6173 writeq(val64, &bar0->mc_rldram_test_add);
6175 val64 = MC_RLDRAM_TEST_MODE |
6176 MC_RLDRAM_TEST_WRITE |
6178 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6180 for (cnt = 0; cnt < 5; cnt++) {
6181 val64 = readq(&bar0->mc_rldram_test_ctrl);
6182 if (val64 & MC_RLDRAM_TEST_DONE)
6190 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6191 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6193 for (cnt = 0; cnt < 5; cnt++) {
6194 val64 = readq(&bar0->mc_rldram_test_ctrl);
6195 if (val64 & MC_RLDRAM_TEST_DONE)
6203 val64 = readq(&bar0->mc_rldram_test_ctrl);
6204 if (!(val64 & MC_RLDRAM_TEST_PASS))
6212 /* Bring the adapter out of test mode */
6213 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6219 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6220 * @sp : private member of the device structure, which is a pointer to the
6221 * s2io_nic structure.
6222 * @ethtest : pointer to a ethtool command specific structure that will be
6223 * returned to the user.
6224 * @data : variable that returns the result of each of the test
6225 * conducted by the driver.
6227 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6228 * the health of the card.
6233 static void s2io_ethtool_test(struct net_device *dev,
6234 struct ethtool_test *ethtest,
6237 struct s2io_nic *sp = netdev_priv(dev);
6238 int orig_state = netif_running(sp->dev);
6240 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6241 /* Offline Tests. */
6243 s2io_close(sp->dev);
6245 if (s2io_register_test(sp, &data[0]))
6246 ethtest->flags |= ETH_TEST_FL_FAILED;
6250 if (s2io_rldram_test(sp, &data[3]))
6251 ethtest->flags |= ETH_TEST_FL_FAILED;
6255 if (s2io_eeprom_test(sp, &data[1]))
6256 ethtest->flags |= ETH_TEST_FL_FAILED;
6258 if (s2io_bist_test(sp, &data[4]))
6259 ethtest->flags |= ETH_TEST_FL_FAILED;
6268 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6277 if (s2io_link_test(sp, &data[2]))
6278 ethtest->flags |= ETH_TEST_FL_FAILED;
6287 static void s2io_get_ethtool_stats(struct net_device *dev,
6288 struct ethtool_stats *estats,
6292 struct s2io_nic *sp = netdev_priv(dev);
6293 struct stat_block *stats = sp->mac_control.stats_info;
6294 struct swStat *swstats = &stats->sw_stat;
6295 struct xpakStat *xstats = &stats->xpak_stat;
6297 s2io_updt_stats(sp);
6299 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6300 le32_to_cpu(stats->tmac_frms);
6302 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6303 le32_to_cpu(stats->tmac_data_octets);
6304 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6306 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6307 le32_to_cpu(stats->tmac_mcst_frms);
6309 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6310 le32_to_cpu(stats->tmac_bcst_frms);
6311 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6313 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6314 le32_to_cpu(stats->tmac_ttl_octets);
6316 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6317 le32_to_cpu(stats->tmac_ucst_frms);
6319 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6320 le32_to_cpu(stats->tmac_nucst_frms);
6322 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6323 le32_to_cpu(stats->tmac_any_err_frms);
6324 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6325 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6327 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6328 le32_to_cpu(stats->tmac_vld_ip);
6330 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6331 le32_to_cpu(stats->tmac_drop_ip);
6333 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6334 le32_to_cpu(stats->tmac_icmp);
6336 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6337 le32_to_cpu(stats->tmac_rst_tcp);
6338 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6339 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6340 le32_to_cpu(stats->tmac_udp);
6342 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6343 le32_to_cpu(stats->rmac_vld_frms);
6345 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6346 le32_to_cpu(stats->rmac_data_octets);
6347 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6348 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6350 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6351 le32_to_cpu(stats->rmac_vld_mcst_frms);
6353 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6354 le32_to_cpu(stats->rmac_vld_bcst_frms);
6355 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6356 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6357 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6358 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6359 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6361 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6362 le32_to_cpu(stats->rmac_ttl_octets);
6364 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6365 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6367 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6368 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6370 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6371 le32_to_cpu(stats->rmac_discarded_frms);
6373 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6374 << 32 | le32_to_cpu(stats->rmac_drop_events);
6375 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6376 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6378 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6379 le32_to_cpu(stats->rmac_usized_frms);
6381 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6382 le32_to_cpu(stats->rmac_osized_frms);
6384 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6385 le32_to_cpu(stats->rmac_frag_frms);
6387 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6388 le32_to_cpu(stats->rmac_jabber_frms);
6389 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6390 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6391 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6392 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6393 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6394 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6396 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6397 le32_to_cpu(stats->rmac_ip);
6398 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6399 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6401 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6402 le32_to_cpu(stats->rmac_drop_ip);
6404 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6405 le32_to_cpu(stats->rmac_icmp);
6406 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6408 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6409 le32_to_cpu(stats->rmac_udp);
6411 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6412 le32_to_cpu(stats->rmac_err_drp_udp);
6413 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6418 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6419 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6420 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6421 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6422 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6423 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6424 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6425 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6426 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6427 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6428 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6429 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6431 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6432 le32_to_cpu(stats->rmac_pause_cnt);
6433 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6434 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6436 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6437 le32_to_cpu(stats->rmac_accepted_ip);
6438 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6439 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6440 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6441 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6442 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6443 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6444 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6445 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6446 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6447 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6448 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6449 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6450 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6451 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6452 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6453 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6454 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6455 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6456 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6458 /* Enhanced statistics exist only for Hercules */
6459 if (sp->device_type == XFRAME_II_DEVICE) {
6461 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6463 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6465 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6466 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6467 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6468 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6469 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6470 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6471 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6472 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6473 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6474 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6475 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6476 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6477 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6478 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6482 tmp_stats[i++] = swstats->single_ecc_errs;
6483 tmp_stats[i++] = swstats->double_ecc_errs;
6484 tmp_stats[i++] = swstats->parity_err_cnt;
6485 tmp_stats[i++] = swstats->serious_err_cnt;
6486 tmp_stats[i++] = swstats->soft_reset_cnt;
6487 tmp_stats[i++] = swstats->fifo_full_cnt;
6488 for (k = 0; k < MAX_RX_RINGS; k++)
6489 tmp_stats[i++] = swstats->ring_full_cnt[k];
6490 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6491 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6492 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6493 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6494 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6495 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6496 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6497 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6498 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6499 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6500 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6501 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6502 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6503 tmp_stats[i++] = swstats->sending_both;
6504 tmp_stats[i++] = swstats->outof_sequence_pkts;
6505 tmp_stats[i++] = swstats->flush_max_pkts;
6506 if (swstats->num_aggregations) {
6507 u64 tmp = swstats->sum_avg_pkts_aggregated;
6510 * Since 64-bit divide does not work on all platforms,
6511 * do repeated subtraction.
6513 while (tmp >= swstats->num_aggregations) {
6514 tmp -= swstats->num_aggregations;
6517 tmp_stats[i++] = count;
6520 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6521 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6522 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6523 tmp_stats[i++] = swstats->mem_allocated;
6524 tmp_stats[i++] = swstats->mem_freed;
6525 tmp_stats[i++] = swstats->link_up_cnt;
6526 tmp_stats[i++] = swstats->link_down_cnt;
6527 tmp_stats[i++] = swstats->link_up_time;
6528 tmp_stats[i++] = swstats->link_down_time;
6530 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6531 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6532 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6533 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6534 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6536 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6537 tmp_stats[i++] = swstats->rx_abort_cnt;
6538 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6539 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6540 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6541 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6542 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6543 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6544 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6545 tmp_stats[i++] = swstats->tda_err_cnt;
6546 tmp_stats[i++] = swstats->pfc_err_cnt;
6547 tmp_stats[i++] = swstats->pcc_err_cnt;
6548 tmp_stats[i++] = swstats->tti_err_cnt;
6549 tmp_stats[i++] = swstats->tpa_err_cnt;
6550 tmp_stats[i++] = swstats->sm_err_cnt;
6551 tmp_stats[i++] = swstats->lso_err_cnt;
6552 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6553 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6554 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6555 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6556 tmp_stats[i++] = swstats->rc_err_cnt;
6557 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6558 tmp_stats[i++] = swstats->rpa_err_cnt;
6559 tmp_stats[i++] = swstats->rda_err_cnt;
6560 tmp_stats[i++] = swstats->rti_err_cnt;
6561 tmp_stats[i++] = swstats->mc_err_cnt;
6564 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6566 return XENA_REG_SPACE;
6570 static int s2io_get_eeprom_len(struct net_device *dev)
6572 return XENA_EEPROM_SPACE;
6575 static int s2io_get_sset_count(struct net_device *dev, int sset)
6577 struct s2io_nic *sp = netdev_priv(dev);
6581 return S2IO_TEST_LEN;
6583 switch (sp->device_type) {
6584 case XFRAME_I_DEVICE:
6585 return XFRAME_I_STAT_LEN;
6586 case XFRAME_II_DEVICE:
6587 return XFRAME_II_STAT_LEN;
6596 static void s2io_ethtool_get_strings(struct net_device *dev,
6597 u32 stringset, u8 *data)
6600 struct s2io_nic *sp = netdev_priv(dev);
6602 switch (stringset) {
6604 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6607 stat_size = sizeof(ethtool_xena_stats_keys);
6608 memcpy(data, ðtool_xena_stats_keys, stat_size);
6609 if (sp->device_type == XFRAME_II_DEVICE) {
6610 memcpy(data + stat_size,
6611 ðtool_enhanced_stats_keys,
6612 sizeof(ethtool_enhanced_stats_keys));
6613 stat_size += sizeof(ethtool_enhanced_stats_keys);
6616 memcpy(data + stat_size, ðtool_driver_stats_keys,
6617 sizeof(ethtool_driver_stats_keys));
6621 static int s2io_set_features(struct net_device *dev, u32 features)
6623 struct s2io_nic *sp = netdev_priv(dev);
6624 u32 changed = (features ^ dev->features) & NETIF_F_LRO;
6626 if (changed && netif_running(dev)) {
6629 s2io_stop_all_tx_queue(sp);
6631 dev->features = features;
6632 rc = s2io_card_up(sp);
6636 s2io_start_all_tx_queue(sp);
6644 static const struct ethtool_ops netdev_ethtool_ops = {
6645 .get_settings = s2io_ethtool_gset,
6646 .set_settings = s2io_ethtool_sset,
6647 .get_drvinfo = s2io_ethtool_gdrvinfo,
6648 .get_regs_len = s2io_ethtool_get_regs_len,
6649 .get_regs = s2io_ethtool_gregs,
6650 .get_link = ethtool_op_get_link,
6651 .get_eeprom_len = s2io_get_eeprom_len,
6652 .get_eeprom = s2io_ethtool_geeprom,
6653 .set_eeprom = s2io_ethtool_seeprom,
6654 .get_ringparam = s2io_ethtool_gringparam,
6655 .get_pauseparam = s2io_ethtool_getpause_data,
6656 .set_pauseparam = s2io_ethtool_setpause_data,
6657 .self_test = s2io_ethtool_test,
6658 .get_strings = s2io_ethtool_get_strings,
6659 .set_phys_id = s2io_ethtool_set_led,
6660 .get_ethtool_stats = s2io_get_ethtool_stats,
6661 .get_sset_count = s2io_get_sset_count,
6665 * s2io_ioctl - Entry point for the Ioctl
6666 * @dev : Device pointer.
6667 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6668 * a proprietary structure used to pass information to the driver.
6669 * @cmd : This is used to distinguish between the different commands that
6670 * can be passed to the IOCTL functions.
6672 * Currently there are no special functionality supported in IOCTL, hence
6673 * function always return EOPNOTSUPPORTED
6676 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6682 * s2io_change_mtu - entry point to change MTU size for the device.
6683 * @dev : device pointer.
6684 * @new_mtu : the new MTU size for the device.
6685 * Description: A driver entry point to change MTU size for the device.
6686 * Before changing the MTU the device must be stopped.
6688 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6692 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6694 struct s2io_nic *sp = netdev_priv(dev);
6697 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6698 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6703 if (netif_running(dev)) {
6704 s2io_stop_all_tx_queue(sp);
6706 ret = s2io_card_up(sp);
6708 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6712 s2io_wake_all_tx_queue(sp);
6713 } else { /* Device is down */
6714 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6715 u64 val64 = new_mtu;
6717 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6724 * s2io_set_link - Set the LInk status
6725 * @data: long pointer to device private structue
6726 * Description: Sets the link status for the adapter
6729 static void s2io_set_link(struct work_struct *work)
6731 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6733 struct net_device *dev = nic->dev;
6734 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6740 if (!netif_running(dev))
6743 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6744 /* The card is being reset, no point doing anything */
6748 subid = nic->pdev->subsystem_device;
6749 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6751 * Allow a small delay for the NICs self initiated
6752 * cleanup to complete.
6757 val64 = readq(&bar0->adapter_status);
6758 if (LINK_IS_UP(val64)) {
6759 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6760 if (verify_xena_quiescence(nic)) {
6761 val64 = readq(&bar0->adapter_control);
6762 val64 |= ADAPTER_CNTL_EN;
6763 writeq(val64, &bar0->adapter_control);
6764 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6765 nic->device_type, subid)) {
6766 val64 = readq(&bar0->gpio_control);
6767 val64 |= GPIO_CTRL_GPIO_0;
6768 writeq(val64, &bar0->gpio_control);
6769 val64 = readq(&bar0->gpio_control);
6771 val64 |= ADAPTER_LED_ON;
6772 writeq(val64, &bar0->adapter_control);
6774 nic->device_enabled_once = true;
6777 "%s: Error: device is not Quiescent\n",
6779 s2io_stop_all_tx_queue(nic);
6782 val64 = readq(&bar0->adapter_control);
6783 val64 |= ADAPTER_LED_ON;
6784 writeq(val64, &bar0->adapter_control);
6785 s2io_link(nic, LINK_UP);
6787 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6789 val64 = readq(&bar0->gpio_control);
6790 val64 &= ~GPIO_CTRL_GPIO_0;
6791 writeq(val64, &bar0->gpio_control);
6792 val64 = readq(&bar0->gpio_control);
6795 val64 = readq(&bar0->adapter_control);
6796 val64 = val64 & (~ADAPTER_LED_ON);
6797 writeq(val64, &bar0->adapter_control);
6798 s2io_link(nic, LINK_DOWN);
6800 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6806 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6808 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6809 u64 *temp2, int size)
6811 struct net_device *dev = sp->dev;
6812 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6814 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6815 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6818 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6820 * As Rx frame are not going to be processed,
6821 * using same mapped address for the Rxd
6824 rxdp1->Buffer0_ptr = *temp0;
6826 *skb = dev_alloc_skb(size);
6829 "%s: Out of memory to allocate %s\n",
6830 dev->name, "1 buf mode SKBs");
6831 stats->mem_alloc_fail_cnt++;
6834 stats->mem_allocated += (*skb)->truesize;
6835 /* storing the mapped addr in a temp variable
6836 * such it will be used for next rxd whose
6837 * Host Control is NULL
6839 rxdp1->Buffer0_ptr = *temp0 =
6840 pci_map_single(sp->pdev, (*skb)->data,
6841 size - NET_IP_ALIGN,
6842 PCI_DMA_FROMDEVICE);
6843 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6844 goto memalloc_failed;
6845 rxdp->Host_Control = (unsigned long) (*skb);
6847 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6848 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6849 /* Two buffer Mode */
6851 rxdp3->Buffer2_ptr = *temp2;
6852 rxdp3->Buffer0_ptr = *temp0;
6853 rxdp3->Buffer1_ptr = *temp1;
6855 *skb = dev_alloc_skb(size);
6858 "%s: Out of memory to allocate %s\n",
6861 stats->mem_alloc_fail_cnt++;
6864 stats->mem_allocated += (*skb)->truesize;
6865 rxdp3->Buffer2_ptr = *temp2 =
6866 pci_map_single(sp->pdev, (*skb)->data,
6868 PCI_DMA_FROMDEVICE);
6869 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6870 goto memalloc_failed;
6871 rxdp3->Buffer0_ptr = *temp0 =
6872 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6873 PCI_DMA_FROMDEVICE);
6874 if (pci_dma_mapping_error(sp->pdev,
6875 rxdp3->Buffer0_ptr)) {
6876 pci_unmap_single(sp->pdev,
6877 (dma_addr_t)rxdp3->Buffer2_ptr,
6879 PCI_DMA_FROMDEVICE);
6880 goto memalloc_failed;
6882 rxdp->Host_Control = (unsigned long) (*skb);
6884 /* Buffer-1 will be dummy buffer not used */
6885 rxdp3->Buffer1_ptr = *temp1 =
6886 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6887 PCI_DMA_FROMDEVICE);
6888 if (pci_dma_mapping_error(sp->pdev,
6889 rxdp3->Buffer1_ptr)) {
6890 pci_unmap_single(sp->pdev,
6891 (dma_addr_t)rxdp3->Buffer0_ptr,
6892 BUF0_LEN, PCI_DMA_FROMDEVICE);
6893 pci_unmap_single(sp->pdev,
6894 (dma_addr_t)rxdp3->Buffer2_ptr,
6896 PCI_DMA_FROMDEVICE);
6897 goto memalloc_failed;
6904 stats->pci_map_fail_cnt++;
6905 stats->mem_freed += (*skb)->truesize;
6906 dev_kfree_skb(*skb);
6910 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6913 struct net_device *dev = sp->dev;
6914 if (sp->rxd_mode == RXD_MODE_1) {
6915 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6916 } else if (sp->rxd_mode == RXD_MODE_3B) {
6917 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6918 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6919 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6923 static int rxd_owner_bit_reset(struct s2io_nic *sp)
6925 int i, j, k, blk_cnt = 0, size;
6926 struct config_param *config = &sp->config;
6927 struct mac_info *mac_control = &sp->mac_control;
6928 struct net_device *dev = sp->dev;
6929 struct RxD_t *rxdp = NULL;
6930 struct sk_buff *skb = NULL;
6931 struct buffAdd *ba = NULL;
6932 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6934 /* Calculate the size based on ring mode */
6935 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6936 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6937 if (sp->rxd_mode == RXD_MODE_1)
6938 size += NET_IP_ALIGN;
6939 else if (sp->rxd_mode == RXD_MODE_3B)
6940 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6942 for (i = 0; i < config->rx_ring_num; i++) {
6943 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6944 struct ring_info *ring = &mac_control->rings[i];
6946 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6948 for (j = 0; j < blk_cnt; j++) {
6949 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6950 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
6951 if (sp->rxd_mode == RXD_MODE_3B)
6952 ba = &ring->ba[j][k];
6953 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
6961 set_rxd_buffer_size(sp, rxdp, size);
6963 /* flip the Ownership bit to Hardware */
6964 rxdp->Control_1 |= RXD_OWN_XENA;
6972 static int s2io_add_isr(struct s2io_nic *sp)
6975 struct net_device *dev = sp->dev;
6978 if (sp->config.intr_type == MSI_X)
6979 ret = s2io_enable_msi_x(sp);
6981 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6982 sp->config.intr_type = INTA;
6986 * Store the values of the MSIX table in
6987 * the struct s2io_nic structure
6989 store_xmsi_data(sp);
6991 /* After proper initialization of H/W, register ISR */
6992 if (sp->config.intr_type == MSI_X) {
6993 int i, msix_rx_cnt = 0;
6995 for (i = 0; i < sp->num_entries; i++) {
6996 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
6997 if (sp->s2io_entries[i].type ==
6999 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7001 err = request_irq(sp->entries[i].vector,
7002 s2io_msix_ring_handle,
7005 sp->s2io_entries[i].arg);
7006 } else if (sp->s2io_entries[i].type ==
7008 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
7010 err = request_irq(sp->entries[i].vector,
7011 s2io_msix_fifo_handle,
7014 sp->s2io_entries[i].arg);
7017 /* if either data or addr is zero print it. */
7018 if (!(sp->msix_info[i].addr &&
7019 sp->msix_info[i].data)) {
7021 "%s @Addr:0x%llx Data:0x%llx\n",
7023 (unsigned long long)
7024 sp->msix_info[i].addr,
7025 (unsigned long long)
7026 ntohl(sp->msix_info[i].data));
7030 remove_msix_isr(sp);
7033 "%s:MSI-X-%d registration "
7034 "failed\n", dev->name, i);
7037 "%s: Defaulting to INTA\n",
7039 sp->config.intr_type = INTA;
7042 sp->s2io_entries[i].in_use =
7043 MSIX_REGISTERED_SUCCESS;
7047 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7049 "MSI-X-TX entries enabled through alarm vector\n");
7052 if (sp->config.intr_type == INTA) {
7053 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7056 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7064 static void s2io_rem_isr(struct s2io_nic *sp)
7066 if (sp->config.intr_type == MSI_X)
7067 remove_msix_isr(sp);
7069 remove_inta_isr(sp);
7072 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7075 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7076 register u64 val64 = 0;
7077 struct config_param *config;
7078 config = &sp->config;
7080 if (!is_s2io_card_up(sp))
7083 del_timer_sync(&sp->alarm_timer);
7084 /* If s2io_set_link task is executing, wait till it completes. */
7085 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7087 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7090 if (sp->config.napi) {
7092 if (config->intr_type == MSI_X) {
7093 for (; off < sp->config.rx_ring_num; off++)
7094 napi_disable(&sp->mac_control.rings[off].napi);
7097 napi_disable(&sp->napi);
7100 /* disable Tx and Rx traffic on the NIC */
7106 /* stop the tx queue, indicate link down */
7107 s2io_link(sp, LINK_DOWN);
7109 /* Check if the device is Quiescent and then Reset the NIC */
7111 /* As per the HW requirement we need to replenish the
7112 * receive buffer to avoid the ring bump. Since there is
7113 * no intention of processing the Rx frame at this pointwe are
7114 * just setting the ownership bit of rxd in Each Rx
7115 * ring to HW and set the appropriate buffer size
7116 * based on the ring mode
7118 rxd_owner_bit_reset(sp);
7120 val64 = readq(&bar0->adapter_status);
7121 if (verify_xena_quiescence(sp)) {
7122 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7129 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7130 "adapter status reads 0x%llx\n",
7131 (unsigned long long)val64);
7138 /* Free all Tx buffers */
7139 free_tx_buffers(sp);
7141 /* Free all Rx buffers */
7142 free_rx_buffers(sp);
7144 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7147 static void s2io_card_down(struct s2io_nic *sp)
7149 do_s2io_card_down(sp, 1);
7152 static int s2io_card_up(struct s2io_nic *sp)
7155 struct config_param *config;
7156 struct mac_info *mac_control;
7157 struct net_device *dev = (struct net_device *)sp->dev;
7160 /* Initialize the H/W I/O registers */
7163 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7171 * Initializing the Rx buffers. For now we are considering only 1
7172 * Rx ring and initializing buffers into 30 Rx blocks
7174 config = &sp->config;
7175 mac_control = &sp->mac_control;
7177 for (i = 0; i < config->rx_ring_num; i++) {
7178 struct ring_info *ring = &mac_control->rings[i];
7180 ring->mtu = dev->mtu;
7181 ring->lro = !!(dev->features & NETIF_F_LRO);
7182 ret = fill_rx_buffers(sp, ring, 1);
7184 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7187 free_rx_buffers(sp);
7190 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7191 ring->rx_bufs_left);
7194 /* Initialise napi */
7196 if (config->intr_type == MSI_X) {
7197 for (i = 0; i < sp->config.rx_ring_num; i++)
7198 napi_enable(&sp->mac_control.rings[i].napi);
7200 napi_enable(&sp->napi);
7204 /* Maintain the state prior to the open */
7205 if (sp->promisc_flg)
7206 sp->promisc_flg = 0;
7207 if (sp->m_cast_flg) {
7209 sp->all_multi_pos = 0;
7212 /* Setting its receive mode */
7213 s2io_set_multicast(dev);
7215 if (dev->features & NETIF_F_LRO) {
7216 /* Initialize max aggregatable pkts per session based on MTU */
7217 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7218 /* Check if we can use (if specified) user provided value */
7219 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7220 sp->lro_max_aggr_per_sess = lro_max_pkts;
7223 /* Enable Rx Traffic and interrupts on the NIC */
7224 if (start_nic(sp)) {
7225 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7227 free_rx_buffers(sp);
7231 /* Add interrupt service routine */
7232 if (s2io_add_isr(sp) != 0) {
7233 if (sp->config.intr_type == MSI_X)
7236 free_rx_buffers(sp);
7240 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7242 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7244 /* Enable select interrupts */
7245 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7246 if (sp->config.intr_type != INTA) {
7247 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7248 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7250 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7251 interruptible |= TX_PIC_INTR;
7252 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7259 * s2io_restart_nic - Resets the NIC.
7260 * @data : long pointer to the device private structure
7262 * This function is scheduled to be run by the s2io_tx_watchdog
7263 * function after 0.5 secs to reset the NIC. The idea is to reduce
7264 * the run time of the watch dog routine which is run holding a
7268 static void s2io_restart_nic(struct work_struct *work)
7270 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7271 struct net_device *dev = sp->dev;
7275 if (!netif_running(dev))
7279 if (s2io_card_up(sp)) {
7280 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7282 s2io_wake_all_tx_queue(sp);
7283 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7289 * s2io_tx_watchdog - Watchdog for transmit side.
7290 * @dev : Pointer to net device structure
7292 * This function is triggered if the Tx Queue is stopped
7293 * for a pre-defined amount of time when the Interface is still up.
7294 * If the Interface is jammed in such a situation, the hardware is
7295 * reset (by s2io_close) and restarted again (by s2io_open) to
7296 * overcome any problem that might have been caused in the hardware.
7301 static void s2io_tx_watchdog(struct net_device *dev)
7303 struct s2io_nic *sp = netdev_priv(dev);
7304 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7306 if (netif_carrier_ok(dev)) {
7307 swstats->watchdog_timer_cnt++;
7308 schedule_work(&sp->rst_timer_task);
7309 swstats->soft_reset_cnt++;
7314 * rx_osm_handler - To perform some OS related operations on SKB.
7315 * @sp: private member of the device structure,pointer to s2io_nic structure.
7316 * @skb : the socket buffer pointer.
7317 * @len : length of the packet
7318 * @cksum : FCS checksum of the frame.
7319 * @ring_no : the ring from which this RxD was extracted.
7321 * This function is called by the Rx interrupt serivce routine to perform
7322 * some OS related operations on the SKB before passing it to the upper
7323 * layers. It mainly checks if the checksum is OK, if so adds it to the
7324 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7325 * to the upper layer. If the checksum is wrong, it increments the Rx
7326 * packet error count, frees the SKB and returns error.
7328 * SUCCESS on success and -1 on failure.
7330 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7332 struct s2io_nic *sp = ring_data->nic;
7333 struct net_device *dev = (struct net_device *)ring_data->dev;
7334 struct sk_buff *skb = (struct sk_buff *)
7335 ((unsigned long)rxdp->Host_Control);
7336 int ring_no = ring_data->ring_no;
7337 u16 l3_csum, l4_csum;
7338 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7339 struct lro *uninitialized_var(lro);
7341 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7346 /* Check for parity error */
7348 swstats->parity_err_cnt++;
7350 err_mask = err >> 48;
7353 swstats->rx_parity_err_cnt++;
7357 swstats->rx_abort_cnt++;
7361 swstats->rx_parity_abort_cnt++;
7365 swstats->rx_rda_fail_cnt++;
7369 swstats->rx_unkn_prot_cnt++;
7373 swstats->rx_fcs_err_cnt++;
7377 swstats->rx_buf_size_err_cnt++;
7381 swstats->rx_rxd_corrupt_cnt++;
7385 swstats->rx_unkn_err_cnt++;
7389 * Drop the packet if bad transfer code. Exception being
7390 * 0x5, which could be due to unsupported IPv6 extension header.
7391 * In this case, we let stack handle the packet.
7392 * Note that in this case, since checksum will be incorrect,
7393 * stack will validate the same.
7395 if (err_mask != 0x5) {
7396 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7397 dev->name, err_mask);
7398 dev->stats.rx_crc_errors++;
7402 ring_data->rx_bufs_left -= 1;
7403 rxdp->Host_Control = 0;
7408 rxdp->Host_Control = 0;
7409 if (sp->rxd_mode == RXD_MODE_1) {
7410 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7413 } else if (sp->rxd_mode == RXD_MODE_3B) {
7414 int get_block = ring_data->rx_curr_get_info.block_index;
7415 int get_off = ring_data->rx_curr_get_info.offset;
7416 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7417 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7418 unsigned char *buff = skb_push(skb, buf0_len);
7420 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7421 memcpy(buff, ba->ba_0, buf0_len);
7422 skb_put(skb, buf2_len);
7425 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7426 ((!ring_data->lro) ||
7427 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
7428 (dev->features & NETIF_F_RXCSUM)) {
7429 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7430 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7431 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7433 * NIC verifies if the Checksum of the received
7434 * frame is Ok or not and accordingly returns
7435 * a flag in the RxD.
7437 skb->ip_summed = CHECKSUM_UNNECESSARY;
7438 if (ring_data->lro) {
7443 ret = s2io_club_tcp_session(ring_data,
7448 case 3: /* Begin anew */
7451 case 1: /* Aggregate */
7452 lro_append_pkt(sp, lro, skb, tcp_len);
7454 case 4: /* Flush session */
7455 lro_append_pkt(sp, lro, skb, tcp_len);
7456 queue_rx_frame(lro->parent,
7458 clear_lro_session(lro);
7459 swstats->flush_max_pkts++;
7461 case 2: /* Flush both */
7462 lro->parent->data_len = lro->frags_len;
7463 swstats->sending_both++;
7464 queue_rx_frame(lro->parent,
7466 clear_lro_session(lro);
7468 case 0: /* sessions exceeded */
7469 case -1: /* non-TCP or not L2 aggregatable */
7471 * First pkt in session not
7472 * L3/L4 aggregatable
7477 "%s: Samadhana!!\n",
7484 * Packet with erroneous checksum, let the
7485 * upper layers deal with it.
7487 skb_checksum_none_assert(skb);
7490 skb_checksum_none_assert(skb);
7492 swstats->mem_freed += skb->truesize;
7494 skb_record_rx_queue(skb, ring_no);
7495 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7497 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7502 * s2io_link - stops/starts the Tx queue.
7503 * @sp : private member of the device structure, which is a pointer to the
7504 * s2io_nic structure.
7505 * @link : inidicates whether link is UP/DOWN.
7507 * This function stops/starts the Tx queue depending on whether the link
7508 * status of the NIC is is down or up. This is called by the Alarm
7509 * interrupt handler whenever a link change interrupt comes up.
7514 static void s2io_link(struct s2io_nic *sp, int link)
7516 struct net_device *dev = (struct net_device *)sp->dev;
7517 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7519 if (link != sp->last_link_state) {
7521 if (link == LINK_DOWN) {
7522 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7523 s2io_stop_all_tx_queue(sp);
7524 netif_carrier_off(dev);
7525 if (swstats->link_up_cnt)
7526 swstats->link_up_time =
7527 jiffies - sp->start_time;
7528 swstats->link_down_cnt++;
7530 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7531 if (swstats->link_down_cnt)
7532 swstats->link_down_time =
7533 jiffies - sp->start_time;
7534 swstats->link_up_cnt++;
7535 netif_carrier_on(dev);
7536 s2io_wake_all_tx_queue(sp);
7539 sp->last_link_state = link;
7540 sp->start_time = jiffies;
7544 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7545 * @sp : private member of the device structure, which is a pointer to the
7546 * s2io_nic structure.
7548 * This function initializes a few of the PCI and PCI-X configuration registers
7549 * with recommended values.
7554 static void s2io_init_pci(struct s2io_nic *sp)
7556 u16 pci_cmd = 0, pcix_cmd = 0;
7558 /* Enable Data Parity Error Recovery in PCI-X command register. */
7559 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7561 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7563 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7566 /* Set the PErr Response bit in PCI command register. */
7567 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7568 pci_write_config_word(sp->pdev, PCI_COMMAND,
7569 (pci_cmd | PCI_COMMAND_PARITY));
7570 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7573 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7578 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7579 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7580 "(%d) not supported\n", tx_fifo_num);
7582 if (tx_fifo_num < 1)
7585 tx_fifo_num = MAX_TX_FIFOS;
7587 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7591 *dev_multiq = multiq;
7593 if (tx_steering_type && (1 == tx_fifo_num)) {
7594 if (tx_steering_type != TX_DEFAULT_STEERING)
7596 "Tx steering is not supported with "
7597 "one fifo. Disabling Tx steering.\n");
7598 tx_steering_type = NO_STEERING;
7601 if ((tx_steering_type < NO_STEERING) ||
7602 (tx_steering_type > TX_DEFAULT_STEERING)) {
7604 "Requested transmit steering not supported\n");
7605 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7606 tx_steering_type = NO_STEERING;
7609 if (rx_ring_num > MAX_RX_RINGS) {
7611 "Requested number of rx rings not supported\n");
7612 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7614 rx_ring_num = MAX_RX_RINGS;
7617 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7618 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7619 "Defaulting to INTA\n");
7620 *dev_intr_type = INTA;
7623 if ((*dev_intr_type == MSI_X) &&
7624 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7625 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7626 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7627 "Defaulting to INTA\n");
7628 *dev_intr_type = INTA;
7631 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7632 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7633 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7637 for (i = 0; i < MAX_RX_RINGS; i++)
7638 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7639 DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7640 "supported\nDefaulting to %d\n",
7641 MAX_RX_BLOCKS_PER_RING);
7642 rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7649 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7650 * or Traffic class respectively.
7651 * @nic: device private variable
7652 * Description: The function configures the receive steering to
7653 * desired receive ring.
7654 * Return Value: SUCCESS on success and
7655 * '-1' on failure (endian settings incorrect).
7657 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7659 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7660 register u64 val64 = 0;
7662 if (ds_codepoint > 63)
7665 val64 = RTS_DS_MEM_DATA(ring);
7666 writeq(val64, &bar0->rts_ds_mem_data);
7668 val64 = RTS_DS_MEM_CTRL_WE |
7669 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7670 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7672 writeq(val64, &bar0->rts_ds_mem_ctrl);
7674 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7675 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7679 static const struct net_device_ops s2io_netdev_ops = {
7680 .ndo_open = s2io_open,
7681 .ndo_stop = s2io_close,
7682 .ndo_get_stats = s2io_get_stats,
7683 .ndo_start_xmit = s2io_xmit,
7684 .ndo_validate_addr = eth_validate_addr,
7685 .ndo_set_multicast_list = s2io_set_multicast,
7686 .ndo_do_ioctl = s2io_ioctl,
7687 .ndo_set_mac_address = s2io_set_mac_addr,
7688 .ndo_change_mtu = s2io_change_mtu,
7689 .ndo_set_features = s2io_set_features,
7690 .ndo_tx_timeout = s2io_tx_watchdog,
7691 #ifdef CONFIG_NET_POLL_CONTROLLER
7692 .ndo_poll_controller = s2io_netpoll,
7697 * s2io_init_nic - Initialization of the adapter .
7698 * @pdev : structure containing the PCI related information of the device.
7699 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7701 * The function initializes an adapter identified by the pci_dec structure.
7702 * All OS related initialization including memory and device structure and
7703 * initlaization of the device private variable is done. Also the swapper
7704 * control register is initialized to enable read and write into the I/O
7705 * registers of the device.
7707 * returns 0 on success and negative on failure.
7710 static int __devinit
7711 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7713 struct s2io_nic *sp;
7714 struct net_device *dev;
7716 int dma_flag = false;
7717 u32 mac_up, mac_down;
7718 u64 val64 = 0, tmp64 = 0;
7719 struct XENA_dev_config __iomem *bar0 = NULL;
7721 struct config_param *config;
7722 struct mac_info *mac_control;
7724 u8 dev_intr_type = intr_type;
7727 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7731 ret = pci_enable_device(pdev);
7734 "%s: pci_enable_device failed\n", __func__);
7738 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7739 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7741 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7743 "Unable to obtain 64bit DMA "
7744 "for consistent allocations\n");
7745 pci_disable_device(pdev);
7748 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7749 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7751 pci_disable_device(pdev);
7754 ret = pci_request_regions(pdev, s2io_driver_name);
7756 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7758 pci_disable_device(pdev);
7762 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7764 dev = alloc_etherdev(sizeof(struct s2io_nic));
7766 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7767 pci_disable_device(pdev);
7768 pci_release_regions(pdev);
7772 pci_set_master(pdev);
7773 pci_set_drvdata(pdev, dev);
7774 SET_NETDEV_DEV(dev, &pdev->dev);
7776 /* Private member variable initialized to s2io NIC structure */
7777 sp = netdev_priv(dev);
7780 sp->high_dma_flag = dma_flag;
7781 sp->device_enabled_once = false;
7782 if (rx_ring_mode == 1)
7783 sp->rxd_mode = RXD_MODE_1;
7784 if (rx_ring_mode == 2)
7785 sp->rxd_mode = RXD_MODE_3B;
7787 sp->config.intr_type = dev_intr_type;
7789 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7790 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7791 sp->device_type = XFRAME_II_DEVICE;
7793 sp->device_type = XFRAME_I_DEVICE;
7796 /* Initialize some PCI/PCI-X fields of the NIC. */
7800 * Setting the device configuration parameters.
7801 * Most of these parameters can be specified by the user during
7802 * module insertion as they are module loadable parameters. If
7803 * these parameters are not not specified during load time, they
7804 * are initialized with default values.
7806 config = &sp->config;
7807 mac_control = &sp->mac_control;
7809 config->napi = napi;
7810 config->tx_steering_type = tx_steering_type;
7812 /* Tx side parameters. */
7813 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7814 config->tx_fifo_num = MAX_TX_FIFOS;
7816 config->tx_fifo_num = tx_fifo_num;
7818 /* Initialize the fifos used for tx steering */
7819 if (config->tx_fifo_num < 5) {
7820 if (config->tx_fifo_num == 1)
7821 sp->total_tcp_fifos = 1;
7823 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7824 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7825 sp->total_udp_fifos = 1;
7826 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7828 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7829 FIFO_OTHER_MAX_NUM);
7830 sp->udp_fifo_idx = sp->total_tcp_fifos;
7831 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7832 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7835 config->multiq = dev_multiq;
7836 for (i = 0; i < config->tx_fifo_num; i++) {
7837 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7839 tx_cfg->fifo_len = tx_fifo_len[i];
7840 tx_cfg->fifo_priority = i;
7843 /* mapping the QoS priority to the configured fifos */
7844 for (i = 0; i < MAX_TX_FIFOS; i++)
7845 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7847 /* map the hashing selector table to the configured fifos */
7848 for (i = 0; i < config->tx_fifo_num; i++)
7849 sp->fifo_selector[i] = fifo_selector[i];
7852 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7853 for (i = 0; i < config->tx_fifo_num; i++) {
7854 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7856 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7857 if (tx_cfg->fifo_len < 65) {
7858 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7862 /* + 2 because one Txd for skb->data and one Txd for UFO */
7863 config->max_txds = MAX_SKB_FRAGS + 2;
7865 /* Rx side parameters. */
7866 config->rx_ring_num = rx_ring_num;
7867 for (i = 0; i < config->rx_ring_num; i++) {
7868 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7869 struct ring_info *ring = &mac_control->rings[i];
7871 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7872 rx_cfg->ring_priority = i;
7873 ring->rx_bufs_left = 0;
7874 ring->rxd_mode = sp->rxd_mode;
7875 ring->rxd_count = rxd_count[sp->rxd_mode];
7876 ring->pdev = sp->pdev;
7877 ring->dev = sp->dev;
7880 for (i = 0; i < rx_ring_num; i++) {
7881 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7883 rx_cfg->ring_org = RING_ORG_BUFF1;
7884 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7887 /* Setting Mac Control parameters */
7888 mac_control->rmac_pause_time = rmac_pause_time;
7889 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7890 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7893 /* initialize the shared memory used by the NIC and the host */
7894 if (init_shared_mem(sp)) {
7895 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7897 goto mem_alloc_failed;
7900 sp->bar0 = pci_ioremap_bar(pdev, 0);
7902 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7905 goto bar0_remap_failed;
7908 sp->bar1 = pci_ioremap_bar(pdev, 2);
7910 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7913 goto bar1_remap_failed;
7916 dev->irq = pdev->irq;
7917 dev->base_addr = (unsigned long)sp->bar0;
7919 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7920 for (j = 0; j < MAX_TX_FIFOS; j++) {
7921 mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000);
7924 /* Driver entry points */
7925 dev->netdev_ops = &s2io_netdev_ops;
7926 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7927 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7928 NETIF_F_TSO | NETIF_F_TSO6 |
7929 NETIF_F_RXCSUM | NETIF_F_LRO;
7930 dev->features |= dev->hw_features |
7931 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7932 if (sp->device_type & XFRAME_II_DEVICE) {
7933 dev->hw_features |= NETIF_F_UFO;
7935 dev->features |= NETIF_F_UFO;
7937 if (sp->high_dma_flag == true)
7938 dev->features |= NETIF_F_HIGHDMA;
7939 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7940 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7941 INIT_WORK(&sp->set_link_task, s2io_set_link);
7943 pci_save_state(sp->pdev);
7945 /* Setting swapper control on the NIC, for proper reset operation */
7946 if (s2io_set_swapper(sp)) {
7947 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7950 goto set_swap_failed;
7953 /* Verify if the Herc works on the slot its placed into */
7954 if (sp->device_type & XFRAME_II_DEVICE) {
7955 mode = s2io_verify_pci_mode(sp);
7957 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
7960 goto set_swap_failed;
7964 if (sp->config.intr_type == MSI_X) {
7965 sp->num_entries = config->rx_ring_num + 1;
7966 ret = s2io_enable_msi_x(sp);
7969 ret = s2io_test_msi(sp);
7970 /* rollback MSI-X, will re-enable during add_isr() */
7971 remove_msix_isr(sp);
7976 "MSI-X requested but failed to enable\n");
7977 sp->config.intr_type = INTA;
7981 if (config->intr_type == MSI_X) {
7982 for (i = 0; i < config->rx_ring_num ; i++) {
7983 struct ring_info *ring = &mac_control->rings[i];
7985 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
7988 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
7991 /* Not needed for Herc */
7992 if (sp->device_type & XFRAME_I_DEVICE) {
7994 * Fix for all "FFs" MAC address problems observed on
7997 fix_mac_address(sp);
8002 * MAC address initialization.
8003 * For now only one mac address will be read and used.
8006 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
8007 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
8008 writeq(val64, &bar0->rmac_addr_cmd_mem);
8009 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
8010 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8012 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8013 mac_down = (u32)tmp64;
8014 mac_up = (u32) (tmp64 >> 32);
8016 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8017 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8018 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8019 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8020 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8021 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8023 /* Set the factory defined MAC address initially */
8024 dev->addr_len = ETH_ALEN;
8025 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8026 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
8028 /* initialize number of multicast & unicast MAC entries variables */
8029 if (sp->device_type == XFRAME_I_DEVICE) {
8030 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8031 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8032 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8033 } else if (sp->device_type == XFRAME_II_DEVICE) {
8034 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8035 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8036 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8039 /* store mac addresses from CAM to s2io_nic structure */
8040 do_s2io_store_unicast_mc(sp);
8042 /* Configure MSIX vector for number of rings configured plus one */
8043 if ((sp->device_type == XFRAME_II_DEVICE) &&
8044 (config->intr_type == MSI_X))
8045 sp->num_entries = config->rx_ring_num + 1;
8047 /* Store the values of the MSIX table in the s2io_nic structure */
8048 store_xmsi_data(sp);
8049 /* reset Nic and bring it to known state */
8053 * Initialize link state flags
8054 * and the card state parameter
8058 /* Initialize spinlocks */
8059 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8060 struct fifo_info *fifo = &mac_control->fifos[i];
8062 spin_lock_init(&fifo->tx_lock);
8066 * SXE-002: Configure link and activity LED to init state
8069 subid = sp->pdev->subsystem_device;
8070 if ((subid & 0xFF) >= 0x07) {
8071 val64 = readq(&bar0->gpio_control);
8072 val64 |= 0x0000800000000000ULL;
8073 writeq(val64, &bar0->gpio_control);
8074 val64 = 0x0411040400000000ULL;
8075 writeq(val64, (void __iomem *)bar0 + 0x2700);
8076 val64 = readq(&bar0->gpio_control);
8079 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8081 if (register_netdev(dev)) {
8082 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8084 goto register_failed;
8087 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8088 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8089 sp->product_name, pdev->revision);
8090 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8091 s2io_driver_version);
8092 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8093 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8094 if (sp->device_type & XFRAME_II_DEVICE) {
8095 mode = s2io_print_pci_mode(sp);
8098 unregister_netdev(dev);
8099 goto set_swap_failed;
8102 switch (sp->rxd_mode) {
8104 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8108 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8113 switch (sp->config.napi) {
8115 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8118 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8122 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8123 sp->config.tx_fifo_num);
8125 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8126 sp->config.rx_ring_num);
8128 switch (sp->config.intr_type) {
8130 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8133 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8136 if (sp->config.multiq) {
8137 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8138 struct fifo_info *fifo = &mac_control->fifos[i];
8140 fifo->multiq = config->multiq;
8142 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8145 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8148 switch (sp->config.tx_steering_type) {
8150 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8153 case TX_PRIORITY_STEERING:
8155 "%s: Priority steering enabled for transmit\n",
8158 case TX_DEFAULT_STEERING:
8160 "%s: Default steering enabled for transmit\n",
8164 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8168 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8170 /* Initialize device name */
8171 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
8174 sp->vlan_strip_flag = 1;
8176 sp->vlan_strip_flag = 0;
8179 * Make Link state as off at this point, when the Link change
8180 * interrupt comes the state will be automatically changed to
8183 netif_carrier_off(dev);
8194 free_shared_mem(sp);
8195 pci_disable_device(pdev);
8196 pci_release_regions(pdev);
8197 pci_set_drvdata(pdev, NULL);
8204 * s2io_rem_nic - Free the PCI device
8205 * @pdev: structure containing the PCI related information of the device.
8206 * Description: This function is called by the Pci subsystem to release a
8207 * PCI device and free up all resource held up by the device. This could
8208 * be in response to a Hot plug event or when the driver is to be removed
8212 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8214 struct net_device *dev = pci_get_drvdata(pdev);
8215 struct s2io_nic *sp;
8218 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8222 sp = netdev_priv(dev);
8224 cancel_work_sync(&sp->rst_timer_task);
8225 cancel_work_sync(&sp->set_link_task);
8227 unregister_netdev(dev);
8229 free_shared_mem(sp);
8232 pci_release_regions(pdev);
8233 pci_set_drvdata(pdev, NULL);
8235 pci_disable_device(pdev);
8239 * s2io_starter - Entry point for the driver
8240 * Description: This function is the entry point for the driver. It verifies
8241 * the module loadable parameters and initializes PCI configuration space.
8244 static int __init s2io_starter(void)
8246 return pci_register_driver(&s2io_driver);
8250 * s2io_closer - Cleanup routine for the driver
8251 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8254 static __exit void s2io_closer(void)
8256 pci_unregister_driver(&s2io_driver);
8257 DBG_PRINT(INIT_DBG, "cleanup done\n");
8260 module_init(s2io_starter);
8261 module_exit(s2io_closer);
8263 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8264 struct tcphdr **tcp, struct RxD_t *rxdp,
8265 struct s2io_nic *sp)
8268 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8270 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8272 "%s: Non-TCP frames not supported for LRO\n",
8277 /* Checking for DIX type or DIX type with VLAN */
8278 if ((l2_type == 0) || (l2_type == 4)) {
8279 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8281 * If vlan stripping is disabled and the frame is VLAN tagged,
8282 * shift the offset by the VLAN header size bytes.
8284 if ((!sp->vlan_strip_flag) &&
8285 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8286 ip_off += HEADER_VLAN_SIZE;
8288 /* LLC, SNAP etc are considered non-mergeable */
8292 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8293 ip_len = (u8)((*ip)->ihl);
8295 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8300 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8303 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8304 if ((lro->iph->saddr != ip->saddr) ||
8305 (lro->iph->daddr != ip->daddr) ||
8306 (lro->tcph->source != tcp->source) ||
8307 (lro->tcph->dest != tcp->dest))
8312 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8314 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8317 static void initiate_new_session(struct lro *lro, u8 *l2h,
8318 struct iphdr *ip, struct tcphdr *tcp,
8319 u32 tcp_pyld_len, u16 vlan_tag)
8321 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8325 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8326 lro->tcp_ack = tcp->ack_seq;
8328 lro->total_len = ntohs(ip->tot_len);
8330 lro->vlan_tag = vlan_tag;
8332 * Check if we saw TCP timestamp.
8333 * Other consistency checks have already been done.
8335 if (tcp->doff == 8) {
8337 ptr = (__be32 *)(tcp+1);
8339 lro->cur_tsval = ntohl(*(ptr+1));
8340 lro->cur_tsecr = *(ptr+2);
8345 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8347 struct iphdr *ip = lro->iph;
8348 struct tcphdr *tcp = lro->tcph;
8350 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8352 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8354 /* Update L3 header */
8355 ip->tot_len = htons(lro->total_len);
8357 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8360 /* Update L4 header */
8361 tcp->ack_seq = lro->tcp_ack;
8362 tcp->window = lro->window;
8364 /* Update tsecr field if this session has timestamps enabled */
8366 __be32 *ptr = (__be32 *)(tcp + 1);
8367 *(ptr+2) = lro->cur_tsecr;
8370 /* Update counters required for calculation of
8371 * average no. of packets aggregated.
8373 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8374 swstats->num_aggregations++;
8377 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8378 struct tcphdr *tcp, u32 l4_pyld)
8380 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8381 lro->total_len += l4_pyld;
8382 lro->frags_len += l4_pyld;
8383 lro->tcp_next_seq += l4_pyld;
8386 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8387 lro->tcp_ack = tcp->ack_seq;
8388 lro->window = tcp->window;
8392 /* Update tsecr and tsval from this packet */
8393 ptr = (__be32 *)(tcp+1);
8394 lro->cur_tsval = ntohl(*(ptr+1));
8395 lro->cur_tsecr = *(ptr + 2);
8399 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8400 struct tcphdr *tcp, u32 tcp_pyld_len)
8404 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8406 if (!tcp_pyld_len) {
8407 /* Runt frame or a pure ack */
8411 if (ip->ihl != 5) /* IP has options */
8414 /* If we see CE codepoint in IP header, packet is not mergeable */
8415 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8418 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8419 if (tcp->urg || tcp->psh || tcp->rst ||
8420 tcp->syn || tcp->fin ||
8421 tcp->ece || tcp->cwr || !tcp->ack) {
8423 * Currently recognize only the ack control word and
8424 * any other control field being set would result in
8425 * flushing the LRO session
8431 * Allow only one TCP timestamp option. Don't aggregate if
8432 * any other options are detected.
8434 if (tcp->doff != 5 && tcp->doff != 8)
8437 if (tcp->doff == 8) {
8438 ptr = (u8 *)(tcp + 1);
8439 while (*ptr == TCPOPT_NOP)
8441 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8444 /* Ensure timestamp value increases monotonically */
8446 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8449 /* timestamp echo reply should be non-zero */
8450 if (*((__be32 *)(ptr+6)) == 0)
8457 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8458 u8 **tcp, u32 *tcp_len, struct lro **lro,
8459 struct RxD_t *rxdp, struct s2io_nic *sp)
8462 struct tcphdr *tcph;
8465 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8467 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8472 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8474 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8475 tcph = (struct tcphdr *)*tcp;
8476 *tcp_len = get_l4_pyld_length(ip, tcph);
8477 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8478 struct lro *l_lro = &ring_data->lro0_n[i];
8479 if (l_lro->in_use) {
8480 if (check_for_socket_match(l_lro, ip, tcph))
8482 /* Sock pair matched */
8485 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8486 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8487 "expected 0x%x, actual 0x%x\n",
8489 (*lro)->tcp_next_seq,
8492 swstats->outof_sequence_pkts++;
8497 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8499 ret = 1; /* Aggregate */
8501 ret = 2; /* Flush both */
8507 /* Before searching for available LRO objects,
8508 * check if the pkt is L3/L4 aggregatable. If not
8509 * don't create new LRO session. Just send this
8512 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8515 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8516 struct lro *l_lro = &ring_data->lro0_n[i];
8517 if (!(l_lro->in_use)) {
8519 ret = 3; /* Begin anew */
8525 if (ret == 0) { /* sessions exceeded */
8526 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8534 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8538 update_L3L4_header(sp, *lro);
8541 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8542 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8543 update_L3L4_header(sp, *lro);
8544 ret = 4; /* Flush the LRO */
8548 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8555 static void clear_lro_session(struct lro *lro)
8557 static u16 lro_struct_size = sizeof(struct lro);
8559 memset(lro, 0, lro_struct_size);
8562 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8564 struct net_device *dev = skb->dev;
8565 struct s2io_nic *sp = netdev_priv(dev);
8567 skb->protocol = eth_type_trans(skb, dev);
8568 if (vlan_tag && sp->vlan_strip_flag)
8569 __vlan_hwaccel_put_tag(skb, vlan_tag);
8570 if (sp->config.napi)
8571 netif_receive_skb(skb);
8576 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8577 struct sk_buff *skb, u32 tcp_len)
8579 struct sk_buff *first = lro->parent;
8580 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8582 first->len += tcp_len;
8583 first->data_len = lro->frags_len;
8584 skb_pull(skb, (skb->len - tcp_len));
8585 if (skb_shinfo(first)->frag_list)
8586 lro->last_frag->next = skb;
8588 skb_shinfo(first)->frag_list = skb;
8589 first->truesize += skb->truesize;
8590 lro->last_frag = skb;
8591 swstats->clubbed_frms_cnt++;
8595 * s2io_io_error_detected - called when PCI error is detected
8596 * @pdev: Pointer to PCI device
8597 * @state: The current pci connection state
8599 * This function is called after a PCI bus error affecting
8600 * this device has been detected.
8602 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8603 pci_channel_state_t state)
8605 struct net_device *netdev = pci_get_drvdata(pdev);
8606 struct s2io_nic *sp = netdev_priv(netdev);
8608 netif_device_detach(netdev);
8610 if (state == pci_channel_io_perm_failure)
8611 return PCI_ERS_RESULT_DISCONNECT;
8613 if (netif_running(netdev)) {
8614 /* Bring down the card, while avoiding PCI I/O */
8615 do_s2io_card_down(sp, 0);
8617 pci_disable_device(pdev);
8619 return PCI_ERS_RESULT_NEED_RESET;
8623 * s2io_io_slot_reset - called after the pci bus has been reset.
8624 * @pdev: Pointer to PCI device
8626 * Restart the card from scratch, as if from a cold-boot.
8627 * At this point, the card has exprienced a hard reset,
8628 * followed by fixups by BIOS, and has its config space
8629 * set up identically to what it was at cold boot.
8631 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8633 struct net_device *netdev = pci_get_drvdata(pdev);
8634 struct s2io_nic *sp = netdev_priv(netdev);
8636 if (pci_enable_device(pdev)) {
8637 pr_err("Cannot re-enable PCI device after reset.\n");
8638 return PCI_ERS_RESULT_DISCONNECT;
8641 pci_set_master(pdev);
8644 return PCI_ERS_RESULT_RECOVERED;
8648 * s2io_io_resume - called when traffic can start flowing again.
8649 * @pdev: Pointer to PCI device
8651 * This callback is called when the error recovery driver tells
8652 * us that its OK to resume normal operation.
8654 static void s2io_io_resume(struct pci_dev *pdev)
8656 struct net_device *netdev = pci_get_drvdata(pdev);
8657 struct s2io_nic *sp = netdev_priv(netdev);
8659 if (netif_running(netdev)) {
8660 if (s2io_card_up(sp)) {
8661 pr_err("Can't bring device back up after reset.\n");
8665 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8667 pr_err("Can't restore mac addr after reset.\n");
8672 netif_device_attach(netdev);
8673 netif_tx_wake_all_queues(netdev);
git.openpandora.org / pandora-kernel.git / blob