drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32
  33 #define RTL8169_VERSION "2.3LK-NAPI"
  34 #define MODULENAME "r8169"
  35 #define PFX MODULENAME ": "
  36
  37 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  38 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  39
  40 #ifdef RTL8169_DEBUG
  41 #define assert(expr) \
  42         if (!(expr)) {                                  \
  43                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  44                 #expr,__FILE__,__func__,__LINE__);              \
  45         }
  46 #define dprintk(fmt, args...) \
  47         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  48 #else
  49 #define assert(expr) do {} while (0)
  50 #define dprintk(fmt, args...)   do {} while (0)
  51 #endif /* RTL8169_DEBUG */
  52
  53 #define R8169_MSG_DEFAULT \
  54         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  55
  56 #define TX_BUFFS_AVAIL(tp) \
  57         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  58
  59 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  60    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  61 static const int multicast_filter_limit = 32;
  62
  63 /* MAC address length */
  64 #define MAC_ADDR_LEN    6
  65
  66 #define MAX_READ_REQUEST_SHIFT  12
  67 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  68 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  69 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_NAPI_WEIGHT       64
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  80
  81 #define RTL8169_TX_TIMEOUT      (6*HZ)
  82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  83
  84 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  85 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  86 #define RTL_EEPROM_SIG_ADDR     0x0000
  87
  88 /* write/read MMIO register */
  89 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  90 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  91 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  92 #define RTL_R8(reg)             readb (ioaddr + (reg))
  93 #define RTL_R16(reg)            readw (ioaddr + (reg))
  94 #define RTL_R32(reg)            readl (ioaddr + (reg))
  95
  96 enum mac_version {
  97         RTL_GIGA_MAC_NONE   = 0x00,
  98         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  99         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 100         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 101         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 102         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 103         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 104         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 105         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 106         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 107         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 108         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 109         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 110         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 111         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 112         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 113         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 114         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 115         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 116         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 117         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 118         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 119         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 120         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 121         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 122         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
 123         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
 124         RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
 125         RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
 126 };
 127
 128 #define _R(NAME,MAC,MASK) \
 129         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 130
 131 static const struct {
 132         const char *name;
 133         u8 mac_version;
 134         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 135 } rtl_chip_info[] = {
 136         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 137         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 138         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 139         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 140         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 141         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 142         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 143         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 144         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 146         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 147         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 148         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 149         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 150         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 151         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 152         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 153         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 154         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 155         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 156         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 157         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 158         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 159         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 160         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
 161         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
 162         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
 163         _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, 0xff7e1880)  // PCI-E
 164 };
 165 #undef _R
 166
 167 enum cfg_version {
 168         RTL_CFG_0 = 0x00,
 169         RTL_CFG_1,
 170         RTL_CFG_2
 171 };
 172
 173 static void rtl_hw_start_8169(struct net_device *);
 174 static void rtl_hw_start_8168(struct net_device *);
 175 static void rtl_hw_start_8101(struct net_device *);
 176
 177 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 178         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 179         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 180         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 181         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 182         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 183         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 184         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 185         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 186         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 187                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 188         { 0x0001,                               0x8168,
 189                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 190         {0,},
 191 };
 192
 193 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 194
 195 static int rx_buf_sz = 16383;
 196 static int use_dac;
 197 static struct {
 198         u32 msg_enable;
 199 } debug = { -1 };
 200
 201 enum rtl_registers {
 202         MAC0            = 0,    /* Ethernet hardware address. */
 203         MAC4            = 4,
 204         MAR0            = 8,    /* Multicast filter. */
 205         CounterAddrLow          = 0x10,
 206         CounterAddrHigh         = 0x14,
 207         TxDescStartAddrLow      = 0x20,
 208         TxDescStartAddrHigh     = 0x24,
 209         TxHDescStartAddrLow     = 0x28,
 210         TxHDescStartAddrHigh    = 0x2c,
 211         FLASH           = 0x30,
 212         ERSR            = 0x36,
 213         ChipCmd         = 0x37,
 214         TxPoll          = 0x38,
 215         IntrMask        = 0x3c,
 216         IntrStatus      = 0x3e,
 217         TxConfig        = 0x40,
 218         RxConfig        = 0x44,
 219         RxMissed        = 0x4c,
 220         Cfg9346         = 0x50,
 221         Config0         = 0x51,
 222         Config1         = 0x52,
 223         Config2         = 0x53,
 224         Config3         = 0x54,
 225         Config4         = 0x55,
 226         Config5         = 0x56,
 227         MultiIntr       = 0x5c,
 228         PHYAR           = 0x60,
 229         PHYstatus       = 0x6c,
 230         RxMaxSize       = 0xda,
 231         CPlusCmd        = 0xe0,
 232         IntrMitigate    = 0xe2,
 233         RxDescAddrLow   = 0xe4,
 234         RxDescAddrHigh  = 0xe8,
 235         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 236
 237 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 238
 239         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 240
 241 #define TxPacketMax     (8064 >> 7)
 242
 243         FuncEvent       = 0xf0,
 244         FuncEventMask   = 0xf4,
 245         FuncPresetState = 0xf8,
 246         FuncForceEvent  = 0xfc,
 247 };
 248
 249 enum rtl8110_registers {
 250         TBICSR                  = 0x64,
 251         TBI_ANAR                = 0x68,
 252         TBI_LPAR                = 0x6a,
 253 };
 254
 255 enum rtl8168_8101_registers {
 256         CSIDR                   = 0x64,
 257         CSIAR                   = 0x68,
 258 #define CSIAR_FLAG                      0x80000000
 259 #define CSIAR_WRITE_CMD                 0x80000000
 260 #define CSIAR_BYTE_ENABLE               0x0f
 261 #define CSIAR_BYTE_ENABLE_SHIFT         12
 262 #define CSIAR_ADDR_MASK                 0x0fff
 263         PMCH                    = 0x6f,
 264         EPHYAR                  = 0x80,
 265 #define EPHYAR_FLAG                     0x80000000
 266 #define EPHYAR_WRITE_CMD                0x80000000
 267 #define EPHYAR_REG_MASK                 0x1f
 268 #define EPHYAR_REG_SHIFT                16
 269 #define EPHYAR_DATA_MASK                0xffff
 270         DBG_REG                 = 0xd1,
 271 #define FIX_NAK_1                       (1 << 4)
 272 #define FIX_NAK_2                       (1 << 3)
 273         EFUSEAR                 = 0xdc,
 274 #define EFUSEAR_FLAG                    0x80000000
 275 #define EFUSEAR_WRITE_CMD               0x80000000
 276 #define EFUSEAR_READ_CMD                0x00000000
 277 #define EFUSEAR_REG_MASK                0x03ff
 278 #define EFUSEAR_REG_SHIFT               8
 279 #define EFUSEAR_DATA_MASK               0xff
 280 };
 281
 282 enum rtl8168_registers {
 283         ERIDR                   = 0x70,
 284         ERIAR                   = 0x74,
 285 #define ERIAR_FLAG                      0x80000000
 286 #define ERIAR_WRITE_CMD                 0x80000000
 287 #define ERIAR_READ_CMD                  0x00000000
 288 #define ERIAR_ADDR_BYTE_ALIGN           4
 289 #define ERIAR_EXGMAC                    0
 290 #define ERIAR_MSIX                      1
 291 #define ERIAR_ASF                       2
 292 #define ERIAR_TYPE_SHIFT                16
 293 #define ERIAR_BYTEEN                    0x0f
 294 #define ERIAR_BYTEEN_SHIFT              12
 295         EPHY_RXER_NUM           = 0x7c,
 296         OCPDR                   = 0xb0, /* OCP GPHY access */
 297 #define OCPDR_WRITE_CMD                 0x80000000
 298 #define OCPDR_READ_CMD                  0x00000000
 299 #define OCPDR_REG_MASK                  0x7f
 300 #define OCPDR_GPHY_REG_SHIFT            16
 301 #define OCPDR_DATA_MASK                 0xffff
 302         OCPAR                   = 0xb4,
 303 #define OCPAR_FLAG                      0x80000000
 304 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 305 #define OCPAR_GPHY_READ_CMD             0x0000f060
 306         RDSAR1                  = 0xd0  /* 8168c only. Undocumented on 8168dp */
 307 };
 308
 309 enum rtl_register_content {
 310         /* InterruptStatusBits */
 311         SYSErr          = 0x8000,
 312         PCSTimeout      = 0x4000,
 313         SWInt           = 0x0100,
 314         TxDescUnavail   = 0x0080,
 315         RxFIFOOver      = 0x0040,
 316         LinkChg         = 0x0020,
 317         RxOverflow      = 0x0010,
 318         TxErr           = 0x0008,
 319         TxOK            = 0x0004,
 320         RxErr           = 0x0002,
 321         RxOK            = 0x0001,
 322
 323         /* RxStatusDesc */
 324         RxFOVF  = (1 << 23),
 325         RxRWT   = (1 << 22),
 326         RxRES   = (1 << 21),
 327         RxRUNT  = (1 << 20),
 328         RxCRC   = (1 << 19),
 329
 330         /* ChipCmdBits */
 331         CmdReset        = 0x10,
 332         CmdRxEnb        = 0x08,
 333         CmdTxEnb        = 0x04,
 334         RxBufEmpty      = 0x01,
 335
 336         /* TXPoll register p.5 */
 337         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 338         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 339         FSWInt          = 0x01,         /* Forced software interrupt */
 340
 341         /* Cfg9346Bits */
 342         Cfg9346_Lock    = 0x00,
 343         Cfg9346_Unlock  = 0xc0,
 344
 345         /* rx_mode_bits */
 346         AcceptErr       = 0x20,
 347         AcceptRunt      = 0x10,
 348         AcceptBroadcast = 0x08,
 349         AcceptMulticast = 0x04,
 350         AcceptMyPhys    = 0x02,
 351         AcceptAllPhys   = 0x01,
 352
 353         /* RxConfigBits */
 354         RxCfgFIFOShift  = 13,
 355         RxCfgDMAShift   =  8,
 356
 357         /* TxConfigBits */
 358         TxInterFrameGapShift = 24,
 359         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 360
 361         /* Config1 register p.24 */
 362         LEDS1           = (1 << 7),
 363         LEDS0           = (1 << 6),
 364         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 365         Speed_down      = (1 << 4),
 366         MEMMAP          = (1 << 3),
 367         IOMAP           = (1 << 2),
 368         VPD             = (1 << 1),
 369         PMEnable        = (1 << 0),     /* Power Management Enable */
 370
 371         /* Config2 register p. 25 */
 372         PCI_Clock_66MHz = 0x01,
 373         PCI_Clock_33MHz = 0x00,
 374
 375         /* Config3 register p.25 */
 376         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 377         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 378         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 379
 380         /* Config5 register p.27 */
 381         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 382         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 383         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 384         LanWake         = (1 << 1),     /* LanWake enable/disable */
 385         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 386
 387         /* TBICSR p.28 */
 388         TBIReset        = 0x80000000,
 389         TBILoopback     = 0x40000000,
 390         TBINwEnable     = 0x20000000,
 391         TBINwRestart    = 0x10000000,
 392         TBILinkOk       = 0x02000000,
 393         TBINwComplete   = 0x01000000,
 394
 395         /* CPlusCmd p.31 */
 396         EnableBist      = (1 << 15),    // 8168 8101
 397         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 398         Normal_mode     = (1 << 13),    // unused
 399         Force_half_dup  = (1 << 12),    // 8168 8101
 400         Force_rxflow_en = (1 << 11),    // 8168 8101
 401         Force_txflow_en = (1 << 10),    // 8168 8101
 402         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 403         ASF             = (1 << 8),     // 8168 8101
 404         PktCntrDisable  = (1 << 7),     // 8168 8101
 405         Mac_dbgo_sel    = 0x001c,       // 8168
 406         RxVlan          = (1 << 6),
 407         RxChkSum        = (1 << 5),
 408         PCIDAC          = (1 << 4),
 409         PCIMulRW        = (1 << 3),
 410         INTT_0          = 0x0000,       // 8168
 411         INTT_1          = 0x0001,       // 8168
 412         INTT_2          = 0x0002,       // 8168
 413         INTT_3          = 0x0003,       // 8168
 414
 415         /* rtl8169_PHYstatus */
 416         TBI_Enable      = 0x80,
 417         TxFlowCtrl      = 0x40,
 418         RxFlowCtrl      = 0x20,
 419         _1000bpsF       = 0x10,
 420         _100bps         = 0x08,
 421         _10bps          = 0x04,
 422         LinkStatus      = 0x02,
 423         FullDup         = 0x01,
 424
 425         /* _TBICSRBit */
 426         TBILinkOK       = 0x02000000,
 427
 428         /* DumpCounterCommand */
 429         CounterDump     = 0x8,
 430 };
 431
 432 enum desc_status_bit {
 433         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 434         RingEnd         = (1 << 30), /* End of descriptor ring */
 435         FirstFrag       = (1 << 29), /* First segment of a packet */
 436         LastFrag        = (1 << 28), /* Final segment of a packet */
 437
 438         /* Tx private */
 439         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 440         MSSShift        = 16,        /* MSS value position */
 441         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 442         IPCS            = (1 << 18), /* Calculate IP checksum */
 443         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 444         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 445         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 446
 447         /* Rx private */
 448         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 449         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 450
 451 #define RxProtoUDP      (PID1)
 452 #define RxProtoTCP      (PID0)
 453 #define RxProtoIP       (PID1 | PID0)
 454 #define RxProtoMask     RxProtoIP
 455
 456         IPFail          = (1 << 16), /* IP checksum failed */
 457         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 458         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 459         RxVlanTag       = (1 << 16), /* VLAN tag available */
 460 };
 461
 462 #define RsvdMask        0x3fffc000
 463
 464 struct TxDesc {
 465         __le32 opts1;
 466         __le32 opts2;
 467         __le64 addr;
 468 };
 469
 470 struct RxDesc {
 471         __le32 opts1;
 472         __le32 opts2;
 473         __le64 addr;
 474 };
 475
 476 struct ring_info {
 477         struct sk_buff  *skb;
 478         u32             len;
 479         u8              __pad[sizeof(void *) - sizeof(u32)];
 480 };
 481
 482 enum features {
 483         RTL_FEATURE_WOL         = (1 << 0),
 484         RTL_FEATURE_MSI         = (1 << 1),
 485         RTL_FEATURE_GMII        = (1 << 2),
 486 };
 487
 488 struct rtl8169_counters {
 489         __le64  tx_packets;
 490         __le64  rx_packets;
 491         __le64  tx_errors;
 492         __le32  rx_errors;
 493         __le16  rx_missed;
 494         __le16  align_errors;
 495         __le32  tx_one_collision;
 496         __le32  tx_multi_collision;
 497         __le64  rx_unicast;
 498         __le64  rx_broadcast;
 499         __le32  rx_multicast;
 500         __le16  tx_aborted;
 501         __le16  tx_underun;
 502 };
 503
 504 struct rtl8169_private {
 505         void __iomem *mmio_addr;        /* memory map physical address */
 506         struct pci_dev *pci_dev;        /* Index of PCI device */
 507         struct net_device *dev;
 508         struct napi_struct napi;
 509         spinlock_t lock;                /* spin lock flag */
 510         u32 msg_enable;
 511         int chipset;
 512         int mac_version;
 513         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 514         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 515         u32 dirty_rx;
 516         u32 dirty_tx;
 517         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 518         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 519         dma_addr_t TxPhyAddr;
 520         dma_addr_t RxPhyAddr;
 521         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 522         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 523         struct timer_list timer;
 524         u16 cp_cmd;
 525         u16 intr_event;
 526         u16 napi_event;
 527         u16 intr_mask;
 528         int phy_1000_ctrl_reg;
 529 #ifdef CONFIG_R8169_VLAN
 530         struct vlan_group *vlgrp;
 531 #endif
 532
 533         struct mdio_ops {
 534                 void (*write)(void __iomem *, int, int);
 535                 int (*read)(void __iomem *, int);
 536         } mdio_ops;
 537
 538         struct pll_power_ops {
 539                 void (*down)(struct rtl8169_private *);
 540                 void (*up)(struct rtl8169_private *);
 541         } pll_power_ops;
 542
 543         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 544         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 545         void (*phy_reset_enable)(struct rtl8169_private *tp);
 546         void (*hw_start)(struct net_device *);
 547         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 548         unsigned int (*link_ok)(void __iomem *);
 549         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 550         int pcie_cap;
 551         struct delayed_work task;
 552         unsigned features;
 553
 554         struct mii_if_info mii;
 555         struct rtl8169_counters counters;
 556         u32 saved_wolopts;
 557
 558         const struct firmware *fw;
 559 };
 560
 561 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 562 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 563 module_param(use_dac, int, 0);
 564 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 565 module_param_named(debug, debug.msg_enable, int, 0);
 566 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 567 MODULE_LICENSE("GPL");
 568 MODULE_VERSION(RTL8169_VERSION);
 569 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 570 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 571
 572 static int rtl8169_open(struct net_device *dev);
 573 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 574                                       struct net_device *dev);
 575 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 576 static int rtl8169_init_ring(struct net_device *dev);
 577 static void rtl_hw_start(struct net_device *dev);
 578 static int rtl8169_close(struct net_device *dev);
 579 static void rtl_set_rx_mode(struct net_device *dev);
 580 static void rtl8169_tx_timeout(struct net_device *dev);
 581 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 582 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 583                                 void __iomem *, u32 budget);
 584 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 585 static void rtl8169_down(struct net_device *dev);
 586 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 587 static int rtl8169_poll(struct napi_struct *napi, int budget);
 588
 589 static const unsigned int rtl8169_rx_config =
 590         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 591
 592 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 593 {
 594         void __iomem *ioaddr = tp->mmio_addr;
 595         int i;
 596
 597         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 598         for (i = 0; i < 20; i++) {
 599                 udelay(100);
 600                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 601                         break;
 602         }
 603         return RTL_R32(OCPDR);
 604 }
 605
 606 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 607 {
 608         void __iomem *ioaddr = tp->mmio_addr;
 609         int i;
 610
 611         RTL_W32(OCPDR, data);
 612         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 613         for (i = 0; i < 20; i++) {
 614                 udelay(100);
 615                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 616                         break;
 617         }
 618 }
 619
 620 static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
 621 {
 622         int i;
 623
 624         RTL_W8(ERIDR, cmd);
 625         RTL_W32(ERIAR, 0x800010e8);
 626         msleep(2);
 627         for (i = 0; i < 5; i++) {
 628                 udelay(100);
 629                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
 630                         break;
 631         }
 632
 633         ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
 634 }
 635
 636 #define OOB_CMD_RESET           0x00
 637 #define OOB_CMD_DRIVER_START    0x05
 638 #define OOB_CMD_DRIVER_STOP     0x06
 639
 640 static void rtl8168_driver_start(struct rtl8169_private *tp)
 641 {
 642         int i;
 643
 644         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 645
 646         for (i = 0; i < 10; i++) {
 647                 msleep(10);
 648                 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
 649                         break;
 650         }
 651 }
 652
 653 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 654 {
 655         int i;
 656
 657         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 658
 659         for (i = 0; i < 10; i++) {
 660                 msleep(10);
 661                 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
 662                         break;
 663         }
 664 }
 665
 666
 667 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 668 {
 669         int i;
 670
 671         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 672
 673         for (i = 20; i > 0; i--) {
 674                 /*
 675                  * Check if the RTL8169 has completed writing to the specified
 676                  * MII register.
 677                  */
 678                 if (!(RTL_R32(PHYAR) & 0x80000000))
 679                         break;
 680                 udelay(25);
 681         }
 682         /*
 683          * According to hardware specs a 20us delay is required after write
 684          * complete indication, but before sending next command.
 685          */
 686         udelay(20);
 687 }
 688
 689 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 690 {
 691         int i, value = -1;
 692
 693         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 694
 695         for (i = 20; i > 0; i--) {
 696                 /*
 697                  * Check if the RTL8169 has completed retrieving data from
 698                  * the specified MII register.
 699                  */
 700                 if (RTL_R32(PHYAR) & 0x80000000) {
 701                         value = RTL_R32(PHYAR) & 0xffff;
 702                         break;
 703                 }
 704                 udelay(25);
 705         }
 706         /*
 707          * According to hardware specs a 20us delay is required after read
 708          * complete indication, but before sending next command.
 709          */
 710         udelay(20);
 711
 712         return value;
 713 }
 714
 715 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 716 {
 717         int i;
 718
 719         RTL_W32(OCPDR, data |
 720                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 721         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 722         RTL_W32(EPHY_RXER_NUM, 0);
 723
 724         for (i = 0; i < 100; i++) {
 725                 mdelay(1);
 726                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 727                         break;
 728         }
 729 }
 730
 731 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 732 {
 733         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 734                 (value & OCPDR_DATA_MASK));
 735 }
 736
 737 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 738 {
 739         int i;
 740
 741         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 742
 743         mdelay(1);
 744         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 745         RTL_W32(EPHY_RXER_NUM, 0);
 746
 747         for (i = 0; i < 100; i++) {
 748                 mdelay(1);
 749                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 750                         break;
 751         }
 752
 753         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 754 }
 755
 756 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 757
 758 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 759 {
 760         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 761 }
 762
 763 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 764 {
 765         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 766 }
 767
 768 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 769 {
 770         r8168dp_2_mdio_start(ioaddr);
 771
 772         r8169_mdio_write(ioaddr, reg_addr, value);
 773
 774         r8168dp_2_mdio_stop(ioaddr);
 775 }
 776
 777 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 778 {
 779         int value;
 780
 781         r8168dp_2_mdio_start(ioaddr);
 782
 783         value = r8169_mdio_read(ioaddr, reg_addr);
 784
 785         r8168dp_2_mdio_stop(ioaddr);
 786
 787         return value;
 788 }
 789
 790 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 791 {
 792         tp->mdio_ops.write(tp->mmio_addr, location, val);
 793 }
 794
 795 static int rtl_readphy(struct rtl8169_private *tp, int location)
 796 {
 797         return tp->mdio_ops.read(tp->mmio_addr, location);
 798 }
 799
 800 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 801 {
 802         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 803 }
 804
 805 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 806 {
 807         int val;
 808
 809         val = rtl_readphy(tp, reg_addr);
 810         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 811 }
 812
 813 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 814                            int val)
 815 {
 816         struct rtl8169_private *tp = netdev_priv(dev);
 817
 818         rtl_writephy(tp, location, val);
 819 }
 820
 821 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 822 {
 823         struct rtl8169_private *tp = netdev_priv(dev);
 824
 825         return rtl_readphy(tp, location);
 826 }
 827
 828 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 829 {
 830         unsigned int i;
 831
 832         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 833                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 834
 835         for (i = 0; i < 100; i++) {
 836                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 837                         break;
 838                 udelay(10);
 839         }
 840 }
 841
 842 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 843 {
 844         u16 value = 0xffff;
 845         unsigned int i;
 846
 847         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 848
 849         for (i = 0; i < 100; i++) {
 850                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 851                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 852                         break;
 853                 }
 854                 udelay(10);
 855         }
 856
 857         return value;
 858 }
 859
 860 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 861 {
 862         unsigned int i;
 863
 864         RTL_W32(CSIDR, value);
 865         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 866                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 867
 868         for (i = 0; i < 100; i++) {
 869                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 870                         break;
 871                 udelay(10);
 872         }
 873 }
 874
 875 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 876 {
 877         u32 value = ~0x00;
 878         unsigned int i;
 879
 880         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 881                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 882
 883         for (i = 0; i < 100; i++) {
 884                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 885                         value = RTL_R32(CSIDR);
 886                         break;
 887                 }
 888                 udelay(10);
 889         }
 890
 891         return value;
 892 }
 893
 894 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
 895 {
 896         u8 value = 0xff;
 897         unsigned int i;
 898
 899         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
 900
 901         for (i = 0; i < 300; i++) {
 902                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
 903                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
 904                         break;
 905                 }
 906                 udelay(100);
 907         }
 908
 909         return value;
 910 }
 911
 912 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 913 {
 914         RTL_W16(IntrMask, 0x0000);
 915
 916         RTL_W16(IntrStatus, 0xffff);
 917 }
 918
 919 static void rtl8169_asic_down(void __iomem *ioaddr)
 920 {
 921         RTL_W8(ChipCmd, 0x00);
 922         rtl8169_irq_mask_and_ack(ioaddr);
 923         RTL_R16(CPlusCmd);
 924 }
 925
 926 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
 927 {
 928         void __iomem *ioaddr = tp->mmio_addr;
 929
 930         return RTL_R32(TBICSR) & TBIReset;
 931 }
 932
 933 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
 934 {
 935         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
 936 }
 937
 938 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 939 {
 940         return RTL_R32(TBICSR) & TBILinkOk;
 941 }
 942
 943 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 944 {
 945         return RTL_R8(PHYstatus) & LinkStatus;
 946 }
 947
 948 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
 949 {
 950         void __iomem *ioaddr = tp->mmio_addr;
 951
 952         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 953 }
 954
 955 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
 956 {
 957         unsigned int val;
 958
 959         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
 960         rtl_writephy(tp, MII_BMCR, val & 0xffff);
 961 }
 962
 963 static void __rtl8169_check_link_status(struct net_device *dev,
 964                                       struct rtl8169_private *tp,
 965                                       void __iomem *ioaddr,
 966                                       bool pm)
 967 {
 968         unsigned long flags;
 969
 970         spin_lock_irqsave(&tp->lock, flags);
 971         if (tp->link_ok(ioaddr)) {
 972                 /* This is to cancel a scheduled suspend if there's one. */
 973                 if (pm)
 974                         pm_request_resume(&tp->pci_dev->dev);
 975                 netif_carrier_on(dev);
 976                 if (net_ratelimit())
 977                         netif_info(tp, ifup, dev, "link up\n");
 978         } else {
 979                 netif_carrier_off(dev);
 980                 netif_info(tp, ifdown, dev, "link down\n");
 981                 if (pm)
 982                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
 983         }
 984         spin_unlock_irqrestore(&tp->lock, flags);
 985 }
 986
 987 static void rtl8169_check_link_status(struct net_device *dev,
 988                                       struct rtl8169_private *tp,
 989                                       void __iomem *ioaddr)
 990 {
 991         __rtl8169_check_link_status(dev, tp, ioaddr, false);
 992 }
 993
 994 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 995
 996 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
 997 {
 998         void __iomem *ioaddr = tp->mmio_addr;
 999         u8 options;
1000         u32 wolopts = 0;
1001
1002         options = RTL_R8(Config1);
1003         if (!(options & PMEnable))
1004                 return 0;
1005
1006         options = RTL_R8(Config3);
1007         if (options & LinkUp)
1008                 wolopts |= WAKE_PHY;
1009         if (options & MagicPacket)
1010                 wolopts |= WAKE_MAGIC;
1011
1012         options = RTL_R8(Config5);
1013         if (options & UWF)
1014                 wolopts |= WAKE_UCAST;
1015         if (options & BWF)
1016                 wolopts |= WAKE_BCAST;
1017         if (options & MWF)
1018                 wolopts |= WAKE_MCAST;
1019
1020         return wolopts;
1021 }
1022
1023 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1024 {
1025         struct rtl8169_private *tp = netdev_priv(dev);
1026
1027         spin_lock_irq(&tp->lock);
1028
1029         wol->supported = WAKE_ANY;
1030         wol->wolopts = __rtl8169_get_wol(tp);
1031
1032         spin_unlock_irq(&tp->lock);
1033 }
1034
1035 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1036 {
1037         void __iomem *ioaddr = tp->mmio_addr;
1038         unsigned int i;
1039         static const struct {
1040                 u32 opt;
1041                 u16 reg;
1042                 u8  mask;
1043         } cfg[] = {
1044                 { WAKE_ANY,   Config1, PMEnable },
1045                 { WAKE_PHY,   Config3, LinkUp },
1046                 { WAKE_MAGIC, Config3, MagicPacket },
1047                 { WAKE_UCAST, Config5, UWF },
1048                 { WAKE_BCAST, Config5, BWF },
1049                 { WAKE_MCAST, Config5, MWF },
1050                 { WAKE_ANY,   Config5, LanWake }
1051         };
1052
1053         RTL_W8(Cfg9346, Cfg9346_Unlock);
1054
1055         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1056                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1057                 if (wolopts & cfg[i].opt)
1058                         options |= cfg[i].mask;
1059                 RTL_W8(cfg[i].reg, options);
1060         }
1061
1062         RTL_W8(Cfg9346, Cfg9346_Lock);
1063 }
1064
1065 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1066 {
1067         struct rtl8169_private *tp = netdev_priv(dev);
1068
1069         spin_lock_irq(&tp->lock);
1070
1071         if (wol->wolopts)
1072                 tp->features |= RTL_FEATURE_WOL;
1073         else
1074                 tp->features &= ~RTL_FEATURE_WOL;
1075         __rtl8169_set_wol(tp, wol->wolopts);
1076         spin_unlock_irq(&tp->lock);
1077
1078         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1079
1080         return 0;
1081 }
1082
1083 static void rtl8169_get_drvinfo(struct net_device *dev,
1084                                 struct ethtool_drvinfo *info)
1085 {
1086         struct rtl8169_private *tp = netdev_priv(dev);
1087
1088         strcpy(info->driver, MODULENAME);
1089         strcpy(info->version, RTL8169_VERSION);
1090         strcpy(info->bus_info, pci_name(tp->pci_dev));
1091 }
1092
1093 static int rtl8169_get_regs_len(struct net_device *dev)
1094 {
1095         return R8169_REGS_SIZE;
1096 }
1097
1098 static int rtl8169_set_speed_tbi(struct net_device *dev,
1099                                  u8 autoneg, u16 speed, u8 duplex)
1100 {
1101         struct rtl8169_private *tp = netdev_priv(dev);
1102         void __iomem *ioaddr = tp->mmio_addr;
1103         int ret = 0;
1104         u32 reg;
1105
1106         reg = RTL_R32(TBICSR);
1107         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1108             (duplex == DUPLEX_FULL)) {
1109                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1110         } else if (autoneg == AUTONEG_ENABLE)
1111                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1112         else {
1113                 netif_warn(tp, link, dev,
1114                            "incorrect speed setting refused in TBI mode\n");
1115                 ret = -EOPNOTSUPP;
1116         }
1117
1118         return ret;
1119 }
1120
1121 static int rtl8169_set_speed_xmii(struct net_device *dev,
1122                                   u8 autoneg, u16 speed, u8 duplex)
1123 {
1124         struct rtl8169_private *tp = netdev_priv(dev);
1125         int giga_ctrl, bmcr;
1126
1127         if (autoneg == AUTONEG_ENABLE) {
1128                 int auto_nego;
1129
1130                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1131                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1132                               ADVERTISE_100HALF | ADVERTISE_100FULL);
1133                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1134
1135                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1136                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1137
1138                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1139                 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1140                     (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1141                     (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1142                     (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1143                     (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1144                     (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1145                     (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1146                     (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1147                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1148                 } else {
1149                         netif_info(tp, link, dev,
1150                                    "PHY does not support 1000Mbps\n");
1151                 }
1152
1153                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1154
1155                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1156                     (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1157                     (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1158                         /*
1159                          * Wake up the PHY.
1160                          * Vendor specific (0x1f) and reserved (0x0e) MII
1161                          * registers.
1162                          */
1163                         rtl_writephy(tp, 0x1f, 0x0000);
1164                         rtl_writephy(tp, 0x0e, 0x0000);
1165                 }
1166
1167                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1168                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1169         } else {
1170                 giga_ctrl = 0;
1171
1172                 if (speed == SPEED_10)
1173                         bmcr = 0;
1174                 else if (speed == SPEED_100)
1175                         bmcr = BMCR_SPEED100;
1176                 else
1177                         return -EINVAL;
1178
1179                 if (duplex == DUPLEX_FULL)
1180                         bmcr |= BMCR_FULLDPLX;
1181
1182                 rtl_writephy(tp, 0x1f, 0x0000);
1183         }
1184
1185         tp->phy_1000_ctrl_reg = giga_ctrl;
1186
1187         rtl_writephy(tp, MII_BMCR, bmcr);
1188
1189         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1190             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1191                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1192                         rtl_writephy(tp, 0x17, 0x2138);
1193                         rtl_writephy(tp, 0x0e, 0x0260);
1194                 } else {
1195                         rtl_writephy(tp, 0x17, 0x2108);
1196                         rtl_writephy(tp, 0x0e, 0x0000);
1197                 }
1198         }
1199
1200         return 0;
1201 }
1202
1203 static int rtl8169_set_speed(struct net_device *dev,
1204                              u8 autoneg, u16 speed, u8 duplex)
1205 {
1206         struct rtl8169_private *tp = netdev_priv(dev);
1207         int ret;
1208
1209         ret = tp->set_speed(dev, autoneg, speed, duplex);
1210
1211         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1212                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1213
1214         return ret;
1215 }
1216
1217 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1218 {
1219         struct rtl8169_private *tp = netdev_priv(dev);
1220         unsigned long flags;
1221         int ret;
1222
1223         spin_lock_irqsave(&tp->lock, flags);
1224         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1225         spin_unlock_irqrestore(&tp->lock, flags);
1226
1227         return ret;
1228 }
1229
1230 static u32 rtl8169_get_rx_csum(struct net_device *dev)
1231 {
1232         struct rtl8169_private *tp = netdev_priv(dev);
1233
1234         return tp->cp_cmd & RxChkSum;
1235 }
1236
1237 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1238 {
1239         struct rtl8169_private *tp = netdev_priv(dev);
1240         void __iomem *ioaddr = tp->mmio_addr;
1241         unsigned long flags;
1242
1243         spin_lock_irqsave(&tp->lock, flags);
1244
1245         if (data)
1246                 tp->cp_cmd |= RxChkSum;
1247         else
1248                 tp->cp_cmd &= ~RxChkSum;
1249
1250         RTL_W16(CPlusCmd, tp->cp_cmd);
1251         RTL_R16(CPlusCmd);
1252
1253         spin_unlock_irqrestore(&tp->lock, flags);
1254
1255         return 0;
1256 }
1257
1258 #ifdef CONFIG_R8169_VLAN
1259
1260 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1261                                       struct sk_buff *skb)
1262 {
1263         return (vlan_tx_tag_present(skb)) ?
1264                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1265 }
1266
1267 static void rtl8169_vlan_rx_register(struct net_device *dev,
1268                                      struct vlan_group *grp)
1269 {
1270         struct rtl8169_private *tp = netdev_priv(dev);
1271         void __iomem *ioaddr = tp->mmio_addr;
1272         unsigned long flags;
1273
1274         spin_lock_irqsave(&tp->lock, flags);
1275         tp->vlgrp = grp;
1276         /*
1277          * Do not disable RxVlan on 8110SCd.
1278          */
1279         if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1280                 tp->cp_cmd |= RxVlan;
1281         else
1282                 tp->cp_cmd &= ~RxVlan;
1283         RTL_W16(CPlusCmd, tp->cp_cmd);
1284         RTL_R16(CPlusCmd);
1285         spin_unlock_irqrestore(&tp->lock, flags);
1286 }
1287
1288 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1289                                struct sk_buff *skb, int polling)
1290 {
1291         u32 opts2 = le32_to_cpu(desc->opts2);
1292         struct vlan_group *vlgrp = tp->vlgrp;
1293         int ret;
1294
1295         if (vlgrp && (opts2 & RxVlanTag)) {
1296                 u16 vtag = swab16(opts2 & 0xffff);
1297
1298                 if (likely(polling))
1299                         vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1300                 else
1301                         __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1302                 ret = 0;
1303         } else
1304                 ret = -1;
1305         desc->opts2 = 0;
1306         return ret;
1307 }
1308
1309 #else /* !CONFIG_R8169_VLAN */
1310
1311 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1312                                       struct sk_buff *skb)
1313 {
1314         return 0;
1315 }
1316
1317 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1318                                struct sk_buff *skb, int polling)
1319 {
1320         return -1;
1321 }
1322
1323 #endif
1324
1325 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1326 {
1327         struct rtl8169_private *tp = netdev_priv(dev);
1328         void __iomem *ioaddr = tp->mmio_addr;
1329         u32 status;
1330
1331         cmd->supported =
1332                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1333         cmd->port = PORT_FIBRE;
1334         cmd->transceiver = XCVR_INTERNAL;
1335
1336         status = RTL_R32(TBICSR);
1337         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1338         cmd->autoneg = !!(status & TBINwEnable);
1339
1340         cmd->speed = SPEED_1000;
1341         cmd->duplex = DUPLEX_FULL; /* Always set */
1342
1343         return 0;
1344 }
1345
1346 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1347 {
1348         struct rtl8169_private *tp = netdev_priv(dev);
1349
1350         return mii_ethtool_gset(&tp->mii, cmd);
1351 }
1352
1353 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1354 {
1355         struct rtl8169_private *tp = netdev_priv(dev);
1356         unsigned long flags;
1357         int rc;
1358
1359         spin_lock_irqsave(&tp->lock, flags);
1360
1361         rc = tp->get_settings(dev, cmd);
1362
1363         spin_unlock_irqrestore(&tp->lock, flags);
1364         return rc;
1365 }
1366
1367 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1368                              void *p)
1369 {
1370         struct rtl8169_private *tp = netdev_priv(dev);
1371         unsigned long flags;
1372
1373         if (regs->len > R8169_REGS_SIZE)
1374                 regs->len = R8169_REGS_SIZE;
1375
1376         spin_lock_irqsave(&tp->lock, flags);
1377         memcpy_fromio(p, tp->mmio_addr, regs->len);
1378         spin_unlock_irqrestore(&tp->lock, flags);
1379 }
1380
1381 static u32 rtl8169_get_msglevel(struct net_device *dev)
1382 {
1383         struct rtl8169_private *tp = netdev_priv(dev);
1384
1385         return tp->msg_enable;
1386 }
1387
1388 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1389 {
1390         struct rtl8169_private *tp = netdev_priv(dev);
1391
1392         tp->msg_enable = value;
1393 }
1394
1395 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1396         "tx_packets",
1397         "rx_packets",
1398         "tx_errors",
1399         "rx_errors",
1400         "rx_missed",
1401         "align_errors",
1402         "tx_single_collisions",
1403         "tx_multi_collisions",
1404         "unicast",
1405         "broadcast",
1406         "multicast",
1407         "tx_aborted",
1408         "tx_underrun",
1409 };
1410
1411 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1412 {
1413         switch (sset) {
1414         case ETH_SS_STATS:
1415                 return ARRAY_SIZE(rtl8169_gstrings);
1416         default:
1417                 return -EOPNOTSUPP;
1418         }
1419 }
1420
1421 static void rtl8169_update_counters(struct net_device *dev)
1422 {
1423         struct rtl8169_private *tp = netdev_priv(dev);
1424         void __iomem *ioaddr = tp->mmio_addr;
1425         struct rtl8169_counters *counters;
1426         dma_addr_t paddr;
1427         u32 cmd;
1428         int wait = 1000;
1429         struct device *d = &tp->pci_dev->dev;
1430
1431         /*
1432          * Some chips are unable to dump tally counters when the receiver
1433          * is disabled.
1434          */
1435         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1436                 return;
1437
1438         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1439         if (!counters)
1440                 return;
1441
1442         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1443         cmd = (u64)paddr & DMA_BIT_MASK(32);
1444         RTL_W32(CounterAddrLow, cmd);
1445         RTL_W32(CounterAddrLow, cmd | CounterDump);
1446
1447         while (wait--) {
1448                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1449                         /* copy updated counters */
1450                         memcpy(&tp->counters, counters, sizeof(*counters));
1451                         break;
1452                 }
1453                 udelay(10);
1454         }
1455
1456         RTL_W32(CounterAddrLow, 0);
1457         RTL_W32(CounterAddrHigh, 0);
1458
1459         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1460 }
1461
1462 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1463                                       struct ethtool_stats *stats, u64 *data)
1464 {
1465         struct rtl8169_private *tp = netdev_priv(dev);
1466
1467         ASSERT_RTNL();
1468
1469         rtl8169_update_counters(dev);
1470
1471         data[0] = le64_to_cpu(tp->counters.tx_packets);
1472         data[1] = le64_to_cpu(tp->counters.rx_packets);
1473         data[2] = le64_to_cpu(tp->counters.tx_errors);
1474         data[3] = le32_to_cpu(tp->counters.rx_errors);
1475         data[4] = le16_to_cpu(tp->counters.rx_missed);
1476         data[5] = le16_to_cpu(tp->counters.align_errors);
1477         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1478         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1479         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1480         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1481         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1482         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1483         data[12] = le16_to_cpu(tp->counters.tx_underun);
1484 }
1485
1486 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1487 {
1488         switch(stringset) {
1489         case ETH_SS_STATS:
1490                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1491                 break;
1492         }
1493 }
1494
1495 static const struct ethtool_ops rtl8169_ethtool_ops = {
1496         .get_drvinfo            = rtl8169_get_drvinfo,
1497         .get_regs_len           = rtl8169_get_regs_len,
1498         .get_link               = ethtool_op_get_link,
1499         .get_settings           = rtl8169_get_settings,
1500         .set_settings           = rtl8169_set_settings,
1501         .get_msglevel           = rtl8169_get_msglevel,
1502         .set_msglevel           = rtl8169_set_msglevel,
1503         .get_rx_csum            = rtl8169_get_rx_csum,
1504         .set_rx_csum            = rtl8169_set_rx_csum,
1505         .set_tx_csum            = ethtool_op_set_tx_csum,
1506         .set_sg                 = ethtool_op_set_sg,
1507         .set_tso                = ethtool_op_set_tso,
1508         .get_regs               = rtl8169_get_regs,
1509         .get_wol                = rtl8169_get_wol,
1510         .set_wol                = rtl8169_set_wol,
1511         .get_strings            = rtl8169_get_strings,
1512         .get_sset_count         = rtl8169_get_sset_count,
1513         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1514 };
1515
1516 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1517                                     void __iomem *ioaddr)
1518 {
1519         /*
1520          * The driver currently handles the 8168Bf and the 8168Be identically
1521          * but they can be identified more specifically through the test below
1522          * if needed:
1523          *
1524          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1525          *
1526          * Same thing for the 8101Eb and the 8101Ec:
1527          *
1528          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1529          */
1530         static const struct {
1531                 u32 mask;
1532                 u32 val;
1533                 int mac_version;
1534         } mac_info[] = {
1535                 /* 8168D family. */
1536                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1537                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1538                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1539
1540                 /* 8168DP family. */
1541                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1542                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1543
1544                 /* 8168C family. */
1545                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1546                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1547                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1548                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1549                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1550                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1551                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1552                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1553                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1554
1555                 /* 8168B family. */
1556                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1557                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1558                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1559                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1560
1561                 /* 8101 family. */
1562                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1563                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1564                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1565                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1566                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1567                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1568                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1569                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1570                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1571                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1572                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1573                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1574                 /* FIXME: where did these entries come from ? -- FR */
1575                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1576                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1577
1578                 /* 8110 family. */
1579                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1580                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1581                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1582                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1583                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1584                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1585
1586                 /* Catch-all */
1587                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1588         }, *p = mac_info;
1589         u32 reg;
1590
1591         reg = RTL_R32(TxConfig);
1592         while ((reg & p->mask) != p->val)
1593                 p++;
1594         tp->mac_version = p->mac_version;
1595 }
1596
1597 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1598 {
1599         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1600 }
1601
1602 struct phy_reg {
1603         u16 reg;
1604         u16 val;
1605 };
1606
1607 static void rtl_writephy_batch(struct rtl8169_private *tp,
1608                                const struct phy_reg *regs, int len)
1609 {
1610         while (len-- > 0) {
1611                 rtl_writephy(tp, regs->reg, regs->val);
1612                 regs++;
1613         }
1614 }
1615
1616 #define PHY_READ                0x00000000
1617 #define PHY_DATA_OR             0x10000000
1618 #define PHY_DATA_AND            0x20000000
1619 #define PHY_BJMPN               0x30000000
1620 #define PHY_READ_EFUSE          0x40000000
1621 #define PHY_READ_MAC_BYTE       0x50000000
1622 #define PHY_WRITE_MAC_BYTE      0x60000000
1623 #define PHY_CLEAR_READCOUNT     0x70000000
1624 #define PHY_WRITE               0x80000000
1625 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1626 #define PHY_COMP_EQ_SKIPN       0xa0000000
1627 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1628 #define PHY_WRITE_PREVIOUS      0xc0000000
1629 #define PHY_SKIPN               0xd0000000
1630 #define PHY_DELAY_MS            0xe0000000
1631 #define PHY_WRITE_ERI_WORD      0xf0000000
1632
1633 static void
1634 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1635 {
1636         __le32 *phytable = (__le32 *)fw->data;
1637         struct net_device *dev = tp->dev;
1638         size_t index, fw_size = fw->size / sizeof(*phytable);
1639         u32 predata, count;
1640
1641         if (fw->size % sizeof(*phytable)) {
1642                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1643                 return;
1644         }
1645
1646         for (index = 0; index < fw_size; index++) {
1647                 u32 action = le32_to_cpu(phytable[index]);
1648                 u32 regno = (action & 0x0fff0000) >> 16;
1649
1650                 switch(action & 0xf0000000) {
1651                 case PHY_READ:
1652                 case PHY_DATA_OR:
1653                 case PHY_DATA_AND:
1654                 case PHY_READ_EFUSE:
1655                 case PHY_CLEAR_READCOUNT:
1656                 case PHY_WRITE:
1657                 case PHY_WRITE_PREVIOUS:
1658                 case PHY_DELAY_MS:
1659                         break;
1660
1661                 case PHY_BJMPN:
1662                         if (regno > index) {
1663                                 netif_err(tp, probe, tp->dev,
1664                                         "Out of range of firmware\n");
1665                                 return;
1666                         }
1667                         break;
1668                 case PHY_READCOUNT_EQ_SKIP:
1669                         if (index + 2 >= fw_size) {
1670                                 netif_err(tp, probe, tp->dev,
1671                                         "Out of range of firmware\n");
1672                                 return;
1673                         }
1674                         break;
1675                 case PHY_COMP_EQ_SKIPN:
1676                 case PHY_COMP_NEQ_SKIPN:
1677                 case PHY_SKIPN:
1678                         if (index + 1 + regno >= fw_size) {
1679                                 netif_err(tp, probe, tp->dev,
1680                                         "Out of range of firmware\n");
1681                                 return;
1682                         }
1683                         break;
1684
1685                 case PHY_READ_MAC_BYTE:
1686                 case PHY_WRITE_MAC_BYTE:
1687                 case PHY_WRITE_ERI_WORD:
1688                 default:
1689                         netif_err(tp, probe, tp->dev,
1690                                   "Invalid action 0x%08x\n", action);
1691                         return;
1692                 }
1693         }
1694
1695         predata = 0;
1696         count = 0;
1697
1698         for (index = 0; index < fw_size; ) {
1699                 u32 action = le32_to_cpu(phytable[index]);
1700                 u32 data = action & 0x0000ffff;
1701                 u32 regno = (action & 0x0fff0000) >> 16;
1702
1703                 if (!action)
1704                         break;
1705
1706                 switch(action & 0xf0000000) {
1707                 case PHY_READ:
1708                         predata = rtl_readphy(tp, regno);
1709                         count++;
1710                         index++;
1711                         break;
1712                 case PHY_DATA_OR:
1713                         predata |= data;
1714                         index++;
1715                         break;
1716                 case PHY_DATA_AND:
1717                         predata &= data;
1718                         index++;
1719                         break;
1720                 case PHY_BJMPN:
1721                         index -= regno;
1722                         break;
1723                 case PHY_READ_EFUSE:
1724                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1725                         index++;
1726                         break;
1727                 case PHY_CLEAR_READCOUNT:
1728                         count = 0;
1729                         index++;
1730                         break;
1731                 case PHY_WRITE:
1732                         rtl_writephy(tp, regno, data);
1733                         index++;
1734                         break;
1735                 case PHY_READCOUNT_EQ_SKIP:
1736                         if (count == data)
1737                                 index += 2;
1738                         else
1739                                 index += 1;
1740                         break;
1741                 case PHY_COMP_EQ_SKIPN:
1742                         if (predata == data)
1743                                 index += regno;
1744                         index++;
1745                         break;
1746                 case PHY_COMP_NEQ_SKIPN:
1747                         if (predata != data)
1748                                 index += regno;
1749                         index++;
1750                         break;
1751                 case PHY_WRITE_PREVIOUS:
1752                         rtl_writephy(tp, regno, predata);
1753                         index++;
1754                         break;
1755                 case PHY_SKIPN:
1756                         index += regno + 1;
1757                         break;
1758                 case PHY_DELAY_MS:
1759                         mdelay(data);
1760                         index++;
1761                         break;
1762
1763                 case PHY_READ_MAC_BYTE:
1764                 case PHY_WRITE_MAC_BYTE:
1765                 case PHY_WRITE_ERI_WORD:
1766                 default:
1767                         BUG();
1768                 }
1769         }
1770 }
1771
1772 static void rtl_release_firmware(struct rtl8169_private *tp)
1773 {
1774         release_firmware(tp->fw);
1775         tp->fw = NULL;
1776 }
1777
1778 static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1779 {
1780         const struct firmware **fw = &tp->fw;
1781         int rc = !*fw;
1782
1783         if (rc) {
1784                 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1785                 if (rc < 0)
1786                         goto out;
1787         }
1788
1789         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1790         rtl_phy_write_fw(tp, *fw);
1791 out:
1792         return rc;
1793 }
1794
1795 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1796 {
1797         static const struct phy_reg phy_reg_init[] = {
1798                 { 0x1f, 0x0001 },
1799                 { 0x06, 0x006e },
1800                 { 0x08, 0x0708 },
1801                 { 0x15, 0x4000 },
1802                 { 0x18, 0x65c7 },
1803
1804                 { 0x1f, 0x0001 },
1805                 { 0x03, 0x00a1 },
1806                 { 0x02, 0x0008 },
1807                 { 0x01, 0x0120 },
1808                 { 0x00, 0x1000 },
1809                 { 0x04, 0x0800 },
1810                 { 0x04, 0x0000 },
1811
1812                 { 0x03, 0xff41 },
1813                 { 0x02, 0xdf60 },
1814                 { 0x01, 0x0140 },
1815                 { 0x00, 0x0077 },
1816                 { 0x04, 0x7800 },
1817                 { 0x04, 0x7000 },
1818
1819                 { 0x03, 0x802f },
1820                 { 0x02, 0x4f02 },
1821                 { 0x01, 0x0409 },
1822                 { 0x00, 0xf0f9 },
1823                 { 0x04, 0x9800 },
1824                 { 0x04, 0x9000 },
1825
1826                 { 0x03, 0xdf01 },
1827                 { 0x02, 0xdf20 },
1828                 { 0x01, 0xff95 },
1829                 { 0x00, 0xba00 },
1830                 { 0x04, 0xa800 },
1831                 { 0x04, 0xa000 },
1832
1833                 { 0x03, 0xff41 },
1834                 { 0x02, 0xdf20 },
1835                 { 0x01, 0x0140 },
1836                 { 0x00, 0x00bb },
1837                 { 0x04, 0xb800 },
1838                 { 0x04, 0xb000 },
1839
1840                 { 0x03, 0xdf41 },
1841                 { 0x02, 0xdc60 },
1842                 { 0x01, 0x6340 },
1843                 { 0x00, 0x007d },
1844                 { 0x04, 0xd800 },
1845                 { 0x04, 0xd000 },
1846
1847                 { 0x03, 0xdf01 },
1848                 { 0x02, 0xdf20 },
1849                 { 0x01, 0x100a },
1850                 { 0x00, 0xa0ff },
1851                 { 0x04, 0xf800 },
1852                 { 0x04, 0xf000 },
1853
1854                 { 0x1f, 0x0000 },
1855                 { 0x0b, 0x0000 },
1856                 { 0x00, 0x9200 }
1857         };
1858
1859         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1860 }
1861
1862 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1863 {
1864         static const struct phy_reg phy_reg_init[] = {
1865                 { 0x1f, 0x0002 },
1866                 { 0x01, 0x90d0 },
1867                 { 0x1f, 0x0000 }
1868         };
1869
1870         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1871 }
1872
1873 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1874 {
1875         struct pci_dev *pdev = tp->pci_dev;
1876         u16 vendor_id, device_id;
1877
1878         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1879         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1880
1881         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1882                 return;
1883
1884         rtl_writephy(tp, 0x1f, 0x0001);
1885         rtl_writephy(tp, 0x10, 0xf01b);
1886         rtl_writephy(tp, 0x1f, 0x0000);
1887 }
1888
1889 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1890 {
1891         static const struct phy_reg phy_reg_init[] = {
1892                 { 0x1f, 0x0001 },
1893                 { 0x04, 0x0000 },
1894                 { 0x03, 0x00a1 },
1895                 { 0x02, 0x0008 },
1896                 { 0x01, 0x0120 },
1897                 { 0x00, 0x1000 },
1898                 { 0x04, 0x0800 },
1899                 { 0x04, 0x9000 },
1900                 { 0x03, 0x802f },
1901                 { 0x02, 0x4f02 },
1902                 { 0x01, 0x0409 },
1903                 { 0x00, 0xf099 },
1904                 { 0x04, 0x9800 },
1905                 { 0x04, 0xa000 },
1906                 { 0x03, 0xdf01 },
1907                 { 0x02, 0xdf20 },
1908                 { 0x01, 0xff95 },
1909                 { 0x00, 0xba00 },
1910                 { 0x04, 0xa800 },
1911                 { 0x04, 0xf000 },
1912                 { 0x03, 0xdf01 },
1913                 { 0x02, 0xdf20 },
1914                 { 0x01, 0x101a },
1915                 { 0x00, 0xa0ff },
1916                 { 0x04, 0xf800 },
1917                 { 0x04, 0x0000 },
1918                 { 0x1f, 0x0000 },
1919
1920                 { 0x1f, 0x0001 },
1921                 { 0x10, 0xf41b },
1922                 { 0x14, 0xfb54 },
1923                 { 0x18, 0xf5c7 },
1924                 { 0x1f, 0x0000 },
1925
1926                 { 0x1f, 0x0001 },
1927                 { 0x17, 0x0cc0 },
1928                 { 0x1f, 0x0000 }
1929         };
1930
1931         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1932
1933         rtl8169scd_hw_phy_config_quirk(tp);
1934 }
1935
1936 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
1937 {
1938         static const struct phy_reg phy_reg_init[] = {
1939                 { 0x1f, 0x0001 },
1940                 { 0x04, 0x0000 },
1941                 { 0x03, 0x00a1 },
1942                 { 0x02, 0x0008 },
1943                 { 0x01, 0x0120 },
1944                 { 0x00, 0x1000 },
1945                 { 0x04, 0x0800 },
1946                 { 0x04, 0x9000 },
1947                 { 0x03, 0x802f },
1948                 { 0x02, 0x4f02 },
1949                 { 0x01, 0x0409 },
1950                 { 0x00, 0xf099 },
1951                 { 0x04, 0x9800 },
1952                 { 0x04, 0xa000 },
1953                 { 0x03, 0xdf01 },
1954                 { 0x02, 0xdf20 },
1955                 { 0x01, 0xff95 },
1956                 { 0x00, 0xba00 },
1957                 { 0x04, 0xa800 },
1958                 { 0x04, 0xf000 },
1959                 { 0x03, 0xdf01 },
1960                 { 0x02, 0xdf20 },
1961                 { 0x01, 0x101a },
1962                 { 0x00, 0xa0ff },
1963                 { 0x04, 0xf800 },
1964                 { 0x04, 0x0000 },
1965                 { 0x1f, 0x0000 },
1966
1967                 { 0x1f, 0x0001 },
1968                 { 0x0b, 0x8480 },
1969                 { 0x1f, 0x0000 },
1970
1971                 { 0x1f, 0x0001 },
1972                 { 0x18, 0x67c7 },
1973                 { 0x04, 0x2000 },
1974                 { 0x03, 0x002f },
1975                 { 0x02, 0x4360 },
1976                 { 0x01, 0x0109 },
1977                 { 0x00, 0x3022 },
1978                 { 0x04, 0x2800 },
1979                 { 0x1f, 0x0000 },
1980
1981                 { 0x1f, 0x0001 },
1982                 { 0x17, 0x0cc0 },
1983                 { 0x1f, 0x0000 }
1984         };
1985
1986         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1987 }
1988
1989 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
1990 {
1991         static const struct phy_reg phy_reg_init[] = {
1992                 { 0x10, 0xf41b },
1993                 { 0x1f, 0x0000 }
1994         };
1995
1996         rtl_writephy(tp, 0x1f, 0x0001);
1997         rtl_patchphy(tp, 0x16, 1 << 0);
1998
1999         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2000 }
2001
2002 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2003 {
2004         static const struct phy_reg phy_reg_init[] = {
2005                 { 0x1f, 0x0001 },
2006                 { 0x10, 0xf41b },
2007                 { 0x1f, 0x0000 }
2008         };
2009
2010         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2011 }
2012
2013 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2014 {
2015         static const struct phy_reg phy_reg_init[] = {
2016                 { 0x1f, 0x0000 },
2017                 { 0x1d, 0x0f00 },
2018                 { 0x1f, 0x0002 },
2019                 { 0x0c, 0x1ec8 },
2020                 { 0x1f, 0x0000 }
2021         };
2022
2023         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2024 }
2025
2026 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2027 {
2028         static const struct phy_reg phy_reg_init[] = {
2029                 { 0x1f, 0x0001 },
2030                 { 0x1d, 0x3d98 },
2031                 { 0x1f, 0x0000 }
2032         };
2033
2034         rtl_writephy(tp, 0x1f, 0x0000);
2035         rtl_patchphy(tp, 0x14, 1 << 5);
2036         rtl_patchphy(tp, 0x0d, 1 << 5);
2037
2038         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2039 }
2040
2041 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2042 {
2043         static const struct phy_reg phy_reg_init[] = {
2044                 { 0x1f, 0x0001 },
2045                 { 0x12, 0x2300 },
2046                 { 0x1f, 0x0002 },
2047                 { 0x00, 0x88d4 },
2048                 { 0x01, 0x82b1 },
2049                 { 0x03, 0x7002 },
2050                 { 0x08, 0x9e30 },
2051                 { 0x09, 0x01f0 },
2052                 { 0x0a, 0x5500 },
2053                 { 0x0c, 0x00c8 },
2054                 { 0x1f, 0x0003 },
2055                 { 0x12, 0xc096 },
2056                 { 0x16, 0x000a },
2057                 { 0x1f, 0x0000 },
2058                 { 0x1f, 0x0000 },
2059                 { 0x09, 0x2000 },
2060                 { 0x09, 0x0000 }
2061         };
2062
2063         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2064
2065         rtl_patchphy(tp, 0x14, 1 << 5);
2066         rtl_patchphy(tp, 0x0d, 1 << 5);
2067         rtl_writephy(tp, 0x1f, 0x0000);
2068 }
2069
2070 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2071 {
2072         static const struct phy_reg phy_reg_init[] = {
2073                 { 0x1f, 0x0001 },
2074                 { 0x12, 0x2300 },
2075                 { 0x03, 0x802f },
2076                 { 0x02, 0x4f02 },
2077                 { 0x01, 0x0409 },
2078                 { 0x00, 0xf099 },
2079                 { 0x04, 0x9800 },
2080                 { 0x04, 0x9000 },
2081                 { 0x1d, 0x3d98 },
2082                 { 0x1f, 0x0002 },
2083                 { 0x0c, 0x7eb8 },
2084                 { 0x06, 0x0761 },
2085                 { 0x1f, 0x0003 },
2086                 { 0x16, 0x0f0a },
2087                 { 0x1f, 0x0000 }
2088         };
2089
2090         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2091
2092         rtl_patchphy(tp, 0x16, 1 << 0);
2093         rtl_patchphy(tp, 0x14, 1 << 5);
2094         rtl_patchphy(tp, 0x0d, 1 << 5);
2095         rtl_writephy(tp, 0x1f, 0x0000);
2096 }
2097
2098 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2099 {
2100         static const struct phy_reg phy_reg_init[] = {
2101                 { 0x1f, 0x0001 },
2102                 { 0x12, 0x2300 },
2103                 { 0x1d, 0x3d98 },
2104                 { 0x1f, 0x0002 },
2105                 { 0x0c, 0x7eb8 },
2106                 { 0x06, 0x5461 },
2107                 { 0x1f, 0x0003 },
2108                 { 0x16, 0x0f0a },
2109                 { 0x1f, 0x0000 }
2110         };
2111
2112         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2113
2114         rtl_patchphy(tp, 0x16, 1 << 0);
2115         rtl_patchphy(tp, 0x14, 1 << 5);
2116         rtl_patchphy(tp, 0x0d, 1 << 5);
2117         rtl_writephy(tp, 0x1f, 0x0000);
2118 }
2119
2120 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2121 {
2122         rtl8168c_3_hw_phy_config(tp);
2123 }
2124
2125 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2126 {
2127         static const struct phy_reg phy_reg_init_0[] = {
2128                 /* Channel Estimation */
2129                 { 0x1f, 0x0001 },
2130                 { 0x06, 0x4064 },
2131                 { 0x07, 0x2863 },
2132                 { 0x08, 0x059c },
2133                 { 0x09, 0x26b4 },
2134                 { 0x0a, 0x6a19 },
2135                 { 0x0b, 0xdcc8 },
2136                 { 0x10, 0xf06d },
2137                 { 0x14, 0x7f68 },
2138                 { 0x18, 0x7fd9 },
2139                 { 0x1c, 0xf0ff },
2140                 { 0x1d, 0x3d9c },
2141                 { 0x1f, 0x0003 },
2142                 { 0x12, 0xf49f },
2143                 { 0x13, 0x070b },
2144                 { 0x1a, 0x05ad },
2145                 { 0x14, 0x94c0 },
2146
2147                 /*
2148                  * Tx Error Issue
2149                  * enhance line driver power
2150                  */
2151                 { 0x1f, 0x0002 },
2152                 { 0x06, 0x5561 },
2153                 { 0x1f, 0x0005 },
2154                 { 0x05, 0x8332 },
2155                 { 0x06, 0x5561 },
2156
2157                 /*
2158                  * Can not link to 1Gbps with bad cable
2159                  * Decrease SNR threshold form 21.07dB to 19.04dB
2160                  */
2161                 { 0x1f, 0x0001 },
2162                 { 0x17, 0x0cc0 },
2163
2164                 { 0x1f, 0x0000 },
2165                 { 0x0d, 0xf880 }
2166         };
2167         void __iomem *ioaddr = tp->mmio_addr;
2168
2169         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2170
2171         /*
2172          * Rx Error Issue
2173          * Fine Tune Switching regulator parameter
2174          */
2175         rtl_writephy(tp, 0x1f, 0x0002);
2176         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2177         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2178
2179         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2180                 static const struct phy_reg phy_reg_init[] = {
2181                         { 0x1f, 0x0002 },
2182                         { 0x05, 0x669a },
2183                         { 0x1f, 0x0005 },
2184                         { 0x05, 0x8330 },
2185                         { 0x06, 0x669a },
2186                         { 0x1f, 0x0002 }
2187                 };
2188                 int val;
2189
2190                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2191
2192                 val = rtl_readphy(tp, 0x0d);
2193
2194                 if ((val & 0x00ff) != 0x006c) {
2195                         static const u32 set[] = {
2196                                 0x0065, 0x0066, 0x0067, 0x0068,
2197                                 0x0069, 0x006a, 0x006b, 0x006c
2198                         };
2199                         int i;
2200
2201                         rtl_writephy(tp, 0x1f, 0x0002);
2202
2203                         val &= 0xff00;
2204                         for (i = 0; i < ARRAY_SIZE(set); i++)
2205                                 rtl_writephy(tp, 0x0d, val | set[i]);
2206                 }
2207         } else {
2208                 static const struct phy_reg phy_reg_init[] = {
2209                         { 0x1f, 0x0002 },
2210                         { 0x05, 0x6662 },
2211                         { 0x1f, 0x0005 },
2212                         { 0x05, 0x8330 },
2213                         { 0x06, 0x6662 }
2214                 };
2215
2216                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2217         }
2218
2219         /* RSET couple improve */
2220         rtl_writephy(tp, 0x1f, 0x0002);
2221         rtl_patchphy(tp, 0x0d, 0x0300);
2222         rtl_patchphy(tp, 0x0f, 0x0010);
2223
2224         /* Fine tune PLL performance */
2225         rtl_writephy(tp, 0x1f, 0x0002);
2226         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2227         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2228
2229         rtl_writephy(tp, 0x1f, 0x0005);
2230         rtl_writephy(tp, 0x05, 0x001b);
2231         if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2232             (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
2233                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2234         }
2235
2236         rtl_writephy(tp, 0x1f, 0x0000);
2237 }
2238
2239 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2240 {
2241         static const struct phy_reg phy_reg_init_0[] = {
2242                 /* Channel Estimation */
2243                 { 0x1f, 0x0001 },
2244                 { 0x06, 0x4064 },
2245                 { 0x07, 0x2863 },
2246                 { 0x08, 0x059c },
2247                 { 0x09, 0x26b4 },
2248                 { 0x0a, 0x6a19 },
2249                 { 0x0b, 0xdcc8 },
2250                 { 0x10, 0xf06d },
2251                 { 0x14, 0x7f68 },
2252                 { 0x18, 0x7fd9 },
2253                 { 0x1c, 0xf0ff },
2254                 { 0x1d, 0x3d9c },
2255                 { 0x1f, 0x0003 },
2256                 { 0x12, 0xf49f },
2257                 { 0x13, 0x070b },
2258                 { 0x1a, 0x05ad },
2259                 { 0x14, 0x94c0 },
2260
2261                 /*
2262                  * Tx Error Issue
2263                  * enhance line driver power
2264                  */
2265                 { 0x1f, 0x0002 },
2266                 { 0x06, 0x5561 },
2267                 { 0x1f, 0x0005 },
2268                 { 0x05, 0x8332 },
2269                 { 0x06, 0x5561 },
2270
2271                 /*
2272                  * Can not link to 1Gbps with bad cable
2273                  * Decrease SNR threshold form 21.07dB to 19.04dB
2274                  */
2275                 { 0x1f, 0x0001 },
2276                 { 0x17, 0x0cc0 },
2277
2278                 { 0x1f, 0x0000 },
2279                 { 0x0d, 0xf880 }
2280         };
2281         void __iomem *ioaddr = tp->mmio_addr;
2282
2283         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2284
2285         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2286                 static const struct phy_reg phy_reg_init[] = {
2287                         { 0x1f, 0x0002 },
2288                         { 0x05, 0x669a },
2289                         { 0x1f, 0x0005 },
2290                         { 0x05, 0x8330 },
2291                         { 0x06, 0x669a },
2292
2293                         { 0x1f, 0x0002 }
2294                 };
2295                 int val;
2296
2297                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2298
2299                 val = rtl_readphy(tp, 0x0d);
2300                 if ((val & 0x00ff) != 0x006c) {
2301                         static const u32 set[] = {
2302                                 0x0065, 0x0066, 0x0067, 0x0068,
2303                                 0x0069, 0x006a, 0x006b, 0x006c
2304                         };
2305                         int i;
2306
2307                         rtl_writephy(tp, 0x1f, 0x0002);
2308
2309                         val &= 0xff00;
2310                         for (i = 0; i < ARRAY_SIZE(set); i++)
2311                                 rtl_writephy(tp, 0x0d, val | set[i]);
2312                 }
2313         } else {
2314                 static const struct phy_reg phy_reg_init[] = {
2315                         { 0x1f, 0x0002 },
2316                         { 0x05, 0x2642 },
2317                         { 0x1f, 0x0005 },
2318                         { 0x05, 0x8330 },
2319                         { 0x06, 0x2642 }
2320                 };
2321
2322                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2323         }
2324
2325         /* Fine tune PLL performance */
2326         rtl_writephy(tp, 0x1f, 0x0002);
2327         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2328         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2329
2330         /* Switching regulator Slew rate */
2331         rtl_writephy(tp, 0x1f, 0x0002);
2332         rtl_patchphy(tp, 0x0f, 0x0017);
2333
2334         rtl_writephy(tp, 0x1f, 0x0005);
2335         rtl_writephy(tp, 0x05, 0x001b);
2336         if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2337             (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
2338                 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2339         }
2340
2341         rtl_writephy(tp, 0x1f, 0x0000);
2342 }
2343
2344 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2345 {
2346         static const struct phy_reg phy_reg_init[] = {
2347                 { 0x1f, 0x0002 },
2348                 { 0x10, 0x0008 },
2349                 { 0x0d, 0x006c },
2350
2351                 { 0x1f, 0x0000 },
2352                 { 0x0d, 0xf880 },
2353
2354                 { 0x1f, 0x0001 },
2355                 { 0x17, 0x0cc0 },
2356
2357                 { 0x1f, 0x0001 },
2358                 { 0x0b, 0xa4d8 },
2359                 { 0x09, 0x281c },
2360                 { 0x07, 0x2883 },
2361                 { 0x0a, 0x6b35 },
2362                 { 0x1d, 0x3da4 },
2363                 { 0x1c, 0xeffd },
2364                 { 0x14, 0x7f52 },
2365                 { 0x18, 0x7fc6 },
2366                 { 0x08, 0x0601 },
2367                 { 0x06, 0x4063 },
2368                 { 0x10, 0xf074 },
2369                 { 0x1f, 0x0003 },
2370                 { 0x13, 0x0789 },
2371                 { 0x12, 0xf4bd },
2372                 { 0x1a, 0x04fd },
2373                 { 0x14, 0x84b0 },
2374                 { 0x1f, 0x0000 },
2375                 { 0x00, 0x9200 },
2376
2377                 { 0x1f, 0x0005 },
2378                 { 0x01, 0x0340 },
2379                 { 0x1f, 0x0001 },
2380                 { 0x04, 0x4000 },
2381                 { 0x03, 0x1d21 },
2382                 { 0x02, 0x0c32 },
2383                 { 0x01, 0x0200 },
2384                 { 0x00, 0x5554 },
2385                 { 0x04, 0x4800 },
2386                 { 0x04, 0x4000 },
2387                 { 0x04, 0xf000 },
2388                 { 0x03, 0xdf01 },
2389                 { 0x02, 0xdf20 },
2390                 { 0x01, 0x101a },
2391                 { 0x00, 0xa0ff },
2392                 { 0x04, 0xf800 },
2393                 { 0x04, 0xf000 },
2394                 { 0x1f, 0x0000 },
2395
2396                 { 0x1f, 0x0007 },
2397                 { 0x1e, 0x0023 },
2398                 { 0x16, 0x0000 },
2399                 { 0x1f, 0x0000 }
2400         };
2401
2402         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2403 }
2404
2405 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2406 {
2407         static const struct phy_reg phy_reg_init[] = {
2408                 { 0x1f, 0x0001 },
2409                 { 0x17, 0x0cc0 },
2410
2411                 { 0x1f, 0x0007 },
2412                 { 0x1e, 0x002d },
2413                 { 0x18, 0x0040 },
2414                 { 0x1f, 0x0000 }
2415         };
2416
2417         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2418         rtl_patchphy(tp, 0x0d, 1 << 5);
2419 }
2420
2421 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2422 {
2423         static const struct phy_reg phy_reg_init[] = {
2424                 { 0x1f, 0x0003 },
2425                 { 0x08, 0x441d },
2426                 { 0x01, 0x9100 },
2427                 { 0x1f, 0x0000 }
2428         };
2429
2430         rtl_writephy(tp, 0x1f, 0x0000);
2431         rtl_patchphy(tp, 0x11, 1 << 12);
2432         rtl_patchphy(tp, 0x19, 1 << 13);
2433         rtl_patchphy(tp, 0x10, 1 << 15);
2434
2435         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2436 }
2437
2438 static void rtl_hw_phy_config(struct net_device *dev)
2439 {
2440         struct rtl8169_private *tp = netdev_priv(dev);
2441
2442         rtl8169_print_mac_version(tp);
2443
2444         switch (tp->mac_version) {
2445         case RTL_GIGA_MAC_VER_01:
2446                 break;
2447         case RTL_GIGA_MAC_VER_02:
2448         case RTL_GIGA_MAC_VER_03:
2449                 rtl8169s_hw_phy_config(tp);
2450                 break;
2451         case RTL_GIGA_MAC_VER_04:
2452                 rtl8169sb_hw_phy_config(tp);
2453                 break;
2454         case RTL_GIGA_MAC_VER_05:
2455                 rtl8169scd_hw_phy_config(tp);
2456                 break;
2457         case RTL_GIGA_MAC_VER_06:
2458                 rtl8169sce_hw_phy_config(tp);
2459                 break;
2460         case RTL_GIGA_MAC_VER_07:
2461         case RTL_GIGA_MAC_VER_08:
2462         case RTL_GIGA_MAC_VER_09:
2463                 rtl8102e_hw_phy_config(tp);
2464                 break;
2465         case RTL_GIGA_MAC_VER_11:
2466                 rtl8168bb_hw_phy_config(tp);
2467                 break;
2468         case RTL_GIGA_MAC_VER_12:
2469                 rtl8168bef_hw_phy_config(tp);
2470                 break;
2471         case RTL_GIGA_MAC_VER_17:
2472                 rtl8168bef_hw_phy_config(tp);
2473                 break;
2474         case RTL_GIGA_MAC_VER_18:
2475                 rtl8168cp_1_hw_phy_config(tp);
2476                 break;
2477         case RTL_GIGA_MAC_VER_19:
2478                 rtl8168c_1_hw_phy_config(tp);
2479                 break;
2480         case RTL_GIGA_MAC_VER_20:
2481                 rtl8168c_2_hw_phy_config(tp);
2482                 break;
2483         case RTL_GIGA_MAC_VER_21:
2484                 rtl8168c_3_hw_phy_config(tp);
2485                 break;
2486         case RTL_GIGA_MAC_VER_22:
2487                 rtl8168c_4_hw_phy_config(tp);
2488                 break;
2489         case RTL_GIGA_MAC_VER_23:
2490         case RTL_GIGA_MAC_VER_24:
2491                 rtl8168cp_2_hw_phy_config(tp);
2492                 break;
2493         case RTL_GIGA_MAC_VER_25:
2494                 rtl8168d_1_hw_phy_config(tp);
2495                 break;
2496         case RTL_GIGA_MAC_VER_26:
2497                 rtl8168d_2_hw_phy_config(tp);
2498                 break;
2499         case RTL_GIGA_MAC_VER_27:
2500                 rtl8168d_3_hw_phy_config(tp);
2501                 break;
2502         case RTL_GIGA_MAC_VER_28:
2503                 rtl8168d_4_hw_phy_config(tp);
2504                 break;
2505
2506         default:
2507                 break;
2508         }
2509 }
2510
2511 static void rtl8169_phy_timer(unsigned long __opaque)
2512 {
2513         struct net_device *dev = (struct net_device *)__opaque;
2514         struct rtl8169_private *tp = netdev_priv(dev);
2515         struct timer_list *timer = &tp->timer;
2516         void __iomem *ioaddr = tp->mmio_addr;
2517         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2518
2519         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2520
2521         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2522                 return;
2523
2524         spin_lock_irq(&tp->lock);
2525
2526         if (tp->phy_reset_pending(tp)) {
2527                 /*
2528                  * A busy loop could burn quite a few cycles on nowadays CPU.
2529                  * Let's delay the execution of the timer for a few ticks.
2530                  */
2531                 timeout = HZ/10;
2532                 goto out_mod_timer;
2533         }
2534
2535         if (tp->link_ok(ioaddr))
2536                 goto out_unlock;
2537
2538         netif_warn(tp, link, dev, "PHY reset until link up\n");
2539
2540         tp->phy_reset_enable(tp);
2541
2542 out_mod_timer:
2543         mod_timer(timer, jiffies + timeout);
2544 out_unlock:
2545         spin_unlock_irq(&tp->lock);
2546 }
2547
2548 static inline void rtl8169_delete_timer(struct net_device *dev)
2549 {
2550         struct rtl8169_private *tp = netdev_priv(dev);
2551         struct timer_list *timer = &tp->timer;
2552
2553         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2554                 return;
2555
2556         del_timer_sync(timer);
2557 }
2558
2559 static inline void rtl8169_request_timer(struct net_device *dev)
2560 {
2561         struct rtl8169_private *tp = netdev_priv(dev);
2562         struct timer_list *timer = &tp->timer;
2563
2564         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2565                 return;
2566
2567         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2568 }
2569
2570 #ifdef CONFIG_NET_POLL_CONTROLLER
2571 /*
2572  * Polling 'interrupt' - used by things like netconsole to send skbs
2573  * without having to re-enable interrupts. It's not called while
2574  * the interrupt routine is executing.
2575  */
2576 static void rtl8169_netpoll(struct net_device *dev)
2577 {
2578         struct rtl8169_private *tp = netdev_priv(dev);
2579         struct pci_dev *pdev = tp->pci_dev;
2580
2581         disable_irq(pdev->irq);
2582         rtl8169_interrupt(pdev->irq, dev);
2583         enable_irq(pdev->irq);
2584 }
2585 #endif
2586
2587 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2588                                   void __iomem *ioaddr)
2589 {
2590         iounmap(ioaddr);
2591         pci_release_regions(pdev);
2592         pci_clear_mwi(pdev);
2593         pci_disable_device(pdev);
2594         free_netdev(dev);
2595 }
2596
2597 static void rtl8169_phy_reset(struct net_device *dev,
2598                               struct rtl8169_private *tp)
2599 {
2600         unsigned int i;
2601
2602         tp->phy_reset_enable(tp);
2603         for (i = 0; i < 100; i++) {
2604                 if (!tp->phy_reset_pending(tp))
2605                         return;
2606                 msleep(1);
2607         }
2608         netif_err(tp, link, dev, "PHY reset failed\n");
2609 }
2610
2611 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2612 {
2613         void __iomem *ioaddr = tp->mmio_addr;
2614
2615         rtl_hw_phy_config(dev);
2616
2617         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2618                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2619                 RTL_W8(0x82, 0x01);
2620         }
2621
2622         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2623
2624         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2625                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2626
2627         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2628                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2629                 RTL_W8(0x82, 0x01);
2630                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2631                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2632         }
2633
2634         rtl8169_phy_reset(dev, tp);
2635
2636         /*
2637          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2638          * only 8101. Don't panic.
2639          */
2640         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2641
2642         if (RTL_R8(PHYstatus) & TBI_Enable)
2643                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2644 }
2645
2646 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2647 {
2648         void __iomem *ioaddr = tp->mmio_addr;
2649         u32 high;
2650         u32 low;
2651
2652         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2653         high = addr[4] | (addr[5] << 8);
2654
2655         spin_lock_irq(&tp->lock);
2656
2657         RTL_W8(Cfg9346, Cfg9346_Unlock);
2658
2659         RTL_W32(MAC4, high);
2660         RTL_R32(MAC4);
2661
2662         RTL_W32(MAC0, low);
2663         RTL_R32(MAC0);
2664
2665         RTL_W8(Cfg9346, Cfg9346_Lock);
2666
2667         spin_unlock_irq(&tp->lock);
2668 }
2669
2670 static int rtl_set_mac_address(struct net_device *dev, void *p)
2671 {
2672         struct rtl8169_private *tp = netdev_priv(dev);
2673         struct sockaddr *addr = p;
2674
2675         if (!is_valid_ether_addr(addr->sa_data))
2676                 return -EADDRNOTAVAIL;
2677
2678         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2679
2680         rtl_rar_set(tp, dev->dev_addr);
2681
2682         return 0;
2683 }
2684
2685 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2686 {
2687         struct rtl8169_private *tp = netdev_priv(dev);
2688         struct mii_ioctl_data *data = if_mii(ifr);
2689
2690         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2691 }
2692
2693 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2694 {
2695         switch (cmd) {
2696         case SIOCGMIIPHY:
2697                 data->phy_id = 32; /* Internal PHY */
2698                 return 0;
2699
2700         case SIOCGMIIREG:
2701                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2702                 return 0;
2703
2704         case SIOCSMIIREG:
2705                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2706                 return 0;
2707         }
2708         return -EOPNOTSUPP;
2709 }
2710
2711 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2712 {
2713         return -EOPNOTSUPP;
2714 }
2715
2716 static const struct rtl_cfg_info {
2717         void (*hw_start)(struct net_device *);
2718         unsigned int region;
2719         unsigned int align;
2720         u16 intr_event;
2721         u16 napi_event;
2722         unsigned features;
2723         u8 default_ver;
2724 } rtl_cfg_infos [] = {
2725         [RTL_CFG_0] = {
2726                 .hw_start       = rtl_hw_start_8169,
2727                 .region         = 1,
2728                 .align          = 0,
2729                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2730                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2731                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2732                 .features       = RTL_FEATURE_GMII,
2733                 .default_ver    = RTL_GIGA_MAC_VER_01,
2734         },
2735         [RTL_CFG_1] = {
2736                 .hw_start       = rtl_hw_start_8168,
2737                 .region         = 2,
2738                 .align          = 8,
2739                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2740                                   TxErr | TxOK | RxOK | RxErr,
2741                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2742                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2743                 .default_ver    = RTL_GIGA_MAC_VER_11,
2744         },
2745         [RTL_CFG_2] = {
2746                 .hw_start       = rtl_hw_start_8101,
2747                 .region         = 2,
2748                 .align          = 8,
2749                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2750                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2751                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2752                 .features       = RTL_FEATURE_MSI,
2753                 .default_ver    = RTL_GIGA_MAC_VER_13,
2754         }
2755 };
2756
2757 /* Cfg9346_Unlock assumed. */
2758 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2759                             const struct rtl_cfg_info *cfg)
2760 {
2761         unsigned msi = 0;
2762         u8 cfg2;
2763
2764         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2765         if (cfg->features & RTL_FEATURE_MSI) {
2766                 if (pci_enable_msi(pdev)) {
2767                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2768                 } else {
2769                         cfg2 |= MSIEnable;
2770                         msi = RTL_FEATURE_MSI;
2771                 }
2772         }
2773         RTL_W8(Config2, cfg2);
2774         return msi;
2775 }
2776
2777 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2778 {
2779         if (tp->features & RTL_FEATURE_MSI) {
2780                 pci_disable_msi(pdev);
2781                 tp->features &= ~RTL_FEATURE_MSI;
2782         }
2783 }
2784
2785 static const struct net_device_ops rtl8169_netdev_ops = {
2786         .ndo_open               = rtl8169_open,
2787         .ndo_stop               = rtl8169_close,
2788         .ndo_get_stats          = rtl8169_get_stats,
2789         .ndo_start_xmit         = rtl8169_start_xmit,
2790         .ndo_tx_timeout         = rtl8169_tx_timeout,
2791         .ndo_validate_addr      = eth_validate_addr,
2792         .ndo_change_mtu         = rtl8169_change_mtu,
2793         .ndo_set_mac_address    = rtl_set_mac_address,
2794         .ndo_do_ioctl           = rtl8169_ioctl,
2795         .ndo_set_multicast_list = rtl_set_rx_mode,
2796 #ifdef CONFIG_R8169_VLAN
2797         .ndo_vlan_rx_register   = rtl8169_vlan_rx_register,
2798 #endif
2799 #ifdef CONFIG_NET_POLL_CONTROLLER
2800         .ndo_poll_controller    = rtl8169_netpoll,
2801 #endif
2802
2803 };
2804
2805 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2806 {
2807         struct mdio_ops *ops = &tp->mdio_ops;
2808
2809         switch (tp->mac_version) {
2810         case RTL_GIGA_MAC_VER_27:
2811                 ops->write      = r8168dp_1_mdio_write;
2812                 ops->read       = r8168dp_1_mdio_read;
2813                 break;
2814         case RTL_GIGA_MAC_VER_28:
2815                 ops->write      = r8168dp_2_mdio_write;
2816                 ops->read       = r8168dp_2_mdio_read;
2817                 break;
2818         default:
2819                 ops->write      = r8169_mdio_write;
2820                 ops->read       = r8169_mdio_read;
2821                 break;
2822         }
2823 }
2824
2825 static void r810x_phy_power_down(struct rtl8169_private *tp)
2826 {
2827         rtl_writephy(tp, 0x1f, 0x0000);
2828         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2829 }
2830
2831 static void r810x_phy_power_up(struct rtl8169_private *tp)
2832 {
2833         rtl_writephy(tp, 0x1f, 0x0000);
2834         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2835 }
2836
2837 static void r810x_pll_power_down(struct rtl8169_private *tp)
2838 {
2839         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2840                 rtl_writephy(tp, 0x1f, 0x0000);
2841                 rtl_writephy(tp, MII_BMCR, 0x0000);
2842                 return;
2843         }
2844
2845         r810x_phy_power_down(tp);
2846 }
2847
2848 static void r810x_pll_power_up(struct rtl8169_private *tp)
2849 {
2850         r810x_phy_power_up(tp);
2851 }
2852
2853 static void r8168_phy_power_up(struct rtl8169_private *tp)
2854 {
2855         rtl_writephy(tp, 0x1f, 0x0000);
2856         rtl_writephy(tp, 0x0e, 0x0000);
2857         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2858 }
2859
2860 static void r8168_phy_power_down(struct rtl8169_private *tp)
2861 {
2862         rtl_writephy(tp, 0x1f, 0x0000);
2863         rtl_writephy(tp, 0x0e, 0x0200);
2864         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2865 }
2866
2867 static void r8168_pll_power_down(struct rtl8169_private *tp)
2868 {
2869         void __iomem *ioaddr = tp->mmio_addr;
2870
2871         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2872                 return;
2873
2874         if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2875              (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2876             (RTL_R16(CPlusCmd) & ASF)) {
2877                 return;
2878         }
2879
2880         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2881                 rtl_writephy(tp, 0x1f, 0x0000);
2882                 rtl_writephy(tp, MII_BMCR, 0x0000);
2883
2884                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2885                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2886                 return;
2887         }
2888
2889         r8168_phy_power_down(tp);
2890
2891         switch (tp->mac_version) {
2892         case RTL_GIGA_MAC_VER_25:
2893         case RTL_GIGA_MAC_VER_26:
2894                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2895                 break;
2896         }
2897 }
2898
2899 static void r8168_pll_power_up(struct rtl8169_private *tp)
2900 {
2901         void __iomem *ioaddr = tp->mmio_addr;
2902
2903         if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2904                 return;
2905
2906         switch (tp->mac_version) {
2907         case RTL_GIGA_MAC_VER_25:
2908         case RTL_GIGA_MAC_VER_26:
2909                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2910                 break;
2911         }
2912
2913         r8168_phy_power_up(tp);
2914 }
2915
2916 static void rtl_pll_power_op(struct rtl8169_private *tp,
2917                              void (*op)(struct rtl8169_private *))
2918 {
2919         if (op)
2920                 op(tp);
2921 }
2922
2923 static void rtl_pll_power_down(struct rtl8169_private *tp)
2924 {
2925         rtl_pll_power_op(tp, tp->pll_power_ops.down);
2926 }
2927
2928 static void rtl_pll_power_up(struct rtl8169_private *tp)
2929 {
2930         rtl_pll_power_op(tp, tp->pll_power_ops.up);
2931 }
2932
2933 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2934 {
2935         struct pll_power_ops *ops = &tp->pll_power_ops;
2936
2937         switch (tp->mac_version) {
2938         case RTL_GIGA_MAC_VER_07:
2939         case RTL_GIGA_MAC_VER_08:
2940         case RTL_GIGA_MAC_VER_09:
2941         case RTL_GIGA_MAC_VER_10:
2942         case RTL_GIGA_MAC_VER_16:
2943                 ops->down       = r810x_pll_power_down;
2944                 ops->up         = r810x_pll_power_up;
2945                 break;
2946
2947         case RTL_GIGA_MAC_VER_11:
2948         case RTL_GIGA_MAC_VER_12:
2949         case RTL_GIGA_MAC_VER_17:
2950         case RTL_GIGA_MAC_VER_18:
2951         case RTL_GIGA_MAC_VER_19:
2952         case RTL_GIGA_MAC_VER_20:
2953         case RTL_GIGA_MAC_VER_21:
2954         case RTL_GIGA_MAC_VER_22:
2955         case RTL_GIGA_MAC_VER_23:
2956         case RTL_GIGA_MAC_VER_24:
2957         case RTL_GIGA_MAC_VER_25:
2958         case RTL_GIGA_MAC_VER_26:
2959         case RTL_GIGA_MAC_VER_27:
2960         case RTL_GIGA_MAC_VER_28:
2961                 ops->down       = r8168_pll_power_down;
2962                 ops->up         = r8168_pll_power_up;
2963                 break;
2964
2965         default:
2966                 ops->down       = NULL;
2967                 ops->up         = NULL;
2968                 break;
2969         }
2970 }
2971
2972 static int __devinit
2973 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2974 {
2975         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2976         const unsigned int region = cfg->region;
2977         struct rtl8169_private *tp;
2978         struct mii_if_info *mii;
2979         struct net_device *dev;
2980         void __iomem *ioaddr;
2981         unsigned int i;
2982         int rc;
2983
2984         if (netif_msg_drv(&debug)) {
2985                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2986                        MODULENAME, RTL8169_VERSION);
2987         }
2988
2989         dev = alloc_etherdev(sizeof (*tp));
2990         if (!dev) {
2991                 if (netif_msg_drv(&debug))
2992                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2993                 rc = -ENOMEM;
2994                 goto out;
2995         }
2996
2997         SET_NETDEV_DEV(dev, &pdev->dev);
2998         dev->netdev_ops = &rtl8169_netdev_ops;
2999         tp = netdev_priv(dev);
3000         tp->dev = dev;
3001         tp->pci_dev = pdev;
3002         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3003
3004         mii = &tp->mii;
3005         mii->dev = dev;
3006         mii->mdio_read = rtl_mdio_read;
3007         mii->mdio_write = rtl_mdio_write;
3008         mii->phy_id_mask = 0x1f;
3009         mii->reg_num_mask = 0x1f;
3010         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3011
3012         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3013         rc = pci_enable_device(pdev);
3014         if (rc < 0) {
3015                 netif_err(tp, probe, dev, "enable failure\n");
3016                 goto err_out_free_dev_1;
3017         }
3018
3019         if (pci_set_mwi(pdev) < 0)
3020                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3021
3022         /* make sure PCI base addr 1 is MMIO */
3023         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3024                 netif_err(tp, probe, dev,
3025                           "region #%d not an MMIO resource, aborting\n",
3026                           region);
3027                 rc = -ENODEV;
3028                 goto err_out_mwi_2;
3029         }
3030
3031         /* check for weird/broken PCI region reporting */
3032         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3033                 netif_err(tp, probe, dev,
3034                           "Invalid PCI region size(s), aborting\n");
3035                 rc = -ENODEV;
3036                 goto err_out_mwi_2;
3037         }
3038
3039         rc = pci_request_regions(pdev, MODULENAME);
3040         if (rc < 0) {
3041                 netif_err(tp, probe, dev, "could not request regions\n");
3042                 goto err_out_mwi_2;
3043         }
3044
3045         tp->cp_cmd = PCIMulRW | RxChkSum;
3046
3047         if ((sizeof(dma_addr_t) > 4) &&
3048             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3049                 tp->cp_cmd |= PCIDAC;
3050                 dev->features |= NETIF_F_HIGHDMA;
3051         } else {
3052                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3053                 if (rc < 0) {
3054                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3055                         goto err_out_free_res_3;
3056                 }
3057         }
3058
3059         /* ioremap MMIO region */
3060         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3061         if (!ioaddr) {
3062                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3063                 rc = -EIO;
3064                 goto err_out_free_res_3;
3065         }
3066
3067         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3068         if (!tp->pcie_cap)
3069                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3070
3071         RTL_W16(IntrMask, 0x0000);
3072
3073         /* Soft reset the chip. */
3074         RTL_W8(ChipCmd, CmdReset);
3075
3076         /* Check that the chip has finished the reset. */
3077         for (i = 0; i < 100; i++) {
3078                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3079                         break;
3080                 msleep_interruptible(1);
3081         }
3082
3083         RTL_W16(IntrStatus, 0xffff);
3084
3085         pci_set_master(pdev);
3086
3087         /* Identify chip attached to board */
3088         rtl8169_get_mac_version(tp, ioaddr);
3089
3090         rtl_init_mdio_ops(tp);
3091         rtl_init_pll_power_ops(tp);
3092
3093         /* Use appropriate default if unknown */
3094         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3095                 netif_notice(tp, probe, dev,
3096                              "unknown MAC, using family default\n");
3097                 tp->mac_version = cfg->default_ver;
3098         }
3099
3100         rtl8169_print_mac_version(tp);
3101
3102         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3103                 if (tp->mac_version == rtl_chip_info[i].mac_version)
3104                         break;
3105         }
3106         if (i == ARRAY_SIZE(rtl_chip_info)) {
3107                 dev_err(&pdev->dev,
3108                         "driver bug, MAC version not found in rtl_chip_info\n");
3109                 goto err_out_msi_4;
3110         }
3111         tp->chipset = i;
3112
3113         RTL_W8(Cfg9346, Cfg9346_Unlock);
3114         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3115         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3116         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3117                 tp->features |= RTL_FEATURE_WOL;
3118         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3119                 tp->features |= RTL_FEATURE_WOL;
3120         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3121         RTL_W8(Cfg9346, Cfg9346_Lock);
3122
3123         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3124             (RTL_R8(PHYstatus) & TBI_Enable)) {
3125                 tp->set_speed = rtl8169_set_speed_tbi;
3126                 tp->get_settings = rtl8169_gset_tbi;
3127                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3128                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3129                 tp->link_ok = rtl8169_tbi_link_ok;
3130                 tp->do_ioctl = rtl_tbi_ioctl;
3131
3132                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3133         } else {
3134                 tp->set_speed = rtl8169_set_speed_xmii;
3135                 tp->get_settings = rtl8169_gset_xmii;
3136                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3137                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3138                 tp->link_ok = rtl8169_xmii_link_ok;
3139                 tp->do_ioctl = rtl_xmii_ioctl;
3140         }
3141
3142         spin_lock_init(&tp->lock);
3143
3144         tp->mmio_addr = ioaddr;
3145
3146         /* Get MAC address */
3147         for (i = 0; i < MAC_ADDR_LEN; i++)
3148                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3149         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3150
3151         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3152         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3153         dev->irq = pdev->irq;
3154         dev->base_addr = (unsigned long) ioaddr;
3155
3156         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3157
3158 #ifdef CONFIG_R8169_VLAN
3159         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3160 #endif
3161         dev->features |= NETIF_F_GRO;
3162
3163         tp->intr_mask = 0xffff;
3164         tp->hw_start = cfg->hw_start;
3165         tp->intr_event = cfg->intr_event;
3166         tp->napi_event = cfg->napi_event;
3167
3168         init_timer(&tp->timer);
3169         tp->timer.data = (unsigned long) dev;
3170         tp->timer.function = rtl8169_phy_timer;
3171
3172         rc = register_netdev(dev);
3173         if (rc < 0)
3174                 goto err_out_msi_4;
3175
3176         pci_set_drvdata(pdev, dev);
3177
3178         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3179                    rtl_chip_info[tp->chipset].name,
3180                    dev->base_addr, dev->dev_addr,
3181                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3182
3183         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3184             (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3185                 rtl8168_driver_start(tp);
3186         }
3187
3188         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3189
3190         if (pci_dev_run_wake(pdev))
3191                 pm_runtime_put_noidle(&pdev->dev);
3192
3193 out:
3194         return rc;
3195
3196 err_out_msi_4:
3197         rtl_disable_msi(pdev, tp);
3198         iounmap(ioaddr);
3199 err_out_free_res_3:
3200         pci_release_regions(pdev);
3201 err_out_mwi_2:
3202         pci_clear_mwi(pdev);
3203         pci_disable_device(pdev);
3204 err_out_free_dev_1:
3205         free_netdev(dev);
3206         goto out;
3207 }
3208
3209 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3210 {
3211         struct net_device *dev = pci_get_drvdata(pdev);
3212         struct rtl8169_private *tp = netdev_priv(dev);
3213
3214         if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3215             (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
3216                 rtl8168_driver_stop(tp);
3217         }
3218
3219         cancel_delayed_work_sync(&tp->task);
3220
3221         rtl_release_firmware(tp);
3222
3223         unregister_netdev(dev);
3224
3225         if (pci_dev_run_wake(pdev))
3226                 pm_runtime_get_noresume(&pdev->dev);
3227
3228         /* restore original MAC address */
3229         rtl_rar_set(tp, dev->perm_addr);
3230
3231         rtl_disable_msi(pdev, tp);
3232         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3233         pci_set_drvdata(pdev, NULL);
3234 }
3235
3236 static int rtl8169_open(struct net_device *dev)
3237 {
3238         struct rtl8169_private *tp = netdev_priv(dev);
3239         void __iomem *ioaddr = tp->mmio_addr;
3240         struct pci_dev *pdev = tp->pci_dev;
3241         int retval = -ENOMEM;
3242
3243         pm_runtime_get_sync(&pdev->dev);
3244
3245         /*
3246          * Rx and Tx desscriptors needs 256 bytes alignment.
3247          * dma_alloc_coherent provides more.
3248          */
3249         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3250                                              &tp->TxPhyAddr, GFP_KERNEL);
3251         if (!tp->TxDescArray)
3252                 goto err_pm_runtime_put;
3253
3254         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3255                                              &tp->RxPhyAddr, GFP_KERNEL);
3256         if (!tp->RxDescArray)
3257                 goto err_free_tx_0;
3258
3259         retval = rtl8169_init_ring(dev);
3260         if (retval < 0)
3261                 goto err_free_rx_1;
3262
3263         INIT_DELAYED_WORK(&tp->task, NULL);
3264
3265         smp_mb();
3266
3267         retval = request_irq(dev->irq, rtl8169_interrupt,
3268                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3269                              dev->name, dev);
3270         if (retval < 0)
3271                 goto err_release_ring_2;
3272
3273         napi_enable(&tp->napi);
3274
3275         rtl8169_init_phy(dev, tp);
3276
3277         /*
3278          * Pretend we are using VLANs; This bypasses a nasty bug where
3279          * Interrupts stop flowing on high load on 8110SCd controllers.
3280          */
3281         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3282                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3283
3284         rtl_pll_power_up(tp);
3285
3286         rtl_hw_start(dev);
3287
3288         rtl8169_request_timer(dev);
3289
3290         tp->saved_wolopts = 0;
3291         pm_runtime_put_noidle(&pdev->dev);
3292
3293         rtl8169_check_link_status(dev, tp, ioaddr);
3294 out:
3295         return retval;
3296
3297 err_release_ring_2:
3298         rtl8169_rx_clear(tp);
3299 err_free_rx_1:
3300         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3301                           tp->RxPhyAddr);
3302         tp->RxDescArray = NULL;
3303 err_free_tx_0:
3304         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3305                           tp->TxPhyAddr);
3306         tp->TxDescArray = NULL;
3307 err_pm_runtime_put:
3308         pm_runtime_put_noidle(&pdev->dev);
3309         goto out;
3310 }
3311
3312 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3313 {
3314         void __iomem *ioaddr = tp->mmio_addr;
3315
3316         /* Disable interrupts */
3317         rtl8169_irq_mask_and_ack(ioaddr);
3318
3319         if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3320                 while (RTL_R8(TxPoll) & NPQ)
3321                         udelay(20);
3322
3323         }
3324
3325         /* Reset the chipset */
3326         RTL_W8(ChipCmd, CmdReset);
3327
3328         /* PCI commit */
3329         RTL_R8(ChipCmd);
3330 }
3331
3332 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3333 {
3334         void __iomem *ioaddr = tp->mmio_addr;
3335         u32 cfg = rtl8169_rx_config;
3336
3337         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3338         RTL_W32(RxConfig, cfg);
3339
3340         /* Set DMA burst size and Interframe Gap Time */
3341         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3342                 (InterFrameGap << TxInterFrameGapShift));
3343 }
3344
3345 static void rtl_hw_start(struct net_device *dev)
3346 {
3347         struct rtl8169_private *tp = netdev_priv(dev);
3348         void __iomem *ioaddr = tp->mmio_addr;
3349         unsigned int i;
3350
3351         /* Soft reset the chip. */
3352         RTL_W8(ChipCmd, CmdReset);
3353
3354         /* Check that the chip has finished the reset. */
3355         for (i = 0; i < 100; i++) {
3356                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3357                         break;
3358                 msleep_interruptible(1);
3359         }
3360
3361         tp->hw_start(dev);
3362
3363         netif_start_queue(dev);
3364 }
3365
3366
3367 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3368                                          void __iomem *ioaddr)
3369 {
3370         /*
3371          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3372          * register to be written before TxDescAddrLow to work.
3373          * Switching from MMIO to I/O access fixes the issue as well.
3374          */
3375         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3376         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3377         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3378         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3379 }
3380
3381 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3382 {
3383         u16 cmd;
3384
3385         cmd = RTL_R16(CPlusCmd);
3386         RTL_W16(CPlusCmd, cmd);
3387         return cmd;
3388 }
3389
3390 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3391 {
3392         /* Low hurts. Let's disable the filtering. */
3393         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3394 }
3395
3396 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3397 {
3398         static const struct {
3399                 u32 mac_version;
3400                 u32 clk;
3401                 u32 val;
3402         } cfg2_info [] = {
3403                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3404                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3405                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3406                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3407         }, *p = cfg2_info;
3408         unsigned int i;
3409         u32 clk;
3410
3411         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3412         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3413                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3414                         RTL_W32(0x7c, p->val);
3415                         break;
3416                 }
3417         }
3418 }
3419
3420 static void rtl_hw_start_8169(struct net_device *dev)
3421 {
3422         struct rtl8169_private *tp = netdev_priv(dev);
3423         void __iomem *ioaddr = tp->mmio_addr;
3424         struct pci_dev *pdev = tp->pci_dev;
3425
3426         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3427                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3428                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3429         }
3430
3431         RTL_W8(Cfg9346, Cfg9346_Unlock);
3432         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3433             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3434             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3435             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3436                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3437
3438         RTL_W8(EarlyTxThres, NoEarlyTx);
3439
3440         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3441
3442         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3443             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3444             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3445             (tp->mac_version == RTL_GIGA_MAC_VER_04))
3446                 rtl_set_rx_tx_config_registers(tp);
3447
3448         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3449
3450         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3451             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3452                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3453                         "Bit-3 and bit-14 MUST be 1\n");
3454                 tp->cp_cmd |= (1 << 14);
3455         }
3456
3457         RTL_W16(CPlusCmd, tp->cp_cmd);
3458
3459         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3460
3461         /*
3462          * Undocumented corner. Supposedly:
3463          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3464          */
3465         RTL_W16(IntrMitigate, 0x0000);
3466
3467         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3468
3469         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3470             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3471             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3472             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3473                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3474                 rtl_set_rx_tx_config_registers(tp);
3475         }
3476
3477         RTL_W8(Cfg9346, Cfg9346_Lock);
3478
3479         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3480         RTL_R8(IntrMask);
3481
3482         RTL_W32(RxMissed, 0);
3483
3484         rtl_set_rx_mode(dev);
3485
3486         /* no early-rx interrupts */
3487         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3488
3489         /* Enable all known interrupts by setting the interrupt mask. */
3490         RTL_W16(IntrMask, tp->intr_event);
3491 }
3492
3493 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3494 {
3495         struct net_device *dev = pci_get_drvdata(pdev);
3496         struct rtl8169_private *tp = netdev_priv(dev);
3497         int cap = tp->pcie_cap;
3498
3499         if (cap) {
3500                 u16 ctl;
3501
3502                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3503                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3504                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3505         }
3506 }
3507
3508 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3509 {
3510         u32 csi;
3511
3512         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3513         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3514 }
3515
3516 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3517 {
3518         rtl_csi_access_enable(ioaddr, 0x17000000);
3519 }
3520
3521 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3522 {
3523         rtl_csi_access_enable(ioaddr, 0x27000000);
3524 }
3525
3526 struct ephy_info {
3527         unsigned int offset;
3528         u16 mask;
3529         u16 bits;
3530 };
3531
3532 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3533 {
3534         u16 w;
3535
3536         while (len-- > 0) {
3537                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3538                 rtl_ephy_write(ioaddr, e->offset, w);
3539                 e++;
3540         }
3541 }
3542
3543 static void rtl_disable_clock_request(struct pci_dev *pdev)
3544 {
3545         struct net_device *dev = pci_get_drvdata(pdev);
3546         struct rtl8169_private *tp = netdev_priv(dev);
3547         int cap = tp->pcie_cap;
3548
3549         if (cap) {
3550                 u16 ctl;
3551
3552                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3553                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3554                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3555         }
3556 }
3557
3558 static void rtl_enable_clock_request(struct pci_dev *pdev)
3559 {
3560         struct net_device *dev = pci_get_drvdata(pdev);
3561         struct rtl8169_private *tp = netdev_priv(dev);
3562         int cap = tp->pcie_cap;
3563
3564         if (cap) {
3565                 u16 ctl;
3566
3567                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3568                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3569                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3570         }
3571 }
3572
3573 #define R8168_CPCMD_QUIRK_MASK (\
3574         EnableBist | \
3575         Mac_dbgo_oe | \
3576         Force_half_dup | \
3577         Force_rxflow_en | \
3578         Force_txflow_en | \
3579         Cxpl_dbg_sel | \
3580         ASF | \
3581         PktCntrDisable | \
3582         Mac_dbgo_sel)
3583
3584 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3585 {
3586         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3587
3588         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3589
3590         rtl_tx_performance_tweak(pdev,
3591                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3592 }
3593
3594 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3595 {
3596         rtl_hw_start_8168bb(ioaddr, pdev);
3597
3598         RTL_W8(MaxTxPacketSize, TxPacketMax);
3599
3600         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3601 }
3602
3603 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3604 {
3605         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3606
3607         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3608
3609         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3610
3611         rtl_disable_clock_request(pdev);
3612
3613         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3614 }
3615
3616 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3617 {
3618         static const struct ephy_info e_info_8168cp[] = {
3619                 { 0x01, 0,      0x0001 },
3620                 { 0x02, 0x0800, 0x1000 },
3621                 { 0x03, 0,      0x0042 },
3622                 { 0x06, 0x0080, 0x0000 },
3623                 { 0x07, 0,      0x2000 }
3624         };
3625
3626         rtl_csi_access_enable_2(ioaddr);
3627
3628         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3629
3630         __rtl_hw_start_8168cp(ioaddr, pdev);
3631 }
3632
3633 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3634 {
3635         rtl_csi_access_enable_2(ioaddr);
3636
3637         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3638
3639         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3640
3641         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3642 }
3643
3644 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3645 {
3646         rtl_csi_access_enable_2(ioaddr);
3647
3648         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3649
3650         /* Magic. */
3651         RTL_W8(DBG_REG, 0x20);
3652
3653         RTL_W8(MaxTxPacketSize, TxPacketMax);
3654
3655         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3656
3657         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3658 }
3659
3660 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3661 {
3662         static const struct ephy_info e_info_8168c_1[] = {
3663                 { 0x02, 0x0800, 0x1000 },
3664                 { 0x03, 0,      0x0002 },
3665                 { 0x06, 0x0080, 0x0000 }
3666         };
3667
3668         rtl_csi_access_enable_2(ioaddr);
3669
3670         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3671
3672         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3673
3674         __rtl_hw_start_8168cp(ioaddr, pdev);
3675 }
3676
3677 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3678 {
3679         static const struct ephy_info e_info_8168c_2[] = {
3680                 { 0x01, 0,      0x0001 },
3681                 { 0x03, 0x0400, 0x0220 }
3682         };
3683
3684         rtl_csi_access_enable_2(ioaddr);
3685
3686         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3687
3688         __rtl_hw_start_8168cp(ioaddr, pdev);
3689 }
3690
3691 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3692 {
3693         rtl_hw_start_8168c_2(ioaddr, pdev);
3694 }
3695
3696 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3697 {
3698         rtl_csi_access_enable_2(ioaddr);
3699
3700         __rtl_hw_start_8168cp(ioaddr, pdev);
3701 }
3702
3703 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3704 {
3705         rtl_csi_access_enable_2(ioaddr);
3706
3707         rtl_disable_clock_request(pdev);
3708
3709         RTL_W8(MaxTxPacketSize, TxPacketMax);
3710
3711         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3712
3713         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3714 }
3715
3716 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3717 {
3718         static const struct ephy_info e_info_8168d_4[] = {
3719                 { 0x0b, ~0,     0x48 },
3720                 { 0x19, 0x20,   0x50 },
3721                 { 0x0c, ~0,     0x20 }
3722         };
3723         int i;
3724
3725         rtl_csi_access_enable_1(ioaddr);
3726
3727         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3728
3729         RTL_W8(MaxTxPacketSize, TxPacketMax);
3730
3731         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3732                 const struct ephy_info *e = e_info_8168d_4 + i;
3733                 u16 w;
3734
3735                 w = rtl_ephy_read(ioaddr, e->offset);
3736                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3737         }
3738
3739         rtl_enable_clock_request(pdev);
3740 }
3741
3742 static void rtl_hw_start_8168(struct net_device *dev)
3743 {
3744         struct rtl8169_private *tp = netdev_priv(dev);
3745         void __iomem *ioaddr = tp->mmio_addr;
3746         struct pci_dev *pdev = tp->pci_dev;
3747
3748         RTL_W8(Cfg9346, Cfg9346_Unlock);
3749
3750         RTL_W8(MaxTxPacketSize, TxPacketMax);
3751
3752         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3753
3754         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3755
3756         RTL_W16(CPlusCmd, tp->cp_cmd);
3757
3758         RTL_W16(IntrMitigate, 0x5151);
3759
3760         /* Work around for RxFIFO overflow. */
3761         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3762             tp->mac_version == RTL_GIGA_MAC_VER_22) {
3763                 tp->intr_event |= RxFIFOOver | PCSTimeout;
3764                 tp->intr_event &= ~RxOverflow;
3765         }
3766
3767         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3768
3769         rtl_set_rx_mode(dev);
3770
3771         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3772                 (InterFrameGap << TxInterFrameGapShift));
3773
3774         RTL_R8(IntrMask);
3775
3776         switch (tp->mac_version) {
3777         case RTL_GIGA_MAC_VER_11:
3778                 rtl_hw_start_8168bb(ioaddr, pdev);
3779         break;
3780
3781         case RTL_GIGA_MAC_VER_12:
3782         case RTL_GIGA_MAC_VER_17:
3783                 rtl_hw_start_8168bef(ioaddr, pdev);
3784         break;
3785
3786         case RTL_GIGA_MAC_VER_18:
3787                 rtl_hw_start_8168cp_1(ioaddr, pdev);
3788         break;
3789
3790         case RTL_GIGA_MAC_VER_19:
3791                 rtl_hw_start_8168c_1(ioaddr, pdev);
3792         break;
3793
3794         case RTL_GIGA_MAC_VER_20:
3795                 rtl_hw_start_8168c_2(ioaddr, pdev);
3796         break;
3797
3798         case RTL_GIGA_MAC_VER_21:
3799                 rtl_hw_start_8168c_3(ioaddr, pdev);
3800         break;
3801
3802         case RTL_GIGA_MAC_VER_22:
3803                 rtl_hw_start_8168c_4(ioaddr, pdev);
3804         break;
3805
3806         case RTL_GIGA_MAC_VER_23:
3807                 rtl_hw_start_8168cp_2(ioaddr, pdev);
3808         break;
3809
3810         case RTL_GIGA_MAC_VER_24:
3811                 rtl_hw_start_8168cp_3(ioaddr, pdev);
3812         break;
3813
3814         case RTL_GIGA_MAC_VER_25:
3815         case RTL_GIGA_MAC_VER_26:
3816         case RTL_GIGA_MAC_VER_27:
3817                 rtl_hw_start_8168d(ioaddr, pdev);
3818         break;
3819
3820         case RTL_GIGA_MAC_VER_28:
3821                 rtl_hw_start_8168d_4(ioaddr, pdev);
3822         break;
3823
3824         default:
3825                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3826                         dev->name, tp->mac_version);
3827         break;
3828         }
3829
3830         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3831
3832         RTL_W8(Cfg9346, Cfg9346_Lock);
3833
3834         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3835
3836         RTL_W16(IntrMask, tp->intr_event);
3837 }
3838
3839 #define R810X_CPCMD_QUIRK_MASK (\
3840         EnableBist | \
3841         Mac_dbgo_oe | \
3842         Force_half_dup | \
3843         Force_rxflow_en | \
3844         Force_txflow_en | \
3845         Cxpl_dbg_sel | \
3846         ASF | \
3847         PktCntrDisable | \
3848         PCIDAC | \
3849         PCIMulRW)
3850
3851 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3852 {
3853         static const struct ephy_info e_info_8102e_1[] = {
3854                 { 0x01, 0, 0x6e65 },
3855                 { 0x02, 0, 0x091f },
3856                 { 0x03, 0, 0xc2f9 },
3857                 { 0x06, 0, 0xafb5 },
3858                 { 0x07, 0, 0x0e00 },
3859                 { 0x19, 0, 0xec80 },
3860                 { 0x01, 0, 0x2e65 },
3861                 { 0x01, 0, 0x6e65 }
3862         };
3863         u8 cfg1;
3864
3865         rtl_csi_access_enable_2(ioaddr);
3866
3867         RTL_W8(DBG_REG, FIX_NAK_1);
3868
3869         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3870
3871         RTL_W8(Config1,
3872                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3873         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3874
3875         cfg1 = RTL_R8(Config1);
3876         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3877                 RTL_W8(Config1, cfg1 & ~LEDS0);
3878
3879         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3880
3881         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3882 }
3883
3884 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3885 {
3886         rtl_csi_access_enable_2(ioaddr);
3887
3888         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3889
3890         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3891         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3892
3893         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3894 }
3895
3896 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3897 {
3898         rtl_hw_start_8102e_2(ioaddr, pdev);
3899
3900         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3901 }
3902
3903 static void rtl_hw_start_8101(struct net_device *dev)
3904 {
3905         struct rtl8169_private *tp = netdev_priv(dev);
3906         void __iomem *ioaddr = tp->mmio_addr;
3907         struct pci_dev *pdev = tp->pci_dev;
3908
3909         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3910             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3911                 int cap = tp->pcie_cap;
3912
3913                 if (cap) {
3914                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3915                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
3916                 }
3917         }
3918
3919         switch (tp->mac_version) {
3920         case RTL_GIGA_MAC_VER_07:
3921                 rtl_hw_start_8102e_1(ioaddr, pdev);
3922                 break;
3923
3924         case RTL_GIGA_MAC_VER_08:
3925                 rtl_hw_start_8102e_3(ioaddr, pdev);
3926                 break;
3927
3928         case RTL_GIGA_MAC_VER_09:
3929                 rtl_hw_start_8102e_2(ioaddr, pdev);
3930                 break;
3931         }
3932
3933         RTL_W8(Cfg9346, Cfg9346_Unlock);
3934
3935         RTL_W8(MaxTxPacketSize, TxPacketMax);
3936
3937         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3938
3939         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3940
3941         RTL_W16(CPlusCmd, tp->cp_cmd);
3942
3943         RTL_W16(IntrMitigate, 0x0000);
3944
3945         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3946
3947         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3948         rtl_set_rx_tx_config_registers(tp);
3949
3950         RTL_W8(Cfg9346, Cfg9346_Lock);
3951
3952         RTL_R8(IntrMask);
3953
3954         rtl_set_rx_mode(dev);
3955
3956         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3957
3958         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3959
3960         RTL_W16(IntrMask, tp->intr_event);
3961 }
3962
3963 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3964 {
3965         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3966                 return -EINVAL;
3967
3968         dev->mtu = new_mtu;
3969         return 0;
3970 }
3971
3972 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3973 {
3974         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3975         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3976 }
3977
3978 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3979                                      void **data_buff, struct RxDesc *desc)
3980 {
3981         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
3982                          DMA_FROM_DEVICE);
3983
3984         kfree(*data_buff);
3985         *data_buff = NULL;
3986         rtl8169_make_unusable_by_asic(desc);
3987 }
3988
3989 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3990 {
3991         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3992
3993         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3994 }
3995
3996 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3997                                        u32 rx_buf_sz)
3998 {
3999         desc->addr = cpu_to_le64(mapping);
4000         wmb();
4001         rtl8169_mark_to_asic(desc, rx_buf_sz);
4002 }
4003
4004 static inline void *rtl8169_align(void *data)
4005 {
4006         return (void *)ALIGN((long)data, 16);
4007 }
4008
4009 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4010                                              struct RxDesc *desc)
4011 {
4012         void *data;
4013         dma_addr_t mapping;
4014         struct device *d = &tp->pci_dev->dev;
4015         struct net_device *dev = tp->dev;
4016         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4017
4018         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4019         if (!data)
4020                 return NULL;
4021
4022         if (rtl8169_align(data) != data) {
4023                 kfree(data);
4024                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4025                 if (!data)
4026                         return NULL;
4027         }
4028
4029         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4030                                  DMA_FROM_DEVICE);
4031         if (unlikely(dma_mapping_error(d, mapping))) {
4032                 if (net_ratelimit())
4033                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4034                 goto err_out;
4035         }
4036
4037         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4038         return data;
4039
4040 err_out:
4041         kfree(data);
4042         return NULL;
4043 }
4044
4045 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4046 {
4047         unsigned int i;
4048
4049         for (i = 0; i < NUM_RX_DESC; i++) {
4050                 if (tp->Rx_databuff[i]) {
4051                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4052                                             tp->RxDescArray + i);
4053                 }
4054         }
4055 }
4056
4057 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4058 {
4059         desc->opts1 |= cpu_to_le32(RingEnd);
4060 }
4061
4062 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4063 {
4064         unsigned int i;
4065
4066         for (i = 0; i < NUM_RX_DESC; i++) {
4067                 void *data;
4068
4069                 if (tp->Rx_databuff[i])
4070                         continue;
4071
4072                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4073                 if (!data) {
4074                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4075                         goto err_out;
4076                 }
4077                 tp->Rx_databuff[i] = data;
4078         }
4079
4080         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4081         return 0;
4082
4083 err_out:
4084         rtl8169_rx_clear(tp);
4085         return -ENOMEM;
4086 }
4087
4088 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4089 {
4090         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4091 }
4092
4093 static int rtl8169_init_ring(struct net_device *dev)
4094 {
4095         struct rtl8169_private *tp = netdev_priv(dev);
4096
4097         rtl8169_init_ring_indexes(tp);
4098
4099         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4100         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4101
4102         return rtl8169_rx_fill(tp);
4103 }
4104
4105 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4106                                  struct TxDesc *desc)
4107 {
4108         unsigned int len = tx_skb->len;
4109
4110         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4111
4112         desc->opts1 = 0x00;
4113         desc->opts2 = 0x00;
4114         desc->addr = 0x00;
4115         tx_skb->len = 0;
4116 }
4117
4118 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4119                                    unsigned int n)
4120 {
4121         unsigned int i;
4122
4123         for (i = 0; i < n; i++) {
4124                 unsigned int entry = (start + i) % NUM_TX_DESC;
4125                 struct ring_info *tx_skb = tp->tx_skb + entry;
4126                 unsigned int len = tx_skb->len;
4127
4128                 if (len) {
4129                         struct sk_buff *skb = tx_skb->skb;
4130
4131                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4132                                              tp->TxDescArray + entry);
4133                         if (skb) {
4134                                 tp->dev->stats.tx_dropped++;
4135                                 dev_kfree_skb(skb);
4136                                 tx_skb->skb = NULL;
4137                         }
4138                 }
4139         }
4140 }
4141
4142 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4143 {
4144         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4145         tp->cur_tx = tp->dirty_tx = 0;
4146 }
4147
4148 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4149 {
4150         struct rtl8169_private *tp = netdev_priv(dev);
4151
4152         PREPARE_DELAYED_WORK(&tp->task, task);
4153         schedule_delayed_work(&tp->task, 4);
4154 }
4155
4156 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4157 {
4158         struct rtl8169_private *tp = netdev_priv(dev);
4159         void __iomem *ioaddr = tp->mmio_addr;
4160
4161         synchronize_irq(dev->irq);
4162
4163         /* Wait for any pending NAPI task to complete */
4164         napi_disable(&tp->napi);
4165
4166         rtl8169_irq_mask_and_ack(ioaddr);
4167
4168         tp->intr_mask = 0xffff;
4169         RTL_W16(IntrMask, tp->intr_event);
4170         napi_enable(&tp->napi);
4171 }
4172
4173 static void rtl8169_reinit_task(struct work_struct *work)
4174 {
4175         struct rtl8169_private *tp =
4176                 container_of(work, struct rtl8169_private, task.work);
4177         struct net_device *dev = tp->dev;
4178         int ret;
4179
4180         rtnl_lock();
4181
4182         if (!netif_running(dev))
4183                 goto out_unlock;
4184
4185         rtl8169_wait_for_quiescence(dev);
4186         rtl8169_close(dev);
4187
4188         ret = rtl8169_open(dev);
4189         if (unlikely(ret < 0)) {
4190                 if (net_ratelimit())
4191                         netif_err(tp, drv, dev,
4192                                   "reinit failure (status = %d). Rescheduling\n",
4193                                   ret);
4194                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4195         }
4196
4197 out_unlock:
4198         rtnl_unlock();
4199 }
4200
4201 static void rtl8169_reset_task(struct work_struct *work)
4202 {
4203         struct rtl8169_private *tp =
4204                 container_of(work, struct rtl8169_private, task.work);
4205         struct net_device *dev = tp->dev;
4206
4207         rtnl_lock();
4208
4209         if (!netif_running(dev))
4210                 goto out_unlock;
4211
4212         rtl8169_wait_for_quiescence(dev);
4213
4214         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4215         rtl8169_tx_clear(tp);
4216
4217         if (tp->dirty_rx == tp->cur_rx) {
4218                 rtl8169_init_ring_indexes(tp);
4219                 rtl_hw_start(dev);
4220                 netif_wake_queue(dev);
4221                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4222         } else {
4223                 if (net_ratelimit())
4224                         netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4225                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4226         }
4227
4228 out_unlock:
4229         rtnl_unlock();
4230 }
4231
4232 static void rtl8169_tx_timeout(struct net_device *dev)
4233 {
4234         struct rtl8169_private *tp = netdev_priv(dev);
4235
4236         rtl8169_hw_reset(tp);
4237
4238         /* Let's wait a bit while any (async) irq lands on */
4239         rtl8169_schedule_work(dev, rtl8169_reset_task);
4240 }
4241
4242 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4243                               u32 opts1)
4244 {
4245         struct skb_shared_info *info = skb_shinfo(skb);
4246         unsigned int cur_frag, entry;
4247         struct TxDesc * uninitialized_var(txd);
4248         struct device *d = &tp->pci_dev->dev;
4249
4250         entry = tp->cur_tx;
4251         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4252                 skb_frag_t *frag = info->frags + cur_frag;
4253                 dma_addr_t mapping;
4254                 u32 status, len;
4255                 void *addr;
4256
4257                 entry = (entry + 1) % NUM_TX_DESC;
4258
4259                 txd = tp->TxDescArray + entry;
4260                 len = frag->size;
4261                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4262                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4263                 if (unlikely(dma_mapping_error(d, mapping))) {
4264                         if (net_ratelimit())
4265                                 netif_err(tp, drv, tp->dev,
4266                                           "Failed to map TX fragments DMA!\n");
4267                         goto err_out;
4268                 }
4269
4270                 /* anti gcc 2.95.3 bugware (sic) */
4271                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4272
4273                 txd->opts1 = cpu_to_le32(status);
4274                 txd->addr = cpu_to_le64(mapping);
4275
4276                 tp->tx_skb[entry].len = len;
4277         }
4278
4279         if (cur_frag) {
4280                 tp->tx_skb[entry].skb = skb;
4281                 txd->opts1 |= cpu_to_le32(LastFrag);
4282         }
4283
4284         return cur_frag;
4285
4286 err_out:
4287         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4288         return -EIO;
4289 }
4290
4291 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4292 {
4293         if (dev->features & NETIF_F_TSO) {
4294                 u32 mss = skb_shinfo(skb)->gso_size;
4295
4296                 if (mss)
4297                         return LargeSend | ((mss & MSSMask) << MSSShift);
4298         }
4299         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4300                 const struct iphdr *ip = ip_hdr(skb);
4301
4302                 if (ip->protocol == IPPROTO_TCP)
4303                         return IPCS | TCPCS;
4304                 else if (ip->protocol == IPPROTO_UDP)
4305                         return IPCS | UDPCS;
4306                 WARN_ON(1);     /* we need a WARN() */
4307         }
4308         return 0;
4309 }
4310
4311 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4312                                       struct net_device *dev)
4313 {
4314         struct rtl8169_private *tp = netdev_priv(dev);
4315         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4316         struct TxDesc *txd = tp->TxDescArray + entry;
4317         void __iomem *ioaddr = tp->mmio_addr;
4318         struct device *d = &tp->pci_dev->dev;
4319         dma_addr_t mapping;
4320         u32 status, len;
4321         u32 opts1;
4322         int frags;
4323
4324         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4325                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4326                 goto err_stop_0;
4327         }
4328
4329         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4330                 goto err_stop_0;
4331
4332         len = skb_headlen(skb);
4333         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4334         if (unlikely(dma_mapping_error(d, mapping))) {
4335                 if (net_ratelimit())
4336                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4337                 goto err_dma_0;
4338         }
4339
4340         tp->tx_skb[entry].len = len;
4341         txd->addr = cpu_to_le64(mapping);
4342         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4343
4344         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4345
4346         frags = rtl8169_xmit_frags(tp, skb, opts1);
4347         if (frags < 0)
4348                 goto err_dma_1;
4349         else if (frags)
4350                 opts1 |= FirstFrag;
4351         else {
4352                 opts1 |= FirstFrag | LastFrag;
4353                 tp->tx_skb[entry].skb = skb;
4354         }
4355
4356         wmb();
4357
4358         /* anti gcc 2.95.3 bugware (sic) */
4359         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4360         txd->opts1 = cpu_to_le32(status);
4361
4362         tp->cur_tx += frags + 1;
4363
4364         wmb();
4365
4366         RTL_W8(TxPoll, NPQ);    /* set polling bit */
4367
4368         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4369                 netif_stop_queue(dev);
4370                 smp_rmb();
4371                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4372                         netif_wake_queue(dev);
4373         }
4374
4375         return NETDEV_TX_OK;
4376
4377 err_dma_1:
4378         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4379 err_dma_0:
4380         dev_kfree_skb(skb);
4381         dev->stats.tx_dropped++;
4382         return NETDEV_TX_OK;
4383
4384 err_stop_0:
4385         netif_stop_queue(dev);
4386         dev->stats.tx_dropped++;
4387         return NETDEV_TX_BUSY;
4388 }
4389
4390 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4391 {
4392         struct rtl8169_private *tp = netdev_priv(dev);
4393         struct pci_dev *pdev = tp->pci_dev;
4394         u16 pci_status, pci_cmd;
4395
4396         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4397         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4398
4399         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4400                   pci_cmd, pci_status);
4401
4402         /*
4403          * The recovery sequence below admits a very elaborated explanation:
4404          * - it seems to work;
4405          * - I did not see what else could be done;
4406          * - it makes iop3xx happy.
4407          *
4408          * Feel free to adjust to your needs.
4409          */
4410         if (pdev->broken_parity_status)
4411                 pci_cmd &= ~PCI_COMMAND_PARITY;
4412         else
4413                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4414
4415         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4416
4417         pci_write_config_word(pdev, PCI_STATUS,
4418                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4419                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4420                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4421
4422         /* The infamous DAC f*ckup only happens at boot time */
4423         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4424                 void __iomem *ioaddr = tp->mmio_addr;
4425
4426                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4427                 tp->cp_cmd &= ~PCIDAC;
4428                 RTL_W16(CPlusCmd, tp->cp_cmd);
4429                 dev->features &= ~NETIF_F_HIGHDMA;
4430         }
4431
4432         rtl8169_hw_reset(tp);
4433
4434         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4435 }
4436
4437 static void rtl8169_tx_interrupt(struct net_device *dev,
4438                                  struct rtl8169_private *tp,
4439                                  void __iomem *ioaddr)
4440 {
4441         unsigned int dirty_tx, tx_left;
4442
4443         dirty_tx = tp->dirty_tx;
4444         smp_rmb();
4445         tx_left = tp->cur_tx - dirty_tx;
4446
4447         while (tx_left > 0) {
4448                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4449                 struct ring_info *tx_skb = tp->tx_skb + entry;
4450                 u32 status;
4451
4452                 rmb();
4453                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4454                 if (status & DescOwn)
4455                         break;
4456
4457                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4458                                      tp->TxDescArray + entry);
4459                 if (status & LastFrag) {
4460                         dev->stats.tx_packets++;
4461                         dev->stats.tx_bytes += tx_skb->skb->len;
4462                         dev_kfree_skb(tx_skb->skb);
4463                         tx_skb->skb = NULL;
4464                 }
4465                 dirty_tx++;
4466                 tx_left--;
4467         }
4468
4469         if (tp->dirty_tx != dirty_tx) {
4470                 tp->dirty_tx = dirty_tx;
4471                 smp_wmb();
4472                 if (netif_queue_stopped(dev) &&
4473                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4474                         netif_wake_queue(dev);
4475                 }
4476                 /*
4477                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4478                  * too close. Let's kick an extra TxPoll request when a burst
4479                  * of start_xmit activity is detected (if it is not detected,
4480                  * it is slow enough). -- FR
4481                  */
4482                 smp_rmb();
4483                 if (tp->cur_tx != dirty_tx)
4484                         RTL_W8(TxPoll, NPQ);
4485         }
4486 }
4487
4488 static inline int rtl8169_fragmented_frame(u32 status)
4489 {
4490         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4491 }
4492
4493 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4494 {
4495         u32 status = opts1 & RxProtoMask;
4496
4497         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4498             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4499                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4500         else
4501                 skb_checksum_none_assert(skb);
4502 }
4503
4504 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4505                                            struct rtl8169_private *tp,
4506                                            int pkt_size,
4507                                            dma_addr_t addr)
4508 {
4509         struct sk_buff *skb;
4510         struct device *d = &tp->pci_dev->dev;
4511
4512         data = rtl8169_align(data);
4513         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4514         prefetch(data);
4515         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4516         if (skb)
4517                 memcpy(skb->data, data, pkt_size);
4518         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4519
4520         return skb;
4521 }
4522
4523 /*
4524  * Warning : rtl8169_rx_interrupt() might be called :
4525  * 1) from NAPI (softirq) context
4526  *      (polling = 1 : we should call netif_receive_skb())
4527  * 2) from process context (rtl8169_reset_task())
4528  *      (polling = 0 : we must call netif_rx() instead)
4529  */
4530 static int rtl8169_rx_interrupt(struct net_device *dev,
4531                                 struct rtl8169_private *tp,
4532                                 void __iomem *ioaddr, u32 budget)
4533 {
4534         unsigned int cur_rx, rx_left;
4535         unsigned int count;
4536         int polling = (budget != ~(u32)0) ? 1 : 0;
4537
4538         cur_rx = tp->cur_rx;
4539         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4540         rx_left = min(rx_left, budget);
4541
4542         for (; rx_left > 0; rx_left--, cur_rx++) {
4543                 unsigned int entry = cur_rx % NUM_RX_DESC;
4544                 struct RxDesc *desc = tp->RxDescArray + entry;
4545                 u32 status;
4546
4547                 rmb();
4548                 status = le32_to_cpu(desc->opts1);
4549
4550                 if (status & DescOwn)
4551                         break;
4552                 if (unlikely(status & RxRES)) {
4553                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4554                                    status);
4555                         dev->stats.rx_errors++;
4556                         if (status & (RxRWT | RxRUNT))
4557                                 dev->stats.rx_length_errors++;
4558                         if (status & RxCRC)
4559                                 dev->stats.rx_crc_errors++;
4560                         if (status & RxFOVF) {
4561                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4562                                 dev->stats.rx_fifo_errors++;
4563                         }
4564                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4565                 } else {
4566                         struct sk_buff *skb;
4567                         dma_addr_t addr = le64_to_cpu(desc->addr);
4568                         int pkt_size = (status & 0x00001FFF) - 4;
4569
4570                         /*
4571                          * The driver does not support incoming fragmented
4572                          * frames. They are seen as a symptom of over-mtu
4573                          * sized frames.
4574                          */
4575                         if (unlikely(rtl8169_fragmented_frame(status))) {
4576                                 dev->stats.rx_dropped++;
4577                                 dev->stats.rx_length_errors++;
4578                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4579                                 continue;
4580                         }
4581
4582                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4583                                                   tp, pkt_size, addr);
4584                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4585                         if (!skb) {
4586                                 dev->stats.rx_dropped++;
4587                                 continue;
4588                         }
4589
4590                         rtl8169_rx_csum(skb, status);
4591                         skb_put(skb, pkt_size);
4592                         skb->protocol = eth_type_trans(skb, dev);
4593
4594                         if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4595                                 if (likely(polling))
4596                                         napi_gro_receive(&tp->napi, skb);
4597                                 else
4598                                         netif_rx(skb);
4599                         }
4600
4601                         dev->stats.rx_bytes += pkt_size;
4602                         dev->stats.rx_packets++;
4603                 }
4604
4605                 /* Work around for AMD plateform. */
4606                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4607                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4608                         desc->opts2 = 0;
4609                         cur_rx++;
4610                 }
4611         }
4612
4613         count = cur_rx - tp->cur_rx;
4614         tp->cur_rx = cur_rx;
4615
4616         tp->dirty_rx += count;
4617
4618         return count;
4619 }
4620
4621 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4622 {
4623         struct net_device *dev = dev_instance;
4624         struct rtl8169_private *tp = netdev_priv(dev);
4625         void __iomem *ioaddr = tp->mmio_addr;
4626         int handled = 0;
4627         int status;
4628
4629         /* loop handling interrupts until we have no new ones or
4630          * we hit a invalid/hotplug case.
4631          */
4632         status = RTL_R16(IntrStatus);
4633         while (status && status != 0xffff) {
4634                 handled = 1;
4635
4636                 /* Handle all of the error cases first. These will reset
4637                  * the chip, so just exit the loop.
4638                  */
4639                 if (unlikely(!netif_running(dev))) {
4640                         rtl8169_asic_down(ioaddr);
4641                         break;
4642                 }
4643
4644                 if (unlikely(status & RxFIFOOver)) {
4645                         switch (tp->mac_version) {
4646                         /* Work around for rx fifo overflow */
4647                         case RTL_GIGA_MAC_VER_11:
4648                         case RTL_GIGA_MAC_VER_22:
4649                         case RTL_GIGA_MAC_VER_26:
4650                                 netif_stop_queue(dev);
4651                                 rtl8169_tx_timeout(dev);
4652                                 goto done;
4653                         /* Testers needed. */
4654                         case RTL_GIGA_MAC_VER_17:
4655                         case RTL_GIGA_MAC_VER_19:
4656                         case RTL_GIGA_MAC_VER_20:
4657                         case RTL_GIGA_MAC_VER_21:
4658                         case RTL_GIGA_MAC_VER_23:
4659                         case RTL_GIGA_MAC_VER_24:
4660                         case RTL_GIGA_MAC_VER_27:
4661                         case RTL_GIGA_MAC_VER_28:
4662                         /* Experimental science. Pktgen proof. */
4663                         case RTL_GIGA_MAC_VER_12:
4664                         case RTL_GIGA_MAC_VER_25:
4665                                 if (status == RxFIFOOver)
4666                                         goto done;
4667                                 break;
4668                         default:
4669                                 break;
4670                         }
4671                 }
4672
4673                 if (unlikely(status & SYSErr)) {
4674                         rtl8169_pcierr_interrupt(dev);
4675                         break;
4676                 }
4677
4678                 if (status & LinkChg)
4679                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
4680
4681                 /* We need to see the lastest version of tp->intr_mask to
4682                  * avoid ignoring an MSI interrupt and having to wait for
4683                  * another event which may never come.
4684                  */
4685                 smp_rmb();
4686                 if (status & tp->intr_mask & tp->napi_event) {
4687                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4688                         tp->intr_mask = ~tp->napi_event;
4689
4690                         if (likely(napi_schedule_prep(&tp->napi)))
4691                                 __napi_schedule(&tp->napi);
4692                         else
4693                                 netif_info(tp, intr, dev,
4694                                            "interrupt %04x in poll\n", status);
4695                 }
4696
4697                 /* We only get a new MSI interrupt when all active irq
4698                  * sources on the chip have been acknowledged. So, ack
4699                  * everything we've seen and check if new sources have become
4700                  * active to avoid blocking all interrupts from the chip.
4701                  */
4702                 RTL_W16(IntrStatus,
4703                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
4704                 status = RTL_R16(IntrStatus);
4705         }
4706 done:
4707         return IRQ_RETVAL(handled);
4708 }
4709
4710 static int rtl8169_poll(struct napi_struct *napi, int budget)
4711 {
4712         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4713         struct net_device *dev = tp->dev;
4714         void __iomem *ioaddr = tp->mmio_addr;
4715         int work_done;
4716
4717         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4718         rtl8169_tx_interrupt(dev, tp, ioaddr);
4719
4720         if (work_done < budget) {
4721                 napi_complete(napi);
4722
4723                 /* We need for force the visibility of tp->intr_mask
4724                  * for other CPUs, as we can loose an MSI interrupt
4725                  * and potentially wait for a retransmit timeout if we don't.
4726                  * The posted write to IntrMask is safe, as it will
4727                  * eventually make it to the chip and we won't loose anything
4728                  * until it does.
4729                  */
4730                 tp->intr_mask = 0xffff;
4731                 wmb();
4732                 RTL_W16(IntrMask, tp->intr_event);
4733         }
4734
4735         return work_done;
4736 }
4737
4738 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4739 {
4740         struct rtl8169_private *tp = netdev_priv(dev);
4741
4742         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4743                 return;
4744
4745         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4746         RTL_W32(RxMissed, 0);
4747 }
4748
4749 static void rtl8169_down(struct net_device *dev)
4750 {
4751         struct rtl8169_private *tp = netdev_priv(dev);
4752         void __iomem *ioaddr = tp->mmio_addr;
4753
4754         rtl8169_delete_timer(dev);
4755
4756         netif_stop_queue(dev);
4757
4758         napi_disable(&tp->napi);
4759
4760         spin_lock_irq(&tp->lock);
4761
4762         rtl8169_asic_down(ioaddr);
4763         /*
4764          * At this point device interrupts can not be enabled in any function,
4765          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4766          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4767          */
4768         rtl8169_rx_missed(dev, ioaddr);
4769
4770         spin_unlock_irq(&tp->lock);
4771
4772         synchronize_irq(dev->irq);
4773
4774         /* Give a racing hard_start_xmit a few cycles to complete. */
4775         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
4776
4777         rtl8169_tx_clear(tp);
4778
4779         rtl8169_rx_clear(tp);
4780
4781         rtl_pll_power_down(tp);
4782 }
4783
4784 static int rtl8169_close(struct net_device *dev)
4785 {
4786         struct rtl8169_private *tp = netdev_priv(dev);
4787         struct pci_dev *pdev = tp->pci_dev;
4788
4789         pm_runtime_get_sync(&pdev->dev);
4790
4791         /* update counters before going down */
4792         rtl8169_update_counters(dev);
4793
4794         rtl8169_down(dev);
4795
4796         free_irq(dev->irq, dev);
4797
4798         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4799                           tp->RxPhyAddr);
4800         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4801                           tp->TxPhyAddr);
4802         tp->TxDescArray = NULL;
4803         tp->RxDescArray = NULL;
4804
4805         pm_runtime_put_sync(&pdev->dev);
4806
4807         return 0;
4808 }
4809
4810 static void rtl_set_rx_mode(struct net_device *dev)
4811 {
4812         struct rtl8169_private *tp = netdev_priv(dev);
4813         void __iomem *ioaddr = tp->mmio_addr;
4814         unsigned long flags;
4815         u32 mc_filter[2];       /* Multicast hash filter */
4816         int rx_mode;
4817         u32 tmp = 0;
4818
4819         if (dev->flags & IFF_PROMISC) {
4820                 /* Unconditionally log net taps. */
4821                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4822                 rx_mode =
4823                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4824                     AcceptAllPhys;
4825                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4826         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4827                    (dev->flags & IFF_ALLMULTI)) {
4828                 /* Too many to filter perfectly -- accept all multicasts. */
4829                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4830                 mc_filter[1] = mc_filter[0] = 0xffffffff;
4831         } else {
4832                 struct netdev_hw_addr *ha;
4833
4834                 rx_mode = AcceptBroadcast | AcceptMyPhys;
4835                 mc_filter[1] = mc_filter[0] = 0;
4836                 netdev_for_each_mc_addr(ha, dev) {
4837                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4838                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4839                         rx_mode |= AcceptMulticast;
4840                 }
4841         }
4842
4843         spin_lock_irqsave(&tp->lock, flags);
4844
4845         tmp = rtl8169_rx_config | rx_mode |
4846               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4847
4848         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4849                 u32 data = mc_filter[0];
4850
4851                 mc_filter[0] = swab32(mc_filter[1]);
4852                 mc_filter[1] = swab32(data);
4853         }
4854
4855         RTL_W32(MAR0 + 4, mc_filter[1]);
4856         RTL_W32(MAR0 + 0, mc_filter[0]);
4857
4858         RTL_W32(RxConfig, tmp);
4859
4860         spin_unlock_irqrestore(&tp->lock, flags);
4861 }
4862
4863 /**
4864  *  rtl8169_get_stats - Get rtl8169 read/write statistics
4865  *  @dev: The Ethernet Device to get statistics for
4866  *
4867  *  Get TX/RX statistics for rtl8169
4868  */
4869 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4870 {
4871         struct rtl8169_private *tp = netdev_priv(dev);
4872         void __iomem *ioaddr = tp->mmio_addr;
4873         unsigned long flags;
4874
4875         if (netif_running(dev)) {
4876                 spin_lock_irqsave(&tp->lock, flags);
4877                 rtl8169_rx_missed(dev, ioaddr);
4878                 spin_unlock_irqrestore(&tp->lock, flags);
4879         }
4880
4881         return &dev->stats;
4882 }
4883
4884 static void rtl8169_net_suspend(struct net_device *dev)
4885 {
4886         struct rtl8169_private *tp = netdev_priv(dev);
4887
4888         if (!netif_running(dev))
4889                 return;
4890
4891         rtl_pll_power_down(tp);
4892
4893         netif_device_detach(dev);
4894         netif_stop_queue(dev);
4895 }
4896
4897 #ifdef CONFIG_PM
4898
4899 static int rtl8169_suspend(struct device *device)
4900 {
4901         struct pci_dev *pdev = to_pci_dev(device);
4902         struct net_device *dev = pci_get_drvdata(pdev);
4903
4904         rtl8169_net_suspend(dev);
4905
4906         return 0;
4907 }
4908
4909 static void __rtl8169_resume(struct net_device *dev)
4910 {
4911         struct rtl8169_private *tp = netdev_priv(dev);
4912
4913         netif_device_attach(dev);
4914
4915         rtl_pll_power_up(tp);
4916
4917         rtl8169_schedule_work(dev, rtl8169_reset_task);
4918 }
4919
4920 static int rtl8169_resume(struct device *device)
4921 {
4922         struct pci_dev *pdev = to_pci_dev(device);
4923         struct net_device *dev = pci_get_drvdata(pdev);
4924         struct rtl8169_private *tp = netdev_priv(dev);
4925
4926         rtl8169_init_phy(dev, tp);
4927
4928         if (netif_running(dev))
4929                 __rtl8169_resume(dev);
4930
4931         return 0;
4932 }
4933
4934 static int rtl8169_runtime_suspend(struct device *device)
4935 {
4936         struct pci_dev *pdev = to_pci_dev(device);
4937         struct net_device *dev = pci_get_drvdata(pdev);
4938         struct rtl8169_private *tp = netdev_priv(dev);
4939
4940         if (!tp->TxDescArray)
4941                 return 0;
4942
4943         spin_lock_irq(&tp->lock);
4944         tp->saved_wolopts = __rtl8169_get_wol(tp);
4945         __rtl8169_set_wol(tp, WAKE_ANY);
4946         spin_unlock_irq(&tp->lock);
4947
4948         rtl8169_net_suspend(dev);
4949
4950         return 0;
4951 }
4952
4953 static int rtl8169_runtime_resume(struct device *device)
4954 {
4955         struct pci_dev *pdev = to_pci_dev(device);
4956         struct net_device *dev = pci_get_drvdata(pdev);
4957         struct rtl8169_private *tp = netdev_priv(dev);
4958
4959         if (!tp->TxDescArray)
4960                 return 0;
4961
4962         spin_lock_irq(&tp->lock);
4963         __rtl8169_set_wol(tp, tp->saved_wolopts);
4964         tp->saved_wolopts = 0;
4965         spin_unlock_irq(&tp->lock);
4966
4967         rtl8169_init_phy(dev, tp);
4968
4969         __rtl8169_resume(dev);
4970
4971         return 0;
4972 }
4973
4974 static int rtl8169_runtime_idle(struct device *device)
4975 {
4976         struct pci_dev *pdev = to_pci_dev(device);
4977         struct net_device *dev = pci_get_drvdata(pdev);
4978         struct rtl8169_private *tp = netdev_priv(dev);
4979
4980         return tp->TxDescArray ? -EBUSY : 0;
4981 }
4982
4983 static const struct dev_pm_ops rtl8169_pm_ops = {
4984         .suspend = rtl8169_suspend,
4985         .resume = rtl8169_resume,
4986         .freeze = rtl8169_suspend,
4987         .thaw = rtl8169_resume,
4988         .poweroff = rtl8169_suspend,
4989         .restore = rtl8169_resume,
4990         .runtime_suspend = rtl8169_runtime_suspend,
4991         .runtime_resume = rtl8169_runtime_resume,
4992         .runtime_idle = rtl8169_runtime_idle,
4993 };
4994
4995 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
4996
4997 #else /* !CONFIG_PM */
4998
4999 #define RTL8169_PM_OPS  NULL
5000
5001 #endif /* !CONFIG_PM */
5002
5003 static void rtl_shutdown(struct pci_dev *pdev)
5004 {
5005         struct net_device *dev = pci_get_drvdata(pdev);
5006         struct rtl8169_private *tp = netdev_priv(dev);
5007         void __iomem *ioaddr = tp->mmio_addr;
5008
5009         rtl8169_net_suspend(dev);
5010
5011         /* restore original MAC address */
5012         rtl_rar_set(tp, dev->perm_addr);
5013
5014         spin_lock_irq(&tp->lock);
5015
5016         rtl8169_asic_down(ioaddr);
5017
5018         spin_unlock_irq(&tp->lock);
5019
5020         if (system_state == SYSTEM_POWER_OFF) {
5021                 /* WoL fails with some 8168 when the receiver is disabled. */
5022                 if (tp->features & RTL_FEATURE_WOL) {
5023                         pci_clear_master(pdev);
5024
5025                         RTL_W8(ChipCmd, CmdRxEnb);
5026                         /* PCI commit */
5027                         RTL_R8(ChipCmd);
5028                 }
5029
5030                 pci_wake_from_d3(pdev, true);
5031                 pci_set_power_state(pdev, PCI_D3hot);
5032         }
5033 }
5034
5035 static struct pci_driver rtl8169_pci_driver = {
5036         .name           = MODULENAME,
5037         .id_table       = rtl8169_pci_tbl,
5038         .probe          = rtl8169_init_one,
5039         .remove         = __devexit_p(rtl8169_remove_one),
5040         .shutdown       = rtl_shutdown,
5041         .driver.pm      = RTL8169_PM_OPS,
5042 };
5043
5044 static int __init rtl8169_init_module(void)
5045 {
5046         return pci_register_driver(&rtl8169_pci_driver);
5047 }
5048
5049 static void __exit rtl8169_cleanup_module(void)
5050 {
5051         pci_unregister_driver(&rtl8169_pci_driver);
5052 }
5053
5054 module_init(rtl8169_init_module);
5055 module_exit(rtl8169_cleanup_module);