drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/firmware.h>
  28 #include <linux/pci-aspm.h>
  29 #include <linux/prefetch.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34
  35 #define RTL8169_VERSION "2.3LK-NAPI"
  36 #define MODULENAME "r8169"
  37 #define PFX MODULENAME ": "
  38
  39 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  40 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  41 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  42 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  43 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  44
  45 #ifdef RTL8169_DEBUG
  46 #define assert(expr) \
  47         if (!(expr)) {                                  \
  48                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  49                 #expr,__FILE__,__func__,__LINE__);              \
  50         }
  51 #define dprintk(fmt, args...) \
  52         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  53 #else
  54 #define assert(expr) do {} while (0)
  55 #define dprintk(fmt, args...)   do {} while (0)
  56 #endif /* RTL8169_DEBUG */
  57
  58 #define R8169_MSG_DEFAULT \
  59         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  60
  61 #define TX_BUFFS_AVAIL(tp) \
  62         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  63
  64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  65    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  66 static const int multicast_filter_limit = 32;
  67
  68 /* MAC address length */
  69 #define MAC_ADDR_LEN    6
  70
  71 #define MAX_READ_REQUEST_SHIFT  12
  72 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  73 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  74 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  76 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  77
  78 #define R8169_REGS_SIZE         256
  79 #define R8169_NAPI_WEIGHT       64
  80 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  81 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  82 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  83 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  84 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  85
  86 #define RTL8169_TX_TIMEOUT      (6*HZ)
  87 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  88
  89 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  90 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  91 #define RTL_EEPROM_SIG_ADDR     0x0000
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_NONE   = 0xff,
 136 };
 137
 138 enum rtl_tx_desc_version {
 139         RTL_TD_0        = 0,
 140         RTL_TD_1        = 1,
 141 };
 142
 143 #define _R(NAME,TD,FW) \
 144         { .name = NAME, .txd_version = TD, .fw_name = FW }
 145
 146 static const struct {
 147         const char *name;
 148         enum rtl_tx_desc_version txd_version;
 149         const char *fw_name;
 150 } rtl_chip_infos[] = {
 151         /* PCI devices. */
 152         [RTL_GIGA_MAC_VER_01] =
 153                 _R("RTL8169",           RTL_TD_0, NULL),
 154         [RTL_GIGA_MAC_VER_02] =
 155                 _R("RTL8169s",          RTL_TD_0, NULL),
 156         [RTL_GIGA_MAC_VER_03] =
 157                 _R("RTL8110s",          RTL_TD_0, NULL),
 158         [RTL_GIGA_MAC_VER_04] =
 159                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 160         [RTL_GIGA_MAC_VER_05] =
 161                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 162         [RTL_GIGA_MAC_VER_06] =
 163                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 164         /* PCI-E devices. */
 165         [RTL_GIGA_MAC_VER_07] =
 166                 _R("RTL8102e",          RTL_TD_1, NULL),
 167         [RTL_GIGA_MAC_VER_08] =
 168                 _R("RTL8102e",          RTL_TD_1, NULL),
 169         [RTL_GIGA_MAC_VER_09] =
 170                 _R("RTL8102e",          RTL_TD_1, NULL),
 171         [RTL_GIGA_MAC_VER_10] =
 172                 _R("RTL8101e",          RTL_TD_0, NULL),
 173         [RTL_GIGA_MAC_VER_11] =
 174                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 175         [RTL_GIGA_MAC_VER_12] =
 176                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 177         [RTL_GIGA_MAC_VER_13] =
 178                 _R("RTL8101e",          RTL_TD_0, NULL),
 179         [RTL_GIGA_MAC_VER_14] =
 180                 _R("RTL8100e",          RTL_TD_0, NULL),
 181         [RTL_GIGA_MAC_VER_15] =
 182                 _R("RTL8100e",          RTL_TD_0, NULL),
 183         [RTL_GIGA_MAC_VER_16] =
 184                 _R("RTL8101e",          RTL_TD_0, NULL),
 185         [RTL_GIGA_MAC_VER_17] =
 186                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 187         [RTL_GIGA_MAC_VER_18] =
 188                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 189         [RTL_GIGA_MAC_VER_19] =
 190                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 191         [RTL_GIGA_MAC_VER_20] =
 192                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 193         [RTL_GIGA_MAC_VER_21] =
 194                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 195         [RTL_GIGA_MAC_VER_22] =
 196                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 197         [RTL_GIGA_MAC_VER_23] =
 198                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 199         [RTL_GIGA_MAC_VER_24] =
 200                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 201         [RTL_GIGA_MAC_VER_25] =
 202                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 203         [RTL_GIGA_MAC_VER_26] =
 204                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 205         [RTL_GIGA_MAC_VER_27] =
 206                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 207         [RTL_GIGA_MAC_VER_28] =
 208                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 209         [RTL_GIGA_MAC_VER_29] =
 210                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 211         [RTL_GIGA_MAC_VER_30] =
 212                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 213         [RTL_GIGA_MAC_VER_31] =
 214                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 215         [RTL_GIGA_MAC_VER_32] =
 216                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 217         [RTL_GIGA_MAC_VER_33] =
 218                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2)
 219 };
 220 #undef _R
 221
 222 enum cfg_version {
 223         RTL_CFG_0 = 0x00,
 224         RTL_CFG_1,
 225         RTL_CFG_2
 226 };
 227
 228 static void rtl_hw_start_8169(struct net_device *);
 229 static void rtl_hw_start_8168(struct net_device *);
 230 static void rtl_hw_start_8101(struct net_device *);
 231
 232 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 233         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 234         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 235         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 238         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 239         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 240         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 241         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 242                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 243         { 0x0001,                               0x8168,
 244                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 245         {0,},
 246 };
 247
 248 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 249
 250 static int rx_buf_sz = 16383;
 251 static int use_dac;
 252 static struct {
 253         u32 msg_enable;
 254 } debug = { -1 };
 255
 256 enum rtl_registers {
 257         MAC0            = 0,    /* Ethernet hardware address. */
 258         MAC4            = 4,
 259         MAR0            = 8,    /* Multicast filter. */
 260         CounterAddrLow          = 0x10,
 261         CounterAddrHigh         = 0x14,
 262         TxDescStartAddrLow      = 0x20,
 263         TxDescStartAddrHigh     = 0x24,
 264         TxHDescStartAddrLow     = 0x28,
 265         TxHDescStartAddrHigh    = 0x2c,
 266         FLASH           = 0x30,
 267         ERSR            = 0x36,
 268         ChipCmd         = 0x37,
 269         TxPoll          = 0x38,
 270         IntrMask        = 0x3c,
 271         IntrStatus      = 0x3e,
 272         TxConfig        = 0x40,
 273         RxConfig        = 0x44,
 274
 275 #define RTL_RX_CONFIG_MASK              0xff7e1880u
 276
 277         RxMissed        = 0x4c,
 278         Cfg9346         = 0x50,
 279         Config0         = 0x51,
 280         Config1         = 0x52,
 281         Config2         = 0x53,
 282         Config3         = 0x54,
 283         Config4         = 0x55,
 284         Config5         = 0x56,
 285         MultiIntr       = 0x5c,
 286         PHYAR           = 0x60,
 287         PHYstatus       = 0x6c,
 288         RxMaxSize       = 0xda,
 289         CPlusCmd        = 0xe0,
 290         IntrMitigate    = 0xe2,
 291         RxDescAddrLow   = 0xe4,
 292         RxDescAddrHigh  = 0xe8,
 293         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 294
 295 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 296
 297         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 298
 299 #define TxPacketMax     (8064 >> 7)
 300
 301         FuncEvent       = 0xf0,
 302         FuncEventMask   = 0xf4,
 303         FuncPresetState = 0xf8,
 304         FuncForceEvent  = 0xfc,
 305 };
 306
 307 enum rtl8110_registers {
 308         TBICSR                  = 0x64,
 309         TBI_ANAR                = 0x68,
 310         TBI_LPAR                = 0x6a,
 311 };
 312
 313 enum rtl8168_8101_registers {
 314         CSIDR                   = 0x64,
 315         CSIAR                   = 0x68,
 316 #define CSIAR_FLAG                      0x80000000
 317 #define CSIAR_WRITE_CMD                 0x80000000
 318 #define CSIAR_BYTE_ENABLE               0x0f
 319 #define CSIAR_BYTE_ENABLE_SHIFT         12
 320 #define CSIAR_ADDR_MASK                 0x0fff
 321         PMCH                    = 0x6f,
 322         EPHYAR                  = 0x80,
 323 #define EPHYAR_FLAG                     0x80000000
 324 #define EPHYAR_WRITE_CMD                0x80000000
 325 #define EPHYAR_REG_MASK                 0x1f
 326 #define EPHYAR_REG_SHIFT                16
 327 #define EPHYAR_DATA_MASK                0xffff
 328         DLLPR                   = 0xd0,
 329 #define PM_SWITCH                       (1 << 6)
 330         DBG_REG                 = 0xd1,
 331 #define FIX_NAK_1                       (1 << 4)
 332 #define FIX_NAK_2                       (1 << 3)
 333         TWSI                    = 0xd2,
 334         MCU                     = 0xd3,
 335 #define EN_NDP                          (1 << 3)
 336 #define EN_OOB_RESET                    (1 << 2)
 337         EFUSEAR                 = 0xdc,
 338 #define EFUSEAR_FLAG                    0x80000000
 339 #define EFUSEAR_WRITE_CMD               0x80000000
 340 #define EFUSEAR_READ_CMD                0x00000000
 341 #define EFUSEAR_REG_MASK                0x03ff
 342 #define EFUSEAR_REG_SHIFT               8
 343 #define EFUSEAR_DATA_MASK               0xff
 344 };
 345
 346 enum rtl8168_registers {
 347         ERIDR                   = 0x70,
 348         ERIAR                   = 0x74,
 349 #define ERIAR_FLAG                      0x80000000
 350 #define ERIAR_WRITE_CMD                 0x80000000
 351 #define ERIAR_READ_CMD                  0x00000000
 352 #define ERIAR_ADDR_BYTE_ALIGN           4
 353 #define ERIAR_EXGMAC                    0
 354 #define ERIAR_MSIX                      1
 355 #define ERIAR_ASF                       2
 356 #define ERIAR_TYPE_SHIFT                16
 357 #define ERIAR_BYTEEN                    0x0f
 358 #define ERIAR_BYTEEN_SHIFT              12
 359         EPHY_RXER_NUM           = 0x7c,
 360         OCPDR                   = 0xb0, /* OCP GPHY access */
 361 #define OCPDR_WRITE_CMD                 0x80000000
 362 #define OCPDR_READ_CMD                  0x00000000
 363 #define OCPDR_REG_MASK                  0x7f
 364 #define OCPDR_GPHY_REG_SHIFT            16
 365 #define OCPDR_DATA_MASK                 0xffff
 366         OCPAR                   = 0xb4,
 367 #define OCPAR_FLAG                      0x80000000
 368 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 369 #define OCPAR_GPHY_READ_CMD             0x0000f060
 370         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 371         MISC                    = 0xf0, /* 8168e only. */
 372 #define TXPLA_RST                       (1 << 29)
 373 };
 374
 375 enum rtl_register_content {
 376         /* InterruptStatusBits */
 377         SYSErr          = 0x8000,
 378         PCSTimeout      = 0x4000,
 379         SWInt           = 0x0100,
 380         TxDescUnavail   = 0x0080,
 381         RxFIFOOver      = 0x0040,
 382         LinkChg         = 0x0020,
 383         RxOverflow      = 0x0010,
 384         TxErr           = 0x0008,
 385         TxOK            = 0x0004,
 386         RxErr           = 0x0002,
 387         RxOK            = 0x0001,
 388
 389         /* RxStatusDesc */
 390         RxFOVF  = (1 << 23),
 391         RxRWT   = (1 << 22),
 392         RxRES   = (1 << 21),
 393         RxRUNT  = (1 << 20),
 394         RxCRC   = (1 << 19),
 395
 396         /* ChipCmdBits */
 397         CmdReset        = 0x10,
 398         CmdRxEnb        = 0x08,
 399         CmdTxEnb        = 0x04,
 400         RxBufEmpty      = 0x01,
 401
 402         /* TXPoll register p.5 */
 403         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 404         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 405         FSWInt          = 0x01,         /* Forced software interrupt */
 406
 407         /* Cfg9346Bits */
 408         Cfg9346_Lock    = 0x00,
 409         Cfg9346_Unlock  = 0xc0,
 410
 411         /* rx_mode_bits */
 412         AcceptErr       = 0x20,
 413         AcceptRunt      = 0x10,
 414         AcceptBroadcast = 0x08,
 415         AcceptMulticast = 0x04,
 416         AcceptMyPhys    = 0x02,
 417         AcceptAllPhys   = 0x01,
 418
 419         /* RxConfigBits */
 420         RxCfgFIFOShift  = 13,
 421         RxCfgDMAShift   =  8,
 422
 423         /* TxConfigBits */
 424         TxInterFrameGapShift = 24,
 425         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 426
 427         /* Config1 register p.24 */
 428         LEDS1           = (1 << 7),
 429         LEDS0           = (1 << 6),
 430         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 431         Speed_down      = (1 << 4),
 432         MEMMAP          = (1 << 3),
 433         IOMAP           = (1 << 2),
 434         VPD             = (1 << 1),
 435         PMEnable        = (1 << 0),     /* Power Management Enable */
 436
 437         /* Config2 register p. 25 */
 438         PCI_Clock_66MHz = 0x01,
 439         PCI_Clock_33MHz = 0x00,
 440
 441         /* Config3 register p.25 */
 442         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 443         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 444         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 445
 446         /* Config5 register p.27 */
 447         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 448         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 449         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 450         Spi_en          = (1 << 3),
 451         LanWake         = (1 << 1),     /* LanWake enable/disable */
 452         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 453
 454         /* TBICSR p.28 */
 455         TBIReset        = 0x80000000,
 456         TBILoopback     = 0x40000000,
 457         TBINwEnable     = 0x20000000,
 458         TBINwRestart    = 0x10000000,
 459         TBILinkOk       = 0x02000000,
 460         TBINwComplete   = 0x01000000,
 461
 462         /* CPlusCmd p.31 */
 463         EnableBist      = (1 << 15),    // 8168 8101
 464         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 465         Normal_mode     = (1 << 13),    // unused
 466         Force_half_dup  = (1 << 12),    // 8168 8101
 467         Force_rxflow_en = (1 << 11),    // 8168 8101
 468         Force_txflow_en = (1 << 10),    // 8168 8101
 469         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 470         ASF             = (1 << 8),     // 8168 8101
 471         PktCntrDisable  = (1 << 7),     // 8168 8101
 472         Mac_dbgo_sel    = 0x001c,       // 8168
 473         RxVlan          = (1 << 6),
 474         RxChkSum        = (1 << 5),
 475         PCIDAC          = (1 << 4),
 476         PCIMulRW        = (1 << 3),
 477         INTT_0          = 0x0000,       // 8168
 478         INTT_1          = 0x0001,       // 8168
 479         INTT_2          = 0x0002,       // 8168
 480         INTT_3          = 0x0003,       // 8168
 481
 482         /* rtl8169_PHYstatus */
 483         TBI_Enable      = 0x80,
 484         TxFlowCtrl      = 0x40,
 485         RxFlowCtrl      = 0x20,
 486         _1000bpsF       = 0x10,
 487         _100bps         = 0x08,
 488         _10bps          = 0x04,
 489         LinkStatus      = 0x02,
 490         FullDup         = 0x01,
 491
 492         /* _TBICSRBit */
 493         TBILinkOK       = 0x02000000,
 494
 495         /* DumpCounterCommand */
 496         CounterDump     = 0x8,
 497 };
 498
 499 enum rtl_desc_bit {
 500         /* First doubleword. */
 501         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 502         RingEnd         = (1 << 30), /* End of descriptor ring */
 503         FirstFrag       = (1 << 29), /* First segment of a packet */
 504         LastFrag        = (1 << 28), /* Final segment of a packet */
 505 };
 506
 507 /* Generic case. */
 508 enum rtl_tx_desc_bit {
 509         /* First doubleword. */
 510         TD_LSO          = (1 << 27),            /* Large Send Offload */
 511 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 512
 513         /* Second doubleword. */
 514         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 515 };
 516
 517 /* 8169, 8168b and 810x except 8102e. */
 518 enum rtl_tx_desc_bit_0 {
 519         /* First doubleword. */
 520 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 521         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 522         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 523         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 524 };
 525
 526 /* 8102e, 8168c and beyond. */
 527 enum rtl_tx_desc_bit_1 {
 528         /* Second doubleword. */
 529 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 530         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 531         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 532         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 533 };
 534
 535 static const struct rtl_tx_desc_info {
 536         struct {
 537                 u32 udp;
 538                 u32 tcp;
 539         } checksum;
 540         u16 mss_shift;
 541         u16 opts_offset;
 542 } tx_desc_info [] = {
 543         [RTL_TD_0] = {
 544                 .checksum = {
 545                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 546                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 547                 },
 548                 .mss_shift      = TD0_MSS_SHIFT,
 549                 .opts_offset    = 0
 550         },
 551         [RTL_TD_1] = {
 552                 .checksum = {
 553                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 554                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 555                 },
 556                 .mss_shift      = TD1_MSS_SHIFT,
 557                 .opts_offset    = 1
 558         }
 559 };
 560
 561 enum rtl_rx_desc_bit {
 562         /* Rx private */
 563         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 564         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 565
 566 #define RxProtoUDP      (PID1)
 567 #define RxProtoTCP      (PID0)
 568 #define RxProtoIP       (PID1 | PID0)
 569 #define RxProtoMask     RxProtoIP
 570
 571         IPFail          = (1 << 16), /* IP checksum failed */
 572         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 573         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 574         RxVlanTag       = (1 << 16), /* VLAN tag available */
 575 };
 576
 577 #define RsvdMask        0x3fffc000
 578
 579 struct TxDesc {
 580         __le32 opts1;
 581         __le32 opts2;
 582         __le64 addr;
 583 };
 584
 585 struct RxDesc {
 586         __le32 opts1;
 587         __le32 opts2;
 588         __le64 addr;
 589 };
 590
 591 struct ring_info {
 592         struct sk_buff  *skb;
 593         u32             len;
 594         u8              __pad[sizeof(void *) - sizeof(u32)];
 595 };
 596
 597 enum features {
 598         RTL_FEATURE_WOL         = (1 << 0),
 599         RTL_FEATURE_MSI         = (1 << 1),
 600         RTL_FEATURE_GMII        = (1 << 2),
 601 };
 602
 603 struct rtl8169_counters {
 604         __le64  tx_packets;
 605         __le64  rx_packets;
 606         __le64  tx_errors;
 607         __le32  rx_errors;
 608         __le16  rx_missed;
 609         __le16  align_errors;
 610         __le32  tx_one_collision;
 611         __le32  tx_multi_collision;
 612         __le64  rx_unicast;
 613         __le64  rx_broadcast;
 614         __le32  rx_multicast;
 615         __le16  tx_aborted;
 616         __le16  tx_underun;
 617 };
 618
 619 struct rtl8169_private {
 620         void __iomem *mmio_addr;        /* memory map physical address */
 621         struct pci_dev *pci_dev;
 622         struct net_device *dev;
 623         struct napi_struct napi;
 624         spinlock_t lock;
 625         u32 msg_enable;
 626         u16 txd_version;
 627         u16 mac_version;
 628         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 629         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 630         u32 dirty_rx;
 631         u32 dirty_tx;
 632         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 633         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 634         dma_addr_t TxPhyAddr;
 635         dma_addr_t RxPhyAddr;
 636         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 637         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 638         struct timer_list timer;
 639         u16 cp_cmd;
 640         u16 intr_event;
 641         u16 napi_event;
 642         u16 intr_mask;
 643
 644         struct mdio_ops {
 645                 void (*write)(void __iomem *, int, int);
 646                 int (*read)(void __iomem *, int);
 647         } mdio_ops;
 648
 649         struct pll_power_ops {
 650                 void (*down)(struct rtl8169_private *);
 651                 void (*up)(struct rtl8169_private *);
 652         } pll_power_ops;
 653
 654         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 655         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 656         void (*phy_reset_enable)(struct rtl8169_private *tp);
 657         void (*hw_start)(struct net_device *);
 658         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 659         unsigned int (*link_ok)(void __iomem *);
 660         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 661         int pcie_cap;
 662         struct delayed_work task;
 663         unsigned features;
 664
 665         struct mii_if_info mii;
 666         struct rtl8169_counters counters;
 667         u32 saved_wolopts;
 668
 669         const struct firmware *fw;
 670 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 671 };
 672
 673 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 674 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 675 module_param(use_dac, int, 0);
 676 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 677 module_param_named(debug, debug.msg_enable, int, 0);
 678 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 679 MODULE_LICENSE("GPL");
 680 MODULE_VERSION(RTL8169_VERSION);
 681 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 682 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 683 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 684 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 685 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 686
 687 static int rtl8169_open(struct net_device *dev);
 688 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 689                                       struct net_device *dev);
 690 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 691 static int rtl8169_init_ring(struct net_device *dev);
 692 static void rtl_hw_start(struct net_device *dev);
 693 static int rtl8169_close(struct net_device *dev);
 694 static void rtl_set_rx_mode(struct net_device *dev);
 695 static void rtl8169_tx_timeout(struct net_device *dev);
 696 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 697 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 698                                 void __iomem *, u32 budget);
 699 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 700 static void rtl8169_down(struct net_device *dev);
 701 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 702 static int rtl8169_poll(struct napi_struct *napi, int budget);
 703
 704 static const unsigned int rtl8169_rx_config =
 705         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 706
 707 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 708 {
 709         void __iomem *ioaddr = tp->mmio_addr;
 710         int i;
 711
 712         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 713         for (i = 0; i < 20; i++) {
 714                 udelay(100);
 715                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 716                         break;
 717         }
 718         return RTL_R32(OCPDR);
 719 }
 720
 721 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 722 {
 723         void __iomem *ioaddr = tp->mmio_addr;
 724         int i;
 725
 726         RTL_W32(OCPDR, data);
 727         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 728         for (i = 0; i < 20; i++) {
 729                 udelay(100);
 730                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 731                         break;
 732         }
 733 }
 734
 735 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 736 {
 737         void __iomem *ioaddr = tp->mmio_addr;
 738         int i;
 739
 740         RTL_W8(ERIDR, cmd);
 741         RTL_W32(ERIAR, 0x800010e8);
 742         msleep(2);
 743         for (i = 0; i < 5; i++) {
 744                 udelay(100);
 745                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 746                         break;
 747         }
 748
 749         ocp_write(tp, 0x1, 0x30, 0x00000001);
 750 }
 751
 752 #define OOB_CMD_RESET           0x00
 753 #define OOB_CMD_DRIVER_START    0x05
 754 #define OOB_CMD_DRIVER_STOP     0x06
 755
 756 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 757 {
 758         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 759 }
 760
 761 static void rtl8168_driver_start(struct rtl8169_private *tp)
 762 {
 763         u16 reg;
 764         int i;
 765
 766         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 767
 768         reg = rtl8168_get_ocp_reg(tp);
 769
 770         for (i = 0; i < 10; i++) {
 771                 msleep(10);
 772                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 773                         break;
 774         }
 775 }
 776
 777 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 778 {
 779         u16 reg;
 780         int i;
 781
 782         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 783
 784         reg = rtl8168_get_ocp_reg(tp);
 785
 786         for (i = 0; i < 10; i++) {
 787                 msleep(10);
 788                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 789                         break;
 790         }
 791 }
 792
 793 static int r8168dp_check_dash(struct rtl8169_private *tp)
 794 {
 795         u16 reg = rtl8168_get_ocp_reg(tp);
 796
 797         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 798 }
 799
 800 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 801 {
 802         int i;
 803
 804         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 805
 806         for (i = 20; i > 0; i--) {
 807                 /*
 808                  * Check if the RTL8169 has completed writing to the specified
 809                  * MII register.
 810                  */
 811                 if (!(RTL_R32(PHYAR) & 0x80000000))
 812                         break;
 813                 udelay(25);
 814         }
 815         /*
 816          * According to hardware specs a 20us delay is required after write
 817          * complete indication, but before sending next command.
 818          */
 819         udelay(20);
 820 }
 821
 822 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 823 {
 824         int i, value = -1;
 825
 826         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 827
 828         for (i = 20; i > 0; i--) {
 829                 /*
 830                  * Check if the RTL8169 has completed retrieving data from
 831                  * the specified MII register.
 832                  */
 833                 if (RTL_R32(PHYAR) & 0x80000000) {
 834                         value = RTL_R32(PHYAR) & 0xffff;
 835                         break;
 836                 }
 837                 udelay(25);
 838         }
 839         /*
 840          * According to hardware specs a 20us delay is required after read
 841          * complete indication, but before sending next command.
 842          */
 843         udelay(20);
 844
 845         return value;
 846 }
 847
 848 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 849 {
 850         int i;
 851
 852         RTL_W32(OCPDR, data |
 853                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 854         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 855         RTL_W32(EPHY_RXER_NUM, 0);
 856
 857         for (i = 0; i < 100; i++) {
 858                 mdelay(1);
 859                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 860                         break;
 861         }
 862 }
 863
 864 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 865 {
 866         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 867                 (value & OCPDR_DATA_MASK));
 868 }
 869
 870 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 871 {
 872         int i;
 873
 874         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 875
 876         mdelay(1);
 877         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 878         RTL_W32(EPHY_RXER_NUM, 0);
 879
 880         for (i = 0; i < 100; i++) {
 881                 mdelay(1);
 882                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 883                         break;
 884         }
 885
 886         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 887 }
 888
 889 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 890
 891 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 892 {
 893         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 894 }
 895
 896 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 897 {
 898         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 899 }
 900
 901 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 902 {
 903         r8168dp_2_mdio_start(ioaddr);
 904
 905         r8169_mdio_write(ioaddr, reg_addr, value);
 906
 907         r8168dp_2_mdio_stop(ioaddr);
 908 }
 909
 910 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 911 {
 912         int value;
 913
 914         r8168dp_2_mdio_start(ioaddr);
 915
 916         value = r8169_mdio_read(ioaddr, reg_addr);
 917
 918         r8168dp_2_mdio_stop(ioaddr);
 919
 920         return value;
 921 }
 922
 923 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 924 {
 925         tp->mdio_ops.write(tp->mmio_addr, location, val);
 926 }
 927
 928 static int rtl_readphy(struct rtl8169_private *tp, int location)
 929 {
 930         return tp->mdio_ops.read(tp->mmio_addr, location);
 931 }
 932
 933 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 934 {
 935         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 936 }
 937
 938 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 939 {
 940         int val;
 941
 942         val = rtl_readphy(tp, reg_addr);
 943         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 944 }
 945
 946 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 947                            int val)
 948 {
 949         struct rtl8169_private *tp = netdev_priv(dev);
 950
 951         rtl_writephy(tp, location, val);
 952 }
 953
 954 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 955 {
 956         struct rtl8169_private *tp = netdev_priv(dev);
 957
 958         return rtl_readphy(tp, location);
 959 }
 960
 961 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 962 {
 963         unsigned int i;
 964
 965         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 966                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 967
 968         for (i = 0; i < 100; i++) {
 969                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 970                         break;
 971                 udelay(10);
 972         }
 973 }
 974
 975 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 976 {
 977         u16 value = 0xffff;
 978         unsigned int i;
 979
 980         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 981
 982         for (i = 0; i < 100; i++) {
 983                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 984                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 985                         break;
 986                 }
 987                 udelay(10);
 988         }
 989
 990         return value;
 991 }
 992
 993 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 994 {
 995         unsigned int i;
 996
 997         RTL_W32(CSIDR, value);
 998         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 999                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1000
1001         for (i = 0; i < 100; i++) {
1002                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1003                         break;
1004                 udelay(10);
1005         }
1006 }
1007
1008 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1009 {
1010         u32 value = ~0x00;
1011         unsigned int i;
1012
1013         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1014                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1015
1016         for (i = 0; i < 100; i++) {
1017                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1018                         value = RTL_R32(CSIDR);
1019                         break;
1020                 }
1021                 udelay(10);
1022         }
1023
1024         return value;
1025 }
1026
1027 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1028 {
1029         u8 value = 0xff;
1030         unsigned int i;
1031
1032         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1033
1034         for (i = 0; i < 300; i++) {
1035                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1036                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1037                         break;
1038                 }
1039                 udelay(100);
1040         }
1041
1042         return value;
1043 }
1044
1045 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1046 {
1047         RTL_W16(IntrMask, 0x0000);
1048
1049         RTL_W16(IntrStatus, 0xffff);
1050 }
1051
1052 static void rtl8169_asic_down(void __iomem *ioaddr)
1053 {
1054         RTL_W8(ChipCmd, 0x00);
1055         rtl8169_irq_mask_and_ack(ioaddr);
1056         RTL_R16(CPlusCmd);
1057 }
1058
1059 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1060 {
1061         void __iomem *ioaddr = tp->mmio_addr;
1062
1063         return RTL_R32(TBICSR) & TBIReset;
1064 }
1065
1066 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1067 {
1068         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1069 }
1070
1071 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1072 {
1073         return RTL_R32(TBICSR) & TBILinkOk;
1074 }
1075
1076 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1077 {
1078         return RTL_R8(PHYstatus) & LinkStatus;
1079 }
1080
1081 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1082 {
1083         void __iomem *ioaddr = tp->mmio_addr;
1084
1085         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1086 }
1087
1088 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1089 {
1090         unsigned int val;
1091
1092         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1093         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1094 }
1095
1096 static void __rtl8169_check_link_status(struct net_device *dev,
1097                                         struct rtl8169_private *tp,
1098                                         void __iomem *ioaddr, bool pm)
1099 {
1100         unsigned long flags;
1101
1102         spin_lock_irqsave(&tp->lock, flags);
1103         if (tp->link_ok(ioaddr)) {
1104                 /* This is to cancel a scheduled suspend if there's one. */
1105                 if (pm)
1106                         pm_request_resume(&tp->pci_dev->dev);
1107                 netif_carrier_on(dev);
1108                 if (net_ratelimit())
1109                         netif_info(tp, ifup, dev, "link up\n");
1110         } else {
1111                 netif_carrier_off(dev);
1112                 netif_info(tp, ifdown, dev, "link down\n");
1113                 if (pm)
1114                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1115         }
1116         spin_unlock_irqrestore(&tp->lock, flags);
1117 }
1118
1119 static void rtl8169_check_link_status(struct net_device *dev,
1120                                       struct rtl8169_private *tp,
1121                                       void __iomem *ioaddr)
1122 {
1123         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1124 }
1125
1126 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1127
1128 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1129 {
1130         void __iomem *ioaddr = tp->mmio_addr;
1131         u8 options;
1132         u32 wolopts = 0;
1133
1134         options = RTL_R8(Config1);
1135         if (!(options & PMEnable))
1136                 return 0;
1137
1138         options = RTL_R8(Config3);
1139         if (options & LinkUp)
1140                 wolopts |= WAKE_PHY;
1141         if (options & MagicPacket)
1142                 wolopts |= WAKE_MAGIC;
1143
1144         options = RTL_R8(Config5);
1145         if (options & UWF)
1146                 wolopts |= WAKE_UCAST;
1147         if (options & BWF)
1148                 wolopts |= WAKE_BCAST;
1149         if (options & MWF)
1150                 wolopts |= WAKE_MCAST;
1151
1152         return wolopts;
1153 }
1154
1155 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1156 {
1157         struct rtl8169_private *tp = netdev_priv(dev);
1158
1159         spin_lock_irq(&tp->lock);
1160
1161         wol->supported = WAKE_ANY;
1162         wol->wolopts = __rtl8169_get_wol(tp);
1163
1164         spin_unlock_irq(&tp->lock);
1165 }
1166
1167 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1168 {
1169         void __iomem *ioaddr = tp->mmio_addr;
1170         unsigned int i;
1171         static const struct {
1172                 u32 opt;
1173                 u16 reg;
1174                 u8  mask;
1175         } cfg[] = {
1176                 { WAKE_ANY,   Config1, PMEnable },
1177                 { WAKE_PHY,   Config3, LinkUp },
1178                 { WAKE_MAGIC, Config3, MagicPacket },
1179                 { WAKE_UCAST, Config5, UWF },
1180                 { WAKE_BCAST, Config5, BWF },
1181                 { WAKE_MCAST, Config5, MWF },
1182                 { WAKE_ANY,   Config5, LanWake }
1183         };
1184
1185         RTL_W8(Cfg9346, Cfg9346_Unlock);
1186
1187         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1188                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1189                 if (wolopts & cfg[i].opt)
1190                         options |= cfg[i].mask;
1191                 RTL_W8(cfg[i].reg, options);
1192         }
1193
1194         RTL_W8(Cfg9346, Cfg9346_Lock);
1195 }
1196
1197 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1198 {
1199         struct rtl8169_private *tp = netdev_priv(dev);
1200
1201         spin_lock_irq(&tp->lock);
1202
1203         if (wol->wolopts)
1204                 tp->features |= RTL_FEATURE_WOL;
1205         else
1206                 tp->features &= ~RTL_FEATURE_WOL;
1207         __rtl8169_set_wol(tp, wol->wolopts);
1208         spin_unlock_irq(&tp->lock);
1209
1210         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1211
1212         return 0;
1213 }
1214
1215 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1216 {
1217         return rtl_chip_infos[tp->mac_version].fw_name;
1218 }
1219
1220 static void rtl8169_get_drvinfo(struct net_device *dev,
1221                                 struct ethtool_drvinfo *info)
1222 {
1223         struct rtl8169_private *tp = netdev_priv(dev);
1224
1225         strcpy(info->driver, MODULENAME);
1226         strcpy(info->version, RTL8169_VERSION);
1227         strcpy(info->bus_info, pci_name(tp->pci_dev));
1228         strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1229                 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1230 }
1231
1232 static int rtl8169_get_regs_len(struct net_device *dev)
1233 {
1234         return R8169_REGS_SIZE;
1235 }
1236
1237 static int rtl8169_set_speed_tbi(struct net_device *dev,
1238                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1239 {
1240         struct rtl8169_private *tp = netdev_priv(dev);
1241         void __iomem *ioaddr = tp->mmio_addr;
1242         int ret = 0;
1243         u32 reg;
1244
1245         reg = RTL_R32(TBICSR);
1246         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1247             (duplex == DUPLEX_FULL)) {
1248                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1249         } else if (autoneg == AUTONEG_ENABLE)
1250                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1251         else {
1252                 netif_warn(tp, link, dev,
1253                            "incorrect speed setting refused in TBI mode\n");
1254                 ret = -EOPNOTSUPP;
1255         }
1256
1257         return ret;
1258 }
1259
1260 static int rtl8169_set_speed_xmii(struct net_device *dev,
1261                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1262 {
1263         struct rtl8169_private *tp = netdev_priv(dev);
1264         int giga_ctrl, bmcr;
1265         int rc = -EINVAL;
1266
1267         rtl_writephy(tp, 0x1f, 0x0000);
1268
1269         if (autoneg == AUTONEG_ENABLE) {
1270                 int auto_nego;
1271
1272                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1273                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1274                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1275
1276                 if (adv & ADVERTISED_10baseT_Half)
1277                         auto_nego |= ADVERTISE_10HALF;
1278                 if (adv & ADVERTISED_10baseT_Full)
1279                         auto_nego |= ADVERTISE_10FULL;
1280                 if (adv & ADVERTISED_100baseT_Half)
1281                         auto_nego |= ADVERTISE_100HALF;
1282                 if (adv & ADVERTISED_100baseT_Full)
1283                         auto_nego |= ADVERTISE_100FULL;
1284
1285                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1286
1287                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1288                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1289
1290                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1291                 if (tp->mii.supports_gmii) {
1292                         if (adv & ADVERTISED_1000baseT_Half)
1293                                 giga_ctrl |= ADVERTISE_1000HALF;
1294                         if (adv & ADVERTISED_1000baseT_Full)
1295                                 giga_ctrl |= ADVERTISE_1000FULL;
1296                 } else if (adv & (ADVERTISED_1000baseT_Half |
1297                                   ADVERTISED_1000baseT_Full)) {
1298                         netif_info(tp, link, dev,
1299                                    "PHY does not support 1000Mbps\n");
1300                         goto out;
1301                 }
1302
1303                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1304
1305                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1306                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1307         } else {
1308                 giga_ctrl = 0;
1309
1310                 if (speed == SPEED_10)
1311                         bmcr = 0;
1312                 else if (speed == SPEED_100)
1313                         bmcr = BMCR_SPEED100;
1314                 else
1315                         goto out;
1316
1317                 if (duplex == DUPLEX_FULL)
1318                         bmcr |= BMCR_FULLDPLX;
1319         }
1320
1321         rtl_writephy(tp, MII_BMCR, bmcr);
1322
1323         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1324             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1325                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1326                         rtl_writephy(tp, 0x17, 0x2138);
1327                         rtl_writephy(tp, 0x0e, 0x0260);
1328                 } else {
1329                         rtl_writephy(tp, 0x17, 0x2108);
1330                         rtl_writephy(tp, 0x0e, 0x0000);
1331                 }
1332         }
1333
1334         rc = 0;
1335 out:
1336         return rc;
1337 }
1338
1339 static int rtl8169_set_speed(struct net_device *dev,
1340                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1341 {
1342         struct rtl8169_private *tp = netdev_priv(dev);
1343         int ret;
1344
1345         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1346         if (ret < 0)
1347                 goto out;
1348
1349         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1350             (advertising & ADVERTISED_1000baseT_Full)) {
1351                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1352         }
1353 out:
1354         return ret;
1355 }
1356
1357 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1358 {
1359         struct rtl8169_private *tp = netdev_priv(dev);
1360         unsigned long flags;
1361         int ret;
1362
1363         del_timer_sync(&tp->timer);
1364
1365         spin_lock_irqsave(&tp->lock, flags);
1366         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1367                                 cmd->duplex, cmd->advertising);
1368         spin_unlock_irqrestore(&tp->lock, flags);
1369
1370         return ret;
1371 }
1372
1373 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1374 {
1375         if (dev->mtu > TD_MSS_MAX)
1376                 features &= ~NETIF_F_ALL_TSO;
1377
1378         return features;
1379 }
1380
1381 static int rtl8169_set_features(struct net_device *dev, u32 features)
1382 {
1383         struct rtl8169_private *tp = netdev_priv(dev);
1384         void __iomem *ioaddr = tp->mmio_addr;
1385         unsigned long flags;
1386
1387         spin_lock_irqsave(&tp->lock, flags);
1388
1389         if (features & NETIF_F_RXCSUM)
1390                 tp->cp_cmd |= RxChkSum;
1391         else
1392                 tp->cp_cmd &= ~RxChkSum;
1393
1394         if (dev->features & NETIF_F_HW_VLAN_RX)
1395                 tp->cp_cmd |= RxVlan;
1396         else
1397                 tp->cp_cmd &= ~RxVlan;
1398
1399         RTL_W16(CPlusCmd, tp->cp_cmd);
1400         RTL_R16(CPlusCmd);
1401
1402         spin_unlock_irqrestore(&tp->lock, flags);
1403
1404         return 0;
1405 }
1406
1407 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1408                                       struct sk_buff *skb)
1409 {
1410         return (vlan_tx_tag_present(skb)) ?
1411                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1412 }
1413
1414 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1415 {
1416         u32 opts2 = le32_to_cpu(desc->opts2);
1417
1418         if (opts2 & RxVlanTag)
1419                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1420
1421         desc->opts2 = 0;
1422 }
1423
1424 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1425 {
1426         struct rtl8169_private *tp = netdev_priv(dev);
1427         void __iomem *ioaddr = tp->mmio_addr;
1428         u32 status;
1429
1430         cmd->supported =
1431                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1432         cmd->port = PORT_FIBRE;
1433         cmd->transceiver = XCVR_INTERNAL;
1434
1435         status = RTL_R32(TBICSR);
1436         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1437         cmd->autoneg = !!(status & TBINwEnable);
1438
1439         ethtool_cmd_speed_set(cmd, SPEED_1000);
1440         cmd->duplex = DUPLEX_FULL; /* Always set */
1441
1442         return 0;
1443 }
1444
1445 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1446 {
1447         struct rtl8169_private *tp = netdev_priv(dev);
1448
1449         return mii_ethtool_gset(&tp->mii, cmd);
1450 }
1451
1452 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1453 {
1454         struct rtl8169_private *tp = netdev_priv(dev);
1455         unsigned long flags;
1456         int rc;
1457
1458         spin_lock_irqsave(&tp->lock, flags);
1459
1460         rc = tp->get_settings(dev, cmd);
1461
1462         spin_unlock_irqrestore(&tp->lock, flags);
1463         return rc;
1464 }
1465
1466 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1467                              void *p)
1468 {
1469         struct rtl8169_private *tp = netdev_priv(dev);
1470         unsigned long flags;
1471
1472         if (regs->len > R8169_REGS_SIZE)
1473                 regs->len = R8169_REGS_SIZE;
1474
1475         spin_lock_irqsave(&tp->lock, flags);
1476         memcpy_fromio(p, tp->mmio_addr, regs->len);
1477         spin_unlock_irqrestore(&tp->lock, flags);
1478 }
1479
1480 static u32 rtl8169_get_msglevel(struct net_device *dev)
1481 {
1482         struct rtl8169_private *tp = netdev_priv(dev);
1483
1484         return tp->msg_enable;
1485 }
1486
1487 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1488 {
1489         struct rtl8169_private *tp = netdev_priv(dev);
1490
1491         tp->msg_enable = value;
1492 }
1493
1494 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1495         "tx_packets",
1496         "rx_packets",
1497         "tx_errors",
1498         "rx_errors",
1499         "rx_missed",
1500         "align_errors",
1501         "tx_single_collisions",
1502         "tx_multi_collisions",
1503         "unicast",
1504         "broadcast",
1505         "multicast",
1506         "tx_aborted",
1507         "tx_underrun",
1508 };
1509
1510 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1511 {
1512         switch (sset) {
1513         case ETH_SS_STATS:
1514                 return ARRAY_SIZE(rtl8169_gstrings);
1515         default:
1516                 return -EOPNOTSUPP;
1517         }
1518 }
1519
1520 static void rtl8169_update_counters(struct net_device *dev)
1521 {
1522         struct rtl8169_private *tp = netdev_priv(dev);
1523         void __iomem *ioaddr = tp->mmio_addr;
1524         struct device *d = &tp->pci_dev->dev;
1525         struct rtl8169_counters *counters;
1526         dma_addr_t paddr;
1527         u32 cmd;
1528         int wait = 1000;
1529
1530         /*
1531          * Some chips are unable to dump tally counters when the receiver
1532          * is disabled.
1533          */
1534         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1535                 return;
1536
1537         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1538         if (!counters)
1539                 return;
1540
1541         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1542         cmd = (u64)paddr & DMA_BIT_MASK(32);
1543         RTL_W32(CounterAddrLow, cmd);
1544         RTL_W32(CounterAddrLow, cmd | CounterDump);
1545
1546         while (wait--) {
1547                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1548                         memcpy(&tp->counters, counters, sizeof(*counters));
1549                         break;
1550                 }
1551                 udelay(10);
1552         }
1553
1554         RTL_W32(CounterAddrLow, 0);
1555         RTL_W32(CounterAddrHigh, 0);
1556
1557         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1558 }
1559
1560 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1561                                       struct ethtool_stats *stats, u64 *data)
1562 {
1563         struct rtl8169_private *tp = netdev_priv(dev);
1564
1565         ASSERT_RTNL();
1566
1567         rtl8169_update_counters(dev);
1568
1569         data[0] = le64_to_cpu(tp->counters.tx_packets);
1570         data[1] = le64_to_cpu(tp->counters.rx_packets);
1571         data[2] = le64_to_cpu(tp->counters.tx_errors);
1572         data[3] = le32_to_cpu(tp->counters.rx_errors);
1573         data[4] = le16_to_cpu(tp->counters.rx_missed);
1574         data[5] = le16_to_cpu(tp->counters.align_errors);
1575         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1576         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1577         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1578         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1579         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1580         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1581         data[12] = le16_to_cpu(tp->counters.tx_underun);
1582 }
1583
1584 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1585 {
1586         switch(stringset) {
1587         case ETH_SS_STATS:
1588                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1589                 break;
1590         }
1591 }
1592
1593 static const struct ethtool_ops rtl8169_ethtool_ops = {
1594         .get_drvinfo            = rtl8169_get_drvinfo,
1595         .get_regs_len           = rtl8169_get_regs_len,
1596         .get_link               = ethtool_op_get_link,
1597         .get_settings           = rtl8169_get_settings,
1598         .set_settings           = rtl8169_set_settings,
1599         .get_msglevel           = rtl8169_get_msglevel,
1600         .set_msglevel           = rtl8169_set_msglevel,
1601         .get_regs               = rtl8169_get_regs,
1602         .get_wol                = rtl8169_get_wol,
1603         .set_wol                = rtl8169_set_wol,
1604         .get_strings            = rtl8169_get_strings,
1605         .get_sset_count         = rtl8169_get_sset_count,
1606         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1607 };
1608
1609 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1610                                     struct net_device *dev, u8 default_version)
1611 {
1612         void __iomem *ioaddr = tp->mmio_addr;
1613         /*
1614          * The driver currently handles the 8168Bf and the 8168Be identically
1615          * but they can be identified more specifically through the test below
1616          * if needed:
1617          *
1618          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1619          *
1620          * Same thing for the 8101Eb and the 8101Ec:
1621          *
1622          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1623          */
1624         static const struct rtl_mac_info {
1625                 u32 mask;
1626                 u32 val;
1627                 int mac_version;
1628         } mac_info[] = {
1629                 /* 8168E family. */
1630                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1631                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1632                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1633
1634                 /* 8168D family. */
1635                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1636                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1637                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1638
1639                 /* 8168DP family. */
1640                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1641                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1642                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1643
1644                 /* 8168C family. */
1645                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1646                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1647                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1648                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1649                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1650                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1651                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1652                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1653                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1654
1655                 /* 8168B family. */
1656                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1657                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1658                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1659                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1660
1661                 /* 8101 family. */
1662                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1663                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1664                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1665                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1666                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1667                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1668                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1669                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1670                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1671                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1672                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1673                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1674                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1675                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1676                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1677                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1678                 /* FIXME: where did these entries come from ? -- FR */
1679                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1680                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1681
1682                 /* 8110 family. */
1683                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1684                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1685                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1686                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1687                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1688                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1689
1690                 /* Catch-all */
1691                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1692         };
1693         const struct rtl_mac_info *p = mac_info;
1694         u32 reg;
1695
1696         reg = RTL_R32(TxConfig);
1697         while ((reg & p->mask) != p->val)
1698                 p++;
1699         tp->mac_version = p->mac_version;
1700
1701         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1702                 netif_notice(tp, probe, dev,
1703                              "unknown MAC, using family default\n");
1704                 tp->mac_version = default_version;
1705         }
1706 }
1707
1708 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1709 {
1710         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1711 }
1712
1713 struct phy_reg {
1714         u16 reg;
1715         u16 val;
1716 };
1717
1718 static void rtl_writephy_batch(struct rtl8169_private *tp,
1719                                const struct phy_reg *regs, int len)
1720 {
1721         while (len-- > 0) {
1722                 rtl_writephy(tp, regs->reg, regs->val);
1723                 regs++;
1724         }
1725 }
1726
1727 #define PHY_READ                0x00000000
1728 #define PHY_DATA_OR             0x10000000
1729 #define PHY_DATA_AND            0x20000000
1730 #define PHY_BJMPN               0x30000000
1731 #define PHY_READ_EFUSE          0x40000000
1732 #define PHY_READ_MAC_BYTE       0x50000000
1733 #define PHY_WRITE_MAC_BYTE      0x60000000
1734 #define PHY_CLEAR_READCOUNT     0x70000000
1735 #define PHY_WRITE               0x80000000
1736 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1737 #define PHY_COMP_EQ_SKIPN       0xa0000000
1738 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1739 #define PHY_WRITE_PREVIOUS      0xc0000000
1740 #define PHY_SKIPN               0xd0000000
1741 #define PHY_DELAY_MS            0xe0000000
1742 #define PHY_WRITE_ERI_WORD      0xf0000000
1743
1744 static void
1745 rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1746 {
1747         __le32 *phytable = (__le32 *)fw->data;
1748         struct net_device *dev = tp->dev;
1749         size_t index, fw_size = fw->size / sizeof(*phytable);
1750         u32 predata, count;
1751
1752         if (fw->size % sizeof(*phytable)) {
1753                 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1754                 return;
1755         }
1756
1757         for (index = 0; index < fw_size; index++) {
1758                 u32 action = le32_to_cpu(phytable[index]);
1759                 u32 regno = (action & 0x0fff0000) >> 16;
1760
1761                 switch(action & 0xf0000000) {
1762                 case PHY_READ:
1763                 case PHY_DATA_OR:
1764                 case PHY_DATA_AND:
1765                 case PHY_READ_EFUSE:
1766                 case PHY_CLEAR_READCOUNT:
1767                 case PHY_WRITE:
1768                 case PHY_WRITE_PREVIOUS:
1769                 case PHY_DELAY_MS:
1770                         break;
1771
1772                 case PHY_BJMPN:
1773                         if (regno > index) {
1774                                 netif_err(tp, probe, tp->dev,
1775                                           "Out of range of firmware\n");
1776                                 return;
1777                         }
1778                         break;
1779                 case PHY_READCOUNT_EQ_SKIP:
1780                         if (index + 2 >= fw_size) {
1781                                 netif_err(tp, probe, tp->dev,
1782                                           "Out of range of firmware\n");
1783                                 return;
1784                         }
1785                         break;
1786                 case PHY_COMP_EQ_SKIPN:
1787                 case PHY_COMP_NEQ_SKIPN:
1788                 case PHY_SKIPN:
1789                         if (index + 1 + regno >= fw_size) {
1790                                 netif_err(tp, probe, tp->dev,
1791                                           "Out of range of firmware\n");
1792                                 return;
1793                         }
1794                         break;
1795
1796                 case PHY_READ_MAC_BYTE:
1797                 case PHY_WRITE_MAC_BYTE:
1798                 case PHY_WRITE_ERI_WORD:
1799                 default:
1800                         netif_err(tp, probe, tp->dev,
1801                                   "Invalid action 0x%08x\n", action);
1802                         return;
1803                 }
1804         }
1805
1806         predata = 0;
1807         count = 0;
1808
1809         for (index = 0; index < fw_size; ) {
1810                 u32 action = le32_to_cpu(phytable[index]);
1811                 u32 data = action & 0x0000ffff;
1812                 u32 regno = (action & 0x0fff0000) >> 16;
1813
1814                 if (!action)
1815                         break;
1816
1817                 switch(action & 0xf0000000) {
1818                 case PHY_READ:
1819                         predata = rtl_readphy(tp, regno);
1820                         count++;
1821                         index++;
1822                         break;
1823                 case PHY_DATA_OR:
1824                         predata |= data;
1825                         index++;
1826                         break;
1827                 case PHY_DATA_AND:
1828                         predata &= data;
1829                         index++;
1830                         break;
1831                 case PHY_BJMPN:
1832                         index -= regno;
1833                         break;
1834                 case PHY_READ_EFUSE:
1835                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1836                         index++;
1837                         break;
1838                 case PHY_CLEAR_READCOUNT:
1839                         count = 0;
1840                         index++;
1841                         break;
1842                 case PHY_WRITE:
1843                         rtl_writephy(tp, regno, data);
1844                         index++;
1845                         break;
1846                 case PHY_READCOUNT_EQ_SKIP:
1847                         index += (count == data) ? 2 : 1;
1848                         break;
1849                 case PHY_COMP_EQ_SKIPN:
1850                         if (predata == data)
1851                                 index += regno;
1852                         index++;
1853                         break;
1854                 case PHY_COMP_NEQ_SKIPN:
1855                         if (predata != data)
1856                                 index += regno;
1857                         index++;
1858                         break;
1859                 case PHY_WRITE_PREVIOUS:
1860                         rtl_writephy(tp, regno, predata);
1861                         index++;
1862                         break;
1863                 case PHY_SKIPN:
1864                         index += regno + 1;
1865                         break;
1866                 case PHY_DELAY_MS:
1867                         mdelay(data);
1868                         index++;
1869                         break;
1870
1871                 case PHY_READ_MAC_BYTE:
1872                 case PHY_WRITE_MAC_BYTE:
1873                 case PHY_WRITE_ERI_WORD:
1874                 default:
1875                         BUG();
1876                 }
1877         }
1878 }
1879
1880 static void rtl_release_firmware(struct rtl8169_private *tp)
1881 {
1882         if (!IS_ERR_OR_NULL(tp->fw))
1883                 release_firmware(tp->fw);
1884         tp->fw = RTL_FIRMWARE_UNKNOWN;
1885 }
1886
1887 static void rtl_apply_firmware(struct rtl8169_private *tp)
1888 {
1889         const struct firmware *fw = tp->fw;
1890
1891         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1892         if (!IS_ERR_OR_NULL(fw))
1893                 rtl_phy_write_fw(tp, fw);
1894 }
1895
1896 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1897 {
1898         if (rtl_readphy(tp, reg) != val)
1899                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1900         else
1901                 rtl_apply_firmware(tp);
1902 }
1903
1904 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1905 {
1906         static const struct phy_reg phy_reg_init[] = {
1907                 { 0x1f, 0x0001 },
1908                 { 0x06, 0x006e },
1909                 { 0x08, 0x0708 },
1910                 { 0x15, 0x4000 },
1911                 { 0x18, 0x65c7 },
1912
1913                 { 0x1f, 0x0001 },
1914                 { 0x03, 0x00a1 },
1915                 { 0x02, 0x0008 },
1916                 { 0x01, 0x0120 },
1917                 { 0x00, 0x1000 },
1918                 { 0x04, 0x0800 },
1919                 { 0x04, 0x0000 },
1920
1921                 { 0x03, 0xff41 },
1922                 { 0x02, 0xdf60 },
1923                 { 0x01, 0x0140 },
1924                 { 0x00, 0x0077 },
1925                 { 0x04, 0x7800 },
1926                 { 0x04, 0x7000 },
1927
1928                 { 0x03, 0x802f },
1929                 { 0x02, 0x4f02 },
1930                 { 0x01, 0x0409 },
1931                 { 0x00, 0xf0f9 },
1932                 { 0x04, 0x9800 },
1933                 { 0x04, 0x9000 },
1934
1935                 { 0x03, 0xdf01 },
1936                 { 0x02, 0xdf20 },
1937                 { 0x01, 0xff95 },
1938                 { 0x00, 0xba00 },
1939                 { 0x04, 0xa800 },
1940                 { 0x04, 0xa000 },
1941
1942                 { 0x03, 0xff41 },
1943                 { 0x02, 0xdf20 },
1944                 { 0x01, 0x0140 },
1945                 { 0x00, 0x00bb },
1946                 { 0x04, 0xb800 },
1947                 { 0x04, 0xb000 },
1948
1949                 { 0x03, 0xdf41 },
1950                 { 0x02, 0xdc60 },
1951                 { 0x01, 0x6340 },
1952                 { 0x00, 0x007d },
1953                 { 0x04, 0xd800 },
1954                 { 0x04, 0xd000 },
1955
1956                 { 0x03, 0xdf01 },
1957                 { 0x02, 0xdf20 },
1958                 { 0x01, 0x100a },
1959                 { 0x00, 0xa0ff },
1960                 { 0x04, 0xf800 },
1961                 { 0x04, 0xf000 },
1962
1963                 { 0x1f, 0x0000 },
1964                 { 0x0b, 0x0000 },
1965                 { 0x00, 0x9200 }
1966         };
1967
1968         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1969 }
1970
1971 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
1972 {
1973         static const struct phy_reg phy_reg_init[] = {
1974                 { 0x1f, 0x0002 },
1975                 { 0x01, 0x90d0 },
1976                 { 0x1f, 0x0000 }
1977         };
1978
1979         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1980 }
1981
1982 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
1983 {
1984         struct pci_dev *pdev = tp->pci_dev;
1985         u16 vendor_id, device_id;
1986
1987         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1988         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1989
1990         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1991                 return;
1992
1993         rtl_writephy(tp, 0x1f, 0x0001);
1994         rtl_writephy(tp, 0x10, 0xf01b);
1995         rtl_writephy(tp, 0x1f, 0x0000);
1996 }
1997
1998 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
1999 {
2000         static const struct phy_reg phy_reg_init[] = {
2001                 { 0x1f, 0x0001 },
2002                 { 0x04, 0x0000 },
2003                 { 0x03, 0x00a1 },
2004                 { 0x02, 0x0008 },
2005                 { 0x01, 0x0120 },
2006                 { 0x00, 0x1000 },
2007                 { 0x04, 0x0800 },
2008                 { 0x04, 0x9000 },
2009                 { 0x03, 0x802f },
2010                 { 0x02, 0x4f02 },
2011                 { 0x01, 0x0409 },
2012                 { 0x00, 0xf099 },
2013                 { 0x04, 0x9800 },
2014                 { 0x04, 0xa000 },
2015                 { 0x03, 0xdf01 },
2016                 { 0x02, 0xdf20 },
2017                 { 0x01, 0xff95 },
2018                 { 0x00, 0xba00 },
2019                 { 0x04, 0xa800 },
2020                 { 0x04, 0xf000 },
2021                 { 0x03, 0xdf01 },
2022                 { 0x02, 0xdf20 },
2023                 { 0x01, 0x101a },
2024                 { 0x00, 0xa0ff },
2025                 { 0x04, 0xf800 },
2026                 { 0x04, 0x0000 },
2027                 { 0x1f, 0x0000 },
2028
2029                 { 0x1f, 0x0001 },
2030                 { 0x10, 0xf41b },
2031                 { 0x14, 0xfb54 },
2032                 { 0x18, 0xf5c7 },
2033                 { 0x1f, 0x0000 },
2034
2035                 { 0x1f, 0x0001 },
2036                 { 0x17, 0x0cc0 },
2037                 { 0x1f, 0x0000 }
2038         };
2039
2040         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2041
2042         rtl8169scd_hw_phy_config_quirk(tp);
2043 }
2044
2045 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2046 {
2047         static const struct phy_reg phy_reg_init[] = {
2048                 { 0x1f, 0x0001 },
2049                 { 0x04, 0x0000 },
2050                 { 0x03, 0x00a1 },
2051                 { 0x02, 0x0008 },
2052                 { 0x01, 0x0120 },
2053                 { 0x00, 0x1000 },
2054                 { 0x04, 0x0800 },
2055                 { 0x04, 0x9000 },
2056                 { 0x03, 0x802f },
2057                 { 0x02, 0x4f02 },
2058                 { 0x01, 0x0409 },
2059                 { 0x00, 0xf099 },
2060                 { 0x04, 0x9800 },
2061                 { 0x04, 0xa000 },
2062                 { 0x03, 0xdf01 },
2063                 { 0x02, 0xdf20 },
2064                 { 0x01, 0xff95 },
2065                 { 0x00, 0xba00 },
2066                 { 0x04, 0xa800 },
2067                 { 0x04, 0xf000 },
2068                 { 0x03, 0xdf01 },
2069                 { 0x02, 0xdf20 },
2070                 { 0x01, 0x101a },
2071                 { 0x00, 0xa0ff },
2072                 { 0x04, 0xf800 },
2073                 { 0x04, 0x0000 },
2074                 { 0x1f, 0x0000 },
2075
2076                 { 0x1f, 0x0001 },
2077                 { 0x0b, 0x8480 },
2078                 { 0x1f, 0x0000 },
2079
2080                 { 0x1f, 0x0001 },
2081                 { 0x18, 0x67c7 },
2082                 { 0x04, 0x2000 },
2083                 { 0x03, 0x002f },
2084                 { 0x02, 0x4360 },
2085                 { 0x01, 0x0109 },
2086                 { 0x00, 0x3022 },
2087                 { 0x04, 0x2800 },
2088                 { 0x1f, 0x0000 },
2089
2090                 { 0x1f, 0x0001 },
2091                 { 0x17, 0x0cc0 },
2092                 { 0x1f, 0x0000 }
2093         };
2094
2095         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2096 }
2097
2098 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2099 {
2100         static const struct phy_reg phy_reg_init[] = {
2101                 { 0x10, 0xf41b },
2102                 { 0x1f, 0x0000 }
2103         };
2104
2105         rtl_writephy(tp, 0x1f, 0x0001);
2106         rtl_patchphy(tp, 0x16, 1 << 0);
2107
2108         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2109 }
2110
2111 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2112 {
2113         static const struct phy_reg phy_reg_init[] = {
2114                 { 0x1f, 0x0001 },
2115                 { 0x10, 0xf41b },
2116                 { 0x1f, 0x0000 }
2117         };
2118
2119         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2120 }
2121
2122 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2123 {
2124         static const struct phy_reg phy_reg_init[] = {
2125                 { 0x1f, 0x0000 },
2126                 { 0x1d, 0x0f00 },
2127                 { 0x1f, 0x0002 },
2128                 { 0x0c, 0x1ec8 },
2129                 { 0x1f, 0x0000 }
2130         };
2131
2132         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2133 }
2134
2135 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2136 {
2137         static const struct phy_reg phy_reg_init[] = {
2138                 { 0x1f, 0x0001 },
2139                 { 0x1d, 0x3d98 },
2140                 { 0x1f, 0x0000 }
2141         };
2142
2143         rtl_writephy(tp, 0x1f, 0x0000);
2144         rtl_patchphy(tp, 0x14, 1 << 5);
2145         rtl_patchphy(tp, 0x0d, 1 << 5);
2146
2147         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2148 }
2149
2150 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2151 {
2152         static const struct phy_reg phy_reg_init[] = {
2153                 { 0x1f, 0x0001 },
2154                 { 0x12, 0x2300 },
2155                 { 0x1f, 0x0002 },
2156                 { 0x00, 0x88d4 },
2157                 { 0x01, 0x82b1 },
2158                 { 0x03, 0x7002 },
2159                 { 0x08, 0x9e30 },
2160                 { 0x09, 0x01f0 },
2161                 { 0x0a, 0x5500 },
2162                 { 0x0c, 0x00c8 },
2163                 { 0x1f, 0x0003 },
2164                 { 0x12, 0xc096 },
2165                 { 0x16, 0x000a },
2166                 { 0x1f, 0x0000 },
2167                 { 0x1f, 0x0000 },
2168                 { 0x09, 0x2000 },
2169                 { 0x09, 0x0000 }
2170         };
2171
2172         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2173
2174         rtl_patchphy(tp, 0x14, 1 << 5);
2175         rtl_patchphy(tp, 0x0d, 1 << 5);
2176         rtl_writephy(tp, 0x1f, 0x0000);
2177 }
2178
2179 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2180 {
2181         static const struct phy_reg phy_reg_init[] = {
2182                 { 0x1f, 0x0001 },
2183                 { 0x12, 0x2300 },
2184                 { 0x03, 0x802f },
2185                 { 0x02, 0x4f02 },
2186                 { 0x01, 0x0409 },
2187                 { 0x00, 0xf099 },
2188                 { 0x04, 0x9800 },
2189                 { 0x04, 0x9000 },
2190                 { 0x1d, 0x3d98 },
2191                 { 0x1f, 0x0002 },
2192                 { 0x0c, 0x7eb8 },
2193                 { 0x06, 0x0761 },
2194                 { 0x1f, 0x0003 },
2195                 { 0x16, 0x0f0a },
2196                 { 0x1f, 0x0000 }
2197         };
2198
2199         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2200
2201         rtl_patchphy(tp, 0x16, 1 << 0);
2202         rtl_patchphy(tp, 0x14, 1 << 5);
2203         rtl_patchphy(tp, 0x0d, 1 << 5);
2204         rtl_writephy(tp, 0x1f, 0x0000);
2205 }
2206
2207 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2208 {
2209         static const struct phy_reg phy_reg_init[] = {
2210                 { 0x1f, 0x0001 },
2211                 { 0x12, 0x2300 },
2212                 { 0x1d, 0x3d98 },
2213                 { 0x1f, 0x0002 },
2214                 { 0x0c, 0x7eb8 },
2215                 { 0x06, 0x5461 },
2216                 { 0x1f, 0x0003 },
2217                 { 0x16, 0x0f0a },
2218                 { 0x1f, 0x0000 }
2219         };
2220
2221         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2222
2223         rtl_patchphy(tp, 0x16, 1 << 0);
2224         rtl_patchphy(tp, 0x14, 1 << 5);
2225         rtl_patchphy(tp, 0x0d, 1 << 5);
2226         rtl_writephy(tp, 0x1f, 0x0000);
2227 }
2228
2229 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2230 {
2231         rtl8168c_3_hw_phy_config(tp);
2232 }
2233
2234 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2235 {
2236         static const struct phy_reg phy_reg_init_0[] = {
2237                 /* Channel Estimation */
2238                 { 0x1f, 0x0001 },
2239                 { 0x06, 0x4064 },
2240                 { 0x07, 0x2863 },
2241                 { 0x08, 0x059c },
2242                 { 0x09, 0x26b4 },
2243                 { 0x0a, 0x6a19 },
2244                 { 0x0b, 0xdcc8 },
2245                 { 0x10, 0xf06d },
2246                 { 0x14, 0x7f68 },
2247                 { 0x18, 0x7fd9 },
2248                 { 0x1c, 0xf0ff },
2249                 { 0x1d, 0x3d9c },
2250                 { 0x1f, 0x0003 },
2251                 { 0x12, 0xf49f },
2252                 { 0x13, 0x070b },
2253                 { 0x1a, 0x05ad },
2254                 { 0x14, 0x94c0 },
2255
2256                 /*
2257                  * Tx Error Issue
2258                  * Enhance line driver power
2259                  */
2260                 { 0x1f, 0x0002 },
2261                 { 0x06, 0x5561 },
2262                 { 0x1f, 0x0005 },
2263                 { 0x05, 0x8332 },
2264                 { 0x06, 0x5561 },
2265
2266                 /*
2267                  * Can not link to 1Gbps with bad cable
2268                  * Decrease SNR threshold form 21.07dB to 19.04dB
2269                  */
2270                 { 0x1f, 0x0001 },
2271                 { 0x17, 0x0cc0 },
2272
2273                 { 0x1f, 0x0000 },
2274                 { 0x0d, 0xf880 }
2275         };
2276         void __iomem *ioaddr = tp->mmio_addr;
2277
2278         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2279
2280         /*
2281          * Rx Error Issue
2282          * Fine Tune Switching regulator parameter
2283          */
2284         rtl_writephy(tp, 0x1f, 0x0002);
2285         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2286         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2287
2288         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2289                 static const struct phy_reg phy_reg_init[] = {
2290                         { 0x1f, 0x0002 },
2291                         { 0x05, 0x669a },
2292                         { 0x1f, 0x0005 },
2293                         { 0x05, 0x8330 },
2294                         { 0x06, 0x669a },
2295                         { 0x1f, 0x0002 }
2296                 };
2297                 int val;
2298
2299                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2300
2301                 val = rtl_readphy(tp, 0x0d);
2302
2303                 if ((val & 0x00ff) != 0x006c) {
2304                         static const u32 set[] = {
2305                                 0x0065, 0x0066, 0x0067, 0x0068,
2306                                 0x0069, 0x006a, 0x006b, 0x006c
2307                         };
2308                         int i;
2309
2310                         rtl_writephy(tp, 0x1f, 0x0002);
2311
2312                         val &= 0xff00;
2313                         for (i = 0; i < ARRAY_SIZE(set); i++)
2314                                 rtl_writephy(tp, 0x0d, val | set[i]);
2315                 }
2316         } else {
2317                 static const struct phy_reg phy_reg_init[] = {
2318                         { 0x1f, 0x0002 },
2319                         { 0x05, 0x6662 },
2320                         { 0x1f, 0x0005 },
2321                         { 0x05, 0x8330 },
2322                         { 0x06, 0x6662 }
2323                 };
2324
2325                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2326         }
2327
2328         /* RSET couple improve */
2329         rtl_writephy(tp, 0x1f, 0x0002);
2330         rtl_patchphy(tp, 0x0d, 0x0300);
2331         rtl_patchphy(tp, 0x0f, 0x0010);
2332
2333         /* Fine tune PLL performance */
2334         rtl_writephy(tp, 0x1f, 0x0002);
2335         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2336         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2337
2338         rtl_writephy(tp, 0x1f, 0x0005);
2339         rtl_writephy(tp, 0x05, 0x001b);
2340
2341         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2342
2343         rtl_writephy(tp, 0x1f, 0x0000);
2344 }
2345
2346 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2347 {
2348         static const struct phy_reg phy_reg_init_0[] = {
2349                 /* Channel Estimation */
2350                 { 0x1f, 0x0001 },
2351                 { 0x06, 0x4064 },
2352                 { 0x07, 0x2863 },
2353                 { 0x08, 0x059c },
2354                 { 0x09, 0x26b4 },
2355                 { 0x0a, 0x6a19 },
2356                 { 0x0b, 0xdcc8 },
2357                 { 0x10, 0xf06d },
2358                 { 0x14, 0x7f68 },
2359                 { 0x18, 0x7fd9 },
2360                 { 0x1c, 0xf0ff },
2361                 { 0x1d, 0x3d9c },
2362                 { 0x1f, 0x0003 },
2363                 { 0x12, 0xf49f },
2364                 { 0x13, 0x070b },
2365                 { 0x1a, 0x05ad },
2366                 { 0x14, 0x94c0 },
2367
2368                 /*
2369                  * Tx Error Issue
2370                  * Enhance line driver power
2371                  */
2372                 { 0x1f, 0x0002 },
2373                 { 0x06, 0x5561 },
2374                 { 0x1f, 0x0005 },
2375                 { 0x05, 0x8332 },
2376                 { 0x06, 0x5561 },
2377
2378                 /*
2379                  * Can not link to 1Gbps with bad cable
2380                  * Decrease SNR threshold form 21.07dB to 19.04dB
2381                  */
2382                 { 0x1f, 0x0001 },
2383                 { 0x17, 0x0cc0 },
2384
2385                 { 0x1f, 0x0000 },
2386                 { 0x0d, 0xf880 }
2387         };
2388         void __iomem *ioaddr = tp->mmio_addr;
2389
2390         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2391
2392         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2393                 static const struct phy_reg phy_reg_init[] = {
2394                         { 0x1f, 0x0002 },
2395                         { 0x05, 0x669a },
2396                         { 0x1f, 0x0005 },
2397                         { 0x05, 0x8330 },
2398                         { 0x06, 0x669a },
2399
2400                         { 0x1f, 0x0002 }
2401                 };
2402                 int val;
2403
2404                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2405
2406                 val = rtl_readphy(tp, 0x0d);
2407                 if ((val & 0x00ff) != 0x006c) {
2408                         static const u32 set[] = {
2409                                 0x0065, 0x0066, 0x0067, 0x0068,
2410                                 0x0069, 0x006a, 0x006b, 0x006c
2411                         };
2412                         int i;
2413
2414                         rtl_writephy(tp, 0x1f, 0x0002);
2415
2416                         val &= 0xff00;
2417                         for (i = 0; i < ARRAY_SIZE(set); i++)
2418                                 rtl_writephy(tp, 0x0d, val | set[i]);
2419                 }
2420         } else {
2421                 static const struct phy_reg phy_reg_init[] = {
2422                         { 0x1f, 0x0002 },
2423                         { 0x05, 0x2642 },
2424                         { 0x1f, 0x0005 },
2425                         { 0x05, 0x8330 },
2426                         { 0x06, 0x2642 }
2427                 };
2428
2429                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2430         }
2431
2432         /* Fine tune PLL performance */
2433         rtl_writephy(tp, 0x1f, 0x0002);
2434         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2435         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2436
2437         /* Switching regulator Slew rate */
2438         rtl_writephy(tp, 0x1f, 0x0002);
2439         rtl_patchphy(tp, 0x0f, 0x0017);
2440
2441         rtl_writephy(tp, 0x1f, 0x0005);
2442         rtl_writephy(tp, 0x05, 0x001b);
2443
2444         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2445
2446         rtl_writephy(tp, 0x1f, 0x0000);
2447 }
2448
2449 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2450 {
2451         static const struct phy_reg phy_reg_init[] = {
2452                 { 0x1f, 0x0002 },
2453                 { 0x10, 0x0008 },
2454                 { 0x0d, 0x006c },
2455
2456                 { 0x1f, 0x0000 },
2457                 { 0x0d, 0xf880 },
2458
2459                 { 0x1f, 0x0001 },
2460                 { 0x17, 0x0cc0 },
2461
2462                 { 0x1f, 0x0001 },
2463                 { 0x0b, 0xa4d8 },
2464                 { 0x09, 0x281c },
2465                 { 0x07, 0x2883 },
2466                 { 0x0a, 0x6b35 },
2467                 { 0x1d, 0x3da4 },
2468                 { 0x1c, 0xeffd },
2469                 { 0x14, 0x7f52 },
2470                 { 0x18, 0x7fc6 },
2471                 { 0x08, 0x0601 },
2472                 { 0x06, 0x4063 },
2473                 { 0x10, 0xf074 },
2474                 { 0x1f, 0x0003 },
2475                 { 0x13, 0x0789 },
2476                 { 0x12, 0xf4bd },
2477                 { 0x1a, 0x04fd },
2478                 { 0x14, 0x84b0 },
2479                 { 0x1f, 0x0000 },
2480                 { 0x00, 0x9200 },
2481
2482                 { 0x1f, 0x0005 },
2483                 { 0x01, 0x0340 },
2484                 { 0x1f, 0x0001 },
2485                 { 0x04, 0x4000 },
2486                 { 0x03, 0x1d21 },
2487                 { 0x02, 0x0c32 },
2488                 { 0x01, 0x0200 },
2489                 { 0x00, 0x5554 },
2490                 { 0x04, 0x4800 },
2491                 { 0x04, 0x4000 },
2492                 { 0x04, 0xf000 },
2493                 { 0x03, 0xdf01 },
2494                 { 0x02, 0xdf20 },
2495                 { 0x01, 0x101a },
2496                 { 0x00, 0xa0ff },
2497                 { 0x04, 0xf800 },
2498                 { 0x04, 0xf000 },
2499                 { 0x1f, 0x0000 },
2500
2501                 { 0x1f, 0x0007 },
2502                 { 0x1e, 0x0023 },
2503                 { 0x16, 0x0000 },
2504                 { 0x1f, 0x0000 }
2505         };
2506
2507         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2508 }
2509
2510 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2511 {
2512         static const struct phy_reg phy_reg_init[] = {
2513                 { 0x1f, 0x0001 },
2514                 { 0x17, 0x0cc0 },
2515
2516                 { 0x1f, 0x0007 },
2517                 { 0x1e, 0x002d },
2518                 { 0x18, 0x0040 },
2519                 { 0x1f, 0x0000 }
2520         };
2521
2522         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2523         rtl_patchphy(tp, 0x0d, 1 << 5);
2524 }
2525
2526 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2527 {
2528         static const struct phy_reg phy_reg_init[] = {
2529                 /* Enable Delay cap */
2530                 { 0x1f, 0x0005 },
2531                 { 0x05, 0x8b80 },
2532                 { 0x06, 0xc896 },
2533                 { 0x1f, 0x0000 },
2534
2535                 /* Channel estimation fine tune */
2536                 { 0x1f, 0x0001 },
2537                 { 0x0b, 0x6c20 },
2538                 { 0x07, 0x2872 },
2539                 { 0x1c, 0xefff },
2540                 { 0x1f, 0x0003 },
2541                 { 0x14, 0x6420 },
2542                 { 0x1f, 0x0000 },
2543
2544                 /* Update PFM & 10M TX idle timer */
2545                 { 0x1f, 0x0007 },
2546                 { 0x1e, 0x002f },
2547                 { 0x15, 0x1919 },
2548                 { 0x1f, 0x0000 },
2549
2550                 { 0x1f, 0x0007 },
2551                 { 0x1e, 0x00ac },
2552                 { 0x18, 0x0006 },
2553                 { 0x1f, 0x0000 }
2554         };
2555
2556         rtl_apply_firmware(tp);
2557
2558         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2559
2560         /* DCO enable for 10M IDLE Power */
2561         rtl_writephy(tp, 0x1f, 0x0007);
2562         rtl_writephy(tp, 0x1e, 0x0023);
2563         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2564         rtl_writephy(tp, 0x1f, 0x0000);
2565
2566         /* For impedance matching */
2567         rtl_writephy(tp, 0x1f, 0x0002);
2568         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2569         rtl_writephy(tp, 0x1f, 0x0000);
2570
2571         /* PHY auto speed down */
2572         rtl_writephy(tp, 0x1f, 0x0007);
2573         rtl_writephy(tp, 0x1e, 0x002d);
2574         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2575         rtl_writephy(tp, 0x1f, 0x0000);
2576         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2577
2578         rtl_writephy(tp, 0x1f, 0x0005);
2579         rtl_writephy(tp, 0x05, 0x8b86);
2580         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2581         rtl_writephy(tp, 0x1f, 0x0000);
2582
2583         rtl_writephy(tp, 0x1f, 0x0005);
2584         rtl_writephy(tp, 0x05, 0x8b85);
2585         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2586         rtl_writephy(tp, 0x1f, 0x0007);
2587         rtl_writephy(tp, 0x1e, 0x0020);
2588         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2589         rtl_writephy(tp, 0x1f, 0x0006);
2590         rtl_writephy(tp, 0x00, 0x5a00);
2591         rtl_writephy(tp, 0x1f, 0x0000);
2592         rtl_writephy(tp, 0x0d, 0x0007);
2593         rtl_writephy(tp, 0x0e, 0x003c);
2594         rtl_writephy(tp, 0x0d, 0x4007);
2595         rtl_writephy(tp, 0x0e, 0x0000);
2596         rtl_writephy(tp, 0x0d, 0x0000);
2597 }
2598
2599 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2600 {
2601         static const struct phy_reg phy_reg_init[] = {
2602                 { 0x1f, 0x0003 },
2603                 { 0x08, 0x441d },
2604                 { 0x01, 0x9100 },
2605                 { 0x1f, 0x0000 }
2606         };
2607
2608         rtl_writephy(tp, 0x1f, 0x0000);
2609         rtl_patchphy(tp, 0x11, 1 << 12);
2610         rtl_patchphy(tp, 0x19, 1 << 13);
2611         rtl_patchphy(tp, 0x10, 1 << 15);
2612
2613         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2614 }
2615
2616 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2617 {
2618         static const struct phy_reg phy_reg_init[] = {
2619                 { 0x1f, 0x0005 },
2620                 { 0x1a, 0x0000 },
2621                 { 0x1f, 0x0000 },
2622
2623                 { 0x1f, 0x0004 },
2624                 { 0x1c, 0x0000 },
2625                 { 0x1f, 0x0000 },
2626
2627                 { 0x1f, 0x0001 },
2628                 { 0x15, 0x7701 },
2629                 { 0x1f, 0x0000 }
2630         };
2631
2632         /* Disable ALDPS before ram code */
2633         rtl_writephy(tp, 0x1f, 0x0000);
2634         rtl_writephy(tp, 0x18, 0x0310);
2635         msleep(100);
2636
2637         rtl_apply_firmware(tp);
2638
2639         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2640 }
2641
2642 static void rtl_hw_phy_config(struct net_device *dev)
2643 {
2644         struct rtl8169_private *tp = netdev_priv(dev);
2645
2646         rtl8169_print_mac_version(tp);
2647
2648         switch (tp->mac_version) {
2649         case RTL_GIGA_MAC_VER_01:
2650                 break;
2651         case RTL_GIGA_MAC_VER_02:
2652         case RTL_GIGA_MAC_VER_03:
2653                 rtl8169s_hw_phy_config(tp);
2654                 break;
2655         case RTL_GIGA_MAC_VER_04:
2656                 rtl8169sb_hw_phy_config(tp);
2657                 break;
2658         case RTL_GIGA_MAC_VER_05:
2659                 rtl8169scd_hw_phy_config(tp);
2660                 break;
2661         case RTL_GIGA_MAC_VER_06:
2662                 rtl8169sce_hw_phy_config(tp);
2663                 break;
2664         case RTL_GIGA_MAC_VER_07:
2665         case RTL_GIGA_MAC_VER_08:
2666         case RTL_GIGA_MAC_VER_09:
2667                 rtl8102e_hw_phy_config(tp);
2668                 break;
2669         case RTL_GIGA_MAC_VER_11:
2670                 rtl8168bb_hw_phy_config(tp);
2671                 break;
2672         case RTL_GIGA_MAC_VER_12:
2673                 rtl8168bef_hw_phy_config(tp);
2674                 break;
2675         case RTL_GIGA_MAC_VER_17:
2676                 rtl8168bef_hw_phy_config(tp);
2677                 break;
2678         case RTL_GIGA_MAC_VER_18:
2679                 rtl8168cp_1_hw_phy_config(tp);
2680                 break;
2681         case RTL_GIGA_MAC_VER_19:
2682                 rtl8168c_1_hw_phy_config(tp);
2683                 break;
2684         case RTL_GIGA_MAC_VER_20:
2685                 rtl8168c_2_hw_phy_config(tp);
2686                 break;
2687         case RTL_GIGA_MAC_VER_21:
2688                 rtl8168c_3_hw_phy_config(tp);
2689                 break;
2690         case RTL_GIGA_MAC_VER_22:
2691                 rtl8168c_4_hw_phy_config(tp);
2692                 break;
2693         case RTL_GIGA_MAC_VER_23:
2694         case RTL_GIGA_MAC_VER_24:
2695                 rtl8168cp_2_hw_phy_config(tp);
2696                 break;
2697         case RTL_GIGA_MAC_VER_25:
2698                 rtl8168d_1_hw_phy_config(tp);
2699                 break;
2700         case RTL_GIGA_MAC_VER_26:
2701                 rtl8168d_2_hw_phy_config(tp);
2702                 break;
2703         case RTL_GIGA_MAC_VER_27:
2704                 rtl8168d_3_hw_phy_config(tp);
2705                 break;
2706         case RTL_GIGA_MAC_VER_28:
2707                 rtl8168d_4_hw_phy_config(tp);
2708                 break;
2709         case RTL_GIGA_MAC_VER_29:
2710         case RTL_GIGA_MAC_VER_30:
2711                 rtl8105e_hw_phy_config(tp);
2712                 break;
2713         case RTL_GIGA_MAC_VER_31:
2714                 /* None. */
2715                 break;
2716         case RTL_GIGA_MAC_VER_32:
2717         case RTL_GIGA_MAC_VER_33:
2718                 rtl8168e_hw_phy_config(tp);
2719                 break;
2720
2721         default:
2722                 break;
2723         }
2724 }
2725
2726 static void rtl8169_phy_timer(unsigned long __opaque)
2727 {
2728         struct net_device *dev = (struct net_device *)__opaque;
2729         struct rtl8169_private *tp = netdev_priv(dev);
2730         struct timer_list *timer = &tp->timer;
2731         void __iomem *ioaddr = tp->mmio_addr;
2732         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2733
2734         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2735
2736         spin_lock_irq(&tp->lock);
2737
2738         if (tp->phy_reset_pending(tp)) {
2739                 /*
2740                  * A busy loop could burn quite a few cycles on nowadays CPU.
2741                  * Let's delay the execution of the timer for a few ticks.
2742                  */
2743                 timeout = HZ/10;
2744                 goto out_mod_timer;
2745         }
2746
2747         if (tp->link_ok(ioaddr))
2748                 goto out_unlock;
2749
2750         netif_warn(tp, link, dev, "PHY reset until link up\n");
2751
2752         tp->phy_reset_enable(tp);
2753
2754 out_mod_timer:
2755         mod_timer(timer, jiffies + timeout);
2756 out_unlock:
2757         spin_unlock_irq(&tp->lock);
2758 }
2759
2760 #ifdef CONFIG_NET_POLL_CONTROLLER
2761 /*
2762  * Polling 'interrupt' - used by things like netconsole to send skbs
2763  * without having to re-enable interrupts. It's not called while
2764  * the interrupt routine is executing.
2765  */
2766 static void rtl8169_netpoll(struct net_device *dev)
2767 {
2768         struct rtl8169_private *tp = netdev_priv(dev);
2769         struct pci_dev *pdev = tp->pci_dev;
2770
2771         disable_irq(pdev->irq);
2772         rtl8169_interrupt(pdev->irq, dev);
2773         enable_irq(pdev->irq);
2774 }
2775 #endif
2776
2777 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2778                                   void __iomem *ioaddr)
2779 {
2780         iounmap(ioaddr);
2781         pci_release_regions(pdev);
2782         pci_clear_mwi(pdev);
2783         pci_disable_device(pdev);
2784         free_netdev(dev);
2785 }
2786
2787 static void rtl8169_phy_reset(struct net_device *dev,
2788                               struct rtl8169_private *tp)
2789 {
2790         unsigned int i;
2791
2792         tp->phy_reset_enable(tp);
2793         for (i = 0; i < 100; i++) {
2794                 if (!tp->phy_reset_pending(tp))
2795                         return;
2796                 msleep(1);
2797         }
2798         netif_err(tp, link, dev, "PHY reset failed\n");
2799 }
2800
2801 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2802 {
2803         void __iomem *ioaddr = tp->mmio_addr;
2804
2805         rtl_hw_phy_config(dev);
2806
2807         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2808                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2809                 RTL_W8(0x82, 0x01);
2810         }
2811
2812         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2813
2814         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2815                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2816
2817         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2818                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2819                 RTL_W8(0x82, 0x01);
2820                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2821                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2822         }
2823
2824         rtl8169_phy_reset(dev, tp);
2825
2826         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2827                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2828                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2829                           (tp->mii.supports_gmii ?
2830                            ADVERTISED_1000baseT_Half |
2831                            ADVERTISED_1000baseT_Full : 0));
2832
2833         if (RTL_R8(PHYstatus) & TBI_Enable)
2834                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2835 }
2836
2837 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2838 {
2839         void __iomem *ioaddr = tp->mmio_addr;
2840         u32 high;
2841         u32 low;
2842
2843         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2844         high = addr[4] | (addr[5] << 8);
2845
2846         spin_lock_irq(&tp->lock);
2847
2848         RTL_W8(Cfg9346, Cfg9346_Unlock);
2849
2850         RTL_W32(MAC4, high);
2851         RTL_R32(MAC4);
2852
2853         RTL_W32(MAC0, low);
2854         RTL_R32(MAC0);
2855
2856         RTL_W8(Cfg9346, Cfg9346_Lock);
2857
2858         spin_unlock_irq(&tp->lock);
2859 }
2860
2861 static int rtl_set_mac_address(struct net_device *dev, void *p)
2862 {
2863         struct rtl8169_private *tp = netdev_priv(dev);
2864         struct sockaddr *addr = p;
2865
2866         if (!is_valid_ether_addr(addr->sa_data))
2867                 return -EADDRNOTAVAIL;
2868
2869         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2870
2871         rtl_rar_set(tp, dev->dev_addr);
2872
2873         return 0;
2874 }
2875
2876 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2877 {
2878         struct rtl8169_private *tp = netdev_priv(dev);
2879         struct mii_ioctl_data *data = if_mii(ifr);
2880
2881         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2882 }
2883
2884 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2885                           struct mii_ioctl_data *data, int cmd)
2886 {
2887         switch (cmd) {
2888         case SIOCGMIIPHY:
2889                 data->phy_id = 32; /* Internal PHY */
2890                 return 0;
2891
2892         case SIOCGMIIREG:
2893                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2894                 return 0;
2895
2896         case SIOCSMIIREG:
2897                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2898                 return 0;
2899         }
2900         return -EOPNOTSUPP;
2901 }
2902
2903 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2904 {
2905         return -EOPNOTSUPP;
2906 }
2907
2908 static const struct rtl_cfg_info {
2909         void (*hw_start)(struct net_device *);
2910         unsigned int region;
2911         unsigned int align;
2912         u16 intr_event;
2913         u16 napi_event;
2914         unsigned features;
2915         u8 default_ver;
2916 } rtl_cfg_infos [] = {
2917         [RTL_CFG_0] = {
2918                 .hw_start       = rtl_hw_start_8169,
2919                 .region         = 1,
2920                 .align          = 0,
2921                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2922                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2923                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2924                 .features       = RTL_FEATURE_GMII,
2925                 .default_ver    = RTL_GIGA_MAC_VER_01,
2926         },
2927         [RTL_CFG_1] = {
2928                 .hw_start       = rtl_hw_start_8168,
2929                 .region         = 2,
2930                 .align          = 8,
2931                 .intr_event     = SYSErr | LinkChg | RxOverflow |
2932                                   TxErr | TxOK | RxOK | RxErr,
2933                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
2934                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2935                 .default_ver    = RTL_GIGA_MAC_VER_11,
2936         },
2937         [RTL_CFG_2] = {
2938                 .hw_start       = rtl_hw_start_8101,
2939                 .region         = 2,
2940                 .align          = 8,
2941                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2942                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2943                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2944                 .features       = RTL_FEATURE_MSI,
2945                 .default_ver    = RTL_GIGA_MAC_VER_13,
2946         }
2947 };
2948
2949 /* Cfg9346_Unlock assumed. */
2950 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2951                             const struct rtl_cfg_info *cfg)
2952 {
2953         unsigned msi = 0;
2954         u8 cfg2;
2955
2956         cfg2 = RTL_R8(Config2) & ~MSIEnable;
2957         if (cfg->features & RTL_FEATURE_MSI) {
2958                 if (pci_enable_msi(pdev)) {
2959                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2960                 } else {
2961                         cfg2 |= MSIEnable;
2962                         msi = RTL_FEATURE_MSI;
2963                 }
2964         }
2965         RTL_W8(Config2, cfg2);
2966         return msi;
2967 }
2968
2969 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2970 {
2971         if (tp->features & RTL_FEATURE_MSI) {
2972                 pci_disable_msi(pdev);
2973                 tp->features &= ~RTL_FEATURE_MSI;
2974         }
2975 }
2976
2977 static const struct net_device_ops rtl8169_netdev_ops = {
2978         .ndo_open               = rtl8169_open,
2979         .ndo_stop               = rtl8169_close,
2980         .ndo_get_stats          = rtl8169_get_stats,
2981         .ndo_start_xmit         = rtl8169_start_xmit,
2982         .ndo_tx_timeout         = rtl8169_tx_timeout,
2983         .ndo_validate_addr      = eth_validate_addr,
2984         .ndo_change_mtu         = rtl8169_change_mtu,
2985         .ndo_fix_features       = rtl8169_fix_features,
2986         .ndo_set_features       = rtl8169_set_features,
2987         .ndo_set_mac_address    = rtl_set_mac_address,
2988         .ndo_do_ioctl           = rtl8169_ioctl,
2989         .ndo_set_multicast_list = rtl_set_rx_mode,
2990 #ifdef CONFIG_NET_POLL_CONTROLLER
2991         .ndo_poll_controller    = rtl8169_netpoll,
2992 #endif
2993
2994 };
2995
2996 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2997 {
2998         struct mdio_ops *ops = &tp->mdio_ops;
2999
3000         switch (tp->mac_version) {
3001         case RTL_GIGA_MAC_VER_27:
3002                 ops->write      = r8168dp_1_mdio_write;
3003                 ops->read       = r8168dp_1_mdio_read;
3004                 break;
3005         case RTL_GIGA_MAC_VER_28:
3006         case RTL_GIGA_MAC_VER_31:
3007                 ops->write      = r8168dp_2_mdio_write;
3008                 ops->read       = r8168dp_2_mdio_read;
3009                 break;
3010         default:
3011                 ops->write      = r8169_mdio_write;
3012                 ops->read       = r8169_mdio_read;
3013                 break;
3014         }
3015 }
3016
3017 static void r810x_phy_power_down(struct rtl8169_private *tp)
3018 {
3019         rtl_writephy(tp, 0x1f, 0x0000);
3020         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3021 }
3022
3023 static void r810x_phy_power_up(struct rtl8169_private *tp)
3024 {
3025         rtl_writephy(tp, 0x1f, 0x0000);
3026         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3027 }
3028
3029 static void r810x_pll_power_down(struct rtl8169_private *tp)
3030 {
3031         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3032                 rtl_writephy(tp, 0x1f, 0x0000);
3033                 rtl_writephy(tp, MII_BMCR, 0x0000);
3034                 return;
3035         }
3036
3037         r810x_phy_power_down(tp);
3038 }
3039
3040 static void r810x_pll_power_up(struct rtl8169_private *tp)
3041 {
3042         r810x_phy_power_up(tp);
3043 }
3044
3045 static void r8168_phy_power_up(struct rtl8169_private *tp)
3046 {
3047         rtl_writephy(tp, 0x1f, 0x0000);
3048         switch (tp->mac_version) {
3049         case RTL_GIGA_MAC_VER_11:
3050         case RTL_GIGA_MAC_VER_12:
3051         case RTL_GIGA_MAC_VER_17:
3052         case RTL_GIGA_MAC_VER_18:
3053         case RTL_GIGA_MAC_VER_19:
3054         case RTL_GIGA_MAC_VER_20:
3055         case RTL_GIGA_MAC_VER_21:
3056         case RTL_GIGA_MAC_VER_22:
3057         case RTL_GIGA_MAC_VER_23:
3058         case RTL_GIGA_MAC_VER_24:
3059         case RTL_GIGA_MAC_VER_25:
3060         case RTL_GIGA_MAC_VER_26:
3061         case RTL_GIGA_MAC_VER_27:
3062         case RTL_GIGA_MAC_VER_28:
3063         case RTL_GIGA_MAC_VER_31:
3064                 rtl_writephy(tp, 0x0e, 0x0000);
3065                 break;
3066         default:
3067                 break;
3068         }
3069         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3070 }
3071
3072 static void r8168_phy_power_down(struct rtl8169_private *tp)
3073 {
3074         rtl_writephy(tp, 0x1f, 0x0000);
3075         switch (tp->mac_version) {
3076         case RTL_GIGA_MAC_VER_32:
3077         case RTL_GIGA_MAC_VER_33:
3078                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3079                 break;
3080
3081         case RTL_GIGA_MAC_VER_11:
3082         case RTL_GIGA_MAC_VER_12:
3083         case RTL_GIGA_MAC_VER_17:
3084         case RTL_GIGA_MAC_VER_18:
3085         case RTL_GIGA_MAC_VER_19:
3086         case RTL_GIGA_MAC_VER_20:
3087         case RTL_GIGA_MAC_VER_21:
3088         case RTL_GIGA_MAC_VER_22:
3089         case RTL_GIGA_MAC_VER_23:
3090         case RTL_GIGA_MAC_VER_24:
3091         case RTL_GIGA_MAC_VER_25:
3092         case RTL_GIGA_MAC_VER_26:
3093         case RTL_GIGA_MAC_VER_27:
3094         case RTL_GIGA_MAC_VER_28:
3095         case RTL_GIGA_MAC_VER_31:
3096                 rtl_writephy(tp, 0x0e, 0x0200);
3097         default:
3098                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3099                 break;
3100         }
3101 }
3102
3103 static void r8168_pll_power_down(struct rtl8169_private *tp)
3104 {
3105         void __iomem *ioaddr = tp->mmio_addr;
3106
3107         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3108              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3109              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3110             r8168dp_check_dash(tp)) {
3111                 return;
3112         }
3113
3114         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3115              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3116             (RTL_R16(CPlusCmd) & ASF)) {
3117                 return;
3118         }
3119
3120         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3121             tp->mac_version == RTL_GIGA_MAC_VER_33)
3122                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3123
3124         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3125                 rtl_writephy(tp, 0x1f, 0x0000);
3126                 rtl_writephy(tp, MII_BMCR, 0x0000);
3127
3128                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3129                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3130                 return;
3131         }
3132
3133         r8168_phy_power_down(tp);
3134
3135         switch (tp->mac_version) {
3136         case RTL_GIGA_MAC_VER_25:
3137         case RTL_GIGA_MAC_VER_26:
3138         case RTL_GIGA_MAC_VER_27:
3139         case RTL_GIGA_MAC_VER_28:
3140         case RTL_GIGA_MAC_VER_31:
3141         case RTL_GIGA_MAC_VER_32:
3142         case RTL_GIGA_MAC_VER_33:
3143                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3144                 break;
3145         }
3146 }
3147
3148 static void r8168_pll_power_up(struct rtl8169_private *tp)
3149 {
3150         void __iomem *ioaddr = tp->mmio_addr;
3151
3152         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3153              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3154              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3155             r8168dp_check_dash(tp)) {
3156                 return;
3157         }
3158
3159         switch (tp->mac_version) {
3160         case RTL_GIGA_MAC_VER_25:
3161         case RTL_GIGA_MAC_VER_26:
3162         case RTL_GIGA_MAC_VER_27:
3163         case RTL_GIGA_MAC_VER_28:
3164         case RTL_GIGA_MAC_VER_31:
3165         case RTL_GIGA_MAC_VER_32:
3166         case RTL_GIGA_MAC_VER_33:
3167                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3168                 break;
3169         }
3170
3171         r8168_phy_power_up(tp);
3172 }
3173
3174 static void rtl_pll_power_op(struct rtl8169_private *tp,
3175                              void (*op)(struct rtl8169_private *))
3176 {
3177         if (op)
3178                 op(tp);
3179 }
3180
3181 static void rtl_pll_power_down(struct rtl8169_private *tp)
3182 {
3183         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3184 }
3185
3186 static void rtl_pll_power_up(struct rtl8169_private *tp)
3187 {
3188         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3189 }
3190
3191 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3192 {
3193         struct pll_power_ops *ops = &tp->pll_power_ops;
3194
3195         switch (tp->mac_version) {
3196         case RTL_GIGA_MAC_VER_07:
3197         case RTL_GIGA_MAC_VER_08:
3198         case RTL_GIGA_MAC_VER_09:
3199         case RTL_GIGA_MAC_VER_10:
3200         case RTL_GIGA_MAC_VER_16:
3201         case RTL_GIGA_MAC_VER_29:
3202         case RTL_GIGA_MAC_VER_30:
3203                 ops->down       = r810x_pll_power_down;
3204                 ops->up         = r810x_pll_power_up;
3205                 break;
3206
3207         case RTL_GIGA_MAC_VER_11:
3208         case RTL_GIGA_MAC_VER_12:
3209         case RTL_GIGA_MAC_VER_17:
3210         case RTL_GIGA_MAC_VER_18:
3211         case RTL_GIGA_MAC_VER_19:
3212         case RTL_GIGA_MAC_VER_20:
3213         case RTL_GIGA_MAC_VER_21:
3214         case RTL_GIGA_MAC_VER_22:
3215         case RTL_GIGA_MAC_VER_23:
3216         case RTL_GIGA_MAC_VER_24:
3217         case RTL_GIGA_MAC_VER_25:
3218         case RTL_GIGA_MAC_VER_26:
3219         case RTL_GIGA_MAC_VER_27:
3220         case RTL_GIGA_MAC_VER_28:
3221         case RTL_GIGA_MAC_VER_31:
3222         case RTL_GIGA_MAC_VER_32:
3223         case RTL_GIGA_MAC_VER_33:
3224                 ops->down       = r8168_pll_power_down;
3225                 ops->up         = r8168_pll_power_up;
3226                 break;
3227
3228         default:
3229                 ops->down       = NULL;
3230                 ops->up         = NULL;
3231                 break;
3232         }
3233 }
3234
3235 static void rtl_hw_reset(struct rtl8169_private *tp)
3236 {
3237         void __iomem *ioaddr = tp->mmio_addr;
3238         int i;
3239
3240         /* Soft reset the chip. */
3241         RTL_W8(ChipCmd, CmdReset);
3242
3243         /* Check that the chip has finished the reset. */
3244         for (i = 0; i < 100; i++) {
3245                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3246                         break;
3247                 msleep_interruptible(1);
3248         }
3249 }
3250
3251 static int __devinit
3252 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3253 {
3254         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3255         const unsigned int region = cfg->region;
3256         struct rtl8169_private *tp;
3257         struct mii_if_info *mii;
3258         struct net_device *dev;
3259         void __iomem *ioaddr;
3260         int chipset, i;
3261         int rc;
3262
3263         if (netif_msg_drv(&debug)) {
3264                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3265                        MODULENAME, RTL8169_VERSION);
3266         }
3267
3268         dev = alloc_etherdev(sizeof (*tp));
3269         if (!dev) {
3270                 if (netif_msg_drv(&debug))
3271                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3272                 rc = -ENOMEM;
3273                 goto out;
3274         }
3275
3276         SET_NETDEV_DEV(dev, &pdev->dev);
3277         dev->netdev_ops = &rtl8169_netdev_ops;
3278         tp = netdev_priv(dev);
3279         tp->dev = dev;
3280         tp->pci_dev = pdev;
3281         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3282
3283         mii = &tp->mii;
3284         mii->dev = dev;
3285         mii->mdio_read = rtl_mdio_read;
3286         mii->mdio_write = rtl_mdio_write;
3287         mii->phy_id_mask = 0x1f;
3288         mii->reg_num_mask = 0x1f;
3289         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3290
3291         /* disable ASPM completely as that cause random device stop working
3292          * problems as well as full system hangs for some PCIe devices users */
3293         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3294                                      PCIE_LINK_STATE_CLKPM);
3295
3296         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3297         rc = pci_enable_device(pdev);
3298         if (rc < 0) {
3299                 netif_err(tp, probe, dev, "enable failure\n");
3300                 goto err_out_free_dev_1;
3301         }
3302
3303         if (pci_set_mwi(pdev) < 0)
3304                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3305
3306         /* make sure PCI base addr 1 is MMIO */
3307         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3308                 netif_err(tp, probe, dev,
3309                           "region #%d not an MMIO resource, aborting\n",
3310                           region);
3311                 rc = -ENODEV;
3312                 goto err_out_mwi_2;
3313         }
3314
3315         /* check for weird/broken PCI region reporting */
3316         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3317                 netif_err(tp, probe, dev,
3318                           "Invalid PCI region size(s), aborting\n");
3319                 rc = -ENODEV;
3320                 goto err_out_mwi_2;
3321         }
3322
3323         rc = pci_request_regions(pdev, MODULENAME);
3324         if (rc < 0) {
3325                 netif_err(tp, probe, dev, "could not request regions\n");
3326                 goto err_out_mwi_2;
3327         }
3328
3329         tp->cp_cmd = RxChkSum;
3330
3331         if ((sizeof(dma_addr_t) > 4) &&
3332             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3333                 tp->cp_cmd |= PCIDAC;
3334                 dev->features |= NETIF_F_HIGHDMA;
3335         } else {
3336                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3337                 if (rc < 0) {
3338                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3339                         goto err_out_free_res_3;
3340                 }
3341         }
3342
3343         /* ioremap MMIO region */
3344         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3345         if (!ioaddr) {
3346                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3347                 rc = -EIO;
3348                 goto err_out_free_res_3;
3349         }
3350         tp->mmio_addr = ioaddr;
3351
3352         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3353         if (!tp->pcie_cap)
3354                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3355
3356         RTL_W16(IntrMask, 0x0000);
3357
3358         rtl_hw_reset(tp);
3359
3360         RTL_W16(IntrStatus, 0xffff);
3361
3362         pci_set_master(pdev);
3363
3364         /* Identify chip attached to board */
3365         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3366
3367         /*
3368          * Pretend we are using VLANs; This bypasses a nasty bug where
3369          * Interrupts stop flowing on high load on 8110SCd controllers.
3370          */
3371         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3372                 tp->cp_cmd |= RxVlan;
3373
3374         rtl_init_mdio_ops(tp);
3375         rtl_init_pll_power_ops(tp);
3376
3377         rtl8169_print_mac_version(tp);
3378
3379         chipset = tp->mac_version;
3380         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3381
3382         RTL_W8(Cfg9346, Cfg9346_Unlock);
3383         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3384         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3385         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3386                 tp->features |= RTL_FEATURE_WOL;
3387         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3388                 tp->features |= RTL_FEATURE_WOL;
3389         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3390         RTL_W8(Cfg9346, Cfg9346_Lock);
3391
3392         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3393             (RTL_R8(PHYstatus) & TBI_Enable)) {
3394                 tp->set_speed = rtl8169_set_speed_tbi;
3395                 tp->get_settings = rtl8169_gset_tbi;
3396                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3397                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3398                 tp->link_ok = rtl8169_tbi_link_ok;
3399                 tp->do_ioctl = rtl_tbi_ioctl;
3400         } else {
3401                 tp->set_speed = rtl8169_set_speed_xmii;
3402                 tp->get_settings = rtl8169_gset_xmii;
3403                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3404                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3405                 tp->link_ok = rtl8169_xmii_link_ok;
3406                 tp->do_ioctl = rtl_xmii_ioctl;
3407         }
3408
3409         spin_lock_init(&tp->lock);
3410
3411         /* Get MAC address */
3412         for (i = 0; i < MAC_ADDR_LEN; i++)
3413                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3414         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3415
3416         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3417         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3418         dev->irq = pdev->irq;
3419         dev->base_addr = (unsigned long) ioaddr;
3420
3421         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3422
3423         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3424          * properly for all devices */
3425         dev->features |= NETIF_F_RXCSUM |
3426                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3427
3428         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3429                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3430         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3431                 NETIF_F_HIGHDMA;
3432
3433         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3434                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3435                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3436
3437         tp->intr_mask = 0xffff;
3438         tp->hw_start = cfg->hw_start;
3439         tp->intr_event = cfg->intr_event;
3440         tp->napi_event = cfg->napi_event;
3441
3442         init_timer(&tp->timer);
3443         tp->timer.data = (unsigned long) dev;
3444         tp->timer.function = rtl8169_phy_timer;
3445
3446         tp->fw = RTL_FIRMWARE_UNKNOWN;
3447
3448         rc = register_netdev(dev);
3449         if (rc < 0)
3450                 goto err_out_msi_4;
3451
3452         pci_set_drvdata(pdev, dev);
3453
3454         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3455                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3456                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3457
3458         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3459             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3460             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3461                 rtl8168_driver_start(tp);
3462         }
3463
3464         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3465
3466         if (pci_dev_run_wake(pdev))
3467                 pm_runtime_put_noidle(&pdev->dev);
3468
3469         netif_carrier_off(dev);
3470
3471 out:
3472         return rc;
3473
3474 err_out_msi_4:
3475         rtl_disable_msi(pdev, tp);
3476         iounmap(ioaddr);
3477 err_out_free_res_3:
3478         pci_release_regions(pdev);
3479 err_out_mwi_2:
3480         pci_clear_mwi(pdev);
3481         pci_disable_device(pdev);
3482 err_out_free_dev_1:
3483         free_netdev(dev);
3484         goto out;
3485 }
3486
3487 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3488 {
3489         struct net_device *dev = pci_get_drvdata(pdev);
3490         struct rtl8169_private *tp = netdev_priv(dev);
3491
3492         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3493             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3494             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3495                 rtl8168_driver_stop(tp);
3496         }
3497
3498         cancel_delayed_work_sync(&tp->task);
3499
3500         unregister_netdev(dev);
3501
3502         rtl_release_firmware(tp);
3503
3504         if (pci_dev_run_wake(pdev))
3505                 pm_runtime_get_noresume(&pdev->dev);
3506
3507         /* restore original MAC address */
3508         rtl_rar_set(tp, dev->perm_addr);
3509
3510         rtl_disable_msi(pdev, tp);
3511         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3512         pci_set_drvdata(pdev, NULL);
3513 }
3514
3515 static void rtl_request_firmware(struct rtl8169_private *tp)
3516 {
3517         /* Return early if the firmware is already loaded / cached. */
3518         if (IS_ERR(tp->fw)) {
3519                 const char *name;
3520
3521                 name = rtl_lookup_firmware_name(tp);
3522                 if (name) {
3523                         int rc;
3524
3525                         rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
3526                         if (rc >= 0)
3527                                 return;
3528
3529                         netif_warn(tp, ifup, tp->dev, "unable to load "
3530                                 "firmware patch %s (%d)\n", name, rc);
3531                 }
3532                 tp->fw = NULL;
3533         }
3534 }
3535
3536 static int rtl8169_open(struct net_device *dev)
3537 {
3538         struct rtl8169_private *tp = netdev_priv(dev);
3539         void __iomem *ioaddr = tp->mmio_addr;
3540         struct pci_dev *pdev = tp->pci_dev;
3541         int retval = -ENOMEM;
3542
3543         pm_runtime_get_sync(&pdev->dev);
3544
3545         /*
3546          * Rx and Tx desscriptors needs 256 bytes alignment.
3547          * dma_alloc_coherent provides more.
3548          */
3549         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3550                                              &tp->TxPhyAddr, GFP_KERNEL);
3551         if (!tp->TxDescArray)
3552                 goto err_pm_runtime_put;
3553
3554         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3555                                              &tp->RxPhyAddr, GFP_KERNEL);
3556         if (!tp->RxDescArray)
3557                 goto err_free_tx_0;
3558
3559         retval = rtl8169_init_ring(dev);
3560         if (retval < 0)
3561                 goto err_free_rx_1;
3562
3563         INIT_DELAYED_WORK(&tp->task, NULL);
3564
3565         smp_mb();
3566
3567         rtl_request_firmware(tp);
3568
3569         retval = request_irq(dev->irq, rtl8169_interrupt,
3570                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3571                              dev->name, dev);
3572         if (retval < 0)
3573                 goto err_release_fw_2;
3574
3575         napi_enable(&tp->napi);
3576
3577         rtl8169_init_phy(dev, tp);
3578
3579         rtl8169_set_features(dev, dev->features);
3580
3581         rtl_pll_power_up(tp);
3582
3583         rtl_hw_start(dev);
3584
3585         tp->saved_wolopts = 0;
3586         pm_runtime_put_noidle(&pdev->dev);
3587
3588         rtl8169_check_link_status(dev, tp, ioaddr);
3589 out:
3590         return retval;
3591
3592 err_release_fw_2:
3593         rtl_release_firmware(tp);
3594         rtl8169_rx_clear(tp);
3595 err_free_rx_1:
3596         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3597                           tp->RxPhyAddr);
3598         tp->RxDescArray = NULL;
3599 err_free_tx_0:
3600         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3601                           tp->TxPhyAddr);
3602         tp->TxDescArray = NULL;
3603 err_pm_runtime_put:
3604         pm_runtime_put_noidle(&pdev->dev);
3605         goto out;
3606 }
3607
3608 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3609 {
3610         void __iomem *ioaddr = tp->mmio_addr;
3611
3612         /* Disable interrupts */
3613         rtl8169_irq_mask_and_ack(ioaddr);
3614
3615         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3616             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3617             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3618                 while (RTL_R8(TxPoll) & NPQ)
3619                         udelay(20);
3620
3621         }
3622
3623         /* Reset the chipset */
3624         RTL_W8(ChipCmd, CmdReset);
3625
3626         /* PCI commit */
3627         RTL_R8(ChipCmd);
3628 }
3629
3630 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3631 {
3632         void __iomem *ioaddr = tp->mmio_addr;
3633         u32 cfg = rtl8169_rx_config;
3634
3635         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3636         RTL_W32(RxConfig, cfg);
3637
3638         /* Set DMA burst size and Interframe Gap Time */
3639         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3640                 (InterFrameGap << TxInterFrameGapShift));
3641 }
3642
3643 static void rtl_hw_start(struct net_device *dev)
3644 {
3645         struct rtl8169_private *tp = netdev_priv(dev);
3646
3647         rtl_hw_reset(tp);
3648
3649         tp->hw_start(dev);
3650
3651         netif_start_queue(dev);
3652 }
3653
3654 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3655                                          void __iomem *ioaddr)
3656 {
3657         /*
3658          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3659          * register to be written before TxDescAddrLow to work.
3660          * Switching from MMIO to I/O access fixes the issue as well.
3661          */
3662         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3663         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3664         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3665         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3666 }
3667
3668 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3669 {
3670         u16 cmd;
3671
3672         cmd = RTL_R16(CPlusCmd);
3673         RTL_W16(CPlusCmd, cmd);
3674         return cmd;
3675 }
3676
3677 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3678 {
3679         /* Low hurts. Let's disable the filtering. */
3680         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3681 }
3682
3683 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3684 {
3685         static const struct rtl_cfg2_info {
3686                 u32 mac_version;
3687                 u32 clk;
3688                 u32 val;
3689         } cfg2_info [] = {
3690                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3691                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3692                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3693                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3694         };
3695         const struct rtl_cfg2_info *p = cfg2_info;
3696         unsigned int i;
3697         u32 clk;
3698
3699         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3700         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3701                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3702                         RTL_W32(0x7c, p->val);
3703                         break;
3704                 }
3705         }
3706 }
3707
3708 static void rtl_hw_start_8169(struct net_device *dev)
3709 {
3710         struct rtl8169_private *tp = netdev_priv(dev);
3711         void __iomem *ioaddr = tp->mmio_addr;
3712         struct pci_dev *pdev = tp->pci_dev;
3713
3714         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3715                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3716                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3717         }
3718
3719         RTL_W8(Cfg9346, Cfg9346_Unlock);
3720         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3721             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3722             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3723             tp->mac_version == RTL_GIGA_MAC_VER_04)
3724                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3725
3726         RTL_W8(EarlyTxThres, NoEarlyTx);
3727
3728         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3729
3730         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3731             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3732             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3733             tp->mac_version == RTL_GIGA_MAC_VER_04)
3734                 rtl_set_rx_tx_config_registers(tp);
3735
3736         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3737
3738         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3739             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3740                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3741                         "Bit-3 and bit-14 MUST be 1\n");
3742                 tp->cp_cmd |= (1 << 14);
3743         }
3744
3745         RTL_W16(CPlusCmd, tp->cp_cmd);
3746
3747         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3748
3749         /*
3750          * Undocumented corner. Supposedly:
3751          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3752          */
3753         RTL_W16(IntrMitigate, 0x0000);
3754
3755         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3756
3757         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3758             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3759             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3760             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3761                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3762                 rtl_set_rx_tx_config_registers(tp);
3763         }
3764
3765         RTL_W8(Cfg9346, Cfg9346_Lock);
3766
3767         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3768         RTL_R8(IntrMask);
3769
3770         RTL_W32(RxMissed, 0);
3771
3772         rtl_set_rx_mode(dev);
3773
3774         /* no early-rx interrupts */
3775         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3776
3777         /* Enable all known interrupts by setting the interrupt mask. */
3778         RTL_W16(IntrMask, tp->intr_event);
3779 }
3780
3781 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3782 {
3783         struct net_device *dev = pci_get_drvdata(pdev);
3784         struct rtl8169_private *tp = netdev_priv(dev);
3785         int cap = tp->pcie_cap;
3786
3787         if (cap) {
3788                 u16 ctl;
3789
3790                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3791                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3792                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3793         }
3794 }
3795
3796 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3797 {
3798         u32 csi;
3799
3800         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3801         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3802 }
3803
3804 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3805 {
3806         rtl_csi_access_enable(ioaddr, 0x17000000);
3807 }
3808
3809 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3810 {
3811         rtl_csi_access_enable(ioaddr, 0x27000000);
3812 }
3813
3814 struct ephy_info {
3815         unsigned int offset;
3816         u16 mask;
3817         u16 bits;
3818 };
3819
3820 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3821 {
3822         u16 w;
3823
3824         while (len-- > 0) {
3825                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3826                 rtl_ephy_write(ioaddr, e->offset, w);
3827                 e++;
3828         }
3829 }
3830
3831 static void rtl_disable_clock_request(struct pci_dev *pdev)
3832 {
3833         struct net_device *dev = pci_get_drvdata(pdev);
3834         struct rtl8169_private *tp = netdev_priv(dev);
3835         int cap = tp->pcie_cap;
3836
3837         if (cap) {
3838                 u16 ctl;
3839
3840                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3841                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3842                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3843         }
3844 }
3845
3846 static void rtl_enable_clock_request(struct pci_dev *pdev)
3847 {
3848         struct net_device *dev = pci_get_drvdata(pdev);
3849         struct rtl8169_private *tp = netdev_priv(dev);
3850         int cap = tp->pcie_cap;
3851
3852         if (cap) {
3853                 u16 ctl;
3854
3855                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3856                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3857                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3858         }
3859 }
3860
3861 #define R8168_CPCMD_QUIRK_MASK (\
3862         EnableBist | \
3863         Mac_dbgo_oe | \
3864         Force_half_dup | \
3865         Force_rxflow_en | \
3866         Force_txflow_en | \
3867         Cxpl_dbg_sel | \
3868         ASF | \
3869         PktCntrDisable | \
3870         Mac_dbgo_sel)
3871
3872 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3873 {
3874         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3875
3876         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3877
3878         rtl_tx_performance_tweak(pdev,
3879                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3880 }
3881
3882 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3883 {
3884         rtl_hw_start_8168bb(ioaddr, pdev);
3885
3886         RTL_W8(MaxTxPacketSize, TxPacketMax);
3887
3888         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3889 }
3890
3891 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3892 {
3893         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3894
3895         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3896
3897         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3898
3899         rtl_disable_clock_request(pdev);
3900
3901         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3902 }
3903
3904 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3905 {
3906         static const struct ephy_info e_info_8168cp[] = {
3907                 { 0x01, 0,      0x0001 },
3908                 { 0x02, 0x0800, 0x1000 },
3909                 { 0x03, 0,      0x0042 },
3910                 { 0x06, 0x0080, 0x0000 },
3911                 { 0x07, 0,      0x2000 }
3912         };
3913
3914         rtl_csi_access_enable_2(ioaddr);
3915
3916         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3917
3918         __rtl_hw_start_8168cp(ioaddr, pdev);
3919 }
3920
3921 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3922 {
3923         rtl_csi_access_enable_2(ioaddr);
3924
3925         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3926
3927         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3928
3929         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3930 }
3931
3932 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3933 {
3934         rtl_csi_access_enable_2(ioaddr);
3935
3936         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3937
3938         /* Magic. */
3939         RTL_W8(DBG_REG, 0x20);
3940
3941         RTL_W8(MaxTxPacketSize, TxPacketMax);
3942
3943         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3944
3945         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3946 }
3947
3948 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3949 {
3950         static const struct ephy_info e_info_8168c_1[] = {
3951                 { 0x02, 0x0800, 0x1000 },
3952                 { 0x03, 0,      0x0002 },
3953                 { 0x06, 0x0080, 0x0000 }
3954         };
3955
3956         rtl_csi_access_enable_2(ioaddr);
3957
3958         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3959
3960         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3961
3962         __rtl_hw_start_8168cp(ioaddr, pdev);
3963 }
3964
3965 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3966 {
3967         static const struct ephy_info e_info_8168c_2[] = {
3968                 { 0x01, 0,      0x0001 },
3969                 { 0x03, 0x0400, 0x0220 }
3970         };
3971
3972         rtl_csi_access_enable_2(ioaddr);
3973
3974         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3975
3976         __rtl_hw_start_8168cp(ioaddr, pdev);
3977 }
3978
3979 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3980 {
3981         rtl_hw_start_8168c_2(ioaddr, pdev);
3982 }
3983
3984 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3985 {
3986         rtl_csi_access_enable_2(ioaddr);
3987
3988         __rtl_hw_start_8168cp(ioaddr, pdev);
3989 }
3990
3991 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3992 {
3993         rtl_csi_access_enable_2(ioaddr);
3994
3995         rtl_disable_clock_request(pdev);
3996
3997         RTL_W8(MaxTxPacketSize, TxPacketMax);
3998
3999         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4000
4001         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4002 }
4003
4004 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4005 {
4006         rtl_csi_access_enable_1(ioaddr);
4007
4008         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4009
4010         RTL_W8(MaxTxPacketSize, TxPacketMax);
4011
4012         rtl_disable_clock_request(pdev);
4013 }
4014
4015 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4016 {
4017         static const struct ephy_info e_info_8168d_4[] = {
4018                 { 0x0b, ~0,     0x48 },
4019                 { 0x19, 0x20,   0x50 },
4020                 { 0x0c, ~0,     0x20 }
4021         };
4022         int i;
4023
4024         rtl_csi_access_enable_1(ioaddr);
4025
4026         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4027
4028         RTL_W8(MaxTxPacketSize, TxPacketMax);
4029
4030         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4031                 const struct ephy_info *e = e_info_8168d_4 + i;
4032                 u16 w;
4033
4034                 w = rtl_ephy_read(ioaddr, e->offset);
4035                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4036         }
4037
4038         rtl_enable_clock_request(pdev);
4039 }
4040
4041 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4042 {
4043         static const struct ephy_info e_info_8168e[] = {
4044                 { 0x00, 0x0200, 0x0100 },
4045                 { 0x00, 0x0000, 0x0004 },
4046                 { 0x06, 0x0002, 0x0001 },
4047                 { 0x06, 0x0000, 0x0030 },
4048                 { 0x07, 0x0000, 0x2000 },
4049                 { 0x00, 0x0000, 0x0020 },
4050                 { 0x03, 0x5800, 0x2000 },
4051                 { 0x03, 0x0000, 0x0001 },
4052                 { 0x01, 0x0800, 0x1000 },
4053                 { 0x07, 0x0000, 0x4000 },
4054                 { 0x1e, 0x0000, 0x2000 },
4055                 { 0x19, 0xffff, 0xfe6c },
4056                 { 0x0a, 0x0000, 0x0040 }
4057         };
4058
4059         rtl_csi_access_enable_2(ioaddr);
4060
4061         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4062
4063         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4064
4065         RTL_W8(MaxTxPacketSize, TxPacketMax);
4066
4067         rtl_disable_clock_request(pdev);
4068
4069         /* Reset tx FIFO pointer */
4070         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4071         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4072
4073         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4074 }
4075
4076 static void rtl_hw_start_8168(struct net_device *dev)
4077 {
4078         struct rtl8169_private *tp = netdev_priv(dev);
4079         void __iomem *ioaddr = tp->mmio_addr;
4080         struct pci_dev *pdev = tp->pci_dev;
4081
4082         RTL_W8(Cfg9346, Cfg9346_Unlock);
4083
4084         RTL_W8(MaxTxPacketSize, TxPacketMax);
4085
4086         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4087
4088         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4089
4090         RTL_W16(CPlusCmd, tp->cp_cmd);
4091
4092         RTL_W16(IntrMitigate, 0x5151);
4093
4094         /* Work around for RxFIFO overflow. */
4095         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4096             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4097                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4098                 tp->intr_event &= ~RxOverflow;
4099         }
4100
4101         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4102
4103         rtl_set_rx_mode(dev);
4104
4105         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4106                 (InterFrameGap << TxInterFrameGapShift));
4107
4108         RTL_R8(IntrMask);
4109
4110         switch (tp->mac_version) {
4111         case RTL_GIGA_MAC_VER_11:
4112                 rtl_hw_start_8168bb(ioaddr, pdev);
4113                 break;
4114
4115         case RTL_GIGA_MAC_VER_12:
4116         case RTL_GIGA_MAC_VER_17:
4117                 rtl_hw_start_8168bef(ioaddr, pdev);
4118                 break;
4119
4120         case RTL_GIGA_MAC_VER_18:
4121                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4122                 break;
4123
4124         case RTL_GIGA_MAC_VER_19:
4125                 rtl_hw_start_8168c_1(ioaddr, pdev);
4126                 break;
4127
4128         case RTL_GIGA_MAC_VER_20:
4129                 rtl_hw_start_8168c_2(ioaddr, pdev);
4130                 break;
4131
4132         case RTL_GIGA_MAC_VER_21:
4133                 rtl_hw_start_8168c_3(ioaddr, pdev);
4134                 break;
4135
4136         case RTL_GIGA_MAC_VER_22:
4137                 rtl_hw_start_8168c_4(ioaddr, pdev);
4138                 break;
4139
4140         case RTL_GIGA_MAC_VER_23:
4141                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4142                 break;
4143
4144         case RTL_GIGA_MAC_VER_24:
4145                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4146                 break;
4147
4148         case RTL_GIGA_MAC_VER_25:
4149         case RTL_GIGA_MAC_VER_26:
4150         case RTL_GIGA_MAC_VER_27:
4151                 rtl_hw_start_8168d(ioaddr, pdev);
4152                 break;
4153
4154         case RTL_GIGA_MAC_VER_28:
4155                 rtl_hw_start_8168d_4(ioaddr, pdev);
4156                 break;
4157
4158         case RTL_GIGA_MAC_VER_31:
4159                 rtl_hw_start_8168dp(ioaddr, pdev);
4160                 break;
4161
4162         case RTL_GIGA_MAC_VER_32:
4163         case RTL_GIGA_MAC_VER_33:
4164                 rtl_hw_start_8168e(ioaddr, pdev);
4165                 break;
4166
4167         default:
4168                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4169                         dev->name, tp->mac_version);
4170                 break;
4171         }
4172
4173         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4174
4175         RTL_W8(Cfg9346, Cfg9346_Lock);
4176
4177         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4178
4179         RTL_W16(IntrMask, tp->intr_event);
4180 }
4181
4182 #define R810X_CPCMD_QUIRK_MASK (\
4183         EnableBist | \
4184         Mac_dbgo_oe | \
4185         Force_half_dup | \
4186         Force_rxflow_en | \
4187         Force_txflow_en | \
4188         Cxpl_dbg_sel | \
4189         ASF | \
4190         PktCntrDisable | \
4191         Mac_dbgo_sel)
4192
4193 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4194 {
4195         static const struct ephy_info e_info_8102e_1[] = {
4196                 { 0x01, 0, 0x6e65 },
4197                 { 0x02, 0, 0x091f },
4198                 { 0x03, 0, 0xc2f9 },
4199                 { 0x06, 0, 0xafb5 },
4200                 { 0x07, 0, 0x0e00 },
4201                 { 0x19, 0, 0xec80 },
4202                 { 0x01, 0, 0x2e65 },
4203                 { 0x01, 0, 0x6e65 }
4204         };
4205         u8 cfg1;
4206
4207         rtl_csi_access_enable_2(ioaddr);
4208
4209         RTL_W8(DBG_REG, FIX_NAK_1);
4210
4211         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4212
4213         RTL_W8(Config1,
4214                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4215         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4216
4217         cfg1 = RTL_R8(Config1);
4218         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4219                 RTL_W8(Config1, cfg1 & ~LEDS0);
4220
4221         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4222 }
4223
4224 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4225 {
4226         rtl_csi_access_enable_2(ioaddr);
4227
4228         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4229
4230         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4231         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4232 }
4233
4234 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4235 {
4236         rtl_hw_start_8102e_2(ioaddr, pdev);
4237
4238         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4239 }
4240
4241 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4242 {
4243         static const struct ephy_info e_info_8105e_1[] = {
4244                 { 0x07, 0, 0x4000 },
4245                 { 0x19, 0, 0x0200 },
4246                 { 0x19, 0, 0x0020 },
4247                 { 0x1e, 0, 0x2000 },
4248                 { 0x03, 0, 0x0001 },
4249                 { 0x19, 0, 0x0100 },
4250                 { 0x19, 0, 0x0004 },
4251                 { 0x0a, 0, 0x0020 }
4252         };
4253
4254         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4255         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4256
4257         /* Disable Early Tally Counter */
4258         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4259
4260         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4261         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4262
4263         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4264 }
4265
4266 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4267 {
4268         rtl_hw_start_8105e_1(ioaddr, pdev);
4269         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4270 }
4271
4272 static void rtl_hw_start_8101(struct net_device *dev)
4273 {
4274         struct rtl8169_private *tp = netdev_priv(dev);
4275         void __iomem *ioaddr = tp->mmio_addr;
4276         struct pci_dev *pdev = tp->pci_dev;
4277
4278         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4279             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4280                 int cap = tp->pcie_cap;
4281
4282                 if (cap) {
4283                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4284                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4285                 }
4286         }
4287
4288         RTL_W8(Cfg9346, Cfg9346_Unlock);
4289
4290         switch (tp->mac_version) {
4291         case RTL_GIGA_MAC_VER_07:
4292                 rtl_hw_start_8102e_1(ioaddr, pdev);
4293                 break;
4294
4295         case RTL_GIGA_MAC_VER_08:
4296                 rtl_hw_start_8102e_3(ioaddr, pdev);
4297                 break;
4298
4299         case RTL_GIGA_MAC_VER_09:
4300                 rtl_hw_start_8102e_2(ioaddr, pdev);
4301                 break;
4302
4303         case RTL_GIGA_MAC_VER_29:
4304                 rtl_hw_start_8105e_1(ioaddr, pdev);
4305                 break;
4306         case RTL_GIGA_MAC_VER_30:
4307                 rtl_hw_start_8105e_2(ioaddr, pdev);
4308                 break;
4309         }
4310
4311         RTL_W8(Cfg9346, Cfg9346_Lock);
4312
4313         RTL_W8(MaxTxPacketSize, TxPacketMax);
4314
4315         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4316
4317         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4318         RTL_W16(CPlusCmd, tp->cp_cmd);
4319
4320         RTL_W16(IntrMitigate, 0x0000);
4321
4322         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4323
4324         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4325         rtl_set_rx_tx_config_registers(tp);
4326
4327         RTL_R8(IntrMask);
4328
4329         rtl_set_rx_mode(dev);
4330
4331         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4332
4333         RTL_W16(IntrMask, tp->intr_event);
4334 }
4335
4336 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4337 {
4338         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4339                 return -EINVAL;
4340
4341         dev->mtu = new_mtu;
4342         netdev_update_features(dev);
4343
4344         return 0;
4345 }
4346
4347 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4348 {
4349         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4350         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4351 }
4352
4353 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4354                                      void **data_buff, struct RxDesc *desc)
4355 {
4356         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4357                          DMA_FROM_DEVICE);
4358
4359         kfree(*data_buff);
4360         *data_buff = NULL;
4361         rtl8169_make_unusable_by_asic(desc);
4362 }
4363
4364 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4365 {
4366         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4367
4368         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4369 }
4370
4371 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4372                                        u32 rx_buf_sz)
4373 {
4374         desc->addr = cpu_to_le64(mapping);
4375         wmb();
4376         rtl8169_mark_to_asic(desc, rx_buf_sz);
4377 }
4378
4379 static inline void *rtl8169_align(void *data)
4380 {
4381         return (void *)ALIGN((long)data, 16);
4382 }
4383
4384 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4385                                              struct RxDesc *desc)
4386 {
4387         void *data;
4388         dma_addr_t mapping;
4389         struct device *d = &tp->pci_dev->dev;
4390         struct net_device *dev = tp->dev;
4391         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4392
4393         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4394         if (!data)
4395                 return NULL;
4396
4397         if (rtl8169_align(data) != data) {
4398                 kfree(data);
4399                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4400                 if (!data)
4401                         return NULL;
4402         }
4403
4404         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4405                                  DMA_FROM_DEVICE);
4406         if (unlikely(dma_mapping_error(d, mapping))) {
4407                 if (net_ratelimit())
4408                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4409                 goto err_out;
4410         }
4411
4412         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4413         return data;
4414
4415 err_out:
4416         kfree(data);
4417         return NULL;
4418 }
4419
4420 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4421 {
4422         unsigned int i;
4423
4424         for (i = 0; i < NUM_RX_DESC; i++) {
4425                 if (tp->Rx_databuff[i]) {
4426                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4427                                             tp->RxDescArray + i);
4428                 }
4429         }
4430 }
4431
4432 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4433 {
4434         desc->opts1 |= cpu_to_le32(RingEnd);
4435 }
4436
4437 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4438 {
4439         unsigned int i;
4440
4441         for (i = 0; i < NUM_RX_DESC; i++) {
4442                 void *data;
4443
4444                 if (tp->Rx_databuff[i])
4445                         continue;
4446
4447                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4448                 if (!data) {
4449                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4450                         goto err_out;
4451                 }
4452                 tp->Rx_databuff[i] = data;
4453         }
4454
4455         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4456         return 0;
4457
4458 err_out:
4459         rtl8169_rx_clear(tp);
4460         return -ENOMEM;
4461 }
4462
4463 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4464 {
4465         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4466 }
4467
4468 static int rtl8169_init_ring(struct net_device *dev)
4469 {
4470         struct rtl8169_private *tp = netdev_priv(dev);
4471
4472         rtl8169_init_ring_indexes(tp);
4473
4474         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4475         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4476
4477         return rtl8169_rx_fill(tp);
4478 }
4479
4480 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4481                                  struct TxDesc *desc)
4482 {
4483         unsigned int len = tx_skb->len;
4484
4485         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4486
4487         desc->opts1 = 0x00;
4488         desc->opts2 = 0x00;
4489         desc->addr = 0x00;
4490         tx_skb->len = 0;
4491 }
4492
4493 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4494                                    unsigned int n)
4495 {
4496         unsigned int i;
4497
4498         for (i = 0; i < n; i++) {
4499                 unsigned int entry = (start + i) % NUM_TX_DESC;
4500                 struct ring_info *tx_skb = tp->tx_skb + entry;
4501                 unsigned int len = tx_skb->len;
4502
4503                 if (len) {
4504                         struct sk_buff *skb = tx_skb->skb;
4505
4506                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4507                                              tp->TxDescArray + entry);
4508                         if (skb) {
4509                                 tp->dev->stats.tx_dropped++;
4510                                 dev_kfree_skb(skb);
4511                                 tx_skb->skb = NULL;
4512                         }
4513                 }
4514         }
4515 }
4516
4517 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4518 {
4519         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4520         tp->cur_tx = tp->dirty_tx = 0;
4521 }
4522
4523 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4524 {
4525         struct rtl8169_private *tp = netdev_priv(dev);
4526
4527         PREPARE_DELAYED_WORK(&tp->task, task);
4528         schedule_delayed_work(&tp->task, 4);
4529 }
4530
4531 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4532 {
4533         struct rtl8169_private *tp = netdev_priv(dev);
4534         void __iomem *ioaddr = tp->mmio_addr;
4535
4536         synchronize_irq(dev->irq);
4537
4538         /* Wait for any pending NAPI task to complete */
4539         napi_disable(&tp->napi);
4540
4541         rtl8169_irq_mask_and_ack(ioaddr);
4542
4543         tp->intr_mask = 0xffff;
4544         RTL_W16(IntrMask, tp->intr_event);
4545         napi_enable(&tp->napi);
4546 }
4547
4548 static void rtl8169_reinit_task(struct work_struct *work)
4549 {
4550         struct rtl8169_private *tp =
4551                 container_of(work, struct rtl8169_private, task.work);
4552         struct net_device *dev = tp->dev;
4553         int ret;
4554
4555         rtnl_lock();
4556
4557         if (!netif_running(dev))
4558                 goto out_unlock;
4559
4560         rtl8169_wait_for_quiescence(dev);
4561         rtl8169_close(dev);
4562
4563         ret = rtl8169_open(dev);
4564         if (unlikely(ret < 0)) {
4565                 if (net_ratelimit())
4566                         netif_err(tp, drv, dev,
4567                                   "reinit failure (status = %d). Rescheduling\n",
4568                                   ret);
4569                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4570         }
4571
4572 out_unlock:
4573         rtnl_unlock();
4574 }
4575
4576 static void rtl8169_reset_task(struct work_struct *work)
4577 {
4578         struct rtl8169_private *tp =
4579                 container_of(work, struct rtl8169_private, task.work);
4580         struct net_device *dev = tp->dev;
4581         int i;
4582
4583         rtnl_lock();
4584
4585         if (!netif_running(dev))
4586                 goto out_unlock;
4587
4588         rtl8169_wait_for_quiescence(dev);
4589
4590         for (i = 0; i < NUM_RX_DESC; i++)
4591                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4592
4593         rtl8169_tx_clear(tp);
4594
4595         rtl8169_init_ring_indexes(tp);
4596         rtl_hw_start(dev);
4597         netif_wake_queue(dev);
4598         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4599
4600 out_unlock:
4601         rtnl_unlock();
4602 }
4603
4604 static void rtl8169_tx_timeout(struct net_device *dev)
4605 {
4606         struct rtl8169_private *tp = netdev_priv(dev);
4607
4608         rtl8169_hw_reset(tp);
4609
4610         /* Let's wait a bit while any (async) irq lands on */
4611         rtl8169_schedule_work(dev, rtl8169_reset_task);
4612 }
4613
4614 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4615                               u32 *opts)
4616 {
4617         struct skb_shared_info *info = skb_shinfo(skb);
4618         unsigned int cur_frag, entry;
4619         struct TxDesc * uninitialized_var(txd);
4620         struct device *d = &tp->pci_dev->dev;
4621
4622         entry = tp->cur_tx;
4623         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4624                 skb_frag_t *frag = info->frags + cur_frag;
4625                 dma_addr_t mapping;
4626                 u32 status, len;
4627                 void *addr;
4628
4629                 entry = (entry + 1) % NUM_TX_DESC;
4630
4631                 txd = tp->TxDescArray + entry;
4632                 len = frag->size;
4633                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4634                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4635                 if (unlikely(dma_mapping_error(d, mapping))) {
4636                         if (net_ratelimit())
4637                                 netif_err(tp, drv, tp->dev,
4638                                           "Failed to map TX fragments DMA!\n");
4639                         goto err_out;
4640                 }
4641
4642                 /* Anti gcc 2.95.3 bugware (sic) */
4643                 status = opts[0] | len |
4644                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4645
4646                 txd->opts1 = cpu_to_le32(status);
4647                 txd->opts2 = cpu_to_le32(opts[1]);
4648                 txd->addr = cpu_to_le64(mapping);
4649
4650                 tp->tx_skb[entry].len = len;
4651         }
4652
4653         if (cur_frag) {
4654                 tp->tx_skb[entry].skb = skb;
4655                 txd->opts1 |= cpu_to_le32(LastFrag);
4656         }
4657
4658         return cur_frag;
4659
4660 err_out:
4661         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4662         return -EIO;
4663 }
4664
4665 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4666                                     struct sk_buff *skb, u32 *opts)
4667 {
4668         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4669         u32 mss = skb_shinfo(skb)->gso_size;
4670         int offset = info->opts_offset;
4671
4672         if (mss) {
4673                 opts[0] |= TD_LSO;
4674                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4675         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4676                 const struct iphdr *ip = ip_hdr(skb);
4677
4678                 if (ip->protocol == IPPROTO_TCP)
4679                         opts[offset] |= info->checksum.tcp;
4680                 else if (ip->protocol == IPPROTO_UDP)
4681                         opts[offset] |= info->checksum.udp;
4682                 else
4683                         WARN_ON_ONCE(1);
4684         }
4685 }
4686
4687 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4688                                       struct net_device *dev)
4689 {
4690         struct rtl8169_private *tp = netdev_priv(dev);
4691         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4692         struct TxDesc *txd = tp->TxDescArray + entry;
4693         void __iomem *ioaddr = tp->mmio_addr;
4694         struct device *d = &tp->pci_dev->dev;
4695         dma_addr_t mapping;
4696         u32 status, len;
4697         u32 opts[2];
4698         int frags;
4699
4700         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4701                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4702                 goto err_stop_0;
4703         }
4704
4705         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4706                 goto err_stop_0;
4707
4708         len = skb_headlen(skb);
4709         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4710         if (unlikely(dma_mapping_error(d, mapping))) {
4711                 if (net_ratelimit())
4712                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4713                 goto err_dma_0;
4714         }
4715
4716         tp->tx_skb[entry].len = len;
4717         txd->addr = cpu_to_le64(mapping);
4718
4719         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4720         opts[0] = DescOwn;
4721
4722         rtl8169_tso_csum(tp, skb, opts);
4723
4724         frags = rtl8169_xmit_frags(tp, skb, opts);
4725         if (frags < 0)
4726                 goto err_dma_1;
4727         else if (frags)
4728                 opts[0] |= FirstFrag;
4729         else {
4730                 opts[0] |= FirstFrag | LastFrag;
4731                 tp->tx_skb[entry].skb = skb;
4732         }
4733
4734         txd->opts2 = cpu_to_le32(opts[1]);
4735
4736         wmb();
4737
4738         /* Anti gcc 2.95.3 bugware (sic) */
4739         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4740         txd->opts1 = cpu_to_le32(status);
4741
4742         tp->cur_tx += frags + 1;
4743
4744         wmb();
4745
4746         RTL_W8(TxPoll, NPQ);
4747
4748         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4749                 netif_stop_queue(dev);
4750                 smp_rmb();
4751                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4752                         netif_wake_queue(dev);
4753         }
4754
4755         return NETDEV_TX_OK;
4756
4757 err_dma_1:
4758         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4759 err_dma_0:
4760         dev_kfree_skb(skb);
4761         dev->stats.tx_dropped++;
4762         return NETDEV_TX_OK;
4763
4764 err_stop_0:
4765         netif_stop_queue(dev);
4766         dev->stats.tx_dropped++;
4767         return NETDEV_TX_BUSY;
4768 }
4769
4770 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4771 {
4772         struct rtl8169_private *tp = netdev_priv(dev);
4773         struct pci_dev *pdev = tp->pci_dev;
4774         u16 pci_status, pci_cmd;
4775
4776         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4777         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4778
4779         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4780                   pci_cmd, pci_status);
4781
4782         /*
4783          * The recovery sequence below admits a very elaborated explanation:
4784          * - it seems to work;
4785          * - I did not see what else could be done;
4786          * - it makes iop3xx happy.
4787          *
4788          * Feel free to adjust to your needs.
4789          */
4790         if (pdev->broken_parity_status)
4791                 pci_cmd &= ~PCI_COMMAND_PARITY;
4792         else
4793                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4794
4795         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4796
4797         pci_write_config_word(pdev, PCI_STATUS,
4798                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4799                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4800                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4801
4802         /* The infamous DAC f*ckup only happens at boot time */
4803         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4804                 void __iomem *ioaddr = tp->mmio_addr;
4805
4806                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4807                 tp->cp_cmd &= ~PCIDAC;
4808                 RTL_W16(CPlusCmd, tp->cp_cmd);
4809                 dev->features &= ~NETIF_F_HIGHDMA;
4810         }
4811
4812         rtl8169_hw_reset(tp);
4813
4814         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4815 }
4816
4817 static void rtl8169_tx_interrupt(struct net_device *dev,
4818                                  struct rtl8169_private *tp,
4819                                  void __iomem *ioaddr)
4820 {
4821         unsigned int dirty_tx, tx_left;
4822
4823         dirty_tx = tp->dirty_tx;
4824         smp_rmb();
4825         tx_left = tp->cur_tx - dirty_tx;
4826
4827         while (tx_left > 0) {
4828                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4829                 struct ring_info *tx_skb = tp->tx_skb + entry;
4830                 u32 status;
4831
4832                 rmb();
4833                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4834                 if (status & DescOwn)
4835                         break;
4836
4837                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4838                                      tp->TxDescArray + entry);
4839                 if (status & LastFrag) {
4840                         dev->stats.tx_packets++;
4841                         dev->stats.tx_bytes += tx_skb->skb->len;
4842                         dev_kfree_skb(tx_skb->skb);
4843                         tx_skb->skb = NULL;
4844                 }
4845                 dirty_tx++;
4846                 tx_left--;
4847         }
4848
4849         if (tp->dirty_tx != dirty_tx) {
4850                 tp->dirty_tx = dirty_tx;
4851                 smp_wmb();
4852                 if (netif_queue_stopped(dev) &&
4853                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4854                         netif_wake_queue(dev);
4855                 }
4856                 /*
4857                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4858                  * too close. Let's kick an extra TxPoll request when a burst
4859                  * of start_xmit activity is detected (if it is not detected,
4860                  * it is slow enough). -- FR
4861                  */
4862                 smp_rmb();
4863                 if (tp->cur_tx != dirty_tx)
4864                         RTL_W8(TxPoll, NPQ);
4865         }
4866 }
4867
4868 static inline int rtl8169_fragmented_frame(u32 status)
4869 {
4870         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4871 }
4872
4873 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4874 {
4875         u32 status = opts1 & RxProtoMask;
4876
4877         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4878             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4879                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4880         else
4881                 skb_checksum_none_assert(skb);
4882 }
4883
4884 static struct sk_buff *rtl8169_try_rx_copy(void *data,
4885                                            struct rtl8169_private *tp,
4886                                            int pkt_size,
4887                                            dma_addr_t addr)
4888 {
4889         struct sk_buff *skb;
4890         struct device *d = &tp->pci_dev->dev;
4891
4892         data = rtl8169_align(data);
4893         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
4894         prefetch(data);
4895         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4896         if (skb)
4897                 memcpy(skb->data, data, pkt_size);
4898         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4899
4900         return skb;
4901 }
4902
4903 static int rtl8169_rx_interrupt(struct net_device *dev,
4904                                 struct rtl8169_private *tp,
4905                                 void __iomem *ioaddr, u32 budget)
4906 {
4907         unsigned int cur_rx, rx_left;
4908         unsigned int count;
4909
4910         cur_rx = tp->cur_rx;
4911         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4912         rx_left = min(rx_left, budget);
4913
4914         for (; rx_left > 0; rx_left--, cur_rx++) {
4915                 unsigned int entry = cur_rx % NUM_RX_DESC;
4916                 struct RxDesc *desc = tp->RxDescArray + entry;
4917                 u32 status;
4918
4919                 rmb();
4920                 status = le32_to_cpu(desc->opts1);
4921
4922                 if (status & DescOwn)
4923                         break;
4924                 if (unlikely(status & RxRES)) {
4925                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4926                                    status);
4927                         dev->stats.rx_errors++;
4928                         if (status & (RxRWT | RxRUNT))
4929                                 dev->stats.rx_length_errors++;
4930                         if (status & RxCRC)
4931                                 dev->stats.rx_crc_errors++;
4932                         if (status & RxFOVF) {
4933                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
4934                                 dev->stats.rx_fifo_errors++;
4935                         }
4936                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4937                 } else {
4938                         struct sk_buff *skb;
4939                         dma_addr_t addr = le64_to_cpu(desc->addr);
4940                         int pkt_size = (status & 0x00001FFF) - 4;
4941
4942                         /*
4943                          * The driver does not support incoming fragmented
4944                          * frames. They are seen as a symptom of over-mtu
4945                          * sized frames.
4946                          */
4947                         if (unlikely(rtl8169_fragmented_frame(status))) {
4948                                 dev->stats.rx_dropped++;
4949                                 dev->stats.rx_length_errors++;
4950                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
4951                                 continue;
4952                         }
4953
4954                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4955                                                   tp, pkt_size, addr);
4956                         rtl8169_mark_to_asic(desc, rx_buf_sz);
4957                         if (!skb) {
4958                                 dev->stats.rx_dropped++;
4959                                 continue;
4960                         }
4961
4962                         rtl8169_rx_csum(skb, status);
4963                         skb_put(skb, pkt_size);
4964                         skb->protocol = eth_type_trans(skb, dev);
4965
4966                         rtl8169_rx_vlan_tag(desc, skb);
4967
4968                         napi_gro_receive(&tp->napi, skb);
4969
4970                         dev->stats.rx_bytes += pkt_size;
4971                         dev->stats.rx_packets++;
4972                 }
4973
4974                 /* Work around for AMD plateform. */
4975                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4976                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4977                         desc->opts2 = 0;
4978                         cur_rx++;
4979                 }
4980         }
4981
4982         count = cur_rx - tp->cur_rx;
4983         tp->cur_rx = cur_rx;
4984
4985         tp->dirty_rx += count;
4986
4987         return count;
4988 }
4989
4990 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4991 {
4992         struct net_device *dev = dev_instance;
4993         struct rtl8169_private *tp = netdev_priv(dev);
4994         void __iomem *ioaddr = tp->mmio_addr;
4995         int handled = 0;
4996         int status;
4997
4998         /* loop handling interrupts until we have no new ones or
4999          * we hit a invalid/hotplug case.
5000          */
5001         status = RTL_R16(IntrStatus);
5002         while (status && status != 0xffff) {
5003                 handled = 1;
5004
5005                 /* Handle all of the error cases first. These will reset
5006                  * the chip, so just exit the loop.
5007                  */
5008                 if (unlikely(!netif_running(dev))) {
5009                         rtl8169_asic_down(ioaddr);
5010                         break;
5011                 }
5012
5013                 if (unlikely(status & RxFIFOOver)) {
5014                         switch (tp->mac_version) {
5015                         /* Work around for rx fifo overflow */
5016                         case RTL_GIGA_MAC_VER_11:
5017                         case RTL_GIGA_MAC_VER_22:
5018                         case RTL_GIGA_MAC_VER_26:
5019                                 netif_stop_queue(dev);
5020                                 rtl8169_tx_timeout(dev);
5021                                 goto done;
5022                         /* Testers needed. */
5023                         case RTL_GIGA_MAC_VER_17:
5024                         case RTL_GIGA_MAC_VER_19:
5025                         case RTL_GIGA_MAC_VER_20:
5026                         case RTL_GIGA_MAC_VER_21:
5027                         case RTL_GIGA_MAC_VER_23:
5028                         case RTL_GIGA_MAC_VER_24:
5029                         case RTL_GIGA_MAC_VER_27:
5030                         case RTL_GIGA_MAC_VER_28:
5031                         case RTL_GIGA_MAC_VER_31:
5032                         /* Experimental science. Pktgen proof. */
5033                         case RTL_GIGA_MAC_VER_12:
5034                         case RTL_GIGA_MAC_VER_25:
5035                                 if (status == RxFIFOOver)
5036                                         goto done;
5037                                 break;
5038                         default:
5039                                 break;
5040                         }
5041                 }
5042
5043                 if (unlikely(status & SYSErr)) {
5044                         rtl8169_pcierr_interrupt(dev);
5045                         break;
5046                 }
5047
5048                 if (status & LinkChg)
5049                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5050
5051                 /* We need to see the lastest version of tp->intr_mask to
5052                  * avoid ignoring an MSI interrupt and having to wait for
5053                  * another event which may never come.
5054                  */
5055                 smp_rmb();
5056                 if (status & tp->intr_mask & tp->napi_event) {
5057                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5058                         tp->intr_mask = ~tp->napi_event;
5059
5060                         if (likely(napi_schedule_prep(&tp->napi)))
5061                                 __napi_schedule(&tp->napi);
5062                         else
5063                                 netif_info(tp, intr, dev,
5064                                            "interrupt %04x in poll\n", status);
5065                 }
5066
5067                 /* We only get a new MSI interrupt when all active irq
5068                  * sources on the chip have been acknowledged. So, ack
5069                  * everything we've seen and check if new sources have become
5070                  * active to avoid blocking all interrupts from the chip.
5071                  */
5072                 RTL_W16(IntrStatus,
5073                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5074                 status = RTL_R16(IntrStatus);
5075         }
5076 done:
5077         return IRQ_RETVAL(handled);
5078 }
5079
5080 static int rtl8169_poll(struct napi_struct *napi, int budget)
5081 {
5082         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5083         struct net_device *dev = tp->dev;
5084         void __iomem *ioaddr = tp->mmio_addr;
5085         int work_done;
5086
5087         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5088         rtl8169_tx_interrupt(dev, tp, ioaddr);
5089
5090         if (work_done < budget) {
5091                 napi_complete(napi);
5092
5093                 /* We need for force the visibility of tp->intr_mask
5094                  * for other CPUs, as we can loose an MSI interrupt
5095                  * and potentially wait for a retransmit timeout if we don't.
5096                  * The posted write to IntrMask is safe, as it will
5097                  * eventually make it to the chip and we won't loose anything
5098                  * until it does.
5099                  */
5100                 tp->intr_mask = 0xffff;
5101                 wmb();
5102                 RTL_W16(IntrMask, tp->intr_event);
5103         }
5104
5105         return work_done;
5106 }
5107
5108 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5109 {
5110         struct rtl8169_private *tp = netdev_priv(dev);
5111
5112         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5113                 return;
5114
5115         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5116         RTL_W32(RxMissed, 0);
5117 }
5118
5119 static void rtl8169_down(struct net_device *dev)
5120 {
5121         struct rtl8169_private *tp = netdev_priv(dev);
5122         void __iomem *ioaddr = tp->mmio_addr;
5123
5124         del_timer_sync(&tp->timer);
5125
5126         netif_stop_queue(dev);
5127
5128         napi_disable(&tp->napi);
5129
5130         spin_lock_irq(&tp->lock);
5131
5132         rtl8169_asic_down(ioaddr);
5133         /*
5134          * At this point device interrupts can not be enabled in any function,
5135          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5136          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5137          */
5138         rtl8169_rx_missed(dev, ioaddr);
5139
5140         spin_unlock_irq(&tp->lock);
5141
5142         synchronize_irq(dev->irq);
5143
5144         /* Give a racing hard_start_xmit a few cycles to complete. */
5145         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5146
5147         rtl8169_tx_clear(tp);
5148
5149         rtl8169_rx_clear(tp);
5150
5151         rtl_pll_power_down(tp);
5152 }
5153
5154 static int rtl8169_close(struct net_device *dev)
5155 {
5156         struct rtl8169_private *tp = netdev_priv(dev);
5157         struct pci_dev *pdev = tp->pci_dev;
5158
5159         pm_runtime_get_sync(&pdev->dev);
5160
5161         /* Update counters before going down */
5162         rtl8169_update_counters(dev);
5163
5164         rtl8169_down(dev);
5165
5166         free_irq(dev->irq, dev);
5167
5168         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5169                           tp->RxPhyAddr);
5170         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5171                           tp->TxPhyAddr);
5172         tp->TxDescArray = NULL;
5173         tp->RxDescArray = NULL;
5174
5175         pm_runtime_put_sync(&pdev->dev);
5176
5177         return 0;
5178 }
5179
5180 static void rtl_set_rx_mode(struct net_device *dev)
5181 {
5182         struct rtl8169_private *tp = netdev_priv(dev);
5183         void __iomem *ioaddr = tp->mmio_addr;
5184         unsigned long flags;
5185         u32 mc_filter[2];       /* Multicast hash filter */
5186         int rx_mode;
5187         u32 tmp = 0;
5188
5189         if (dev->flags & IFF_PROMISC) {
5190                 /* Unconditionally log net taps. */
5191                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5192                 rx_mode =
5193                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5194                     AcceptAllPhys;
5195                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5196         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5197                    (dev->flags & IFF_ALLMULTI)) {
5198                 /* Too many to filter perfectly -- accept all multicasts. */
5199                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5200                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5201         } else {
5202                 struct netdev_hw_addr *ha;
5203
5204                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5205                 mc_filter[1] = mc_filter[0] = 0;
5206                 netdev_for_each_mc_addr(ha, dev) {
5207                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5208                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5209                         rx_mode |= AcceptMulticast;
5210                 }
5211         }
5212
5213         spin_lock_irqsave(&tp->lock, flags);
5214
5215         tmp = rtl8169_rx_config | rx_mode |
5216               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5217
5218         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5219                 u32 data = mc_filter[0];
5220
5221                 mc_filter[0] = swab32(mc_filter[1]);
5222                 mc_filter[1] = swab32(data);
5223         }
5224
5225         RTL_W32(MAR0 + 4, mc_filter[1]);
5226         RTL_W32(MAR0 + 0, mc_filter[0]);
5227
5228         RTL_W32(RxConfig, tmp);
5229
5230         spin_unlock_irqrestore(&tp->lock, flags);
5231 }
5232
5233 /**
5234  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5235  *  @dev: The Ethernet Device to get statistics for
5236  *
5237  *  Get TX/RX statistics for rtl8169
5238  */
5239 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5240 {
5241         struct rtl8169_private *tp = netdev_priv(dev);
5242         void __iomem *ioaddr = tp->mmio_addr;
5243         unsigned long flags;
5244
5245         if (netif_running(dev)) {
5246                 spin_lock_irqsave(&tp->lock, flags);
5247                 rtl8169_rx_missed(dev, ioaddr);
5248                 spin_unlock_irqrestore(&tp->lock, flags);
5249         }
5250
5251         return &dev->stats;
5252 }
5253
5254 static void rtl8169_net_suspend(struct net_device *dev)
5255 {
5256         struct rtl8169_private *tp = netdev_priv(dev);
5257
5258         if (!netif_running(dev))
5259                 return;
5260
5261         rtl_pll_power_down(tp);
5262
5263         netif_device_detach(dev);
5264         netif_stop_queue(dev);
5265 }
5266
5267 #ifdef CONFIG_PM
5268
5269 static int rtl8169_suspend(struct device *device)
5270 {
5271         struct pci_dev *pdev = to_pci_dev(device);
5272         struct net_device *dev = pci_get_drvdata(pdev);
5273
5274         rtl8169_net_suspend(dev);
5275
5276         return 0;
5277 }
5278
5279 static void __rtl8169_resume(struct net_device *dev)
5280 {
5281         struct rtl8169_private *tp = netdev_priv(dev);
5282
5283         netif_device_attach(dev);
5284
5285         rtl_pll_power_up(tp);
5286
5287         rtl8169_schedule_work(dev, rtl8169_reset_task);
5288 }
5289
5290 static int rtl8169_resume(struct device *device)
5291 {
5292         struct pci_dev *pdev = to_pci_dev(device);
5293         struct net_device *dev = pci_get_drvdata(pdev);
5294         struct rtl8169_private *tp = netdev_priv(dev);
5295
5296         rtl8169_init_phy(dev, tp);
5297
5298         if (netif_running(dev))
5299                 __rtl8169_resume(dev);
5300
5301         return 0;
5302 }
5303
5304 static int rtl8169_runtime_suspend(struct device *device)
5305 {
5306         struct pci_dev *pdev = to_pci_dev(device);
5307         struct net_device *dev = pci_get_drvdata(pdev);
5308         struct rtl8169_private *tp = netdev_priv(dev);
5309
5310         if (!tp->TxDescArray)
5311                 return 0;
5312
5313         spin_lock_irq(&tp->lock);
5314         tp->saved_wolopts = __rtl8169_get_wol(tp);
5315         __rtl8169_set_wol(tp, WAKE_ANY);
5316         spin_unlock_irq(&tp->lock);
5317
5318         rtl8169_net_suspend(dev);
5319
5320         return 0;
5321 }
5322
5323 static int rtl8169_runtime_resume(struct device *device)
5324 {
5325         struct pci_dev *pdev = to_pci_dev(device);
5326         struct net_device *dev = pci_get_drvdata(pdev);
5327         struct rtl8169_private *tp = netdev_priv(dev);
5328
5329         if (!tp->TxDescArray)
5330                 return 0;
5331
5332         spin_lock_irq(&tp->lock);
5333         __rtl8169_set_wol(tp, tp->saved_wolopts);
5334         tp->saved_wolopts = 0;
5335         spin_unlock_irq(&tp->lock);
5336
5337         rtl8169_init_phy(dev, tp);
5338
5339         __rtl8169_resume(dev);
5340
5341         return 0;
5342 }
5343
5344 static int rtl8169_runtime_idle(struct device *device)
5345 {
5346         struct pci_dev *pdev = to_pci_dev(device);
5347         struct net_device *dev = pci_get_drvdata(pdev);
5348         struct rtl8169_private *tp = netdev_priv(dev);
5349
5350         return tp->TxDescArray ? -EBUSY : 0;
5351 }
5352
5353 static const struct dev_pm_ops rtl8169_pm_ops = {
5354         .suspend                = rtl8169_suspend,
5355         .resume                 = rtl8169_resume,
5356         .freeze                 = rtl8169_suspend,
5357         .thaw                   = rtl8169_resume,
5358         .poweroff               = rtl8169_suspend,
5359         .restore                = rtl8169_resume,
5360         .runtime_suspend        = rtl8169_runtime_suspend,
5361         .runtime_resume         = rtl8169_runtime_resume,
5362         .runtime_idle           = rtl8169_runtime_idle,
5363 };
5364
5365 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5366
5367 #else /* !CONFIG_PM */
5368
5369 #define RTL8169_PM_OPS  NULL
5370
5371 #endif /* !CONFIG_PM */
5372
5373 static void rtl_shutdown(struct pci_dev *pdev)
5374 {
5375         struct net_device *dev = pci_get_drvdata(pdev);
5376         struct rtl8169_private *tp = netdev_priv(dev);
5377         void __iomem *ioaddr = tp->mmio_addr;
5378
5379         rtl8169_net_suspend(dev);
5380
5381         /* Restore original MAC address */
5382         rtl_rar_set(tp, dev->perm_addr);
5383
5384         spin_lock_irq(&tp->lock);
5385
5386         rtl8169_asic_down(ioaddr);
5387
5388         spin_unlock_irq(&tp->lock);
5389
5390         if (system_state == SYSTEM_POWER_OFF) {
5391                 /* WoL fails with some 8168 when the receiver is disabled. */
5392                 if (tp->features & RTL_FEATURE_WOL) {
5393                         pci_clear_master(pdev);
5394
5395                         RTL_W8(ChipCmd, CmdRxEnb);
5396                         /* PCI commit */
5397                         RTL_R8(ChipCmd);
5398                 }
5399
5400                 pci_wake_from_d3(pdev, true);
5401                 pci_set_power_state(pdev, PCI_D3hot);
5402         }
5403 }
5404
5405 static struct pci_driver rtl8169_pci_driver = {
5406         .name           = MODULENAME,
5407         .id_table       = rtl8169_pci_tbl,
5408         .probe          = rtl8169_init_one,
5409         .remove         = __devexit_p(rtl8169_remove_one),
5410         .shutdown       = rtl_shutdown,
5411         .driver.pm      = RTL8169_PM_OPS,
5412 };
5413
5414 static int __init rtl8169_init_module(void)
5415 {
5416         return pci_register_driver(&rtl8169_pci_driver);
5417 }
5418
5419 static void __exit rtl8169_cleanup_module(void)
5420 {
5421         pci_unregister_driver(&rtl8169_pci_driver);
5422 }
5423
5424 module_init(rtl8169_init_module);
5425 module_exit(rtl8169_cleanup_module);