drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  46
  47 #ifdef RTL8169_DEBUG
  48 #define assert(expr) \
  49         if (!(expr)) {                                  \
  50                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  51                 #expr,__FILE__,__func__,__LINE__);              \
  52         }
  53 #define dprintk(fmt, args...) \
  54         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  55 #else
  56 #define assert(expr) do {} while (0)
  57 #define dprintk(fmt, args...)   do {} while (0)
  58 #endif /* RTL8169_DEBUG */
  59
  60 #define R8169_MSG_DEFAULT \
  61         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  62
  63 #define TX_BUFFS_AVAIL(tp) \
  64         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  65
  66 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  67    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  68 static const int multicast_filter_limit = 32;
  69
  70 /* MAC address length */
  71 #define MAC_ADDR_LEN    6
  72
  73 #define MAX_READ_REQUEST_SHIFT  12
  74 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  76 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  77
  78 #define R8169_REGS_SIZE         256
  79 #define R8169_NAPI_WEIGHT       64
  80 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  81 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  82 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  83 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  84 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  85
  86 #define RTL8169_TX_TIMEOUT      (6*HZ)
  87 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  88
  89 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  90 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  91 #define RTL_EEPROM_SIG_ADDR     0x0000
  92
  93 /* write/read MMIO register */
  94 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  95 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  96 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  97 #define RTL_R8(reg)             readb (ioaddr + (reg))
  98 #define RTL_R16(reg)            readw (ioaddr + (reg))
  99 #define RTL_R32(reg)            readl (ioaddr + (reg))
 100
 101 enum mac_version {
 102         RTL_GIGA_MAC_VER_01 = 0,
 103         RTL_GIGA_MAC_VER_02,
 104         RTL_GIGA_MAC_VER_03,
 105         RTL_GIGA_MAC_VER_04,
 106         RTL_GIGA_MAC_VER_05,
 107         RTL_GIGA_MAC_VER_06,
 108         RTL_GIGA_MAC_VER_07,
 109         RTL_GIGA_MAC_VER_08,
 110         RTL_GIGA_MAC_VER_09,
 111         RTL_GIGA_MAC_VER_10,
 112         RTL_GIGA_MAC_VER_11,
 113         RTL_GIGA_MAC_VER_12,
 114         RTL_GIGA_MAC_VER_13,
 115         RTL_GIGA_MAC_VER_14,
 116         RTL_GIGA_MAC_VER_15,
 117         RTL_GIGA_MAC_VER_16,
 118         RTL_GIGA_MAC_VER_17,
 119         RTL_GIGA_MAC_VER_18,
 120         RTL_GIGA_MAC_VER_19,
 121         RTL_GIGA_MAC_VER_20,
 122         RTL_GIGA_MAC_VER_21,
 123         RTL_GIGA_MAC_VER_22,
 124         RTL_GIGA_MAC_VER_23,
 125         RTL_GIGA_MAC_VER_24,
 126         RTL_GIGA_MAC_VER_25,
 127         RTL_GIGA_MAC_VER_26,
 128         RTL_GIGA_MAC_VER_27,
 129         RTL_GIGA_MAC_VER_28,
 130         RTL_GIGA_MAC_VER_29,
 131         RTL_GIGA_MAC_VER_30,
 132         RTL_GIGA_MAC_VER_31,
 133         RTL_GIGA_MAC_VER_32,
 134         RTL_GIGA_MAC_VER_33,
 135         RTL_GIGA_MAC_VER_34,
 136         RTL_GIGA_MAC_NONE   = 0xff,
 137 };
 138
 139 enum rtl_tx_desc_version {
 140         RTL_TD_0        = 0,
 141         RTL_TD_1        = 1,
 142 };
 143
 144 #define _R(NAME,TD,FW) \
 145         { .name = NAME, .txd_version = TD, .fw_name = FW }
 146
 147 static const struct {
 148         const char *name;
 149         enum rtl_tx_desc_version txd_version;
 150         const char *fw_name;
 151 } rtl_chip_infos[] = {
 152         /* PCI devices. */
 153         [RTL_GIGA_MAC_VER_01] =
 154                 _R("RTL8169",           RTL_TD_0, NULL),
 155         [RTL_GIGA_MAC_VER_02] =
 156                 _R("RTL8169s",          RTL_TD_0, NULL),
 157         [RTL_GIGA_MAC_VER_03] =
 158                 _R("RTL8110s",          RTL_TD_0, NULL),
 159         [RTL_GIGA_MAC_VER_04] =
 160                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 161         [RTL_GIGA_MAC_VER_05] =
 162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 163         [RTL_GIGA_MAC_VER_06] =
 164                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 165         /* PCI-E devices. */
 166         [RTL_GIGA_MAC_VER_07] =
 167                 _R("RTL8102e",          RTL_TD_1, NULL),
 168         [RTL_GIGA_MAC_VER_08] =
 169                 _R("RTL8102e",          RTL_TD_1, NULL),
 170         [RTL_GIGA_MAC_VER_09] =
 171                 _R("RTL8102e",          RTL_TD_1, NULL),
 172         [RTL_GIGA_MAC_VER_10] =
 173                 _R("RTL8101e",          RTL_TD_0, NULL),
 174         [RTL_GIGA_MAC_VER_11] =
 175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 176         [RTL_GIGA_MAC_VER_12] =
 177                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 178         [RTL_GIGA_MAC_VER_13] =
 179                 _R("RTL8101e",          RTL_TD_0, NULL),
 180         [RTL_GIGA_MAC_VER_14] =
 181                 _R("RTL8100e",          RTL_TD_0, NULL),
 182         [RTL_GIGA_MAC_VER_15] =
 183                 _R("RTL8100e",          RTL_TD_0, NULL),
 184         [RTL_GIGA_MAC_VER_16] =
 185                 _R("RTL8101e",          RTL_TD_0, NULL),
 186         [RTL_GIGA_MAC_VER_17] =
 187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 188         [RTL_GIGA_MAC_VER_18] =
 189                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 190         [RTL_GIGA_MAC_VER_19] =
 191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 192         [RTL_GIGA_MAC_VER_20] =
 193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 194         [RTL_GIGA_MAC_VER_21] =
 195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 196         [RTL_GIGA_MAC_VER_22] =
 197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 198         [RTL_GIGA_MAC_VER_23] =
 199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 200         [RTL_GIGA_MAC_VER_24] =
 201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 202         [RTL_GIGA_MAC_VER_25] =
 203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 204         [RTL_GIGA_MAC_VER_26] =
 205                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 206         [RTL_GIGA_MAC_VER_27] =
 207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 208         [RTL_GIGA_MAC_VER_28] =
 209                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 210         [RTL_GIGA_MAC_VER_29] =
 211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 212         [RTL_GIGA_MAC_VER_30] =
 213                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 214         [RTL_GIGA_MAC_VER_31] =
 215                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 216         [RTL_GIGA_MAC_VER_32] =
 217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 218         [RTL_GIGA_MAC_VER_33] =
 219                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2),
 220         [RTL_GIGA_MAC_VER_34] =
 221                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
 222 };
 223 #undef _R
 224
 225 enum cfg_version {
 226         RTL_CFG_0 = 0x00,
 227         RTL_CFG_1,
 228         RTL_CFG_2
 229 };
 230
 231 static void rtl_hw_start_8169(struct net_device *);
 232 static void rtl_hw_start_8168(struct net_device *);
 233 static void rtl_hw_start_8101(struct net_device *);
 234
 235 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 238         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 239         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 240         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 241         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 242         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 243         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 244         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 245                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 246         { 0x0001,                               0x8168,
 247                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 248         {0,},
 249 };
 250
 251 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 252
 253 static int rx_buf_sz = 16383;
 254 static int use_dac;
 255 static struct {
 256         u32 msg_enable;
 257 } debug = { -1 };
 258
 259 enum rtl_registers {
 260         MAC0            = 0,    /* Ethernet hardware address. */
 261         MAC4            = 4,
 262         MAR0            = 8,    /* Multicast filter. */
 263         CounterAddrLow          = 0x10,
 264         CounterAddrHigh         = 0x14,
 265         TxDescStartAddrLow      = 0x20,
 266         TxDescStartAddrHigh     = 0x24,
 267         TxHDescStartAddrLow     = 0x28,
 268         TxHDescStartAddrHigh    = 0x2c,
 269         FLASH           = 0x30,
 270         ERSR            = 0x36,
 271         ChipCmd         = 0x37,
 272         TxPoll          = 0x38,
 273         IntrMask        = 0x3c,
 274         IntrStatus      = 0x3e,
 275
 276         TxConfig        = 0x40,
 277 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 278 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 279
 280         RxConfig        = 0x44,
 281 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 282 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 283 #define RXCFG_FIFO_SHIFT                13
 284                                         /* No threshold before first PCI xfer */
 285 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 286 #define RXCFG_DMA_SHIFT                 8
 287                                         /* Unlimited maximum PCI burst. */
 288 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 289
 290         RxMissed        = 0x4c,
 291         Cfg9346         = 0x50,
 292         Config0         = 0x51,
 293         Config1         = 0x52,
 294         Config2         = 0x53,
 295         Config3         = 0x54,
 296         Config4         = 0x55,
 297         Config5         = 0x56,
 298         MultiIntr       = 0x5c,
 299         PHYAR           = 0x60,
 300         PHYstatus       = 0x6c,
 301         RxMaxSize       = 0xda,
 302         CPlusCmd        = 0xe0,
 303         IntrMitigate    = 0xe2,
 304         RxDescAddrLow   = 0xe4,
 305         RxDescAddrHigh  = 0xe8,
 306         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 307
 308 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 309
 310         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 311
 312 #define TxPacketMax     (8064 >> 7)
 313
 314         FuncEvent       = 0xf0,
 315         FuncEventMask   = 0xf4,
 316         FuncPresetState = 0xf8,
 317         FuncForceEvent  = 0xfc,
 318 };
 319
 320 enum rtl8110_registers {
 321         TBICSR                  = 0x64,
 322         TBI_ANAR                = 0x68,
 323         TBI_LPAR                = 0x6a,
 324 };
 325
 326 enum rtl8168_8101_registers {
 327         CSIDR                   = 0x64,
 328         CSIAR                   = 0x68,
 329 #define CSIAR_FLAG                      0x80000000
 330 #define CSIAR_WRITE_CMD                 0x80000000
 331 #define CSIAR_BYTE_ENABLE               0x0f
 332 #define CSIAR_BYTE_ENABLE_SHIFT         12
 333 #define CSIAR_ADDR_MASK                 0x0fff
 334         PMCH                    = 0x6f,
 335         EPHYAR                  = 0x80,
 336 #define EPHYAR_FLAG                     0x80000000
 337 #define EPHYAR_WRITE_CMD                0x80000000
 338 #define EPHYAR_REG_MASK                 0x1f
 339 #define EPHYAR_REG_SHIFT                16
 340 #define EPHYAR_DATA_MASK                0xffff
 341         DLLPR                   = 0xd0,
 342 #define PFM_EN                          (1 << 6)
 343         DBG_REG                 = 0xd1,
 344 #define FIX_NAK_1                       (1 << 4)
 345 #define FIX_NAK_2                       (1 << 3)
 346         TWSI                    = 0xd2,
 347         MCU                     = 0xd3,
 348 #define NOW_IS_OOB                      (1 << 7)
 349 #define EN_NDP                          (1 << 3)
 350 #define EN_OOB_RESET                    (1 << 2)
 351         EFUSEAR                 = 0xdc,
 352 #define EFUSEAR_FLAG                    0x80000000
 353 #define EFUSEAR_WRITE_CMD               0x80000000
 354 #define EFUSEAR_READ_CMD                0x00000000
 355 #define EFUSEAR_REG_MASK                0x03ff
 356 #define EFUSEAR_REG_SHIFT               8
 357 #define EFUSEAR_DATA_MASK               0xff
 358 };
 359
 360 enum rtl8168_registers {
 361         LED_FREQ                = 0x1a,
 362         EEE_LED                 = 0x1b,
 363         ERIDR                   = 0x70,
 364         ERIAR                   = 0x74,
 365 #define ERIAR_FLAG                      0x80000000
 366 #define ERIAR_WRITE_CMD                 0x80000000
 367 #define ERIAR_READ_CMD                  0x00000000
 368 #define ERIAR_ADDR_BYTE_ALIGN           4
 369 #define ERIAR_TYPE_SHIFT                16
 370 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 371 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 372 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 373 #define ERIAR_MASK_SHIFT                12
 374 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 375 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 376 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 377         EPHY_RXER_NUM           = 0x7c,
 378         OCPDR                   = 0xb0, /* OCP GPHY access */
 379 #define OCPDR_WRITE_CMD                 0x80000000
 380 #define OCPDR_READ_CMD                  0x00000000
 381 #define OCPDR_REG_MASK                  0x7f
 382 #define OCPDR_GPHY_REG_SHIFT            16
 383 #define OCPDR_DATA_MASK                 0xffff
 384         OCPAR                   = 0xb4,
 385 #define OCPAR_FLAG                      0x80000000
 386 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 387 #define OCPAR_GPHY_READ_CMD             0x0000f060
 388         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 389         MISC                    = 0xf0, /* 8168e only. */
 390 #define TXPLA_RST                       (1 << 29)
 391 #define PWM_EN                          (1 << 22)
 392 };
 393
 394 enum rtl_register_content {
 395         /* InterruptStatusBits */
 396         SYSErr          = 0x8000,
 397         PCSTimeout      = 0x4000,
 398         SWInt           = 0x0100,
 399         TxDescUnavail   = 0x0080,
 400         RxFIFOOver      = 0x0040,
 401         LinkChg         = 0x0020,
 402         RxOverflow      = 0x0010,
 403         TxErr           = 0x0008,
 404         TxOK            = 0x0004,
 405         RxErr           = 0x0002,
 406         RxOK            = 0x0001,
 407
 408         /* RxStatusDesc */
 409         RxFOVF  = (1 << 23),
 410         RxRWT   = (1 << 22),
 411         RxRES   = (1 << 21),
 412         RxRUNT  = (1 << 20),
 413         RxCRC   = (1 << 19),
 414
 415         /* ChipCmdBits */
 416         StopReq         = 0x80,
 417         CmdReset        = 0x10,
 418         CmdRxEnb        = 0x08,
 419         CmdTxEnb        = 0x04,
 420         RxBufEmpty      = 0x01,
 421
 422         /* TXPoll register p.5 */
 423         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 424         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 425         FSWInt          = 0x01,         /* Forced software interrupt */
 426
 427         /* Cfg9346Bits */
 428         Cfg9346_Lock    = 0x00,
 429         Cfg9346_Unlock  = 0xc0,
 430
 431         /* rx_mode_bits */
 432         AcceptErr       = 0x20,
 433         AcceptRunt      = 0x10,
 434         AcceptBroadcast = 0x08,
 435         AcceptMulticast = 0x04,
 436         AcceptMyPhys    = 0x02,
 437         AcceptAllPhys   = 0x01,
 438 #define RX_CONFIG_ACCEPT_MASK           0x3f
 439
 440         /* TxConfigBits */
 441         TxInterFrameGapShift = 24,
 442         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 443
 444         /* Config1 register p.24 */
 445         LEDS1           = (1 << 7),
 446         LEDS0           = (1 << 6),
 447         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 448         Speed_down      = (1 << 4),
 449         MEMMAP          = (1 << 3),
 450         IOMAP           = (1 << 2),
 451         VPD             = (1 << 1),
 452         PMEnable        = (1 << 0),     /* Power Management Enable */
 453
 454         /* Config2 register p. 25 */
 455         PCI_Clock_66MHz = 0x01,
 456         PCI_Clock_33MHz = 0x00,
 457
 458         /* Config3 register p.25 */
 459         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 460         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 461         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 462
 463         /* Config5 register p.27 */
 464         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 465         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 466         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 467         Spi_en          = (1 << 3),
 468         LanWake         = (1 << 1),     /* LanWake enable/disable */
 469         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 470
 471         /* TBICSR p.28 */
 472         TBIReset        = 0x80000000,
 473         TBILoopback     = 0x40000000,
 474         TBINwEnable     = 0x20000000,
 475         TBINwRestart    = 0x10000000,
 476         TBILinkOk       = 0x02000000,
 477         TBINwComplete   = 0x01000000,
 478
 479         /* CPlusCmd p.31 */
 480         EnableBist      = (1 << 15),    // 8168 8101
 481         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 482         Normal_mode     = (1 << 13),    // unused
 483         Force_half_dup  = (1 << 12),    // 8168 8101
 484         Force_rxflow_en = (1 << 11),    // 8168 8101
 485         Force_txflow_en = (1 << 10),    // 8168 8101
 486         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 487         ASF             = (1 << 8),     // 8168 8101
 488         PktCntrDisable  = (1 << 7),     // 8168 8101
 489         Mac_dbgo_sel    = 0x001c,       // 8168
 490         RxVlan          = (1 << 6),
 491         RxChkSum        = (1 << 5),
 492         PCIDAC          = (1 << 4),
 493         PCIMulRW        = (1 << 3),
 494         INTT_0          = 0x0000,       // 8168
 495         INTT_1          = 0x0001,       // 8168
 496         INTT_2          = 0x0002,       // 8168
 497         INTT_3          = 0x0003,       // 8168
 498
 499         /* rtl8169_PHYstatus */
 500         TBI_Enable      = 0x80,
 501         TxFlowCtrl      = 0x40,
 502         RxFlowCtrl      = 0x20,
 503         _1000bpsF       = 0x10,
 504         _100bps         = 0x08,
 505         _10bps          = 0x04,
 506         LinkStatus      = 0x02,
 507         FullDup         = 0x01,
 508
 509         /* _TBICSRBit */
 510         TBILinkOK       = 0x02000000,
 511
 512         /* DumpCounterCommand */
 513         CounterDump     = 0x8,
 514 };
 515
 516 enum rtl_desc_bit {
 517         /* First doubleword. */
 518         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 519         RingEnd         = (1 << 30), /* End of descriptor ring */
 520         FirstFrag       = (1 << 29), /* First segment of a packet */
 521         LastFrag        = (1 << 28), /* Final segment of a packet */
 522 };
 523
 524 /* Generic case. */
 525 enum rtl_tx_desc_bit {
 526         /* First doubleword. */
 527         TD_LSO          = (1 << 27),            /* Large Send Offload */
 528 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 529
 530         /* Second doubleword. */
 531         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 532 };
 533
 534 /* 8169, 8168b and 810x except 8102e. */
 535 enum rtl_tx_desc_bit_0 {
 536         /* First doubleword. */
 537 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 538         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 539         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 540         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 541 };
 542
 543 /* 8102e, 8168c and beyond. */
 544 enum rtl_tx_desc_bit_1 {
 545         /* Second doubleword. */
 546 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 547         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 548         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 549         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 550 };
 551
 552 static const struct rtl_tx_desc_info {
 553         struct {
 554                 u32 udp;
 555                 u32 tcp;
 556         } checksum;
 557         u16 mss_shift;
 558         u16 opts_offset;
 559 } tx_desc_info [] = {
 560         [RTL_TD_0] = {
 561                 .checksum = {
 562                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 563                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 564                 },
 565                 .mss_shift      = TD0_MSS_SHIFT,
 566                 .opts_offset    = 0
 567         },
 568         [RTL_TD_1] = {
 569                 .checksum = {
 570                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 571                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 572                 },
 573                 .mss_shift      = TD1_MSS_SHIFT,
 574                 .opts_offset    = 1
 575         }
 576 };
 577
 578 enum rtl_rx_desc_bit {
 579         /* Rx private */
 580         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 581         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 582
 583 #define RxProtoUDP      (PID1)
 584 #define RxProtoTCP      (PID0)
 585 #define RxProtoIP       (PID1 | PID0)
 586 #define RxProtoMask     RxProtoIP
 587
 588         IPFail          = (1 << 16), /* IP checksum failed */
 589         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 590         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 591         RxVlanTag       = (1 << 16), /* VLAN tag available */
 592 };
 593
 594 #define RsvdMask        0x3fffc000
 595
 596 struct TxDesc {
 597         __le32 opts1;
 598         __le32 opts2;
 599         __le64 addr;
 600 };
 601
 602 struct RxDesc {
 603         __le32 opts1;
 604         __le32 opts2;
 605         __le64 addr;
 606 };
 607
 608 struct ring_info {
 609         struct sk_buff  *skb;
 610         u32             len;
 611         u8              __pad[sizeof(void *) - sizeof(u32)];
 612 };
 613
 614 enum features {
 615         RTL_FEATURE_WOL         = (1 << 0),
 616         RTL_FEATURE_MSI         = (1 << 1),
 617         RTL_FEATURE_GMII        = (1 << 2),
 618 };
 619
 620 struct rtl8169_counters {
 621         __le64  tx_packets;
 622         __le64  rx_packets;
 623         __le64  tx_errors;
 624         __le32  rx_errors;
 625         __le16  rx_missed;
 626         __le16  align_errors;
 627         __le32  tx_one_collision;
 628         __le32  tx_multi_collision;
 629         __le64  rx_unicast;
 630         __le64  rx_broadcast;
 631         __le32  rx_multicast;
 632         __le16  tx_aborted;
 633         __le16  tx_underun;
 634 };
 635
 636 struct rtl8169_private {
 637         void __iomem *mmio_addr;        /* memory map physical address */
 638         struct pci_dev *pci_dev;
 639         struct net_device *dev;
 640         struct napi_struct napi;
 641         spinlock_t lock;
 642         u32 msg_enable;
 643         u16 txd_version;
 644         u16 mac_version;
 645         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 646         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 647         u32 dirty_rx;
 648         u32 dirty_tx;
 649         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 650         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 651         dma_addr_t TxPhyAddr;
 652         dma_addr_t RxPhyAddr;
 653         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 654         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 655         struct timer_list timer;
 656         u16 cp_cmd;
 657         u16 intr_event;
 658         u16 napi_event;
 659         u16 intr_mask;
 660
 661         struct mdio_ops {
 662                 void (*write)(void __iomem *, int, int);
 663                 int (*read)(void __iomem *, int);
 664         } mdio_ops;
 665
 666         struct pll_power_ops {
 667                 void (*down)(struct rtl8169_private *);
 668                 void (*up)(struct rtl8169_private *);
 669         } pll_power_ops;
 670
 671         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 672         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 673         void (*phy_reset_enable)(struct rtl8169_private *tp);
 674         void (*hw_start)(struct net_device *);
 675         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 676         unsigned int (*link_ok)(void __iomem *);
 677         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 678         struct delayed_work task;
 679         unsigned features;
 680
 681         struct mii_if_info mii;
 682         struct rtl8169_counters counters;
 683         u32 saved_wolopts;
 684
 685         struct rtl_fw {
 686                 const struct firmware *fw;
 687
 688 #define RTL_VER_SIZE            32
 689
 690                 char version[RTL_VER_SIZE];
 691
 692                 struct rtl_fw_phy_action {
 693                         __le32 *code;
 694                         size_t size;
 695                 } phy_action;
 696         } *rtl_fw;
 697 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 698 };
 699
 700 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 701 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 702 module_param(use_dac, int, 0);
 703 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 704 module_param_named(debug, debug.msg_enable, int, 0);
 705 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 706 MODULE_LICENSE("GPL");
 707 MODULE_VERSION(RTL8169_VERSION);
 708 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 709 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 710 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 711 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 712 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 713
 714 static int rtl8169_open(struct net_device *dev);
 715 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 716                                       struct net_device *dev);
 717 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 718 static int rtl8169_init_ring(struct net_device *dev);
 719 static void rtl_hw_start(struct net_device *dev);
 720 static int rtl8169_close(struct net_device *dev);
 721 static void rtl_set_rx_mode(struct net_device *dev);
 722 static void rtl8169_tx_timeout(struct net_device *dev);
 723 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 724 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 725                                 void __iomem *, u32 budget);
 726 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 727 static void rtl8169_down(struct net_device *dev);
 728 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 729 static int rtl8169_poll(struct napi_struct *napi, int budget);
 730
 731 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 732 {
 733         void __iomem *ioaddr = tp->mmio_addr;
 734         int i;
 735
 736         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 737         for (i = 0; i < 20; i++) {
 738                 udelay(100);
 739                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 740                         break;
 741         }
 742         return RTL_R32(OCPDR);
 743 }
 744
 745 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 746 {
 747         void __iomem *ioaddr = tp->mmio_addr;
 748         int i;
 749
 750         RTL_W32(OCPDR, data);
 751         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 752         for (i = 0; i < 20; i++) {
 753                 udelay(100);
 754                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 755                         break;
 756         }
 757 }
 758
 759 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 760 {
 761         void __iomem *ioaddr = tp->mmio_addr;
 762         int i;
 763
 764         RTL_W8(ERIDR, cmd);
 765         RTL_W32(ERIAR, 0x800010e8);
 766         msleep(2);
 767         for (i = 0; i < 5; i++) {
 768                 udelay(100);
 769                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 770                         break;
 771         }
 772
 773         ocp_write(tp, 0x1, 0x30, 0x00000001);
 774 }
 775
 776 #define OOB_CMD_RESET           0x00
 777 #define OOB_CMD_DRIVER_START    0x05
 778 #define OOB_CMD_DRIVER_STOP     0x06
 779
 780 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 781 {
 782         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 783 }
 784
 785 static void rtl8168_driver_start(struct rtl8169_private *tp)
 786 {
 787         u16 reg;
 788         int i;
 789
 790         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 791
 792         reg = rtl8168_get_ocp_reg(tp);
 793
 794         for (i = 0; i < 10; i++) {
 795                 msleep(10);
 796                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 797                         break;
 798         }
 799 }
 800
 801 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 802 {
 803         u16 reg;
 804         int i;
 805
 806         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 807
 808         reg = rtl8168_get_ocp_reg(tp);
 809
 810         for (i = 0; i < 10; i++) {
 811                 msleep(10);
 812                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 813                         break;
 814         }
 815 }
 816
 817 static int r8168dp_check_dash(struct rtl8169_private *tp)
 818 {
 819         u16 reg = rtl8168_get_ocp_reg(tp);
 820
 821         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 822 }
 823
 824 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 825 {
 826         int i;
 827
 828         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 829
 830         for (i = 20; i > 0; i--) {
 831                 /*
 832                  * Check if the RTL8169 has completed writing to the specified
 833                  * MII register.
 834                  */
 835                 if (!(RTL_R32(PHYAR) & 0x80000000))
 836                         break;
 837                 udelay(25);
 838         }
 839         /*
 840          * According to hardware specs a 20us delay is required after write
 841          * complete indication, but before sending next command.
 842          */
 843         udelay(20);
 844 }
 845
 846 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 847 {
 848         int i, value = -1;
 849
 850         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 851
 852         for (i = 20; i > 0; i--) {
 853                 /*
 854                  * Check if the RTL8169 has completed retrieving data from
 855                  * the specified MII register.
 856                  */
 857                 if (RTL_R32(PHYAR) & 0x80000000) {
 858                         value = RTL_R32(PHYAR) & 0xffff;
 859                         break;
 860                 }
 861                 udelay(25);
 862         }
 863         /*
 864          * According to hardware specs a 20us delay is required after read
 865          * complete indication, but before sending next command.
 866          */
 867         udelay(20);
 868
 869         return value;
 870 }
 871
 872 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 873 {
 874         int i;
 875
 876         RTL_W32(OCPDR, data |
 877                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 878         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 879         RTL_W32(EPHY_RXER_NUM, 0);
 880
 881         for (i = 0; i < 100; i++) {
 882                 mdelay(1);
 883                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 884                         break;
 885         }
 886 }
 887
 888 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 889 {
 890         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 891                 (value & OCPDR_DATA_MASK));
 892 }
 893
 894 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 895 {
 896         int i;
 897
 898         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 899
 900         mdelay(1);
 901         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 902         RTL_W32(EPHY_RXER_NUM, 0);
 903
 904         for (i = 0; i < 100; i++) {
 905                 mdelay(1);
 906                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 907                         break;
 908         }
 909
 910         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 911 }
 912
 913 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 914
 915 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 916 {
 917         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 918 }
 919
 920 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 921 {
 922         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 923 }
 924
 925 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 926 {
 927         r8168dp_2_mdio_start(ioaddr);
 928
 929         r8169_mdio_write(ioaddr, reg_addr, value);
 930
 931         r8168dp_2_mdio_stop(ioaddr);
 932 }
 933
 934 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 935 {
 936         int value;
 937
 938         r8168dp_2_mdio_start(ioaddr);
 939
 940         value = r8169_mdio_read(ioaddr, reg_addr);
 941
 942         r8168dp_2_mdio_stop(ioaddr);
 943
 944         return value;
 945 }
 946
 947 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 948 {
 949         tp->mdio_ops.write(tp->mmio_addr, location, val);
 950 }
 951
 952 static int rtl_readphy(struct rtl8169_private *tp, int location)
 953 {
 954         return tp->mdio_ops.read(tp->mmio_addr, location);
 955 }
 956
 957 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 958 {
 959         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 960 }
 961
 962 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 963 {
 964         int val;
 965
 966         val = rtl_readphy(tp, reg_addr);
 967         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 968 }
 969
 970 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 971                            int val)
 972 {
 973         struct rtl8169_private *tp = netdev_priv(dev);
 974
 975         rtl_writephy(tp, location, val);
 976 }
 977
 978 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 979 {
 980         struct rtl8169_private *tp = netdev_priv(dev);
 981
 982         return rtl_readphy(tp, location);
 983 }
 984
 985 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 986 {
 987         unsigned int i;
 988
 989         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 990                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 991
 992         for (i = 0; i < 100; i++) {
 993                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 994                         break;
 995                 udelay(10);
 996         }
 997 }
 998
 999 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1000 {
1001         u16 value = 0xffff;
1002         unsigned int i;
1003
1004         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1005
1006         for (i = 0; i < 100; i++) {
1007                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1008                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1009                         break;
1010                 }
1011                 udelay(10);
1012         }
1013
1014         return value;
1015 }
1016
1017 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1018 {
1019         unsigned int i;
1020
1021         RTL_W32(CSIDR, value);
1022         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1023                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1024
1025         for (i = 0; i < 100; i++) {
1026                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1027                         break;
1028                 udelay(10);
1029         }
1030 }
1031
1032 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1033 {
1034         u32 value = ~0x00;
1035         unsigned int i;
1036
1037         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1038                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1039
1040         for (i = 0; i < 100; i++) {
1041                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1042                         value = RTL_R32(CSIDR);
1043                         break;
1044                 }
1045                 udelay(10);
1046         }
1047
1048         return value;
1049 }
1050
1051 static
1052 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1053 {
1054         unsigned int i;
1055
1056         BUG_ON((addr & 3) || (mask == 0));
1057         RTL_W32(ERIDR, val);
1058         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1059
1060         for (i = 0; i < 100; i++) {
1061                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1062                         break;
1063                 udelay(100);
1064         }
1065 }
1066
1067 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1068 {
1069         u32 value = ~0x00;
1070         unsigned int i;
1071
1072         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1073
1074         for (i = 0; i < 100; i++) {
1075                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1076                         value = RTL_R32(ERIDR);
1077                         break;
1078                 }
1079                 udelay(100);
1080         }
1081
1082         return value;
1083 }
1084
1085 static void
1086 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1087 {
1088         u32 val;
1089
1090         val = rtl_eri_read(ioaddr, addr, type);
1091         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1092 }
1093
1094 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1095 {
1096         u8 value = 0xff;
1097         unsigned int i;
1098
1099         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1100
1101         for (i = 0; i < 300; i++) {
1102                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1103                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1104                         break;
1105                 }
1106                 udelay(100);
1107         }
1108
1109         return value;
1110 }
1111
1112 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1113 {
1114         RTL_W16(IntrMask, 0x0000);
1115
1116         RTL_W16(IntrStatus, 0xffff);
1117 }
1118
1119 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1120 {
1121         void __iomem *ioaddr = tp->mmio_addr;
1122
1123         return RTL_R32(TBICSR) & TBIReset;
1124 }
1125
1126 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1127 {
1128         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1129 }
1130
1131 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1132 {
1133         return RTL_R32(TBICSR) & TBILinkOk;
1134 }
1135
1136 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1137 {
1138         return RTL_R8(PHYstatus) & LinkStatus;
1139 }
1140
1141 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1142 {
1143         void __iomem *ioaddr = tp->mmio_addr;
1144
1145         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1146 }
1147
1148 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1149 {
1150         unsigned int val;
1151
1152         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1153         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1154 }
1155
1156 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1157 {
1158         void __iomem *ioaddr = tp->mmio_addr;
1159         struct net_device *dev = tp->dev;
1160
1161         if (!netif_running(dev))
1162                 return;
1163
1164         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1165                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1166                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1167                                       0x00000011, ERIAR_EXGMAC);
1168                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1169                                       0x00000005, ERIAR_EXGMAC);
1170                 } else if (RTL_R8(PHYstatus) & _100bps) {
1171                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1172                                       0x0000001f, ERIAR_EXGMAC);
1173                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1174                                       0x00000005, ERIAR_EXGMAC);
1175                 } else {
1176                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1177                                       0x0000001f, ERIAR_EXGMAC);
1178                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1179                                       0x0000003f, ERIAR_EXGMAC);
1180                 }
1181                 /* Reset packet filter */
1182                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1183                              ERIAR_EXGMAC);
1184                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1185                              ERIAR_EXGMAC);
1186         }
1187 }
1188
1189 static void __rtl8169_check_link_status(struct net_device *dev,
1190                                         struct rtl8169_private *tp,
1191                                         void __iomem *ioaddr, bool pm)
1192 {
1193         unsigned long flags;
1194
1195         spin_lock_irqsave(&tp->lock, flags);
1196         if (tp->link_ok(ioaddr)) {
1197                 rtl_link_chg_patch(tp);
1198                 /* This is to cancel a scheduled suspend if there's one. */
1199                 if (pm)
1200                         pm_request_resume(&tp->pci_dev->dev);
1201                 netif_carrier_on(dev);
1202                 if (net_ratelimit())
1203                         netif_info(tp, ifup, dev, "link up\n");
1204         } else {
1205                 netif_carrier_off(dev);
1206                 netif_info(tp, ifdown, dev, "link down\n");
1207                 if (pm)
1208                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1209         }
1210         spin_unlock_irqrestore(&tp->lock, flags);
1211 }
1212
1213 static void rtl8169_check_link_status(struct net_device *dev,
1214                                       struct rtl8169_private *tp,
1215                                       void __iomem *ioaddr)
1216 {
1217         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1218 }
1219
1220 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1221
1222 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1223 {
1224         void __iomem *ioaddr = tp->mmio_addr;
1225         u8 options;
1226         u32 wolopts = 0;
1227
1228         options = RTL_R8(Config1);
1229         if (!(options & PMEnable))
1230                 return 0;
1231
1232         options = RTL_R8(Config3);
1233         if (options & LinkUp)
1234                 wolopts |= WAKE_PHY;
1235         if (options & MagicPacket)
1236                 wolopts |= WAKE_MAGIC;
1237
1238         options = RTL_R8(Config5);
1239         if (options & UWF)
1240                 wolopts |= WAKE_UCAST;
1241         if (options & BWF)
1242                 wolopts |= WAKE_BCAST;
1243         if (options & MWF)
1244                 wolopts |= WAKE_MCAST;
1245
1246         return wolopts;
1247 }
1248
1249 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1250 {
1251         struct rtl8169_private *tp = netdev_priv(dev);
1252
1253         spin_lock_irq(&tp->lock);
1254
1255         wol->supported = WAKE_ANY;
1256         wol->wolopts = __rtl8169_get_wol(tp);
1257
1258         spin_unlock_irq(&tp->lock);
1259 }
1260
1261 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1262 {
1263         void __iomem *ioaddr = tp->mmio_addr;
1264         unsigned int i;
1265         static const struct {
1266                 u32 opt;
1267                 u16 reg;
1268                 u8  mask;
1269         } cfg[] = {
1270                 { WAKE_ANY,   Config1, PMEnable },
1271                 { WAKE_PHY,   Config3, LinkUp },
1272                 { WAKE_MAGIC, Config3, MagicPacket },
1273                 { WAKE_UCAST, Config5, UWF },
1274                 { WAKE_BCAST, Config5, BWF },
1275                 { WAKE_MCAST, Config5, MWF },
1276                 { WAKE_ANY,   Config5, LanWake }
1277         };
1278
1279         RTL_W8(Cfg9346, Cfg9346_Unlock);
1280
1281         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1282                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1283                 if (wolopts & cfg[i].opt)
1284                         options |= cfg[i].mask;
1285                 RTL_W8(cfg[i].reg, options);
1286         }
1287
1288         RTL_W8(Cfg9346, Cfg9346_Lock);
1289 }
1290
1291 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1292 {
1293         struct rtl8169_private *tp = netdev_priv(dev);
1294
1295         spin_lock_irq(&tp->lock);
1296
1297         if (wol->wolopts)
1298                 tp->features |= RTL_FEATURE_WOL;
1299         else
1300                 tp->features &= ~RTL_FEATURE_WOL;
1301         __rtl8169_set_wol(tp, wol->wolopts);
1302         spin_unlock_irq(&tp->lock);
1303
1304         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1305
1306         return 0;
1307 }
1308
1309 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1310 {
1311         return rtl_chip_infos[tp->mac_version].fw_name;
1312 }
1313
1314 static void rtl8169_get_drvinfo(struct net_device *dev,
1315                                 struct ethtool_drvinfo *info)
1316 {
1317         struct rtl8169_private *tp = netdev_priv(dev);
1318         struct rtl_fw *rtl_fw = tp->rtl_fw;
1319
1320         strcpy(info->driver, MODULENAME);
1321         strcpy(info->version, RTL8169_VERSION);
1322         strcpy(info->bus_info, pci_name(tp->pci_dev));
1323         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1324         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1325                rtl_fw->version);
1326 }
1327
1328 static int rtl8169_get_regs_len(struct net_device *dev)
1329 {
1330         return R8169_REGS_SIZE;
1331 }
1332
1333 static int rtl8169_set_speed_tbi(struct net_device *dev,
1334                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1335 {
1336         struct rtl8169_private *tp = netdev_priv(dev);
1337         void __iomem *ioaddr = tp->mmio_addr;
1338         int ret = 0;
1339         u32 reg;
1340
1341         reg = RTL_R32(TBICSR);
1342         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1343             (duplex == DUPLEX_FULL)) {
1344                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1345         } else if (autoneg == AUTONEG_ENABLE)
1346                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1347         else {
1348                 netif_warn(tp, link, dev,
1349                            "incorrect speed setting refused in TBI mode\n");
1350                 ret = -EOPNOTSUPP;
1351         }
1352
1353         return ret;
1354 }
1355
1356 static int rtl8169_set_speed_xmii(struct net_device *dev,
1357                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1358 {
1359         struct rtl8169_private *tp = netdev_priv(dev);
1360         int giga_ctrl, bmcr;
1361         int rc = -EINVAL;
1362
1363         rtl_writephy(tp, 0x1f, 0x0000);
1364
1365         if (autoneg == AUTONEG_ENABLE) {
1366                 int auto_nego;
1367
1368                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1369                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1370                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1371
1372                 if (adv & ADVERTISED_10baseT_Half)
1373                         auto_nego |= ADVERTISE_10HALF;
1374                 if (adv & ADVERTISED_10baseT_Full)
1375                         auto_nego |= ADVERTISE_10FULL;
1376                 if (adv & ADVERTISED_100baseT_Half)
1377                         auto_nego |= ADVERTISE_100HALF;
1378                 if (adv & ADVERTISED_100baseT_Full)
1379                         auto_nego |= ADVERTISE_100FULL;
1380
1381                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1382
1383                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1384                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1385
1386                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1387                 if (tp->mii.supports_gmii) {
1388                         if (adv & ADVERTISED_1000baseT_Half)
1389                                 giga_ctrl |= ADVERTISE_1000HALF;
1390                         if (adv & ADVERTISED_1000baseT_Full)
1391                                 giga_ctrl |= ADVERTISE_1000FULL;
1392                 } else if (adv & (ADVERTISED_1000baseT_Half |
1393                                   ADVERTISED_1000baseT_Full)) {
1394                         netif_info(tp, link, dev,
1395                                    "PHY does not support 1000Mbps\n");
1396                         goto out;
1397                 }
1398
1399                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1400
1401                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1402                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1403         } else {
1404                 giga_ctrl = 0;
1405
1406                 if (speed == SPEED_10)
1407                         bmcr = 0;
1408                 else if (speed == SPEED_100)
1409                         bmcr = BMCR_SPEED100;
1410                 else
1411                         goto out;
1412
1413                 if (duplex == DUPLEX_FULL)
1414                         bmcr |= BMCR_FULLDPLX;
1415         }
1416
1417         rtl_writephy(tp, MII_BMCR, bmcr);
1418
1419         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1420             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1421                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1422                         rtl_writephy(tp, 0x17, 0x2138);
1423                         rtl_writephy(tp, 0x0e, 0x0260);
1424                 } else {
1425                         rtl_writephy(tp, 0x17, 0x2108);
1426                         rtl_writephy(tp, 0x0e, 0x0000);
1427                 }
1428         }
1429
1430         rc = 0;
1431 out:
1432         return rc;
1433 }
1434
1435 static int rtl8169_set_speed(struct net_device *dev,
1436                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1437 {
1438         struct rtl8169_private *tp = netdev_priv(dev);
1439         int ret;
1440
1441         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1442         if (ret < 0)
1443                 goto out;
1444
1445         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1446             (advertising & ADVERTISED_1000baseT_Full)) {
1447                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1448         }
1449 out:
1450         return ret;
1451 }
1452
1453 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1454 {
1455         struct rtl8169_private *tp = netdev_priv(dev);
1456         unsigned long flags;
1457         int ret;
1458
1459         del_timer_sync(&tp->timer);
1460
1461         spin_lock_irqsave(&tp->lock, flags);
1462         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1463                                 cmd->duplex, cmd->advertising);
1464         spin_unlock_irqrestore(&tp->lock, flags);
1465
1466         return ret;
1467 }
1468
1469 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1470 {
1471         if (dev->mtu > TD_MSS_MAX)
1472                 features &= ~NETIF_F_ALL_TSO;
1473
1474         return features;
1475 }
1476
1477 static int rtl8169_set_features(struct net_device *dev, u32 features)
1478 {
1479         struct rtl8169_private *tp = netdev_priv(dev);
1480         void __iomem *ioaddr = tp->mmio_addr;
1481         unsigned long flags;
1482
1483         spin_lock_irqsave(&tp->lock, flags);
1484
1485         if (features & NETIF_F_RXCSUM)
1486                 tp->cp_cmd |= RxChkSum;
1487         else
1488                 tp->cp_cmd &= ~RxChkSum;
1489
1490         if (dev->features & NETIF_F_HW_VLAN_RX)
1491                 tp->cp_cmd |= RxVlan;
1492         else
1493                 tp->cp_cmd &= ~RxVlan;
1494
1495         RTL_W16(CPlusCmd, tp->cp_cmd);
1496         RTL_R16(CPlusCmd);
1497
1498         spin_unlock_irqrestore(&tp->lock, flags);
1499
1500         return 0;
1501 }
1502
1503 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1504                                       struct sk_buff *skb)
1505 {
1506         return (vlan_tx_tag_present(skb)) ?
1507                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1508 }
1509
1510 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1511 {
1512         u32 opts2 = le32_to_cpu(desc->opts2);
1513
1514         if (opts2 & RxVlanTag)
1515                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1516
1517         desc->opts2 = 0;
1518 }
1519
1520 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1521 {
1522         struct rtl8169_private *tp = netdev_priv(dev);
1523         void __iomem *ioaddr = tp->mmio_addr;
1524         u32 status;
1525
1526         cmd->supported =
1527                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1528         cmd->port = PORT_FIBRE;
1529         cmd->transceiver = XCVR_INTERNAL;
1530
1531         status = RTL_R32(TBICSR);
1532         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1533         cmd->autoneg = !!(status & TBINwEnable);
1534
1535         ethtool_cmd_speed_set(cmd, SPEED_1000);
1536         cmd->duplex = DUPLEX_FULL; /* Always set */
1537
1538         return 0;
1539 }
1540
1541 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1542 {
1543         struct rtl8169_private *tp = netdev_priv(dev);
1544
1545         return mii_ethtool_gset(&tp->mii, cmd);
1546 }
1547
1548 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1549 {
1550         struct rtl8169_private *tp = netdev_priv(dev);
1551         unsigned long flags;
1552         int rc;
1553
1554         spin_lock_irqsave(&tp->lock, flags);
1555
1556         rc = tp->get_settings(dev, cmd);
1557
1558         spin_unlock_irqrestore(&tp->lock, flags);
1559         return rc;
1560 }
1561
1562 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1563                              void *p)
1564 {
1565         struct rtl8169_private *tp = netdev_priv(dev);
1566         unsigned long flags;
1567
1568         if (regs->len > R8169_REGS_SIZE)
1569                 regs->len = R8169_REGS_SIZE;
1570
1571         spin_lock_irqsave(&tp->lock, flags);
1572         memcpy_fromio(p, tp->mmio_addr, regs->len);
1573         spin_unlock_irqrestore(&tp->lock, flags);
1574 }
1575
1576 static u32 rtl8169_get_msglevel(struct net_device *dev)
1577 {
1578         struct rtl8169_private *tp = netdev_priv(dev);
1579
1580         return tp->msg_enable;
1581 }
1582
1583 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1584 {
1585         struct rtl8169_private *tp = netdev_priv(dev);
1586
1587         tp->msg_enable = value;
1588 }
1589
1590 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1591         "tx_packets",
1592         "rx_packets",
1593         "tx_errors",
1594         "rx_errors",
1595         "rx_missed",
1596         "align_errors",
1597         "tx_single_collisions",
1598         "tx_multi_collisions",
1599         "unicast",
1600         "broadcast",
1601         "multicast",
1602         "tx_aborted",
1603         "tx_underrun",
1604 };
1605
1606 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1607 {
1608         switch (sset) {
1609         case ETH_SS_STATS:
1610                 return ARRAY_SIZE(rtl8169_gstrings);
1611         default:
1612                 return -EOPNOTSUPP;
1613         }
1614 }
1615
1616 static void rtl8169_update_counters(struct net_device *dev)
1617 {
1618         struct rtl8169_private *tp = netdev_priv(dev);
1619         void __iomem *ioaddr = tp->mmio_addr;
1620         struct device *d = &tp->pci_dev->dev;
1621         struct rtl8169_counters *counters;
1622         dma_addr_t paddr;
1623         u32 cmd;
1624         int wait = 1000;
1625
1626         /*
1627          * Some chips are unable to dump tally counters when the receiver
1628          * is disabled.
1629          */
1630         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1631                 return;
1632
1633         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1634         if (!counters)
1635                 return;
1636
1637         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1638         cmd = (u64)paddr & DMA_BIT_MASK(32);
1639         RTL_W32(CounterAddrLow, cmd);
1640         RTL_W32(CounterAddrLow, cmd | CounterDump);
1641
1642         while (wait--) {
1643                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1644                         memcpy(&tp->counters, counters, sizeof(*counters));
1645                         break;
1646                 }
1647                 udelay(10);
1648         }
1649
1650         RTL_W32(CounterAddrLow, 0);
1651         RTL_W32(CounterAddrHigh, 0);
1652
1653         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1654 }
1655
1656 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1657                                       struct ethtool_stats *stats, u64 *data)
1658 {
1659         struct rtl8169_private *tp = netdev_priv(dev);
1660
1661         ASSERT_RTNL();
1662
1663         rtl8169_update_counters(dev);
1664
1665         data[0] = le64_to_cpu(tp->counters.tx_packets);
1666         data[1] = le64_to_cpu(tp->counters.rx_packets);
1667         data[2] = le64_to_cpu(tp->counters.tx_errors);
1668         data[3] = le32_to_cpu(tp->counters.rx_errors);
1669         data[4] = le16_to_cpu(tp->counters.rx_missed);
1670         data[5] = le16_to_cpu(tp->counters.align_errors);
1671         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1672         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1673         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1674         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1675         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1676         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1677         data[12] = le16_to_cpu(tp->counters.tx_underun);
1678 }
1679
1680 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1681 {
1682         switch(stringset) {
1683         case ETH_SS_STATS:
1684                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1685                 break;
1686         }
1687 }
1688
1689 static const struct ethtool_ops rtl8169_ethtool_ops = {
1690         .get_drvinfo            = rtl8169_get_drvinfo,
1691         .get_regs_len           = rtl8169_get_regs_len,
1692         .get_link               = ethtool_op_get_link,
1693         .get_settings           = rtl8169_get_settings,
1694         .set_settings           = rtl8169_set_settings,
1695         .get_msglevel           = rtl8169_get_msglevel,
1696         .set_msglevel           = rtl8169_set_msglevel,
1697         .get_regs               = rtl8169_get_regs,
1698         .get_wol                = rtl8169_get_wol,
1699         .set_wol                = rtl8169_set_wol,
1700         .get_strings            = rtl8169_get_strings,
1701         .get_sset_count         = rtl8169_get_sset_count,
1702         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1703 };
1704
1705 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1706                                     struct net_device *dev, u8 default_version)
1707 {
1708         void __iomem *ioaddr = tp->mmio_addr;
1709         /*
1710          * The driver currently handles the 8168Bf and the 8168Be identically
1711          * but they can be identified more specifically through the test below
1712          * if needed:
1713          *
1714          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1715          *
1716          * Same thing for the 8101Eb and the 8101Ec:
1717          *
1718          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1719          */
1720         static const struct rtl_mac_info {
1721                 u32 mask;
1722                 u32 val;
1723                 int mac_version;
1724         } mac_info[] = {
1725                 /* 8168E family. */
1726                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1727                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1728                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1729                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1730
1731                 /* 8168D family. */
1732                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1733                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1734                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1735
1736                 /* 8168DP family. */
1737                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1738                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1739                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1740
1741                 /* 8168C family. */
1742                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1743                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1744                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1745                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1746                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1747                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1748                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1749                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1750                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1751
1752                 /* 8168B family. */
1753                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1754                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1755                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1756                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1757
1758                 /* 8101 family. */
1759                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1760                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1761                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1762                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1763                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1764                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1765                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1766                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1767                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1768                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1769                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1770                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1771                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1772                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1773                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1774                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1775                 /* FIXME: where did these entries come from ? -- FR */
1776                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1777                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1778
1779                 /* 8110 family. */
1780                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1781                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1782                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1783                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1784                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1785                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1786
1787                 /* Catch-all */
1788                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1789         };
1790         const struct rtl_mac_info *p = mac_info;
1791         u32 reg;
1792
1793         reg = RTL_R32(TxConfig);
1794         while ((reg & p->mask) != p->val)
1795                 p++;
1796         tp->mac_version = p->mac_version;
1797
1798         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1799                 netif_notice(tp, probe, dev,
1800                              "unknown MAC, using family default\n");
1801                 tp->mac_version = default_version;
1802         }
1803 }
1804
1805 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1806 {
1807         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1808 }
1809
1810 struct phy_reg {
1811         u16 reg;
1812         u16 val;
1813 };
1814
1815 static void rtl_writephy_batch(struct rtl8169_private *tp,
1816                                const struct phy_reg *regs, int len)
1817 {
1818         while (len-- > 0) {
1819                 rtl_writephy(tp, regs->reg, regs->val);
1820                 regs++;
1821         }
1822 }
1823
1824 #define PHY_READ                0x00000000
1825 #define PHY_DATA_OR             0x10000000
1826 #define PHY_DATA_AND            0x20000000
1827 #define PHY_BJMPN               0x30000000
1828 #define PHY_READ_EFUSE          0x40000000
1829 #define PHY_READ_MAC_BYTE       0x50000000
1830 #define PHY_WRITE_MAC_BYTE      0x60000000
1831 #define PHY_CLEAR_READCOUNT     0x70000000
1832 #define PHY_WRITE               0x80000000
1833 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1834 #define PHY_COMP_EQ_SKIPN       0xa0000000
1835 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1836 #define PHY_WRITE_PREVIOUS      0xc0000000
1837 #define PHY_SKIPN               0xd0000000
1838 #define PHY_DELAY_MS            0xe0000000
1839 #define PHY_WRITE_ERI_WORD      0xf0000000
1840
1841 struct fw_info {
1842         u32     magic;
1843         char    version[RTL_VER_SIZE];
1844         __le32  fw_start;
1845         __le32  fw_len;
1846         u8      chksum;
1847 } __packed;
1848
1849 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1850
1851 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1852 {
1853         const struct firmware *fw = rtl_fw->fw;
1854         struct fw_info *fw_info = (struct fw_info *)fw->data;
1855         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1856         char *version = rtl_fw->version;
1857         bool rc = false;
1858
1859         if (fw->size < FW_OPCODE_SIZE)
1860                 goto out;
1861
1862         if (!fw_info->magic) {
1863                 size_t i, size, start;
1864                 u8 checksum = 0;
1865
1866                 if (fw->size < sizeof(*fw_info))
1867                         goto out;
1868
1869                 for (i = 0; i < fw->size; i++)
1870                         checksum += fw->data[i];
1871                 if (checksum != 0)
1872                         goto out;
1873
1874                 start = le32_to_cpu(fw_info->fw_start);
1875                 if (start > fw->size)
1876                         goto out;
1877
1878                 size = le32_to_cpu(fw_info->fw_len);
1879                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1880                         goto out;
1881
1882                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1883
1884                 pa->code = (__le32 *)(fw->data + start);
1885                 pa->size = size;
1886         } else {
1887                 if (fw->size % FW_OPCODE_SIZE)
1888                         goto out;
1889
1890                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1891
1892                 pa->code = (__le32 *)fw->data;
1893                 pa->size = fw->size / FW_OPCODE_SIZE;
1894         }
1895         version[RTL_VER_SIZE - 1] = 0;
1896
1897         rc = true;
1898 out:
1899         return rc;
1900 }
1901
1902 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1903                            struct rtl_fw_phy_action *pa)
1904 {
1905         bool rc = false;
1906         size_t index;
1907
1908         for (index = 0; index < pa->size; index++) {
1909                 u32 action = le32_to_cpu(pa->code[index]);
1910                 u32 regno = (action & 0x0fff0000) >> 16;
1911
1912                 switch(action & 0xf0000000) {
1913                 case PHY_READ:
1914                 case PHY_DATA_OR:
1915                 case PHY_DATA_AND:
1916                 case PHY_READ_EFUSE:
1917                 case PHY_CLEAR_READCOUNT:
1918                 case PHY_WRITE:
1919                 case PHY_WRITE_PREVIOUS:
1920                 case PHY_DELAY_MS:
1921                         break;
1922
1923                 case PHY_BJMPN:
1924                         if (regno > index) {
1925                                 netif_err(tp, ifup, tp->dev,
1926                                           "Out of range of firmware\n");
1927                                 goto out;
1928                         }
1929                         break;
1930                 case PHY_READCOUNT_EQ_SKIP:
1931                         if (index + 2 >= pa->size) {
1932                                 netif_err(tp, ifup, tp->dev,
1933                                           "Out of range of firmware\n");
1934                                 goto out;
1935                         }
1936                         break;
1937                 case PHY_COMP_EQ_SKIPN:
1938                 case PHY_COMP_NEQ_SKIPN:
1939                 case PHY_SKIPN:
1940                         if (index + 1 + regno >= pa->size) {
1941                                 netif_err(tp, ifup, tp->dev,
1942                                           "Out of range of firmware\n");
1943                                 goto out;
1944                         }
1945                         break;
1946
1947                 case PHY_READ_MAC_BYTE:
1948                 case PHY_WRITE_MAC_BYTE:
1949                 case PHY_WRITE_ERI_WORD:
1950                 default:
1951                         netif_err(tp, ifup, tp->dev,
1952                                   "Invalid action 0x%08x\n", action);
1953                         goto out;
1954                 }
1955         }
1956         rc = true;
1957 out:
1958         return rc;
1959 }
1960
1961 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1962 {
1963         struct net_device *dev = tp->dev;
1964         int rc = -EINVAL;
1965
1966         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1967                 netif_err(tp, ifup, dev, "invalid firwmare\n");
1968                 goto out;
1969         }
1970
1971         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1972                 rc = 0;
1973 out:
1974         return rc;
1975 }
1976
1977 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1978 {
1979         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1980         u32 predata, count;
1981         size_t index;
1982
1983         predata = count = 0;
1984
1985         for (index = 0; index < pa->size; ) {
1986                 u32 action = le32_to_cpu(pa->code[index]);
1987                 u32 data = action & 0x0000ffff;
1988                 u32 regno = (action & 0x0fff0000) >> 16;
1989
1990                 if (!action)
1991                         break;
1992
1993                 switch(action & 0xf0000000) {
1994                 case PHY_READ:
1995                         predata = rtl_readphy(tp, regno);
1996                         count++;
1997                         index++;
1998                         break;
1999                 case PHY_DATA_OR:
2000                         predata |= data;
2001                         index++;
2002                         break;
2003                 case PHY_DATA_AND:
2004                         predata &= data;
2005                         index++;
2006                         break;
2007                 case PHY_BJMPN:
2008                         index -= regno;
2009                         break;
2010                 case PHY_READ_EFUSE:
2011                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2012                         index++;
2013                         break;
2014                 case PHY_CLEAR_READCOUNT:
2015                         count = 0;
2016                         index++;
2017                         break;
2018                 case PHY_WRITE:
2019                         rtl_writephy(tp, regno, data);
2020                         index++;
2021                         break;
2022                 case PHY_READCOUNT_EQ_SKIP:
2023                         index += (count == data) ? 2 : 1;
2024                         break;
2025                 case PHY_COMP_EQ_SKIPN:
2026                         if (predata == data)
2027                                 index += regno;
2028                         index++;
2029                         break;
2030                 case PHY_COMP_NEQ_SKIPN:
2031                         if (predata != data)
2032                                 index += regno;
2033                         index++;
2034                         break;
2035                 case PHY_WRITE_PREVIOUS:
2036                         rtl_writephy(tp, regno, predata);
2037                         index++;
2038                         break;
2039                 case PHY_SKIPN:
2040                         index += regno + 1;
2041                         break;
2042                 case PHY_DELAY_MS:
2043                         mdelay(data);
2044                         index++;
2045                         break;
2046
2047                 case PHY_READ_MAC_BYTE:
2048                 case PHY_WRITE_MAC_BYTE:
2049                 case PHY_WRITE_ERI_WORD:
2050                 default:
2051                         BUG();
2052                 }
2053         }
2054 }
2055
2056 static void rtl_release_firmware(struct rtl8169_private *tp)
2057 {
2058         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2059                 release_firmware(tp->rtl_fw->fw);
2060                 kfree(tp->rtl_fw);
2061         }
2062         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2063 }
2064
2065 static void rtl_apply_firmware(struct rtl8169_private *tp)
2066 {
2067         struct rtl_fw *rtl_fw = tp->rtl_fw;
2068
2069         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2070         if (!IS_ERR_OR_NULL(rtl_fw))
2071                 rtl_phy_write_fw(tp, rtl_fw);
2072 }
2073
2074 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2075 {
2076         if (rtl_readphy(tp, reg) != val)
2077                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2078         else
2079                 rtl_apply_firmware(tp);
2080 }
2081
2082 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2083 {
2084         static const struct phy_reg phy_reg_init[] = {
2085                 { 0x1f, 0x0001 },
2086                 { 0x06, 0x006e },
2087                 { 0x08, 0x0708 },
2088                 { 0x15, 0x4000 },
2089                 { 0x18, 0x65c7 },
2090
2091                 { 0x1f, 0x0001 },
2092                 { 0x03, 0x00a1 },
2093                 { 0x02, 0x0008 },
2094                 { 0x01, 0x0120 },
2095                 { 0x00, 0x1000 },
2096                 { 0x04, 0x0800 },
2097                 { 0x04, 0x0000 },
2098
2099                 { 0x03, 0xff41 },
2100                 { 0x02, 0xdf60 },
2101                 { 0x01, 0x0140 },
2102                 { 0x00, 0x0077 },
2103                 { 0x04, 0x7800 },
2104                 { 0x04, 0x7000 },
2105
2106                 { 0x03, 0x802f },
2107                 { 0x02, 0x4f02 },
2108                 { 0x01, 0x0409 },
2109                 { 0x00, 0xf0f9 },
2110                 { 0x04, 0x9800 },
2111                 { 0x04, 0x9000 },
2112
2113                 { 0x03, 0xdf01 },
2114                 { 0x02, 0xdf20 },
2115                 { 0x01, 0xff95 },
2116                 { 0x00, 0xba00 },
2117                 { 0x04, 0xa800 },
2118                 { 0x04, 0xa000 },
2119
2120                 { 0x03, 0xff41 },
2121                 { 0x02, 0xdf20 },
2122                 { 0x01, 0x0140 },
2123                 { 0x00, 0x00bb },
2124                 { 0x04, 0xb800 },
2125                 { 0x04, 0xb000 },
2126
2127                 { 0x03, 0xdf41 },
2128                 { 0x02, 0xdc60 },
2129                 { 0x01, 0x6340 },
2130                 { 0x00, 0x007d },
2131                 { 0x04, 0xd800 },
2132                 { 0x04, 0xd000 },
2133
2134                 { 0x03, 0xdf01 },
2135                 { 0x02, 0xdf20 },
2136                 { 0x01, 0x100a },
2137                 { 0x00, 0xa0ff },
2138                 { 0x04, 0xf800 },
2139                 { 0x04, 0xf000 },
2140
2141                 { 0x1f, 0x0000 },
2142                 { 0x0b, 0x0000 },
2143                 { 0x00, 0x9200 }
2144         };
2145
2146         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2147 }
2148
2149 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2150 {
2151         static const struct phy_reg phy_reg_init[] = {
2152                 { 0x1f, 0x0002 },
2153                 { 0x01, 0x90d0 },
2154                 { 0x1f, 0x0000 }
2155         };
2156
2157         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2158 }
2159
2160 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2161 {
2162         struct pci_dev *pdev = tp->pci_dev;
2163         u16 vendor_id, device_id;
2164
2165         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2166         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2167
2168         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2169                 return;
2170
2171         rtl_writephy(tp, 0x1f, 0x0001);
2172         rtl_writephy(tp, 0x10, 0xf01b);
2173         rtl_writephy(tp, 0x1f, 0x0000);
2174 }
2175
2176 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2177 {
2178         static const struct phy_reg phy_reg_init[] = {
2179                 { 0x1f, 0x0001 },
2180                 { 0x04, 0x0000 },
2181                 { 0x03, 0x00a1 },
2182                 { 0x02, 0x0008 },
2183                 { 0x01, 0x0120 },
2184                 { 0x00, 0x1000 },
2185                 { 0x04, 0x0800 },
2186                 { 0x04, 0x9000 },
2187                 { 0x03, 0x802f },
2188                 { 0x02, 0x4f02 },
2189                 { 0x01, 0x0409 },
2190                 { 0x00, 0xf099 },
2191                 { 0x04, 0x9800 },
2192                 { 0x04, 0xa000 },
2193                 { 0x03, 0xdf01 },
2194                 { 0x02, 0xdf20 },
2195                 { 0x01, 0xff95 },
2196                 { 0x00, 0xba00 },
2197                 { 0x04, 0xa800 },
2198                 { 0x04, 0xf000 },
2199                 { 0x03, 0xdf01 },
2200                 { 0x02, 0xdf20 },
2201                 { 0x01, 0x101a },
2202                 { 0x00, 0xa0ff },
2203                 { 0x04, 0xf800 },
2204                 { 0x04, 0x0000 },
2205                 { 0x1f, 0x0000 },
2206
2207                 { 0x1f, 0x0001 },
2208                 { 0x10, 0xf41b },
2209                 { 0x14, 0xfb54 },
2210                 { 0x18, 0xf5c7 },
2211                 { 0x1f, 0x0000 },
2212
2213                 { 0x1f, 0x0001 },
2214                 { 0x17, 0x0cc0 },
2215                 { 0x1f, 0x0000 }
2216         };
2217
2218         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2219
2220         rtl8169scd_hw_phy_config_quirk(tp);
2221 }
2222
2223 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2224 {
2225         static const struct phy_reg phy_reg_init[] = {
2226                 { 0x1f, 0x0001 },
2227                 { 0x04, 0x0000 },
2228                 { 0x03, 0x00a1 },
2229                 { 0x02, 0x0008 },
2230                 { 0x01, 0x0120 },
2231                 { 0x00, 0x1000 },
2232                 { 0x04, 0x0800 },
2233                 { 0x04, 0x9000 },
2234                 { 0x03, 0x802f },
2235                 { 0x02, 0x4f02 },
2236                 { 0x01, 0x0409 },
2237                 { 0x00, 0xf099 },
2238                 { 0x04, 0x9800 },
2239                 { 0x04, 0xa000 },
2240                 { 0x03, 0xdf01 },
2241                 { 0x02, 0xdf20 },
2242                 { 0x01, 0xff95 },
2243                 { 0x00, 0xba00 },
2244                 { 0x04, 0xa800 },
2245                 { 0x04, 0xf000 },
2246                 { 0x03, 0xdf01 },
2247                 { 0x02, 0xdf20 },
2248                 { 0x01, 0x101a },
2249                 { 0x00, 0xa0ff },
2250                 { 0x04, 0xf800 },
2251                 { 0x04, 0x0000 },
2252                 { 0x1f, 0x0000 },
2253
2254                 { 0x1f, 0x0001 },
2255                 { 0x0b, 0x8480 },
2256                 { 0x1f, 0x0000 },
2257
2258                 { 0x1f, 0x0001 },
2259                 { 0x18, 0x67c7 },
2260                 { 0x04, 0x2000 },
2261                 { 0x03, 0x002f },
2262                 { 0x02, 0x4360 },
2263                 { 0x01, 0x0109 },
2264                 { 0x00, 0x3022 },
2265                 { 0x04, 0x2800 },
2266                 { 0x1f, 0x0000 },
2267
2268                 { 0x1f, 0x0001 },
2269                 { 0x17, 0x0cc0 },
2270                 { 0x1f, 0x0000 }
2271         };
2272
2273         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2274 }
2275
2276 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2277 {
2278         static const struct phy_reg phy_reg_init[] = {
2279                 { 0x10, 0xf41b },
2280                 { 0x1f, 0x0000 }
2281         };
2282
2283         rtl_writephy(tp, 0x1f, 0x0001);
2284         rtl_patchphy(tp, 0x16, 1 << 0);
2285
2286         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2287 }
2288
2289 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2290 {
2291         static const struct phy_reg phy_reg_init[] = {
2292                 { 0x1f, 0x0001 },
2293                 { 0x10, 0xf41b },
2294                 { 0x1f, 0x0000 }
2295         };
2296
2297         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2298 }
2299
2300 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2301 {
2302         static const struct phy_reg phy_reg_init[] = {
2303                 { 0x1f, 0x0000 },
2304                 { 0x1d, 0x0f00 },
2305                 { 0x1f, 0x0002 },
2306                 { 0x0c, 0x1ec8 },
2307                 { 0x1f, 0x0000 }
2308         };
2309
2310         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2311 }
2312
2313 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2314 {
2315         static const struct phy_reg phy_reg_init[] = {
2316                 { 0x1f, 0x0001 },
2317                 { 0x1d, 0x3d98 },
2318                 { 0x1f, 0x0000 }
2319         };
2320
2321         rtl_writephy(tp, 0x1f, 0x0000);
2322         rtl_patchphy(tp, 0x14, 1 << 5);
2323         rtl_patchphy(tp, 0x0d, 1 << 5);
2324
2325         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2326 }
2327
2328 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2329 {
2330         static const struct phy_reg phy_reg_init[] = {
2331                 { 0x1f, 0x0001 },
2332                 { 0x12, 0x2300 },
2333                 { 0x1f, 0x0002 },
2334                 { 0x00, 0x88d4 },
2335                 { 0x01, 0x82b1 },
2336                 { 0x03, 0x7002 },
2337                 { 0x08, 0x9e30 },
2338                 { 0x09, 0x01f0 },
2339                 { 0x0a, 0x5500 },
2340                 { 0x0c, 0x00c8 },
2341                 { 0x1f, 0x0003 },
2342                 { 0x12, 0xc096 },
2343                 { 0x16, 0x000a },
2344                 { 0x1f, 0x0000 },
2345                 { 0x1f, 0x0000 },
2346                 { 0x09, 0x2000 },
2347                 { 0x09, 0x0000 }
2348         };
2349
2350         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2351
2352         rtl_patchphy(tp, 0x14, 1 << 5);
2353         rtl_patchphy(tp, 0x0d, 1 << 5);
2354         rtl_writephy(tp, 0x1f, 0x0000);
2355 }
2356
2357 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2358 {
2359         static const struct phy_reg phy_reg_init[] = {
2360                 { 0x1f, 0x0001 },
2361                 { 0x12, 0x2300 },
2362                 { 0x03, 0x802f },
2363                 { 0x02, 0x4f02 },
2364                 { 0x01, 0x0409 },
2365                 { 0x00, 0xf099 },
2366                 { 0x04, 0x9800 },
2367                 { 0x04, 0x9000 },
2368                 { 0x1d, 0x3d98 },
2369                 { 0x1f, 0x0002 },
2370                 { 0x0c, 0x7eb8 },
2371                 { 0x06, 0x0761 },
2372                 { 0x1f, 0x0003 },
2373                 { 0x16, 0x0f0a },
2374                 { 0x1f, 0x0000 }
2375         };
2376
2377         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2378
2379         rtl_patchphy(tp, 0x16, 1 << 0);
2380         rtl_patchphy(tp, 0x14, 1 << 5);
2381         rtl_patchphy(tp, 0x0d, 1 << 5);
2382         rtl_writephy(tp, 0x1f, 0x0000);
2383 }
2384
2385 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2386 {
2387         static const struct phy_reg phy_reg_init[] = {
2388                 { 0x1f, 0x0001 },
2389                 { 0x12, 0x2300 },
2390                 { 0x1d, 0x3d98 },
2391                 { 0x1f, 0x0002 },
2392                 { 0x0c, 0x7eb8 },
2393                 { 0x06, 0x5461 },
2394                 { 0x1f, 0x0003 },
2395                 { 0x16, 0x0f0a },
2396                 { 0x1f, 0x0000 }
2397         };
2398
2399         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2400
2401         rtl_patchphy(tp, 0x16, 1 << 0);
2402         rtl_patchphy(tp, 0x14, 1 << 5);
2403         rtl_patchphy(tp, 0x0d, 1 << 5);
2404         rtl_writephy(tp, 0x1f, 0x0000);
2405 }
2406
2407 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2408 {
2409         rtl8168c_3_hw_phy_config(tp);
2410 }
2411
2412 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2413 {
2414         static const struct phy_reg phy_reg_init_0[] = {
2415                 /* Channel Estimation */
2416                 { 0x1f, 0x0001 },
2417                 { 0x06, 0x4064 },
2418                 { 0x07, 0x2863 },
2419                 { 0x08, 0x059c },
2420                 { 0x09, 0x26b4 },
2421                 { 0x0a, 0x6a19 },
2422                 { 0x0b, 0xdcc8 },
2423                 { 0x10, 0xf06d },
2424                 { 0x14, 0x7f68 },
2425                 { 0x18, 0x7fd9 },
2426                 { 0x1c, 0xf0ff },
2427                 { 0x1d, 0x3d9c },
2428                 { 0x1f, 0x0003 },
2429                 { 0x12, 0xf49f },
2430                 { 0x13, 0x070b },
2431                 { 0x1a, 0x05ad },
2432                 { 0x14, 0x94c0 },
2433
2434                 /*
2435                  * Tx Error Issue
2436                  * Enhance line driver power
2437                  */
2438                 { 0x1f, 0x0002 },
2439                 { 0x06, 0x5561 },
2440                 { 0x1f, 0x0005 },
2441                 { 0x05, 0x8332 },
2442                 { 0x06, 0x5561 },
2443
2444                 /*
2445                  * Can not link to 1Gbps with bad cable
2446                  * Decrease SNR threshold form 21.07dB to 19.04dB
2447                  */
2448                 { 0x1f, 0x0001 },
2449                 { 0x17, 0x0cc0 },
2450
2451                 { 0x1f, 0x0000 },
2452                 { 0x0d, 0xf880 }
2453         };
2454         void __iomem *ioaddr = tp->mmio_addr;
2455
2456         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2457
2458         /*
2459          * Rx Error Issue
2460          * Fine Tune Switching regulator parameter
2461          */
2462         rtl_writephy(tp, 0x1f, 0x0002);
2463         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2464         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2465
2466         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2467                 static const struct phy_reg phy_reg_init[] = {
2468                         { 0x1f, 0x0002 },
2469                         { 0x05, 0x669a },
2470                         { 0x1f, 0x0005 },
2471                         { 0x05, 0x8330 },
2472                         { 0x06, 0x669a },
2473                         { 0x1f, 0x0002 }
2474                 };
2475                 int val;
2476
2477                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2478
2479                 val = rtl_readphy(tp, 0x0d);
2480
2481                 if ((val & 0x00ff) != 0x006c) {
2482                         static const u32 set[] = {
2483                                 0x0065, 0x0066, 0x0067, 0x0068,
2484                                 0x0069, 0x006a, 0x006b, 0x006c
2485                         };
2486                         int i;
2487
2488                         rtl_writephy(tp, 0x1f, 0x0002);
2489
2490                         val &= 0xff00;
2491                         for (i = 0; i < ARRAY_SIZE(set); i++)
2492                                 rtl_writephy(tp, 0x0d, val | set[i]);
2493                 }
2494         } else {
2495                 static const struct phy_reg phy_reg_init[] = {
2496                         { 0x1f, 0x0002 },
2497                         { 0x05, 0x6662 },
2498                         { 0x1f, 0x0005 },
2499                         { 0x05, 0x8330 },
2500                         { 0x06, 0x6662 }
2501                 };
2502
2503                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2504         }
2505
2506         /* RSET couple improve */
2507         rtl_writephy(tp, 0x1f, 0x0002);
2508         rtl_patchphy(tp, 0x0d, 0x0300);
2509         rtl_patchphy(tp, 0x0f, 0x0010);
2510
2511         /* Fine tune PLL performance */
2512         rtl_writephy(tp, 0x1f, 0x0002);
2513         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2514         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2515
2516         rtl_writephy(tp, 0x1f, 0x0005);
2517         rtl_writephy(tp, 0x05, 0x001b);
2518
2519         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2520
2521         rtl_writephy(tp, 0x1f, 0x0000);
2522 }
2523
2524 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2525 {
2526         static const struct phy_reg phy_reg_init_0[] = {
2527                 /* Channel Estimation */
2528                 { 0x1f, 0x0001 },
2529                 { 0x06, 0x4064 },
2530                 { 0x07, 0x2863 },
2531                 { 0x08, 0x059c },
2532                 { 0x09, 0x26b4 },
2533                 { 0x0a, 0x6a19 },
2534                 { 0x0b, 0xdcc8 },
2535                 { 0x10, 0xf06d },
2536                 { 0x14, 0x7f68 },
2537                 { 0x18, 0x7fd9 },
2538                 { 0x1c, 0xf0ff },
2539                 { 0x1d, 0x3d9c },
2540                 { 0x1f, 0x0003 },
2541                 { 0x12, 0xf49f },
2542                 { 0x13, 0x070b },
2543                 { 0x1a, 0x05ad },
2544                 { 0x14, 0x94c0 },
2545
2546                 /*
2547                  * Tx Error Issue
2548                  * Enhance line driver power
2549                  */
2550                 { 0x1f, 0x0002 },
2551                 { 0x06, 0x5561 },
2552                 { 0x1f, 0x0005 },
2553                 { 0x05, 0x8332 },
2554                 { 0x06, 0x5561 },
2555
2556                 /*
2557                  * Can not link to 1Gbps with bad cable
2558                  * Decrease SNR threshold form 21.07dB to 19.04dB
2559                  */
2560                 { 0x1f, 0x0001 },
2561                 { 0x17, 0x0cc0 },
2562
2563                 { 0x1f, 0x0000 },
2564                 { 0x0d, 0xf880 }
2565         };
2566         void __iomem *ioaddr = tp->mmio_addr;
2567
2568         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2569
2570         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2571                 static const struct phy_reg phy_reg_init[] = {
2572                         { 0x1f, 0x0002 },
2573                         { 0x05, 0x669a },
2574                         { 0x1f, 0x0005 },
2575                         { 0x05, 0x8330 },
2576                         { 0x06, 0x669a },
2577
2578                         { 0x1f, 0x0002 }
2579                 };
2580                 int val;
2581
2582                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2583
2584                 val = rtl_readphy(tp, 0x0d);
2585                 if ((val & 0x00ff) != 0x006c) {
2586                         static const u32 set[] = {
2587                                 0x0065, 0x0066, 0x0067, 0x0068,
2588                                 0x0069, 0x006a, 0x006b, 0x006c
2589                         };
2590                         int i;
2591
2592                         rtl_writephy(tp, 0x1f, 0x0002);
2593
2594                         val &= 0xff00;
2595                         for (i = 0; i < ARRAY_SIZE(set); i++)
2596                                 rtl_writephy(tp, 0x0d, val | set[i]);
2597                 }
2598         } else {
2599                 static const struct phy_reg phy_reg_init[] = {
2600                         { 0x1f, 0x0002 },
2601                         { 0x05, 0x2642 },
2602                         { 0x1f, 0x0005 },
2603                         { 0x05, 0x8330 },
2604                         { 0x06, 0x2642 }
2605                 };
2606
2607                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2608         }
2609
2610         /* Fine tune PLL performance */
2611         rtl_writephy(tp, 0x1f, 0x0002);
2612         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2613         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2614
2615         /* Switching regulator Slew rate */
2616         rtl_writephy(tp, 0x1f, 0x0002);
2617         rtl_patchphy(tp, 0x0f, 0x0017);
2618
2619         rtl_writephy(tp, 0x1f, 0x0005);
2620         rtl_writephy(tp, 0x05, 0x001b);
2621
2622         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2623
2624         rtl_writephy(tp, 0x1f, 0x0000);
2625 }
2626
2627 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2628 {
2629         static const struct phy_reg phy_reg_init[] = {
2630                 { 0x1f, 0x0002 },
2631                 { 0x10, 0x0008 },
2632                 { 0x0d, 0x006c },
2633
2634                 { 0x1f, 0x0000 },
2635                 { 0x0d, 0xf880 },
2636
2637                 { 0x1f, 0x0001 },
2638                 { 0x17, 0x0cc0 },
2639
2640                 { 0x1f, 0x0001 },
2641                 { 0x0b, 0xa4d8 },
2642                 { 0x09, 0x281c },
2643                 { 0x07, 0x2883 },
2644                 { 0x0a, 0x6b35 },
2645                 { 0x1d, 0x3da4 },
2646                 { 0x1c, 0xeffd },
2647                 { 0x14, 0x7f52 },
2648                 { 0x18, 0x7fc6 },
2649                 { 0x08, 0x0601 },
2650                 { 0x06, 0x4063 },
2651                 { 0x10, 0xf074 },
2652                 { 0x1f, 0x0003 },
2653                 { 0x13, 0x0789 },
2654                 { 0x12, 0xf4bd },
2655                 { 0x1a, 0x04fd },
2656                 { 0x14, 0x84b0 },
2657                 { 0x1f, 0x0000 },
2658                 { 0x00, 0x9200 },
2659
2660                 { 0x1f, 0x0005 },
2661                 { 0x01, 0x0340 },
2662                 { 0x1f, 0x0001 },
2663                 { 0x04, 0x4000 },
2664                 { 0x03, 0x1d21 },
2665                 { 0x02, 0x0c32 },
2666                 { 0x01, 0x0200 },
2667                 { 0x00, 0x5554 },
2668                 { 0x04, 0x4800 },
2669                 { 0x04, 0x4000 },
2670                 { 0x04, 0xf000 },
2671                 { 0x03, 0xdf01 },
2672                 { 0x02, 0xdf20 },
2673                 { 0x01, 0x101a },
2674                 { 0x00, 0xa0ff },
2675                 { 0x04, 0xf800 },
2676                 { 0x04, 0xf000 },
2677                 { 0x1f, 0x0000 },
2678
2679                 { 0x1f, 0x0007 },
2680                 { 0x1e, 0x0023 },
2681                 { 0x16, 0x0000 },
2682                 { 0x1f, 0x0000 }
2683         };
2684
2685         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2686 }
2687
2688 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2689 {
2690         static const struct phy_reg phy_reg_init[] = {
2691                 { 0x1f, 0x0001 },
2692                 { 0x17, 0x0cc0 },
2693
2694                 { 0x1f, 0x0007 },
2695                 { 0x1e, 0x002d },
2696                 { 0x18, 0x0040 },
2697                 { 0x1f, 0x0000 }
2698         };
2699
2700         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2701         rtl_patchphy(tp, 0x0d, 1 << 5);
2702 }
2703
2704 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2705 {
2706         static const struct phy_reg phy_reg_init[] = {
2707                 /* Enable Delay cap */
2708                 { 0x1f, 0x0005 },
2709                 { 0x05, 0x8b80 },
2710                 { 0x06, 0xc896 },
2711                 { 0x1f, 0x0000 },
2712
2713                 /* Channel estimation fine tune */
2714                 { 0x1f, 0x0001 },
2715                 { 0x0b, 0x6c20 },
2716                 { 0x07, 0x2872 },
2717                 { 0x1c, 0xefff },
2718                 { 0x1f, 0x0003 },
2719                 { 0x14, 0x6420 },
2720                 { 0x1f, 0x0000 },
2721
2722                 /* Update PFM & 10M TX idle timer */
2723                 { 0x1f, 0x0007 },
2724                 { 0x1e, 0x002f },
2725                 { 0x15, 0x1919 },
2726                 { 0x1f, 0x0000 },
2727
2728                 { 0x1f, 0x0007 },
2729                 { 0x1e, 0x00ac },
2730                 { 0x18, 0x0006 },
2731                 { 0x1f, 0x0000 }
2732         };
2733
2734         rtl_apply_firmware(tp);
2735
2736         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2737
2738         /* DCO enable for 10M IDLE Power */
2739         rtl_writephy(tp, 0x1f, 0x0007);
2740         rtl_writephy(tp, 0x1e, 0x0023);
2741         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2742         rtl_writephy(tp, 0x1f, 0x0000);
2743
2744         /* For impedance matching */
2745         rtl_writephy(tp, 0x1f, 0x0002);
2746         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2747         rtl_writephy(tp, 0x1f, 0x0000);
2748
2749         /* PHY auto speed down */
2750         rtl_writephy(tp, 0x1f, 0x0007);
2751         rtl_writephy(tp, 0x1e, 0x002d);
2752         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2753         rtl_writephy(tp, 0x1f, 0x0000);
2754         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2755
2756         rtl_writephy(tp, 0x1f, 0x0005);
2757         rtl_writephy(tp, 0x05, 0x8b86);
2758         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2759         rtl_writephy(tp, 0x1f, 0x0000);
2760
2761         rtl_writephy(tp, 0x1f, 0x0005);
2762         rtl_writephy(tp, 0x05, 0x8b85);
2763         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2764         rtl_writephy(tp, 0x1f, 0x0007);
2765         rtl_writephy(tp, 0x1e, 0x0020);
2766         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2767         rtl_writephy(tp, 0x1f, 0x0006);
2768         rtl_writephy(tp, 0x00, 0x5a00);
2769         rtl_writephy(tp, 0x1f, 0x0000);
2770         rtl_writephy(tp, 0x0d, 0x0007);
2771         rtl_writephy(tp, 0x0e, 0x003c);
2772         rtl_writephy(tp, 0x0d, 0x4007);
2773         rtl_writephy(tp, 0x0e, 0x0000);
2774         rtl_writephy(tp, 0x0d, 0x0000);
2775 }
2776
2777 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2778 {
2779         static const struct phy_reg phy_reg_init[] = {
2780                 /* Enable Delay cap */
2781                 { 0x1f, 0x0004 },
2782                 { 0x1f, 0x0007 },
2783                 { 0x1e, 0x00ac },
2784                 { 0x18, 0x0006 },
2785                 { 0x1f, 0x0002 },
2786                 { 0x1f, 0x0000 },
2787                 { 0x1f, 0x0000 },
2788
2789                 /* Channel estimation fine tune */
2790                 { 0x1f, 0x0003 },
2791                 { 0x09, 0xa20f },
2792                 { 0x1f, 0x0000 },
2793                 { 0x1f, 0x0000 },
2794
2795                 /* Green Setting */
2796                 { 0x1f, 0x0005 },
2797                 { 0x05, 0x8b5b },
2798                 { 0x06, 0x9222 },
2799                 { 0x05, 0x8b6d },
2800                 { 0x06, 0x8000 },
2801                 { 0x05, 0x8b76 },
2802                 { 0x06, 0x8000 },
2803                 { 0x1f, 0x0000 }
2804         };
2805
2806         rtl_apply_firmware(tp);
2807
2808         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2809
2810         /* For 4-corner performance improve */
2811         rtl_writephy(tp, 0x1f, 0x0005);
2812         rtl_writephy(tp, 0x05, 0x8b80);
2813         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2814         rtl_writephy(tp, 0x1f, 0x0000);
2815
2816         /* PHY auto speed down */
2817         rtl_writephy(tp, 0x1f, 0x0004);
2818         rtl_writephy(tp, 0x1f, 0x0007);
2819         rtl_writephy(tp, 0x1e, 0x002d);
2820         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2821         rtl_writephy(tp, 0x1f, 0x0002);
2822         rtl_writephy(tp, 0x1f, 0x0000);
2823         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2824
2825         /* improve 10M EEE waveform */
2826         rtl_writephy(tp, 0x1f, 0x0005);
2827         rtl_writephy(tp, 0x05, 0x8b86);
2828         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2829         rtl_writephy(tp, 0x1f, 0x0000);
2830
2831         /* Improve 2-pair detection performance */
2832         rtl_writephy(tp, 0x1f, 0x0005);
2833         rtl_writephy(tp, 0x05, 0x8b85);
2834         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2835         rtl_writephy(tp, 0x1f, 0x0000);
2836
2837         /* EEE setting */
2838         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2839                      ERIAR_EXGMAC);
2840         rtl_writephy(tp, 0x1f, 0x0005);
2841         rtl_writephy(tp, 0x05, 0x8b85);
2842         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2843         rtl_writephy(tp, 0x1f, 0x0004);
2844         rtl_writephy(tp, 0x1f, 0x0007);
2845         rtl_writephy(tp, 0x1e, 0x0020);
2846         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2847         rtl_writephy(tp, 0x1f, 0x0002);
2848         rtl_writephy(tp, 0x1f, 0x0000);
2849         rtl_writephy(tp, 0x0d, 0x0007);
2850         rtl_writephy(tp, 0x0e, 0x003c);
2851         rtl_writephy(tp, 0x0d, 0x4007);
2852         rtl_writephy(tp, 0x0e, 0x0000);
2853         rtl_writephy(tp, 0x0d, 0x0000);
2854
2855         /* Green feature */
2856         rtl_writephy(tp, 0x1f, 0x0003);
2857         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2858         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2859         rtl_writephy(tp, 0x1f, 0x0000);
2860 }
2861
2862 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2863 {
2864         static const struct phy_reg phy_reg_init[] = {
2865                 { 0x1f, 0x0003 },
2866                 { 0x08, 0x441d },
2867                 { 0x01, 0x9100 },
2868                 { 0x1f, 0x0000 }
2869         };
2870
2871         rtl_writephy(tp, 0x1f, 0x0000);
2872         rtl_patchphy(tp, 0x11, 1 << 12);
2873         rtl_patchphy(tp, 0x19, 1 << 13);
2874         rtl_patchphy(tp, 0x10, 1 << 15);
2875
2876         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2877 }
2878
2879 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2880 {
2881         static const struct phy_reg phy_reg_init[] = {
2882                 { 0x1f, 0x0005 },
2883                 { 0x1a, 0x0000 },
2884                 { 0x1f, 0x0000 },
2885
2886                 { 0x1f, 0x0004 },
2887                 { 0x1c, 0x0000 },
2888                 { 0x1f, 0x0000 },
2889
2890                 { 0x1f, 0x0001 },
2891                 { 0x15, 0x7701 },
2892                 { 0x1f, 0x0000 }
2893         };
2894
2895         /* Disable ALDPS before ram code */
2896         rtl_writephy(tp, 0x1f, 0x0000);
2897         rtl_writephy(tp, 0x18, 0x0310);
2898         msleep(100);
2899
2900         rtl_apply_firmware(tp);
2901
2902         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2903 }
2904
2905 static void rtl_hw_phy_config(struct net_device *dev)
2906 {
2907         struct rtl8169_private *tp = netdev_priv(dev);
2908
2909         rtl8169_print_mac_version(tp);
2910
2911         switch (tp->mac_version) {
2912         case RTL_GIGA_MAC_VER_01:
2913                 break;
2914         case RTL_GIGA_MAC_VER_02:
2915         case RTL_GIGA_MAC_VER_03:
2916                 rtl8169s_hw_phy_config(tp);
2917                 break;
2918         case RTL_GIGA_MAC_VER_04:
2919                 rtl8169sb_hw_phy_config(tp);
2920                 break;
2921         case RTL_GIGA_MAC_VER_05:
2922                 rtl8169scd_hw_phy_config(tp);
2923                 break;
2924         case RTL_GIGA_MAC_VER_06:
2925                 rtl8169sce_hw_phy_config(tp);
2926                 break;
2927         case RTL_GIGA_MAC_VER_07:
2928         case RTL_GIGA_MAC_VER_08:
2929         case RTL_GIGA_MAC_VER_09:
2930                 rtl8102e_hw_phy_config(tp);
2931                 break;
2932         case RTL_GIGA_MAC_VER_11:
2933                 rtl8168bb_hw_phy_config(tp);
2934                 break;
2935         case RTL_GIGA_MAC_VER_12:
2936                 rtl8168bef_hw_phy_config(tp);
2937                 break;
2938         case RTL_GIGA_MAC_VER_17:
2939                 rtl8168bef_hw_phy_config(tp);
2940                 break;
2941         case RTL_GIGA_MAC_VER_18:
2942                 rtl8168cp_1_hw_phy_config(tp);
2943                 break;
2944         case RTL_GIGA_MAC_VER_19:
2945                 rtl8168c_1_hw_phy_config(tp);
2946                 break;
2947         case RTL_GIGA_MAC_VER_20:
2948                 rtl8168c_2_hw_phy_config(tp);
2949                 break;
2950         case RTL_GIGA_MAC_VER_21:
2951                 rtl8168c_3_hw_phy_config(tp);
2952                 break;
2953         case RTL_GIGA_MAC_VER_22:
2954                 rtl8168c_4_hw_phy_config(tp);
2955                 break;
2956         case RTL_GIGA_MAC_VER_23:
2957         case RTL_GIGA_MAC_VER_24:
2958                 rtl8168cp_2_hw_phy_config(tp);
2959                 break;
2960         case RTL_GIGA_MAC_VER_25:
2961                 rtl8168d_1_hw_phy_config(tp);
2962                 break;
2963         case RTL_GIGA_MAC_VER_26:
2964                 rtl8168d_2_hw_phy_config(tp);
2965                 break;
2966         case RTL_GIGA_MAC_VER_27:
2967                 rtl8168d_3_hw_phy_config(tp);
2968                 break;
2969         case RTL_GIGA_MAC_VER_28:
2970                 rtl8168d_4_hw_phy_config(tp);
2971                 break;
2972         case RTL_GIGA_MAC_VER_29:
2973         case RTL_GIGA_MAC_VER_30:
2974                 rtl8105e_hw_phy_config(tp);
2975                 break;
2976         case RTL_GIGA_MAC_VER_31:
2977                 /* None. */
2978                 break;
2979         case RTL_GIGA_MAC_VER_32:
2980         case RTL_GIGA_MAC_VER_33:
2981                 rtl8168e_1_hw_phy_config(tp);
2982                 break;
2983         case RTL_GIGA_MAC_VER_34:
2984                 rtl8168e_2_hw_phy_config(tp);
2985                 break;
2986
2987         default:
2988                 break;
2989         }
2990 }
2991
2992 static void rtl8169_phy_timer(unsigned long __opaque)
2993 {
2994         struct net_device *dev = (struct net_device *)__opaque;
2995         struct rtl8169_private *tp = netdev_priv(dev);
2996         struct timer_list *timer = &tp->timer;
2997         void __iomem *ioaddr = tp->mmio_addr;
2998         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2999
3000         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3001
3002         spin_lock_irq(&tp->lock);
3003
3004         if (tp->phy_reset_pending(tp)) {
3005                 /*
3006                  * A busy loop could burn quite a few cycles on nowadays CPU.
3007                  * Let's delay the execution of the timer for a few ticks.
3008                  */
3009                 timeout = HZ/10;
3010                 goto out_mod_timer;
3011         }
3012
3013         if (tp->link_ok(ioaddr))
3014                 goto out_unlock;
3015
3016         netif_warn(tp, link, dev, "PHY reset until link up\n");
3017
3018         tp->phy_reset_enable(tp);
3019
3020 out_mod_timer:
3021         mod_timer(timer, jiffies + timeout);
3022 out_unlock:
3023         spin_unlock_irq(&tp->lock);
3024 }
3025
3026 #ifdef CONFIG_NET_POLL_CONTROLLER
3027 /*
3028  * Polling 'interrupt' - used by things like netconsole to send skbs
3029  * without having to re-enable interrupts. It's not called while
3030  * the interrupt routine is executing.
3031  */
3032 static void rtl8169_netpoll(struct net_device *dev)
3033 {
3034         struct rtl8169_private *tp = netdev_priv(dev);
3035         struct pci_dev *pdev = tp->pci_dev;
3036
3037         disable_irq(pdev->irq);
3038         rtl8169_interrupt(pdev->irq, dev);
3039         enable_irq(pdev->irq);
3040 }
3041 #endif
3042
3043 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3044                                   void __iomem *ioaddr)
3045 {
3046         iounmap(ioaddr);
3047         pci_release_regions(pdev);
3048         pci_clear_mwi(pdev);
3049         pci_disable_device(pdev);
3050         free_netdev(dev);
3051 }
3052
3053 static void rtl8169_phy_reset(struct net_device *dev,
3054                               struct rtl8169_private *tp)
3055 {
3056         unsigned int i;
3057
3058         tp->phy_reset_enable(tp);
3059         for (i = 0; i < 100; i++) {
3060                 if (!tp->phy_reset_pending(tp))
3061                         return;
3062                 msleep(1);
3063         }
3064         netif_err(tp, link, dev, "PHY reset failed\n");
3065 }
3066
3067 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3068 {
3069         void __iomem *ioaddr = tp->mmio_addr;
3070
3071         rtl_hw_phy_config(dev);
3072
3073         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3074                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3075                 RTL_W8(0x82, 0x01);
3076         }
3077
3078         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3079
3080         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3081                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3082
3083         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3084                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3085                 RTL_W8(0x82, 0x01);
3086                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3087                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3088         }
3089
3090         rtl8169_phy_reset(dev, tp);
3091
3092         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3093                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3094                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3095                           (tp->mii.supports_gmii ?
3096                            ADVERTISED_1000baseT_Half |
3097                            ADVERTISED_1000baseT_Full : 0));
3098
3099         if (RTL_R8(PHYstatus) & TBI_Enable)
3100                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3101 }
3102
3103 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3104 {
3105         void __iomem *ioaddr = tp->mmio_addr;
3106         u32 high;
3107         u32 low;
3108
3109         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3110         high = addr[4] | (addr[5] << 8);
3111
3112         spin_lock_irq(&tp->lock);
3113
3114         RTL_W8(Cfg9346, Cfg9346_Unlock);
3115
3116         RTL_W32(MAC4, high);
3117         RTL_R32(MAC4);
3118
3119         RTL_W32(MAC0, low);
3120         RTL_R32(MAC0);
3121
3122         RTL_W8(Cfg9346, Cfg9346_Lock);
3123
3124         spin_unlock_irq(&tp->lock);
3125 }
3126
3127 static int rtl_set_mac_address(struct net_device *dev, void *p)
3128 {
3129         struct rtl8169_private *tp = netdev_priv(dev);
3130         struct sockaddr *addr = p;
3131
3132         if (!is_valid_ether_addr(addr->sa_data))
3133                 return -EADDRNOTAVAIL;
3134
3135         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3136
3137         rtl_rar_set(tp, dev->dev_addr);
3138
3139         return 0;
3140 }
3141
3142 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3143 {
3144         struct rtl8169_private *tp = netdev_priv(dev);
3145         struct mii_ioctl_data *data = if_mii(ifr);
3146
3147         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3148 }
3149
3150 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3151                           struct mii_ioctl_data *data, int cmd)
3152 {
3153         switch (cmd) {
3154         case SIOCGMIIPHY:
3155                 data->phy_id = 32; /* Internal PHY */
3156                 return 0;
3157
3158         case SIOCGMIIREG:
3159                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3160                 return 0;
3161
3162         case SIOCSMIIREG:
3163                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3164                 return 0;
3165         }
3166         return -EOPNOTSUPP;
3167 }
3168
3169 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3170 {
3171         return -EOPNOTSUPP;
3172 }
3173
3174 static const struct rtl_cfg_info {
3175         void (*hw_start)(struct net_device *);
3176         unsigned int region;
3177         unsigned int align;
3178         u16 intr_event;
3179         u16 napi_event;
3180         unsigned features;
3181         u8 default_ver;
3182 } rtl_cfg_infos [] = {
3183         [RTL_CFG_0] = {
3184                 .hw_start       = rtl_hw_start_8169,
3185                 .region         = 1,
3186                 .align          = 0,
3187                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3188                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3189                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3190                 .features       = RTL_FEATURE_GMII,
3191                 .default_ver    = RTL_GIGA_MAC_VER_01,
3192         },
3193         [RTL_CFG_1] = {
3194                 .hw_start       = rtl_hw_start_8168,
3195                 .region         = 2,
3196                 .align          = 8,
3197                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3198                                   TxErr | TxOK | RxOK | RxErr,
3199                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3200                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3201                 .default_ver    = RTL_GIGA_MAC_VER_11,
3202         },
3203         [RTL_CFG_2] = {
3204                 .hw_start       = rtl_hw_start_8101,
3205                 .region         = 2,
3206                 .align          = 8,
3207                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3208                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3209                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3210                 .features       = RTL_FEATURE_MSI,
3211                 .default_ver    = RTL_GIGA_MAC_VER_13,
3212         }
3213 };
3214
3215 /* Cfg9346_Unlock assumed. */
3216 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3217                             const struct rtl_cfg_info *cfg)
3218 {
3219         unsigned msi = 0;
3220         u8 cfg2;
3221
3222         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3223         if (cfg->features & RTL_FEATURE_MSI) {
3224                 if (pci_enable_msi(pdev)) {
3225                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3226                 } else {
3227                         cfg2 |= MSIEnable;
3228                         msi = RTL_FEATURE_MSI;
3229                 }
3230         }
3231         RTL_W8(Config2, cfg2);
3232         return msi;
3233 }
3234
3235 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3236 {
3237         if (tp->features & RTL_FEATURE_MSI) {
3238                 pci_disable_msi(pdev);
3239                 tp->features &= ~RTL_FEATURE_MSI;
3240         }
3241 }
3242
3243 static const struct net_device_ops rtl8169_netdev_ops = {
3244         .ndo_open               = rtl8169_open,
3245         .ndo_stop               = rtl8169_close,
3246         .ndo_get_stats          = rtl8169_get_stats,
3247         .ndo_start_xmit         = rtl8169_start_xmit,
3248         .ndo_tx_timeout         = rtl8169_tx_timeout,
3249         .ndo_validate_addr      = eth_validate_addr,
3250         .ndo_change_mtu         = rtl8169_change_mtu,
3251         .ndo_fix_features       = rtl8169_fix_features,
3252         .ndo_set_features       = rtl8169_set_features,
3253         .ndo_set_mac_address    = rtl_set_mac_address,
3254         .ndo_do_ioctl           = rtl8169_ioctl,
3255         .ndo_set_multicast_list = rtl_set_rx_mode,
3256 #ifdef CONFIG_NET_POLL_CONTROLLER
3257         .ndo_poll_controller    = rtl8169_netpoll,
3258 #endif
3259
3260 };
3261
3262 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3263 {
3264         struct mdio_ops *ops = &tp->mdio_ops;
3265
3266         switch (tp->mac_version) {
3267         case RTL_GIGA_MAC_VER_27:
3268                 ops->write      = r8168dp_1_mdio_write;
3269                 ops->read       = r8168dp_1_mdio_read;
3270                 break;
3271         case RTL_GIGA_MAC_VER_28:
3272         case RTL_GIGA_MAC_VER_31:
3273                 ops->write      = r8168dp_2_mdio_write;
3274                 ops->read       = r8168dp_2_mdio_read;
3275                 break;
3276         default:
3277                 ops->write      = r8169_mdio_write;
3278                 ops->read       = r8169_mdio_read;
3279                 break;
3280         }
3281 }
3282
3283 static void r810x_phy_power_down(struct rtl8169_private *tp)
3284 {
3285         rtl_writephy(tp, 0x1f, 0x0000);
3286         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3287 }
3288
3289 static void r810x_phy_power_up(struct rtl8169_private *tp)
3290 {
3291         rtl_writephy(tp, 0x1f, 0x0000);
3292         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3293 }
3294
3295 static void r810x_pll_power_down(struct rtl8169_private *tp)
3296 {
3297         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3298                 rtl_writephy(tp, 0x1f, 0x0000);
3299                 rtl_writephy(tp, MII_BMCR, 0x0000);
3300                 return;
3301         }
3302
3303         r810x_phy_power_down(tp);
3304 }
3305
3306 static void r810x_pll_power_up(struct rtl8169_private *tp)
3307 {
3308         r810x_phy_power_up(tp);
3309 }
3310
3311 static void r8168_phy_power_up(struct rtl8169_private *tp)
3312 {
3313         rtl_writephy(tp, 0x1f, 0x0000);
3314         switch (tp->mac_version) {
3315         case RTL_GIGA_MAC_VER_11:
3316         case RTL_GIGA_MAC_VER_12:
3317         case RTL_GIGA_MAC_VER_17:
3318         case RTL_GIGA_MAC_VER_18:
3319         case RTL_GIGA_MAC_VER_19:
3320         case RTL_GIGA_MAC_VER_20:
3321         case RTL_GIGA_MAC_VER_21:
3322         case RTL_GIGA_MAC_VER_22:
3323         case RTL_GIGA_MAC_VER_23:
3324         case RTL_GIGA_MAC_VER_24:
3325         case RTL_GIGA_MAC_VER_25:
3326         case RTL_GIGA_MAC_VER_26:
3327         case RTL_GIGA_MAC_VER_27:
3328         case RTL_GIGA_MAC_VER_28:
3329         case RTL_GIGA_MAC_VER_31:
3330                 rtl_writephy(tp, 0x0e, 0x0000);
3331                 break;
3332         default:
3333                 break;
3334         }
3335         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3336 }
3337
3338 static void r8168_phy_power_down(struct rtl8169_private *tp)
3339 {
3340         rtl_writephy(tp, 0x1f, 0x0000);
3341         switch (tp->mac_version) {
3342         case RTL_GIGA_MAC_VER_32:
3343         case RTL_GIGA_MAC_VER_33:
3344                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3345                 break;
3346
3347         case RTL_GIGA_MAC_VER_11:
3348         case RTL_GIGA_MAC_VER_12:
3349         case RTL_GIGA_MAC_VER_17:
3350         case RTL_GIGA_MAC_VER_18:
3351         case RTL_GIGA_MAC_VER_19:
3352         case RTL_GIGA_MAC_VER_20:
3353         case RTL_GIGA_MAC_VER_21:
3354         case RTL_GIGA_MAC_VER_22:
3355         case RTL_GIGA_MAC_VER_23:
3356         case RTL_GIGA_MAC_VER_24:
3357         case RTL_GIGA_MAC_VER_25:
3358         case RTL_GIGA_MAC_VER_26:
3359         case RTL_GIGA_MAC_VER_27:
3360         case RTL_GIGA_MAC_VER_28:
3361         case RTL_GIGA_MAC_VER_31:
3362                 rtl_writephy(tp, 0x0e, 0x0200);
3363         default:
3364                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3365                 break;
3366         }
3367 }
3368
3369 static void r8168_pll_power_down(struct rtl8169_private *tp)
3370 {
3371         void __iomem *ioaddr = tp->mmio_addr;
3372
3373         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3374              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3375              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3376             r8168dp_check_dash(tp)) {
3377                 return;
3378         }
3379
3380         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3381              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3382             (RTL_R16(CPlusCmd) & ASF)) {
3383                 return;
3384         }
3385
3386         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3387             tp->mac_version == RTL_GIGA_MAC_VER_33)
3388                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3389
3390         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3391                 rtl_writephy(tp, 0x1f, 0x0000);
3392                 rtl_writephy(tp, MII_BMCR, 0x0000);
3393
3394                 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3395                     tp->mac_version == RTL_GIGA_MAC_VER_33)
3396                         RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3397                                 AcceptMulticast | AcceptMyPhys);
3398                 return;
3399         }
3400
3401         r8168_phy_power_down(tp);
3402
3403         switch (tp->mac_version) {
3404         case RTL_GIGA_MAC_VER_25:
3405         case RTL_GIGA_MAC_VER_26:
3406         case RTL_GIGA_MAC_VER_27:
3407         case RTL_GIGA_MAC_VER_28:
3408         case RTL_GIGA_MAC_VER_31:
3409         case RTL_GIGA_MAC_VER_32:
3410         case RTL_GIGA_MAC_VER_33:
3411                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3412                 break;
3413         }
3414 }
3415
3416 static void r8168_pll_power_up(struct rtl8169_private *tp)
3417 {
3418         void __iomem *ioaddr = tp->mmio_addr;
3419
3420         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3421              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3422              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3423             r8168dp_check_dash(tp)) {
3424                 return;
3425         }
3426
3427         switch (tp->mac_version) {
3428         case RTL_GIGA_MAC_VER_25:
3429         case RTL_GIGA_MAC_VER_26:
3430         case RTL_GIGA_MAC_VER_27:
3431         case RTL_GIGA_MAC_VER_28:
3432         case RTL_GIGA_MAC_VER_31:
3433         case RTL_GIGA_MAC_VER_32:
3434         case RTL_GIGA_MAC_VER_33:
3435                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3436                 break;
3437         }
3438
3439         r8168_phy_power_up(tp);
3440 }
3441
3442 static void rtl_pll_power_op(struct rtl8169_private *tp,
3443                              void (*op)(struct rtl8169_private *))
3444 {
3445         if (op)
3446                 op(tp);
3447 }
3448
3449 static void rtl_pll_power_down(struct rtl8169_private *tp)
3450 {
3451         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3452 }
3453
3454 static void rtl_pll_power_up(struct rtl8169_private *tp)
3455 {
3456         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3457 }
3458
3459 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3460 {
3461         struct pll_power_ops *ops = &tp->pll_power_ops;
3462
3463         switch (tp->mac_version) {
3464         case RTL_GIGA_MAC_VER_07:
3465         case RTL_GIGA_MAC_VER_08:
3466         case RTL_GIGA_MAC_VER_09:
3467         case RTL_GIGA_MAC_VER_10:
3468         case RTL_GIGA_MAC_VER_16:
3469         case RTL_GIGA_MAC_VER_29:
3470         case RTL_GIGA_MAC_VER_30:
3471                 ops->down       = r810x_pll_power_down;
3472                 ops->up         = r810x_pll_power_up;
3473                 break;
3474
3475         case RTL_GIGA_MAC_VER_11:
3476         case RTL_GIGA_MAC_VER_12:
3477         case RTL_GIGA_MAC_VER_17:
3478         case RTL_GIGA_MAC_VER_18:
3479         case RTL_GIGA_MAC_VER_19:
3480         case RTL_GIGA_MAC_VER_20:
3481         case RTL_GIGA_MAC_VER_21:
3482         case RTL_GIGA_MAC_VER_22:
3483         case RTL_GIGA_MAC_VER_23:
3484         case RTL_GIGA_MAC_VER_24:
3485         case RTL_GIGA_MAC_VER_25:
3486         case RTL_GIGA_MAC_VER_26:
3487         case RTL_GIGA_MAC_VER_27:
3488         case RTL_GIGA_MAC_VER_28:
3489         case RTL_GIGA_MAC_VER_31:
3490         case RTL_GIGA_MAC_VER_32:
3491         case RTL_GIGA_MAC_VER_33:
3492         case RTL_GIGA_MAC_VER_34:
3493                 ops->down       = r8168_pll_power_down;
3494                 ops->up         = r8168_pll_power_up;
3495                 break;
3496
3497         default:
3498                 ops->down       = NULL;
3499                 ops->up         = NULL;
3500                 break;
3501         }
3502 }
3503
3504 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3505 {
3506         void __iomem *ioaddr = tp->mmio_addr;
3507
3508         switch (tp->mac_version) {
3509         case RTL_GIGA_MAC_VER_01:
3510         case RTL_GIGA_MAC_VER_02:
3511         case RTL_GIGA_MAC_VER_03:
3512         case RTL_GIGA_MAC_VER_04:
3513         case RTL_GIGA_MAC_VER_05:
3514         case RTL_GIGA_MAC_VER_06:
3515         case RTL_GIGA_MAC_VER_10:
3516         case RTL_GIGA_MAC_VER_11:
3517         case RTL_GIGA_MAC_VER_12:
3518         case RTL_GIGA_MAC_VER_13:
3519         case RTL_GIGA_MAC_VER_14:
3520         case RTL_GIGA_MAC_VER_15:
3521         case RTL_GIGA_MAC_VER_16:
3522         case RTL_GIGA_MAC_VER_17:
3523                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3524                 break;
3525         case RTL_GIGA_MAC_VER_18:
3526         case RTL_GIGA_MAC_VER_19:
3527         case RTL_GIGA_MAC_VER_20:
3528         case RTL_GIGA_MAC_VER_21:
3529         case RTL_GIGA_MAC_VER_22:
3530         case RTL_GIGA_MAC_VER_23:
3531         case RTL_GIGA_MAC_VER_24:
3532                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3533                 break;
3534         default:
3535                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3536                 break;
3537         }
3538 }
3539
3540 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3541 {
3542         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3543 }
3544
3545 static void rtl_hw_reset(struct rtl8169_private *tp)
3546 {
3547         void __iomem *ioaddr = tp->mmio_addr;
3548         int i;
3549
3550         /* Soft reset the chip. */
3551         RTL_W8(ChipCmd, CmdReset);
3552
3553         /* Check that the chip has finished the reset. */
3554         for (i = 0; i < 100; i++) {
3555                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3556                         break;
3557                 udelay(100);
3558         }
3559
3560         rtl8169_init_ring_indexes(tp);
3561 }
3562
3563 static int __devinit
3564 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3565 {
3566         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3567         const unsigned int region = cfg->region;
3568         struct rtl8169_private *tp;
3569         struct mii_if_info *mii;
3570         struct net_device *dev;
3571         void __iomem *ioaddr;
3572         int chipset, i;
3573         int rc;
3574
3575         if (netif_msg_drv(&debug)) {
3576                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3577                        MODULENAME, RTL8169_VERSION);
3578         }
3579
3580         dev = alloc_etherdev(sizeof (*tp));
3581         if (!dev) {
3582                 if (netif_msg_drv(&debug))
3583                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3584                 rc = -ENOMEM;
3585                 goto out;
3586         }
3587
3588         SET_NETDEV_DEV(dev, &pdev->dev);
3589         dev->netdev_ops = &rtl8169_netdev_ops;
3590         tp = netdev_priv(dev);
3591         tp->dev = dev;
3592         tp->pci_dev = pdev;
3593         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3594
3595         mii = &tp->mii;
3596         mii->dev = dev;
3597         mii->mdio_read = rtl_mdio_read;
3598         mii->mdio_write = rtl_mdio_write;
3599         mii->phy_id_mask = 0x1f;
3600         mii->reg_num_mask = 0x1f;
3601         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3602
3603         /* disable ASPM completely as that cause random device stop working
3604          * problems as well as full system hangs for some PCIe devices users */
3605         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3606                                      PCIE_LINK_STATE_CLKPM);
3607
3608         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3609         rc = pci_enable_device(pdev);
3610         if (rc < 0) {
3611                 netif_err(tp, probe, dev, "enable failure\n");
3612                 goto err_out_free_dev_1;
3613         }
3614
3615         if (pci_set_mwi(pdev) < 0)
3616                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3617
3618         /* make sure PCI base addr 1 is MMIO */
3619         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3620                 netif_err(tp, probe, dev,
3621                           "region #%d not an MMIO resource, aborting\n",
3622                           region);
3623                 rc = -ENODEV;
3624                 goto err_out_mwi_2;
3625         }
3626
3627         /* check for weird/broken PCI region reporting */
3628         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3629                 netif_err(tp, probe, dev,
3630                           "Invalid PCI region size(s), aborting\n");
3631                 rc = -ENODEV;
3632                 goto err_out_mwi_2;
3633         }
3634
3635         rc = pci_request_regions(pdev, MODULENAME);
3636         if (rc < 0) {
3637                 netif_err(tp, probe, dev, "could not request regions\n");
3638                 goto err_out_mwi_2;
3639         }
3640
3641         tp->cp_cmd = RxChkSum;
3642
3643         if ((sizeof(dma_addr_t) > 4) &&
3644             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3645                 tp->cp_cmd |= PCIDAC;
3646                 dev->features |= NETIF_F_HIGHDMA;
3647         } else {
3648                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3649                 if (rc < 0) {
3650                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3651                         goto err_out_free_res_3;
3652                 }
3653         }
3654
3655         /* ioremap MMIO region */
3656         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3657         if (!ioaddr) {
3658                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3659                 rc = -EIO;
3660                 goto err_out_free_res_3;
3661         }
3662         tp->mmio_addr = ioaddr;
3663
3664         if (!pci_is_pcie(pdev))
3665                 netif_info(tp, probe, dev, "not PCI Express\n");
3666
3667         /* Identify chip attached to board */
3668         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3669
3670         rtl_init_rxcfg(tp);
3671
3672         RTL_W16(IntrMask, 0x0000);
3673
3674         rtl_hw_reset(tp);
3675
3676         RTL_W16(IntrStatus, 0xffff);
3677
3678         pci_set_master(pdev);
3679
3680         /*
3681          * Pretend we are using VLANs; This bypasses a nasty bug where
3682          * Interrupts stop flowing on high load on 8110SCd controllers.
3683          */
3684         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3685                 tp->cp_cmd |= RxVlan;
3686
3687         rtl_init_mdio_ops(tp);
3688         rtl_init_pll_power_ops(tp);
3689
3690         rtl8169_print_mac_version(tp);
3691
3692         chipset = tp->mac_version;
3693         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3694
3695         RTL_W8(Cfg9346, Cfg9346_Unlock);
3696         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3697         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3698         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3699                 tp->features |= RTL_FEATURE_WOL;
3700         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3701                 tp->features |= RTL_FEATURE_WOL;
3702         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3703         RTL_W8(Cfg9346, Cfg9346_Lock);
3704
3705         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3706             (RTL_R8(PHYstatus) & TBI_Enable)) {
3707                 tp->set_speed = rtl8169_set_speed_tbi;
3708                 tp->get_settings = rtl8169_gset_tbi;
3709                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3710                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3711                 tp->link_ok = rtl8169_tbi_link_ok;
3712                 tp->do_ioctl = rtl_tbi_ioctl;
3713         } else {
3714                 tp->set_speed = rtl8169_set_speed_xmii;
3715                 tp->get_settings = rtl8169_gset_xmii;
3716                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3717                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3718                 tp->link_ok = rtl8169_xmii_link_ok;
3719                 tp->do_ioctl = rtl_xmii_ioctl;
3720         }
3721
3722         spin_lock_init(&tp->lock);
3723
3724         /* Get MAC address */
3725         for (i = 0; i < MAC_ADDR_LEN; i++)
3726                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3727         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3728
3729         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3730         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3731         dev->irq = pdev->irq;
3732         dev->base_addr = (unsigned long) ioaddr;
3733
3734         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3735
3736         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3737          * properly for all devices */
3738         dev->features |= NETIF_F_RXCSUM |
3739                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3740
3741         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3742                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3743         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3744                 NETIF_F_HIGHDMA;
3745
3746         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3747                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3748                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3749
3750         tp->intr_mask = 0xffff;
3751         tp->hw_start = cfg->hw_start;
3752         tp->intr_event = cfg->intr_event;
3753         tp->napi_event = cfg->napi_event;
3754
3755         init_timer(&tp->timer);
3756         tp->timer.data = (unsigned long) dev;
3757         tp->timer.function = rtl8169_phy_timer;
3758
3759         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3760
3761         rc = register_netdev(dev);
3762         if (rc < 0)
3763                 goto err_out_msi_4;
3764
3765         pci_set_drvdata(pdev, dev);
3766
3767         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3768                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3769                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3770
3771         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3772             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3773             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3774                 rtl8168_driver_start(tp);
3775         }
3776
3777         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3778
3779         if (pci_dev_run_wake(pdev))
3780                 pm_runtime_put_noidle(&pdev->dev);
3781
3782         netif_carrier_off(dev);
3783
3784 out:
3785         return rc;
3786
3787 err_out_msi_4:
3788         rtl_disable_msi(pdev, tp);
3789         iounmap(ioaddr);
3790 err_out_free_res_3:
3791         pci_release_regions(pdev);
3792 err_out_mwi_2:
3793         pci_clear_mwi(pdev);
3794         pci_disable_device(pdev);
3795 err_out_free_dev_1:
3796         free_netdev(dev);
3797         goto out;
3798 }
3799
3800 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3801 {
3802         struct net_device *dev = pci_get_drvdata(pdev);
3803         struct rtl8169_private *tp = netdev_priv(dev);
3804
3805         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3806             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3807             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3808                 rtl8168_driver_stop(tp);
3809         }
3810
3811         cancel_delayed_work_sync(&tp->task);
3812
3813         unregister_netdev(dev);
3814
3815         rtl_release_firmware(tp);
3816
3817         if (pci_dev_run_wake(pdev))
3818                 pm_runtime_get_noresume(&pdev->dev);
3819
3820         /* restore original MAC address */
3821         rtl_rar_set(tp, dev->perm_addr);
3822
3823         rtl_disable_msi(pdev, tp);
3824         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3825         pci_set_drvdata(pdev, NULL);
3826 }
3827
3828 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3829 {
3830         struct rtl_fw *rtl_fw;
3831         const char *name;
3832         int rc = -ENOMEM;
3833
3834         name = rtl_lookup_firmware_name(tp);
3835         if (!name)
3836                 goto out_no_firmware;
3837
3838         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3839         if (!rtl_fw)
3840                 goto err_warn;
3841
3842         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3843         if (rc < 0)
3844                 goto err_free;
3845
3846         rc = rtl_check_firmware(tp, rtl_fw);
3847         if (rc < 0)
3848                 goto err_release_firmware;
3849
3850         tp->rtl_fw = rtl_fw;
3851 out:
3852         return;
3853
3854 err_release_firmware:
3855         release_firmware(rtl_fw->fw);
3856 err_free:
3857         kfree(rtl_fw);
3858 err_warn:
3859         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3860                    name, rc);
3861 out_no_firmware:
3862         tp->rtl_fw = NULL;
3863         goto out;
3864 }
3865
3866 static void rtl_request_firmware(struct rtl8169_private *tp)
3867 {
3868         if (IS_ERR(tp->rtl_fw))
3869                 rtl_request_uncached_firmware(tp);
3870 }
3871
3872 static int rtl8169_open(struct net_device *dev)
3873 {
3874         struct rtl8169_private *tp = netdev_priv(dev);
3875         void __iomem *ioaddr = tp->mmio_addr;
3876         struct pci_dev *pdev = tp->pci_dev;
3877         int retval = -ENOMEM;
3878
3879         pm_runtime_get_sync(&pdev->dev);
3880
3881         /*
3882          * Rx and Tx desscriptors needs 256 bytes alignment.
3883          * dma_alloc_coherent provides more.
3884          */
3885         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3886                                              &tp->TxPhyAddr, GFP_KERNEL);
3887         if (!tp->TxDescArray)
3888                 goto err_pm_runtime_put;
3889
3890         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3891                                              &tp->RxPhyAddr, GFP_KERNEL);
3892         if (!tp->RxDescArray)
3893                 goto err_free_tx_0;
3894
3895         retval = rtl8169_init_ring(dev);
3896         if (retval < 0)
3897                 goto err_free_rx_1;
3898
3899         INIT_DELAYED_WORK(&tp->task, NULL);
3900
3901         smp_mb();
3902
3903         rtl_request_firmware(tp);
3904
3905         retval = request_irq(dev->irq, rtl8169_interrupt,
3906                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3907                              dev->name, dev);
3908         if (retval < 0)
3909                 goto err_release_fw_2;
3910
3911         napi_enable(&tp->napi);
3912
3913         rtl8169_init_phy(dev, tp);
3914
3915         rtl8169_set_features(dev, dev->features);
3916
3917         rtl_pll_power_up(tp);
3918
3919         rtl_hw_start(dev);
3920
3921         tp->saved_wolopts = 0;
3922         pm_runtime_put_noidle(&pdev->dev);
3923
3924         rtl8169_check_link_status(dev, tp, ioaddr);
3925 out:
3926         return retval;
3927
3928 err_release_fw_2:
3929         rtl_release_firmware(tp);
3930         rtl8169_rx_clear(tp);
3931 err_free_rx_1:
3932         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3933                           tp->RxPhyAddr);
3934         tp->RxDescArray = NULL;
3935 err_free_tx_0:
3936         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3937                           tp->TxPhyAddr);
3938         tp->TxDescArray = NULL;
3939 err_pm_runtime_put:
3940         pm_runtime_put_noidle(&pdev->dev);
3941         goto out;
3942 }
3943
3944 static void rtl_rx_close(struct rtl8169_private *tp)
3945 {
3946         void __iomem *ioaddr = tp->mmio_addr;
3947
3948         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
3949 }
3950
3951 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3952 {
3953         void __iomem *ioaddr = tp->mmio_addr;
3954
3955         /* Disable interrupts */
3956         rtl8169_irq_mask_and_ack(ioaddr);
3957
3958         rtl_rx_close(tp);
3959
3960         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3961             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3962             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3963                 while (RTL_R8(TxPoll) & NPQ)
3964                         udelay(20);
3965         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3966                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
3967                         udelay(100);
3968         } else {
3969                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
3970                 udelay(100);
3971         }
3972
3973         rtl_hw_reset(tp);
3974 }
3975
3976 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3977 {
3978         void __iomem *ioaddr = tp->mmio_addr;
3979
3980         /* Set DMA burst size and Interframe Gap Time */
3981         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3982                 (InterFrameGap << TxInterFrameGapShift));
3983 }
3984
3985 static void rtl_hw_start(struct net_device *dev)
3986 {
3987         struct rtl8169_private *tp = netdev_priv(dev);
3988
3989         tp->hw_start(dev);
3990
3991         netif_start_queue(dev);
3992 }
3993
3994 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3995                                          void __iomem *ioaddr)
3996 {
3997         /*
3998          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3999          * register to be written before TxDescAddrLow to work.
4000          * Switching from MMIO to I/O access fixes the issue as well.
4001          */
4002         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4003         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4004         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4005         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4006 }
4007
4008 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4009 {
4010         u16 cmd;
4011
4012         cmd = RTL_R16(CPlusCmd);
4013         RTL_W16(CPlusCmd, cmd);
4014         return cmd;
4015 }
4016
4017 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4018 {
4019         /* Low hurts. Let's disable the filtering. */
4020         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4021 }
4022
4023 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4024 {
4025         static const struct rtl_cfg2_info {
4026                 u32 mac_version;
4027                 u32 clk;
4028                 u32 val;
4029         } cfg2_info [] = {
4030                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4031                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4032                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4033                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4034         };
4035         const struct rtl_cfg2_info *p = cfg2_info;
4036         unsigned int i;
4037         u32 clk;
4038
4039         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4040         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4041                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4042                         RTL_W32(0x7c, p->val);
4043                         break;
4044                 }
4045         }
4046 }
4047
4048 static void rtl_hw_start_8169(struct net_device *dev)
4049 {
4050         struct rtl8169_private *tp = netdev_priv(dev);
4051         void __iomem *ioaddr = tp->mmio_addr;
4052         struct pci_dev *pdev = tp->pci_dev;
4053
4054         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4055                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4056                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4057         }
4058
4059         RTL_W8(Cfg9346, Cfg9346_Unlock);
4060         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4061             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4062             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4063             tp->mac_version == RTL_GIGA_MAC_VER_04)
4064                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4065
4066         rtl_init_rxcfg(tp);
4067
4068         RTL_W8(EarlyTxThres, NoEarlyTx);
4069
4070         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4071
4072         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4073             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4074             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4075             tp->mac_version == RTL_GIGA_MAC_VER_04)
4076                 rtl_set_rx_tx_config_registers(tp);
4077
4078         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4079
4080         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4081             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4082                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4083                         "Bit-3 and bit-14 MUST be 1\n");
4084                 tp->cp_cmd |= (1 << 14);
4085         }
4086
4087         RTL_W16(CPlusCmd, tp->cp_cmd);
4088
4089         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4090
4091         /*
4092          * Undocumented corner. Supposedly:
4093          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4094          */
4095         RTL_W16(IntrMitigate, 0x0000);
4096
4097         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4098
4099         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4100             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4101             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4102             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4103                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4104                 rtl_set_rx_tx_config_registers(tp);
4105         }
4106
4107         RTL_W8(Cfg9346, Cfg9346_Lock);
4108
4109         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4110         RTL_R8(IntrMask);
4111
4112         RTL_W32(RxMissed, 0);
4113
4114         rtl_set_rx_mode(dev);
4115
4116         /* no early-rx interrupts */
4117         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4118
4119         /* Enable all known interrupts by setting the interrupt mask. */
4120         RTL_W16(IntrMask, tp->intr_event);
4121 }
4122
4123 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
4124 {
4125         int cap = pci_pcie_cap(pdev);
4126
4127         if (cap) {
4128                 u16 ctl;
4129
4130                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4131                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4132                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4133         }
4134 }
4135
4136 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4137 {
4138         u32 csi;
4139
4140         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4141         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4142 }
4143
4144 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4145 {
4146         rtl_csi_access_enable(ioaddr, 0x17000000);
4147 }
4148
4149 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4150 {
4151         rtl_csi_access_enable(ioaddr, 0x27000000);
4152 }
4153
4154 struct ephy_info {
4155         unsigned int offset;
4156         u16 mask;
4157         u16 bits;
4158 };
4159
4160 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4161 {
4162         u16 w;
4163
4164         while (len-- > 0) {
4165                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4166                 rtl_ephy_write(ioaddr, e->offset, w);
4167                 e++;
4168         }
4169 }
4170
4171 static void rtl_disable_clock_request(struct pci_dev *pdev)
4172 {
4173         int cap = pci_pcie_cap(pdev);
4174
4175         if (cap) {
4176                 u16 ctl;
4177
4178                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4179                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4180                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4181         }
4182 }
4183
4184 static void rtl_enable_clock_request(struct pci_dev *pdev)
4185 {
4186         int cap = pci_pcie_cap(pdev);
4187
4188         if (cap) {
4189                 u16 ctl;
4190
4191                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4192                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4193                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4194         }
4195 }
4196
4197 #define R8168_CPCMD_QUIRK_MASK (\
4198         EnableBist | \
4199         Mac_dbgo_oe | \
4200         Force_half_dup | \
4201         Force_rxflow_en | \
4202         Force_txflow_en | \
4203         Cxpl_dbg_sel | \
4204         ASF | \
4205         PktCntrDisable | \
4206         Mac_dbgo_sel)
4207
4208 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4209 {
4210         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4211
4212         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4213
4214         rtl_tx_performance_tweak(pdev,
4215                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4216 }
4217
4218 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4219 {
4220         rtl_hw_start_8168bb(ioaddr, pdev);
4221
4222         RTL_W8(MaxTxPacketSize, TxPacketMax);
4223
4224         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4225 }
4226
4227 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4228 {
4229         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4230
4231         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4232
4233         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4234
4235         rtl_disable_clock_request(pdev);
4236
4237         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4238 }
4239
4240 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4241 {
4242         static const struct ephy_info e_info_8168cp[] = {
4243                 { 0x01, 0,      0x0001 },
4244                 { 0x02, 0x0800, 0x1000 },
4245                 { 0x03, 0,      0x0042 },
4246                 { 0x06, 0x0080, 0x0000 },
4247                 { 0x07, 0,      0x2000 }
4248         };
4249
4250         rtl_csi_access_enable_2(ioaddr);
4251
4252         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4253
4254         __rtl_hw_start_8168cp(ioaddr, pdev);
4255 }
4256
4257 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4258 {
4259         rtl_csi_access_enable_2(ioaddr);
4260
4261         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4262
4263         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4264
4265         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4266 }
4267
4268 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4269 {
4270         rtl_csi_access_enable_2(ioaddr);
4271
4272         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4273
4274         /* Magic. */
4275         RTL_W8(DBG_REG, 0x20);
4276
4277         RTL_W8(MaxTxPacketSize, TxPacketMax);
4278
4279         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4280
4281         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4282 }
4283
4284 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4285 {
4286         static const struct ephy_info e_info_8168c_1[] = {
4287                 { 0x02, 0x0800, 0x1000 },
4288                 { 0x03, 0,      0x0002 },
4289                 { 0x06, 0x0080, 0x0000 }
4290         };
4291
4292         rtl_csi_access_enable_2(ioaddr);
4293
4294         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4295
4296         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4297
4298         __rtl_hw_start_8168cp(ioaddr, pdev);
4299 }
4300
4301 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4302 {
4303         static const struct ephy_info e_info_8168c_2[] = {
4304                 { 0x01, 0,      0x0001 },
4305                 { 0x03, 0x0400, 0x0220 }
4306         };
4307
4308         rtl_csi_access_enable_2(ioaddr);
4309
4310         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4311
4312         __rtl_hw_start_8168cp(ioaddr, pdev);
4313 }
4314
4315 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4316 {
4317         rtl_hw_start_8168c_2(ioaddr, pdev);
4318 }
4319
4320 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4321 {
4322         rtl_csi_access_enable_2(ioaddr);
4323
4324         __rtl_hw_start_8168cp(ioaddr, pdev);
4325 }
4326
4327 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4328 {
4329         rtl_csi_access_enable_2(ioaddr);
4330
4331         rtl_disable_clock_request(pdev);
4332
4333         RTL_W8(MaxTxPacketSize, TxPacketMax);
4334
4335         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4336
4337         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4338 }
4339
4340 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4341 {
4342         rtl_csi_access_enable_1(ioaddr);
4343
4344         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4345
4346         RTL_W8(MaxTxPacketSize, TxPacketMax);
4347
4348         rtl_disable_clock_request(pdev);
4349 }
4350
4351 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4352 {
4353         static const struct ephy_info e_info_8168d_4[] = {
4354                 { 0x0b, ~0,     0x48 },
4355                 { 0x19, 0x20,   0x50 },
4356                 { 0x0c, ~0,     0x20 }
4357         };
4358         int i;
4359
4360         rtl_csi_access_enable_1(ioaddr);
4361
4362         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4363
4364         RTL_W8(MaxTxPacketSize, TxPacketMax);
4365
4366         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4367                 const struct ephy_info *e = e_info_8168d_4 + i;
4368                 u16 w;
4369
4370                 w = rtl_ephy_read(ioaddr, e->offset);
4371                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4372         }
4373
4374         rtl_enable_clock_request(pdev);
4375 }
4376
4377 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4378 {
4379         static const struct ephy_info e_info_8168e_1[] = {
4380                 { 0x00, 0x0200, 0x0100 },
4381                 { 0x00, 0x0000, 0x0004 },
4382                 { 0x06, 0x0002, 0x0001 },
4383                 { 0x06, 0x0000, 0x0030 },
4384                 { 0x07, 0x0000, 0x2000 },
4385                 { 0x00, 0x0000, 0x0020 },
4386                 { 0x03, 0x5800, 0x2000 },
4387                 { 0x03, 0x0000, 0x0001 },
4388                 { 0x01, 0x0800, 0x1000 },
4389                 { 0x07, 0x0000, 0x4000 },
4390                 { 0x1e, 0x0000, 0x2000 },
4391                 { 0x19, 0xffff, 0xfe6c },
4392                 { 0x0a, 0x0000, 0x0040 }
4393         };
4394
4395         rtl_csi_access_enable_2(ioaddr);
4396
4397         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4398
4399         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4400
4401         RTL_W8(MaxTxPacketSize, TxPacketMax);
4402
4403         rtl_disable_clock_request(pdev);
4404
4405         /* Reset tx FIFO pointer */
4406         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4407         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4408
4409         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4410 }
4411
4412 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4413 {
4414         static const struct ephy_info e_info_8168e_2[] = {
4415                 { 0x09, 0x0000, 0x0080 },
4416                 { 0x19, 0x0000, 0x0224 }
4417         };
4418
4419         rtl_csi_access_enable_1(ioaddr);
4420
4421         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4422
4423         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4424
4425         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4426         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4427         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4428         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4429         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4430         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4431         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4432         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4433                      ERIAR_EXGMAC);
4434
4435         RTL_W8(MaxTxPacketSize, 0x27);
4436
4437         rtl_disable_clock_request(pdev);
4438
4439         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4440         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4441
4442         /* Adjust EEE LED frequency */
4443         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4444
4445         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4446         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4447         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4448 }
4449
4450 static void rtl_hw_start_8168(struct net_device *dev)
4451 {
4452         struct rtl8169_private *tp = netdev_priv(dev);
4453         void __iomem *ioaddr = tp->mmio_addr;
4454         struct pci_dev *pdev = tp->pci_dev;
4455
4456         RTL_W8(Cfg9346, Cfg9346_Unlock);
4457
4458         RTL_W8(MaxTxPacketSize, TxPacketMax);
4459
4460         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4461
4462         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4463
4464         RTL_W16(CPlusCmd, tp->cp_cmd);
4465
4466         RTL_W16(IntrMitigate, 0x5151);
4467
4468         /* Work around for RxFIFO overflow. */
4469         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4470             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4471                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4472                 tp->intr_event &= ~RxOverflow;
4473         }
4474
4475         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4476
4477         rtl_set_rx_mode(dev);
4478
4479         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4480                 (InterFrameGap << TxInterFrameGapShift));
4481
4482         RTL_R8(IntrMask);
4483
4484         switch (tp->mac_version) {
4485         case RTL_GIGA_MAC_VER_11:
4486                 rtl_hw_start_8168bb(ioaddr, pdev);
4487                 break;
4488
4489         case RTL_GIGA_MAC_VER_12:
4490         case RTL_GIGA_MAC_VER_17:
4491                 rtl_hw_start_8168bef(ioaddr, pdev);
4492                 break;
4493
4494         case RTL_GIGA_MAC_VER_18:
4495                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4496                 break;
4497
4498         case RTL_GIGA_MAC_VER_19:
4499                 rtl_hw_start_8168c_1(ioaddr, pdev);
4500                 break;
4501
4502         case RTL_GIGA_MAC_VER_20:
4503                 rtl_hw_start_8168c_2(ioaddr, pdev);
4504                 break;
4505
4506         case RTL_GIGA_MAC_VER_21:
4507                 rtl_hw_start_8168c_3(ioaddr, pdev);
4508                 break;
4509
4510         case RTL_GIGA_MAC_VER_22:
4511                 rtl_hw_start_8168c_4(ioaddr, pdev);
4512                 break;
4513
4514         case RTL_GIGA_MAC_VER_23:
4515                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4516                 break;
4517
4518         case RTL_GIGA_MAC_VER_24:
4519                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4520                 break;
4521
4522         case RTL_GIGA_MAC_VER_25:
4523         case RTL_GIGA_MAC_VER_26:
4524         case RTL_GIGA_MAC_VER_27:
4525                 rtl_hw_start_8168d(ioaddr, pdev);
4526                 break;
4527
4528         case RTL_GIGA_MAC_VER_28:
4529                 rtl_hw_start_8168d_4(ioaddr, pdev);
4530                 break;
4531
4532         case RTL_GIGA_MAC_VER_31:
4533                 rtl_hw_start_8168dp(ioaddr, pdev);
4534                 break;
4535
4536         case RTL_GIGA_MAC_VER_32:
4537         case RTL_GIGA_MAC_VER_33:
4538                 rtl_hw_start_8168e_1(ioaddr, pdev);
4539                 break;
4540         case RTL_GIGA_MAC_VER_34:
4541                 rtl_hw_start_8168e_2(ioaddr, pdev);
4542                 break;
4543
4544         default:
4545                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4546                         dev->name, tp->mac_version);
4547                 break;
4548         }
4549
4550         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4551
4552         RTL_W8(Cfg9346, Cfg9346_Lock);
4553
4554         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4555
4556         RTL_W16(IntrMask, tp->intr_event);
4557 }
4558
4559 #define R810X_CPCMD_QUIRK_MASK (\
4560         EnableBist | \
4561         Mac_dbgo_oe | \
4562         Force_half_dup | \
4563         Force_rxflow_en | \
4564         Force_txflow_en | \
4565         Cxpl_dbg_sel | \
4566         ASF | \
4567         PktCntrDisable | \
4568         Mac_dbgo_sel)
4569
4570 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4571 {
4572         static const struct ephy_info e_info_8102e_1[] = {
4573                 { 0x01, 0, 0x6e65 },
4574                 { 0x02, 0, 0x091f },
4575                 { 0x03, 0, 0xc2f9 },
4576                 { 0x06, 0, 0xafb5 },
4577                 { 0x07, 0, 0x0e00 },
4578                 { 0x19, 0, 0xec80 },
4579                 { 0x01, 0, 0x2e65 },
4580                 { 0x01, 0, 0x6e65 }
4581         };
4582         u8 cfg1;
4583
4584         rtl_csi_access_enable_2(ioaddr);
4585
4586         RTL_W8(DBG_REG, FIX_NAK_1);
4587
4588         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4589
4590         RTL_W8(Config1,
4591                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4592         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4593
4594         cfg1 = RTL_R8(Config1);
4595         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4596                 RTL_W8(Config1, cfg1 & ~LEDS0);
4597
4598         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4599 }
4600
4601 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4602 {
4603         rtl_csi_access_enable_2(ioaddr);
4604
4605         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4606
4607         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4608         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4609 }
4610
4611 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4612 {
4613         rtl_hw_start_8102e_2(ioaddr, pdev);
4614
4615         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4616 }
4617
4618 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4619 {
4620         static const struct ephy_info e_info_8105e_1[] = {
4621                 { 0x07, 0, 0x4000 },
4622                 { 0x19, 0, 0x0200 },
4623                 { 0x19, 0, 0x0020 },
4624                 { 0x1e, 0, 0x2000 },
4625                 { 0x03, 0, 0x0001 },
4626                 { 0x19, 0, 0x0100 },
4627                 { 0x19, 0, 0x0004 },
4628                 { 0x0a, 0, 0x0020 }
4629         };
4630
4631         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4632         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4633
4634         /* Disable Early Tally Counter */
4635         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4636
4637         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4638         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4639
4640         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4641 }
4642
4643 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4644 {
4645         rtl_hw_start_8105e_1(ioaddr, pdev);
4646         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4647 }
4648
4649 static void rtl_hw_start_8101(struct net_device *dev)
4650 {
4651         struct rtl8169_private *tp = netdev_priv(dev);
4652         void __iomem *ioaddr = tp->mmio_addr;
4653         struct pci_dev *pdev = tp->pci_dev;
4654
4655         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4656             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4657                 int cap = pci_pcie_cap(pdev);
4658
4659                 if (cap) {
4660                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4661                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4662                 }
4663         }
4664
4665         RTL_W8(Cfg9346, Cfg9346_Unlock);
4666
4667         switch (tp->mac_version) {
4668         case RTL_GIGA_MAC_VER_07:
4669                 rtl_hw_start_8102e_1(ioaddr, pdev);
4670                 break;
4671
4672         case RTL_GIGA_MAC_VER_08:
4673                 rtl_hw_start_8102e_3(ioaddr, pdev);
4674                 break;
4675
4676         case RTL_GIGA_MAC_VER_09:
4677                 rtl_hw_start_8102e_2(ioaddr, pdev);
4678                 break;
4679
4680         case RTL_GIGA_MAC_VER_29:
4681                 rtl_hw_start_8105e_1(ioaddr, pdev);
4682                 break;
4683         case RTL_GIGA_MAC_VER_30:
4684                 rtl_hw_start_8105e_2(ioaddr, pdev);
4685                 break;
4686         }
4687
4688         RTL_W8(Cfg9346, Cfg9346_Lock);
4689
4690         RTL_W8(MaxTxPacketSize, TxPacketMax);
4691
4692         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4693
4694         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4695         RTL_W16(CPlusCmd, tp->cp_cmd);
4696
4697         RTL_W16(IntrMitigate, 0x0000);
4698
4699         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4700
4701         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4702         rtl_set_rx_tx_config_registers(tp);
4703
4704         RTL_R8(IntrMask);
4705
4706         rtl_set_rx_mode(dev);
4707
4708         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4709
4710         RTL_W16(IntrMask, tp->intr_event);
4711 }
4712
4713 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4714 {
4715         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4716                 return -EINVAL;
4717
4718         dev->mtu = new_mtu;
4719         netdev_update_features(dev);
4720
4721         return 0;
4722 }
4723
4724 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4725 {
4726         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4727         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4728 }
4729
4730 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4731                                      void **data_buff, struct RxDesc *desc)
4732 {
4733         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4734                          DMA_FROM_DEVICE);
4735
4736         kfree(*data_buff);
4737         *data_buff = NULL;
4738         rtl8169_make_unusable_by_asic(desc);
4739 }
4740
4741 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4742 {
4743         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4744
4745         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4746 }
4747
4748 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4749                                        u32 rx_buf_sz)
4750 {
4751         desc->addr = cpu_to_le64(mapping);
4752         wmb();
4753         rtl8169_mark_to_asic(desc, rx_buf_sz);
4754 }
4755
4756 static inline void *rtl8169_align(void *data)
4757 {
4758         return (void *)ALIGN((long)data, 16);
4759 }
4760
4761 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4762                                              struct RxDesc *desc)
4763 {
4764         void *data;
4765         dma_addr_t mapping;
4766         struct device *d = &tp->pci_dev->dev;
4767         struct net_device *dev = tp->dev;
4768         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4769
4770         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4771         if (!data)
4772                 return NULL;
4773
4774         if (rtl8169_align(data) != data) {
4775                 kfree(data);
4776                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4777                 if (!data)
4778                         return NULL;
4779         }
4780
4781         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4782                                  DMA_FROM_DEVICE);
4783         if (unlikely(dma_mapping_error(d, mapping))) {
4784                 if (net_ratelimit())
4785                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4786                 goto err_out;
4787         }
4788
4789         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4790         return data;
4791
4792 err_out:
4793         kfree(data);
4794         return NULL;
4795 }
4796
4797 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4798 {
4799         unsigned int i;
4800
4801         for (i = 0; i < NUM_RX_DESC; i++) {
4802                 if (tp->Rx_databuff[i]) {
4803                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4804                                             tp->RxDescArray + i);
4805                 }
4806         }
4807 }
4808
4809 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4810 {
4811         desc->opts1 |= cpu_to_le32(RingEnd);
4812 }
4813
4814 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4815 {
4816         unsigned int i;
4817
4818         for (i = 0; i < NUM_RX_DESC; i++) {
4819                 void *data;
4820
4821                 if (tp->Rx_databuff[i])
4822                         continue;
4823
4824                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4825                 if (!data) {
4826                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4827                         goto err_out;
4828                 }
4829                 tp->Rx_databuff[i] = data;
4830         }
4831
4832         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4833         return 0;
4834
4835 err_out:
4836         rtl8169_rx_clear(tp);
4837         return -ENOMEM;
4838 }
4839
4840 static int rtl8169_init_ring(struct net_device *dev)
4841 {
4842         struct rtl8169_private *tp = netdev_priv(dev);
4843
4844         rtl8169_init_ring_indexes(tp);
4845
4846         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4847         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4848
4849         return rtl8169_rx_fill(tp);
4850 }
4851
4852 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4853                                  struct TxDesc *desc)
4854 {
4855         unsigned int len = tx_skb->len;
4856
4857         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4858
4859         desc->opts1 = 0x00;
4860         desc->opts2 = 0x00;
4861         desc->addr = 0x00;
4862         tx_skb->len = 0;
4863 }
4864
4865 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4866                                    unsigned int n)
4867 {
4868         unsigned int i;
4869
4870         for (i = 0; i < n; i++) {
4871                 unsigned int entry = (start + i) % NUM_TX_DESC;
4872                 struct ring_info *tx_skb = tp->tx_skb + entry;
4873                 unsigned int len = tx_skb->len;
4874
4875                 if (len) {
4876                         struct sk_buff *skb = tx_skb->skb;
4877
4878                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4879                                              tp->TxDescArray + entry);
4880                         if (skb) {
4881                                 tp->dev->stats.tx_dropped++;
4882                                 dev_kfree_skb(skb);
4883                                 tx_skb->skb = NULL;
4884                         }
4885                 }
4886         }
4887 }
4888
4889 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4890 {
4891         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4892         tp->cur_tx = tp->dirty_tx = 0;
4893 }
4894
4895 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4896 {
4897         struct rtl8169_private *tp = netdev_priv(dev);
4898
4899         PREPARE_DELAYED_WORK(&tp->task, task);
4900         schedule_delayed_work(&tp->task, 4);
4901 }
4902
4903 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4904 {
4905         struct rtl8169_private *tp = netdev_priv(dev);
4906         void __iomem *ioaddr = tp->mmio_addr;
4907
4908         synchronize_irq(dev->irq);
4909
4910         /* Wait for any pending NAPI task to complete */
4911         napi_disable(&tp->napi);
4912
4913         rtl8169_irq_mask_and_ack(ioaddr);
4914
4915         tp->intr_mask = 0xffff;
4916         RTL_W16(IntrMask, tp->intr_event);
4917         napi_enable(&tp->napi);
4918 }
4919
4920 static void rtl8169_reinit_task(struct work_struct *work)
4921 {
4922         struct rtl8169_private *tp =
4923                 container_of(work, struct rtl8169_private, task.work);
4924         struct net_device *dev = tp->dev;
4925         int ret;
4926
4927         rtnl_lock();
4928
4929         if (!netif_running(dev))
4930                 goto out_unlock;
4931
4932         rtl8169_wait_for_quiescence(dev);
4933         rtl8169_close(dev);
4934
4935         ret = rtl8169_open(dev);
4936         if (unlikely(ret < 0)) {
4937                 if (net_ratelimit())
4938                         netif_err(tp, drv, dev,
4939                                   "reinit failure (status = %d). Rescheduling\n",
4940                                   ret);
4941                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4942         }
4943
4944 out_unlock:
4945         rtnl_unlock();
4946 }
4947
4948 static void rtl8169_reset_task(struct work_struct *work)
4949 {
4950         struct rtl8169_private *tp =
4951                 container_of(work, struct rtl8169_private, task.work);
4952         struct net_device *dev = tp->dev;
4953         int i;
4954
4955         rtnl_lock();
4956
4957         if (!netif_running(dev))
4958                 goto out_unlock;
4959
4960         rtl8169_wait_for_quiescence(dev);
4961
4962         for (i = 0; i < NUM_RX_DESC; i++)
4963                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4964
4965         rtl8169_tx_clear(tp);
4966
4967         rtl8169_hw_reset(tp);
4968         rtl_hw_start(dev);
4969         netif_wake_queue(dev);
4970         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4971
4972 out_unlock:
4973         rtnl_unlock();
4974 }
4975
4976 static void rtl8169_tx_timeout(struct net_device *dev)
4977 {
4978         struct rtl8169_private *tp = netdev_priv(dev);
4979
4980         rtl8169_hw_reset(tp);
4981
4982         /* Let's wait a bit while any (async) irq lands on */
4983         rtl8169_schedule_work(dev, rtl8169_reset_task);
4984 }
4985
4986 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4987                               u32 *opts)
4988 {
4989         struct skb_shared_info *info = skb_shinfo(skb);
4990         unsigned int cur_frag, entry;
4991         struct TxDesc * uninitialized_var(txd);
4992         struct device *d = &tp->pci_dev->dev;
4993
4994         entry = tp->cur_tx;
4995         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4996                 skb_frag_t *frag = info->frags + cur_frag;
4997                 dma_addr_t mapping;
4998                 u32 status, len;
4999                 void *addr;
5000
5001                 entry = (entry + 1) % NUM_TX_DESC;
5002
5003                 txd = tp->TxDescArray + entry;
5004                 len = frag->size;
5005                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
5006                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5007                 if (unlikely(dma_mapping_error(d, mapping))) {
5008                         if (net_ratelimit())
5009                                 netif_err(tp, drv, tp->dev,
5010                                           "Failed to map TX fragments DMA!\n");
5011                         goto err_out;
5012                 }
5013
5014                 /* Anti gcc 2.95.3 bugware (sic) */
5015                 status = opts[0] | len |
5016                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5017
5018                 txd->opts1 = cpu_to_le32(status);
5019                 txd->opts2 = cpu_to_le32(opts[1]);
5020                 txd->addr = cpu_to_le64(mapping);
5021
5022                 tp->tx_skb[entry].len = len;
5023         }
5024
5025         if (cur_frag) {
5026                 tp->tx_skb[entry].skb = skb;
5027                 txd->opts1 |= cpu_to_le32(LastFrag);
5028         }
5029
5030         return cur_frag;
5031
5032 err_out:
5033         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5034         return -EIO;
5035 }
5036
5037 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5038                                     struct sk_buff *skb, u32 *opts)
5039 {
5040         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5041         u32 mss = skb_shinfo(skb)->gso_size;
5042         int offset = info->opts_offset;
5043
5044         if (mss) {
5045                 opts[0] |= TD_LSO;
5046                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5047         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5048                 const struct iphdr *ip = ip_hdr(skb);
5049
5050                 if (ip->protocol == IPPROTO_TCP)
5051                         opts[offset] |= info->checksum.tcp;
5052                 else if (ip->protocol == IPPROTO_UDP)
5053                         opts[offset] |= info->checksum.udp;
5054                 else
5055                         WARN_ON_ONCE(1);
5056         }
5057 }
5058
5059 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5060                                       struct net_device *dev)
5061 {
5062         struct rtl8169_private *tp = netdev_priv(dev);
5063         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5064         struct TxDesc *txd = tp->TxDescArray + entry;
5065         void __iomem *ioaddr = tp->mmio_addr;
5066         struct device *d = &tp->pci_dev->dev;
5067         dma_addr_t mapping;
5068         u32 status, len;
5069         u32 opts[2];
5070         int frags;
5071
5072         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5073                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5074                 goto err_stop_0;
5075         }
5076
5077         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5078                 goto err_stop_0;
5079
5080         len = skb_headlen(skb);
5081         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5082         if (unlikely(dma_mapping_error(d, mapping))) {
5083                 if (net_ratelimit())
5084                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5085                 goto err_dma_0;
5086         }
5087
5088         tp->tx_skb[entry].len = len;
5089         txd->addr = cpu_to_le64(mapping);
5090
5091         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5092         opts[0] = DescOwn;
5093
5094         rtl8169_tso_csum(tp, skb, opts);
5095
5096         frags = rtl8169_xmit_frags(tp, skb, opts);
5097         if (frags < 0)
5098                 goto err_dma_1;
5099         else if (frags)
5100                 opts[0] |= FirstFrag;
5101         else {
5102                 opts[0] |= FirstFrag | LastFrag;
5103                 tp->tx_skb[entry].skb = skb;
5104         }
5105
5106         txd->opts2 = cpu_to_le32(opts[1]);
5107
5108         wmb();
5109
5110         /* Anti gcc 2.95.3 bugware (sic) */
5111         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5112         txd->opts1 = cpu_to_le32(status);
5113
5114         tp->cur_tx += frags + 1;
5115
5116         wmb();
5117
5118         RTL_W8(TxPoll, NPQ);
5119
5120         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5121                 netif_stop_queue(dev);
5122                 smp_rmb();
5123                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5124                         netif_wake_queue(dev);
5125         }
5126
5127         return NETDEV_TX_OK;
5128
5129 err_dma_1:
5130         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5131 err_dma_0:
5132         dev_kfree_skb(skb);
5133         dev->stats.tx_dropped++;
5134         return NETDEV_TX_OK;
5135
5136 err_stop_0:
5137         netif_stop_queue(dev);
5138         dev->stats.tx_dropped++;
5139         return NETDEV_TX_BUSY;
5140 }
5141
5142 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5143 {
5144         struct rtl8169_private *tp = netdev_priv(dev);
5145         struct pci_dev *pdev = tp->pci_dev;
5146         u16 pci_status, pci_cmd;
5147
5148         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5149         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5150
5151         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5152                   pci_cmd, pci_status);
5153
5154         /*
5155          * The recovery sequence below admits a very elaborated explanation:
5156          * - it seems to work;
5157          * - I did not see what else could be done;
5158          * - it makes iop3xx happy.
5159          *
5160          * Feel free to adjust to your needs.
5161          */
5162         if (pdev->broken_parity_status)
5163                 pci_cmd &= ~PCI_COMMAND_PARITY;
5164         else
5165                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5166
5167         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5168
5169         pci_write_config_word(pdev, PCI_STATUS,
5170                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5171                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5172                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5173
5174         /* The infamous DAC f*ckup only happens at boot time */
5175         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5176                 void __iomem *ioaddr = tp->mmio_addr;
5177
5178                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5179                 tp->cp_cmd &= ~PCIDAC;
5180                 RTL_W16(CPlusCmd, tp->cp_cmd);
5181                 dev->features &= ~NETIF_F_HIGHDMA;
5182         }
5183
5184         rtl8169_hw_reset(tp);
5185
5186         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5187 }
5188
5189 static void rtl8169_tx_interrupt(struct net_device *dev,
5190                                  struct rtl8169_private *tp,
5191                                  void __iomem *ioaddr)
5192 {
5193         unsigned int dirty_tx, tx_left;
5194
5195         dirty_tx = tp->dirty_tx;
5196         smp_rmb();
5197         tx_left = tp->cur_tx - dirty_tx;
5198
5199         while (tx_left > 0) {
5200                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5201                 struct ring_info *tx_skb = tp->tx_skb + entry;
5202                 u32 status;
5203
5204                 rmb();
5205                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5206                 if (status & DescOwn)
5207                         break;
5208
5209                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5210                                      tp->TxDescArray + entry);
5211                 if (status & LastFrag) {
5212                         dev->stats.tx_packets++;
5213                         dev->stats.tx_bytes += tx_skb->skb->len;
5214                         dev_kfree_skb(tx_skb->skb);
5215                         tx_skb->skb = NULL;
5216                 }
5217                 dirty_tx++;
5218                 tx_left--;
5219         }
5220
5221         if (tp->dirty_tx != dirty_tx) {
5222                 tp->dirty_tx = dirty_tx;
5223                 smp_wmb();
5224                 if (netif_queue_stopped(dev) &&
5225                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5226                         netif_wake_queue(dev);
5227                 }
5228                 /*
5229                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5230                  * too close. Let's kick an extra TxPoll request when a burst
5231                  * of start_xmit activity is detected (if it is not detected,
5232                  * it is slow enough). -- FR
5233                  */
5234                 smp_rmb();
5235                 if (tp->cur_tx != dirty_tx)
5236                         RTL_W8(TxPoll, NPQ);
5237         }
5238 }
5239
5240 static inline int rtl8169_fragmented_frame(u32 status)
5241 {
5242         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5243 }
5244
5245 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5246 {
5247         u32 status = opts1 & RxProtoMask;
5248
5249         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5250             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5251                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5252         else
5253                 skb_checksum_none_assert(skb);
5254 }
5255
5256 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5257                                            struct rtl8169_private *tp,
5258                                            int pkt_size,
5259                                            dma_addr_t addr)
5260 {
5261         struct sk_buff *skb;
5262         struct device *d = &tp->pci_dev->dev;
5263
5264         data = rtl8169_align(data);
5265         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5266         prefetch(data);
5267         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5268         if (skb)
5269                 memcpy(skb->data, data, pkt_size);
5270         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5271
5272         return skb;
5273 }
5274
5275 static int rtl8169_rx_interrupt(struct net_device *dev,
5276                                 struct rtl8169_private *tp,
5277                                 void __iomem *ioaddr, u32 budget)
5278 {
5279         unsigned int cur_rx, rx_left;
5280         unsigned int count;
5281
5282         cur_rx = tp->cur_rx;
5283         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5284         rx_left = min(rx_left, budget);
5285
5286         for (; rx_left > 0; rx_left--, cur_rx++) {
5287                 unsigned int entry = cur_rx % NUM_RX_DESC;
5288                 struct RxDesc *desc = tp->RxDescArray + entry;
5289                 u32 status;
5290
5291                 rmb();
5292                 status = le32_to_cpu(desc->opts1);
5293
5294                 if (status & DescOwn)
5295                         break;
5296                 if (unlikely(status & RxRES)) {
5297                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5298                                    status);
5299                         dev->stats.rx_errors++;
5300                         if (status & (RxRWT | RxRUNT))
5301                                 dev->stats.rx_length_errors++;
5302                         if (status & RxCRC)
5303                                 dev->stats.rx_crc_errors++;
5304                         if (status & RxFOVF) {
5305                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5306                                 dev->stats.rx_fifo_errors++;
5307                         }
5308                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5309                 } else {
5310                         struct sk_buff *skb;
5311                         dma_addr_t addr = le64_to_cpu(desc->addr);
5312                         int pkt_size = (status & 0x00001FFF) - 4;
5313
5314                         /*
5315                          * The driver does not support incoming fragmented
5316                          * frames. They are seen as a symptom of over-mtu
5317                          * sized frames.
5318                          */
5319                         if (unlikely(rtl8169_fragmented_frame(status))) {
5320                                 dev->stats.rx_dropped++;
5321                                 dev->stats.rx_length_errors++;
5322                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5323                                 continue;
5324                         }
5325
5326                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5327                                                   tp, pkt_size, addr);
5328                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5329                         if (!skb) {
5330                                 dev->stats.rx_dropped++;
5331                                 continue;
5332                         }
5333
5334                         rtl8169_rx_csum(skb, status);
5335                         skb_put(skb, pkt_size);
5336                         skb->protocol = eth_type_trans(skb, dev);
5337
5338                         rtl8169_rx_vlan_tag(desc, skb);
5339
5340                         napi_gro_receive(&tp->napi, skb);
5341
5342                         dev->stats.rx_bytes += pkt_size;
5343                         dev->stats.rx_packets++;
5344                 }
5345
5346                 /* Work around for AMD plateform. */
5347                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5348                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5349                         desc->opts2 = 0;
5350                         cur_rx++;
5351                 }
5352         }
5353
5354         count = cur_rx - tp->cur_rx;
5355         tp->cur_rx = cur_rx;
5356
5357         tp->dirty_rx += count;
5358
5359         return count;
5360 }
5361
5362 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5363 {
5364         struct net_device *dev = dev_instance;
5365         struct rtl8169_private *tp = netdev_priv(dev);
5366         void __iomem *ioaddr = tp->mmio_addr;
5367         int handled = 0;
5368         int status;
5369
5370         /* loop handling interrupts until we have no new ones or
5371          * we hit a invalid/hotplug case.
5372          */
5373         status = RTL_R16(IntrStatus);
5374         while (status && status != 0xffff) {
5375                 handled = 1;
5376
5377                 /* Handle all of the error cases first. These will reset
5378                  * the chip, so just exit the loop.
5379                  */
5380                 if (unlikely(!netif_running(dev))) {
5381                         rtl8169_hw_reset(tp);
5382                         break;
5383                 }
5384
5385                 if (unlikely(status & RxFIFOOver)) {
5386                         switch (tp->mac_version) {
5387                         /* Work around for rx fifo overflow */
5388                         case RTL_GIGA_MAC_VER_11:
5389                         case RTL_GIGA_MAC_VER_22:
5390                         case RTL_GIGA_MAC_VER_26:
5391                                 netif_stop_queue(dev);
5392                                 rtl8169_tx_timeout(dev);
5393                                 goto done;
5394                         /* Testers needed. */
5395                         case RTL_GIGA_MAC_VER_17:
5396                         case RTL_GIGA_MAC_VER_19:
5397                         case RTL_GIGA_MAC_VER_20:
5398                         case RTL_GIGA_MAC_VER_21:
5399                         case RTL_GIGA_MAC_VER_23:
5400                         case RTL_GIGA_MAC_VER_24:
5401                         case RTL_GIGA_MAC_VER_27:
5402                         case RTL_GIGA_MAC_VER_28:
5403                         case RTL_GIGA_MAC_VER_31:
5404                         /* Experimental science. Pktgen proof. */
5405                         case RTL_GIGA_MAC_VER_12:
5406                         case RTL_GIGA_MAC_VER_25:
5407                                 if (status == RxFIFOOver)
5408                                         goto done;
5409                                 break;
5410                         default:
5411                                 break;
5412                         }
5413                 }
5414
5415                 if (unlikely(status & SYSErr)) {
5416                         rtl8169_pcierr_interrupt(dev);
5417                         break;
5418                 }
5419
5420                 if (status & LinkChg)
5421                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5422
5423                 /* We need to see the lastest version of tp->intr_mask to
5424                  * avoid ignoring an MSI interrupt and having to wait for
5425                  * another event which may never come.
5426                  */
5427                 smp_rmb();
5428                 if (status & tp->intr_mask & tp->napi_event) {
5429                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5430                         tp->intr_mask = ~tp->napi_event;
5431
5432                         if (likely(napi_schedule_prep(&tp->napi)))
5433                                 __napi_schedule(&tp->napi);
5434                         else
5435                                 netif_info(tp, intr, dev,
5436                                            "interrupt %04x in poll\n", status);
5437                 }
5438
5439                 /* We only get a new MSI interrupt when all active irq
5440                  * sources on the chip have been acknowledged. So, ack
5441                  * everything we've seen and check if new sources have become
5442                  * active to avoid blocking all interrupts from the chip.
5443                  */
5444                 RTL_W16(IntrStatus,
5445                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5446                 status = RTL_R16(IntrStatus);
5447         }
5448 done:
5449         return IRQ_RETVAL(handled);
5450 }
5451
5452 static int rtl8169_poll(struct napi_struct *napi, int budget)
5453 {
5454         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5455         struct net_device *dev = tp->dev;
5456         void __iomem *ioaddr = tp->mmio_addr;
5457         int work_done;
5458
5459         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5460         rtl8169_tx_interrupt(dev, tp, ioaddr);
5461
5462         if (work_done < budget) {
5463                 napi_complete(napi);
5464
5465                 /* We need for force the visibility of tp->intr_mask
5466                  * for other CPUs, as we can loose an MSI interrupt
5467                  * and potentially wait for a retransmit timeout if we don't.
5468                  * The posted write to IntrMask is safe, as it will
5469                  * eventually make it to the chip and we won't loose anything
5470                  * until it does.
5471                  */
5472                 tp->intr_mask = 0xffff;
5473                 wmb();
5474                 RTL_W16(IntrMask, tp->intr_event);
5475         }
5476
5477         return work_done;
5478 }
5479
5480 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5481 {
5482         struct rtl8169_private *tp = netdev_priv(dev);
5483
5484         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5485                 return;
5486
5487         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5488         RTL_W32(RxMissed, 0);
5489 }
5490
5491 static void rtl8169_down(struct net_device *dev)
5492 {
5493         struct rtl8169_private *tp = netdev_priv(dev);
5494         void __iomem *ioaddr = tp->mmio_addr;
5495
5496         del_timer_sync(&tp->timer);
5497
5498         netif_stop_queue(dev);
5499
5500         napi_disable(&tp->napi);
5501
5502         spin_lock_irq(&tp->lock);
5503
5504         rtl8169_hw_reset(tp);
5505         /*
5506          * At this point device interrupts can not be enabled in any function,
5507          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5508          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5509          */
5510         rtl8169_rx_missed(dev, ioaddr);
5511
5512         spin_unlock_irq(&tp->lock);
5513
5514         synchronize_irq(dev->irq);
5515
5516         /* Give a racing hard_start_xmit a few cycles to complete. */
5517         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5518
5519         rtl8169_tx_clear(tp);
5520
5521         rtl8169_rx_clear(tp);
5522
5523         rtl_pll_power_down(tp);
5524 }
5525
5526 static int rtl8169_close(struct net_device *dev)
5527 {
5528         struct rtl8169_private *tp = netdev_priv(dev);
5529         struct pci_dev *pdev = tp->pci_dev;
5530
5531         pm_runtime_get_sync(&pdev->dev);
5532
5533         /* Update counters before going down */
5534         rtl8169_update_counters(dev);
5535
5536         rtl8169_down(dev);
5537
5538         free_irq(dev->irq, dev);
5539
5540         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5541                           tp->RxPhyAddr);
5542         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5543                           tp->TxPhyAddr);
5544         tp->TxDescArray = NULL;
5545         tp->RxDescArray = NULL;
5546
5547         pm_runtime_put_sync(&pdev->dev);
5548
5549         return 0;
5550 }
5551
5552 static void rtl_set_rx_mode(struct net_device *dev)
5553 {
5554         struct rtl8169_private *tp = netdev_priv(dev);
5555         void __iomem *ioaddr = tp->mmio_addr;
5556         unsigned long flags;
5557         u32 mc_filter[2];       /* Multicast hash filter */
5558         int rx_mode;
5559         u32 tmp = 0;
5560
5561         if (dev->flags & IFF_PROMISC) {
5562                 /* Unconditionally log net taps. */
5563                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5564                 rx_mode =
5565                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5566                     AcceptAllPhys;
5567                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5568         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5569                    (dev->flags & IFF_ALLMULTI)) {
5570                 /* Too many to filter perfectly -- accept all multicasts. */
5571                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5572                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5573         } else {
5574                 struct netdev_hw_addr *ha;
5575
5576                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5577                 mc_filter[1] = mc_filter[0] = 0;
5578                 netdev_for_each_mc_addr(ha, dev) {
5579                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5580                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5581                         rx_mode |= AcceptMulticast;
5582                 }
5583         }
5584
5585         spin_lock_irqsave(&tp->lock, flags);
5586
5587         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5588
5589         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5590                 u32 data = mc_filter[0];
5591
5592                 mc_filter[0] = swab32(mc_filter[1]);
5593                 mc_filter[1] = swab32(data);
5594         }
5595
5596         RTL_W32(MAR0 + 4, mc_filter[1]);
5597         RTL_W32(MAR0 + 0, mc_filter[0]);
5598
5599         RTL_W32(RxConfig, tmp);
5600
5601         spin_unlock_irqrestore(&tp->lock, flags);
5602 }
5603
5604 /**
5605  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5606  *  @dev: The Ethernet Device to get statistics for
5607  *
5608  *  Get TX/RX statistics for rtl8169
5609  */
5610 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5611 {
5612         struct rtl8169_private *tp = netdev_priv(dev);
5613         void __iomem *ioaddr = tp->mmio_addr;
5614         unsigned long flags;
5615
5616         if (netif_running(dev)) {
5617                 spin_lock_irqsave(&tp->lock, flags);
5618                 rtl8169_rx_missed(dev, ioaddr);
5619                 spin_unlock_irqrestore(&tp->lock, flags);
5620         }
5621
5622         return &dev->stats;
5623 }
5624
5625 static void rtl8169_net_suspend(struct net_device *dev)
5626 {
5627         struct rtl8169_private *tp = netdev_priv(dev);
5628
5629         if (!netif_running(dev))
5630                 return;
5631
5632         rtl_pll_power_down(tp);
5633
5634         netif_device_detach(dev);
5635         netif_stop_queue(dev);
5636 }
5637
5638 #ifdef CONFIG_PM
5639
5640 static int rtl8169_suspend(struct device *device)
5641 {
5642         struct pci_dev *pdev = to_pci_dev(device);
5643         struct net_device *dev = pci_get_drvdata(pdev);
5644
5645         rtl8169_net_suspend(dev);
5646
5647         return 0;
5648 }
5649
5650 static void __rtl8169_resume(struct net_device *dev)
5651 {
5652         struct rtl8169_private *tp = netdev_priv(dev);
5653
5654         netif_device_attach(dev);
5655
5656         rtl_pll_power_up(tp);
5657
5658         rtl8169_schedule_work(dev, rtl8169_reset_task);
5659 }
5660
5661 static int rtl8169_resume(struct device *device)
5662 {
5663         struct pci_dev *pdev = to_pci_dev(device);
5664         struct net_device *dev = pci_get_drvdata(pdev);
5665         struct rtl8169_private *tp = netdev_priv(dev);
5666
5667         rtl8169_init_phy(dev, tp);
5668
5669         if (netif_running(dev))
5670                 __rtl8169_resume(dev);
5671
5672         return 0;
5673 }
5674
5675 static int rtl8169_runtime_suspend(struct device *device)
5676 {
5677         struct pci_dev *pdev = to_pci_dev(device);
5678         struct net_device *dev = pci_get_drvdata(pdev);
5679         struct rtl8169_private *tp = netdev_priv(dev);
5680
5681         if (!tp->TxDescArray)
5682                 return 0;
5683
5684         spin_lock_irq(&tp->lock);
5685         tp->saved_wolopts = __rtl8169_get_wol(tp);
5686         __rtl8169_set_wol(tp, WAKE_ANY);
5687         spin_unlock_irq(&tp->lock);
5688
5689         rtl8169_net_suspend(dev);
5690
5691         return 0;
5692 }
5693
5694 static int rtl8169_runtime_resume(struct device *device)
5695 {
5696         struct pci_dev *pdev = to_pci_dev(device);
5697         struct net_device *dev = pci_get_drvdata(pdev);
5698         struct rtl8169_private *tp = netdev_priv(dev);
5699
5700         if (!tp->TxDescArray)
5701                 return 0;
5702
5703         spin_lock_irq(&tp->lock);
5704         __rtl8169_set_wol(tp, tp->saved_wolopts);
5705         tp->saved_wolopts = 0;
5706         spin_unlock_irq(&tp->lock);
5707
5708         rtl8169_init_phy(dev, tp);
5709
5710         __rtl8169_resume(dev);
5711
5712         return 0;
5713 }
5714
5715 static int rtl8169_runtime_idle(struct device *device)
5716 {
5717         struct pci_dev *pdev = to_pci_dev(device);
5718         struct net_device *dev = pci_get_drvdata(pdev);
5719         struct rtl8169_private *tp = netdev_priv(dev);
5720
5721         return tp->TxDescArray ? -EBUSY : 0;
5722 }
5723
5724 static const struct dev_pm_ops rtl8169_pm_ops = {
5725         .suspend                = rtl8169_suspend,
5726         .resume                 = rtl8169_resume,
5727         .freeze                 = rtl8169_suspend,
5728         .thaw                   = rtl8169_resume,
5729         .poweroff               = rtl8169_suspend,
5730         .restore                = rtl8169_resume,
5731         .runtime_suspend        = rtl8169_runtime_suspend,
5732         .runtime_resume         = rtl8169_runtime_resume,
5733         .runtime_idle           = rtl8169_runtime_idle,
5734 };
5735
5736 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5737
5738 #else /* !CONFIG_PM */
5739
5740 #define RTL8169_PM_OPS  NULL
5741
5742 #endif /* !CONFIG_PM */
5743
5744 static void rtl_shutdown(struct pci_dev *pdev)
5745 {
5746         struct net_device *dev = pci_get_drvdata(pdev);
5747         struct rtl8169_private *tp = netdev_priv(dev);
5748         void __iomem *ioaddr = tp->mmio_addr;
5749
5750         rtl8169_net_suspend(dev);
5751
5752         /* Restore original MAC address */
5753         rtl_rar_set(tp, dev->perm_addr);
5754
5755         spin_lock_irq(&tp->lock);
5756
5757         rtl8169_hw_reset(tp);
5758
5759         spin_unlock_irq(&tp->lock);
5760
5761         if (system_state == SYSTEM_POWER_OFF) {
5762                 /* WoL fails with 8168b when the receiver is disabled. */
5763                 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5764                      tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5765                      tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5766                     (tp->features & RTL_FEATURE_WOL)) {
5767                         pci_clear_master(pdev);
5768
5769                         RTL_W8(ChipCmd, CmdRxEnb);
5770                         /* PCI commit */
5771                         RTL_R8(ChipCmd);
5772                 }
5773
5774                 pci_wake_from_d3(pdev, true);
5775                 pci_set_power_state(pdev, PCI_D3hot);
5776         }
5777 }
5778
5779 static struct pci_driver rtl8169_pci_driver = {
5780         .name           = MODULENAME,
5781         .id_table       = rtl8169_pci_tbl,
5782         .probe          = rtl8169_init_one,
5783         .remove         = __devexit_p(rtl8169_remove_one),
5784         .shutdown       = rtl_shutdown,
5785         .driver.pm      = RTL8169_PM_OPS,
5786 };
5787
5788 static int __init rtl8169_init_module(void)
5789 {
5790         return pci_register_driver(&rtl8169_pci_driver);
5791 }
5792
5793 static void __exit rtl8169_cleanup_module(void)
5794 {
5795         pci_unregister_driver(&rtl8169_pci_driver);
5796 }
5797
5798 module_init(rtl8169_init_module);
5799 module_exit(rtl8169_cleanup_module);