drivers/net/phy/dp83640.c

   1 /*
   2  * Driver for the National Semiconductor DP83640 PHYTER
   3  *
   4  * Copyright (C) 2010 OMICRON electronics GmbH
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/ethtool.h>
  21 #include <linux/kernel.h>
  22 #include <linux/list.h>
  23 #include <linux/mii.h>
  24 #include <linux/module.h>
  25 #include <linux/net_tstamp.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/phy.h>
  28 #include <linux/ptp_classify.h>
  29 #include <linux/ptp_clock_kernel.h>
  30
  31 #include "dp83640_reg.h"
  32
  33 #define DP83640_PHY_ID  0x20005ce1
  34 #define PAGESEL         0x13
  35 #define LAYER4          0x02
  36 #define LAYER2          0x01
  37 #define MAX_RXTS        64
  38 #define N_EXT_TS        1
  39 #define PSF_PTPVER      2
  40 #define PSF_EVNT        0x4000
  41 #define PSF_RX          0x2000
  42 #define PSF_TX          0x1000
  43 #define EXT_EVENT       1
  44 #define EXT_GPIO        1
  45 #define CAL_EVENT       2
  46 #define CAL_GPIO        9
  47 #define CAL_TRIGGER     2
  48
  49 /* phyter seems to miss the mark by 16 ns */
  50 #define ADJTIME_FIX     16
  51
  52 #if defined(__BIG_ENDIAN)
  53 #define ENDIAN_FLAG     0
  54 #elif defined(__LITTLE_ENDIAN)
  55 #define ENDIAN_FLAG     PSF_ENDIAN
  56 #endif
  57
  58 #define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
  59
  60 struct phy_rxts {
  61         u16 ns_lo;   /* ns[15:0] */
  62         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  63         u16 sec_lo;  /* sec[15:0] */
  64         u16 sec_hi;  /* sec[31:16] */
  65         u16 seqid;   /* sequenceId[15:0] */
  66         u16 msgtype; /* messageType[3:0], hash[11:0] */
  67 };
  68
  69 struct phy_txts {
  70         u16 ns_lo;   /* ns[15:0] */
  71         u16 ns_hi;   /* overflow[1:0], ns[29:16] */
  72         u16 sec_lo;  /* sec[15:0] */
  73         u16 sec_hi;  /* sec[31:16] */
  74 };
  75
  76 struct rxts {
  77         struct list_head list;
  78         unsigned long tmo;
  79         u64 ns;
  80         u16 seqid;
  81         u8  msgtype;
  82         u16 hash;
  83 };
  84
  85 struct dp83640_clock;
  86
  87 struct dp83640_private {
  88         struct list_head list;
  89         struct dp83640_clock *clock;
  90         struct phy_device *phydev;
  91         struct work_struct ts_work;
  92         int hwts_tx_en;
  93         int hwts_rx_en;
  94         int layer;
  95         int version;
  96         /* remember state of cfg0 during calibration */
  97         int cfg0;
  98         /* remember the last event time stamp */
  99         struct phy_txts edata;
 100         /* list of rx timestamps */
 101         struct list_head rxts;
 102         struct list_head rxpool;
 103         struct rxts rx_pool_data[MAX_RXTS];
 104         /* protects above three fields from concurrent access */
 105         spinlock_t rx_lock;
 106         /* queues of incoming and outgoing packets */
 107         struct sk_buff_head rx_queue;
 108         struct sk_buff_head tx_queue;
 109 };
 110
 111 struct dp83640_clock {
 112         /* keeps the instance in the 'phyter_clocks' list */
 113         struct list_head list;
 114         /* we create one clock instance per MII bus */
 115         struct mii_bus *bus;
 116         /* protects extended registers from concurrent access */
 117         struct mutex extreg_lock;
 118         /* remembers which page was last selected */
 119         int page;
 120         /* our advertised capabilities */
 121         struct ptp_clock_info caps;
 122         /* protects the three fields below from concurrent access */
 123         struct mutex clock_lock;
 124         /* the one phyter from which we shall read */
 125         struct dp83640_private *chosen;
 126         /* list of the other attached phyters, not chosen */
 127         struct list_head phylist;
 128         /* reference to our PTP hardware clock */
 129         struct ptp_clock *ptp_clock;
 130 };
 131
 132 /* globals */
 133
 134 static int chosen_phy = -1;
 135 static ushort cal_gpio = 4;
 136
 137 module_param(chosen_phy, int, 0444);
 138 module_param(cal_gpio, ushort, 0444);
 139
 140 MODULE_PARM_DESC(chosen_phy, \
 141         "The address of the PHY to use for the ancillary clock features");
 142 MODULE_PARM_DESC(cal_gpio, \
 143         "Which GPIO line to use for synchronizing multiple PHYs");
 144
 145 /* a list of clocks and a mutex to protect it */
 146 static LIST_HEAD(phyter_clocks);
 147 static DEFINE_MUTEX(phyter_clocks_lock);
 148
 149 static void rx_timestamp_work(struct work_struct *work);
 150
 151 /* extended register access functions */
 152
 153 #define BROADCAST_ADDR 31
 154
 155 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
 156 {
 157         return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
 158 }
 159
 160 /* Caller must hold extreg_lock. */
 161 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
 162 {
 163         struct dp83640_private *dp83640 = phydev->priv;
 164         int val;
 165
 166         if (dp83640->clock->page != page) {
 167                 broadcast_write(phydev->bus, PAGESEL, page);
 168                 dp83640->clock->page = page;
 169         }
 170         val = phy_read(phydev, regnum);
 171
 172         return val;
 173 }
 174
 175 /* Caller must hold extreg_lock. */
 176 static void ext_write(int broadcast, struct phy_device *phydev,
 177                       int page, u32 regnum, u16 val)
 178 {
 179         struct dp83640_private *dp83640 = phydev->priv;
 180
 181         if (dp83640->clock->page != page) {
 182                 broadcast_write(phydev->bus, PAGESEL, page);
 183                 dp83640->clock->page = page;
 184         }
 185         if (broadcast)
 186                 broadcast_write(phydev->bus, regnum, val);
 187         else
 188                 phy_write(phydev, regnum, val);
 189 }
 190
 191 /* Caller must hold extreg_lock. */
 192 static int tdr_write(int bc, struct phy_device *dev,
 193                      const struct timespec *ts, u16 cmd)
 194 {
 195         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0]  */
 196         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);   /* ns[31:16] */
 197         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
 198         ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);    /* sec[31:16]*/
 199
 200         ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
 201
 202         return 0;
 203 }
 204
 205 /* convert phy timestamps into driver timestamps */
 206
 207 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
 208 {
 209         u32 sec;
 210
 211         sec = p->sec_lo;
 212         sec |= p->sec_hi << 16;
 213
 214         rxts->ns = p->ns_lo;
 215         rxts->ns |= (p->ns_hi & 0x3fff) << 16;
 216         rxts->ns += ((u64)sec) * 1000000000ULL;
 217         rxts->seqid = p->seqid;
 218         rxts->msgtype = (p->msgtype >> 12) & 0xf;
 219         rxts->hash = p->msgtype & 0x0fff;
 220         rxts->tmo = jiffies + 2;
 221 }
 222
 223 static u64 phy2txts(struct phy_txts *p)
 224 {
 225         u64 ns;
 226         u32 sec;
 227
 228         sec = p->sec_lo;
 229         sec |= p->sec_hi << 16;
 230
 231         ns = p->ns_lo;
 232         ns |= (p->ns_hi & 0x3fff) << 16;
 233         ns += ((u64)sec) * 1000000000ULL;
 234
 235         return ns;
 236 }
 237
 238 /* ptp clock methods */
 239
 240 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
 241 {
 242         struct dp83640_clock *clock =
 243                 container_of(ptp, struct dp83640_clock, caps);
 244         struct phy_device *phydev = clock->chosen->phydev;
 245         u64 rate;
 246         int neg_adj = 0;
 247         u16 hi, lo;
 248
 249         if (ppb < 0) {
 250                 neg_adj = 1;
 251                 ppb = -ppb;
 252         }
 253         rate = ppb;
 254         rate <<= 26;
 255         rate = div_u64(rate, 1953125);
 256
 257         hi = (rate >> 16) & PTP_RATE_HI_MASK;
 258         if (neg_adj)
 259                 hi |= PTP_RATE_DIR;
 260
 261         lo = rate & 0xffff;
 262
 263         mutex_lock(&clock->extreg_lock);
 264
 265         ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
 266         ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
 267
 268         mutex_unlock(&clock->extreg_lock);
 269
 270         return 0;
 271 }
 272
 273 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
 274 {
 275         struct dp83640_clock *clock =
 276                 container_of(ptp, struct dp83640_clock, caps);
 277         struct phy_device *phydev = clock->chosen->phydev;
 278         struct timespec ts;
 279         int err;
 280
 281         delta += ADJTIME_FIX;
 282
 283         ts = ns_to_timespec(delta);
 284
 285         mutex_lock(&clock->extreg_lock);
 286
 287         err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
 288
 289         mutex_unlock(&clock->extreg_lock);
 290
 291         return err;
 292 }
 293
 294 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
 295 {
 296         struct dp83640_clock *clock =
 297                 container_of(ptp, struct dp83640_clock, caps);
 298         struct phy_device *phydev = clock->chosen->phydev;
 299         unsigned int val[4];
 300
 301         mutex_lock(&clock->extreg_lock);
 302
 303         ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
 304
 305         val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
 306         val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
 307         val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
 308         val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
 309
 310         mutex_unlock(&clock->extreg_lock);
 311
 312         ts->tv_nsec = val[0] | (val[1] << 16);
 313         ts->tv_sec  = val[2] | (val[3] << 16);
 314
 315         return 0;
 316 }
 317
 318 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
 319                                const struct timespec *ts)
 320 {
 321         struct dp83640_clock *clock =
 322                 container_of(ptp, struct dp83640_clock, caps);
 323         struct phy_device *phydev = clock->chosen->phydev;
 324         int err;
 325
 326         mutex_lock(&clock->extreg_lock);
 327
 328         err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
 329
 330         mutex_unlock(&clock->extreg_lock);
 331
 332         return err;
 333 }
 334
 335 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
 336                               struct ptp_clock_request *rq, int on)
 337 {
 338         struct dp83640_clock *clock =
 339                 container_of(ptp, struct dp83640_clock, caps);
 340         struct phy_device *phydev = clock->chosen->phydev;
 341         u16 evnt;
 342
 343         switch (rq->type) {
 344         case PTP_CLK_REQ_EXTTS:
 345                 if (rq->extts.index != 0)
 346                         return -EINVAL;
 347                 evnt = EVNT_WR | (EXT_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 348                 if (on) {
 349                         evnt |= (EXT_GPIO & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 350                         evnt |= EVNT_RISE;
 351                 }
 352                 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
 353                 return 0;
 354         default:
 355                 break;
 356         }
 357
 358         return -EOPNOTSUPP;
 359 }
 360
 361 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
 362 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
 363
 364 static void enable_status_frames(struct phy_device *phydev, bool on)
 365 {
 366         u16 cfg0 = 0, ver;
 367
 368         if (on)
 369                 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
 370
 371         ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
 372
 373         ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
 374         ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
 375
 376         if (!phydev->attached_dev) {
 377                 pr_warning("dp83640: expected to find an attached netdevice\n");
 378                 return;
 379         }
 380
 381         if (on) {
 382                 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
 383                         pr_warning("dp83640: failed to add mc address\n");
 384         } else {
 385                 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
 386                         pr_warning("dp83640: failed to delete mc address\n");
 387         }
 388 }
 389
 390 static bool is_status_frame(struct sk_buff *skb, int type)
 391 {
 392         struct ethhdr *h = eth_hdr(skb);
 393
 394         if (PTP_CLASS_V2_L2 == type &&
 395             !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
 396                 return true;
 397         else
 398                 return false;
 399 }
 400
 401 static int expired(struct rxts *rxts)
 402 {
 403         return time_after(jiffies, rxts->tmo);
 404 }
 405
 406 /* Caller must hold rx_lock. */
 407 static void prune_rx_ts(struct dp83640_private *dp83640)
 408 {
 409         struct list_head *this, *next;
 410         struct rxts *rxts;
 411
 412         list_for_each_safe(this, next, &dp83640->rxts) {
 413                 rxts = list_entry(this, struct rxts, list);
 414                 if (expired(rxts)) {
 415                         list_del_init(&rxts->list);
 416                         list_add(&rxts->list, &dp83640->rxpool);
 417                 }
 418         }
 419 }
 420
 421 /* synchronize the phyters so they act as one clock */
 422
 423 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
 424 {
 425         int val;
 426         phy_write(phydev, PAGESEL, 0);
 427         val = phy_read(phydev, PHYCR2);
 428         if (on)
 429                 val |= BC_WRITE;
 430         else
 431                 val &= ~BC_WRITE;
 432         phy_write(phydev, PHYCR2, val);
 433         phy_write(phydev, PAGESEL, init_page);
 434 }
 435
 436 static void recalibrate(struct dp83640_clock *clock)
 437 {
 438         s64 now, diff;
 439         struct phy_txts event_ts;
 440         struct timespec ts;
 441         struct list_head *this;
 442         struct dp83640_private *tmp;
 443         struct phy_device *master = clock->chosen->phydev;
 444         u16 cfg0, evnt, ptp_trig, trigger, val;
 445
 446         trigger = CAL_TRIGGER;
 447
 448         mutex_lock(&clock->extreg_lock);
 449
 450         /*
 451          * enable broadcast, disable status frames, enable ptp clock
 452          */
 453         list_for_each(this, &clock->phylist) {
 454                 tmp = list_entry(this, struct dp83640_private, list);
 455                 enable_broadcast(tmp->phydev, clock->page, 1);
 456                 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
 457                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
 458                 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
 459         }
 460         enable_broadcast(master, clock->page, 1);
 461         cfg0 = ext_read(master, PAGE5, PSF_CFG0);
 462         ext_write(0, master, PAGE5, PSF_CFG0, 0);
 463         ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
 464
 465         /*
 466          * enable an event timestamp
 467          */
 468         evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
 469         evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
 470         evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
 471
 472         list_for_each(this, &clock->phylist) {
 473                 tmp = list_entry(this, struct dp83640_private, list);
 474                 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
 475         }
 476         ext_write(0, master, PAGE5, PTP_EVNT, evnt);
 477
 478         /*
 479          * configure a trigger
 480          */
 481         ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
 482         ptp_trig |= (trigger  & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
 483         ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
 484         ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
 485
 486         /* load trigger */
 487         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 488         val |= TRIG_LOAD;
 489         ext_write(0, master, PAGE4, PTP_CTL, val);
 490
 491         /* enable trigger */
 492         val &= ~TRIG_LOAD;
 493         val |= TRIG_EN;
 494         ext_write(0, master, PAGE4, PTP_CTL, val);
 495
 496         /* disable trigger */
 497         val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
 498         val |= TRIG_DIS;
 499         ext_write(0, master, PAGE4, PTP_CTL, val);
 500
 501         /*
 502          * read out and correct offsets
 503          */
 504         val = ext_read(master, PAGE4, PTP_STS);
 505         pr_info("master PTP_STS  0x%04hx", val);
 506         val = ext_read(master, PAGE4, PTP_ESTS);
 507         pr_info("master PTP_ESTS 0x%04hx", val);
 508         event_ts.ns_lo  = ext_read(master, PAGE4, PTP_EDATA);
 509         event_ts.ns_hi  = ext_read(master, PAGE4, PTP_EDATA);
 510         event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
 511         event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
 512         now = phy2txts(&event_ts);
 513
 514         list_for_each(this, &clock->phylist) {
 515                 tmp = list_entry(this, struct dp83640_private, list);
 516                 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
 517                 pr_info("slave  PTP_STS  0x%04hx", val);
 518                 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
 519                 pr_info("slave  PTP_ESTS 0x%04hx", val);
 520                 event_ts.ns_lo  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 521                 event_ts.ns_hi  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 522                 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 523                 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
 524                 diff = now - (s64) phy2txts(&event_ts);
 525                 pr_info("slave offset %lld nanoseconds\n", diff);
 526                 diff += ADJTIME_FIX;
 527                 ts = ns_to_timespec(diff);
 528                 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
 529         }
 530
 531         /*
 532          * restore status frames
 533          */
 534         list_for_each(this, &clock->phylist) {
 535                 tmp = list_entry(this, struct dp83640_private, list);
 536                 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
 537         }
 538         ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
 539
 540         mutex_unlock(&clock->extreg_lock);
 541 }
 542
 543 /* time stamping methods */
 544
 545 static int decode_evnt(struct dp83640_private *dp83640,
 546                        void *data, u16 ests)
 547 {
 548         struct phy_txts *phy_txts;
 549         struct ptp_clock_event event;
 550         int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
 551         u16 ext_status = 0;
 552
 553         if (ests & MULT_EVNT) {
 554                 ext_status = *(u16 *) data;
 555                 data += sizeof(ext_status);
 556         }
 557
 558         phy_txts = data;
 559
 560         switch (words) { /* fall through in every case */
 561         case 3:
 562                 dp83640->edata.sec_hi = phy_txts->sec_hi;
 563         case 2:
 564                 dp83640->edata.sec_lo = phy_txts->sec_lo;
 565         case 1:
 566                 dp83640->edata.ns_hi = phy_txts->ns_hi;
 567         case 0:
 568                 dp83640->edata.ns_lo = phy_txts->ns_lo;
 569         }
 570
 571         event.type = PTP_CLOCK_EXTTS;
 572         event.index = 0;
 573         event.timestamp = phy2txts(&dp83640->edata);
 574
 575         ptp_clock_event(dp83640->clock->ptp_clock, &event);
 576
 577         words = ext_status ? words + 2 : words + 1;
 578         return words * sizeof(u16);
 579 }
 580
 581 static void decode_rxts(struct dp83640_private *dp83640,
 582                         struct phy_rxts *phy_rxts)
 583 {
 584         struct rxts *rxts;
 585         unsigned long flags;
 586
 587         spin_lock_irqsave(&dp83640->rx_lock, flags);
 588
 589         prune_rx_ts(dp83640);
 590
 591         if (list_empty(&dp83640->rxpool)) {
 592                 pr_debug("dp83640: rx timestamp pool is empty\n");
 593                 goto out;
 594         }
 595         rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
 596         list_del_init(&rxts->list);
 597         phy2rxts(phy_rxts, rxts);
 598         list_add_tail(&rxts->list, &dp83640->rxts);
 599 out:
 600         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
 601 }
 602
 603 static void decode_txts(struct dp83640_private *dp83640,
 604                         struct phy_txts *phy_txts)
 605 {
 606         struct skb_shared_hwtstamps shhwtstamps;
 607         struct sk_buff *skb;
 608         u64 ns;
 609
 610         /* We must already have the skb that triggered this. */
 611
 612         skb = skb_dequeue(&dp83640->tx_queue);
 613
 614         if (!skb) {
 615                 pr_debug("dp83640: have timestamp but tx_queue empty\n");
 616                 return;
 617         }
 618         ns = phy2txts(phy_txts);
 619         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 620         shhwtstamps.hwtstamp = ns_to_ktime(ns);
 621         skb_complete_tx_timestamp(skb, &shhwtstamps);
 622 }
 623
 624 static void decode_status_frame(struct dp83640_private *dp83640,
 625                                 struct sk_buff *skb)
 626 {
 627         struct phy_rxts *phy_rxts;
 628         struct phy_txts *phy_txts;
 629         u8 *ptr;
 630         int len, size;
 631         u16 ests, type;
 632
 633         ptr = skb->data + 2;
 634
 635         for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
 636
 637                 type = *(u16 *)ptr;
 638                 ests = type & 0x0fff;
 639                 type = type & 0xf000;
 640                 len -= sizeof(type);
 641                 ptr += sizeof(type);
 642
 643                 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
 644
 645                         phy_rxts = (struct phy_rxts *) ptr;
 646                         decode_rxts(dp83640, phy_rxts);
 647                         size = sizeof(*phy_rxts);
 648
 649                 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
 650
 651                         phy_txts = (struct phy_txts *) ptr;
 652                         decode_txts(dp83640, phy_txts);
 653                         size = sizeof(*phy_txts);
 654
 655                 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
 656
 657                         size = decode_evnt(dp83640, ptr, ests);
 658
 659                 } else {
 660                         size = 0;
 661                         break;
 662                 }
 663                 ptr += size;
 664         }
 665 }
 666
 667 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
 668 {
 669         u16 *seqid;
 670         unsigned int offset;
 671         u8 *msgtype, *data = skb_mac_header(skb);
 672
 673         /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
 674
 675         switch (type) {
 676         case PTP_CLASS_V1_IPV4:
 677         case PTP_CLASS_V2_IPV4:
 678                 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 679                 break;
 680         case PTP_CLASS_V1_IPV6:
 681         case PTP_CLASS_V2_IPV6:
 682                 offset = OFF_PTP6;
 683                 break;
 684         case PTP_CLASS_V2_L2:
 685                 offset = ETH_HLEN;
 686                 break;
 687         case PTP_CLASS_V2_VLAN:
 688                 offset = ETH_HLEN + VLAN_HLEN;
 689                 break;
 690         default:
 691                 return 0;
 692         }
 693
 694         if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
 695                 return 0;
 696
 697         if (unlikely(type & PTP_CLASS_V1))
 698                 msgtype = data + offset + OFF_PTP_CONTROL;
 699         else
 700                 msgtype = data + offset;
 701
 702         seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 703
 704         return (rxts->msgtype == (*msgtype & 0xf) &&
 705                 rxts->seqid   == ntohs(*seqid));
 706 }
 707
 708 static void dp83640_free_clocks(void)
 709 {
 710         struct dp83640_clock *clock;
 711         struct list_head *this, *next;
 712
 713         mutex_lock(&phyter_clocks_lock);
 714
 715         list_for_each_safe(this, next, &phyter_clocks) {
 716                 clock = list_entry(this, struct dp83640_clock, list);
 717                 if (!list_empty(&clock->phylist)) {
 718                         pr_warning("phy list non-empty while unloading");
 719                         BUG();
 720                 }
 721                 list_del(&clock->list);
 722                 mutex_destroy(&clock->extreg_lock);
 723                 mutex_destroy(&clock->clock_lock);
 724                 put_device(&clock->bus->dev);
 725                 kfree(clock);
 726         }
 727
 728         mutex_unlock(&phyter_clocks_lock);
 729 }
 730
 731 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
 732 {
 733         INIT_LIST_HEAD(&clock->list);
 734         clock->bus = bus;
 735         mutex_init(&clock->extreg_lock);
 736         mutex_init(&clock->clock_lock);
 737         INIT_LIST_HEAD(&clock->phylist);
 738         clock->caps.owner = THIS_MODULE;
 739         sprintf(clock->caps.name, "dp83640 timer");
 740         clock->caps.max_adj     = 1953124;
 741         clock->caps.n_alarm     = 0;
 742         clock->caps.n_ext_ts    = N_EXT_TS;
 743         clock->caps.n_per_out   = 0;
 744         clock->caps.pps         = 0;
 745         clock->caps.adjfreq     = ptp_dp83640_adjfreq;
 746         clock->caps.adjtime     = ptp_dp83640_adjtime;
 747         clock->caps.gettime     = ptp_dp83640_gettime;
 748         clock->caps.settime     = ptp_dp83640_settime;
 749         clock->caps.enable      = ptp_dp83640_enable;
 750         /*
 751          * Get a reference to this bus instance.
 752          */
 753         get_device(&bus->dev);
 754 }
 755
 756 static int choose_this_phy(struct dp83640_clock *clock,
 757                            struct phy_device *phydev)
 758 {
 759         if (chosen_phy == -1 && !clock->chosen)
 760                 return 1;
 761
 762         if (chosen_phy == phydev->addr)
 763                 return 1;
 764
 765         return 0;
 766 }
 767
 768 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
 769 {
 770         if (clock)
 771                 mutex_lock(&clock->clock_lock);
 772         return clock;
 773 }
 774
 775 /*
 776  * Look up and lock a clock by bus instance.
 777  * If there is no clock for this bus, then create it first.
 778  */
 779 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
 780 {
 781         struct dp83640_clock *clock = NULL, *tmp;
 782         struct list_head *this;
 783
 784         mutex_lock(&phyter_clocks_lock);
 785
 786         list_for_each(this, &phyter_clocks) {
 787                 tmp = list_entry(this, struct dp83640_clock, list);
 788                 if (tmp->bus == bus) {
 789                         clock = tmp;
 790                         break;
 791                 }
 792         }
 793         if (clock)
 794                 goto out;
 795
 796         clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
 797         if (!clock)
 798                 goto out;
 799
 800         dp83640_clock_init(clock, bus);
 801         list_add_tail(&phyter_clocks, &clock->list);
 802 out:
 803         mutex_unlock(&phyter_clocks_lock);
 804
 805         return dp83640_clock_get(clock);
 806 }
 807
 808 static void dp83640_clock_put(struct dp83640_clock *clock)
 809 {
 810         mutex_unlock(&clock->clock_lock);
 811 }
 812
 813 static int dp83640_probe(struct phy_device *phydev)
 814 {
 815         struct dp83640_clock *clock;
 816         struct dp83640_private *dp83640;
 817         int err = -ENOMEM, i;
 818
 819         if (phydev->addr == BROADCAST_ADDR)
 820                 return 0;
 821
 822         clock = dp83640_clock_get_bus(phydev->bus);
 823         if (!clock)
 824                 goto no_clock;
 825
 826         dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
 827         if (!dp83640)
 828                 goto no_memory;
 829
 830         dp83640->phydev = phydev;
 831         INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
 832
 833         INIT_LIST_HEAD(&dp83640->rxts);
 834         INIT_LIST_HEAD(&dp83640->rxpool);
 835         for (i = 0; i < MAX_RXTS; i++)
 836                 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
 837
 838         phydev->priv = dp83640;
 839
 840         spin_lock_init(&dp83640->rx_lock);
 841         skb_queue_head_init(&dp83640->rx_queue);
 842         skb_queue_head_init(&dp83640->tx_queue);
 843
 844         dp83640->clock = clock;
 845
 846         if (choose_this_phy(clock, phydev)) {
 847                 clock->chosen = dp83640;
 848                 clock->ptp_clock = ptp_clock_register(&clock->caps);
 849                 if (IS_ERR(clock->ptp_clock)) {
 850                         err = PTR_ERR(clock->ptp_clock);
 851                         goto no_register;
 852                 }
 853         } else
 854                 list_add_tail(&dp83640->list, &clock->phylist);
 855
 856         if (clock->chosen && !list_empty(&clock->phylist))
 857                 recalibrate(clock);
 858         else
 859                 enable_broadcast(dp83640->phydev, clock->page, 1);
 860
 861         dp83640_clock_put(clock);
 862         return 0;
 863
 864 no_register:
 865         clock->chosen = NULL;
 866         kfree(dp83640);
 867 no_memory:
 868         dp83640_clock_put(clock);
 869 no_clock:
 870         return err;
 871 }
 872
 873 static void dp83640_remove(struct phy_device *phydev)
 874 {
 875         struct dp83640_clock *clock;
 876         struct list_head *this, *next;
 877         struct dp83640_private *tmp, *dp83640 = phydev->priv;
 878
 879         if (phydev->addr == BROADCAST_ADDR)
 880                 return;
 881
 882         enable_status_frames(phydev, false);
 883         cancel_work_sync(&dp83640->ts_work);
 884
 885         clock = dp83640_clock_get(dp83640->clock);
 886
 887         if (dp83640 == clock->chosen) {
 888                 ptp_clock_unregister(clock->ptp_clock);
 889                 clock->chosen = NULL;
 890         } else {
 891                 list_for_each_safe(this, next, &clock->phylist) {
 892                         tmp = list_entry(this, struct dp83640_private, list);
 893                         if (tmp == dp83640) {
 894                                 list_del_init(&tmp->list);
 895                                 break;
 896                         }
 897                 }
 898         }
 899
 900         dp83640_clock_put(clock);
 901         kfree(dp83640);
 902 }
 903
 904 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
 905 {
 906         struct dp83640_private *dp83640 = phydev->priv;
 907         struct hwtstamp_config cfg;
 908         u16 txcfg0, rxcfg0;
 909
 910         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 911                 return -EFAULT;
 912
 913         if (cfg.flags) /* reserved for future extensions */
 914                 return -EINVAL;
 915
 916         switch (cfg.tx_type) {
 917         case HWTSTAMP_TX_OFF:
 918                 dp83640->hwts_tx_en = 0;
 919                 break;
 920         case HWTSTAMP_TX_ON:
 921                 dp83640->hwts_tx_en = 1;
 922                 break;
 923         default:
 924                 return -ERANGE;
 925         }
 926
 927         switch (cfg.rx_filter) {
 928         case HWTSTAMP_FILTER_NONE:
 929                 dp83640->hwts_rx_en = 0;
 930                 dp83640->layer = 0;
 931                 dp83640->version = 0;
 932                 break;
 933         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 934         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 935         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 936                 dp83640->hwts_rx_en = 1;
 937                 dp83640->layer = LAYER4;
 938                 dp83640->version = 1;
 939                 break;
 940         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 941         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 942         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 943                 dp83640->hwts_rx_en = 1;
 944                 dp83640->layer = LAYER4;
 945                 dp83640->version = 2;
 946                 break;
 947         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 948         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 949         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 950                 dp83640->hwts_rx_en = 1;
 951                 dp83640->layer = LAYER2;
 952                 dp83640->version = 2;
 953                 break;
 954         case HWTSTAMP_FILTER_PTP_V2_EVENT:
 955         case HWTSTAMP_FILTER_PTP_V2_SYNC:
 956         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 957                 dp83640->hwts_rx_en = 1;
 958                 dp83640->layer = LAYER4|LAYER2;
 959                 dp83640->version = 2;
 960                 break;
 961         default:
 962                 return -ERANGE;
 963         }
 964
 965         txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
 966         rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
 967
 968         if (dp83640->layer & LAYER2) {
 969                 txcfg0 |= TX_L2_EN;
 970                 rxcfg0 |= RX_L2_EN;
 971         }
 972         if (dp83640->layer & LAYER4) {
 973                 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
 974                 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
 975         }
 976
 977         if (dp83640->hwts_tx_en)
 978                 txcfg0 |= TX_TS_EN;
 979
 980         if (dp83640->hwts_rx_en)
 981                 rxcfg0 |= RX_TS_EN;
 982
 983         mutex_lock(&dp83640->clock->extreg_lock);
 984
 985         if (dp83640->hwts_tx_en || dp83640->hwts_rx_en) {
 986                 enable_status_frames(phydev, true);
 987                 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
 988         }
 989
 990         ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
 991         ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
 992
 993         mutex_unlock(&dp83640->clock->extreg_lock);
 994
 995         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 996 }
 997
 998 static void rx_timestamp_work(struct work_struct *work)
 999 {
1000         struct dp83640_private *dp83640 =
1001                 container_of(work, struct dp83640_private, ts_work);
1002         struct list_head *this, *next;
1003         struct rxts *rxts;
1004         struct skb_shared_hwtstamps *shhwtstamps;
1005         struct sk_buff *skb;
1006         unsigned int type;
1007         unsigned long flags;
1008
1009         /* Deliver each deferred packet, with or without a time stamp. */
1010
1011         while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
1012                 type = SKB_PTP_TYPE(skb);
1013                 spin_lock_irqsave(&dp83640->rx_lock, flags);
1014                 list_for_each_safe(this, next, &dp83640->rxts) {
1015                         rxts = list_entry(this, struct rxts, list);
1016                         if (match(skb, type, rxts)) {
1017                                 shhwtstamps = skb_hwtstamps(skb);
1018                                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1019                                 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1020                                 list_del_init(&rxts->list);
1021                                 list_add(&rxts->list, &dp83640->rxpool);
1022                                 break;
1023                         }
1024                 }
1025                 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1026                 netif_rx(skb);
1027         }
1028
1029         /* Clear out expired time stamps. */
1030
1031         spin_lock_irqsave(&dp83640->rx_lock, flags);
1032         prune_rx_ts(dp83640);
1033         spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1034 }
1035
1036 static bool dp83640_rxtstamp(struct phy_device *phydev,
1037                              struct sk_buff *skb, int type)
1038 {
1039         struct dp83640_private *dp83640 = phydev->priv;
1040
1041         if (!dp83640->hwts_rx_en)
1042                 return false;
1043
1044         if (is_status_frame(skb, type)) {
1045                 decode_status_frame(dp83640, skb);
1046                 kfree_skb(skb);
1047                 return true;
1048         }
1049
1050         SKB_PTP_TYPE(skb) = type;
1051         skb_queue_tail(&dp83640->rx_queue, skb);
1052         schedule_work(&dp83640->ts_work);
1053
1054         return true;
1055 }
1056
1057 static void dp83640_txtstamp(struct phy_device *phydev,
1058                              struct sk_buff *skb, int type)
1059 {
1060         struct dp83640_private *dp83640 = phydev->priv;
1061
1062         if (!dp83640->hwts_tx_en) {
1063                 kfree_skb(skb);
1064                 return;
1065         }
1066         skb_queue_tail(&dp83640->tx_queue, skb);
1067         schedule_work(&dp83640->ts_work);
1068 }
1069
1070 static struct phy_driver dp83640_driver = {
1071         .phy_id         = DP83640_PHY_ID,
1072         .phy_id_mask    = 0xfffffff0,
1073         .name           = "NatSemi DP83640",
1074         .features       = PHY_BASIC_FEATURES,
1075         .flags          = 0,
1076         .probe          = dp83640_probe,
1077         .remove         = dp83640_remove,
1078         .config_aneg    = genphy_config_aneg,
1079         .read_status    = genphy_read_status,
1080         .hwtstamp       = dp83640_hwtstamp,
1081         .rxtstamp       = dp83640_rxtstamp,
1082         .txtstamp       = dp83640_txtstamp,
1083         .driver         = {.owner = THIS_MODULE,}
1084 };
1085
1086 static int __init dp83640_init(void)
1087 {
1088         return phy_driver_register(&dp83640_driver);
1089 }
1090
1091 static void __exit dp83640_exit(void)
1092 {
1093         dp83640_free_clocks();
1094         phy_driver_unregister(&dp83640_driver);
1095 }
1096
1097 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1098 MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
1099 MODULE_LICENSE("GPL");
1100
1101 module_init(dp83640_init);
1102 module_exit(dp83640_exit);
1103
1104 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1105         { DP83640_PHY_ID, 0xfffffff0 },
1106         { }
1107 };
1108
1109 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);