drivers/net/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define DRV_NAME        "pcnet32"
  25 #define DRV_VERSION     "1.35"
  26 #define DRV_RELDATE     "21.Apr.2008"
  27 #define PFX             DRV_NAME ": "
  28
  29 static const char *const version =
  30     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  31
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/string.h>
  35 #include <linux/errno.h>
  36 #include <linux/ioport.h>
  37 #include <linux/slab.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41 #include <linux/init.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/mii.h>
  44 #include <linux/crc32.h>
  45 #include <linux/netdevice.h>
  46 #include <linux/etherdevice.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/spinlock.h>
  49 #include <linux/moduleparam.h>
  50 #include <linux/bitops.h>
  51
  52 #include <asm/dma.h>
  53 #include <asm/io.h>
  54 #include <asm/uaccess.h>
  55 #include <asm/irq.h>
  56
  57 /*
  58  * PCI device identifiers for "new style" Linux PCI Device Drivers
  59  */
  60 static struct pci_device_id pcnet32_pci_tbl[] = {
  61         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  62         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  63
  64         /*
  65          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  66          * the incorrect vendor id.
  67          */
  68         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  69           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  70
  71         { }     /* terminate list */
  72 };
  73
  74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  75
  76 static int cards_found;
  77
  78 /*
  79  * VLB I/O addresses
  80  */
  81 static unsigned int pcnet32_portlist[] __initdata =
  82     { 0x300, 0x320, 0x340, 0x360, 0 };
  83
  84 static int pcnet32_debug = 0;
  85 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  86 static int pcnet32vlb;          /* check for VLB cards ? */
  87
  88 static struct net_device *pcnet32_dev;
  89
  90 static int max_interrupt_work = 2;
  91 static int rx_copybreak = 200;
  92
  93 #define PCNET32_PORT_AUI      0x00
  94 #define PCNET32_PORT_10BT     0x01
  95 #define PCNET32_PORT_GPSI     0x02
  96 #define PCNET32_PORT_MII      0x03
  97
  98 #define PCNET32_PORT_PORTSEL  0x03
  99 #define PCNET32_PORT_ASEL     0x04
 100 #define PCNET32_PORT_100      0x40
 101 #define PCNET32_PORT_FD       0x80
 102
 103 #define PCNET32_DMA_MASK 0xffffffff
 104
 105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 106 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 107
 108 /*
 109  * table to translate option values from tulip
 110  * to internal options
 111  */
 112 static const unsigned char options_mapping[] = {
 113         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 114         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 115         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 116         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 117         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 118         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 119         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 120         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 121         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 122         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 123         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 124         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 125         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 126         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 127                                                 /* 14 MII 100BaseTx-FD */
 128         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 129         PCNET32_PORT_ASEL                       /* 15 not supported    */
 130 };
 131
 132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 133         "Loopback test  (offline)"
 134 };
 135
 136 #define PCNET32_TEST_LEN        ARRAY_SIZE(pcnet32_gstrings_test)
 137
 138 #define PCNET32_NUM_REGS 136
 139
 140 #define MAX_UNITS 8             /* More are supported, limit only on options */
 141 static int options[MAX_UNITS];
 142 static int full_duplex[MAX_UNITS];
 143 static int homepna[MAX_UNITS];
 144
 145 /*
 146  *                              Theory of Operation
 147  *
 148  * This driver uses the same software structure as the normal lance
 149  * driver. So look for a verbose description in lance.c. The differences
 150  * to the normal lance driver is the use of the 32bit mode of PCnet32
 151  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 152  * 16MB limitation and we don't need bounce buffers.
 153  */
 154
 155 /*
 156  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 157  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 158  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 159  */
 160 #ifndef PCNET32_LOG_TX_BUFFERS
 161 #define PCNET32_LOG_TX_BUFFERS          4
 162 #define PCNET32_LOG_RX_BUFFERS          5
 163 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 164 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 165 #endif
 166
 167 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 168 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 169
 170 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 171 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 172
 173 #define PKT_BUF_SKB             1544
 174 /* actual buffer length after being aligned */
 175 #define PKT_BUF_SIZE            (PKT_BUF_SKB - NET_IP_ALIGN)
 176 /* chip wants twos complement of the (aligned) buffer length */
 177 #define NEG_BUF_SIZE            (NET_IP_ALIGN - PKT_BUF_SKB)
 178
 179 /* Offsets from base I/O address. */
 180 #define PCNET32_WIO_RDP         0x10
 181 #define PCNET32_WIO_RAP         0x12
 182 #define PCNET32_WIO_RESET       0x14
 183 #define PCNET32_WIO_BDP         0x16
 184
 185 #define PCNET32_DWIO_RDP        0x10
 186 #define PCNET32_DWIO_RAP        0x14
 187 #define PCNET32_DWIO_RESET      0x18
 188 #define PCNET32_DWIO_BDP        0x1C
 189
 190 #define PCNET32_TOTAL_SIZE      0x20
 191
 192 #define CSR0            0
 193 #define CSR0_INIT       0x1
 194 #define CSR0_START      0x2
 195 #define CSR0_STOP       0x4
 196 #define CSR0_TXPOLL     0x8
 197 #define CSR0_INTEN      0x40
 198 #define CSR0_IDON       0x0100
 199 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 200 #define PCNET32_INIT_LOW        1
 201 #define PCNET32_INIT_HIGH       2
 202 #define CSR3            3
 203 #define CSR4            4
 204 #define CSR5            5
 205 #define CSR5_SUSPEND    0x0001
 206 #define CSR15           15
 207 #define PCNET32_MC_FILTER       8
 208
 209 #define PCNET32_79C970A 0x2621
 210
 211 /* The PCNET32 Rx and Tx ring descriptors. */
 212 struct pcnet32_rx_head {
 213         __le32  base;
 214         __le16  buf_length;     /* two`s complement of length */
 215         __le16  status;
 216         __le32  msg_length;
 217         __le32  reserved;
 218 };
 219
 220 struct pcnet32_tx_head {
 221         __le32  base;
 222         __le16  length;         /* two`s complement of length */
 223         __le16  status;
 224         __le32  misc;
 225         __le32  reserved;
 226 };
 227
 228 /* The PCNET32 32-Bit initialization block, described in databook. */
 229 struct pcnet32_init_block {
 230         __le16  mode;
 231         __le16  tlen_rlen;
 232         u8      phys_addr[6];
 233         __le16  reserved;
 234         __le32  filter[2];
 235         /* Receive and transmit ring base, along with extra bits. */
 236         __le32  rx_ring;
 237         __le32  tx_ring;
 238 };
 239
 240 /* PCnet32 access functions */
 241 struct pcnet32_access {
 242         u16     (*read_csr) (unsigned long, int);
 243         void    (*write_csr) (unsigned long, int, u16);
 244         u16     (*read_bcr) (unsigned long, int);
 245         void    (*write_bcr) (unsigned long, int, u16);
 246         u16     (*read_rap) (unsigned long);
 247         void    (*write_rap) (unsigned long, u16);
 248         void    (*reset) (unsigned long);
 249 };
 250
 251 /*
 252  * The first field of pcnet32_private is read by the ethernet device
 253  * so the structure should be allocated using pci_alloc_consistent().
 254  */
 255 struct pcnet32_private {
 256         struct pcnet32_init_block *init_block;
 257         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 258         struct pcnet32_rx_head  *rx_ring;
 259         struct pcnet32_tx_head  *tx_ring;
 260         dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 261                                    returned by pci_alloc_consistent */
 262         struct pci_dev          *pci_dev;
 263         const char              *name;
 264         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 265         struct sk_buff          **tx_skbuff;
 266         struct sk_buff          **rx_skbuff;
 267         dma_addr_t              *tx_dma_addr;
 268         dma_addr_t              *rx_dma_addr;
 269         struct pcnet32_access   a;
 270         spinlock_t              lock;           /* Guard lock */
 271         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 272         unsigned int            rx_ring_size;   /* current rx ring size */
 273         unsigned int            tx_ring_size;   /* current tx ring size */
 274         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 275         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 276         unsigned short          rx_len_bits;
 277         unsigned short          tx_len_bits;
 278         dma_addr_t              rx_ring_dma_addr;
 279         dma_addr_t              tx_ring_dma_addr;
 280         unsigned int            dirty_rx,       /* ring entries to be freed. */
 281                                 dirty_tx;
 282
 283         struct net_device       *dev;
 284         struct napi_struct      napi;
 285         char                    tx_full;
 286         char                    phycount;       /* number of phys found */
 287         int                     options;
 288         unsigned int            shared_irq:1,   /* shared irq possible */
 289                                 dxsuflo:1,   /* disable transmit stop on uflo */
 290                                 mii:1;          /* mii port available */
 291         struct net_device       *next;
 292         struct mii_if_info      mii_if;
 293         struct timer_list       watchdog_timer;
 294         struct timer_list       blink_timer;
 295         u32                     msg_enable;     /* debug message level */
 296
 297         /* each bit indicates an available PHY */
 298         u32                     phymask;
 299         unsigned short          chip_version;   /* which variant this is */
 300 };
 301
 302 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 303 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 304 static int pcnet32_open(struct net_device *);
 305 static int pcnet32_init_ring(struct net_device *);
 306 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
 307 static void pcnet32_tx_timeout(struct net_device *dev);
 308 static irqreturn_t pcnet32_interrupt(int, void *);
 309 static int pcnet32_close(struct net_device *);
 310 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 311 static void pcnet32_load_multicast(struct net_device *dev);
 312 static void pcnet32_set_multicast_list(struct net_device *);
 313 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 314 static void pcnet32_watchdog(struct net_device *);
 315 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 316 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 317                        int val);
 318 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 319 static void pcnet32_ethtool_test(struct net_device *dev,
 320                                  struct ethtool_test *eth_test, u64 * data);
 321 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 322 static int pcnet32_phys_id(struct net_device *dev, u32 data);
 323 static void pcnet32_led_blink_callback(struct net_device *dev);
 324 static int pcnet32_get_regs_len(struct net_device *dev);
 325 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 326                              void *ptr);
 327 static void pcnet32_purge_tx_ring(struct net_device *dev);
 328 static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
 329 static void pcnet32_free_ring(struct net_device *dev);
 330 static void pcnet32_check_media(struct net_device *dev, int verbose);
 331
 332 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 333 {
 334         outw(index, addr + PCNET32_WIO_RAP);
 335         return inw(addr + PCNET32_WIO_RDP);
 336 }
 337
 338 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 339 {
 340         outw(index, addr + PCNET32_WIO_RAP);
 341         outw(val, addr + PCNET32_WIO_RDP);
 342 }
 343
 344 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 345 {
 346         outw(index, addr + PCNET32_WIO_RAP);
 347         return inw(addr + PCNET32_WIO_BDP);
 348 }
 349
 350 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 351 {
 352         outw(index, addr + PCNET32_WIO_RAP);
 353         outw(val, addr + PCNET32_WIO_BDP);
 354 }
 355
 356 static u16 pcnet32_wio_read_rap(unsigned long addr)
 357 {
 358         return inw(addr + PCNET32_WIO_RAP);
 359 }
 360
 361 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 362 {
 363         outw(val, addr + PCNET32_WIO_RAP);
 364 }
 365
 366 static void pcnet32_wio_reset(unsigned long addr)
 367 {
 368         inw(addr + PCNET32_WIO_RESET);
 369 }
 370
 371 static int pcnet32_wio_check(unsigned long addr)
 372 {
 373         outw(88, addr + PCNET32_WIO_RAP);
 374         return (inw(addr + PCNET32_WIO_RAP) == 88);
 375 }
 376
 377 static struct pcnet32_access pcnet32_wio = {
 378         .read_csr = pcnet32_wio_read_csr,
 379         .write_csr = pcnet32_wio_write_csr,
 380         .read_bcr = pcnet32_wio_read_bcr,
 381         .write_bcr = pcnet32_wio_write_bcr,
 382         .read_rap = pcnet32_wio_read_rap,
 383         .write_rap = pcnet32_wio_write_rap,
 384         .reset = pcnet32_wio_reset
 385 };
 386
 387 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 388 {
 389         outl(index, addr + PCNET32_DWIO_RAP);
 390         return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
 391 }
 392
 393 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 394 {
 395         outl(index, addr + PCNET32_DWIO_RAP);
 396         outl(val, addr + PCNET32_DWIO_RDP);
 397 }
 398
 399 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 400 {
 401         outl(index, addr + PCNET32_DWIO_RAP);
 402         return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
 403 }
 404
 405 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 406 {
 407         outl(index, addr + PCNET32_DWIO_RAP);
 408         outl(val, addr + PCNET32_DWIO_BDP);
 409 }
 410
 411 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 412 {
 413         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
 414 }
 415
 416 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 417 {
 418         outl(val, addr + PCNET32_DWIO_RAP);
 419 }
 420
 421 static void pcnet32_dwio_reset(unsigned long addr)
 422 {
 423         inl(addr + PCNET32_DWIO_RESET);
 424 }
 425
 426 static int pcnet32_dwio_check(unsigned long addr)
 427 {
 428         outl(88, addr + PCNET32_DWIO_RAP);
 429         return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
 430 }
 431
 432 static struct pcnet32_access pcnet32_dwio = {
 433         .read_csr = pcnet32_dwio_read_csr,
 434         .write_csr = pcnet32_dwio_write_csr,
 435         .read_bcr = pcnet32_dwio_read_bcr,
 436         .write_bcr = pcnet32_dwio_write_bcr,
 437         .read_rap = pcnet32_dwio_read_rap,
 438         .write_rap = pcnet32_dwio_write_rap,
 439         .reset = pcnet32_dwio_reset
 440 };
 441
 442 static void pcnet32_netif_stop(struct net_device *dev)
 443 {
 444         struct pcnet32_private *lp = netdev_priv(dev);
 445
 446         dev->trans_start = jiffies;
 447         napi_disable(&lp->napi);
 448         netif_tx_disable(dev);
 449 }
 450
 451 static void pcnet32_netif_start(struct net_device *dev)
 452 {
 453         struct pcnet32_private *lp = netdev_priv(dev);
 454         ulong ioaddr = dev->base_addr;
 455         u16 val;
 456
 457         netif_wake_queue(dev);
 458         val = lp->a.read_csr(ioaddr, CSR3);
 459         val &= 0x00ff;
 460         lp->a.write_csr(ioaddr, CSR3, val);
 461         napi_enable(&lp->napi);
 462 }
 463
 464 /*
 465  * Allocate space for the new sized tx ring.
 466  * Free old resources
 467  * Save new resources.
 468  * Any failure keeps old resources.
 469  * Must be called with lp->lock held.
 470  */
 471 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 472                                     struct pcnet32_private *lp,
 473                                     unsigned int size)
 474 {
 475         dma_addr_t new_ring_dma_addr;
 476         dma_addr_t *new_dma_addr_list;
 477         struct pcnet32_tx_head *new_tx_ring;
 478         struct sk_buff **new_skb_list;
 479
 480         pcnet32_purge_tx_ring(dev);
 481
 482         new_tx_ring = pci_alloc_consistent(lp->pci_dev,
 483                                            sizeof(struct pcnet32_tx_head) *
 484                                            (1 << size),
 485                                            &new_ring_dma_addr);
 486         if (new_tx_ring == NULL) {
 487                 if (netif_msg_drv(lp))
 488                         printk(KERN_ERR
 489                                "%s: Consistent memory allocation failed.\n",
 490                                dev->name);
 491                 return;
 492         }
 493         memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
 494
 495         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 496                                 GFP_ATOMIC);
 497         if (!new_dma_addr_list) {
 498                 if (netif_msg_drv(lp))
 499                         printk(KERN_ERR
 500                                "%s: Memory allocation failed.\n", dev->name);
 501                 goto free_new_tx_ring;
 502         }
 503
 504         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 505                                 GFP_ATOMIC);
 506         if (!new_skb_list) {
 507                 if (netif_msg_drv(lp))
 508                         printk(KERN_ERR
 509                                "%s: Memory allocation failed.\n", dev->name);
 510                 goto free_new_lists;
 511         }
 512
 513         kfree(lp->tx_skbuff);
 514         kfree(lp->tx_dma_addr);
 515         pci_free_consistent(lp->pci_dev,
 516                             sizeof(struct pcnet32_tx_head) *
 517                             lp->tx_ring_size, lp->tx_ring,
 518                             lp->tx_ring_dma_addr);
 519
 520         lp->tx_ring_size = (1 << size);
 521         lp->tx_mod_mask = lp->tx_ring_size - 1;
 522         lp->tx_len_bits = (size << 12);
 523         lp->tx_ring = new_tx_ring;
 524         lp->tx_ring_dma_addr = new_ring_dma_addr;
 525         lp->tx_dma_addr = new_dma_addr_list;
 526         lp->tx_skbuff = new_skb_list;
 527         return;
 528
 529     free_new_lists:
 530         kfree(new_dma_addr_list);
 531     free_new_tx_ring:
 532         pci_free_consistent(lp->pci_dev,
 533                             sizeof(struct pcnet32_tx_head) *
 534                             (1 << size),
 535                             new_tx_ring,
 536                             new_ring_dma_addr);
 537         return;
 538 }
 539
 540 /*
 541  * Allocate space for the new sized rx ring.
 542  * Re-use old receive buffers.
 543  *   alloc extra buffers
 544  *   free unneeded buffers
 545  *   free unneeded buffers
 546  * Save new resources.
 547  * Any failure keeps old resources.
 548  * Must be called with lp->lock held.
 549  */
 550 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 551                                     struct pcnet32_private *lp,
 552                                     unsigned int size)
 553 {
 554         dma_addr_t new_ring_dma_addr;
 555         dma_addr_t *new_dma_addr_list;
 556         struct pcnet32_rx_head *new_rx_ring;
 557         struct sk_buff **new_skb_list;
 558         int new, overlap;
 559
 560         new_rx_ring = pci_alloc_consistent(lp->pci_dev,
 561                                            sizeof(struct pcnet32_rx_head) *
 562                                            (1 << size),
 563                                            &new_ring_dma_addr);
 564         if (new_rx_ring == NULL) {
 565                 if (netif_msg_drv(lp))
 566                         printk(KERN_ERR
 567                                "%s: Consistent memory allocation failed.\n",
 568                                dev->name);
 569                 return;
 570         }
 571         memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
 572
 573         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 574                                 GFP_ATOMIC);
 575         if (!new_dma_addr_list) {
 576                 if (netif_msg_drv(lp))
 577                         printk(KERN_ERR
 578                                "%s: Memory allocation failed.\n", dev->name);
 579                 goto free_new_rx_ring;
 580         }
 581
 582         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 583                                 GFP_ATOMIC);
 584         if (!new_skb_list) {
 585                 if (netif_msg_drv(lp))
 586                         printk(KERN_ERR
 587                                "%s: Memory allocation failed.\n", dev->name);
 588                 goto free_new_lists;
 589         }
 590
 591         /* first copy the current receive buffers */
 592         overlap = min(size, lp->rx_ring_size);
 593         for (new = 0; new < overlap; new++) {
 594                 new_rx_ring[new] = lp->rx_ring[new];
 595                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 596                 new_skb_list[new] = lp->rx_skbuff[new];
 597         }
 598         /* now allocate any new buffers needed */
 599         for (; new < size; new++ ) {
 600                 struct sk_buff *rx_skbuff;
 601                 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
 602                 if (!(rx_skbuff = new_skb_list[new])) {
 603                         /* keep the original lists and buffers */
 604                         if (netif_msg_drv(lp))
 605                                 printk(KERN_ERR
 606                                        "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
 607                                        dev->name);
 608                         goto free_all_new;
 609                 }
 610                 skb_reserve(rx_skbuff, NET_IP_ALIGN);
 611
 612                 new_dma_addr_list[new] =
 613                             pci_map_single(lp->pci_dev, rx_skbuff->data,
 614                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 615                 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 616                 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
 617                 new_rx_ring[new].status = cpu_to_le16(0x8000);
 618         }
 619         /* and free any unneeded buffers */
 620         for (; new < lp->rx_ring_size; new++) {
 621                 if (lp->rx_skbuff[new]) {
 622                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
 623                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 624                         dev_kfree_skb(lp->rx_skbuff[new]);
 625                 }
 626         }
 627
 628         kfree(lp->rx_skbuff);
 629         kfree(lp->rx_dma_addr);
 630         pci_free_consistent(lp->pci_dev,
 631                             sizeof(struct pcnet32_rx_head) *
 632                             lp->rx_ring_size, lp->rx_ring,
 633                             lp->rx_ring_dma_addr);
 634
 635         lp->rx_ring_size = (1 << size);
 636         lp->rx_mod_mask = lp->rx_ring_size - 1;
 637         lp->rx_len_bits = (size << 4);
 638         lp->rx_ring = new_rx_ring;
 639         lp->rx_ring_dma_addr = new_ring_dma_addr;
 640         lp->rx_dma_addr = new_dma_addr_list;
 641         lp->rx_skbuff = new_skb_list;
 642         return;
 643
 644     free_all_new:
 645         for (; --new >= lp->rx_ring_size; ) {
 646                 if (new_skb_list[new]) {
 647                         pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
 648                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 649                         dev_kfree_skb(new_skb_list[new]);
 650                 }
 651         }
 652         kfree(new_skb_list);
 653     free_new_lists:
 654         kfree(new_dma_addr_list);
 655     free_new_rx_ring:
 656         pci_free_consistent(lp->pci_dev,
 657                             sizeof(struct pcnet32_rx_head) *
 658                             (1 << size),
 659                             new_rx_ring,
 660                             new_ring_dma_addr);
 661         return;
 662 }
 663
 664 static void pcnet32_purge_rx_ring(struct net_device *dev)
 665 {
 666         struct pcnet32_private *lp = netdev_priv(dev);
 667         int i;
 668
 669         /* free all allocated skbuffs */
 670         for (i = 0; i < lp->rx_ring_size; i++) {
 671                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 672                 wmb();          /* Make sure adapter sees owner change */
 673                 if (lp->rx_skbuff[i]) {
 674                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
 675                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 676                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 677                 }
 678                 lp->rx_skbuff[i] = NULL;
 679                 lp->rx_dma_addr[i] = 0;
 680         }
 681 }
 682
 683 #ifdef CONFIG_NET_POLL_CONTROLLER
 684 static void pcnet32_poll_controller(struct net_device *dev)
 685 {
 686         disable_irq(dev->irq);
 687         pcnet32_interrupt(0, dev);
 688         enable_irq(dev->irq);
 689 }
 690 #endif
 691
 692 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 693 {
 694         struct pcnet32_private *lp = netdev_priv(dev);
 695         unsigned long flags;
 696         int r = -EOPNOTSUPP;
 697
 698         if (lp->mii) {
 699                 spin_lock_irqsave(&lp->lock, flags);
 700                 mii_ethtool_gset(&lp->mii_if, cmd);
 701                 spin_unlock_irqrestore(&lp->lock, flags);
 702                 r = 0;
 703         }
 704         return r;
 705 }
 706
 707 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 708 {
 709         struct pcnet32_private *lp = netdev_priv(dev);
 710         unsigned long flags;
 711         int r = -EOPNOTSUPP;
 712
 713         if (lp->mii) {
 714                 spin_lock_irqsave(&lp->lock, flags);
 715                 r = mii_ethtool_sset(&lp->mii_if, cmd);
 716                 spin_unlock_irqrestore(&lp->lock, flags);
 717         }
 718         return r;
 719 }
 720
 721 static void pcnet32_get_drvinfo(struct net_device *dev,
 722                                 struct ethtool_drvinfo *info)
 723 {
 724         struct pcnet32_private *lp = netdev_priv(dev);
 725
 726         strcpy(info->driver, DRV_NAME);
 727         strcpy(info->version, DRV_VERSION);
 728         if (lp->pci_dev)
 729                 strcpy(info->bus_info, pci_name(lp->pci_dev));
 730         else
 731                 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
 732 }
 733
 734 static u32 pcnet32_get_link(struct net_device *dev)
 735 {
 736         struct pcnet32_private *lp = netdev_priv(dev);
 737         unsigned long flags;
 738         int r;
 739
 740         spin_lock_irqsave(&lp->lock, flags);
 741         if (lp->mii) {
 742                 r = mii_link_ok(&lp->mii_if);
 743         } else if (lp->chip_version >= PCNET32_79C970A) {
 744                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 745                 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
 746         } else {        /* can not detect link on really old chips */
 747                 r = 1;
 748         }
 749         spin_unlock_irqrestore(&lp->lock, flags);
 750
 751         return r;
 752 }
 753
 754 static u32 pcnet32_get_msglevel(struct net_device *dev)
 755 {
 756         struct pcnet32_private *lp = netdev_priv(dev);
 757         return lp->msg_enable;
 758 }
 759
 760 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 761 {
 762         struct pcnet32_private *lp = netdev_priv(dev);
 763         lp->msg_enable = value;
 764 }
 765
 766 static int pcnet32_nway_reset(struct net_device *dev)
 767 {
 768         struct pcnet32_private *lp = netdev_priv(dev);
 769         unsigned long flags;
 770         int r = -EOPNOTSUPP;
 771
 772         if (lp->mii) {
 773                 spin_lock_irqsave(&lp->lock, flags);
 774                 r = mii_nway_restart(&lp->mii_if);
 775                 spin_unlock_irqrestore(&lp->lock, flags);
 776         }
 777         return r;
 778 }
 779
 780 static void pcnet32_get_ringparam(struct net_device *dev,
 781                                   struct ethtool_ringparam *ering)
 782 {
 783         struct pcnet32_private *lp = netdev_priv(dev);
 784
 785         ering->tx_max_pending = TX_MAX_RING_SIZE;
 786         ering->tx_pending = lp->tx_ring_size;
 787         ering->rx_max_pending = RX_MAX_RING_SIZE;
 788         ering->rx_pending = lp->rx_ring_size;
 789 }
 790
 791 static int pcnet32_set_ringparam(struct net_device *dev,
 792                                  struct ethtool_ringparam *ering)
 793 {
 794         struct pcnet32_private *lp = netdev_priv(dev);
 795         unsigned long flags;
 796         unsigned int size;
 797         ulong ioaddr = dev->base_addr;
 798         int i;
 799
 800         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 801                 return -EINVAL;
 802
 803         if (netif_running(dev))
 804                 pcnet32_netif_stop(dev);
 805
 806         spin_lock_irqsave(&lp->lock, flags);
 807         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 808
 809         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 810
 811         /* set the minimum ring size to 4, to allow the loopback test to work
 812          * unchanged.
 813          */
 814         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 815                 if (size <= (1 << i))
 816                         break;
 817         }
 818         if ((1 << i) != lp->tx_ring_size)
 819                 pcnet32_realloc_tx_ring(dev, lp, i);
 820
 821         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 822         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 823                 if (size <= (1 << i))
 824                         break;
 825         }
 826         if ((1 << i) != lp->rx_ring_size)
 827                 pcnet32_realloc_rx_ring(dev, lp, i);
 828
 829         lp->napi.weight = lp->rx_ring_size / 2;
 830
 831         if (netif_running(dev)) {
 832                 pcnet32_netif_start(dev);
 833                 pcnet32_restart(dev, CSR0_NORMAL);
 834         }
 835
 836         spin_unlock_irqrestore(&lp->lock, flags);
 837
 838         if (netif_msg_drv(lp))
 839                 printk(KERN_INFO
 840                        "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
 841                        lp->rx_ring_size, lp->tx_ring_size);
 842
 843         return 0;
 844 }
 845
 846 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 847                                 u8 * data)
 848 {
 849         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 850 }
 851
 852 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 853 {
 854         switch (sset) {
 855         case ETH_SS_TEST:
 856                 return PCNET32_TEST_LEN;
 857         default:
 858                 return -EOPNOTSUPP;
 859         }
 860 }
 861
 862 static void pcnet32_ethtool_test(struct net_device *dev,
 863                                  struct ethtool_test *test, u64 * data)
 864 {
 865         struct pcnet32_private *lp = netdev_priv(dev);
 866         int rc;
 867
 868         if (test->flags == ETH_TEST_FL_OFFLINE) {
 869                 rc = pcnet32_loopback_test(dev, data);
 870                 if (rc) {
 871                         if (netif_msg_hw(lp))
 872                                 printk(KERN_DEBUG "%s: Loopback test failed.\n",
 873                                        dev->name);
 874                         test->flags |= ETH_TEST_FL_FAILED;
 875                 } else if (netif_msg_hw(lp))
 876                         printk(KERN_DEBUG "%s: Loopback test passed.\n",
 877                                dev->name);
 878         } else if (netif_msg_hw(lp))
 879                 printk(KERN_DEBUG
 880                        "%s: No tests to run (specify 'Offline' on ethtool).",
 881                        dev->name);
 882 }                               /* end pcnet32_ethtool_test */
 883
 884 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 885 {
 886         struct pcnet32_private *lp = netdev_priv(dev);
 887         struct pcnet32_access *a = &lp->a;      /* access to registers */
 888         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 889         struct sk_buff *skb;    /* sk buff */
 890         int x, i;               /* counters */
 891         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 892         u16 status = 0x8300;    /* TX ring status */
 893         __le16 teststatus;      /* test of ring status */
 894         int rc;                 /* return code */
 895         int size;               /* size of packets */
 896         unsigned char *packet;  /* source packet data */
 897         static const int data_len = 60; /* length of source packets */
 898         unsigned long flags;
 899         unsigned long ticks;
 900
 901         rc = 1;                 /* default to fail */
 902
 903         if (netif_running(dev))
 904                 pcnet32_netif_stop(dev);
 905
 906         spin_lock_irqsave(&lp->lock, flags);
 907         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 908
 909         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 910
 911         /* Reset the PCNET32 */
 912         lp->a.reset(ioaddr);
 913         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
 914
 915         /* switch pcnet32 to 32bit mode */
 916         lp->a.write_bcr(ioaddr, 20, 2);
 917
 918         /* purge & init rings but don't actually restart */
 919         pcnet32_restart(dev, 0x0000);
 920
 921         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 922
 923         /* Initialize Transmit buffers. */
 924         size = data_len + 15;
 925         for (x = 0; x < numbuffs; x++) {
 926                 if (!(skb = dev_alloc_skb(size))) {
 927                         if (netif_msg_hw(lp))
 928                                 printk(KERN_DEBUG
 929                                        "%s: Cannot allocate skb at line: %d!\n",
 930                                        dev->name, __LINE__);
 931                         goto clean_up;
 932                 } else {
 933                         packet = skb->data;
 934                         skb_put(skb, size);     /* create space for data */
 935                         lp->tx_skbuff[x] = skb;
 936                         lp->tx_ring[x].length = cpu_to_le16(-skb->len);
 937                         lp->tx_ring[x].misc = 0;
 938
 939                         /* put DA and SA into the skb */
 940                         for (i = 0; i < 6; i++)
 941                                 *packet++ = dev->dev_addr[i];
 942                         for (i = 0; i < 6; i++)
 943                                 *packet++ = dev->dev_addr[i];
 944                         /* type */
 945                         *packet++ = 0x08;
 946                         *packet++ = 0x06;
 947                         /* packet number */
 948                         *packet++ = x;
 949                         /* fill packet with data */
 950                         for (i = 0; i < data_len; i++)
 951                                 *packet++ = i;
 952
 953                         lp->tx_dma_addr[x] =
 954                             pci_map_single(lp->pci_dev, skb->data, skb->len,
 955                                            PCI_DMA_TODEVICE);
 956                         lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
 957                         wmb();  /* Make sure owner changes after all others are visible */
 958                         lp->tx_ring[x].status = cpu_to_le16(status);
 959                 }
 960         }
 961
 962         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
 963         a->write_bcr(ioaddr, 32, x | 0x0002);
 964
 965         /* set int loopback in CSR15 */
 966         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
 967         lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
 968
 969         teststatus = cpu_to_le16(0x8000);
 970         lp->a.write_csr(ioaddr, CSR0, CSR0_START);      /* Set STRT bit */
 971
 972         /* Check status of descriptors */
 973         for (x = 0; x < numbuffs; x++) {
 974                 ticks = 0;
 975                 rmb();
 976                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
 977                         spin_unlock_irqrestore(&lp->lock, flags);
 978                         msleep(1);
 979                         spin_lock_irqsave(&lp->lock, flags);
 980                         rmb();
 981                         ticks++;
 982                 }
 983                 if (ticks == 200) {
 984                         if (netif_msg_hw(lp))
 985                                 printk("%s: Desc %d failed to reset!\n",
 986                                        dev->name, x);
 987                         break;
 988                 }
 989         }
 990
 991         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 992         wmb();
 993         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
 994                 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
 995
 996                 for (x = 0; x < numbuffs; x++) {
 997                         printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
 998                         skb = lp->rx_skbuff[x];
 999                         for (i = 0; i < size; i++) {
1000                                 printk("%02x ", *(skb->data + i));
1001                         }
1002                         printk("\n");
1003                 }
1004         }
1005
1006         x = 0;
1007         rc = 0;
1008         while (x < numbuffs && !rc) {
1009                 skb = lp->rx_skbuff[x];
1010                 packet = lp->tx_skbuff[x]->data;
1011                 for (i = 0; i < size; i++) {
1012                         if (*(skb->data + i) != packet[i]) {
1013                                 if (netif_msg_hw(lp))
1014                                         printk(KERN_DEBUG
1015                                                "%s: Error in compare! %2x - %02x %02x\n",
1016                                                dev->name, i, *(skb->data + i),
1017                                                packet[i]);
1018                                 rc = 1;
1019                                 break;
1020                         }
1021                 }
1022                 x++;
1023         }
1024
1025       clean_up:
1026         *data1 = rc;
1027         pcnet32_purge_tx_ring(dev);
1028
1029         x = a->read_csr(ioaddr, CSR15);
1030         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1031
1032         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1033         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1034
1035         if (netif_running(dev)) {
1036                 pcnet32_netif_start(dev);
1037                 pcnet32_restart(dev, CSR0_NORMAL);
1038         } else {
1039                 pcnet32_purge_rx_ring(dev);
1040                 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1041         }
1042         spin_unlock_irqrestore(&lp->lock, flags);
1043
1044         return (rc);
1045 }                               /* end pcnet32_loopback_test  */
1046
1047 static void pcnet32_led_blink_callback(struct net_device *dev)
1048 {
1049         struct pcnet32_private *lp = netdev_priv(dev);
1050         struct pcnet32_access *a = &lp->a;
1051         ulong ioaddr = dev->base_addr;
1052         unsigned long flags;
1053         int i;
1054
1055         spin_lock_irqsave(&lp->lock, flags);
1056         for (i = 4; i < 8; i++) {
1057                 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1058         }
1059         spin_unlock_irqrestore(&lp->lock, flags);
1060
1061         mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1062 }
1063
1064 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1065 {
1066         struct pcnet32_private *lp = netdev_priv(dev);
1067         struct pcnet32_access *a = &lp->a;
1068         ulong ioaddr = dev->base_addr;
1069         unsigned long flags;
1070         int i, regs[4];
1071
1072         if (!lp->blink_timer.function) {
1073                 init_timer(&lp->blink_timer);
1074                 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1075                 lp->blink_timer.data = (unsigned long)dev;
1076         }
1077
1078         /* Save the current value of the bcrs */
1079         spin_lock_irqsave(&lp->lock, flags);
1080         for (i = 4; i < 8; i++) {
1081                 regs[i - 4] = a->read_bcr(ioaddr, i);
1082         }
1083         spin_unlock_irqrestore(&lp->lock, flags);
1084
1085         mod_timer(&lp->blink_timer, jiffies);
1086         set_current_state(TASK_INTERRUPTIBLE);
1087
1088         /* AV: the limit here makes no sense whatsoever */
1089         if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1090                 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1091
1092         msleep_interruptible(data * 1000);
1093         del_timer_sync(&lp->blink_timer);
1094
1095         /* Restore the original value of the bcrs */
1096         spin_lock_irqsave(&lp->lock, flags);
1097         for (i = 4; i < 8; i++) {
1098                 a->write_bcr(ioaddr, i, regs[i - 4]);
1099         }
1100         spin_unlock_irqrestore(&lp->lock, flags);
1101
1102         return 0;
1103 }
1104
1105 /*
1106  * lp->lock must be held.
1107  */
1108 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1109                 int can_sleep)
1110 {
1111         int csr5;
1112         struct pcnet32_private *lp = netdev_priv(dev);
1113         struct pcnet32_access *a = &lp->a;
1114         ulong ioaddr = dev->base_addr;
1115         int ticks;
1116
1117         /* really old chips have to be stopped. */
1118         if (lp->chip_version < PCNET32_79C970A)
1119                 return 0;
1120
1121         /* set SUSPEND (SPND) - CSR5 bit 0 */
1122         csr5 = a->read_csr(ioaddr, CSR5);
1123         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1124
1125         /* poll waiting for bit to be set */
1126         ticks = 0;
1127         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1128                 spin_unlock_irqrestore(&lp->lock, *flags);
1129                 if (can_sleep)
1130                         msleep(1);
1131                 else
1132                         mdelay(1);
1133                 spin_lock_irqsave(&lp->lock, *flags);
1134                 ticks++;
1135                 if (ticks > 200) {
1136                         if (netif_msg_hw(lp))
1137                                 printk(KERN_DEBUG
1138                                        "%s: Error getting into suspend!\n",
1139                                        dev->name);
1140                         return 0;
1141                 }
1142         }
1143         return 1;
1144 }
1145
1146 /*
1147  * process one receive descriptor entry
1148  */
1149
1150 static void pcnet32_rx_entry(struct net_device *dev,
1151                              struct pcnet32_private *lp,
1152                              struct pcnet32_rx_head *rxp,
1153                              int entry)
1154 {
1155         int status = (short)le16_to_cpu(rxp->status) >> 8;
1156         int rx_in_place = 0;
1157         struct sk_buff *skb;
1158         short pkt_len;
1159
1160         if (status != 0x03) {   /* There was an error. */
1161                 /*
1162                  * There is a tricky error noted by John Murphy,
1163                  * <murf@perftech.com> to Russ Nelson: Even with full-sized
1164                  * buffers it's possible for a jabber packet to use two
1165                  * buffers, with only the last correctly noting the error.
1166                  */
1167                 if (status & 0x01)      /* Only count a general error at the */
1168                         dev->stats.rx_errors++; /* end of a packet. */
1169                 if (status & 0x20)
1170                         dev->stats.rx_frame_errors++;
1171                 if (status & 0x10)
1172                         dev->stats.rx_over_errors++;
1173                 if (status & 0x08)
1174                         dev->stats.rx_crc_errors++;
1175                 if (status & 0x04)
1176                         dev->stats.rx_fifo_errors++;
1177                 return;
1178         }
1179
1180         pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1181
1182         /* Discard oversize frames. */
1183         if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1184                 if (netif_msg_drv(lp))
1185                         printk(KERN_ERR "%s: Impossible packet size %d!\n",
1186                                dev->name, pkt_len);
1187                 dev->stats.rx_errors++;
1188                 return;
1189         }
1190         if (pkt_len < 60) {
1191                 if (netif_msg_rx_err(lp))
1192                         printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1193                 dev->stats.rx_errors++;
1194                 return;
1195         }
1196
1197         if (pkt_len > rx_copybreak) {
1198                 struct sk_buff *newskb;
1199
1200                 if ((newskb = dev_alloc_skb(PKT_BUF_SKB))) {
1201                         skb_reserve(newskb, NET_IP_ALIGN);
1202                         skb = lp->rx_skbuff[entry];
1203                         pci_unmap_single(lp->pci_dev,
1204                                          lp->rx_dma_addr[entry],
1205                                          PKT_BUF_SIZE,
1206                                          PCI_DMA_FROMDEVICE);
1207                         skb_put(skb, pkt_len);
1208                         lp->rx_skbuff[entry] = newskb;
1209                         lp->rx_dma_addr[entry] =
1210                                             pci_map_single(lp->pci_dev,
1211                                                            newskb->data,
1212                                                            PKT_BUF_SIZE,
1213                                                            PCI_DMA_FROMDEVICE);
1214                         rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1215                         rx_in_place = 1;
1216                 } else
1217                         skb = NULL;
1218         } else {
1219                 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
1220         }
1221
1222         if (skb == NULL) {
1223                 if (netif_msg_drv(lp))
1224                         printk(KERN_ERR
1225                                "%s: Memory squeeze, dropping packet.\n",
1226                                dev->name);
1227                 dev->stats.rx_dropped++;
1228                 return;
1229         }
1230         if (!rx_in_place) {
1231                 skb_reserve(skb, NET_IP_ALIGN);
1232                 skb_put(skb, pkt_len);  /* Make room */
1233                 pci_dma_sync_single_for_cpu(lp->pci_dev,
1234                                             lp->rx_dma_addr[entry],
1235                                             pkt_len,
1236                                             PCI_DMA_FROMDEVICE);
1237                 skb_copy_to_linear_data(skb,
1238                                  (unsigned char *)(lp->rx_skbuff[entry]->data),
1239                                  pkt_len);
1240                 pci_dma_sync_single_for_device(lp->pci_dev,
1241                                                lp->rx_dma_addr[entry],
1242                                                pkt_len,
1243                                                PCI_DMA_FROMDEVICE);
1244         }
1245         dev->stats.rx_bytes += skb->len;
1246         skb->protocol = eth_type_trans(skb, dev);
1247         netif_receive_skb(skb);
1248         dev->stats.rx_packets++;
1249         return;
1250 }
1251
1252 static int pcnet32_rx(struct net_device *dev, int budget)
1253 {
1254         struct pcnet32_private *lp = netdev_priv(dev);
1255         int entry = lp->cur_rx & lp->rx_mod_mask;
1256         struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1257         int npackets = 0;
1258
1259         /* If we own the next entry, it's a new packet. Send it up. */
1260         while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1261                 pcnet32_rx_entry(dev, lp, rxp, entry);
1262                 npackets += 1;
1263                 /*
1264                  * The docs say that the buffer length isn't touched, but Andrew
1265                  * Boyd of QNX reports that some revs of the 79C965 clear it.
1266                  */
1267                 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1268                 wmb();  /* Make sure owner changes after others are visible */
1269                 rxp->status = cpu_to_le16(0x8000);
1270                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1271                 rxp = &lp->rx_ring[entry];
1272         }
1273
1274         return npackets;
1275 }
1276
1277 static int pcnet32_tx(struct net_device *dev)
1278 {
1279         struct pcnet32_private *lp = netdev_priv(dev);
1280         unsigned int dirty_tx = lp->dirty_tx;
1281         int delta;
1282         int must_restart = 0;
1283
1284         while (dirty_tx != lp->cur_tx) {
1285                 int entry = dirty_tx & lp->tx_mod_mask;
1286                 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1287
1288                 if (status < 0)
1289                         break;  /* It still hasn't been Txed */
1290
1291                 lp->tx_ring[entry].base = 0;
1292
1293                 if (status & 0x4000) {
1294                         /* There was a major error, log it. */
1295                         int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1296                         dev->stats.tx_errors++;
1297                         if (netif_msg_tx_err(lp))
1298                                 printk(KERN_ERR
1299                                        "%s: Tx error status=%04x err_status=%08x\n",
1300                                        dev->name, status,
1301                                        err_status);
1302                         if (err_status & 0x04000000)
1303                                 dev->stats.tx_aborted_errors++;
1304                         if (err_status & 0x08000000)
1305                                 dev->stats.tx_carrier_errors++;
1306                         if (err_status & 0x10000000)
1307                                 dev->stats.tx_window_errors++;
1308 #ifndef DO_DXSUFLO
1309                         if (err_status & 0x40000000) {
1310                                 dev->stats.tx_fifo_errors++;
1311                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
1312                                 /* Remove this verbosity later! */
1313                                 if (netif_msg_tx_err(lp))
1314                                         printk(KERN_ERR
1315                                                "%s: Tx FIFO error!\n",
1316                                                dev->name);
1317                                 must_restart = 1;
1318                         }
1319 #else
1320                         if (err_status & 0x40000000) {
1321                                 dev->stats.tx_fifo_errors++;
1322                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1323                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
1324                                         /* Remove this verbosity later! */
1325                                         if (netif_msg_tx_err(lp))
1326                                                 printk(KERN_ERR
1327                                                        "%s: Tx FIFO error!\n",
1328                                                        dev->name);
1329                                         must_restart = 1;
1330                                 }
1331                         }
1332 #endif
1333                 } else {
1334                         if (status & 0x1800)
1335                                 dev->stats.collisions++;
1336                         dev->stats.tx_packets++;
1337                 }
1338
1339                 /* We must free the original skb */
1340                 if (lp->tx_skbuff[entry]) {
1341                         pci_unmap_single(lp->pci_dev,
1342                                          lp->tx_dma_addr[entry],
1343                                          lp->tx_skbuff[entry]->
1344                                          len, PCI_DMA_TODEVICE);
1345                         dev_kfree_skb_any(lp->tx_skbuff[entry]);
1346                         lp->tx_skbuff[entry] = NULL;
1347                         lp->tx_dma_addr[entry] = 0;
1348                 }
1349                 dirty_tx++;
1350         }
1351
1352         delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1353         if (delta > lp->tx_ring_size) {
1354                 if (netif_msg_drv(lp))
1355                         printk(KERN_ERR
1356                                "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1357                                dev->name, dirty_tx, lp->cur_tx,
1358                                lp->tx_full);
1359                 dirty_tx += lp->tx_ring_size;
1360                 delta -= lp->tx_ring_size;
1361         }
1362
1363         if (lp->tx_full &&
1364             netif_queue_stopped(dev) &&
1365             delta < lp->tx_ring_size - 2) {
1366                 /* The ring is no longer full, clear tbusy. */
1367                 lp->tx_full = 0;
1368                 netif_wake_queue(dev);
1369         }
1370         lp->dirty_tx = dirty_tx;
1371
1372         return must_restart;
1373 }
1374
1375 static int pcnet32_poll(struct napi_struct *napi, int budget)
1376 {
1377         struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1378         struct net_device *dev = lp->dev;
1379         unsigned long ioaddr = dev->base_addr;
1380         unsigned long flags;
1381         int work_done;
1382         u16 val;
1383
1384         work_done = pcnet32_rx(dev, budget);
1385
1386         spin_lock_irqsave(&lp->lock, flags);
1387         if (pcnet32_tx(dev)) {
1388                 /* reset the chip to clear the error condition, then restart */
1389                 lp->a.reset(ioaddr);
1390                 lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
1391                 pcnet32_restart(dev, CSR0_START);
1392                 netif_wake_queue(dev);
1393         }
1394         spin_unlock_irqrestore(&lp->lock, flags);
1395
1396         if (work_done < budget) {
1397                 spin_lock_irqsave(&lp->lock, flags);
1398
1399                 __napi_complete(napi);
1400
1401                 /* clear interrupt masks */
1402                 val = lp->a.read_csr(ioaddr, CSR3);
1403                 val &= 0x00ff;
1404                 lp->a.write_csr(ioaddr, CSR3, val);
1405
1406                 /* Set interrupt enable. */
1407                 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1408
1409                 spin_unlock_irqrestore(&lp->lock, flags);
1410         }
1411         return work_done;
1412 }
1413
1414 #define PCNET32_REGS_PER_PHY    32
1415 #define PCNET32_MAX_PHYS        32
1416 static int pcnet32_get_regs_len(struct net_device *dev)
1417 {
1418         struct pcnet32_private *lp = netdev_priv(dev);
1419         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1420
1421         return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1422 }
1423
1424 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1425                              void *ptr)
1426 {
1427         int i, csr0;
1428         u16 *buff = ptr;
1429         struct pcnet32_private *lp = netdev_priv(dev);
1430         struct pcnet32_access *a = &lp->a;
1431         ulong ioaddr = dev->base_addr;
1432         unsigned long flags;
1433
1434         spin_lock_irqsave(&lp->lock, flags);
1435
1436         csr0 = a->read_csr(ioaddr, CSR0);
1437         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1438                 pcnet32_suspend(dev, &flags, 1);
1439
1440         /* read address PROM */
1441         for (i = 0; i < 16; i += 2)
1442                 *buff++ = inw(ioaddr + i);
1443
1444         /* read control and status registers */
1445         for (i = 0; i < 90; i++) {
1446                 *buff++ = a->read_csr(ioaddr, i);
1447         }
1448
1449         *buff++ = a->read_csr(ioaddr, 112);
1450         *buff++ = a->read_csr(ioaddr, 114);
1451
1452         /* read bus configuration registers */
1453         for (i = 0; i < 30; i++) {
1454                 *buff++ = a->read_bcr(ioaddr, i);
1455         }
1456         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1457         for (i = 31; i < 36; i++) {
1458                 *buff++ = a->read_bcr(ioaddr, i);
1459         }
1460
1461         /* read mii phy registers */
1462         if (lp->mii) {
1463                 int j;
1464                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1465                         if (lp->phymask & (1 << j)) {
1466                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1467                                         lp->a.write_bcr(ioaddr, 33,
1468                                                         (j << 5) | i);
1469                                         *buff++ = lp->a.read_bcr(ioaddr, 34);
1470                                 }
1471                         }
1472                 }
1473         }
1474
1475         if (!(csr0 & CSR0_STOP)) {      /* If not stopped */
1476                 int csr5;
1477
1478                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1479                 csr5 = a->read_csr(ioaddr, CSR5);
1480                 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1481         }
1482
1483         spin_unlock_irqrestore(&lp->lock, flags);
1484 }
1485
1486 static const struct ethtool_ops pcnet32_ethtool_ops = {
1487         .get_settings           = pcnet32_get_settings,
1488         .set_settings           = pcnet32_set_settings,
1489         .get_drvinfo            = pcnet32_get_drvinfo,
1490         .get_msglevel           = pcnet32_get_msglevel,
1491         .set_msglevel           = pcnet32_set_msglevel,
1492         .nway_reset             = pcnet32_nway_reset,
1493         .get_link               = pcnet32_get_link,
1494         .get_ringparam          = pcnet32_get_ringparam,
1495         .set_ringparam          = pcnet32_set_ringparam,
1496         .get_strings            = pcnet32_get_strings,
1497         .self_test              = pcnet32_ethtool_test,
1498         .phys_id                = pcnet32_phys_id,
1499         .get_regs_len           = pcnet32_get_regs_len,
1500         .get_regs               = pcnet32_get_regs,
1501         .get_sset_count         = pcnet32_get_sset_count,
1502 };
1503
1504 /* only probes for non-PCI devices, the rest are handled by
1505  * pci_register_driver via pcnet32_probe_pci */
1506
1507 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1508 {
1509         unsigned int *port, ioaddr;
1510
1511         /* search for PCnet32 VLB cards at known addresses */
1512         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1513                 if (request_region
1514                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1515                         /* check if there is really a pcnet chip on that ioaddr */
1516                         if ((inb(ioaddr + 14) == 0x57)
1517                             && (inb(ioaddr + 15) == 0x57)) {
1518                                 pcnet32_probe1(ioaddr, 0, NULL);
1519                         } else {
1520                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1521                         }
1522                 }
1523         }
1524 }
1525
1526 static int __devinit
1527 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1528 {
1529         unsigned long ioaddr;
1530         int err;
1531
1532         err = pci_enable_device(pdev);
1533         if (err < 0) {
1534                 if (pcnet32_debug & NETIF_MSG_PROBE)
1535                         printk(KERN_ERR PFX
1536                                "failed to enable device -- err=%d\n", err);
1537                 return err;
1538         }
1539         pci_set_master(pdev);
1540
1541         ioaddr = pci_resource_start(pdev, 0);
1542         if (!ioaddr) {
1543                 if (pcnet32_debug & NETIF_MSG_PROBE)
1544                         printk(KERN_ERR PFX
1545                                "card has no PCI IO resources, aborting\n");
1546                 return -ENODEV;
1547         }
1548
1549         if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1550                 if (pcnet32_debug & NETIF_MSG_PROBE)
1551                         printk(KERN_ERR PFX
1552                                "architecture does not support 32bit PCI busmaster DMA\n");
1553                 return -ENODEV;
1554         }
1555         if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1556             NULL) {
1557                 if (pcnet32_debug & NETIF_MSG_PROBE)
1558                         printk(KERN_ERR PFX
1559                                "io address range already allocated\n");
1560                 return -EBUSY;
1561         }
1562
1563         err = pcnet32_probe1(ioaddr, 1, pdev);
1564         if (err < 0) {
1565                 pci_disable_device(pdev);
1566         }
1567         return err;
1568 }
1569
1570 static const struct net_device_ops pcnet32_netdev_ops = {
1571         .ndo_open               = pcnet32_open,
1572         .ndo_stop               = pcnet32_close,
1573         .ndo_start_xmit         = pcnet32_start_xmit,
1574         .ndo_tx_timeout         = pcnet32_tx_timeout,
1575         .ndo_get_stats          = pcnet32_get_stats,
1576         .ndo_set_multicast_list = pcnet32_set_multicast_list,
1577         .ndo_do_ioctl           = pcnet32_ioctl,
1578         .ndo_change_mtu         = eth_change_mtu,
1579         .ndo_set_mac_address    = eth_mac_addr,
1580         .ndo_validate_addr      = eth_validate_addr,
1581 #ifdef CONFIG_NET_POLL_CONTROLLER
1582         .ndo_poll_controller    = pcnet32_poll_controller,
1583 #endif
1584 };
1585
1586 /* pcnet32_probe1
1587  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1588  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1589  */
1590 static int __devinit
1591 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1592 {
1593         struct pcnet32_private *lp;
1594         int i, media;
1595         int fdx, mii, fset, dxsuflo;
1596         int chip_version;
1597         char *chipname;
1598         struct net_device *dev;
1599         struct pcnet32_access *a = NULL;
1600         u8 promaddr[6];
1601         int ret = -ENODEV;
1602
1603         /* reset the chip */
1604         pcnet32_wio_reset(ioaddr);
1605
1606         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1607         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1608                 a = &pcnet32_wio;
1609         } else {
1610                 pcnet32_dwio_reset(ioaddr);
1611                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1612                     && pcnet32_dwio_check(ioaddr)) {
1613                         a = &pcnet32_dwio;
1614                 } else {
1615                         if (pcnet32_debug & NETIF_MSG_PROBE)
1616                                 printk(KERN_ERR PFX "No access methods\n");
1617                         goto err_release_region;
1618                 }
1619         }
1620
1621         chip_version =
1622             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1623         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1624                 printk(KERN_INFO "  PCnet chip version is %#x.\n",
1625                        chip_version);
1626         if ((chip_version & 0xfff) != 0x003) {
1627                 if (pcnet32_debug & NETIF_MSG_PROBE)
1628                         printk(KERN_INFO PFX "Unsupported chip version.\n");
1629                 goto err_release_region;
1630         }
1631
1632         /* initialize variables */
1633         fdx = mii = fset = dxsuflo = 0;
1634         chip_version = (chip_version >> 12) & 0xffff;
1635
1636         switch (chip_version) {
1637         case 0x2420:
1638                 chipname = "PCnet/PCI 79C970";  /* PCI */
1639                 break;
1640         case 0x2430:
1641                 if (shared)
1642                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1643                 else
1644                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1645                 break;
1646         case 0x2621:
1647                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1648                 fdx = 1;
1649                 break;
1650         case 0x2623:
1651                 chipname = "PCnet/FAST 79C971"; /* PCI */
1652                 fdx = 1;
1653                 mii = 1;
1654                 fset = 1;
1655                 break;
1656         case 0x2624:
1657                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1658                 fdx = 1;
1659                 mii = 1;
1660                 fset = 1;
1661                 break;
1662         case 0x2625:
1663                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1664                 fdx = 1;
1665                 mii = 1;
1666                 break;
1667         case 0x2626:
1668                 chipname = "PCnet/Home 79C978"; /* PCI */
1669                 fdx = 1;
1670                 /*
1671                  * This is based on specs published at www.amd.com.  This section
1672                  * assumes that a card with a 79C978 wants to go into standard
1673                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1674                  * and the module option homepna=1 can select this instead.
1675                  */
1676                 media = a->read_bcr(ioaddr, 49);
1677                 media &= ~3;    /* default to 10Mb ethernet */
1678                 if (cards_found < MAX_UNITS && homepna[cards_found])
1679                         media |= 1;     /* switch to home wiring mode */
1680                 if (pcnet32_debug & NETIF_MSG_PROBE)
1681                         printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1682                                (media & 1) ? "1" : "10");
1683                 a->write_bcr(ioaddr, 49, media);
1684                 break;
1685         case 0x2627:
1686                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1687                 fdx = 1;
1688                 mii = 1;
1689                 break;
1690         case 0x2628:
1691                 chipname = "PCnet/PRO 79C976";
1692                 fdx = 1;
1693                 mii = 1;
1694                 break;
1695         default:
1696                 if (pcnet32_debug & NETIF_MSG_PROBE)
1697                         printk(KERN_INFO PFX
1698                                "PCnet version %#x, no PCnet32 chip.\n",
1699                                chip_version);
1700                 goto err_release_region;
1701         }
1702
1703         /*
1704          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1705          *  starting until the packet is loaded. Strike one for reliability, lose
1706          *  one for latency - although on PCI this isnt a big loss. Older chips
1707          *  have FIFO's smaller than a packet, so you can't do this.
1708          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1709          */
1710
1711         if (fset) {
1712                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1713                 a->write_csr(ioaddr, 80,
1714                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1715                 dxsuflo = 1;
1716         }
1717
1718         dev = alloc_etherdev(sizeof(*lp));
1719         if (!dev) {
1720                 if (pcnet32_debug & NETIF_MSG_PROBE)
1721                         printk(KERN_ERR PFX "Memory allocation failed.\n");
1722                 ret = -ENOMEM;
1723                 goto err_release_region;
1724         }
1725
1726         if (pdev)
1727                 SET_NETDEV_DEV(dev, &pdev->dev);
1728
1729         if (pcnet32_debug & NETIF_MSG_PROBE)
1730                 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1731
1732         /* In most chips, after a chip reset, the ethernet address is read from the
1733          * station address PROM at the base address and programmed into the
1734          * "Physical Address Registers" CSR12-14.
1735          * As a precautionary measure, we read the PROM values and complain if
1736          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1737          * is valid, then the PROM addr is used.
1738          */
1739         for (i = 0; i < 3; i++) {
1740                 unsigned int val;
1741                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1742                 /* There may be endianness issues here. */
1743                 dev->dev_addr[2 * i] = val & 0x0ff;
1744                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1745         }
1746
1747         /* read PROM address and compare with CSR address */
1748         for (i = 0; i < 6; i++)
1749                 promaddr[i] = inb(ioaddr + i);
1750
1751         if (memcmp(promaddr, dev->dev_addr, 6)
1752             || !is_valid_ether_addr(dev->dev_addr)) {
1753                 if (is_valid_ether_addr(promaddr)) {
1754                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1755                                 printk(" warning: CSR address invalid,\n");
1756                                 printk(KERN_INFO
1757                                        "    using instead PROM address of");
1758                         }
1759                         memcpy(dev->dev_addr, promaddr, 6);
1760                 }
1761         }
1762         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1763
1764         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1765         if (!is_valid_ether_addr(dev->perm_addr))
1766                 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1767
1768         if (pcnet32_debug & NETIF_MSG_PROBE) {
1769                 printk(" %pM", dev->dev_addr);
1770
1771                 /* Version 0x2623 and 0x2624 */
1772                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1773                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1774                         printk(KERN_INFO "    tx_start_pt(0x%04x):", i);
1775                         switch (i >> 10) {
1776                         case 0:
1777                                 printk(KERN_CONT "  20 bytes,");
1778                                 break;
1779                         case 1:
1780                                 printk(KERN_CONT "  64 bytes,");
1781                                 break;
1782                         case 2:
1783                                 printk(KERN_CONT " 128 bytes,");
1784                                 break;
1785                         case 3:
1786                                 printk(KERN_CONT "~220 bytes,");
1787                                 break;
1788                         }
1789                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1790                         printk(KERN_CONT " BCR18(%x):", i & 0xffff);
1791                         if (i & (1 << 5))
1792                                 printk(KERN_CONT "BurstWrEn ");
1793                         if (i & (1 << 6))
1794                                 printk(KERN_CONT "BurstRdEn ");
1795                         if (i & (1 << 7))
1796                                 printk(KERN_CONT "DWordIO ");
1797                         if (i & (1 << 11))
1798                                 printk(KERN_CONT "NoUFlow ");
1799                         i = a->read_bcr(ioaddr, 25);
1800                         printk(KERN_INFO "    SRAMSIZE=0x%04x,", i << 8);
1801                         i = a->read_bcr(ioaddr, 26);
1802                         printk(KERN_CONT " SRAM_BND=0x%04x,", i << 8);
1803                         i = a->read_bcr(ioaddr, 27);
1804                         if (i & (1 << 14))
1805                                 printk(KERN_CONT "LowLatRx");
1806                 }
1807         }
1808
1809         dev->base_addr = ioaddr;
1810         lp = netdev_priv(dev);
1811         /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1812         if ((lp->init_block =
1813              pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
1814                 if (pcnet32_debug & NETIF_MSG_PROBE)
1815                         printk(KERN_ERR PFX
1816                                "Consistent memory allocation failed.\n");
1817                 ret = -ENOMEM;
1818                 goto err_free_netdev;
1819         }
1820         lp->pci_dev = pdev;
1821
1822         lp->dev = dev;
1823
1824         spin_lock_init(&lp->lock);
1825
1826         lp->name = chipname;
1827         lp->shared_irq = shared;
1828         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1829         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1830         lp->tx_mod_mask = lp->tx_ring_size - 1;
1831         lp->rx_mod_mask = lp->rx_ring_size - 1;
1832         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1833         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1834         lp->mii_if.full_duplex = fdx;
1835         lp->mii_if.phy_id_mask = 0x1f;
1836         lp->mii_if.reg_num_mask = 0x1f;
1837         lp->dxsuflo = dxsuflo;
1838         lp->mii = mii;
1839         lp->chip_version = chip_version;
1840         lp->msg_enable = pcnet32_debug;
1841         if ((cards_found >= MAX_UNITS)
1842             || (options[cards_found] >= sizeof(options_mapping)))
1843                 lp->options = PCNET32_PORT_ASEL;
1844         else
1845                 lp->options = options_mapping[options[cards_found]];
1846         lp->mii_if.dev = dev;
1847         lp->mii_if.mdio_read = mdio_read;
1848         lp->mii_if.mdio_write = mdio_write;
1849
1850         /* napi.weight is used in both the napi and non-napi cases */
1851         lp->napi.weight = lp->rx_ring_size / 2;
1852
1853         netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1854
1855         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1856             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1857                 lp->options |= PCNET32_PORT_FD;
1858
1859         lp->a = *a;
1860
1861         /* prior to register_netdev, dev->name is not yet correct */
1862         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1863                 ret = -ENOMEM;
1864                 goto err_free_ring;
1865         }
1866         /* detect special T1/E1 WAN card by checking for MAC address */
1867         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1868             && dev->dev_addr[2] == 0x75)
1869                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1870
1871         lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1872         lp->init_block->tlen_rlen =
1873             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1874         for (i = 0; i < 6; i++)
1875                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1876         lp->init_block->filter[0] = 0x00000000;
1877         lp->init_block->filter[1] = 0x00000000;
1878         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1879         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1880
1881         /* switch pcnet32 to 32bit mode */
1882         a->write_bcr(ioaddr, 20, 2);
1883
1884         a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1885         a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1886
1887         if (pdev) {             /* use the IRQ provided by PCI */
1888                 dev->irq = pdev->irq;
1889                 if (pcnet32_debug & NETIF_MSG_PROBE)
1890                         printk(" assigned IRQ %d.\n", dev->irq);
1891         } else {
1892                 unsigned long irq_mask = probe_irq_on();
1893
1894                 /*
1895                  * To auto-IRQ we enable the initialization-done and DMA error
1896                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1897                  * boards will work.
1898                  */
1899                 /* Trigger an initialization just for the interrupt. */
1900                 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1901                 mdelay(1);
1902
1903                 dev->irq = probe_irq_off(irq_mask);
1904                 if (!dev->irq) {
1905                         if (pcnet32_debug & NETIF_MSG_PROBE)
1906                                 printk(", failed to detect IRQ line.\n");
1907                         ret = -ENODEV;
1908                         goto err_free_ring;
1909                 }
1910                 if (pcnet32_debug & NETIF_MSG_PROBE)
1911                         printk(", probed IRQ %d.\n", dev->irq);
1912         }
1913
1914         /* Set the mii phy_id so that we can query the link state */
1915         if (lp->mii) {
1916                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1917
1918                 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1919                 /* scan for PHYs */
1920                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1921                         unsigned short id1, id2;
1922
1923                         id1 = mdio_read(dev, i, MII_PHYSID1);
1924                         if (id1 == 0xffff)
1925                                 continue;
1926                         id2 = mdio_read(dev, i, MII_PHYSID2);
1927                         if (id2 == 0xffff)
1928                                 continue;
1929                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1930                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1931                         lp->phycount++;
1932                         lp->phymask |= (1 << i);
1933                         lp->mii_if.phy_id = i;
1934                         if (pcnet32_debug & NETIF_MSG_PROBE)
1935                                 printk(KERN_INFO PFX
1936                                        "Found PHY %04x:%04x at address %d.\n",
1937                                        id1, id2, i);
1938                 }
1939                 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1940                 if (lp->phycount > 1) {
1941                         lp->options |= PCNET32_PORT_MII;
1942                 }
1943         }
1944
1945         init_timer(&lp->watchdog_timer);
1946         lp->watchdog_timer.data = (unsigned long)dev;
1947         lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1948
1949         /* The PCNET32-specific entries in the device structure. */
1950         dev->netdev_ops = &pcnet32_netdev_ops;
1951         dev->ethtool_ops = &pcnet32_ethtool_ops;
1952         dev->watchdog_timeo = (5 * HZ);
1953
1954         /* Fill in the generic fields of the device structure. */
1955         if (register_netdev(dev))
1956                 goto err_free_ring;
1957
1958         if (pdev) {
1959                 pci_set_drvdata(pdev, dev);
1960         } else {
1961                 lp->next = pcnet32_dev;
1962                 pcnet32_dev = dev;
1963         }
1964
1965         if (pcnet32_debug & NETIF_MSG_PROBE)
1966                 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1967         cards_found++;
1968
1969         /* enable LED writes */
1970         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1971
1972         return 0;
1973
1974 err_free_ring:
1975         pcnet32_free_ring(dev);
1976         pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1977                             lp->init_block, lp->init_dma_addr);
1978 err_free_netdev:
1979         free_netdev(dev);
1980 err_release_region:
1981         release_region(ioaddr, PCNET32_TOTAL_SIZE);
1982         return ret;
1983 }
1984
1985 /* if any allocation fails, caller must also call pcnet32_free_ring */
1986 static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
1987 {
1988         struct pcnet32_private *lp = netdev_priv(dev);
1989
1990         lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1991                                            sizeof(struct pcnet32_tx_head) *
1992                                            lp->tx_ring_size,
1993                                            &lp->tx_ring_dma_addr);
1994         if (lp->tx_ring == NULL) {
1995                 if (netif_msg_drv(lp))
1996                         printk(KERN_ERR PFX
1997                                "%s: Consistent memory allocation failed.\n",
1998                                name);
1999                 return -ENOMEM;
2000         }
2001
2002         lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2003                                            sizeof(struct pcnet32_rx_head) *
2004                                            lp->rx_ring_size,
2005                                            &lp->rx_ring_dma_addr);
2006         if (lp->rx_ring == NULL) {
2007                 if (netif_msg_drv(lp))
2008                         printk(KERN_ERR PFX
2009                                "%s: Consistent memory allocation failed.\n",
2010                                name);
2011                 return -ENOMEM;
2012         }
2013
2014         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2015                                   GFP_ATOMIC);
2016         if (!lp->tx_dma_addr) {
2017                 if (netif_msg_drv(lp))
2018                         printk(KERN_ERR PFX
2019                                "%s: Memory allocation failed.\n", name);
2020                 return -ENOMEM;
2021         }
2022
2023         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2024                                   GFP_ATOMIC);
2025         if (!lp->rx_dma_addr) {
2026                 if (netif_msg_drv(lp))
2027                         printk(KERN_ERR PFX
2028                                "%s: Memory allocation failed.\n", name);
2029                 return -ENOMEM;
2030         }
2031
2032         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2033                                 GFP_ATOMIC);
2034         if (!lp->tx_skbuff) {
2035                 if (netif_msg_drv(lp))
2036                         printk(KERN_ERR PFX
2037                                "%s: Memory allocation failed.\n", name);
2038                 return -ENOMEM;
2039         }
2040
2041         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2042                                 GFP_ATOMIC);
2043         if (!lp->rx_skbuff) {
2044                 if (netif_msg_drv(lp))
2045                         printk(KERN_ERR PFX
2046                                "%s: Memory allocation failed.\n", name);
2047                 return -ENOMEM;
2048         }
2049
2050         return 0;
2051 }
2052
2053 static void pcnet32_free_ring(struct net_device *dev)
2054 {
2055         struct pcnet32_private *lp = netdev_priv(dev);
2056
2057         kfree(lp->tx_skbuff);
2058         lp->tx_skbuff = NULL;
2059
2060         kfree(lp->rx_skbuff);
2061         lp->rx_skbuff = NULL;
2062
2063         kfree(lp->tx_dma_addr);
2064         lp->tx_dma_addr = NULL;
2065
2066         kfree(lp->rx_dma_addr);
2067         lp->rx_dma_addr = NULL;
2068
2069         if (lp->tx_ring) {
2070                 pci_free_consistent(lp->pci_dev,
2071                                     sizeof(struct pcnet32_tx_head) *
2072                                     lp->tx_ring_size, lp->tx_ring,
2073                                     lp->tx_ring_dma_addr);
2074                 lp->tx_ring = NULL;
2075         }
2076
2077         if (lp->rx_ring) {
2078                 pci_free_consistent(lp->pci_dev,
2079                                     sizeof(struct pcnet32_rx_head) *
2080                                     lp->rx_ring_size, lp->rx_ring,
2081                                     lp->rx_ring_dma_addr);
2082                 lp->rx_ring = NULL;
2083         }
2084 }
2085
2086 static int pcnet32_open(struct net_device *dev)
2087 {
2088         struct pcnet32_private *lp = netdev_priv(dev);
2089         struct pci_dev *pdev = lp->pci_dev;
2090         unsigned long ioaddr = dev->base_addr;
2091         u16 val;
2092         int i;
2093         int rc;
2094         unsigned long flags;
2095
2096         if (request_irq(dev->irq, &pcnet32_interrupt,
2097                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2098                         (void *)dev)) {
2099                 return -EAGAIN;
2100         }
2101
2102         spin_lock_irqsave(&lp->lock, flags);
2103         /* Check for a valid station address */
2104         if (!is_valid_ether_addr(dev->dev_addr)) {
2105                 rc = -EINVAL;
2106                 goto err_free_irq;
2107         }
2108
2109         /* Reset the PCNET32 */
2110         lp->a.reset(ioaddr);
2111
2112         /* switch pcnet32 to 32bit mode */
2113         lp->a.write_bcr(ioaddr, 20, 2);
2114
2115         if (netif_msg_ifup(lp))
2116                 printk(KERN_DEBUG
2117                        "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2118                        dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2119                        (u32) (lp->rx_ring_dma_addr),
2120                        (u32) (lp->init_dma_addr));
2121
2122         /* set/reset autoselect bit */
2123         val = lp->a.read_bcr(ioaddr, 2) & ~2;
2124         if (lp->options & PCNET32_PORT_ASEL)
2125                 val |= 2;
2126         lp->a.write_bcr(ioaddr, 2, val);
2127
2128         /* handle full duplex setting */
2129         if (lp->mii_if.full_duplex) {
2130                 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2131                 if (lp->options & PCNET32_PORT_FD) {
2132                         val |= 1;
2133                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2134                                 val |= 2;
2135                 } else if (lp->options & PCNET32_PORT_ASEL) {
2136                         /* workaround of xSeries250, turn on for 79C975 only */
2137                         if (lp->chip_version == 0x2627)
2138                                 val |= 3;
2139                 }
2140                 lp->a.write_bcr(ioaddr, 9, val);
2141         }
2142
2143         /* set/reset GPSI bit in test register */
2144         val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2145         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2146                 val |= 0x10;
2147         lp->a.write_csr(ioaddr, 124, val);
2148
2149         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2150         if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2151             (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2152              pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2153                 if (lp->options & PCNET32_PORT_ASEL) {
2154                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2155                         if (netif_msg_link(lp))
2156                                 printk(KERN_DEBUG
2157                                        "%s: Setting 100Mb-Full Duplex.\n",
2158                                        dev->name);
2159                 }
2160         }
2161         if (lp->phycount < 2) {
2162                 /*
2163                  * 24 Jun 2004 according AMD, in order to change the PHY,
2164                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
2165                  * duplex, and/or enable auto negotiation, and clear DANAS
2166                  */
2167                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2168                         lp->a.write_bcr(ioaddr, 32,
2169                                         lp->a.read_bcr(ioaddr, 32) | 0x0080);
2170                         /* disable Auto Negotiation, set 10Mpbs, HD */
2171                         val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2172                         if (lp->options & PCNET32_PORT_FD)
2173                                 val |= 0x10;
2174                         if (lp->options & PCNET32_PORT_100)
2175                                 val |= 0x08;
2176                         lp->a.write_bcr(ioaddr, 32, val);
2177                 } else {
2178                         if (lp->options & PCNET32_PORT_ASEL) {
2179                                 lp->a.write_bcr(ioaddr, 32,
2180                                                 lp->a.read_bcr(ioaddr,
2181                                                                32) | 0x0080);
2182                                 /* enable auto negotiate, setup, disable fd */
2183                                 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2184                                 val |= 0x20;
2185                                 lp->a.write_bcr(ioaddr, 32, val);
2186                         }
2187                 }
2188         } else {
2189                 int first_phy = -1;
2190                 u16 bmcr;
2191                 u32 bcr9;
2192                 struct ethtool_cmd ecmd;
2193
2194                 /*
2195                  * There is really no good other way to handle multiple PHYs
2196                  * other than turning off all automatics
2197                  */
2198                 val = lp->a.read_bcr(ioaddr, 2);
2199                 lp->a.write_bcr(ioaddr, 2, val & ~2);
2200                 val = lp->a.read_bcr(ioaddr, 32);
2201                 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7));   /* stop MII manager */
2202
2203                 if (!(lp->options & PCNET32_PORT_ASEL)) {
2204                         /* setup ecmd */
2205                         ecmd.port = PORT_MII;
2206                         ecmd.transceiver = XCVR_INTERNAL;
2207                         ecmd.autoneg = AUTONEG_DISABLE;
2208                         ecmd.speed =
2209                             lp->
2210                             options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2211                         bcr9 = lp->a.read_bcr(ioaddr, 9);
2212
2213                         if (lp->options & PCNET32_PORT_FD) {
2214                                 ecmd.duplex = DUPLEX_FULL;
2215                                 bcr9 |= (1 << 0);
2216                         } else {
2217                                 ecmd.duplex = DUPLEX_HALF;
2218                                 bcr9 |= ~(1 << 0);
2219                         }
2220                         lp->a.write_bcr(ioaddr, 9, bcr9);
2221                 }
2222
2223                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2224                         if (lp->phymask & (1 << i)) {
2225                                 /* isolate all but the first PHY */
2226                                 bmcr = mdio_read(dev, i, MII_BMCR);
2227                                 if (first_phy == -1) {
2228                                         first_phy = i;
2229                                         mdio_write(dev, i, MII_BMCR,
2230                                                    bmcr & ~BMCR_ISOLATE);
2231                                 } else {
2232                                         mdio_write(dev, i, MII_BMCR,
2233                                                    bmcr | BMCR_ISOLATE);
2234                                 }
2235                                 /* use mii_ethtool_sset to setup PHY */
2236                                 lp->mii_if.phy_id = i;
2237                                 ecmd.phy_address = i;
2238                                 if (lp->options & PCNET32_PORT_ASEL) {
2239                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
2240                                         ecmd.autoneg = AUTONEG_ENABLE;
2241                                 }
2242                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
2243                         }
2244                 }
2245                 lp->mii_if.phy_id = first_phy;
2246                 if (netif_msg_link(lp))
2247                         printk(KERN_INFO "%s: Using PHY number %d.\n",
2248                                dev->name, first_phy);
2249         }
2250
2251 #ifdef DO_DXSUFLO
2252         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2253                 val = lp->a.read_csr(ioaddr, CSR3);
2254                 val |= 0x40;
2255                 lp->a.write_csr(ioaddr, CSR3, val);
2256         }
2257 #endif
2258
2259         lp->init_block->mode =
2260             cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2261         pcnet32_load_multicast(dev);
2262
2263         if (pcnet32_init_ring(dev)) {
2264                 rc = -ENOMEM;
2265                 goto err_free_ring;
2266         }
2267
2268         napi_enable(&lp->napi);
2269
2270         /* Re-initialize the PCNET32, and start it when done. */
2271         lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2272         lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2273
2274         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
2275         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2276
2277         netif_start_queue(dev);
2278
2279         if (lp->chip_version >= PCNET32_79C970A) {
2280                 /* Print the link status and start the watchdog */
2281                 pcnet32_check_media(dev, 1);
2282                 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
2283         }
2284
2285         i = 0;
2286         while (i++ < 100)
2287                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2288                         break;
2289         /*
2290          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2291          * reports that doing so triggers a bug in the '974.
2292          */
2293         lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2294
2295         if (netif_msg_ifup(lp))
2296                 printk(KERN_DEBUG
2297                        "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2298                        dev->name, i,
2299                        (u32) (lp->init_dma_addr),
2300                        lp->a.read_csr(ioaddr, CSR0));
2301
2302         spin_unlock_irqrestore(&lp->lock, flags);
2303
2304         return 0;               /* Always succeed */
2305
2306       err_free_ring:
2307         /* free any allocated skbuffs */
2308         pcnet32_purge_rx_ring(dev);
2309
2310         /*
2311          * Switch back to 16bit mode to avoid problems with dumb
2312          * DOS packet driver after a warm reboot
2313          */
2314         lp->a.write_bcr(ioaddr, 20, 4);
2315
2316       err_free_irq:
2317         spin_unlock_irqrestore(&lp->lock, flags);
2318         free_irq(dev->irq, dev);
2319         return rc;
2320 }
2321
2322 /*
2323  * The LANCE has been halted for one reason or another (busmaster memory
2324  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2325  * etc.).  Modern LANCE variants always reload their ring-buffer
2326  * configuration when restarted, so we must reinitialize our ring
2327  * context before restarting.  As part of this reinitialization,
2328  * find all packets still on the Tx ring and pretend that they had been
2329  * sent (in effect, drop the packets on the floor) - the higher-level
2330  * protocols will time out and retransmit.  It'd be better to shuffle
2331  * these skbs to a temp list and then actually re-Tx them after
2332  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2333  */
2334
2335 static void pcnet32_purge_tx_ring(struct net_device *dev)
2336 {
2337         struct pcnet32_private *lp = netdev_priv(dev);
2338         int i;
2339
2340         for (i = 0; i < lp->tx_ring_size; i++) {
2341                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2342                 wmb();          /* Make sure adapter sees owner change */
2343                 if (lp->tx_skbuff[i]) {
2344                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2345                                          lp->tx_skbuff[i]->len,
2346                                          PCI_DMA_TODEVICE);
2347                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2348                 }
2349                 lp->tx_skbuff[i] = NULL;
2350                 lp->tx_dma_addr[i] = 0;
2351         }
2352 }
2353
2354 /* Initialize the PCNET32 Rx and Tx rings. */
2355 static int pcnet32_init_ring(struct net_device *dev)
2356 {
2357         struct pcnet32_private *lp = netdev_priv(dev);
2358         int i;
2359
2360         lp->tx_full = 0;
2361         lp->cur_rx = lp->cur_tx = 0;
2362         lp->dirty_rx = lp->dirty_tx = 0;
2363
2364         for (i = 0; i < lp->rx_ring_size; i++) {
2365                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2366                 if (rx_skbuff == NULL) {
2367                         if (!
2368                             (rx_skbuff = lp->rx_skbuff[i] =
2369                              dev_alloc_skb(PKT_BUF_SKB))) {
2370                                 /* there is not much, we can do at this point */
2371                                 if (netif_msg_drv(lp))
2372                                         printk(KERN_ERR
2373                                                "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2374                                                dev->name);
2375                                 return -1;
2376                         }
2377                         skb_reserve(rx_skbuff, NET_IP_ALIGN);
2378                 }
2379
2380                 rmb();
2381                 if (lp->rx_dma_addr[i] == 0)
2382                         lp->rx_dma_addr[i] =
2383                             pci_map_single(lp->pci_dev, rx_skbuff->data,
2384                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2385                 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2386                 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2387                 wmb();          /* Make sure owner changes after all others are visible */
2388                 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2389         }
2390         /* The Tx buffer address is filled in as needed, but we do need to clear
2391          * the upper ownership bit. */
2392         for (i = 0; i < lp->tx_ring_size; i++) {
2393                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2394                 wmb();          /* Make sure adapter sees owner change */
2395                 lp->tx_ring[i].base = 0;
2396                 lp->tx_dma_addr[i] = 0;
2397         }
2398
2399         lp->init_block->tlen_rlen =
2400             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2401         for (i = 0; i < 6; i++)
2402                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2403         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2404         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2405         wmb();                  /* Make sure all changes are visible */
2406         return 0;
2407 }
2408
2409 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2410  * then flush the pending transmit operations, re-initialize the ring,
2411  * and tell the chip to initialize.
2412  */
2413 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2414 {
2415         struct pcnet32_private *lp = netdev_priv(dev);
2416         unsigned long ioaddr = dev->base_addr;
2417         int i;
2418
2419         /* wait for stop */
2420         for (i = 0; i < 100; i++)
2421                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2422                         break;
2423
2424         if (i >= 100 && netif_msg_drv(lp))
2425                 printk(KERN_ERR
2426                        "%s: pcnet32_restart timed out waiting for stop.\n",
2427                        dev->name);
2428
2429         pcnet32_purge_tx_ring(dev);
2430         if (pcnet32_init_ring(dev))
2431                 return;
2432
2433         /* ReInit Ring */
2434         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2435         i = 0;
2436         while (i++ < 1000)
2437                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2438                         break;
2439
2440         lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2441 }
2442
2443 static void pcnet32_tx_timeout(struct net_device *dev)
2444 {
2445         struct pcnet32_private *lp = netdev_priv(dev);
2446         unsigned long ioaddr = dev->base_addr, flags;
2447
2448         spin_lock_irqsave(&lp->lock, flags);
2449         /* Transmitter timeout, serious problems. */
2450         if (pcnet32_debug & NETIF_MSG_DRV)
2451                 printk(KERN_ERR
2452                        "%s: transmit timed out, status %4.4x, resetting.\n",
2453                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2454         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2455         dev->stats.tx_errors++;
2456         if (netif_msg_tx_err(lp)) {
2457                 int i;
2458                 printk(KERN_DEBUG
2459                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2460                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2461                        lp->cur_rx);
2462                 for (i = 0; i < lp->rx_ring_size; i++)
2463                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2464                                le32_to_cpu(lp->rx_ring[i].base),
2465                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2466                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2467                                le16_to_cpu(lp->rx_ring[i].status));
2468                 for (i = 0; i < lp->tx_ring_size; i++)
2469                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2470                                le32_to_cpu(lp->tx_ring[i].base),
2471                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2472                                le32_to_cpu(lp->tx_ring[i].misc),
2473                                le16_to_cpu(lp->tx_ring[i].status));
2474                 printk("\n");
2475         }
2476         pcnet32_restart(dev, CSR0_NORMAL);
2477
2478         dev->trans_start = jiffies;
2479         netif_wake_queue(dev);
2480
2481         spin_unlock_irqrestore(&lp->lock, flags);
2482 }
2483
2484 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2485 {
2486         struct pcnet32_private *lp = netdev_priv(dev);
2487         unsigned long ioaddr = dev->base_addr;
2488         u16 status;
2489         int entry;
2490         unsigned long flags;
2491
2492         spin_lock_irqsave(&lp->lock, flags);
2493
2494         if (netif_msg_tx_queued(lp)) {
2495                 printk(KERN_DEBUG
2496                        "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2497                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2498         }
2499
2500         /* Default status -- will not enable Successful-TxDone
2501          * interrupt when that option is available to us.
2502          */
2503         status = 0x8300;
2504
2505         /* Fill in a Tx ring entry */
2506
2507         /* Mask to ring buffer boundary. */
2508         entry = lp->cur_tx & lp->tx_mod_mask;
2509
2510         /* Caution: the write order is important here, set the status
2511          * with the "ownership" bits last. */
2512
2513         lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2514
2515         lp->tx_ring[entry].misc = 0x00000000;
2516
2517         lp->tx_skbuff[entry] = skb;
2518         lp->tx_dma_addr[entry] =
2519             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2520         lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2521         wmb();                  /* Make sure owner changes after all others are visible */
2522         lp->tx_ring[entry].status = cpu_to_le16(status);
2523
2524         lp->cur_tx++;
2525         dev->stats.tx_bytes += skb->len;
2526
2527         /* Trigger an immediate send poll. */
2528         lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2529
2530         dev->trans_start = jiffies;
2531
2532         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2533                 lp->tx_full = 1;
2534                 netif_stop_queue(dev);
2535         }
2536         spin_unlock_irqrestore(&lp->lock, flags);
2537         return 0;
2538 }
2539
2540 /* The PCNET32 interrupt handler. */
2541 static irqreturn_t
2542 pcnet32_interrupt(int irq, void *dev_id)
2543 {
2544         struct net_device *dev = dev_id;
2545         struct pcnet32_private *lp;
2546         unsigned long ioaddr;
2547         u16 csr0;
2548         int boguscnt = max_interrupt_work;
2549
2550         ioaddr = dev->base_addr;
2551         lp = netdev_priv(dev);
2552
2553         spin_lock(&lp->lock);
2554
2555         csr0 = lp->a.read_csr(ioaddr, CSR0);
2556         while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2557                 if (csr0 == 0xffff) {
2558                         break;  /* PCMCIA remove happened */
2559                 }
2560                 /* Acknowledge all of the current interrupt sources ASAP. */
2561                 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2562
2563                 if (netif_msg_intr(lp))
2564                         printk(KERN_DEBUG
2565                                "%s: interrupt  csr0=%#2.2x new csr=%#2.2x.\n",
2566                                dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2567
2568                 /* Log misc errors. */
2569                 if (csr0 & 0x4000)
2570                         dev->stats.tx_errors++; /* Tx babble. */
2571                 if (csr0 & 0x1000) {
2572                         /*
2573                          * This happens when our receive ring is full. This
2574                          * shouldn't be a problem as we will see normal rx
2575                          * interrupts for the frames in the receive ring.  But
2576                          * there are some PCI chipsets (I can reproduce this
2577                          * on SP3G with Intel saturn chipset) which have
2578                          * sometimes problems and will fill up the receive
2579                          * ring with error descriptors.  In this situation we
2580                          * don't get a rx interrupt, but a missed frame
2581                          * interrupt sooner or later.
2582                          */
2583                         dev->stats.rx_errors++; /* Missed a Rx frame. */
2584                 }
2585                 if (csr0 & 0x0800) {
2586                         if (netif_msg_drv(lp))
2587                                 printk(KERN_ERR
2588                                        "%s: Bus master arbitration failure, status %4.4x.\n",
2589                                        dev->name, csr0);
2590                         /* unlike for the lance, there is no restart needed */
2591                 }
2592                 if (napi_schedule_prep(&lp->napi)) {
2593                         u16 val;
2594                         /* set interrupt masks */
2595                         val = lp->a.read_csr(ioaddr, CSR3);
2596                         val |= 0x5f00;
2597                         lp->a.write_csr(ioaddr, CSR3, val);
2598
2599                         __napi_schedule(&lp->napi);
2600                         break;
2601                 }
2602                 csr0 = lp->a.read_csr(ioaddr, CSR0);
2603         }
2604
2605         if (netif_msg_intr(lp))
2606                 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2607                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2608
2609         spin_unlock(&lp->lock);
2610
2611         return IRQ_HANDLED;
2612 }
2613
2614 static int pcnet32_close(struct net_device *dev)
2615 {
2616         unsigned long ioaddr = dev->base_addr;
2617         struct pcnet32_private *lp = netdev_priv(dev);
2618         unsigned long flags;
2619
2620         del_timer_sync(&lp->watchdog_timer);
2621
2622         netif_stop_queue(dev);
2623         napi_disable(&lp->napi);
2624
2625         spin_lock_irqsave(&lp->lock, flags);
2626
2627         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2628
2629         if (netif_msg_ifdown(lp))
2630                 printk(KERN_DEBUG
2631                        "%s: Shutting down ethercard, status was %2.2x.\n",
2632                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2633
2634         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2635         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2636
2637         /*
2638          * Switch back to 16bit mode to avoid problems with dumb
2639          * DOS packet driver after a warm reboot
2640          */
2641         lp->a.write_bcr(ioaddr, 20, 4);
2642
2643         spin_unlock_irqrestore(&lp->lock, flags);
2644
2645         free_irq(dev->irq, dev);
2646
2647         spin_lock_irqsave(&lp->lock, flags);
2648
2649         pcnet32_purge_rx_ring(dev);
2650         pcnet32_purge_tx_ring(dev);
2651
2652         spin_unlock_irqrestore(&lp->lock, flags);
2653
2654         return 0;
2655 }
2656
2657 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2658 {
2659         struct pcnet32_private *lp = netdev_priv(dev);
2660         unsigned long ioaddr = dev->base_addr;
2661         unsigned long flags;
2662
2663         spin_lock_irqsave(&lp->lock, flags);
2664         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2665         spin_unlock_irqrestore(&lp->lock, flags);
2666
2667         return &dev->stats;
2668 }
2669
2670 /* taken from the sunlance driver, which it took from the depca driver */
2671 static void pcnet32_load_multicast(struct net_device *dev)
2672 {
2673         struct pcnet32_private *lp = netdev_priv(dev);
2674         volatile struct pcnet32_init_block *ib = lp->init_block;
2675         volatile __le16 *mcast_table = (__le16 *)ib->filter;
2676         struct dev_mc_list *dmi = dev->mc_list;
2677         unsigned long ioaddr = dev->base_addr;
2678         char *addrs;
2679         int i;
2680         u32 crc;
2681
2682         /* set all multicast bits */
2683         if (dev->flags & IFF_ALLMULTI) {
2684                 ib->filter[0] = cpu_to_le32(~0U);
2685                 ib->filter[1] = cpu_to_le32(~0U);
2686                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2687                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2688                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2689                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2690                 return;
2691         }
2692         /* clear the multicast filter */
2693         ib->filter[0] = 0;
2694         ib->filter[1] = 0;
2695
2696         /* Add addresses */
2697         for (i = 0; i < dev->mc_count; i++) {
2698                 addrs = dmi->dmi_addr;
2699                 dmi = dmi->next;
2700
2701                 /* multicast address? */
2702                 if (!(*addrs & 1))
2703                         continue;
2704
2705                 crc = ether_crc_le(6, addrs);
2706                 crc = crc >> 26;
2707                 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2708         }
2709         for (i = 0; i < 4; i++)
2710                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2711                                 le16_to_cpu(mcast_table[i]));
2712         return;
2713 }
2714
2715 /*
2716  * Set or clear the multicast filter for this adaptor.
2717  */
2718 static void pcnet32_set_multicast_list(struct net_device *dev)
2719 {
2720         unsigned long ioaddr = dev->base_addr, flags;
2721         struct pcnet32_private *lp = netdev_priv(dev);
2722         int csr15, suspended;
2723
2724         spin_lock_irqsave(&lp->lock, flags);
2725         suspended = pcnet32_suspend(dev, &flags, 0);
2726         csr15 = lp->a.read_csr(ioaddr, CSR15);
2727         if (dev->flags & IFF_PROMISC) {
2728                 /* Log any net taps. */
2729                 if (netif_msg_hw(lp))
2730                         printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2731                                dev->name);
2732                 lp->init_block->mode =
2733                     cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2734                                 7);
2735                 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2736         } else {
2737                 lp->init_block->mode =
2738                     cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2739                 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2740                 pcnet32_load_multicast(dev);
2741         }
2742
2743         if (suspended) {
2744                 int csr5;
2745                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2746                 csr5 = lp->a.read_csr(ioaddr, CSR5);
2747                 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2748         } else {
2749                 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2750                 pcnet32_restart(dev, CSR0_NORMAL);
2751                 netif_wake_queue(dev);
2752         }
2753
2754         spin_unlock_irqrestore(&lp->lock, flags);
2755 }
2756
2757 /* This routine assumes that the lp->lock is held */
2758 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2759 {
2760         struct pcnet32_private *lp = netdev_priv(dev);
2761         unsigned long ioaddr = dev->base_addr;
2762         u16 val_out;
2763
2764         if (!lp->mii)
2765                 return 0;
2766
2767         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2768         val_out = lp->a.read_bcr(ioaddr, 34);
2769
2770         return val_out;
2771 }
2772
2773 /* This routine assumes that the lp->lock is held */
2774 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2775 {
2776         struct pcnet32_private *lp = netdev_priv(dev);
2777         unsigned long ioaddr = dev->base_addr;
2778
2779         if (!lp->mii)
2780                 return;
2781
2782         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2783         lp->a.write_bcr(ioaddr, 34, val);
2784 }
2785
2786 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2787 {
2788         struct pcnet32_private *lp = netdev_priv(dev);
2789         int rc;
2790         unsigned long flags;
2791
2792         /* SIOC[GS]MIIxxx ioctls */
2793         if (lp->mii) {
2794                 spin_lock_irqsave(&lp->lock, flags);
2795                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2796                 spin_unlock_irqrestore(&lp->lock, flags);
2797         } else {
2798                 rc = -EOPNOTSUPP;
2799         }
2800
2801         return rc;
2802 }
2803
2804 static int pcnet32_check_otherphy(struct net_device *dev)
2805 {
2806         struct pcnet32_private *lp = netdev_priv(dev);
2807         struct mii_if_info mii = lp->mii_if;
2808         u16 bmcr;
2809         int i;
2810
2811         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2812                 if (i == lp->mii_if.phy_id)
2813                         continue;       /* skip active phy */
2814                 if (lp->phymask & (1 << i)) {
2815                         mii.phy_id = i;
2816                         if (mii_link_ok(&mii)) {
2817                                 /* found PHY with active link */
2818                                 if (netif_msg_link(lp))
2819                                         printk(KERN_INFO
2820                                                "%s: Using PHY number %d.\n",
2821                                                dev->name, i);
2822
2823                                 /* isolate inactive phy */
2824                                 bmcr =
2825                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2826                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2827                                            bmcr | BMCR_ISOLATE);
2828
2829                                 /* de-isolate new phy */
2830                                 bmcr = mdio_read(dev, i, MII_BMCR);
2831                                 mdio_write(dev, i, MII_BMCR,
2832                                            bmcr & ~BMCR_ISOLATE);
2833
2834                                 /* set new phy address */
2835                                 lp->mii_if.phy_id = i;
2836                                 return 1;
2837                         }
2838                 }
2839         }
2840         return 0;
2841 }
2842
2843 /*
2844  * Show the status of the media.  Similar to mii_check_media however it
2845  * correctly shows the link speed for all (tested) pcnet32 variants.
2846  * Devices with no mii just report link state without speed.
2847  *
2848  * Caller is assumed to hold and release the lp->lock.
2849  */
2850
2851 static void pcnet32_check_media(struct net_device *dev, int verbose)
2852 {
2853         struct pcnet32_private *lp = netdev_priv(dev);
2854         int curr_link;
2855         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2856         u32 bcr9;
2857
2858         if (lp->mii) {
2859                 curr_link = mii_link_ok(&lp->mii_if);
2860         } else {
2861                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2862                 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2863         }
2864         if (!curr_link) {
2865                 if (prev_link || verbose) {
2866                         netif_carrier_off(dev);
2867                         if (netif_msg_link(lp))
2868                                 printk(KERN_INFO "%s: link down\n", dev->name);
2869                 }
2870                 if (lp->phycount > 1) {
2871                         curr_link = pcnet32_check_otherphy(dev);
2872                         prev_link = 0;
2873                 }
2874         } else if (verbose || !prev_link) {
2875                 netif_carrier_on(dev);
2876                 if (lp->mii) {
2877                         if (netif_msg_link(lp)) {
2878                                 struct ethtool_cmd ecmd;
2879                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2880                                 printk(KERN_INFO
2881                                        "%s: link up, %sMbps, %s-duplex\n",
2882                                        dev->name,
2883                                        (ecmd.speed == SPEED_100) ? "100" : "10",
2884                                        (ecmd.duplex ==
2885                                         DUPLEX_FULL) ? "full" : "half");
2886                         }
2887                         bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2888                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2889                                 if (lp->mii_if.full_duplex)
2890                                         bcr9 |= (1 << 0);
2891                                 else
2892                                         bcr9 &= ~(1 << 0);
2893                                 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2894                         }
2895                 } else {
2896                         if (netif_msg_link(lp))
2897                                 printk(KERN_INFO "%s: link up\n", dev->name);
2898                 }
2899         }
2900 }
2901
2902 /*
2903  * Check for loss of link and link establishment.
2904  * Can not use mii_check_media because it does nothing if mode is forced.
2905  */
2906
2907 static void pcnet32_watchdog(struct net_device *dev)
2908 {
2909         struct pcnet32_private *lp = netdev_priv(dev);
2910         unsigned long flags;
2911
2912         /* Print the link status if it has changed */
2913         spin_lock_irqsave(&lp->lock, flags);
2914         pcnet32_check_media(dev, 0);
2915         spin_unlock_irqrestore(&lp->lock, flags);
2916
2917         mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
2918 }
2919
2920 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2921 {
2922         struct net_device *dev = pci_get_drvdata(pdev);
2923
2924         if (netif_running(dev)) {
2925                 netif_device_detach(dev);
2926                 pcnet32_close(dev);
2927         }
2928         pci_save_state(pdev);
2929         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2930         return 0;
2931 }
2932
2933 static int pcnet32_pm_resume(struct pci_dev *pdev)
2934 {
2935         struct net_device *dev = pci_get_drvdata(pdev);
2936
2937         pci_set_power_state(pdev, PCI_D0);
2938         pci_restore_state(pdev);
2939
2940         if (netif_running(dev)) {
2941                 pcnet32_open(dev);
2942                 netif_device_attach(dev);
2943         }
2944         return 0;
2945 }
2946
2947 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2948 {
2949         struct net_device *dev = pci_get_drvdata(pdev);
2950
2951         if (dev) {
2952                 struct pcnet32_private *lp = netdev_priv(dev);
2953
2954                 unregister_netdev(dev);
2955                 pcnet32_free_ring(dev);
2956                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2957                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2958                                     lp->init_block, lp->init_dma_addr);
2959                 free_netdev(dev);
2960                 pci_disable_device(pdev);
2961                 pci_set_drvdata(pdev, NULL);
2962         }
2963 }
2964
2965 static struct pci_driver pcnet32_driver = {
2966         .name = DRV_NAME,
2967         .probe = pcnet32_probe_pci,
2968         .remove = __devexit_p(pcnet32_remove_one),
2969         .id_table = pcnet32_pci_tbl,
2970         .suspend = pcnet32_pm_suspend,
2971         .resume = pcnet32_pm_resume,
2972 };
2973
2974 /* An additional parameter that may be passed in... */
2975 static int debug = -1;
2976 static int tx_start_pt = -1;
2977 static int pcnet32_have_pci;
2978
2979 module_param(debug, int, 0);
2980 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2981 module_param(max_interrupt_work, int, 0);
2982 MODULE_PARM_DESC(max_interrupt_work,
2983                  DRV_NAME " maximum events handled per interrupt");
2984 module_param(rx_copybreak, int, 0);
2985 MODULE_PARM_DESC(rx_copybreak,
2986                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2987 module_param(tx_start_pt, int, 0);
2988 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2989 module_param(pcnet32vlb, int, 0);
2990 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2991 module_param_array(options, int, NULL, 0);
2992 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2993 module_param_array(full_duplex, int, NULL, 0);
2994 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2995 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2996 module_param_array(homepna, int, NULL, 0);
2997 MODULE_PARM_DESC(homepna,
2998                  DRV_NAME
2999                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3000
3001 MODULE_AUTHOR("Thomas Bogendoerfer");
3002 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3003 MODULE_LICENSE("GPL");
3004
3005 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3006
3007 static int __init pcnet32_init_module(void)
3008 {
3009         printk(KERN_INFO "%s", version);
3010
3011         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3012
3013         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3014                 tx_start = tx_start_pt;
3015
3016         /* find the PCI devices */
3017         if (!pci_register_driver(&pcnet32_driver))
3018                 pcnet32_have_pci = 1;
3019
3020         /* should we find any remaining VLbus devices ? */
3021         if (pcnet32vlb)
3022                 pcnet32_probe_vlbus(pcnet32_portlist);
3023
3024         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3025                 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
3026
3027         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3028 }
3029
3030 static void __exit pcnet32_cleanup_module(void)
3031 {
3032         struct net_device *next_dev;
3033
3034         while (pcnet32_dev) {
3035                 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3036                 next_dev = lp->next;
3037                 unregister_netdev(pcnet32_dev);
3038                 pcnet32_free_ring(pcnet32_dev);
3039                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3040                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3041                                     lp->init_block, lp->init_dma_addr);
3042                 free_netdev(pcnet32_dev);
3043                 pcnet32_dev = next_dev;
3044         }
3045
3046         if (pcnet32_have_pci)
3047                 pci_unregister_driver(&pcnet32_driver);
3048 }
3049
3050 module_init(pcnet32_init_module);
3051 module_exit(pcnet32_cleanup_module);
3052
3053 /*
3054  * Local variables:
3055  *  c-indent-level: 4
3056  *  tab-width: 8
3057  * End:
3058  */