drivers/net/myri10ge/myri10ge.c

   1 /*************************************************************************
   2  * myri10ge.c: Myricom Myri-10G Ethernet driver.
   3  *
   4  * Copyright (C) 2005 - 2009 Myricom, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of Myricom, Inc. nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *
  32  * If the eeprom on your board is not recent enough, you will need to get a
  33  * newer firmware image at:
  34  *   http://www.myri.com/scs/download-Myri10GE.html
  35  *
  36  * Contact Information:
  37  *   <help@myri.com>
  38  *   Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
  39  *************************************************************************/
  40
  41 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  42
  43 #include <linux/tcp.h>
  44 #include <linux/netdevice.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/string.h>
  47 #include <linux/module.h>
  48 #include <linux/pci.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/if_ether.h>
  52 #include <linux/if_vlan.h>
  53 #include <linux/inet_lro.h>
  54 #include <linux/dca.h>
  55 #include <linux/ip.h>
  56 #include <linux/inet.h>
  57 #include <linux/in.h>
  58 #include <linux/ethtool.h>
  59 #include <linux/firmware.h>
  60 #include <linux/delay.h>
  61 #include <linux/timer.h>
  62 #include <linux/vmalloc.h>
  63 #include <linux/crc32.h>
  64 #include <linux/moduleparam.h>
  65 #include <linux/io.h>
  66 #include <linux/log2.h>
  67 #include <linux/slab.h>
  68 #include <net/checksum.h>
  69 #include <net/ip.h>
  70 #include <net/tcp.h>
  71 #include <asm/byteorder.h>
  72 #include <asm/io.h>
  73 #include <asm/processor.h>
  74 #ifdef CONFIG_MTRR
  75 #include <asm/mtrr.h>
  76 #endif
  77
  78 #include "myri10ge_mcp.h"
  79 #include "myri10ge_mcp_gen_header.h"
  80
  81 #define MYRI10GE_VERSION_STR "1.5.2-1.459"
  82
  83 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
  84 MODULE_AUTHOR("Maintainer: help@myri.com");
  85 MODULE_VERSION(MYRI10GE_VERSION_STR);
  86 MODULE_LICENSE("Dual BSD/GPL");
  87
  88 #define MYRI10GE_MAX_ETHER_MTU 9014
  89
  90 #define MYRI10GE_ETH_STOPPED 0
  91 #define MYRI10GE_ETH_STOPPING 1
  92 #define MYRI10GE_ETH_STARTING 2
  93 #define MYRI10GE_ETH_RUNNING 3
  94 #define MYRI10GE_ETH_OPEN_FAILED 4
  95
  96 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
  97 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
  98 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
  99 #define MYRI10GE_LRO_MAX_PKTS 64
 100
 101 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
 102 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
 103
 104 #define MYRI10GE_ALLOC_ORDER 0
 105 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
 106 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
 107
 108 #define MYRI10GE_MAX_SLICES 32
 109
 110 struct myri10ge_rx_buffer_state {
 111         struct page *page;
 112         int page_offset;
 113         DEFINE_DMA_UNMAP_ADDR(bus);
 114         DEFINE_DMA_UNMAP_LEN(len);
 115 };
 116
 117 struct myri10ge_tx_buffer_state {
 118         struct sk_buff *skb;
 119         int last;
 120         DEFINE_DMA_UNMAP_ADDR(bus);
 121         DEFINE_DMA_UNMAP_LEN(len);
 122 };
 123
 124 struct myri10ge_cmd {
 125         u32 data0;
 126         u32 data1;
 127         u32 data2;
 128 };
 129
 130 struct myri10ge_rx_buf {
 131         struct mcp_kreq_ether_recv __iomem *lanai;      /* lanai ptr for recv ring */
 132         struct mcp_kreq_ether_recv *shadow;     /* host shadow of recv ring */
 133         struct myri10ge_rx_buffer_state *info;
 134         struct page *page;
 135         dma_addr_t bus;
 136         int page_offset;
 137         int cnt;
 138         int fill_cnt;
 139         int alloc_fail;
 140         int mask;               /* number of rx slots -1 */
 141         int watchdog_needed;
 142 };
 143
 144 struct myri10ge_tx_buf {
 145         struct mcp_kreq_ether_send __iomem *lanai;      /* lanai ptr for sendq */
 146         __be32 __iomem *send_go;        /* "go" doorbell ptr */
 147         __be32 __iomem *send_stop;      /* "stop" doorbell ptr */
 148         struct mcp_kreq_ether_send *req_list;   /* host shadow of sendq */
 149         char *req_bytes;
 150         struct myri10ge_tx_buffer_state *info;
 151         int mask;               /* number of transmit slots -1  */
 152         int req ____cacheline_aligned;  /* transmit slots submitted     */
 153         int pkt_start;          /* packets started */
 154         int stop_queue;
 155         int linearized;
 156         int done ____cacheline_aligned; /* transmit slots completed     */
 157         int pkt_done;           /* packets completed */
 158         int wake_queue;
 159         int queue_active;
 160 };
 161
 162 struct myri10ge_rx_done {
 163         struct mcp_slot *entry;
 164         dma_addr_t bus;
 165         int cnt;
 166         int idx;
 167         struct net_lro_mgr lro_mgr;
 168         struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
 169 };
 170
 171 struct myri10ge_slice_netstats {
 172         unsigned long rx_packets;
 173         unsigned long tx_packets;
 174         unsigned long rx_bytes;
 175         unsigned long tx_bytes;
 176         unsigned long rx_dropped;
 177         unsigned long tx_dropped;
 178 };
 179
 180 struct myri10ge_slice_state {
 181         struct myri10ge_tx_buf tx;      /* transmit ring        */
 182         struct myri10ge_rx_buf rx_small;
 183         struct myri10ge_rx_buf rx_big;
 184         struct myri10ge_rx_done rx_done;
 185         struct net_device *dev;
 186         struct napi_struct napi;
 187         struct myri10ge_priv *mgp;
 188         struct myri10ge_slice_netstats stats;
 189         __be32 __iomem *irq_claim;
 190         struct mcp_irq_data *fw_stats;
 191         dma_addr_t fw_stats_bus;
 192         int watchdog_tx_done;
 193         int watchdog_tx_req;
 194         int watchdog_rx_done;
 195 #ifdef CONFIG_MYRI10GE_DCA
 196         int cached_dca_tag;
 197         int cpu;
 198         __be32 __iomem *dca_tag;
 199 #endif
 200         char irq_desc[32];
 201 };
 202
 203 struct myri10ge_priv {
 204         struct myri10ge_slice_state *ss;
 205         int tx_boundary;        /* boundary transmits cannot cross */
 206         int num_slices;
 207         int running;            /* running?             */
 208         int csum_flag;          /* rx_csums?            */
 209         int small_bytes;
 210         int big_bytes;
 211         int max_intr_slots;
 212         struct net_device *dev;
 213         spinlock_t stats_lock;
 214         u8 __iomem *sram;
 215         int sram_size;
 216         unsigned long board_span;
 217         unsigned long iomem_base;
 218         __be32 __iomem *irq_deassert;
 219         char *mac_addr_string;
 220         struct mcp_cmd_response *cmd;
 221         dma_addr_t cmd_bus;
 222         struct pci_dev *pdev;
 223         int msi_enabled;
 224         int msix_enabled;
 225         struct msix_entry *msix_vectors;
 226 #ifdef CONFIG_MYRI10GE_DCA
 227         int dca_enabled;
 228         int relaxed_order;
 229 #endif
 230         u32 link_state;
 231         unsigned int rdma_tags_available;
 232         int intr_coal_delay;
 233         __be32 __iomem *intr_coal_delay_ptr;
 234         int mtrr;
 235         int wc_enabled;
 236         int down_cnt;
 237         wait_queue_head_t down_wq;
 238         struct work_struct watchdog_work;
 239         struct timer_list watchdog_timer;
 240         int watchdog_resets;
 241         int watchdog_pause;
 242         int pause;
 243         bool fw_name_allocated;
 244         char *fw_name;
 245         char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
 246         char *product_code_string;
 247         char fw_version[128];
 248         int fw_ver_major;
 249         int fw_ver_minor;
 250         int fw_ver_tiny;
 251         int adopted_rx_filter_bug;
 252         u8 mac_addr[6];         /* eeprom mac address */
 253         unsigned long serial_number;
 254         int vendor_specific_offset;
 255         int fw_multicast_support;
 256         u32 features;
 257         u32 max_tso6;
 258         u32 read_dma;
 259         u32 write_dma;
 260         u32 read_write_dma;
 261         u32 link_changes;
 262         u32 msg_enable;
 263         unsigned int board_number;
 264         int rebooted;
 265 };
 266
 267 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
 268 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
 269 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
 270 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
 271 MODULE_FIRMWARE("myri10ge_ethp_z8e.dat");
 272 MODULE_FIRMWARE("myri10ge_eth_z8e.dat");
 273 MODULE_FIRMWARE("myri10ge_rss_ethp_z8e.dat");
 274 MODULE_FIRMWARE("myri10ge_rss_eth_z8e.dat");
 275
 276 /* Careful: must be accessed under kparam_block_sysfs_write */
 277 static char *myri10ge_fw_name = NULL;
 278 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
 279 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
 280
 281 #define MYRI10GE_MAX_BOARDS 8
 282 static char *myri10ge_fw_names[MYRI10GE_MAX_BOARDS] =
 283     {[0 ... (MYRI10GE_MAX_BOARDS - 1)] = NULL };
 284 module_param_array_named(myri10ge_fw_names, myri10ge_fw_names, charp, NULL,
 285                          0444);
 286 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image names per board");
 287
 288 static int myri10ge_ecrc_enable = 1;
 289 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
 290 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
 291
 292 static int myri10ge_small_bytes = -1;   /* -1 == auto */
 293 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
 294 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
 295
 296 static int myri10ge_msi = 1;    /* enable msi by default */
 297 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
 298 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
 299
 300 static int myri10ge_intr_coal_delay = 75;
 301 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
 302 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
 303
 304 static int myri10ge_flow_control = 1;
 305 module_param(myri10ge_flow_control, int, S_IRUGO);
 306 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
 307
 308 static int myri10ge_deassert_wait = 1;
 309 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
 310 MODULE_PARM_DESC(myri10ge_deassert_wait,
 311                  "Wait when deasserting legacy interrupts");
 312
 313 static int myri10ge_force_firmware = 0;
 314 module_param(myri10ge_force_firmware, int, S_IRUGO);
 315 MODULE_PARM_DESC(myri10ge_force_firmware,
 316                  "Force firmware to assume aligned completions");
 317
 318 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
 319 module_param(myri10ge_initial_mtu, int, S_IRUGO);
 320 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
 321
 322 static int myri10ge_napi_weight = 64;
 323 module_param(myri10ge_napi_weight, int, S_IRUGO);
 324 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
 325
 326 static int myri10ge_watchdog_timeout = 1;
 327 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
 328 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
 329
 330 static int myri10ge_max_irq_loops = 1048576;
 331 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
 332 MODULE_PARM_DESC(myri10ge_max_irq_loops,
 333                  "Set stuck legacy IRQ detection threshold");
 334
 335 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
 336
 337 static int myri10ge_debug = -1; /* defaults above */
 338 module_param(myri10ge_debug, int, 0);
 339 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
 340
 341 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
 342 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
 343 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
 344                  "Number of LRO packets to be aggregated");
 345
 346 static int myri10ge_fill_thresh = 256;
 347 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
 348 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
 349
 350 static int myri10ge_reset_recover = 1;
 351
 352 static int myri10ge_max_slices = 1;
 353 module_param(myri10ge_max_slices, int, S_IRUGO);
 354 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
 355
 356 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
 357 module_param(myri10ge_rss_hash, int, S_IRUGO);
 358 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
 359
 360 static int myri10ge_dca = 1;
 361 module_param(myri10ge_dca, int, S_IRUGO);
 362 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
 363
 364 #define MYRI10GE_FW_OFFSET 1024*1024
 365 #define MYRI10GE_HIGHPART_TO_U32(X) \
 366 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
 367 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
 368
 369 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
 370
 371 static void myri10ge_set_multicast_list(struct net_device *dev);
 372 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
 373                                          struct net_device *dev);
 374
 375 static inline void put_be32(__be32 val, __be32 __iomem * p)
 376 {
 377         __raw_writel((__force __u32) val, (__force void __iomem *)p);
 378 }
 379
 380 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev);
 381
 382 static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
 383 {
 384         if (mgp->fw_name_allocated)
 385                 kfree(mgp->fw_name);
 386         mgp->fw_name = name;
 387         mgp->fw_name_allocated = allocated;
 388 }
 389
 390 static int
 391 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
 392                   struct myri10ge_cmd *data, int atomic)
 393 {
 394         struct mcp_cmd *buf;
 395         char buf_bytes[sizeof(*buf) + 8];
 396         struct mcp_cmd_response *response = mgp->cmd;
 397         char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
 398         u32 dma_low, dma_high, result, value;
 399         int sleep_total = 0;
 400
 401         /* ensure buf is aligned to 8 bytes */
 402         buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
 403
 404         buf->data0 = htonl(data->data0);
 405         buf->data1 = htonl(data->data1);
 406         buf->data2 = htonl(data->data2);
 407         buf->cmd = htonl(cmd);
 408         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 409         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 410
 411         buf->response_addr.low = htonl(dma_low);
 412         buf->response_addr.high = htonl(dma_high);
 413         response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
 414         mb();
 415         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
 416
 417         /* wait up to 15ms. Longest command is the DMA benchmark,
 418          * which is capped at 5ms, but runs from a timeout handler
 419          * that runs every 7.8ms. So a 15ms timeout leaves us with
 420          * a 2.2ms margin
 421          */
 422         if (atomic) {
 423                 /* if atomic is set, do not sleep,
 424                  * and try to get the completion quickly
 425                  * (1ms will be enough for those commands) */
 426                 for (sleep_total = 0;
 427                      sleep_total < 1000 &&
 428                      response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 429                      sleep_total += 10) {
 430                         udelay(10);
 431                         mb();
 432                 }
 433         } else {
 434                 /* use msleep for most command */
 435                 for (sleep_total = 0;
 436                      sleep_total < 15 &&
 437                      response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 438                      sleep_total++)
 439                         msleep(1);
 440         }
 441
 442         result = ntohl(response->result);
 443         value = ntohl(response->data);
 444         if (result != MYRI10GE_NO_RESPONSE_RESULT) {
 445                 if (result == 0) {
 446                         data->data0 = value;
 447                         return 0;
 448                 } else if (result == MXGEFW_CMD_UNKNOWN) {
 449                         return -ENOSYS;
 450                 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
 451                         return -E2BIG;
 452                 } else if (result == MXGEFW_CMD_ERROR_RANGE &&
 453                            cmd == MXGEFW_CMD_ENABLE_RSS_QUEUES &&
 454                            (data->
 455                             data1 & MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES) !=
 456                            0) {
 457                         return -ERANGE;
 458                 } else {
 459                         dev_err(&mgp->pdev->dev,
 460                                 "command %d failed, result = %d\n",
 461                                 cmd, result);
 462                         return -ENXIO;
 463                 }
 464         }
 465
 466         dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
 467                 cmd, result);
 468         return -EAGAIN;
 469 }
 470
 471 /*
 472  * The eeprom strings on the lanaiX have the format
 473  * SN=x\0
 474  * MAC=x:x:x:x:x:x\0
 475  * PT:ddd mmm xx xx:xx:xx xx\0
 476  * PV:ddd mmm xx xx:xx:xx xx\0
 477  */
 478 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
 479 {
 480         char *ptr, *limit;
 481         int i;
 482
 483         ptr = mgp->eeprom_strings;
 484         limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
 485
 486         while (*ptr != '\0' && ptr < limit) {
 487                 if (memcmp(ptr, "MAC=", 4) == 0) {
 488                         ptr += 4;
 489                         mgp->mac_addr_string = ptr;
 490                         for (i = 0; i < 6; i++) {
 491                                 if ((ptr + 2) > limit)
 492                                         goto abort;
 493                                 mgp->mac_addr[i] =
 494                                     simple_strtoul(ptr, &ptr, 16);
 495                                 ptr += 1;
 496                         }
 497                 }
 498                 if (memcmp(ptr, "PC=", 3) == 0) {
 499                         ptr += 3;
 500                         mgp->product_code_string = ptr;
 501                 }
 502                 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
 503                         ptr += 3;
 504                         mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
 505                 }
 506                 while (ptr < limit && *ptr++) ;
 507         }
 508
 509         return 0;
 510
 511 abort:
 512         dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
 513         return -ENXIO;
 514 }
 515
 516 /*
 517  * Enable or disable periodic RDMAs from the host to make certain
 518  * chipsets resend dropped PCIe messages
 519  */
 520
 521 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 522 {
 523         char __iomem *submit;
 524         __be32 buf[16] __attribute__ ((__aligned__(8)));
 525         u32 dma_low, dma_high;
 526         int i;
 527
 528         /* clear confirmation addr */
 529         mgp->cmd->data = 0;
 530         mb();
 531
 532         /* send a rdma command to the PCIe engine, and wait for the
 533          * response in the confirmation address.  The firmware should
 534          * write a -1 there to indicate it is alive and well
 535          */
 536         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 537         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 538
 539         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 540         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 541         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 542         buf[3] = htonl(dma_high);       /* dummy addr MSW */
 543         buf[4] = htonl(dma_low);        /* dummy addr LSW */
 544         buf[5] = htonl(enable); /* enable? */
 545
 546         submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
 547
 548         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 549         for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
 550                 msleep(1);
 551         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
 552                 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
 553                         (enable ? "enable" : "disable"));
 554 }
 555
 556 static int
 557 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
 558                            struct mcp_gen_header *hdr)
 559 {
 560         struct device *dev = &mgp->pdev->dev;
 561
 562         /* check firmware type */
 563         if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
 564                 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
 565                 return -EINVAL;
 566         }
 567
 568         /* save firmware version for ethtool */
 569         strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
 570
 571         sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
 572                &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
 573
 574         if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
 575               mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
 576                 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
 577                 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
 578                         MXGEFW_VERSION_MINOR);
 579                 return -EINVAL;
 580         }
 581         return 0;
 582 }
 583
 584 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
 585 {
 586         unsigned crc, reread_crc;
 587         const struct firmware *fw;
 588         struct device *dev = &mgp->pdev->dev;
 589         unsigned char *fw_readback;
 590         struct mcp_gen_header *hdr;
 591         size_t hdr_offset;
 592         int status;
 593         unsigned i;
 594
 595         if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
 596                 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
 597                         mgp->fw_name);
 598                 status = -EINVAL;
 599                 goto abort_with_nothing;
 600         }
 601
 602         /* check size */
 603
 604         if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
 605             fw->size < MCP_HEADER_PTR_OFFSET + 4) {
 606                 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
 607                 status = -EINVAL;
 608                 goto abort_with_fw;
 609         }
 610
 611         /* check id */
 612         hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
 613         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
 614                 dev_err(dev, "Bad firmware file\n");
 615                 status = -EINVAL;
 616                 goto abort_with_fw;
 617         }
 618         hdr = (void *)(fw->data + hdr_offset);
 619
 620         status = myri10ge_validate_firmware(mgp, hdr);
 621         if (status != 0)
 622                 goto abort_with_fw;
 623
 624         crc = crc32(~0, fw->data, fw->size);
 625         for (i = 0; i < fw->size; i += 256) {
 626                 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
 627                                   fw->data + i,
 628                                   min(256U, (unsigned)(fw->size - i)));
 629                 mb();
 630                 readb(mgp->sram);
 631         }
 632         fw_readback = vmalloc(fw->size);
 633         if (!fw_readback) {
 634                 status = -ENOMEM;
 635                 goto abort_with_fw;
 636         }
 637         /* corruption checking is good for parity recovery and buggy chipset */
 638         memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
 639         reread_crc = crc32(~0, fw_readback, fw->size);
 640         vfree(fw_readback);
 641         if (crc != reread_crc) {
 642                 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
 643                         (unsigned)fw->size, reread_crc, crc);
 644                 status = -EIO;
 645                 goto abort_with_fw;
 646         }
 647         *size = (u32) fw->size;
 648
 649 abort_with_fw:
 650         release_firmware(fw);
 651
 652 abort_with_nothing:
 653         return status;
 654 }
 655
 656 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
 657 {
 658         struct mcp_gen_header *hdr;
 659         struct device *dev = &mgp->pdev->dev;
 660         const size_t bytes = sizeof(struct mcp_gen_header);
 661         size_t hdr_offset;
 662         int status;
 663
 664         /* find running firmware header */
 665         hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
 666
 667         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
 668                 dev_err(dev, "Running firmware has bad header offset (%d)\n",
 669                         (int)hdr_offset);
 670                 return -EIO;
 671         }
 672
 673         /* copy header of running firmware from SRAM to host memory to
 674          * validate firmware */
 675         hdr = kmalloc(bytes, GFP_KERNEL);
 676         if (hdr == NULL) {
 677                 dev_err(dev, "could not malloc firmware hdr\n");
 678                 return -ENOMEM;
 679         }
 680         memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
 681         status = myri10ge_validate_firmware(mgp, hdr);
 682         kfree(hdr);
 683
 684         /* check to see if adopted firmware has bug where adopting
 685          * it will cause broadcasts to be filtered unless the NIC
 686          * is kept in ALLMULTI mode */
 687         if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
 688             mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
 689                 mgp->adopted_rx_filter_bug = 1;
 690                 dev_warn(dev, "Adopting fw %d.%d.%d: "
 691                          "working around rx filter bug\n",
 692                          mgp->fw_ver_major, mgp->fw_ver_minor,
 693                          mgp->fw_ver_tiny);
 694         }
 695         return status;
 696 }
 697
 698 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
 699 {
 700         struct myri10ge_cmd cmd;
 701         int status;
 702
 703         /* probe for IPv6 TSO support */
 704         mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
 705         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
 706                                    &cmd, 0);
 707         if (status == 0) {
 708                 mgp->max_tso6 = cmd.data0;
 709                 mgp->features |= NETIF_F_TSO6;
 710         }
 711
 712         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
 713         if (status != 0) {
 714                 dev_err(&mgp->pdev->dev,
 715                         "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
 716                 return -ENXIO;
 717         }
 718
 719         mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
 720
 721         return 0;
 722 }
 723
 724 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
 725 {
 726         char __iomem *submit;
 727         __be32 buf[16] __attribute__ ((__aligned__(8)));
 728         u32 dma_low, dma_high, size;
 729         int status, i;
 730
 731         size = 0;
 732         status = myri10ge_load_hotplug_firmware(mgp, &size);
 733         if (status) {
 734                 if (!adopt)
 735                         return status;
 736                 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
 737
 738                 /* Do not attempt to adopt firmware if there
 739                  * was a bad crc */
 740                 if (status == -EIO)
 741                         return status;
 742
 743                 status = myri10ge_adopt_running_firmware(mgp);
 744                 if (status != 0) {
 745                         dev_err(&mgp->pdev->dev,
 746                                 "failed to adopt running firmware\n");
 747                         return status;
 748                 }
 749                 dev_info(&mgp->pdev->dev,
 750                          "Successfully adopted running firmware\n");
 751                 if (mgp->tx_boundary == 4096) {
 752                         dev_warn(&mgp->pdev->dev,
 753                                  "Using firmware currently running on NIC"
 754                                  ".  For optimal\n");
 755                         dev_warn(&mgp->pdev->dev,
 756                                  "performance consider loading optimized "
 757                                  "firmware\n");
 758                         dev_warn(&mgp->pdev->dev, "via hotplug\n");
 759                 }
 760
 761                 set_fw_name(mgp, "adopted", false);
 762                 mgp->tx_boundary = 2048;
 763                 myri10ge_dummy_rdma(mgp, 1);
 764                 status = myri10ge_get_firmware_capabilities(mgp);
 765                 return status;
 766         }
 767
 768         /* clear confirmation addr */
 769         mgp->cmd->data = 0;
 770         mb();
 771
 772         /* send a reload command to the bootstrap MCP, and wait for the
 773          *  response in the confirmation address.  The firmware should
 774          * write a -1 there to indicate it is alive and well
 775          */
 776         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 777         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 778
 779         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 780         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 781         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 782
 783         /* FIX: All newest firmware should un-protect the bottom of
 784          * the sram before handoff. However, the very first interfaces
 785          * do not. Therefore the handoff copy must skip the first 8 bytes
 786          */
 787         buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
 788         buf[4] = htonl(size - 8);       /* length of code */
 789         buf[5] = htonl(8);      /* where to copy to */
 790         buf[6] = htonl(0);      /* where to jump to */
 791
 792         submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
 793
 794         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 795         mb();
 796         msleep(1);
 797         mb();
 798         i = 0;
 799         while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
 800                 msleep(1 << i);
 801                 i++;
 802         }
 803         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
 804                 dev_err(&mgp->pdev->dev, "handoff failed\n");
 805                 return -ENXIO;
 806         }
 807         myri10ge_dummy_rdma(mgp, 1);
 808         status = myri10ge_get_firmware_capabilities(mgp);
 809
 810         return status;
 811 }
 812
 813 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
 814 {
 815         struct myri10ge_cmd cmd;
 816         int status;
 817
 818         cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
 819                      | (addr[2] << 8) | addr[3]);
 820
 821         cmd.data1 = ((addr[4] << 8) | (addr[5]));
 822
 823         status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
 824         return status;
 825 }
 826
 827 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
 828 {
 829         struct myri10ge_cmd cmd;
 830         int status, ctl;
 831
 832         ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
 833         status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
 834
 835         if (status) {
 836                 netdev_err(mgp->dev, "Failed to set flow control mode\n");
 837                 return status;
 838         }
 839         mgp->pause = pause;
 840         return 0;
 841 }
 842
 843 static void
 844 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
 845 {
 846         struct myri10ge_cmd cmd;
 847         int status, ctl;
 848
 849         ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
 850         status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
 851         if (status)
 852                 netdev_err(mgp->dev, "Failed to set promisc mode\n");
 853 }
 854
 855 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
 856 {
 857         struct myri10ge_cmd cmd;
 858         int status;
 859         u32 len;
 860         struct page *dmatest_page;
 861         dma_addr_t dmatest_bus;
 862         char *test = " ";
 863
 864         dmatest_page = alloc_page(GFP_KERNEL);
 865         if (!dmatest_page)
 866                 return -ENOMEM;
 867         dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
 868                                    DMA_BIDIRECTIONAL);
 869
 870         /* Run a small DMA test.
 871          * The magic multipliers to the length tell the firmware
 872          * to do DMA read, write, or read+write tests.  The
 873          * results are returned in cmd.data0.  The upper 16
 874          * bits or the return is the number of transfers completed.
 875          * The lower 16 bits is the time in 0.5us ticks that the
 876          * transfers took to complete.
 877          */
 878
 879         len = mgp->tx_boundary;
 880
 881         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 882         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 883         cmd.data2 = len * 0x10000;
 884         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 885         if (status != 0) {
 886                 test = "read";
 887                 goto abort;
 888         }
 889         mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 890         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 891         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 892         cmd.data2 = len * 0x1;
 893         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 894         if (status != 0) {
 895                 test = "write";
 896                 goto abort;
 897         }
 898         mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 899
 900         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 901         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 902         cmd.data2 = len * 0x10001;
 903         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 904         if (status != 0) {
 905                 test = "read/write";
 906                 goto abort;
 907         }
 908         mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
 909             (cmd.data0 & 0xffff);
 910
 911 abort:
 912         pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 913         put_page(dmatest_page);
 914
 915         if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
 916                 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
 917                          test, status);
 918
 919         return status;
 920 }
 921
 922 static int myri10ge_reset(struct myri10ge_priv *mgp)
 923 {
 924         struct myri10ge_cmd cmd;
 925         struct myri10ge_slice_state *ss;
 926         int i, status;
 927         size_t bytes;
 928 #ifdef CONFIG_MYRI10GE_DCA
 929         unsigned long dca_tag_off;
 930 #endif
 931
 932         /* try to send a reset command to the card to see if it
 933          * is alive */
 934         memset(&cmd, 0, sizeof(cmd));
 935         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
 936         if (status != 0) {
 937                 dev_err(&mgp->pdev->dev, "failed reset\n");
 938                 return -ENXIO;
 939         }
 940
 941         (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
 942         /*
 943          * Use non-ndis mcp_slot (eg, 4 bytes total,
 944          * no toeplitz hash value returned.  Older firmware will
 945          * not understand this command, but will use the correct
 946          * sized mcp_slot, so we ignore error returns
 947          */
 948         cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
 949         (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
 950
 951         /* Now exchange information about interrupts  */
 952
 953         bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
 954         cmd.data0 = (u32) bytes;
 955         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
 956
 957         /*
 958          * Even though we already know how many slices are supported
 959          * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
 960          * has magic side effects, and must be called after a reset.
 961          * It must be called prior to calling any RSS related cmds,
 962          * including assigning an interrupt queue for anything but
 963          * slice 0.  It must also be called *after*
 964          * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
 965          * the firmware to compute offsets.
 966          */
 967
 968         if (mgp->num_slices > 1) {
 969
 970                 /* ask the maximum number of slices it supports */
 971                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
 972                                            &cmd, 0);
 973                 if (status != 0) {
 974                         dev_err(&mgp->pdev->dev,
 975                                 "failed to get number of slices\n");
 976                 }
 977
 978                 /*
 979                  * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
 980                  * to setting up the interrupt queue DMA
 981                  */
 982
 983                 cmd.data0 = mgp->num_slices;
 984                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 985                 if (mgp->dev->real_num_tx_queues > 1)
 986                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
 987                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
 988                                            &cmd, 0);
 989
 990                 /* Firmware older than 1.4.32 only supports multiple
 991                  * RX queues, so if we get an error, first retry using a
 992                  * single TX queue before giving up */
 993                 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
 994                         netif_set_real_num_tx_queues(mgp->dev, 1);
 995                         cmd.data0 = mgp->num_slices;
 996                         cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
 997                         status = myri10ge_send_cmd(mgp,
 998                                                    MXGEFW_CMD_ENABLE_RSS_QUEUES,
 999                                                    &cmd, 0);
1000                 }
1001
1002                 if (status != 0) {
1003                         dev_err(&mgp->pdev->dev,
1004                                 "failed to set number of slices\n");
1005
1006                         return status;
1007                 }
1008         }
1009         for (i = 0; i < mgp->num_slices; i++) {
1010                 ss = &mgp->ss[i];
1011                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
1012                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
1013                 cmd.data2 = i;
1014                 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1015                                             &cmd, 0);
1016         };
1017
1018         status |=
1019             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1020         for (i = 0; i < mgp->num_slices; i++) {
1021                 ss = &mgp->ss[i];
1022                 ss->irq_claim =
1023                     (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1024         }
1025         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1026                                     &cmd, 0);
1027         mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1028
1029         status |= myri10ge_send_cmd
1030             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1031         mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1032         if (status != 0) {
1033                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1034                 return status;
1035         }
1036         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1037
1038 #ifdef CONFIG_MYRI10GE_DCA
1039         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1040         dca_tag_off = cmd.data0;
1041         for (i = 0; i < mgp->num_slices; i++) {
1042                 ss = &mgp->ss[i];
1043                 if (status == 0) {
1044                         ss->dca_tag = (__iomem __be32 *)
1045                             (mgp->sram + dca_tag_off + 4 * i);
1046                 } else {
1047                         ss->dca_tag = NULL;
1048                 }
1049         }
1050 #endif                          /* CONFIG_MYRI10GE_DCA */
1051
1052         /* reset mcp/driver shared state back to 0 */
1053
1054         mgp->link_changes = 0;
1055         for (i = 0; i < mgp->num_slices; i++) {
1056                 ss = &mgp->ss[i];
1057
1058                 memset(ss->rx_done.entry, 0, bytes);
1059                 ss->tx.req = 0;
1060                 ss->tx.done = 0;
1061                 ss->tx.pkt_start = 0;
1062                 ss->tx.pkt_done = 0;
1063                 ss->rx_big.cnt = 0;
1064                 ss->rx_small.cnt = 0;
1065                 ss->rx_done.idx = 0;
1066                 ss->rx_done.cnt = 0;
1067                 ss->tx.wake_queue = 0;
1068                 ss->tx.stop_queue = 0;
1069         }
1070
1071         status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1072         myri10ge_change_pause(mgp, mgp->pause);
1073         myri10ge_set_multicast_list(mgp->dev);
1074         return status;
1075 }
1076
1077 #ifdef CONFIG_MYRI10GE_DCA
1078 static int myri10ge_toggle_relaxed(struct pci_dev *pdev, int on)
1079 {
1080         int ret, cap, err;
1081         u16 ctl;
1082
1083         cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1084         if (!cap)
1085                 return 0;
1086
1087         err = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
1088         ret = (ctl & PCI_EXP_DEVCTL_RELAX_EN) >> 4;
1089         if (ret != on) {
1090                 ctl &= ~PCI_EXP_DEVCTL_RELAX_EN;
1091                 ctl |= (on << 4);
1092                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
1093         }
1094         return ret;
1095 }
1096
1097 static void
1098 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1099 {
1100         ss->cached_dca_tag = tag;
1101         put_be32(htonl(tag), ss->dca_tag);
1102 }
1103
1104 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1105 {
1106         int cpu = get_cpu();
1107         int tag;
1108
1109         if (cpu != ss->cpu) {
1110                 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
1111                 if (ss->cached_dca_tag != tag)
1112                         myri10ge_write_dca(ss, cpu, tag);
1113                 ss->cpu = cpu;
1114         }
1115         put_cpu();
1116 }
1117
1118 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1119 {
1120         int err, i;
1121         struct pci_dev *pdev = mgp->pdev;
1122
1123         if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1124                 return;
1125         if (!myri10ge_dca) {
1126                 dev_err(&pdev->dev, "dca disabled by administrator\n");
1127                 return;
1128         }
1129         err = dca_add_requester(&pdev->dev);
1130         if (err) {
1131                 if (err != -ENODEV)
1132                         dev_err(&pdev->dev,
1133                                 "dca_add_requester() failed, err=%d\n", err);
1134                 return;
1135         }
1136         mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
1137         mgp->dca_enabled = 1;
1138         for (i = 0; i < mgp->num_slices; i++) {
1139                 mgp->ss[i].cpu = -1;
1140                 mgp->ss[i].cached_dca_tag = -1;
1141                 myri10ge_update_dca(&mgp->ss[i]);
1142          }
1143 }
1144
1145 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1146 {
1147         struct pci_dev *pdev = mgp->pdev;
1148         int err;
1149
1150         if (!mgp->dca_enabled)
1151                 return;
1152         mgp->dca_enabled = 0;
1153         if (mgp->relaxed_order)
1154                 myri10ge_toggle_relaxed(pdev, 1);
1155         err = dca_remove_requester(&pdev->dev);
1156 }
1157
1158 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1159 {
1160         struct myri10ge_priv *mgp;
1161         unsigned long event;
1162
1163         mgp = dev_get_drvdata(dev);
1164         event = *(unsigned long *)data;
1165
1166         if (event == DCA_PROVIDER_ADD)
1167                 myri10ge_setup_dca(mgp);
1168         else if (event == DCA_PROVIDER_REMOVE)
1169                 myri10ge_teardown_dca(mgp);
1170         return 0;
1171 }
1172 #endif                          /* CONFIG_MYRI10GE_DCA */
1173
1174 static inline void
1175 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1176                     struct mcp_kreq_ether_recv *src)
1177 {
1178         __be32 low;
1179
1180         low = src->addr_low;
1181         src->addr_low = htonl(DMA_BIT_MASK(32));
1182         myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1183         mb();
1184         myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1185         mb();
1186         src->addr_low = low;
1187         put_be32(low, &dst->addr_low);
1188         mb();
1189 }
1190
1191 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1192 {
1193         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1194
1195         if ((skb->protocol == htons(ETH_P_8021Q)) &&
1196             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1197              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1198                 skb->csum = hw_csum;
1199                 skb->ip_summed = CHECKSUM_COMPLETE;
1200         }
1201 }
1202
1203 static inline void
1204 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1205                       struct skb_frag_struct *rx_frags, int len, int hlen)
1206 {
1207         struct skb_frag_struct *skb_frags;
1208
1209         skb->len = skb->data_len = len;
1210         skb->truesize = len + sizeof(struct sk_buff);
1211         /* attach the page(s) */
1212
1213         skb_frags = skb_shinfo(skb)->frags;
1214         while (len > 0) {
1215                 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1216                 len -= rx_frags->size;
1217                 skb_frags++;
1218                 rx_frags++;
1219                 skb_shinfo(skb)->nr_frags++;
1220         }
1221
1222         /* pskb_may_pull is not available in irq context, but
1223          * skb_pull() (for ether_pad and eth_type_trans()) requires
1224          * the beginning of the packet in skb_headlen(), move it
1225          * manually */
1226         skb_copy_to_linear_data(skb, va, hlen);
1227         skb_shinfo(skb)->frags[0].page_offset += hlen;
1228         skb_shinfo(skb)->frags[0].size -= hlen;
1229         skb->data_len -= hlen;
1230         skb->tail += hlen;
1231         skb_pull(skb, MXGEFW_PAD);
1232 }
1233
1234 static void
1235 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1236                         int bytes, int watchdog)
1237 {
1238         struct page *page;
1239         int idx;
1240 #if MYRI10GE_ALLOC_SIZE > 4096
1241         int end_offset;
1242 #endif
1243
1244         if (unlikely(rx->watchdog_needed && !watchdog))
1245                 return;
1246
1247         /* try to refill entire ring */
1248         while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1249                 idx = rx->fill_cnt & rx->mask;
1250                 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1251                         /* we can use part of previous page */
1252                         get_page(rx->page);
1253                 } else {
1254                         /* we need a new page */
1255                         page =
1256                             alloc_pages(GFP_ATOMIC | __GFP_COMP,
1257                                         MYRI10GE_ALLOC_ORDER);
1258                         if (unlikely(page == NULL)) {
1259                                 if (rx->fill_cnt - rx->cnt < 16)
1260                                         rx->watchdog_needed = 1;
1261                                 return;
1262                         }
1263                         rx->page = page;
1264                         rx->page_offset = 0;
1265                         rx->bus = pci_map_page(mgp->pdev, page, 0,
1266                                                MYRI10GE_ALLOC_SIZE,
1267                                                PCI_DMA_FROMDEVICE);
1268                 }
1269                 rx->info[idx].page = rx->page;
1270                 rx->info[idx].page_offset = rx->page_offset;
1271                 /* note that this is the address of the start of the
1272                  * page */
1273                 dma_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1274                 rx->shadow[idx].addr_low =
1275                     htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1276                 rx->shadow[idx].addr_high =
1277                     htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1278
1279                 /* start next packet on a cacheline boundary */
1280                 rx->page_offset += SKB_DATA_ALIGN(bytes);
1281
1282 #if MYRI10GE_ALLOC_SIZE > 4096
1283                 /* don't cross a 4KB boundary */
1284                 end_offset = rx->page_offset + bytes - 1;
1285                 if ((unsigned)(rx->page_offset ^ end_offset) > 4095)
1286                         rx->page_offset = end_offset & ~4095;
1287 #endif
1288                 rx->fill_cnt++;
1289
1290                 /* copy 8 descriptors to the firmware at a time */
1291                 if ((idx & 7) == 7) {
1292                         myri10ge_submit_8rx(&rx->lanai[idx - 7],
1293                                             &rx->shadow[idx - 7]);
1294                 }
1295         }
1296 }
1297
1298 static inline void
1299 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1300                        struct myri10ge_rx_buffer_state *info, int bytes)
1301 {
1302         /* unmap the recvd page if we're the only or last user of it */
1303         if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1304             (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1305                 pci_unmap_page(pdev, (dma_unmap_addr(info, bus)
1306                                       & ~(MYRI10GE_ALLOC_SIZE - 1)),
1307                                MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1308         }
1309 }
1310
1311 #define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
1312                                  * page into an skb */
1313
1314 static inline int
1315 myri10ge_rx_done(struct myri10ge_slice_state *ss, int len, __wsum csum,
1316                  int lro_enabled)
1317 {
1318         struct myri10ge_priv *mgp = ss->mgp;
1319         struct sk_buff *skb;
1320         struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1321         struct myri10ge_rx_buf *rx;
1322         int i, idx, hlen, remainder, bytes;
1323         struct pci_dev *pdev = mgp->pdev;
1324         struct net_device *dev = mgp->dev;
1325         u8 *va;
1326
1327         if (len <= mgp->small_bytes) {
1328                 rx = &ss->rx_small;
1329                 bytes = mgp->small_bytes;
1330         } else {
1331                 rx = &ss->rx_big;
1332                 bytes = mgp->big_bytes;
1333         }
1334
1335         len += MXGEFW_PAD;
1336         idx = rx->cnt & rx->mask;
1337         va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1338         prefetch(va);
1339         /* Fill skb_frag_struct(s) with data from our receive */
1340         for (i = 0, remainder = len; remainder > 0; i++) {
1341                 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1342                 rx_frags[i].page = rx->info[idx].page;
1343                 rx_frags[i].page_offset = rx->info[idx].page_offset;
1344                 if (remainder < MYRI10GE_ALLOC_SIZE)
1345                         rx_frags[i].size = remainder;
1346                 else
1347                         rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1348                 rx->cnt++;
1349                 idx = rx->cnt & rx->mask;
1350                 remainder -= MYRI10GE_ALLOC_SIZE;
1351         }
1352
1353         if (lro_enabled) {
1354                 rx_frags[0].page_offset += MXGEFW_PAD;
1355                 rx_frags[0].size -= MXGEFW_PAD;
1356                 len -= MXGEFW_PAD;
1357                 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1358                                   /* opaque, will come back in get_frag_header */
1359                                   len, len,
1360                                   (void *)(__force unsigned long)csum, csum);
1361
1362                 return 1;
1363         }
1364
1365         hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1366
1367         /* allocate an skb to attach the page(s) to. This is done
1368          * after trying LRO, so as to avoid skb allocation overheads */
1369
1370         skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1371         if (unlikely(skb == NULL)) {
1372                 ss->stats.rx_dropped++;
1373                 do {
1374                         i--;
1375                         put_page(rx_frags[i].page);
1376                 } while (i != 0);
1377                 return 0;
1378         }
1379
1380         /* Attach the pages to the skb, and trim off any padding */
1381         myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1382         if (skb_shinfo(skb)->frags[0].size <= 0) {
1383                 put_page(skb_shinfo(skb)->frags[0].page);
1384                 skb_shinfo(skb)->nr_frags = 0;
1385         }
1386         skb->protocol = eth_type_trans(skb, dev);
1387         skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1388
1389         if (mgp->csum_flag) {
1390                 if ((skb->protocol == htons(ETH_P_IP)) ||
1391                     (skb->protocol == htons(ETH_P_IPV6))) {
1392                         skb->csum = csum;
1393                         skb->ip_summed = CHECKSUM_COMPLETE;
1394                 } else
1395                         myri10ge_vlan_ip_csum(skb, csum);
1396         }
1397         netif_receive_skb(skb);
1398         return 1;
1399 }
1400
1401 static inline void
1402 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1403 {
1404         struct pci_dev *pdev = ss->mgp->pdev;
1405         struct myri10ge_tx_buf *tx = &ss->tx;
1406         struct netdev_queue *dev_queue;
1407         struct sk_buff *skb;
1408         int idx, len;
1409
1410         while (tx->pkt_done != mcp_index) {
1411                 idx = tx->done & tx->mask;
1412                 skb = tx->info[idx].skb;
1413
1414                 /* Mark as free */
1415                 tx->info[idx].skb = NULL;
1416                 if (tx->info[idx].last) {
1417                         tx->pkt_done++;
1418                         tx->info[idx].last = 0;
1419                 }
1420                 tx->done++;
1421                 len = dma_unmap_len(&tx->info[idx], len);
1422                 dma_unmap_len_set(&tx->info[idx], len, 0);
1423                 if (skb) {
1424                         ss->stats.tx_bytes += skb->len;
1425                         ss->stats.tx_packets++;
1426                         dev_kfree_skb_irq(skb);
1427                         if (len)
1428                                 pci_unmap_single(pdev,
1429                                                  dma_unmap_addr(&tx->info[idx],
1430                                                                 bus), len,
1431                                                  PCI_DMA_TODEVICE);
1432                 } else {
1433                         if (len)
1434                                 pci_unmap_page(pdev,
1435                                                dma_unmap_addr(&tx->info[idx],
1436                                                               bus), len,
1437                                                PCI_DMA_TODEVICE);
1438                 }
1439         }
1440
1441         dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1442         /*
1443          * Make a minimal effort to prevent the NIC from polling an
1444          * idle tx queue.  If we can't get the lock we leave the queue
1445          * active. In this case, either a thread was about to start
1446          * using the queue anyway, or we lost a race and the NIC will
1447          * waste some of its resources polling an inactive queue for a
1448          * while.
1449          */
1450
1451         if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1452             __netif_tx_trylock(dev_queue)) {
1453                 if (tx->req == tx->done) {
1454                         tx->queue_active = 0;
1455                         put_be32(htonl(1), tx->send_stop);
1456                         mb();
1457                         mmiowb();
1458                 }
1459                 __netif_tx_unlock(dev_queue);
1460         }
1461
1462         /* start the queue if we've stopped it */
1463         if (netif_tx_queue_stopped(dev_queue) &&
1464             tx->req - tx->done < (tx->mask >> 1)) {
1465                 tx->wake_queue++;
1466                 netif_tx_wake_queue(dev_queue);
1467         }
1468 }
1469
1470 static inline int
1471 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1472 {
1473         struct myri10ge_rx_done *rx_done = &ss->rx_done;
1474         struct myri10ge_priv *mgp = ss->mgp;
1475
1476         unsigned long rx_bytes = 0;
1477         unsigned long rx_packets = 0;
1478         unsigned long rx_ok;
1479
1480         int idx = rx_done->idx;
1481         int cnt = rx_done->cnt;
1482         int work_done = 0;
1483         u16 length;
1484         __wsum checksum;
1485
1486         /*
1487          * Prevent compiler from generating more than one ->features memory
1488          * access to avoid theoretical race condition with functions that
1489          * change NETIF_F_LRO flag at runtime.
1490          */
1491         bool lro_enabled = ACCESS_ONCE(mgp->dev->features) & NETIF_F_LRO;
1492
1493         while (rx_done->entry[idx].length != 0 && work_done < budget) {
1494                 length = ntohs(rx_done->entry[idx].length);
1495                 rx_done->entry[idx].length = 0;
1496                 checksum = csum_unfold(rx_done->entry[idx].checksum);
1497                 rx_ok = myri10ge_rx_done(ss, length, checksum, lro_enabled);
1498                 rx_packets += rx_ok;
1499                 rx_bytes += rx_ok * (unsigned long)length;
1500                 cnt++;
1501                 idx = cnt & (mgp->max_intr_slots - 1);
1502                 work_done++;
1503         }
1504         rx_done->idx = idx;
1505         rx_done->cnt = cnt;
1506         ss->stats.rx_packets += rx_packets;
1507         ss->stats.rx_bytes += rx_bytes;
1508
1509         if (lro_enabled)
1510                 lro_flush_all(&rx_done->lro_mgr);
1511
1512         /* restock receive rings if needed */
1513         if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1514                 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1515                                         mgp->small_bytes + MXGEFW_PAD, 0);
1516         if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1517                 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1518
1519         return work_done;
1520 }
1521
1522 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1523 {
1524         struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1525
1526         if (unlikely(stats->stats_updated)) {
1527                 unsigned link_up = ntohl(stats->link_up);
1528                 if (mgp->link_state != link_up) {
1529                         mgp->link_state = link_up;
1530
1531                         if (mgp->link_state == MXGEFW_LINK_UP) {
1532                                 if (netif_msg_link(mgp))
1533                                         netdev_info(mgp->dev, "link up\n");
1534                                 netif_carrier_on(mgp->dev);
1535                                 mgp->link_changes++;
1536                         } else {
1537                                 if (netif_msg_link(mgp))
1538                                         netdev_info(mgp->dev, "link %s\n",
1539                                             link_up == MXGEFW_LINK_MYRINET ?
1540                                             "mismatch (Myrinet detected)" :
1541                                             "down");
1542                                 netif_carrier_off(mgp->dev);
1543                                 mgp->link_changes++;
1544                         }
1545                 }
1546                 if (mgp->rdma_tags_available !=
1547                     ntohl(stats->rdma_tags_available)) {
1548                         mgp->rdma_tags_available =
1549                             ntohl(stats->rdma_tags_available);
1550                         netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1551                                     mgp->rdma_tags_available);
1552                 }
1553                 mgp->down_cnt += stats->link_down;
1554                 if (stats->link_down)
1555                         wake_up(&mgp->down_wq);
1556         }
1557 }
1558
1559 static int myri10ge_poll(struct napi_struct *napi, int budget)
1560 {
1561         struct myri10ge_slice_state *ss =
1562             container_of(napi, struct myri10ge_slice_state, napi);
1563         int work_done;
1564
1565 #ifdef CONFIG_MYRI10GE_DCA
1566         if (ss->mgp->dca_enabled)
1567                 myri10ge_update_dca(ss);
1568 #endif
1569
1570         /* process as many rx events as NAPI will allow */
1571         work_done = myri10ge_clean_rx_done(ss, budget);
1572
1573         if (work_done < budget) {
1574                 napi_complete(napi);
1575                 put_be32(htonl(3), ss->irq_claim);
1576         }
1577         return work_done;
1578 }
1579
1580 static irqreturn_t myri10ge_intr(int irq, void *arg)
1581 {
1582         struct myri10ge_slice_state *ss = arg;
1583         struct myri10ge_priv *mgp = ss->mgp;
1584         struct mcp_irq_data *stats = ss->fw_stats;
1585         struct myri10ge_tx_buf *tx = &ss->tx;
1586         u32 send_done_count;
1587         int i;
1588
1589         /* an interrupt on a non-zero receive-only slice is implicitly
1590          * valid  since MSI-X irqs are not shared */
1591         if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1592                 napi_schedule(&ss->napi);
1593                 return IRQ_HANDLED;
1594         }
1595
1596         /* make sure it is our IRQ, and that the DMA has finished */
1597         if (unlikely(!stats->valid))
1598                 return IRQ_NONE;
1599
1600         /* low bit indicates receives are present, so schedule
1601          * napi poll handler */
1602         if (stats->valid & 1)
1603                 napi_schedule(&ss->napi);
1604
1605         if (!mgp->msi_enabled && !mgp->msix_enabled) {
1606                 put_be32(0, mgp->irq_deassert);
1607                 if (!myri10ge_deassert_wait)
1608                         stats->valid = 0;
1609                 mb();
1610         } else
1611                 stats->valid = 0;
1612
1613         /* Wait for IRQ line to go low, if using INTx */
1614         i = 0;
1615         while (1) {
1616                 i++;
1617                 /* check for transmit completes and receives */
1618                 send_done_count = ntohl(stats->send_done_count);
1619                 if (send_done_count != tx->pkt_done)
1620                         myri10ge_tx_done(ss, (int)send_done_count);
1621                 if (unlikely(i > myri10ge_max_irq_loops)) {
1622                         netdev_err(mgp->dev, "irq stuck?\n");
1623                         stats->valid = 0;
1624                         schedule_work(&mgp->watchdog_work);
1625                 }
1626                 if (likely(stats->valid == 0))
1627                         break;
1628                 cpu_relax();
1629                 barrier();
1630         }
1631
1632         /* Only slice 0 updates stats */
1633         if (ss == mgp->ss)
1634                 myri10ge_check_statblock(mgp);
1635
1636         put_be32(htonl(3), ss->irq_claim + 1);
1637         return IRQ_HANDLED;
1638 }
1639
1640 static int
1641 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1642 {
1643         struct myri10ge_priv *mgp = netdev_priv(netdev);
1644         char *ptr;
1645         int i;
1646
1647         cmd->autoneg = AUTONEG_DISABLE;
1648         cmd->speed = SPEED_10000;
1649         cmd->duplex = DUPLEX_FULL;
1650
1651         /*
1652          * parse the product code to deterimine the interface type
1653          * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1654          * after the 3rd dash in the driver's cached copy of the
1655          * EEPROM's product code string.
1656          */
1657         ptr = mgp->product_code_string;
1658         if (ptr == NULL) {
1659                 netdev_err(netdev, "Missing product code\n");
1660                 return 0;
1661         }
1662         for (i = 0; i < 3; i++, ptr++) {
1663                 ptr = strchr(ptr, '-');
1664                 if (ptr == NULL) {
1665                         netdev_err(netdev, "Invalid product code %s\n",
1666                                    mgp->product_code_string);
1667                         return 0;
1668                 }
1669         }
1670         if (*ptr == '2')
1671                 ptr++;
1672         if (*ptr == 'R' || *ptr == 'Q' || *ptr == 'S') {
1673                 /* We've found either an XFP, quad ribbon fiber, or SFP+ */
1674                 cmd->port = PORT_FIBRE;
1675                 cmd->supported |= SUPPORTED_FIBRE;
1676                 cmd->advertising |= ADVERTISED_FIBRE;
1677         } else {
1678                 cmd->port = PORT_OTHER;
1679         }
1680         if (*ptr == 'R' || *ptr == 'S')
1681                 cmd->transceiver = XCVR_EXTERNAL;
1682         else
1683                 cmd->transceiver = XCVR_INTERNAL;
1684
1685         return 0;
1686 }
1687
1688 static void
1689 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1690 {
1691         struct myri10ge_priv *mgp = netdev_priv(netdev);
1692
1693         strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1694         strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1695         strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1696         strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1697 }
1698
1699 static int
1700 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1701 {
1702         struct myri10ge_priv *mgp = netdev_priv(netdev);
1703
1704         coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1705         return 0;
1706 }
1707
1708 static int
1709 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1710 {
1711         struct myri10ge_priv *mgp = netdev_priv(netdev);
1712
1713         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1714         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1715         return 0;
1716 }
1717
1718 static void
1719 myri10ge_get_pauseparam(struct net_device *netdev,
1720                         struct ethtool_pauseparam *pause)
1721 {
1722         struct myri10ge_priv *mgp = netdev_priv(netdev);
1723
1724         pause->autoneg = 0;
1725         pause->rx_pause = mgp->pause;
1726         pause->tx_pause = mgp->pause;
1727 }
1728
1729 static int
1730 myri10ge_set_pauseparam(struct net_device *netdev,
1731                         struct ethtool_pauseparam *pause)
1732 {
1733         struct myri10ge_priv *mgp = netdev_priv(netdev);
1734
1735         if (pause->tx_pause != mgp->pause)
1736                 return myri10ge_change_pause(mgp, pause->tx_pause);
1737         if (pause->rx_pause != mgp->pause)
1738                 return myri10ge_change_pause(mgp, pause->rx_pause);
1739         if (pause->autoneg != 0)
1740                 return -EINVAL;
1741         return 0;
1742 }
1743
1744 static void
1745 myri10ge_get_ringparam(struct net_device *netdev,
1746                        struct ethtool_ringparam *ring)
1747 {
1748         struct myri10ge_priv *mgp = netdev_priv(netdev);
1749
1750         ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1751         ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1752         ring->rx_jumbo_max_pending = 0;
1753         ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
1754         ring->rx_mini_pending = ring->rx_mini_max_pending;
1755         ring->rx_pending = ring->rx_max_pending;
1756         ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1757         ring->tx_pending = ring->tx_max_pending;
1758 }
1759
1760 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1761 {
1762         struct myri10ge_priv *mgp = netdev_priv(netdev);
1763
1764         if (mgp->csum_flag)
1765                 return 1;
1766         else
1767                 return 0;
1768 }
1769
1770 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1771 {
1772         struct myri10ge_priv *mgp = netdev_priv(netdev);
1773         int err = 0;
1774
1775         if (csum_enabled)
1776                 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1777         else {
1778                 netdev->features &= ~NETIF_F_LRO;
1779                 mgp->csum_flag = 0;
1780
1781         }
1782         return err;
1783 }
1784
1785 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1786 {
1787         struct myri10ge_priv *mgp = netdev_priv(netdev);
1788         u32 flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1789
1790         if (tso_enabled)
1791                 netdev->features |= flags;
1792         else
1793                 netdev->features &= ~flags;
1794         return 0;
1795 }
1796
1797 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1798         "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1799         "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1800         "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1801         "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1802         "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1803         "tx_heartbeat_errors", "tx_window_errors",
1804         /* device-specific stats */
1805         "tx_boundary", "WC", "irq", "MSI", "MSIX",
1806         "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1807         "serial_number", "watchdog_resets",
1808 #ifdef CONFIG_MYRI10GE_DCA
1809         "dca_capable_firmware", "dca_device_present",
1810 #endif
1811         "link_changes", "link_up", "dropped_link_overflow",
1812         "dropped_link_error_or_filtered",
1813         "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1814         "dropped_unicast_filtered", "dropped_multicast_filtered",
1815         "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1816         "dropped_no_big_buffer"
1817 };
1818
1819 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1820         "----------- slice ---------",
1821         "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1822         "rx_small_cnt", "rx_big_cnt",
1823         "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1824             "LRO flushed",
1825         "LRO avg aggr", "LRO no_desc"
1826 };
1827
1828 #define MYRI10GE_NET_STATS_LEN      21
1829 #define MYRI10GE_MAIN_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_main_stats)
1830 #define MYRI10GE_SLICE_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1831
1832 static void
1833 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1834 {
1835         struct myri10ge_priv *mgp = netdev_priv(netdev);
1836         int i;
1837
1838         switch (stringset) {
1839         case ETH_SS_STATS:
1840                 memcpy(data, *myri10ge_gstrings_main_stats,
1841                        sizeof(myri10ge_gstrings_main_stats));
1842                 data += sizeof(myri10ge_gstrings_main_stats);
1843                 for (i = 0; i < mgp->num_slices; i++) {
1844                         memcpy(data, *myri10ge_gstrings_slice_stats,
1845                                sizeof(myri10ge_gstrings_slice_stats));
1846                         data += sizeof(myri10ge_gstrings_slice_stats);
1847                 }
1848                 break;
1849         }
1850 }
1851
1852 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1853 {
1854         struct myri10ge_priv *mgp = netdev_priv(netdev);
1855
1856         switch (sset) {
1857         case ETH_SS_STATS:
1858                 return MYRI10GE_MAIN_STATS_LEN +
1859                     mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1860         default:
1861                 return -EOPNOTSUPP;
1862         }
1863 }
1864
1865 static void
1866 myri10ge_get_ethtool_stats(struct net_device *netdev,
1867                            struct ethtool_stats *stats, u64 * data)
1868 {
1869         struct myri10ge_priv *mgp = netdev_priv(netdev);
1870         struct myri10ge_slice_state *ss;
1871         int slice;
1872         int i;
1873
1874         /* force stats update */
1875         (void)myri10ge_get_stats(netdev);
1876         for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1877                 data[i] = ((unsigned long *)&netdev->stats)[i];
1878
1879         data[i++] = (unsigned int)mgp->tx_boundary;
1880         data[i++] = (unsigned int)mgp->wc_enabled;
1881         data[i++] = (unsigned int)mgp->pdev->irq;
1882         data[i++] = (unsigned int)mgp->msi_enabled;
1883         data[i++] = (unsigned int)mgp->msix_enabled;
1884         data[i++] = (unsigned int)mgp->read_dma;
1885         data[i++] = (unsigned int)mgp->write_dma;
1886         data[i++] = (unsigned int)mgp->read_write_dma;
1887         data[i++] = (unsigned int)mgp->serial_number;
1888         data[i++] = (unsigned int)mgp->watchdog_resets;
1889 #ifdef CONFIG_MYRI10GE_DCA
1890         data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1891         data[i++] = (unsigned int)(mgp->dca_enabled);
1892 #endif
1893         data[i++] = (unsigned int)mgp->link_changes;
1894
1895         /* firmware stats are useful only in the first slice */
1896         ss = &mgp->ss[0];
1897         data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1898         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1899         data[i++] =
1900             (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1901         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1902         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1903         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1904         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1905         data[i++] =
1906             (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1907         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1908         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1909         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1910         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1911
1912         for (slice = 0; slice < mgp->num_slices; slice++) {
1913                 ss = &mgp->ss[slice];
1914                 data[i++] = slice;
1915                 data[i++] = (unsigned int)ss->tx.pkt_start;
1916                 data[i++] = (unsigned int)ss->tx.pkt_done;
1917                 data[i++] = (unsigned int)ss->tx.req;
1918                 data[i++] = (unsigned int)ss->tx.done;
1919                 data[i++] = (unsigned int)ss->rx_small.cnt;
1920                 data[i++] = (unsigned int)ss->rx_big.cnt;
1921                 data[i++] = (unsigned int)ss->tx.wake_queue;
1922                 data[i++] = (unsigned int)ss->tx.stop_queue;
1923                 data[i++] = (unsigned int)ss->tx.linearized;
1924                 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1925                 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1926                 if (ss->rx_done.lro_mgr.stats.flushed)
1927                         data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1928                             ss->rx_done.lro_mgr.stats.flushed;
1929                 else
1930                         data[i++] = 0;
1931                 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1932         }
1933 }
1934
1935 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1936 {
1937         struct myri10ge_priv *mgp = netdev_priv(netdev);
1938         mgp->msg_enable = value;
1939 }
1940
1941 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1942 {
1943         struct myri10ge_priv *mgp = netdev_priv(netdev);
1944         return mgp->msg_enable;
1945 }
1946
1947 static int myri10ge_set_flags(struct net_device *netdev, u32 value)
1948 {
1949         return ethtool_op_set_flags(netdev, value, ETH_FLAG_LRO);
1950 }
1951
1952 static const struct ethtool_ops myri10ge_ethtool_ops = {
1953         .get_settings = myri10ge_get_settings,
1954         .get_drvinfo = myri10ge_get_drvinfo,
1955         .get_coalesce = myri10ge_get_coalesce,
1956         .set_coalesce = myri10ge_set_coalesce,
1957         .get_pauseparam = myri10ge_get_pauseparam,
1958         .set_pauseparam = myri10ge_set_pauseparam,
1959         .get_ringparam = myri10ge_get_ringparam,
1960         .get_rx_csum = myri10ge_get_rx_csum,
1961         .set_rx_csum = myri10ge_set_rx_csum,
1962         .set_tx_csum = ethtool_op_set_tx_hw_csum,
1963         .set_sg = ethtool_op_set_sg,
1964         .set_tso = myri10ge_set_tso,
1965         .get_link = ethtool_op_get_link,
1966         .get_strings = myri10ge_get_strings,
1967         .get_sset_count = myri10ge_get_sset_count,
1968         .get_ethtool_stats = myri10ge_get_ethtool_stats,
1969         .set_msglevel = myri10ge_set_msglevel,
1970         .get_msglevel = myri10ge_get_msglevel,
1971         .get_flags = ethtool_op_get_flags,
1972         .set_flags = myri10ge_set_flags
1973 };
1974
1975 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1976 {
1977         struct myri10ge_priv *mgp = ss->mgp;
1978         struct myri10ge_cmd cmd;
1979         struct net_device *dev = mgp->dev;
1980         int tx_ring_size, rx_ring_size;
1981         int tx_ring_entries, rx_ring_entries;
1982         int i, slice, status;
1983         size_t bytes;
1984
1985         /* get ring sizes */
1986         slice = ss - mgp->ss;
1987         cmd.data0 = slice;
1988         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1989         tx_ring_size = cmd.data0;
1990         cmd.data0 = slice;
1991         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1992         if (status != 0)
1993                 return status;
1994         rx_ring_size = cmd.data0;
1995
1996         tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1997         rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1998         ss->tx.mask = tx_ring_entries - 1;
1999         ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
2000
2001         status = -ENOMEM;
2002
2003         /* allocate the host shadow rings */
2004
2005         bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
2006             * sizeof(*ss->tx.req_list);
2007         ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
2008         if (ss->tx.req_bytes == NULL)
2009                 goto abort_with_nothing;
2010
2011         /* ensure req_list entries are aligned to 8 bytes */
2012         ss->tx.req_list = (struct mcp_kreq_ether_send *)
2013             ALIGN((unsigned long)ss->tx.req_bytes, 8);
2014         ss->tx.queue_active = 0;
2015
2016         bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
2017         ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
2018         if (ss->rx_small.shadow == NULL)
2019                 goto abort_with_tx_req_bytes;
2020
2021         bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
2022         ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
2023         if (ss->rx_big.shadow == NULL)
2024                 goto abort_with_rx_small_shadow;
2025
2026         /* allocate the host info rings */
2027
2028         bytes = tx_ring_entries * sizeof(*ss->tx.info);
2029         ss->tx.info = kzalloc(bytes, GFP_KERNEL);
2030         if (ss->tx.info == NULL)
2031                 goto abort_with_rx_big_shadow;
2032
2033         bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
2034         ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
2035         if (ss->rx_small.info == NULL)
2036                 goto abort_with_tx_info;
2037
2038         bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
2039         ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
2040         if (ss->rx_big.info == NULL)
2041                 goto abort_with_rx_small_info;
2042
2043         /* Fill the receive rings */
2044         ss->rx_big.cnt = 0;
2045         ss->rx_small.cnt = 0;
2046         ss->rx_big.fill_cnt = 0;
2047         ss->rx_small.fill_cnt = 0;
2048         ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
2049         ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
2050         ss->rx_small.watchdog_needed = 0;
2051         ss->rx_big.watchdog_needed = 0;
2052         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2053                                 mgp->small_bytes + MXGEFW_PAD, 0);
2054
2055         if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
2056                 netdev_err(dev, "slice-%d: alloced only %d small bufs\n",
2057                            slice, ss->rx_small.fill_cnt);
2058                 goto abort_with_rx_small_ring;
2059         }
2060
2061         myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2062         if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
2063                 netdev_err(dev, "slice-%d: alloced only %d big bufs\n",
2064                            slice, ss->rx_big.fill_cnt);
2065                 goto abort_with_rx_big_ring;
2066         }
2067
2068         return 0;
2069
2070 abort_with_rx_big_ring:
2071         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2072                 int idx = i & ss->rx_big.mask;
2073                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2074                                        mgp->big_bytes);
2075                 put_page(ss->rx_big.info[idx].page);
2076         }
2077
2078 abort_with_rx_small_ring:
2079         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2080                 int idx = i & ss->rx_small.mask;
2081                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2082                                        mgp->small_bytes + MXGEFW_PAD);
2083                 put_page(ss->rx_small.info[idx].page);
2084         }
2085
2086         kfree(ss->rx_big.info);
2087
2088 abort_with_rx_small_info:
2089         kfree(ss->rx_small.info);
2090
2091 abort_with_tx_info:
2092         kfree(ss->tx.info);
2093
2094 abort_with_rx_big_shadow:
2095         kfree(ss->rx_big.shadow);
2096
2097 abort_with_rx_small_shadow:
2098         kfree(ss->rx_small.shadow);
2099
2100 abort_with_tx_req_bytes:
2101         kfree(ss->tx.req_bytes);
2102         ss->tx.req_bytes = NULL;
2103         ss->tx.req_list = NULL;
2104
2105 abort_with_nothing:
2106         return status;
2107 }
2108
2109 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
2110 {
2111         struct myri10ge_priv *mgp = ss->mgp;
2112         struct sk_buff *skb;
2113         struct myri10ge_tx_buf *tx;
2114         int i, len, idx;
2115
2116         /* If not allocated, skip it */
2117         if (ss->tx.req_list == NULL)
2118                 return;
2119
2120         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2121                 idx = i & ss->rx_big.mask;
2122                 if (i == ss->rx_big.fill_cnt - 1)
2123                         ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2124                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2125                                        mgp->big_bytes);
2126                 put_page(ss->rx_big.info[idx].page);
2127         }
2128
2129         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2130                 idx = i & ss->rx_small.mask;
2131                 if (i == ss->rx_small.fill_cnt - 1)
2132                         ss->rx_small.info[idx].page_offset =
2133                             MYRI10GE_ALLOC_SIZE;
2134                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2135                                        mgp->small_bytes + MXGEFW_PAD);
2136                 put_page(ss->rx_small.info[idx].page);
2137         }
2138         tx = &ss->tx;
2139         while (tx->done != tx->req) {
2140                 idx = tx->done & tx->mask;
2141                 skb = tx->info[idx].skb;
2142
2143                 /* Mark as free */
2144                 tx->info[idx].skb = NULL;
2145                 tx->done++;
2146                 len = dma_unmap_len(&tx->info[idx], len);
2147                 dma_unmap_len_set(&tx->info[idx], len, 0);
2148                 if (skb) {
2149                         ss->stats.tx_dropped++;
2150                         dev_kfree_skb_any(skb);
2151                         if (len)
2152                                 pci_unmap_single(mgp->pdev,
2153                                                  dma_unmap_addr(&tx->info[idx],
2154                                                                 bus), len,
2155                                                  PCI_DMA_TODEVICE);
2156                 } else {
2157                         if (len)
2158                                 pci_unmap_page(mgp->pdev,
2159                                                dma_unmap_addr(&tx->info[idx],
2160                                                               bus), len,
2161                                                PCI_DMA_TODEVICE);
2162                 }
2163         }
2164         kfree(ss->rx_big.info);
2165
2166         kfree(ss->rx_small.info);
2167
2168         kfree(ss->tx.info);
2169
2170         kfree(ss->rx_big.shadow);
2171
2172         kfree(ss->rx_small.shadow);
2173
2174         kfree(ss->tx.req_bytes);
2175         ss->tx.req_bytes = NULL;
2176         ss->tx.req_list = NULL;
2177 }
2178
2179 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2180 {
2181         struct pci_dev *pdev = mgp->pdev;
2182         struct myri10ge_slice_state *ss;
2183         struct net_device *netdev = mgp->dev;
2184         int i;
2185         int status;
2186
2187         mgp->msi_enabled = 0;
2188         mgp->msix_enabled = 0;
2189         status = 0;
2190         if (myri10ge_msi) {
2191                 if (mgp->num_slices > 1) {
2192                         status =
2193                             pci_enable_msix(pdev, mgp->msix_vectors,
2194                                             mgp->num_slices);
2195                         if (status == 0) {
2196                                 mgp->msix_enabled = 1;
2197                         } else {
2198                                 dev_err(&pdev->dev,
2199                                         "Error %d setting up MSI-X\n", status);
2200                                 return status;
2201                         }
2202                 }
2203                 if (mgp->msix_enabled == 0) {
2204                         status = pci_enable_msi(pdev);
2205                         if (status != 0) {
2206                                 dev_err(&pdev->dev,
2207                                         "Error %d setting up MSI; falling back to xPIC\n",
2208                                         status);
2209                         } else {
2210                                 mgp->msi_enabled = 1;
2211                         }
2212                 }
2213         }
2214         if (mgp->msix_enabled) {
2215                 for (i = 0; i < mgp->num_slices; i++) {
2216                         ss = &mgp->ss[i];
2217                         snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2218                                  "%s:slice-%d", netdev->name, i);
2219                         status = request_irq(mgp->msix_vectors[i].vector,
2220                                              myri10ge_intr, 0, ss->irq_desc,
2221                                              ss);
2222                         if (status != 0) {
2223                                 dev_err(&pdev->dev,
2224                                         "slice %d failed to allocate IRQ\n", i);
2225                                 i--;
2226                                 while (i >= 0) {
2227                                         free_irq(mgp->msix_vectors[i].vector,
2228                                                  &mgp->ss[i]);
2229                                         i--;
2230                                 }
2231                                 pci_disable_msix(pdev);
2232                                 return status;
2233                         }
2234                 }
2235         } else {
2236                 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2237                                      mgp->dev->name, &mgp->ss[0]);
2238                 if (status != 0) {
2239                         dev_err(&pdev->dev, "failed to allocate IRQ\n");
2240                         if (mgp->msi_enabled)
2241                                 pci_disable_msi(pdev);
2242                 }
2243         }
2244         return status;
2245 }
2246
2247 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2248 {
2249         struct pci_dev *pdev = mgp->pdev;
2250         int i;
2251
2252         if (mgp->msix_enabled) {
2253                 for (i = 0; i < mgp->num_slices; i++)
2254                         free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2255         } else {
2256                 free_irq(pdev->irq, &mgp->ss[0]);
2257         }
2258         if (mgp->msi_enabled)
2259                 pci_disable_msi(pdev);
2260         if (mgp->msix_enabled)
2261                 pci_disable_msix(pdev);
2262 }
2263
2264 static int
2265 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2266                          void **ip_hdr, void **tcpudp_hdr,
2267                          u64 * hdr_flags, void *priv)
2268 {
2269         struct ethhdr *eh;
2270         struct vlan_ethhdr *veh;
2271         struct iphdr *iph;
2272         u8 *va = page_address(frag->page) + frag->page_offset;
2273         unsigned long ll_hlen;
2274         /* passed opaque through lro_receive_frags() */
2275         __wsum csum = (__force __wsum) (unsigned long)priv;
2276
2277         /* find the mac header, aborting if not IPv4 */
2278
2279         eh = (struct ethhdr *)va;
2280         *mac_hdr = eh;
2281         ll_hlen = ETH_HLEN;
2282         if (eh->h_proto != htons(ETH_P_IP)) {
2283                 if (eh->h_proto == htons(ETH_P_8021Q)) {
2284                         veh = (struct vlan_ethhdr *)va;
2285                         if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2286                                 return -1;
2287
2288                         ll_hlen += VLAN_HLEN;
2289
2290                         /*
2291                          *  HW checksum starts ETH_HLEN bytes into
2292                          *  frame, so we must subtract off the VLAN
2293                          *  header's checksum before csum can be used
2294                          */
2295                         csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2296                                                            VLAN_HLEN, 0));
2297                 } else {
2298                         return -1;
2299                 }
2300         }
2301         *hdr_flags = LRO_IPV4;
2302
2303         iph = (struct iphdr *)(va + ll_hlen);
2304         *ip_hdr = iph;
2305         if (iph->protocol != IPPROTO_TCP)
2306                 return -1;
2307         if (iph->frag_off & htons(IP_MF | IP_OFFSET))
2308                 return -1;
2309         *hdr_flags |= LRO_TCP;
2310         *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2311
2312         /* verify the IP checksum */
2313         if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2314                 return -1;
2315
2316         /* verify the  checksum */
2317         if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2318                                        ntohs(iph->tot_len) - (iph->ihl << 2),
2319                                        IPPROTO_TCP, csum)))
2320                 return -1;
2321
2322         return 0;
2323 }
2324
2325 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2326 {
2327         struct myri10ge_cmd cmd;
2328         struct myri10ge_slice_state *ss;
2329         int status;
2330
2331         ss = &mgp->ss[slice];
2332         status = 0;
2333         if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2334                 cmd.data0 = slice;
2335                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2336                                            &cmd, 0);
2337                 ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2338                     (mgp->sram + cmd.data0);
2339         }
2340         cmd.data0 = slice;
2341         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2342                                     &cmd, 0);
2343         ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2344             (mgp->sram + cmd.data0);
2345
2346         cmd.data0 = slice;
2347         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2348         ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2349             (mgp->sram + cmd.data0);
2350
2351         ss->tx.send_go = (__iomem __be32 *)
2352             (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2353         ss->tx.send_stop = (__iomem __be32 *)
2354             (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2355         return status;
2356
2357 }
2358
2359 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2360 {
2361         struct myri10ge_cmd cmd;
2362         struct myri10ge_slice_state *ss;
2363         int status;
2364
2365         ss = &mgp->ss[slice];
2366         cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2367         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2368         cmd.data2 = sizeof(struct mcp_irq_data) | (slice << 16);
2369         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2370         if (status == -ENOSYS) {
2371                 dma_addr_t bus = ss->fw_stats_bus;
2372                 if (slice != 0)
2373                         return -EINVAL;
2374                 bus += offsetof(struct mcp_irq_data, send_done_count);
2375                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2376                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2377                 status = myri10ge_send_cmd(mgp,
2378                                            MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2379                                            &cmd, 0);
2380                 /* Firmware cannot support multicast without STATS_DMA_V2 */
2381                 mgp->fw_multicast_support = 0;
2382         } else {
2383                 mgp->fw_multicast_support = 1;
2384         }
2385         return 0;
2386 }
2387
2388 static int myri10ge_open(struct net_device *dev)
2389 {
2390         struct myri10ge_slice_state *ss;
2391         struct myri10ge_priv *mgp = netdev_priv(dev);
2392         struct myri10ge_cmd cmd;
2393         int i, status, big_pow2, slice;
2394         u8 *itable;
2395         struct net_lro_mgr *lro_mgr;
2396
2397         if (mgp->running != MYRI10GE_ETH_STOPPED)
2398                 return -EBUSY;
2399
2400         mgp->running = MYRI10GE_ETH_STARTING;
2401         status = myri10ge_reset(mgp);
2402         if (status != 0) {
2403                 netdev_err(dev, "failed reset\n");
2404                 goto abort_with_nothing;
2405         }
2406
2407         if (mgp->num_slices > 1) {
2408                 cmd.data0 = mgp->num_slices;
2409                 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
2410                 if (mgp->dev->real_num_tx_queues > 1)
2411                         cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
2412                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2413                                            &cmd, 0);
2414                 if (status != 0) {
2415                         netdev_err(dev, "failed to set number of slices\n");
2416                         goto abort_with_nothing;
2417                 }
2418                 /* setup the indirection table */
2419                 cmd.data0 = mgp->num_slices;
2420                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2421                                            &cmd, 0);
2422
2423                 status |= myri10ge_send_cmd(mgp,
2424                                             MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2425                                             &cmd, 0);
2426                 if (status != 0) {
2427                         netdev_err(dev, "failed to setup rss tables\n");
2428                         goto abort_with_nothing;
2429                 }
2430
2431                 /* just enable an identity mapping */
2432                 itable = mgp->sram + cmd.data0;
2433                 for (i = 0; i < mgp->num_slices; i++)
2434                         __raw_writeb(i, &itable[i]);
2435
2436                 cmd.data0 = 1;
2437                 cmd.data1 = myri10ge_rss_hash;
2438                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2439                                            &cmd, 0);
2440                 if (status != 0) {
2441                         netdev_err(dev, "failed to enable slices\n");
2442                         goto abort_with_nothing;
2443                 }
2444         }
2445
2446         status = myri10ge_request_irq(mgp);
2447         if (status != 0)
2448                 goto abort_with_nothing;
2449
2450         /* decide what small buffer size to use.  For good TCP rx
2451          * performance, it is important to not receive 1514 byte
2452          * frames into jumbo buffers, as it confuses the socket buffer
2453          * accounting code, leading to drops and erratic performance.
2454          */
2455
2456         if (dev->mtu <= ETH_DATA_LEN)
2457                 /* enough for a TCP header */
2458                 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2459                     ? (128 - MXGEFW_PAD)
2460                     : (SMP_CACHE_BYTES - MXGEFW_PAD);
2461         else
2462                 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2463                 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2464
2465         /* Override the small buffer size? */
2466         if (myri10ge_small_bytes > 0)
2467                 mgp->small_bytes = myri10ge_small_bytes;
2468
2469         /* Firmware needs the big buff size as a power of 2.  Lie and
2470          * tell him the buffer is larger, because we only use 1
2471          * buffer/pkt, and the mtu will prevent overruns.
2472          */
2473         big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2474         if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2475                 while (!is_power_of_2(big_pow2))
2476                         big_pow2++;
2477                 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2478         } else {
2479                 big_pow2 = MYRI10GE_ALLOC_SIZE;
2480                 mgp->big_bytes = big_pow2;
2481         }
2482
2483         /* setup the per-slice data structures */
2484         for (slice = 0; slice < mgp->num_slices; slice++) {
2485                 ss = &mgp->ss[slice];
2486
2487                 status = myri10ge_get_txrx(mgp, slice);
2488                 if (status != 0) {
2489                         netdev_err(dev, "failed to get ring sizes or locations\n");
2490                         goto abort_with_rings;
2491                 }
2492                 status = myri10ge_allocate_rings(ss);
2493                 if (status != 0)
2494                         goto abort_with_rings;
2495
2496                 /* only firmware which supports multiple TX queues
2497                  * supports setting up the tx stats on non-zero
2498                  * slices */
2499                 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2500                         status = myri10ge_set_stats(mgp, slice);
2501                 if (status) {
2502                         netdev_err(dev, "Couldn't set stats DMA\n");
2503                         goto abort_with_rings;
2504                 }
2505
2506                 lro_mgr = &ss->rx_done.lro_mgr;
2507                 lro_mgr->dev = dev;
2508                 lro_mgr->features = LRO_F_NAPI;
2509                 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2510                 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2511                 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2512                 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2513                 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2514                 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2515                 lro_mgr->frag_align_pad = 2;
2516                 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2517                         lro_mgr->max_aggr = MAX_SKB_FRAGS;
2518
2519                 /* must happen prior to any irq */
2520                 napi_enable(&(ss)->napi);
2521         }
2522
2523         /* now give firmware buffers sizes, and MTU */
2524         cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2525         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2526         cmd.data0 = mgp->small_bytes;
2527         status |=
2528             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2529         cmd.data0 = big_pow2;
2530         status |=
2531             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2532         if (status) {
2533                 netdev_err(dev, "Couldn't set buffer sizes\n");
2534                 goto abort_with_rings;
2535         }
2536
2537         /*
2538          * Set Linux style TSO mode; this is needed only on newer
2539          *  firmware versions.  Older versions default to Linux
2540          *  style TSO
2541          */
2542         cmd.data0 = 0;
2543         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2544         if (status && status != -ENOSYS) {
2545                 netdev_err(dev, "Couldn't set TSO mode\n");
2546                 goto abort_with_rings;
2547         }
2548
2549         mgp->link_state = ~0U;
2550         mgp->rdma_tags_available = 15;
2551
2552         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2553         if (status) {
2554                 netdev_err(dev, "Couldn't bring up link\n");
2555                 goto abort_with_rings;
2556         }
2557
2558         mgp->running = MYRI10GE_ETH_RUNNING;
2559         mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2560         add_timer(&mgp->watchdog_timer);
2561         netif_tx_wake_all_queues(dev);
2562
2563         return 0;
2564
2565 abort_with_rings:
2566         while (slice) {
2567                 slice--;
2568                 napi_disable(&mgp->ss[slice].napi);
2569         }
2570         for (i = 0; i < mgp->num_slices; i++)
2571                 myri10ge_free_rings(&mgp->ss[i]);
2572
2573         myri10ge_free_irq(mgp);
2574
2575 abort_with_nothing:
2576         mgp->running = MYRI10GE_ETH_STOPPED;
2577         return -ENOMEM;
2578 }
2579
2580 static int myri10ge_close(struct net_device *dev)
2581 {
2582         struct myri10ge_priv *mgp = netdev_priv(dev);
2583         struct myri10ge_cmd cmd;
2584         int status, old_down_cnt;
2585         int i;
2586
2587         if (mgp->running != MYRI10GE_ETH_RUNNING)
2588                 return 0;
2589
2590         if (mgp->ss[0].tx.req_bytes == NULL)
2591                 return 0;
2592
2593         del_timer_sync(&mgp->watchdog_timer);
2594         mgp->running = MYRI10GE_ETH_STOPPING;
2595         for (i = 0; i < mgp->num_slices; i++) {
2596                 napi_disable(&mgp->ss[i].napi);
2597         }
2598         netif_carrier_off(dev);
2599
2600         netif_tx_stop_all_queues(dev);
2601         if (mgp->rebooted == 0) {
2602                 old_down_cnt = mgp->down_cnt;
2603                 mb();
2604                 status =
2605                     myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2606                 if (status)
2607                         netdev_err(dev, "Couldn't bring down link\n");
2608
2609                 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2610                                    HZ);
2611                 if (old_down_cnt == mgp->down_cnt)
2612                         netdev_err(dev, "never got down irq\n");
2613         }
2614         netif_tx_disable(dev);
2615         myri10ge_free_irq(mgp);
2616         for (i = 0; i < mgp->num_slices; i++)
2617                 myri10ge_free_rings(&mgp->ss[i]);
2618
2619         mgp->running = MYRI10GE_ETH_STOPPED;
2620         return 0;
2621 }
2622
2623 /* copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2624  * backwards one at a time and handle ring wraps */
2625
2626 static inline void
2627 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2628                               struct mcp_kreq_ether_send *src, int cnt)
2629 {
2630         int idx, starting_slot;
2631         starting_slot = tx->req;
2632         while (cnt > 1) {
2633                 cnt--;
2634                 idx = (starting_slot + cnt) & tx->mask;
2635                 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2636                 mb();
2637         }
2638 }
2639
2640 /*
2641  * copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2642  * at most 32 bytes at a time, so as to avoid involving the software
2643  * pio handler in the nic.   We re-write the first segment's flags
2644  * to mark them valid only after writing the entire chain.
2645  */
2646
2647 static inline void
2648 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2649                     int cnt)
2650 {
2651         int idx, i;
2652         struct mcp_kreq_ether_send __iomem *dstp, *dst;
2653         struct mcp_kreq_ether_send *srcp;
2654         u8 last_flags;
2655
2656         idx = tx->req & tx->mask;
2657
2658         last_flags = src->flags;
2659         src->flags = 0;
2660         mb();
2661         dst = dstp = &tx->lanai[idx];
2662         srcp = src;
2663
2664         if ((idx + cnt) < tx->mask) {
2665                 for (i = 0; i < (cnt - 1); i += 2) {
2666                         myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2667                         mb();   /* force write every 32 bytes */
2668                         srcp += 2;
2669                         dstp += 2;
2670                 }
2671         } else {
2672                 /* submit all but the first request, and ensure
2673                  * that it is submitted below */
2674                 myri10ge_submit_req_backwards(tx, src, cnt);
2675                 i = 0;
2676         }
2677         if (i < cnt) {
2678                 /* submit the first request */
2679                 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2680                 mb();           /* barrier before setting valid flag */
2681         }
2682
2683         /* re-write the last 32-bits with the valid flags */
2684         src->flags = last_flags;
2685         put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2686         tx->req += cnt;
2687         mb();
2688 }
2689
2690 /*
2691  * Transmit a packet.  We need to split the packet so that a single
2692  * segment does not cross myri10ge->tx_boundary, so this makes segment
2693  * counting tricky.  So rather than try to count segments up front, we
2694  * just give up if there are too few segments to hold a reasonably
2695  * fragmented packet currently available.  If we run
2696  * out of segments while preparing a packet for DMA, we just linearize
2697  * it and try again.
2698  */
2699
2700 static netdev_tx_t myri10ge_xmit(struct sk_buff *skb,
2701                                        struct net_device *dev)
2702 {
2703         struct myri10ge_priv *mgp = netdev_priv(dev);
2704         struct myri10ge_slice_state *ss;
2705         struct mcp_kreq_ether_send *req;
2706         struct myri10ge_tx_buf *tx;
2707         struct skb_frag_struct *frag;
2708         struct netdev_queue *netdev_queue;
2709         dma_addr_t bus;
2710         u32 low;
2711         __be32 high_swapped;
2712         unsigned int len;
2713         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2714         u16 pseudo_hdr_offset, cksum_offset, queue;
2715         int cum_len, seglen, boundary, rdma_count;
2716         u8 flags, odd_flag;
2717
2718         queue = skb_get_queue_mapping(skb);
2719         ss = &mgp->ss[queue];
2720         netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2721         tx = &ss->tx;
2722
2723 again:
2724         req = tx->req_list;
2725         avail = tx->mask - 1 - (tx->req - tx->done);
2726
2727         mss = 0;
2728         max_segments = MXGEFW_MAX_SEND_DESC;
2729
2730         if (skb_is_gso(skb)) {
2731                 mss = skb_shinfo(skb)->gso_size;
2732                 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2733         }
2734
2735         if ((unlikely(avail < max_segments))) {
2736                 /* we are out of transmit resources */
2737                 tx->stop_queue++;
2738                 netif_tx_stop_queue(netdev_queue);
2739                 return NETDEV_TX_BUSY;
2740         }
2741
2742         /* Setup checksum offloading, if needed */
2743         cksum_offset = 0;
2744         pseudo_hdr_offset = 0;
2745         odd_flag = 0;
2746         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2747         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2748                 cksum_offset = skb_checksum_start_offset(skb);
2749                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2750                 /* If the headers are excessively large, then we must
2751                  * fall back to a software checksum */
2752                 if (unlikely(!mss && (cksum_offset > 255 ||
2753                                       pseudo_hdr_offset > 127))) {
2754                         if (skb_checksum_help(skb))
2755                                 goto drop;
2756                         cksum_offset = 0;
2757                         pseudo_hdr_offset = 0;
2758                 } else {
2759                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2760                         flags |= MXGEFW_FLAGS_CKSUM;
2761                 }
2762         }
2763
2764         cum_len = 0;
2765
2766         if (mss) {              /* TSO */
2767                 /* this removes any CKSUM flag from before */
2768                 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2769
2770                 /* negative cum_len signifies to the
2771                  * send loop that we are still in the
2772                  * header portion of the TSO packet.
2773                  * TSO header can be at most 1KB long */
2774                 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2775
2776                 /* for IPv6 TSO, the checksum offset stores the
2777                  * TCP header length, to save the firmware from
2778                  * the need to parse the headers */
2779                 if (skb_is_gso_v6(skb)) {
2780                         cksum_offset = tcp_hdrlen(skb);
2781                         /* Can only handle headers <= max_tso6 long */
2782                         if (unlikely(-cum_len > mgp->max_tso6))
2783                                 return myri10ge_sw_tso(skb, dev);
2784                 }
2785                 /* for TSO, pseudo_hdr_offset holds mss.
2786                  * The firmware figures out where to put
2787                  * the checksum by parsing the header. */
2788                 pseudo_hdr_offset = mss;
2789         } else
2790                 /* Mark small packets, and pad out tiny packets */
2791         if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2792                 flags |= MXGEFW_FLAGS_SMALL;
2793
2794                 /* pad frames to at least ETH_ZLEN bytes */
2795                 if (unlikely(skb->len < ETH_ZLEN)) {
2796                         if (skb_padto(skb, ETH_ZLEN)) {
2797                                 /* The packet is gone, so we must
2798                                  * return 0 */
2799                                 ss->stats.tx_dropped += 1;
2800                                 return NETDEV_TX_OK;
2801                         }
2802                         /* adjust the len to account for the zero pad
2803                          * so that the nic can know how long it is */
2804                         skb->len = ETH_ZLEN;
2805                 }
2806         }
2807
2808         /* map the skb for DMA */
2809         len = skb_headlen(skb);
2810         idx = tx->req & tx->mask;
2811         tx->info[idx].skb = skb;
2812         bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2813         dma_unmap_addr_set(&tx->info[idx], bus, bus);
2814         dma_unmap_len_set(&tx->info[idx], len, len);
2815
2816         frag_cnt = skb_shinfo(skb)->nr_frags;
2817         frag_idx = 0;
2818         count = 0;
2819         rdma_count = 0;
2820
2821         /* "rdma_count" is the number of RDMAs belonging to the
2822          * current packet BEFORE the current send request. For
2823          * non-TSO packets, this is equal to "count".
2824          * For TSO packets, rdma_count needs to be reset
2825          * to 0 after a segment cut.
2826          *
2827          * The rdma_count field of the send request is
2828          * the number of RDMAs of the packet starting at
2829          * that request. For TSO send requests with one ore more cuts
2830          * in the middle, this is the number of RDMAs starting
2831          * after the last cut in the request. All previous
2832          * segments before the last cut implicitly have 1 RDMA.
2833          *
2834          * Since the number of RDMAs is not known beforehand,
2835          * it must be filled-in retroactively - after each
2836          * segmentation cut or at the end of the entire packet.
2837          */
2838
2839         while (1) {
2840                 /* Break the SKB or Fragment up into pieces which
2841                  * do not cross mgp->tx_boundary */
2842                 low = MYRI10GE_LOWPART_TO_U32(bus);
2843                 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2844                 while (len) {
2845                         u8 flags_next;
2846                         int cum_len_next;
2847
2848                         if (unlikely(count == max_segments))
2849                                 goto abort_linearize;
2850
2851                         boundary =
2852                             (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2853                         seglen = boundary - low;
2854                         if (seglen > len)
2855                                 seglen = len;
2856                         flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2857                         cum_len_next = cum_len + seglen;
2858                         if (mss) {      /* TSO */
2859                                 (req - rdma_count)->rdma_count = rdma_count + 1;
2860
2861                                 if (likely(cum_len >= 0)) {     /* payload */
2862                                         int next_is_first, chop;
2863
2864                                         chop = (cum_len_next > mss);
2865                                         cum_len_next = cum_len_next % mss;
2866                                         next_is_first = (cum_len_next == 0);
2867                                         flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2868                                         flags_next |= next_is_first *
2869                                             MXGEFW_FLAGS_FIRST;
2870                                         rdma_count |= -(chop | next_is_first);
2871                                         rdma_count += chop & !next_is_first;
2872                                 } else if (likely(cum_len_next >= 0)) { /* header ends */
2873                                         int small;
2874
2875                                         rdma_count = -1;
2876                                         cum_len_next = 0;
2877                                         seglen = -cum_len;
2878                                         small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2879                                         flags_next = MXGEFW_FLAGS_TSO_PLD |
2880                                             MXGEFW_FLAGS_FIRST |
2881                                             (small * MXGEFW_FLAGS_SMALL);
2882                                 }
2883                         }
2884                         req->addr_high = high_swapped;
2885                         req->addr_low = htonl(low);
2886                         req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2887                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
2888                         req->rdma_count = 1;
2889                         req->length = htons(seglen);
2890                         req->cksum_offset = cksum_offset;
2891                         req->flags = flags | ((cum_len & 1) * odd_flag);
2892
2893                         low += seglen;
2894                         len -= seglen;
2895                         cum_len = cum_len_next;
2896                         flags = flags_next;
2897                         req++;
2898                         count++;
2899                         rdma_count++;
2900                         if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2901                                 if (unlikely(cksum_offset > seglen))
2902                                         cksum_offset -= seglen;
2903                                 else
2904                                         cksum_offset = 0;
2905                         }
2906                 }
2907                 if (frag_idx == frag_cnt)
2908                         break;
2909
2910                 /* map next fragment for DMA */
2911                 idx = (count + tx->req) & tx->mask;
2912                 frag = &skb_shinfo(skb)->frags[frag_idx];
2913                 frag_idx++;
2914                 len = frag->size;
2915                 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2916                                    len, PCI_DMA_TODEVICE);
2917                 dma_unmap_addr_set(&tx->info[idx], bus, bus);
2918                 dma_unmap_len_set(&tx->info[idx], len, len);
2919         }
2920
2921         (req - rdma_count)->rdma_count = rdma_count;
2922         if (mss)
2923                 do {
2924                         req--;
2925                         req->flags |= MXGEFW_FLAGS_TSO_LAST;
2926                 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2927                                          MXGEFW_FLAGS_FIRST)));
2928         idx = ((count - 1) + tx->req) & tx->mask;
2929         tx->info[idx].last = 1;
2930         myri10ge_submit_req(tx, tx->req_list, count);
2931         /* if using multiple tx queues, make sure NIC polls the
2932          * current slice */
2933         if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2934                 tx->queue_active = 1;
2935                 put_be32(htonl(1), tx->send_go);
2936                 mb();
2937                 mmiowb();
2938         }
2939         tx->pkt_start++;
2940         if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2941                 tx->stop_queue++;
2942                 netif_tx_stop_queue(netdev_queue);
2943         }
2944         return NETDEV_TX_OK;
2945
2946 abort_linearize:
2947         /* Free any DMA resources we've alloced and clear out the skb
2948          * slot so as to not trip up assertions, and to avoid a
2949          * double-free if linearizing fails */
2950
2951         last_idx = (idx + 1) & tx->mask;
2952         idx = tx->req & tx->mask;
2953         tx->info[idx].skb = NULL;
2954         do {
2955                 len = dma_unmap_len(&tx->info[idx], len);
2956                 if (len) {
2957                         if (tx->info[idx].skb != NULL)
2958                                 pci_unmap_single(mgp->pdev,
2959                                                  dma_unmap_addr(&tx->info[idx],
2960                                                                 bus), len,
2961                                                  PCI_DMA_TODEVICE);
2962                         else
2963                                 pci_unmap_page(mgp->pdev,
2964                                                dma_unmap_addr(&tx->info[idx],
2965                                                               bus), len,
2966                                                PCI_DMA_TODEVICE);
2967                         dma_unmap_len_set(&tx->info[idx], len, 0);
2968                         tx->info[idx].skb = NULL;
2969                 }
2970                 idx = (idx + 1) & tx->mask;
2971         } while (idx != last_idx);
2972         if (skb_is_gso(skb)) {
2973                 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
2974                 goto drop;
2975         }
2976
2977         if (skb_linearize(skb))
2978                 goto drop;
2979
2980         tx->linearized++;
2981         goto again;
2982
2983 drop:
2984         dev_kfree_skb_any(skb);
2985         ss->stats.tx_dropped += 1;
2986         return NETDEV_TX_OK;
2987
2988 }
2989
2990 static netdev_tx_t myri10ge_sw_tso(struct sk_buff *skb,
2991                                          struct net_device *dev)
2992 {
2993         struct sk_buff *segs, *curr;
2994         struct myri10ge_priv *mgp = netdev_priv(dev);
2995         struct myri10ge_slice_state *ss;
2996         netdev_tx_t status;
2997
2998         segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2999         if (IS_ERR(segs))
3000                 goto drop;
3001
3002         while (segs) {
3003                 curr = segs;
3004                 segs = segs->next;
3005                 curr->next = NULL;
3006                 status = myri10ge_xmit(curr, dev);
3007                 if (status != 0) {
3008                         dev_kfree_skb_any(curr);
3009                         if (segs != NULL) {
3010                                 curr = segs;
3011                                 segs = segs->next;
3012                                 curr->next = NULL;
3013                                 dev_kfree_skb_any(segs);
3014                         }
3015                         goto drop;
3016                 }
3017         }
3018         dev_kfree_skb_any(skb);
3019         return NETDEV_TX_OK;
3020
3021 drop:
3022         ss = &mgp->ss[skb_get_queue_mapping(skb)];
3023         dev_kfree_skb_any(skb);
3024         ss->stats.tx_dropped += 1;
3025         return NETDEV_TX_OK;
3026 }
3027
3028 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
3029 {
3030         struct myri10ge_priv *mgp = netdev_priv(dev);
3031         struct myri10ge_slice_netstats *slice_stats;
3032         struct net_device_stats *stats = &dev->stats;
3033         int i;
3034
3035         spin_lock(&mgp->stats_lock);
3036         memset(stats, 0, sizeof(*stats));
3037         for (i = 0; i < mgp->num_slices; i++) {
3038                 slice_stats = &mgp->ss[i].stats;
3039                 stats->rx_packets += slice_stats->rx_packets;
3040                 stats->tx_packets += slice_stats->tx_packets;
3041                 stats->rx_bytes += slice_stats->rx_bytes;
3042                 stats->tx_bytes += slice_stats->tx_bytes;
3043                 stats->rx_dropped += slice_stats->rx_dropped;
3044                 stats->tx_dropped += slice_stats->tx_dropped;
3045         }
3046         spin_unlock(&mgp->stats_lock);
3047         return stats;
3048 }
3049
3050 static void myri10ge_set_multicast_list(struct net_device *dev)
3051 {
3052         struct myri10ge_priv *mgp = netdev_priv(dev);
3053         struct myri10ge_cmd cmd;
3054         struct netdev_hw_addr *ha;
3055         __be32 data[2] = { 0, 0 };
3056         int err;
3057
3058         /* can be called from atomic contexts,
3059          * pass 1 to force atomicity in myri10ge_send_cmd() */
3060         myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
3061
3062         /* This firmware is known to not support multicast */
3063         if (!mgp->fw_multicast_support)
3064                 return;
3065
3066         /* Disable multicast filtering */
3067
3068         err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
3069         if (err != 0) {
3070                 netdev_err(dev, "Failed MXGEFW_ENABLE_ALLMULTI, error status: %d\n",
3071                            err);
3072                 goto abort;
3073         }
3074
3075         if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
3076                 /* request to disable multicast filtering, so quit here */
3077                 return;
3078         }
3079
3080         /* Flush the filters */
3081
3082         err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
3083                                 &cmd, 1);
3084         if (err != 0) {
3085                 netdev_err(dev, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, error status: %d\n",
3086                            err);
3087                 goto abort;
3088         }
3089
3090         /* Walk the multicast list, and add each address */
3091         netdev_for_each_mc_addr(ha, dev) {
3092                 memcpy(data, &ha->addr, 6);
3093                 cmd.data0 = ntohl(data[0]);
3094                 cmd.data1 = ntohl(data[1]);
3095                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
3096                                         &cmd, 1);
3097
3098                 if (err != 0) {
3099                         netdev_err(dev, "Failed MXGEFW_JOIN_MULTICAST_GROUP, error status:%d %pM\n",
3100                                    err, ha->addr);
3101                         goto abort;
3102                 }
3103         }
3104         /* Enable multicast filtering */
3105         err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3106         if (err != 0) {
3107                 netdev_err(dev, "Failed MXGEFW_DISABLE_ALLMULTI, error status: %d\n",
3108                            err);
3109                 goto abort;
3110         }
3111
3112         return;
3113
3114 abort:
3115         return;
3116 }
3117
3118 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3119 {
3120         struct sockaddr *sa = addr;
3121         struct myri10ge_priv *mgp = netdev_priv(dev);
3122         int status;
3123
3124         if (!is_valid_ether_addr(sa->sa_data))
3125                 return -EADDRNOTAVAIL;
3126
3127         status = myri10ge_update_mac_address(mgp, sa->sa_data);
3128         if (status != 0) {
3129                 netdev_err(dev, "changing mac address failed with %d\n",
3130                            status);
3131                 return status;
3132         }
3133
3134         /* change the dev structure */
3135         memcpy(dev->dev_addr, sa->sa_data, 6);
3136         return 0;
3137 }
3138
3139 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3140 {
3141         struct myri10ge_priv *mgp = netdev_priv(dev);
3142         int error = 0;
3143
3144         if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3145                 netdev_err(dev, "new mtu (%d) is not valid\n", new_mtu);
3146                 return -EINVAL;
3147         }
3148         netdev_info(dev, "changing mtu from %d to %d\n", dev->mtu, new_mtu);
3149         if (mgp->running) {
3150                 /* if we change the mtu on an active device, we must
3151                  * reset the device so the firmware sees the change */
3152                 myri10ge_close(dev);
3153                 dev->mtu = new_mtu;
3154                 myri10ge_open(dev);
3155         } else
3156                 dev->mtu = new_mtu;
3157
3158         return error;
3159 }
3160
3161 /*
3162  * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3163  * Only do it if the bridge is a root port since we don't want to disturb
3164  * any other device, except if forced with myri10ge_ecrc_enable > 1.
3165  */
3166
3167 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3168 {
3169         struct pci_dev *bridge = mgp->pdev->bus->self;
3170         struct device *dev = &mgp->pdev->dev;
3171         unsigned cap;
3172         unsigned err_cap;
3173         u16 val;
3174         u8 ext_type;
3175         int ret;
3176
3177         if (!myri10ge_ecrc_enable || !bridge)
3178                 return;
3179
3180         /* check that the bridge is a root port */
3181         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3182         pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3183         ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3184         if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3185                 if (myri10ge_ecrc_enable > 1) {
3186                         struct pci_dev *prev_bridge, *old_bridge = bridge;
3187
3188                         /* Walk the hierarchy up to the root port
3189                          * where ECRC has to be enabled */
3190                         do {
3191                                 prev_bridge = bridge;
3192                                 bridge = bridge->bus->self;
3193                                 if (!bridge || prev_bridge == bridge) {
3194                                         dev_err(dev,
3195                                                 "Failed to find root port"
3196                                                 " to force ECRC\n");
3197                                         return;
3198                                 }
3199                                 cap =
3200                                     pci_find_capability(bridge, PCI_CAP_ID_EXP);
3201                                 pci_read_config_word(bridge,
3202                                                      cap + PCI_CAP_FLAGS, &val);
3203                                 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3204                         } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3205
3206                         dev_info(dev,
3207                                  "Forcing ECRC on non-root port %s"
3208                                  " (enabling on root port %s)\n",
3209                                  pci_name(old_bridge), pci_name(bridge));
3210                 } else {
3211                         dev_err(dev,
3212                                 "Not enabling ECRC on non-root port %s\n",
3213                                 pci_name(bridge));
3214                         return;
3215                 }
3216         }
3217
3218         cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3219         if (!cap)
3220                 return;
3221
3222         ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3223         if (ret) {
3224                 dev_err(dev, "failed reading ext-conf-space of %s\n",
3225                         pci_name(bridge));
3226                 dev_err(dev, "\t pci=nommconf in use? "
3227                         "or buggy/incomplete/absent ACPI MCFG attr?\n");
3228                 return;
3229         }
3230         if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3231                 return;
3232
3233         err_cap |= PCI_ERR_CAP_ECRC_GENE;
3234         pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3235         dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3236 }
3237
3238 /*
3239  * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3240  * when the PCI-E Completion packets are aligned on an 8-byte
3241  * boundary.  Some PCI-E chip sets always align Completion packets; on
3242  * the ones that do not, the alignment can be enforced by enabling
3243  * ECRC generation (if supported).
3244  *
3245  * When PCI-E Completion packets are not aligned, it is actually more
3246  * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3247  *
3248  * If the driver can neither enable ECRC nor verify that it has
3249  * already been enabled, then it must use a firmware image which works
3250  * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3251  * should also ensure that it never gives the device a Read-DMA which is
3252  * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
3253  * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3254  * firmware image, and set tx_boundary to 4KB.
3255  */
3256
3257 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3258 {
3259         struct pci_dev *pdev = mgp->pdev;
3260         struct device *dev = &pdev->dev;
3261         int status;
3262
3263         mgp->tx_boundary = 4096;
3264         /*
3265          * Verify the max read request size was set to 4KB
3266          * before trying the test with 4KB.
3267          */
3268         status = pcie_get_readrq(pdev);
3269         if (status < 0) {
3270                 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3271                 goto abort;
3272         }
3273         if (status != 4096) {
3274                 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3275                 mgp->tx_boundary = 2048;
3276         }
3277         /*
3278          * load the optimized firmware (which assumes aligned PCIe
3279          * completions) in order to see if it works on this host.
3280          */
3281         set_fw_name(mgp, myri10ge_fw_aligned, false);
3282         status = myri10ge_load_firmware(mgp, 1);
3283         if (status != 0) {
3284                 goto abort;
3285         }
3286
3287         /*
3288          * Enable ECRC if possible
3289          */
3290         myri10ge_enable_ecrc(mgp);
3291
3292         /*
3293          * Run a DMA test which watches for unaligned completions and
3294          * aborts on the first one seen.
3295          */
3296
3297         status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3298         if (status == 0)
3299                 return;         /* keep the aligned firmware */
3300
3301         if (status != -E2BIG)
3302                 dev_warn(dev, "DMA test failed: %d\n", status);
3303         if (status == -ENOSYS)
3304                 dev_warn(dev, "Falling back to ethp! "
3305                          "Please install up to date fw\n");
3306 abort:
3307         /* fall back to using the unaligned firmware */
3308         mgp->tx_boundary = 2048;
3309         set_fw_name(mgp, myri10ge_fw_unaligned, false);
3310
3311 }
3312
3313 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3314 {
3315         int overridden = 0;
3316
3317         if (myri10ge_force_firmware == 0) {
3318                 int link_width, exp_cap;
3319                 u16 lnk;
3320
3321                 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3322                 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3323                 link_width = (lnk >> 4) & 0x3f;
3324
3325                 /* Check to see if Link is less than 8 or if the
3326                  * upstream bridge is known to provide aligned
3327                  * completions */
3328                 if (link_width < 8) {
3329                         dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3330                                  link_width);
3331                         mgp->tx_boundary = 4096;
3332                         set_fw_name(mgp, myri10ge_fw_aligned, false);
3333                 } else {
3334                         myri10ge_firmware_probe(mgp);
3335                 }
3336         } else {
3337                 if (myri10ge_force_firmware == 1) {
3338                         dev_info(&mgp->pdev->dev,
3339                                  "Assuming aligned completions (forced)\n");
3340                         mgp->tx_boundary = 4096;
3341                         set_fw_name(mgp, myri10ge_fw_aligned, false);
3342                 } else {
3343                         dev_info(&mgp->pdev->dev,
3344                                  "Assuming unaligned completions (forced)\n");
3345                         mgp->tx_boundary = 2048;
3346                         set_fw_name(mgp, myri10ge_fw_unaligned, false);
3347                 }
3348         }
3349
3350         kparam_block_sysfs_write(myri10ge_fw_name);
3351         if (myri10ge_fw_name != NULL) {
3352                 char *fw_name = kstrdup(myri10ge_fw_name, GFP_KERNEL);
3353                 if (fw_name) {
3354                         overridden = 1;
3355                         set_fw_name(mgp, fw_name, true);
3356                 }
3357         }
3358         kparam_unblock_sysfs_write(myri10ge_fw_name);
3359
3360         if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3361             myri10ge_fw_names[mgp->board_number] != NULL &&
3362             strlen(myri10ge_fw_names[mgp->board_number])) {
3363                 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
3364                 overridden = 1;
3365         }
3366         if (overridden)
3367                 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3368                          mgp->fw_name);
3369 }
3370
3371 #ifdef CONFIG_PM
3372 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3373 {
3374         struct myri10ge_priv *mgp;
3375         struct net_device *netdev;
3376
3377         mgp = pci_get_drvdata(pdev);
3378         if (mgp == NULL)
3379                 return -EINVAL;
3380         netdev = mgp->dev;
3381
3382         netif_device_detach(netdev);
3383         if (netif_running(netdev)) {
3384                 netdev_info(netdev, "closing\n");
3385                 rtnl_lock();
3386                 myri10ge_close(netdev);
3387                 rtnl_unlock();
3388         }
3389         myri10ge_dummy_rdma(mgp, 0);
3390         pci_save_state(pdev);
3391         pci_disable_device(pdev);
3392
3393         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3394 }
3395
3396 static int myri10ge_resume(struct pci_dev *pdev)
3397 {
3398         struct myri10ge_priv *mgp;
3399         struct net_device *netdev;
3400         int status;
3401         u16 vendor;
3402
3403         mgp = pci_get_drvdata(pdev);
3404         if (mgp == NULL)
3405                 return -EINVAL;
3406         netdev = mgp->dev;
3407         pci_set_power_state(pdev, 0);   /* zeros conf space as a side effect */
3408         msleep(5);              /* give card time to respond */
3409         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3410         if (vendor == 0xffff) {
3411                 netdev_err(mgp->dev, "device disappeared!\n");
3412                 return -EIO;
3413         }
3414
3415         pci_restore_state(pdev);
3416
3417         status = pci_enable_device(pdev);
3418         if (status) {
3419                 dev_err(&pdev->dev, "failed to enable device\n");
3420                 return status;
3421         }
3422
3423         pci_set_master(pdev);
3424
3425         myri10ge_reset(mgp);
3426         myri10ge_dummy_rdma(mgp, 1);
3427
3428         /* Save configuration space to be restored if the
3429          * nic resets due to a parity error */
3430         pci_save_state(pdev);
3431
3432         if (netif_running(netdev)) {
3433                 rtnl_lock();
3434                 status = myri10ge_open(netdev);
3435                 rtnl_unlock();
3436                 if (status != 0)
3437                         goto abort_with_enabled;
3438
3439         }
3440         netif_device_attach(netdev);
3441
3442         return 0;
3443
3444 abort_with_enabled:
3445         pci_disable_device(pdev);
3446         return -EIO;
3447
3448 }
3449 #endif                          /* CONFIG_PM */
3450
3451 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3452 {
3453         struct pci_dev *pdev = mgp->pdev;
3454         int vs = mgp->vendor_specific_offset;
3455         u32 reboot;
3456
3457         /*enter read32 mode */
3458         pci_write_config_byte(pdev, vs + 0x10, 0x3);
3459
3460         /*read REBOOT_STATUS (0xfffffff0) */
3461         pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3462         pci_read_config_dword(pdev, vs + 0x14, &reboot);
3463         return reboot;
3464 }
3465
3466 /*
3467  * This watchdog is used to check whether the board has suffered
3468  * from a parity error and needs to be recovered.
3469  */
3470 static void myri10ge_watchdog(struct work_struct *work)
3471 {
3472         struct myri10ge_priv *mgp =
3473             container_of(work, struct myri10ge_priv, watchdog_work);
3474         struct myri10ge_tx_buf *tx;
3475         u32 reboot;
3476         int status, rebooted;
3477         int i;
3478         u16 cmd, vendor;
3479
3480         mgp->watchdog_resets++;
3481         pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3482         rebooted = 0;
3483         if ((cmd & PCI_COMMAND_MASTER) == 0) {
3484                 /* Bus master DMA disabled?  Check to see
3485                  * if the card rebooted due to a parity error
3486                  * For now, just report it */
3487                 reboot = myri10ge_read_reboot(mgp);
3488                 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3489                            reboot,
3490                            myri10ge_reset_recover ? "" : " not");
3491                 if (myri10ge_reset_recover == 0)
3492                         return;
3493                 rtnl_lock();
3494                 mgp->rebooted = 1;
3495                 rebooted = 1;
3496                 myri10ge_close(mgp->dev);
3497                 myri10ge_reset_recover--;
3498                 mgp->rebooted = 0;
3499                 /*
3500                  * A rebooted nic will come back with config space as
3501                  * it was after power was applied to PCIe bus.
3502                  * Attempt to restore config space which was saved
3503                  * when the driver was loaded, or the last time the
3504                  * nic was resumed from power saving mode.
3505                  */
3506                 pci_restore_state(mgp->pdev);
3507
3508                 /* save state again for accounting reasons */
3509                 pci_save_state(mgp->pdev);
3510
3511         } else {
3512                 /* if we get back -1's from our slot, perhaps somebody
3513                  * powered off our card.  Don't try to reset it in
3514                  * this case */
3515                 if (cmd == 0xffff) {
3516                         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3517                         if (vendor == 0xffff) {
3518                                 netdev_err(mgp->dev, "device disappeared!\n");
3519                                 return;
3520                         }
3521                 }
3522                 /* Perhaps it is a software error.  Try to reset */
3523
3524                 netdev_err(mgp->dev, "device timeout, resetting\n");
3525                 for (i = 0; i < mgp->num_slices; i++) {
3526                         tx = &mgp->ss[i].tx;
3527                         netdev_err(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3528                                    i, tx->queue_active, tx->req,
3529                                    tx->done, tx->pkt_start, tx->pkt_done,
3530                                    (int)ntohl(mgp->ss[i].fw_stats->
3531                                               send_done_count));
3532                         msleep(2000);
3533                         netdev_info(mgp->dev, "(%d): %d %d %d %d %d %d\n",
3534                                     i, tx->queue_active, tx->req,
3535                                     tx->done, tx->pkt_start, tx->pkt_done,
3536                                     (int)ntohl(mgp->ss[i].fw_stats->
3537                                                send_done_count));
3538                 }
3539         }
3540
3541         if (!rebooted) {
3542                 rtnl_lock();
3543                 myri10ge_close(mgp->dev);
3544         }
3545         status = myri10ge_load_firmware(mgp, 1);
3546         if (status != 0)
3547                 netdev_err(mgp->dev, "failed to load firmware\n");
3548         else
3549                 myri10ge_open(mgp->dev);
3550         rtnl_unlock();
3551 }
3552
3553 /*
3554  * We use our own timer routine rather than relying upon
3555  * netdev->tx_timeout because we have a very large hardware transmit
3556  * queue.  Due to the large queue, the netdev->tx_timeout function
3557  * cannot detect a NIC with a parity error in a timely fashion if the
3558  * NIC is lightly loaded.
3559  */
3560 static void myri10ge_watchdog_timer(unsigned long arg)
3561 {
3562         struct myri10ge_priv *mgp;
3563         struct myri10ge_slice_state *ss;
3564         int i, reset_needed, busy_slice_cnt;
3565         u32 rx_pause_cnt;
3566         u16 cmd;
3567
3568         mgp = (struct myri10ge_priv *)arg;
3569
3570         rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3571         busy_slice_cnt = 0;
3572         for (i = 0, reset_needed = 0;
3573              i < mgp->num_slices && reset_needed == 0; ++i) {
3574
3575                 ss = &mgp->ss[i];
3576                 if (ss->rx_small.watchdog_needed) {
3577                         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3578                                                 mgp->small_bytes + MXGEFW_PAD,
3579                                                 1);
3580                         if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3581                             myri10ge_fill_thresh)
3582                                 ss->rx_small.watchdog_needed = 0;
3583                 }
3584                 if (ss->rx_big.watchdog_needed) {
3585                         myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3586                                                 mgp->big_bytes, 1);
3587                         if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3588                             myri10ge_fill_thresh)
3589                                 ss->rx_big.watchdog_needed = 0;
3590                 }
3591
3592                 if (ss->tx.req != ss->tx.done &&
3593                     ss->tx.done == ss->watchdog_tx_done &&
3594                     ss->watchdog_tx_req != ss->watchdog_tx_done) {
3595                         /* nic seems like it might be stuck.. */
3596                         if (rx_pause_cnt != mgp->watchdog_pause) {
3597                                 if (net_ratelimit())
3598                                         netdev_err(mgp->dev, "slice %d: TX paused, check link partner\n",
3599                                                    i);
3600                         } else {
3601                                 netdev_warn(mgp->dev, "slice %d stuck:", i);
3602                                 reset_needed = 1;
3603                         }
3604                 }
3605                 if (ss->watchdog_tx_done != ss->tx.done ||
3606                     ss->watchdog_rx_done != ss->rx_done.cnt) {
3607                         busy_slice_cnt++;
3608                 }
3609                 ss->watchdog_tx_done = ss->tx.done;
3610                 ss->watchdog_tx_req = ss->tx.req;
3611                 ss->watchdog_rx_done = ss->rx_done.cnt;
3612         }
3613         /* if we've sent or received no traffic, poll the NIC to
3614          * ensure it is still there.  Otherwise, we risk not noticing
3615          * an error in a timely fashion */
3616         if (busy_slice_cnt == 0) {
3617                 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3618                 if ((cmd & PCI_COMMAND_MASTER) == 0) {
3619                         reset_needed = 1;
3620                 }
3621         }
3622         mgp->watchdog_pause = rx_pause_cnt;
3623
3624         if (reset_needed) {
3625                 schedule_work(&mgp->watchdog_work);
3626         } else {
3627                 /* rearm timer */
3628                 mod_timer(&mgp->watchdog_timer,
3629                           jiffies + myri10ge_watchdog_timeout * HZ);
3630         }
3631 }
3632
3633 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3634 {
3635         struct myri10ge_slice_state *ss;
3636         struct pci_dev *pdev = mgp->pdev;
3637         size_t bytes;
3638         int i;
3639
3640         if (mgp->ss == NULL)
3641                 return;
3642
3643         for (i = 0; i < mgp->num_slices; i++) {
3644                 ss = &mgp->ss[i];
3645                 if (ss->rx_done.entry != NULL) {
3646                         bytes = mgp->max_intr_slots *
3647                             sizeof(*ss->rx_done.entry);
3648                         dma_free_coherent(&pdev->dev, bytes,
3649                                           ss->rx_done.entry, ss->rx_done.bus);
3650                         ss->rx_done.entry = NULL;
3651                 }
3652                 if (ss->fw_stats != NULL) {
3653                         bytes = sizeof(*ss->fw_stats);
3654                         dma_free_coherent(&pdev->dev, bytes,
3655                                           ss->fw_stats, ss->fw_stats_bus);
3656                         ss->fw_stats = NULL;
3657                         netif_napi_del(&ss->napi);
3658                 }
3659         }
3660         kfree(mgp->ss);
3661         mgp->ss = NULL;
3662 }
3663
3664 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3665 {
3666         struct myri10ge_slice_state *ss;
3667         struct pci_dev *pdev = mgp->pdev;
3668         size_t bytes;
3669         int i;
3670
3671         bytes = sizeof(*mgp->ss) * mgp->num_slices;
3672         mgp->ss = kzalloc(bytes, GFP_KERNEL);
3673         if (mgp->ss == NULL) {
3674                 return -ENOMEM;
3675         }
3676
3677         for (i = 0; i < mgp->num_slices; i++) {
3678                 ss = &mgp->ss[i];
3679                 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3680                 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3681                                                        &ss->rx_done.bus,
3682                                                        GFP_KERNEL);
3683                 if (ss->rx_done.entry == NULL)
3684                         goto abort;
3685                 memset(ss->rx_done.entry, 0, bytes);
3686                 bytes = sizeof(*ss->fw_stats);
3687                 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3688                                                   &ss->fw_stats_bus,
3689                                                   GFP_KERNEL);
3690                 if (ss->fw_stats == NULL)
3691                         goto abort;
3692                 ss->mgp = mgp;
3693                 ss->dev = mgp->dev;
3694                 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3695                                myri10ge_napi_weight);
3696         }
3697         return 0;
3698 abort:
3699         myri10ge_free_slices(mgp);
3700         return -ENOMEM;
3701 }
3702
3703 /*
3704  * This function determines the number of slices supported.
3705  * The number slices is the minumum of the number of CPUS,
3706  * the number of MSI-X irqs supported, the number of slices
3707  * supported by the firmware
3708  */
3709 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3710 {
3711         struct myri10ge_cmd cmd;
3712         struct pci_dev *pdev = mgp->pdev;
3713         char *old_fw;
3714         bool old_allocated;
3715         int i, status, ncpus, msix_cap;
3716
3717         mgp->num_slices = 1;
3718         msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3719         ncpus = num_online_cpus();
3720
3721         if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3722             (myri10ge_max_slices == -1 && ncpus < 2))
3723                 return;
3724
3725         /* try to load the slice aware rss firmware */
3726         old_fw = mgp->fw_name;
3727         old_allocated = mgp->fw_name_allocated;
3728         /* don't free old_fw if we override it. */
3729         mgp->fw_name_allocated = false;
3730
3731         if (myri10ge_fw_name != NULL) {
3732                 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3733                          myri10ge_fw_name);
3734                 set_fw_name(mgp, myri10ge_fw_name, false);
3735         } else if (old_fw == myri10ge_fw_aligned)
3736                 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
3737         else
3738                 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
3739         status = myri10ge_load_firmware(mgp, 0);
3740         if (status != 0) {
3741                 dev_info(&pdev->dev, "Rss firmware not found\n");
3742                 if (old_allocated)
3743                         kfree(old_fw);
3744                 return;
3745         }
3746
3747         /* hit the board with a reset to ensure it is alive */
3748         memset(&cmd, 0, sizeof(cmd));
3749         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3750         if (status != 0) {
3751                 dev_err(&mgp->pdev->dev, "failed reset\n");
3752                 goto abort_with_fw;
3753         }
3754
3755         mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3756
3757         /* tell it the size of the interrupt queues */
3758         cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3759         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3760         if (status != 0) {
3761                 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3762                 goto abort_with_fw;
3763         }
3764
3765         /* ask the maximum number of slices it supports */
3766         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3767         if (status != 0)
3768                 goto abort_with_fw;
3769         else
3770                 mgp->num_slices = cmd.data0;
3771
3772         /* Only allow multiple slices if MSI-X is usable */
3773         if (!myri10ge_msi) {
3774                 goto abort_with_fw;
3775         }
3776
3777         /* if the admin did not specify a limit to how many
3778          * slices we should use, cap it automatically to the
3779          * number of CPUs currently online */
3780         if (myri10ge_max_slices == -1)
3781                 myri10ge_max_slices = ncpus;
3782
3783         if (mgp->num_slices > myri10ge_max_slices)
3784                 mgp->num_slices = myri10ge_max_slices;
3785
3786         /* Now try to allocate as many MSI-X vectors as we have
3787          * slices. We give up on MSI-X if we can only get a single
3788          * vector. */
3789
3790         mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3791                                     GFP_KERNEL);
3792         if (mgp->msix_vectors == NULL)
3793                 goto disable_msix;
3794         for (i = 0; i < mgp->num_slices; i++) {
3795                 mgp->msix_vectors[i].entry = i;
3796         }
3797
3798         while (mgp->num_slices > 1) {
3799                 /* make sure it is a power of two */
3800                 while (!is_power_of_2(mgp->num_slices))
3801                         mgp->num_slices--;
3802                 if (mgp->num_slices == 1)
3803                         goto disable_msix;
3804                 status = pci_enable_msix(pdev, mgp->msix_vectors,
3805                                          mgp->num_slices);
3806                 if (status == 0) {
3807                         pci_disable_msix(pdev);
3808                         if (old_allocated)
3809                                 kfree(old_fw);
3810                         return;
3811                 }
3812                 if (status > 0)
3813                         mgp->num_slices = status;
3814                 else
3815                         goto disable_msix;
3816         }
3817
3818 disable_msix:
3819         if (mgp->msix_vectors != NULL) {
3820                 kfree(mgp->msix_vectors);
3821                 mgp->msix_vectors = NULL;
3822         }
3823
3824 abort_with_fw:
3825         mgp->num_slices = 1;
3826         set_fw_name(mgp, old_fw, old_allocated);
3827         myri10ge_load_firmware(mgp, 0);
3828 }
3829
3830 static const struct net_device_ops myri10ge_netdev_ops = {
3831         .ndo_open               = myri10ge_open,
3832         .ndo_stop               = myri10ge_close,
3833         .ndo_start_xmit         = myri10ge_xmit,
3834         .ndo_get_stats          = myri10ge_get_stats,
3835         .ndo_validate_addr      = eth_validate_addr,
3836         .ndo_change_mtu         = myri10ge_change_mtu,
3837         .ndo_set_multicast_list = myri10ge_set_multicast_list,
3838         .ndo_set_mac_address    = myri10ge_set_mac_address,
3839 };
3840
3841 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3842 {
3843         struct net_device *netdev;
3844         struct myri10ge_priv *mgp;
3845         struct device *dev = &pdev->dev;
3846         int i;
3847         int status = -ENXIO;
3848         int dac_enabled;
3849         unsigned hdr_offset, ss_offset;
3850         static int board_number;
3851
3852         netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3853         if (netdev == NULL) {
3854                 dev_err(dev, "Could not allocate ethernet device\n");
3855                 return -ENOMEM;
3856         }
3857
3858         SET_NETDEV_DEV(netdev, &pdev->dev);
3859
3860         mgp = netdev_priv(netdev);
3861         mgp->dev = netdev;
3862         mgp->pdev = pdev;
3863         mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3864         mgp->pause = myri10ge_flow_control;
3865         mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3866         mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3867         mgp->board_number = board_number;
3868         init_waitqueue_head(&mgp->down_wq);
3869
3870         if (pci_enable_device(pdev)) {
3871                 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3872                 status = -ENODEV;
3873                 goto abort_with_netdev;
3874         }
3875
3876         /* Find the vendor-specific cap so we can check
3877          * the reboot register later on */
3878         mgp->vendor_specific_offset
3879             = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3880
3881         /* Set our max read request to 4KB */
3882         status = pcie_set_readrq(pdev, 4096);
3883         if (status != 0) {
3884                 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3885                         status);
3886                 goto abort_with_enabled;
3887         }
3888
3889         pci_set_master(pdev);
3890         dac_enabled = 1;
3891         status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3892         if (status != 0) {
3893                 dac_enabled = 0;
3894                 dev_err(&pdev->dev,
3895                         "64-bit pci address mask was refused, "
3896                         "trying 32-bit\n");
3897                 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3898         }
3899         if (status != 0) {
3900                 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3901                 goto abort_with_enabled;
3902         }
3903         (void)pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3904         mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3905                                       &mgp->cmd_bus, GFP_KERNEL);
3906         if (mgp->cmd == NULL)
3907                 goto abort_with_enabled;
3908
3909         mgp->board_span = pci_resource_len(pdev, 0);
3910         mgp->iomem_base = pci_resource_start(pdev, 0);
3911         mgp->mtrr = -1;
3912         mgp->wc_enabled = 0;
3913 #ifdef CONFIG_MTRR
3914         mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3915                              MTRR_TYPE_WRCOMB, 1);
3916         if (mgp->mtrr >= 0)
3917                 mgp->wc_enabled = 1;
3918 #endif
3919         mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3920         if (mgp->sram == NULL) {
3921                 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3922                         mgp->board_span, mgp->iomem_base);
3923                 status = -ENXIO;
3924                 goto abort_with_mtrr;
3925         }
3926         hdr_offset =
3927             ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3928         ss_offset = hdr_offset + offsetof(struct mcp_gen_header, string_specs);
3929         mgp->sram_size = ntohl(__raw_readl(mgp->sram + ss_offset));
3930         if (mgp->sram_size > mgp->board_span ||
3931             mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3932                 dev_err(&pdev->dev,
3933                         "invalid sram_size %dB or board span %ldB\n",
3934                         mgp->sram_size, mgp->board_span);
3935                 goto abort_with_ioremap;
3936         }
3937         memcpy_fromio(mgp->eeprom_strings,
3938                       mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3939         memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3940         status = myri10ge_read_mac_addr(mgp);
3941         if (status)
3942                 goto abort_with_ioremap;
3943
3944         for (i = 0; i < ETH_ALEN; i++)
3945                 netdev->dev_addr[i] = mgp->mac_addr[i];
3946
3947         myri10ge_select_firmware(mgp);
3948
3949         status = myri10ge_load_firmware(mgp, 1);
3950         if (status != 0) {
3951                 dev_err(&pdev->dev, "failed to load firmware\n");
3952                 goto abort_with_ioremap;
3953         }
3954         myri10ge_probe_slices(mgp);
3955         status = myri10ge_alloc_slices(mgp);
3956         if (status != 0) {
3957                 dev_err(&pdev->dev, "failed to alloc slice state\n");
3958                 goto abort_with_firmware;
3959         }
3960         netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3961         netif_set_real_num_rx_queues(netdev, mgp->num_slices);
3962         status = myri10ge_reset(mgp);
3963         if (status != 0) {
3964                 dev_err(&pdev->dev, "failed reset\n");
3965                 goto abort_with_slices;
3966         }
3967 #ifdef CONFIG_MYRI10GE_DCA
3968         myri10ge_setup_dca(mgp);
3969 #endif
3970         pci_set_drvdata(pdev, mgp);
3971         if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3972                 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3973         if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3974                 myri10ge_initial_mtu = 68;
3975
3976         netdev->netdev_ops = &myri10ge_netdev_ops;
3977         netdev->mtu = myri10ge_initial_mtu;
3978         netdev->base_addr = mgp->iomem_base;
3979         netdev->features = mgp->features;
3980
3981         if (dac_enabled)
3982                 netdev->features |= NETIF_F_HIGHDMA;
3983         netdev->features |= NETIF_F_LRO;
3984
3985         netdev->vlan_features |= mgp->features;
3986         if (mgp->fw_ver_tiny < 37)
3987                 netdev->vlan_features &= ~NETIF_F_TSO6;
3988         if (mgp->fw_ver_tiny < 32)
3989                 netdev->vlan_features &= ~NETIF_F_TSO;
3990
3991         /* make sure we can get an irq, and that MSI can be
3992          * setup (if available).  Also ensure netdev->irq
3993          * is set to correct value if MSI is enabled */
3994         status = myri10ge_request_irq(mgp);
3995         if (status != 0)
3996                 goto abort_with_firmware;
3997         netdev->irq = pdev->irq;
3998         myri10ge_free_irq(mgp);
3999
4000         /* Save configuration space to be restored if the
4001          * nic resets due to a parity error */
4002         pci_save_state(pdev);
4003
4004         /* Setup the watchdog timer */
4005         setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
4006                     (unsigned long)mgp);
4007
4008         spin_lock_init(&mgp->stats_lock);
4009         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
4010         INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
4011         status = register_netdev(netdev);
4012         if (status != 0) {
4013                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
4014                 goto abort_with_state;
4015         }
4016         if (mgp->msix_enabled)
4017                 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
4018                          mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
4019                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
4020         else
4021                 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
4022                          mgp->msi_enabled ? "MSI" : "xPIC",
4023                          netdev->irq, mgp->tx_boundary, mgp->fw_name,
4024                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
4025
4026         board_number++;
4027         return 0;
4028
4029 abort_with_state:
4030         pci_restore_state(pdev);
4031
4032 abort_with_slices:
4033         myri10ge_free_slices(mgp);
4034
4035 abort_with_firmware:
4036         myri10ge_dummy_rdma(mgp, 0);
4037
4038 abort_with_ioremap:
4039         if (mgp->mac_addr_string != NULL)
4040                 dev_err(&pdev->dev,
4041                         "myri10ge_probe() failed: MAC=%s, SN=%ld\n",
4042                         mgp->mac_addr_string, mgp->serial_number);
4043         iounmap(mgp->sram);
4044
4045 abort_with_mtrr:
4046 #ifdef CONFIG_MTRR
4047         if (mgp->mtrr >= 0)
4048                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4049 #endif
4050         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4051                           mgp->cmd, mgp->cmd_bus);
4052
4053 abort_with_enabled:
4054         pci_disable_device(pdev);
4055
4056 abort_with_netdev:
4057         set_fw_name(mgp, NULL, false);
4058         free_netdev(netdev);
4059         return status;
4060 }
4061
4062 /*
4063  * myri10ge_remove
4064  *
4065  * Does what is necessary to shutdown one Myrinet device. Called
4066  *   once for each Myrinet card by the kernel when a module is
4067  *   unloaded.
4068  */
4069 static void myri10ge_remove(struct pci_dev *pdev)
4070 {
4071         struct myri10ge_priv *mgp;
4072         struct net_device *netdev;
4073
4074         mgp = pci_get_drvdata(pdev);
4075         if (mgp == NULL)
4076                 return;
4077
4078         cancel_work_sync(&mgp->watchdog_work);
4079         netdev = mgp->dev;
4080         unregister_netdev(netdev);
4081
4082 #ifdef CONFIG_MYRI10GE_DCA
4083         myri10ge_teardown_dca(mgp);
4084 #endif
4085         myri10ge_dummy_rdma(mgp, 0);
4086
4087         /* avoid a memory leak */
4088         pci_restore_state(pdev);
4089
4090         iounmap(mgp->sram);
4091
4092 #ifdef CONFIG_MTRR
4093         if (mgp->mtrr >= 0)
4094                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
4095 #endif
4096         myri10ge_free_slices(mgp);
4097         if (mgp->msix_vectors != NULL)
4098                 kfree(mgp->msix_vectors);
4099         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
4100                           mgp->cmd, mgp->cmd_bus);
4101
4102         set_fw_name(mgp, NULL, false);
4103         free_netdev(netdev);
4104         pci_disable_device(pdev);
4105         pci_set_drvdata(pdev, NULL);
4106 }
4107
4108 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E      0x0008
4109 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9    0x0009
4110
4111 static DEFINE_PCI_DEVICE_TABLE(myri10ge_pci_tbl) = {
4112         {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
4113         {PCI_DEVICE
4114          (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
4115         {0},
4116 };
4117
4118 MODULE_DEVICE_TABLE(pci, myri10ge_pci_tbl);
4119
4120 static struct pci_driver myri10ge_driver = {
4121         .name = "myri10ge",
4122         .probe = myri10ge_probe,
4123         .remove = myri10ge_remove,
4124         .id_table = myri10ge_pci_tbl,
4125 #ifdef CONFIG_PM
4126         .suspend = myri10ge_suspend,
4127         .resume = myri10ge_resume,
4128 #endif
4129 };
4130
4131 #ifdef CONFIG_MYRI10GE_DCA
4132 static int
4133 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
4134 {
4135         int err = driver_for_each_device(&myri10ge_driver.driver,
4136                                          NULL, &event,
4137                                          myri10ge_notify_dca_device);
4138
4139         if (err)
4140                 return NOTIFY_BAD;
4141         return NOTIFY_DONE;
4142 }
4143
4144 static struct notifier_block myri10ge_dca_notifier = {
4145         .notifier_call = myri10ge_notify_dca,
4146         .next = NULL,
4147         .priority = 0,
4148 };
4149 #endif                          /* CONFIG_MYRI10GE_DCA */
4150
4151 static __init int myri10ge_init_module(void)
4152 {
4153         pr_info("Version %s\n", MYRI10GE_VERSION_STR);
4154
4155         if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_MAX) {
4156                 pr_err("Illegal rssh hash type %d, defaulting to source port\n",
4157                        myri10ge_rss_hash);
4158                 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
4159         }
4160 #ifdef CONFIG_MYRI10GE_DCA
4161         dca_register_notify(&myri10ge_dca_notifier);
4162 #endif
4163         if (myri10ge_max_slices > MYRI10GE_MAX_SLICES)
4164                 myri10ge_max_slices = MYRI10GE_MAX_SLICES;
4165
4166         return pci_register_driver(&myri10ge_driver);
4167 }
4168
4169 module_init(myri10ge_init_module);
4170
4171 static __exit void myri10ge_cleanup_module(void)
4172 {
4173 #ifdef CONFIG_MYRI10GE_DCA
4174         dca_unregister_notify(&myri10ge_dca_notifier);
4175 #endif
4176         pci_unregister_driver(&myri10ge_driver);
4177 }
4178
4179 module_exit(myri10ge_cleanup_module);