drivers/net/ixgbe/ixgbe_x540.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_X540_MAX_TX_QUEUES 128
  36 #define IXGBE_X540_MAX_RX_QUEUES 128
  37 #define IXGBE_X540_RAR_ENTRIES   128
  38 #define IXGBE_X540_MC_TBL_SIZE   128
  39 #define IXGBE_X540_VFT_TBL_SIZE  128
  40 #define IXGBE_X540_RX_PB_SIZE    384
  41
  42 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
  43 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
  44 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
  45 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
  46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
  47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
  48
  49 static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
  50 {
  51         return ixgbe_media_type_copper;
  52 }
  53
  54 static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
  55 {
  56         struct ixgbe_mac_info *mac = &hw->mac;
  57
  58         /* Call PHY identify routine to get the phy type */
  59         ixgbe_identify_phy_generic(hw);
  60
  61         mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
  62         mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
  63         mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
  64         mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
  65         mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
  66         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  *  ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
  73  *  @hw: pointer to hardware structure
  74  *  @speed: new link speed
  75  *  @autoneg: true if autonegotiation enabled
  76  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  77  **/
  78 static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
  79                                      ixgbe_link_speed speed, bool autoneg,
  80                                      bool autoneg_wait_to_complete)
  81 {
  82         return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
  83                                             autoneg_wait_to_complete);
  84 }
  85
  86 /**
  87  *  ixgbe_reset_hw_X540 - Perform hardware reset
  88  *  @hw: pointer to hardware structure
  89  *
  90  *  Resets the hardware by resetting the transmit and receive units, masks
  91  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
  92  *  reset.
  93  **/
  94 static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
  95 {
  96         ixgbe_link_speed link_speed;
  97         s32 status = 0;
  98         u32 ctrl;
  99         u32 ctrl_ext;
 100         u32 reset_bit;
 101         u32 i;
 102         u32 autoc;
 103         u32 autoc2;
 104         bool link_up = false;
 105
 106         /* Call adapter stop to disable tx/rx and clear interrupts */
 107         hw->mac.ops.stop_adapter(hw);
 108
 109         /*
 110          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 111          * access and verify no pending requests before reset
 112          */
 113         ixgbe_disable_pcie_master(hw);
 114
 115 mac_reset_top:
 116         /*
 117          * Issue global reset to the MAC.  Needs to be SW reset if link is up.
 118          * If link reset is used when link is up, it might reset the PHY when
 119          * mng is using it.  If link is down or the flag to force full link
 120          * reset is set, then perform link reset.
 121          */
 122         if (hw->force_full_reset) {
 123                 reset_bit = IXGBE_CTRL_LNK_RST;
 124         } else {
 125                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 126                 if (!link_up)
 127                         reset_bit = IXGBE_CTRL_LNK_RST;
 128                 else
 129                         reset_bit = IXGBE_CTRL_RST;
 130         }
 131
 132         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 133         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | reset_bit));
 134         IXGBE_WRITE_FLUSH(hw);
 135
 136         /* Poll for reset bit to self-clear indicating reset is complete */
 137         for (i = 0; i < 10; i++) {
 138                 udelay(1);
 139                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 140                 if (!(ctrl & reset_bit))
 141                         break;
 142         }
 143         if (ctrl & reset_bit) {
 144                 status = IXGBE_ERR_RESET_FAILED;
 145                 hw_dbg(hw, "Reset polling failed to complete.\n");
 146         }
 147
 148         /*
 149          * Double resets are required for recovery from certain error
 150          * conditions.  Between resets, it is necessary to stall to allow time
 151          * for any pending HW events to complete.  We use 1usec since that is
 152          * what is needed for ixgbe_disable_pcie_master().  The second reset
 153          * then clears out any effects of those events.
 154          */
 155         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 156                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 157                 udelay(1);
 158                 goto mac_reset_top;
 159         }
 160
 161         /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
 162         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 163         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 164         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 165
 166         msleep(50);
 167
 168         /* Set the Rx packet buffer size. */
 169         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
 170
 171         /* Store the permanent mac address */
 172         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 173
 174         /*
 175          * Store the original AUTOC/AUTOC2 values if they have not been
 176          * stored off yet.  Otherwise restore the stored original
 177          * values since the reset operation sets back to defaults.
 178          */
 179         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 180         autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 181         if (hw->mac.orig_link_settings_stored == false) {
 182                 hw->mac.orig_autoc = autoc;
 183                 hw->mac.orig_autoc2 = autoc2;
 184                 hw->mac.orig_link_settings_stored = true;
 185         } else {
 186                 if (autoc != hw->mac.orig_autoc)
 187                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
 188                                         IXGBE_AUTOC_AN_RESTART));
 189
 190                 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 191                     (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 192                         autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 193                         autoc2 |= (hw->mac.orig_autoc2 &
 194                                    IXGBE_AUTOC2_UPPER_MASK);
 195                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 196                 }
 197         }
 198
 199         /*
 200          * Store MAC address from RAR0, clear receive address registers, and
 201          * clear the multicast table.  Also reset num_rar_entries to 128,
 202          * since we modify this value when programming the SAN MAC address.
 203          */
 204         hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
 205         hw->mac.ops.init_rx_addrs(hw);
 206
 207         /* Store the permanent mac address */
 208         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 209
 210         /* Store the permanent SAN mac address */
 211         hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 212
 213         /* Add the SAN MAC address to the RAR only if it's a valid address */
 214         if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
 215                 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 216                                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
 217
 218                 /* Reserve the last RAR for the SAN MAC address */
 219                 hw->mac.num_rar_entries--;
 220         }
 221
 222         /* Store the alternative WWNN/WWPN prefix */
 223         hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 224                                    &hw->mac.wwpn_prefix);
 225
 226         return status;
 227 }
 228
 229 /**
 230  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
 231  *  @hw: pointer to hardware structure
 232  *
 233  *  Starts the hardware using the generic start_hw function
 234  *  and the generation start_hw function.
 235  *  Then performs revision-specific operations, if any.
 236  **/
 237 static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
 238 {
 239         s32 ret_val = 0;
 240
 241         ret_val = ixgbe_start_hw_generic(hw);
 242         if (ret_val != 0)
 243                 goto out;
 244
 245         ret_val = ixgbe_start_hw_gen2(hw);
 246         hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE;
 247 out:
 248         return ret_val;
 249 }
 250
 251 /**
 252  *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
 253  *  @hw: pointer to hardware structure
 254  *
 255  *  Determines physical layer capabilities of the current configuration.
 256  **/
 257 static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
 258 {
 259         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 260         u16 ext_ability = 0;
 261
 262         hw->phy.ops.identify(hw);
 263
 264         hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
 265                              &ext_ability);
 266         if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
 267                 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 268         if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
 269                 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 270         if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
 271                 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 272
 273         return physical_layer;
 274 }
 275
 276 /**
 277  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
 278  *  @hw: pointer to hardware structure
 279  *
 280  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 281  *  ixgbe_hw struct in order to set up EEPROM access.
 282  **/
 283 static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
 284 {
 285         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 286         u32 eec;
 287         u16 eeprom_size;
 288
 289         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 290                 eeprom->semaphore_delay = 10;
 291                 eeprom->type = ixgbe_flash;
 292
 293                 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 294                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 295                                     IXGBE_EEC_SIZE_SHIFT);
 296                 eeprom->word_size = 1 << (eeprom_size +
 297                                           IXGBE_EEPROM_WORD_SIZE_SHIFT);
 298
 299                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 300                        eeprom->type, eeprom->word_size);
 301         }
 302
 303         return 0;
 304 }
 305
 306 /**
 307  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
 308  *  @hw: pointer to hardware structure
 309  *  @offset: offset of  word in the EEPROM to read
 310  *  @data: word read from the EEPROM
 311  *
 312  *  Reads a 16 bit word from the EEPROM using the EERD register.
 313  **/
 314 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
 315 {
 316         s32 status = 0;
 317
 318         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 319             0)
 320                 status = ixgbe_read_eerd_generic(hw, offset, data);
 321         else
 322                 status = IXGBE_ERR_SWFW_SYNC;
 323
 324         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 325         return status;
 326 }
 327
 328 /**
 329  *  ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
 330  *  @hw: pointer to hardware structure
 331  *  @offset: offset of  word in the EEPROM to read
 332  *  @words: number of words
 333  *  @data: word(s) read from the EEPROM
 334  *
 335  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
 336  **/
 337 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
 338                                        u16 offset, u16 words, u16 *data)
 339 {
 340         s32 status = 0;
 341
 342         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 343             0)
 344                 status = ixgbe_read_eerd_buffer_generic(hw, offset,
 345                                                         words, data);
 346         else
 347                 status = IXGBE_ERR_SWFW_SYNC;
 348
 349         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 350         return status;
 351 }
 352
 353 /**
 354  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
 355  *  @hw: pointer to hardware structure
 356  *  @offset: offset of  word in the EEPROM to write
 357  *  @data: word write to the EEPROM
 358  *
 359  *  Write a 16 bit word to the EEPROM using the EEWR register.
 360  **/
 361 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
 362 {
 363         s32 status = 0;
 364
 365         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0)
 366                 status = ixgbe_write_eewr_generic(hw, offset, data);
 367         else
 368                 status = IXGBE_ERR_SWFW_SYNC;
 369
 370         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 371         return status;
 372 }
 373
 374 /**
 375  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
 376  *  @hw: pointer to hardware structure
 377  *  @offset: offset of  word in the EEPROM to write
 378  *  @words: number of words
 379  *  @data: word(s) write to the EEPROM
 380  *
 381  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
 382  **/
 383 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
 384                                         u16 offset, u16 words, u16 *data)
 385 {
 386         s32 status = 0;
 387
 388         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
 389             0)
 390                 status = ixgbe_write_eewr_buffer_generic(hw, offset,
 391                                                          words, data);
 392         else
 393                 status = IXGBE_ERR_SWFW_SYNC;
 394
 395         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 396         return status;
 397 }
 398
 399 /**
 400  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
 401  *
 402  *  This function does not use synchronization for EERD and EEWR. It can
 403  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
 404  *
 405  *  @hw: pointer to hardware structure
 406  **/
 407 static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
 408 {
 409         u16 i;
 410         u16 j;
 411         u16 checksum = 0;
 412         u16 length = 0;
 413         u16 pointer = 0;
 414         u16 word = 0;
 415
 416         /*
 417          * Do not use hw->eeprom.ops.read because we do not want to take
 418          * the synchronization semaphores here. Instead use
 419          * ixgbe_read_eerd_generic
 420          */
 421
 422         /* Include 0x0-0x3F in the checksum */
 423         for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 424                 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
 425                         hw_dbg(hw, "EEPROM read failed\n");
 426                         break;
 427                 }
 428                 checksum += word;
 429         }
 430
 431         /*
 432          * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 433          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 434          */
 435         for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 436                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 437                         continue;
 438
 439                 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
 440                         hw_dbg(hw, "EEPROM read failed\n");
 441                         break;
 442                 }
 443
 444                 /* Skip pointer section if the pointer is invalid. */
 445                 if (pointer == 0xFFFF || pointer == 0 ||
 446                     pointer >= hw->eeprom.word_size)
 447                         continue;
 448
 449                 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) {
 450                         hw_dbg(hw, "EEPROM read failed\n");
 451                         break;
 452                 }
 453
 454                 /* Skip pointer section if length is invalid. */
 455                 if (length == 0xFFFF || length == 0 ||
 456                     (pointer + length) >= hw->eeprom.word_size)
 457                         continue;
 458
 459                 for (j = pointer+1; j <= pointer+length; j++) {
 460                         if (ixgbe_read_eerd_generic(hw, j, &word) != 0) {
 461                                 hw_dbg(hw, "EEPROM read failed\n");
 462                                 break;
 463                         }
 464                         checksum += word;
 465                 }
 466         }
 467
 468         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 469
 470         return checksum;
 471 }
 472
 473 /**
 474  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
 475  *  @hw: pointer to hardware structure
 476  *  @checksum_val: calculated checksum
 477  *
 478  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 479  *  caller does not need checksum_val, the value can be NULL.
 480  **/
 481 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
 482                                                u16 *checksum_val)
 483 {
 484         s32 status;
 485         u16 checksum;
 486         u16 read_checksum = 0;
 487
 488         /*
 489          * Read the first word from the EEPROM. If this times out or fails, do
 490          * not continue or we could be in for a very long wait while every
 491          * EEPROM read fails
 492          */
 493         status = hw->eeprom.ops.read(hw, 0, &checksum);
 494
 495         if (status != 0) {
 496                 hw_dbg(hw, "EEPROM read failed\n");
 497                 goto out;
 498         }
 499
 500         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 501                 checksum = hw->eeprom.ops.calc_checksum(hw);
 502
 503                 /*
 504                  * Do not use hw->eeprom.ops.read because we do not want to take
 505                  * the synchronization semaphores twice here.
 506                  */
 507                 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
 508                                         &read_checksum);
 509
 510                 /*
 511                  * Verify read checksum from EEPROM is the same as
 512                  * calculated checksum
 513                  */
 514                 if (read_checksum != checksum)
 515                         status = IXGBE_ERR_EEPROM_CHECKSUM;
 516
 517                 /* If the user cares, return the calculated checksum */
 518                 if (checksum_val)
 519                         *checksum_val = checksum;
 520         } else {
 521                 status = IXGBE_ERR_SWFW_SYNC;
 522         }
 523
 524         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 525 out:
 526         return status;
 527 }
 528
 529 /**
 530  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
 531  * @hw: pointer to hardware structure
 532  *
 533  * After writing EEPROM to shadow RAM using EEWR register, software calculates
 534  * checksum and updates the EEPROM and instructs the hardware to update
 535  * the flash.
 536  **/
 537 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
 538 {
 539         s32 status;
 540         u16 checksum;
 541
 542         /*
 543          * Read the first word from the EEPROM. If this times out or fails, do
 544          * not continue or we could be in for a very long wait while every
 545          * EEPROM read fails
 546          */
 547         status = hw->eeprom.ops.read(hw, 0, &checksum);
 548
 549         if (status != 0)
 550                 hw_dbg(hw, "EEPROM read failed\n");
 551
 552         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 553                 checksum = hw->eeprom.ops.calc_checksum(hw);
 554
 555                 /*
 556                  * Do not use hw->eeprom.ops.write because we do not want to
 557                  * take the synchronization semaphores twice here.
 558                  */
 559                 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
 560                                                   checksum);
 561
 562         if (status == 0)
 563                 status = ixgbe_update_flash_X540(hw);
 564         else
 565                 status = IXGBE_ERR_SWFW_SYNC;
 566         }
 567
 568         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 569
 570         return status;
 571 }
 572
 573 /**
 574  * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
 575  * @hw: pointer to hardware structure
 576  *
 577  * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
 578  * EEPROM from shadow RAM to the flash device.
 579  **/
 580 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
 581 {
 582         u32 flup;
 583         s32 status = IXGBE_ERR_EEPROM;
 584
 585         status = ixgbe_poll_flash_update_done_X540(hw);
 586         if (status == IXGBE_ERR_EEPROM) {
 587                 hw_dbg(hw, "Flash update time out\n");
 588                 goto out;
 589         }
 590
 591         flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
 592         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 593
 594         status = ixgbe_poll_flash_update_done_X540(hw);
 595         if (status == 0)
 596                 hw_dbg(hw, "Flash update complete\n");
 597         else
 598                 hw_dbg(hw, "Flash update time out\n");
 599
 600         if (hw->revision_id == 0) {
 601                 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
 602
 603                 if (flup & IXGBE_EEC_SEC1VAL) {
 604                         flup |= IXGBE_EEC_FLUP;
 605                         IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
 606                 }
 607
 608                 status = ixgbe_poll_flash_update_done_X540(hw);
 609                 if (status == 0)
 610                         hw_dbg(hw, "Flash update complete\n");
 611                 else
 612                         hw_dbg(hw, "Flash update time out\n");
 613         }
 614 out:
 615         return status;
 616 }
 617
 618 /**
 619  * ixgbe_poll_flash_update_done_X540 - Poll flash update status
 620  * @hw: pointer to hardware structure
 621  *
 622  * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
 623  * flash update is done.
 624  **/
 625 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
 626 {
 627         u32 i;
 628         u32 reg;
 629         s32 status = IXGBE_ERR_EEPROM;
 630
 631         for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
 632                 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
 633                 if (reg & IXGBE_EEC_FLUDONE) {
 634                         status = 0;
 635                         break;
 636                 }
 637                 udelay(5);
 638         }
 639         return status;
 640 }
 641
 642 /**
 643  * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
 644  * @hw: pointer to hardware structure
 645  * @mask: Mask to specify which semaphore to acquire
 646  *
 647  * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
 648  * the specified function (CSR, PHY0, PHY1, NVM, Flash)
 649  **/
 650 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 651 {
 652         u32 swfw_sync;
 653         u32 swmask = mask;
 654         u32 fwmask = mask << 5;
 655         u32 hwmask = 0;
 656         u32 timeout = 200;
 657         u32 i;
 658
 659         if (swmask == IXGBE_GSSR_EEP_SM)
 660                 hwmask = IXGBE_GSSR_FLASH_SM;
 661
 662         for (i = 0; i < timeout; i++) {
 663                 /*
 664                  * SW NVM semaphore bit is used for access to all
 665                  * SW_FW_SYNC bits (not just NVM)
 666                  */
 667                 if (ixgbe_get_swfw_sync_semaphore(hw))
 668                         return IXGBE_ERR_SWFW_SYNC;
 669
 670                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 671                 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
 672                         swfw_sync |= swmask;
 673                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 674                         ixgbe_release_swfw_sync_semaphore(hw);
 675                         break;
 676                 } else {
 677                         /*
 678                          * Firmware currently using resource (fwmask),
 679                          * hardware currently using resource (hwmask),
 680                          * or other software thread currently using
 681                          * resource (swmask)
 682                          */
 683                         ixgbe_release_swfw_sync_semaphore(hw);
 684                         usleep_range(5000, 10000);
 685                 }
 686         }
 687
 688         /*
 689          * If the resource is not released by the FW/HW the SW can assume that
 690          * the FW/HW malfunctions. In that case the SW should sets the
 691          * SW bit(s) of the requested resource(s) while ignoring the
 692          * corresponding FW/HW bits in the SW_FW_SYNC register.
 693          */
 694         if (i >= timeout) {
 695                 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 696                 if (swfw_sync & (fwmask | hwmask)) {
 697                         if (ixgbe_get_swfw_sync_semaphore(hw))
 698                                 return IXGBE_ERR_SWFW_SYNC;
 699
 700                         swfw_sync |= swmask;
 701                         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 702                         ixgbe_release_swfw_sync_semaphore(hw);
 703                 }
 704         }
 705
 706         usleep_range(5000, 10000);
 707         return 0;
 708 }
 709
 710 /**
 711  * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
 712  * @hw: pointer to hardware structure
 713  * @mask: Mask to specify which semaphore to release
 714  *
 715  * Releases the SWFW semaphore through the SW_FW_SYNC register
 716  * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
 717  **/
 718 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
 719 {
 720         u32 swfw_sync;
 721         u32 swmask = mask;
 722
 723         ixgbe_get_swfw_sync_semaphore(hw);
 724
 725         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 726         swfw_sync &= ~swmask;
 727         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
 728
 729         ixgbe_release_swfw_sync_semaphore(hw);
 730         usleep_range(5000, 10000);
 731 }
 732
 733 /**
 734  * ixgbe_get_nvm_semaphore - Get hardware semaphore
 735  * @hw: pointer to hardware structure
 736  *
 737  * Sets the hardware semaphores so SW/FW can gain control of shared resources
 738  **/
 739 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
 740 {
 741         s32 status = IXGBE_ERR_EEPROM;
 742         u32 timeout = 2000;
 743         u32 i;
 744         u32 swsm;
 745
 746         /* Get SMBI software semaphore between device drivers first */
 747         for (i = 0; i < timeout; i++) {
 748                 /*
 749                  * If the SMBI bit is 0 when we read it, then the bit will be
 750                  * set and we have the semaphore
 751                  */
 752                 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 753                 if (!(swsm & IXGBE_SWSM_SMBI)) {
 754                         status = 0;
 755                         break;
 756                 }
 757                 udelay(50);
 758         }
 759
 760         /* Now get the semaphore between SW/FW through the REGSMP bit */
 761         if (status) {
 762                 for (i = 0; i < timeout; i++) {
 763                         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 764                         if (!(swsm & IXGBE_SWFW_REGSMP))
 765                                 break;
 766
 767                         udelay(50);
 768                 }
 769         } else {
 770                 hw_dbg(hw, "Software semaphore SMBI between device drivers "
 771                            "not granted.\n");
 772         }
 773
 774         return status;
 775 }
 776
 777 /**
 778  * ixgbe_release_nvm_semaphore - Release hardware semaphore
 779  * @hw: pointer to hardware structure
 780  *
 781  * This function clears hardware semaphore bits.
 782  **/
 783 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
 784 {
 785          u32 swsm;
 786
 787         /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
 788
 789         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 790         swsm &= ~IXGBE_SWSM_SMBI;
 791         IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 792
 793         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
 794         swsm &= ~IXGBE_SWFW_REGSMP;
 795         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
 796
 797         IXGBE_WRITE_FLUSH(hw);
 798 }
 799
 800 /**
 801  * ixgbe_blink_led_start_X540 - Blink LED based on index.
 802  * @hw: pointer to hardware structure
 803  * @index: led number to blink
 804  *
 805  * Devices that implement the version 2 interface:
 806  *   X540
 807  **/
 808 static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
 809 {
 810         u32 macc_reg;
 811         u32 ledctl_reg;
 812
 813         /*
 814          * In order for the blink bit in the LED control register
 815          * to work, link and speed must be forced in the MAC. We
 816          * will reverse this when we stop the blinking.
 817          */
 818         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 819         macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
 820         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 821
 822         /* Set the LED to LINK_UP + BLINK. */
 823         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 824         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 825         ledctl_reg |= IXGBE_LED_BLINK(index);
 826         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 827         IXGBE_WRITE_FLUSH(hw);
 828
 829         return 0;
 830 }
 831
 832 /**
 833  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
 834  * @hw: pointer to hardware structure
 835  * @index: led number to stop blinking
 836  *
 837  * Devices that implement the version 2 interface:
 838  *   X540
 839  **/
 840 static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
 841 {
 842         u32 macc_reg;
 843         u32 ledctl_reg;
 844
 845         /* Restore the LED to its default value. */
 846         ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 847         ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
 848         ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 849         ledctl_reg &= ~IXGBE_LED_BLINK(index);
 850         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
 851
 852         /* Unforce link and speed in the MAC. */
 853         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
 854         macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
 855         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
 856         IXGBE_WRITE_FLUSH(hw);
 857
 858         return 0;
 859 }
 860 static struct ixgbe_mac_operations mac_ops_X540 = {
 861         .init_hw                = &ixgbe_init_hw_generic,
 862         .reset_hw               = &ixgbe_reset_hw_X540,
 863         .start_hw               = &ixgbe_start_hw_X540,
 864         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
 865         .get_media_type         = &ixgbe_get_media_type_X540,
 866         .get_supported_physical_layer =
 867                                   &ixgbe_get_supported_physical_layer_X540,
 868         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
 869         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
 870         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
 871         .get_device_caps        = &ixgbe_get_device_caps_generic,
 872         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
 873         .stop_adapter           = &ixgbe_stop_adapter_generic,
 874         .get_bus_info           = &ixgbe_get_bus_info_generic,
 875         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
 876         .read_analog_reg8       = NULL,
 877         .write_analog_reg8      = NULL,
 878         .setup_link             = &ixgbe_setup_mac_link_X540,
 879         .set_rxpba              = &ixgbe_set_rxpba_generic,
 880         .check_link             = &ixgbe_check_mac_link_generic,
 881         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
 882         .led_on                 = &ixgbe_led_on_generic,
 883         .led_off                = &ixgbe_led_off_generic,
 884         .blink_led_start        = &ixgbe_blink_led_start_X540,
 885         .blink_led_stop         = &ixgbe_blink_led_stop_X540,
 886         .set_rar                = &ixgbe_set_rar_generic,
 887         .clear_rar              = &ixgbe_clear_rar_generic,
 888         .set_vmdq               = &ixgbe_set_vmdq_generic,
 889         .clear_vmdq             = &ixgbe_clear_vmdq_generic,
 890         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
 891         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
 892         .enable_mc              = &ixgbe_enable_mc_generic,
 893         .disable_mc             = &ixgbe_disable_mc_generic,
 894         .clear_vfta             = &ixgbe_clear_vfta_generic,
 895         .set_vfta               = &ixgbe_set_vfta_generic,
 896         .fc_enable              = &ixgbe_fc_enable_generic,
 897         .set_fw_drv_ver         = &ixgbe_set_fw_drv_ver_generic,
 898         .init_uta_tables        = &ixgbe_init_uta_tables_generic,
 899         .setup_sfp              = NULL,
 900         .set_mac_anti_spoofing  = &ixgbe_set_mac_anti_spoofing,
 901         .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
 902         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
 903         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
 904 };
 905
 906 static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
 907         .init_params            = &ixgbe_init_eeprom_params_X540,
 908         .read                   = &ixgbe_read_eerd_X540,
 909         .read_buffer            = &ixgbe_read_eerd_buffer_X540,
 910         .write                  = &ixgbe_write_eewr_X540,
 911         .write_buffer           = &ixgbe_write_eewr_buffer_X540,
 912         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X540,
 913         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X540,
 914         .update_checksum        = &ixgbe_update_eeprom_checksum_X540,
 915 };
 916
 917 static struct ixgbe_phy_operations phy_ops_X540 = {
 918         .identify               = &ixgbe_identify_phy_generic,
 919         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
 920         .init                   = NULL,
 921         .reset                  = NULL,
 922         .read_reg               = &ixgbe_read_phy_reg_generic,
 923         .write_reg              = &ixgbe_write_phy_reg_generic,
 924         .setup_link             = &ixgbe_setup_phy_link_generic,
 925         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
 926         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
 927         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
 928         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
 929         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
 930         .check_overtemp         = &ixgbe_tn_check_overtemp,
 931 };
 932
 933 struct ixgbe_info ixgbe_X540_info = {
 934         .mac                    = ixgbe_mac_X540,
 935         .get_invariants         = &ixgbe_get_invariants_X540,
 936         .mac_ops                = &mac_ops_X540,
 937         .eeprom_ops             = &eeprom_ops_X540,
 938         .phy_ops                = &phy_ops_X540,
 939         .mbx_ops                = &mbx_ops_generic,
 940 };