drivers/net/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe_common.h"
  33 #include "ixgbe_phy.h"
  34
  35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  49
  50 /**
  51  *  ixgbe_identify_phy_generic - Get physical layer module
  52  *  @hw: pointer to hardware structure
  53  *
  54  *  Determines the physical layer module found on the current adapter.
  55  **/
  56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  57 {
  58         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  59         u32 phy_addr;
  60         u16 ext_ability = 0;
  61
  62         if (hw->phy.type == ixgbe_phy_unknown) {
  63                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  64                         hw->phy.mdio.prtad = phy_addr;
  65                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  66                                 ixgbe_get_phy_id(hw);
  67                                 hw->phy.type =
  68                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  69
  70                                 if (hw->phy.type == ixgbe_phy_unknown) {
  71                                         hw->phy.ops.read_reg(hw,
  72                                                              MDIO_PMA_EXTABLE,
  73                                                              MDIO_MMD_PMAPMD,
  74                                                              &ext_ability);
  75                                         if (ext_ability &
  76                                             (MDIO_PMA_EXTABLE_10GBT |
  77                                              MDIO_PMA_EXTABLE_1000BT))
  78                                                 hw->phy.type =
  79                                                          ixgbe_phy_cu_unknown;
  80                                         else
  81                                                 hw->phy.type =
  82                                                          ixgbe_phy_generic;
  83                                 }
  84
  85                                 status = 0;
  86                                 break;
  87                         }
  88                 }
  89                 /* clear value if nothing found */
  90                 if (status != 0)
  91                         hw->phy.mdio.prtad = 0;
  92         } else {
  93                 status = 0;
  94         }
  95
  96         return status;
  97 }
  98
  99 /**
 100  *  ixgbe_get_phy_id - Get the phy type
 101  *  @hw: pointer to hardware structure
 102  *
 103  **/
 104 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 105 {
 106         u32 status;
 107         u16 phy_id_high = 0;
 108         u16 phy_id_low = 0;
 109
 110         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 111                                       &phy_id_high);
 112
 113         if (status == 0) {
 114                 hw->phy.id = (u32)(phy_id_high << 16);
 115                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 116                                               &phy_id_low);
 117                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 118                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 119         }
 120         return status;
 121 }
 122
 123 /**
 124  *  ixgbe_get_phy_type_from_id - Get the phy type
 125  *  @hw: pointer to hardware structure
 126  *
 127  **/
 128 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 129 {
 130         enum ixgbe_phy_type phy_type;
 131
 132         switch (phy_id) {
 133         case TN1010_PHY_ID:
 134                 phy_type = ixgbe_phy_tn;
 135                 break;
 136         case X540_PHY_ID:
 137                 phy_type = ixgbe_phy_aq;
 138                 break;
 139         case QT2022_PHY_ID:
 140                 phy_type = ixgbe_phy_qt;
 141                 break;
 142         case ATH_PHY_ID:
 143                 phy_type = ixgbe_phy_nl;
 144                 break;
 145         default:
 146                 phy_type = ixgbe_phy_unknown;
 147                 break;
 148         }
 149
 150         return phy_type;
 151 }
 152
 153 /**
 154  *  ixgbe_reset_phy_generic - Performs a PHY reset
 155  *  @hw: pointer to hardware structure
 156  **/
 157 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 158 {
 159         u32 i;
 160         u16 ctrl = 0;
 161         s32 status = 0;
 162
 163         if (hw->phy.type == ixgbe_phy_unknown)
 164                 status = ixgbe_identify_phy_generic(hw);
 165
 166         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 167                 goto out;
 168
 169         /* Don't reset PHY if it's shut down due to overtemp. */
 170         if (!hw->phy.reset_if_overtemp &&
 171             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 172                 goto out;
 173
 174         /*
 175          * Perform soft PHY reset to the PHY_XS.
 176          * This will cause a soft reset to the PHY
 177          */
 178         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 179                               MDIO_MMD_PHYXS,
 180                               MDIO_CTRL1_RESET);
 181
 182         /*
 183          * Poll for reset bit to self-clear indicating reset is complete.
 184          * Some PHYs could take up to 3 seconds to complete and need about
 185          * 1.7 usec delay after the reset is complete.
 186          */
 187         for (i = 0; i < 30; i++) {
 188                 msleep(100);
 189                 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 190                                      MDIO_MMD_PHYXS, &ctrl);
 191                 if (!(ctrl & MDIO_CTRL1_RESET)) {
 192                         udelay(2);
 193                         break;
 194                 }
 195         }
 196
 197         if (ctrl & MDIO_CTRL1_RESET) {
 198                 status = IXGBE_ERR_RESET_FAILED;
 199                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 200         }
 201
 202 out:
 203         return status;
 204 }
 205
 206 /**
 207  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 208  *  @hw: pointer to hardware structure
 209  *  @reg_addr: 32 bit address of PHY register to read
 210  *  @phy_data: Pointer to read data from PHY register
 211  **/
 212 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 213                                u32 device_type, u16 *phy_data)
 214 {
 215         u32 command;
 216         u32 i;
 217         u32 data;
 218         s32 status = 0;
 219         u16 gssr;
 220
 221         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 222                 gssr = IXGBE_GSSR_PHY1_SM;
 223         else
 224                 gssr = IXGBE_GSSR_PHY0_SM;
 225
 226         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
 227                 status = IXGBE_ERR_SWFW_SYNC;
 228
 229         if (status == 0) {
 230                 /* Setup and write the address cycle command */
 231                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 232                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 233                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 234                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 235
 236                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 237
 238                 /*
 239                  * Check every 10 usec to see if the address cycle completed.
 240                  * The MDI Command bit will clear when the operation is
 241                  * complete
 242                  */
 243                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 244                         udelay(10);
 245
 246                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 247
 248                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 249                                 break;
 250                 }
 251
 252                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 253                         hw_dbg(hw, "PHY address command did not complete.\n");
 254                         status = IXGBE_ERR_PHY;
 255                 }
 256
 257                 if (status == 0) {
 258                         /*
 259                          * Address cycle complete, setup and write the read
 260                          * command
 261                          */
 262                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 263                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 264                                    (hw->phy.mdio.prtad <<
 265                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 266                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 267
 268                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 269
 270                         /*
 271                          * Check every 10 usec to see if the address cycle
 272                          * completed. The MDI Command bit will clear when the
 273                          * operation is complete
 274                          */
 275                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 276                                 udelay(10);
 277
 278                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 279
 280                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 281                                         break;
 282                         }
 283
 284                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 285                                 hw_dbg(hw, "PHY read command didn't complete\n");
 286                                 status = IXGBE_ERR_PHY;
 287                         } else {
 288                                 /*
 289                                  * Read operation is complete.  Get the data
 290                                  * from MSRWD
 291                                  */
 292                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 293                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 294                                 *phy_data = (u16)(data);
 295                         }
 296                 }
 297
 298                 hw->mac.ops.release_swfw_sync(hw, gssr);
 299         }
 300
 301         return status;
 302 }
 303
 304 /**
 305  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 306  *  @hw: pointer to hardware structure
 307  *  @reg_addr: 32 bit PHY register to write
 308  *  @device_type: 5 bit device type
 309  *  @phy_data: Data to write to the PHY register
 310  **/
 311 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 312                                 u32 device_type, u16 phy_data)
 313 {
 314         u32 command;
 315         u32 i;
 316         s32 status = 0;
 317         u16 gssr;
 318
 319         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 320                 gssr = IXGBE_GSSR_PHY1_SM;
 321         else
 322                 gssr = IXGBE_GSSR_PHY0_SM;
 323
 324         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
 325                 status = IXGBE_ERR_SWFW_SYNC;
 326
 327         if (status == 0) {
 328                 /* Put the data in the MDI single read and write data register*/
 329                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 330
 331                 /* Setup and write the address cycle command */
 332                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 333                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 334                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 335                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 336
 337                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 338
 339                 /*
 340                  * Check every 10 usec to see if the address cycle completed.
 341                  * The MDI Command bit will clear when the operation is
 342                  * complete
 343                  */
 344                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 345                         udelay(10);
 346
 347                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 348
 349                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 350                                 break;
 351                 }
 352
 353                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 354                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 355                         status = IXGBE_ERR_PHY;
 356                 }
 357
 358                 if (status == 0) {
 359                         /*
 360                          * Address cycle complete, setup and write the write
 361                          * command
 362                          */
 363                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 364                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 365                                    (hw->phy.mdio.prtad <<
 366                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 367                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 368
 369                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 370
 371                         /*
 372                          * Check every 10 usec to see if the address cycle
 373                          * completed. The MDI Command bit will clear when the
 374                          * operation is complete
 375                          */
 376                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 377                                 udelay(10);
 378
 379                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 380
 381                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 382                                         break;
 383                         }
 384
 385                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 386                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 387                                 status = IXGBE_ERR_PHY;
 388                         }
 389                 }
 390
 391                 hw->mac.ops.release_swfw_sync(hw, gssr);
 392         }
 393
 394         return status;
 395 }
 396
 397 /**
 398  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 399  *  @hw: pointer to hardware structure
 400  *
 401  *  Restart autonegotiation and PHY and waits for completion.
 402  **/
 403 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 404 {
 405         s32 status = 0;
 406         u32 time_out;
 407         u32 max_time_out = 10;
 408         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 409         bool autoneg = false;
 410         ixgbe_link_speed speed;
 411
 412         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 413
 414         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 415                 /* Set or unset auto-negotiation 10G advertisement */
 416                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 417                                      MDIO_MMD_AN,
 418                                      &autoneg_reg);
 419
 420                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 421                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 422                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 423
 424                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 425                                       MDIO_MMD_AN,
 426                                       autoneg_reg);
 427         }
 428
 429         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 430                 /* Set or unset auto-negotiation 1G advertisement */
 431                 hw->phy.ops.read_reg(hw,
 432                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 433                                      MDIO_MMD_AN,
 434                                      &autoneg_reg);
 435
 436                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 437                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 438                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 439
 440                 hw->phy.ops.write_reg(hw,
 441                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 442                                       MDIO_MMD_AN,
 443                                       autoneg_reg);
 444         }
 445
 446         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 447                 /* Set or unset auto-negotiation 100M advertisement */
 448                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 449                                      MDIO_MMD_AN,
 450                                      &autoneg_reg);
 451
 452                 autoneg_reg &= ~(ADVERTISE_100FULL |
 453                                  ADVERTISE_100HALF);
 454                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 455                         autoneg_reg |= ADVERTISE_100FULL;
 456
 457                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 458                                       MDIO_MMD_AN,
 459                                       autoneg_reg);
 460         }
 461
 462         /* Restart PHY autonegotiation and wait for completion */
 463         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 464                              MDIO_MMD_AN, &autoneg_reg);
 465
 466         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 467
 468         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 469                               MDIO_MMD_AN, autoneg_reg);
 470
 471         /* Wait for autonegotiation to finish */
 472         for (time_out = 0; time_out < max_time_out; time_out++) {
 473                 udelay(10);
 474                 /* Restart PHY autonegotiation and wait for completion */
 475                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
 476                                               MDIO_MMD_AN,
 477                                               &autoneg_reg);
 478
 479                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 480                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
 481                         break;
 482                 }
 483         }
 484
 485         if (time_out == max_time_out) {
 486                 status = IXGBE_ERR_LINK_SETUP;
 487                 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
 488         }
 489
 490         return status;
 491 }
 492
 493 /**
 494  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 495  *  @hw: pointer to hardware structure
 496  *  @speed: new link speed
 497  *  @autoneg: true if autonegotiation enabled
 498  **/
 499 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 500                                        ixgbe_link_speed speed,
 501                                        bool autoneg,
 502                                        bool autoneg_wait_to_complete)
 503 {
 504
 505         /*
 506          * Clear autoneg_advertised and set new values based on input link
 507          * speed.
 508          */
 509         hw->phy.autoneg_advertised = 0;
 510
 511         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 512                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 513
 514         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 515                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 516
 517         if (speed & IXGBE_LINK_SPEED_100_FULL)
 518                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 519
 520         /* Setup link based on the new speed settings */
 521         hw->phy.ops.setup_link(hw);
 522
 523         return 0;
 524 }
 525
 526 /**
 527  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 528  * @hw: pointer to hardware structure
 529  * @speed: pointer to link speed
 530  * @autoneg: boolean auto-negotiation value
 531  *
 532  * Determines the link capabilities by reading the AUTOC register.
 533  */
 534 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 535                                                ixgbe_link_speed *speed,
 536                                                bool *autoneg)
 537 {
 538         s32 status = IXGBE_ERR_LINK_SETUP;
 539         u16 speed_ability;
 540
 541         *speed = 0;
 542         *autoneg = true;
 543
 544         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 545                                       &speed_ability);
 546
 547         if (status == 0) {
 548                 if (speed_ability & MDIO_SPEED_10G)
 549                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 550                 if (speed_ability & MDIO_PMA_SPEED_1000)
 551                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 552                 if (speed_ability & MDIO_PMA_SPEED_100)
 553                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 554         }
 555
 556         return status;
 557 }
 558
 559 /**
 560  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 561  *  @hw: pointer to hardware structure
 562  *
 563  *  Reads the VS1 register to determine if link is up and the current speed for
 564  *  the PHY.
 565  **/
 566 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 567                              bool *link_up)
 568 {
 569         s32 status = 0;
 570         u32 time_out;
 571         u32 max_time_out = 10;
 572         u16 phy_link = 0;
 573         u16 phy_speed = 0;
 574         u16 phy_data = 0;
 575
 576         /* Initialize speed and link to default case */
 577         *link_up = false;
 578         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 579
 580         /*
 581          * Check current speed and link status of the PHY register.
 582          * This is a vendor specific register and may have to
 583          * be changed for other copper PHYs.
 584          */
 585         for (time_out = 0; time_out < max_time_out; time_out++) {
 586                 udelay(10);
 587                 status = hw->phy.ops.read_reg(hw,
 588                                               MDIO_STAT1,
 589                                               MDIO_MMD_VEND1,
 590                                               &phy_data);
 591                 phy_link = phy_data &
 592                             IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 593                 phy_speed = phy_data &
 594                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 595                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 596                         *link_up = true;
 597                         if (phy_speed ==
 598                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 599                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 600                         break;
 601                 }
 602         }
 603
 604         return status;
 605 }
 606
 607 /**
 608  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 609  *      @hw: pointer to hardware structure
 610  *
 611  *      Restart autonegotiation and PHY and waits for completion.
 612  **/
 613 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 614 {
 615         s32 status = 0;
 616         u32 time_out;
 617         u32 max_time_out = 10;
 618         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 619         bool autoneg = false;
 620         ixgbe_link_speed speed;
 621
 622         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 623
 624         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 625                 /* Set or unset auto-negotiation 10G advertisement */
 626                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 627                                      MDIO_MMD_AN,
 628                                      &autoneg_reg);
 629
 630                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 631                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 632                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 633
 634                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 635                                       MDIO_MMD_AN,
 636                                       autoneg_reg);
 637         }
 638
 639         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 640                 /* Set or unset auto-negotiation 1G advertisement */
 641                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 642                                      MDIO_MMD_AN,
 643                                      &autoneg_reg);
 644
 645                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 646                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 647                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 648
 649                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 650                                       MDIO_MMD_AN,
 651                                       autoneg_reg);
 652         }
 653
 654         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 655                 /* Set or unset auto-negotiation 100M advertisement */
 656                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 657                                      MDIO_MMD_AN,
 658                                      &autoneg_reg);
 659
 660                 autoneg_reg &= ~(ADVERTISE_100FULL |
 661                                  ADVERTISE_100HALF);
 662                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 663                         autoneg_reg |= ADVERTISE_100FULL;
 664
 665                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 666                                       MDIO_MMD_AN,
 667                                       autoneg_reg);
 668         }
 669
 670         /* Restart PHY autonegotiation and wait for completion */
 671         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 672                              MDIO_MMD_AN, &autoneg_reg);
 673
 674         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 675
 676         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 677                               MDIO_MMD_AN, autoneg_reg);
 678
 679         /* Wait for autonegotiation to finish */
 680         for (time_out = 0; time_out < max_time_out; time_out++) {
 681                 udelay(10);
 682                 /* Restart PHY autonegotiation and wait for completion */
 683                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
 684                                               MDIO_MMD_AN,
 685                                               &autoneg_reg);
 686
 687                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 688                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
 689                         break;
 690         }
 691
 692         if (time_out == max_time_out) {
 693                 status = IXGBE_ERR_LINK_SETUP;
 694                 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
 695         }
 696
 697         return status;
 698 }
 699
 700 /**
 701  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 702  *  @hw: pointer to hardware structure
 703  *  @firmware_version: pointer to the PHY Firmware Version
 704  **/
 705 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 706                                        u16 *firmware_version)
 707 {
 708         s32 status = 0;
 709
 710         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 711                                       MDIO_MMD_VEND1,
 712                                       firmware_version);
 713
 714         return status;
 715 }
 716
 717 /**
 718  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 719  *  @hw: pointer to hardware structure
 720  *  @firmware_version: pointer to the PHY Firmware Version
 721  **/
 722 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 723                                            u16 *firmware_version)
 724 {
 725         s32 status = 0;
 726
 727         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 728                                       MDIO_MMD_VEND1,
 729                                       firmware_version);
 730
 731         return status;
 732 }
 733
 734 /**
 735  *  ixgbe_reset_phy_nl - Performs a PHY reset
 736  *  @hw: pointer to hardware structure
 737  **/
 738 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 739 {
 740         u16 phy_offset, control, eword, edata, block_crc;
 741         bool end_data = false;
 742         u16 list_offset, data_offset;
 743         u16 phy_data = 0;
 744         s32 ret_val = 0;
 745         u32 i;
 746
 747         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 748
 749         /* reset the PHY and poll for completion */
 750         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 751                               (phy_data | MDIO_CTRL1_RESET));
 752
 753         for (i = 0; i < 100; i++) {
 754                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 755                                      &phy_data);
 756                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 757                         break;
 758                 usleep_range(10000, 20000);
 759         }
 760
 761         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 762                 hw_dbg(hw, "PHY reset did not complete.\n");
 763                 ret_val = IXGBE_ERR_PHY;
 764                 goto out;
 765         }
 766
 767         /* Get init offsets */
 768         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 769                                                       &data_offset);
 770         if (ret_val != 0)
 771                 goto out;
 772
 773         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 774         data_offset++;
 775         while (!end_data) {
 776                 /*
 777                  * Read control word from PHY init contents offset
 778                  */
 779                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 780                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 781                            IXGBE_CONTROL_SHIFT_NL;
 782                 edata = eword & IXGBE_DATA_MASK_NL;
 783                 switch (control) {
 784                 case IXGBE_DELAY_NL:
 785                         data_offset++;
 786                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 787                         usleep_range(edata * 1000, edata * 2000);
 788                         break;
 789                 case IXGBE_DATA_NL:
 790                         hw_dbg(hw, "DATA:\n");
 791                         data_offset++;
 792                         hw->eeprom.ops.read(hw, data_offset++,
 793                                             &phy_offset);
 794                         for (i = 0; i < edata; i++) {
 795                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 796                                 hw->phy.ops.write_reg(hw, phy_offset,
 797                                                       MDIO_MMD_PMAPMD, eword);
 798                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 799                                        phy_offset);
 800                                 data_offset++;
 801                                 phy_offset++;
 802                         }
 803                         break;
 804                 case IXGBE_CONTROL_NL:
 805                         data_offset++;
 806                         hw_dbg(hw, "CONTROL:\n");
 807                         if (edata == IXGBE_CONTROL_EOL_NL) {
 808                                 hw_dbg(hw, "EOL\n");
 809                                 end_data = true;
 810                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 811                                 hw_dbg(hw, "SOL\n");
 812                         } else {
 813                                 hw_dbg(hw, "Bad control value\n");
 814                                 ret_val = IXGBE_ERR_PHY;
 815                                 goto out;
 816                         }
 817                         break;
 818                 default:
 819                         hw_dbg(hw, "Bad control type\n");
 820                         ret_val = IXGBE_ERR_PHY;
 821                         goto out;
 822                 }
 823         }
 824
 825 out:
 826         return ret_val;
 827 }
 828
 829 /**
 830  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 831  *  @hw: pointer to hardware structure
 832  *
 833  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 834  **/
 835 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 836 {
 837         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 838         u32 vendor_oui = 0;
 839         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 840         u8 identifier = 0;
 841         u8 comp_codes_1g = 0;
 842         u8 comp_codes_10g = 0;
 843         u8 oui_bytes[3] = {0, 0, 0};
 844         u8 cable_tech = 0;
 845         u8 cable_spec = 0;
 846         u16 enforce_sfp = 0;
 847
 848         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 849                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 850                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 851                 goto out;
 852         }
 853
 854         status = hw->phy.ops.read_i2c_eeprom(hw,
 855                                              IXGBE_SFF_IDENTIFIER,
 856                                              &identifier);
 857
 858         if (status == IXGBE_ERR_SWFW_SYNC ||
 859             status == IXGBE_ERR_I2C ||
 860             status == IXGBE_ERR_SFP_NOT_PRESENT)
 861                 goto err_read_i2c_eeprom;
 862
 863         /* LAN ID is needed for sfp_type determination */
 864         hw->mac.ops.set_lan_id(hw);
 865
 866         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 867                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 868                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 869         } else {
 870                 status = hw->phy.ops.read_i2c_eeprom(hw,
 871                                                      IXGBE_SFF_1GBE_COMP_CODES,
 872                                                      &comp_codes_1g);
 873
 874                 if (status == IXGBE_ERR_SWFW_SYNC ||
 875                     status == IXGBE_ERR_I2C ||
 876                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 877                         goto err_read_i2c_eeprom;
 878
 879                 status = hw->phy.ops.read_i2c_eeprom(hw,
 880                                                      IXGBE_SFF_10GBE_COMP_CODES,
 881                                                      &comp_codes_10g);
 882
 883                 if (status == IXGBE_ERR_SWFW_SYNC ||
 884                     status == IXGBE_ERR_I2C ||
 885                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 886                         goto err_read_i2c_eeprom;
 887                 status = hw->phy.ops.read_i2c_eeprom(hw,
 888                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
 889                                                      &cable_tech);
 890
 891                 if (status == IXGBE_ERR_SWFW_SYNC ||
 892                     status == IXGBE_ERR_I2C ||
 893                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 894                         goto err_read_i2c_eeprom;
 895
 896                  /* ID Module
 897                   * =========
 898                   * 0   SFP_DA_CU
 899                   * 1   SFP_SR
 900                   * 2   SFP_LR
 901                   * 3   SFP_DA_CORE0 - 82599-specific
 902                   * 4   SFP_DA_CORE1 - 82599-specific
 903                   * 5   SFP_SR/LR_CORE0 - 82599-specific
 904                   * 6   SFP_SR/LR_CORE1 - 82599-specific
 905                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
 906                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
 907                   * 9   SFP_1g_cu_CORE0 - 82599-specific
 908                   * 10  SFP_1g_cu_CORE1 - 82599-specific
 909                   */
 910                 if (hw->mac.type == ixgbe_mac_82598EB) {
 911                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 912                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 913                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 914                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
 915                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 916                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
 917                         else
 918                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 919                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
 920                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 921                                 if (hw->bus.lan_id == 0)
 922                                         hw->phy.sfp_type =
 923                                                      ixgbe_sfp_type_da_cu_core0;
 924                                 else
 925                                         hw->phy.sfp_type =
 926                                                      ixgbe_sfp_type_da_cu_core1;
 927                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 928                                 hw->phy.ops.read_i2c_eeprom(
 929                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
 930                                                 &cable_spec);
 931                                 if (cable_spec &
 932                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 933                                         if (hw->bus.lan_id == 0)
 934                                                 hw->phy.sfp_type =
 935                                                 ixgbe_sfp_type_da_act_lmt_core0;
 936                                         else
 937                                                 hw->phy.sfp_type =
 938                                                 ixgbe_sfp_type_da_act_lmt_core1;
 939                                 } else {
 940                                         hw->phy.sfp_type =
 941                                                         ixgbe_sfp_type_unknown;
 942                                 }
 943                         } else if (comp_codes_10g &
 944                                    (IXGBE_SFF_10GBASESR_CAPABLE |
 945                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
 946                                 if (hw->bus.lan_id == 0)
 947                                         hw->phy.sfp_type =
 948                                                       ixgbe_sfp_type_srlr_core0;
 949                                 else
 950                                         hw->phy.sfp_type =
 951                                                       ixgbe_sfp_type_srlr_core1;
 952                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
 953                                 if (hw->bus.lan_id == 0)
 954                                         hw->phy.sfp_type =
 955                                                 ixgbe_sfp_type_1g_cu_core0;
 956                                 else
 957                                         hw->phy.sfp_type =
 958                                                 ixgbe_sfp_type_1g_cu_core1;
 959                         } else {
 960                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 961                         }
 962                 }
 963
 964                 if (hw->phy.sfp_type != stored_sfp_type)
 965                         hw->phy.sfp_setup_needed = true;
 966
 967                 /* Determine if the SFP+ PHY is dual speed or not. */
 968                 hw->phy.multispeed_fiber = false;
 969                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
 970                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
 971                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
 972                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
 973                         hw->phy.multispeed_fiber = true;
 974
 975                 /* Determine PHY vendor */
 976                 if (hw->phy.type != ixgbe_phy_nl) {
 977                         hw->phy.id = identifier;
 978                         status = hw->phy.ops.read_i2c_eeprom(hw,
 979                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
 980                                                     &oui_bytes[0]);
 981
 982                         if (status == IXGBE_ERR_SWFW_SYNC ||
 983                             status == IXGBE_ERR_I2C ||
 984                             status == IXGBE_ERR_SFP_NOT_PRESENT)
 985                                 goto err_read_i2c_eeprom;
 986
 987                         status = hw->phy.ops.read_i2c_eeprom(hw,
 988                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
 989                                                     &oui_bytes[1]);
 990
 991                         if (status == IXGBE_ERR_SWFW_SYNC ||
 992                             status == IXGBE_ERR_I2C ||
 993                             status == IXGBE_ERR_SFP_NOT_PRESENT)
 994                                 goto err_read_i2c_eeprom;
 995
 996                         status = hw->phy.ops.read_i2c_eeprom(hw,
 997                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
 998                                                     &oui_bytes[2]);
 999
1000                         if (status == IXGBE_ERR_SWFW_SYNC ||
1001                             status == IXGBE_ERR_I2C ||
1002                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1003                                 goto err_read_i2c_eeprom;
1004
1005                         vendor_oui =
1006                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1007                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1008                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1009
1010                         switch (vendor_oui) {
1011                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1012                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1013                                         hw->phy.type =
1014                                                     ixgbe_phy_sfp_passive_tyco;
1015                                 break;
1016                         case IXGBE_SFF_VENDOR_OUI_FTL:
1017                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1018                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1019                                 else
1020                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1021                                 break;
1022                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1023                                 hw->phy.type = ixgbe_phy_sfp_avago;
1024                                 break;
1025                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1026                                 hw->phy.type = ixgbe_phy_sfp_intel;
1027                                 break;
1028                         default:
1029                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1030                                         hw->phy.type =
1031                                                  ixgbe_phy_sfp_passive_unknown;
1032                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1033                                         hw->phy.type =
1034                                                 ixgbe_phy_sfp_active_unknown;
1035                                 else
1036                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1037                                 break;
1038                         }
1039                 }
1040
1041                 /* Allow any DA cable vendor */
1042                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1043                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1044                         status = 0;
1045                         goto out;
1046                 }
1047
1048                 /* Verify supported 1G SFP modules */
1049                 if (comp_codes_10g == 0 &&
1050                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1051                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
1052                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1053                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1054                         goto out;
1055                 }
1056
1057                 /* Anything else 82598-based is supported */
1058                 if (hw->mac.type == ixgbe_mac_82598EB) {
1059                         status = 0;
1060                         goto out;
1061                 }
1062
1063                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1064                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1065                     !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1066                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
1067                         /* Make sure we're a supported PHY type */
1068                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1069                                 status = 0;
1070                         } else {
1071                                 hw_dbg(hw, "SFP+ module not supported\n");
1072                                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1073                                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1074                         }
1075                 } else {
1076                         status = 0;
1077                 }
1078         }
1079
1080 out:
1081         return status;
1082
1083 err_read_i2c_eeprom:
1084         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1085         if (hw->phy.type != ixgbe_phy_nl) {
1086                 hw->phy.id = 0;
1087                 hw->phy.type = ixgbe_phy_unknown;
1088         }
1089         return IXGBE_ERR_SFP_NOT_PRESENT;
1090 }
1091
1092 /**
1093  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1094  *  @hw: pointer to hardware structure
1095  *  @list_offset: offset to the SFP ID list
1096  *  @data_offset: offset to the SFP data block
1097  *
1098  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1099  *  so it returns the offsets to the phy init sequence block.
1100  **/
1101 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1102                                         u16 *list_offset,
1103                                         u16 *data_offset)
1104 {
1105         u16 sfp_id;
1106         u16 sfp_type = hw->phy.sfp_type;
1107
1108         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1109                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1110
1111         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1112                 return IXGBE_ERR_SFP_NOT_PRESENT;
1113
1114         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1115             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1116                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1117
1118         /*
1119          * Limiting active cables and 1G Phys must be initialized as
1120          * SR modules
1121          */
1122         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1123             sfp_type == ixgbe_sfp_type_1g_cu_core0)
1124                 sfp_type = ixgbe_sfp_type_srlr_core0;
1125         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1126                  sfp_type == ixgbe_sfp_type_1g_cu_core1)
1127                 sfp_type = ixgbe_sfp_type_srlr_core1;
1128
1129         /* Read offset to PHY init contents */
1130         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1131
1132         if ((!*list_offset) || (*list_offset == 0xFFFF))
1133                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1134
1135         /* Shift offset to first ID word */
1136         (*list_offset)++;
1137
1138         /*
1139          * Find the matching SFP ID in the EEPROM
1140          * and program the init sequence
1141          */
1142         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1143
1144         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1145                 if (sfp_id == sfp_type) {
1146                         (*list_offset)++;
1147                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
1148                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1149                                 hw_dbg(hw, "SFP+ module not supported\n");
1150                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1151                         } else {
1152                                 break;
1153                         }
1154                 } else {
1155                         (*list_offset) += 2;
1156                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1157                                 return IXGBE_ERR_PHY;
1158                 }
1159         }
1160
1161         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1162                 hw_dbg(hw, "No matching SFP+ module found\n");
1163                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1164         }
1165
1166         return 0;
1167 }
1168
1169 /**
1170  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1171  *  @hw: pointer to hardware structure
1172  *  @byte_offset: EEPROM byte offset to read
1173  *  @eeprom_data: value read
1174  *
1175  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1176  **/
1177 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1178                                   u8 *eeprom_data)
1179 {
1180         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1181                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1182                                          eeprom_data);
1183 }
1184
1185 /**
1186  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1187  *  @hw: pointer to hardware structure
1188  *  @byte_offset: EEPROM byte offset to write
1189  *  @eeprom_data: value to write
1190  *
1191  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1192  **/
1193 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1194                                    u8 eeprom_data)
1195 {
1196         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1197                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1198                                           eeprom_data);
1199 }
1200
1201 /**
1202  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1203  *  @hw: pointer to hardware structure
1204  *  @byte_offset: byte offset to read
1205  *  @data: value read
1206  *
1207  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1208  *  a specified deivce address.
1209  **/
1210 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1211                                 u8 dev_addr, u8 *data)
1212 {
1213         s32 status = 0;
1214         u32 max_retry = 10;
1215         u32 retry = 0;
1216         u16 swfw_mask = 0;
1217         bool nack = 1;
1218
1219         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1220                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1221         else
1222                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1223
1224         do {
1225                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1226                         status = IXGBE_ERR_SWFW_SYNC;
1227                         goto read_byte_out;
1228                 }
1229
1230                 ixgbe_i2c_start(hw);
1231
1232                 /* Device Address and write indication */
1233                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1234                 if (status != 0)
1235                         goto fail;
1236
1237                 status = ixgbe_get_i2c_ack(hw);
1238                 if (status != 0)
1239                         goto fail;
1240
1241                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1242                 if (status != 0)
1243                         goto fail;
1244
1245                 status = ixgbe_get_i2c_ack(hw);
1246                 if (status != 0)
1247                         goto fail;
1248
1249                 ixgbe_i2c_start(hw);
1250
1251                 /* Device Address and read indication */
1252                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1253                 if (status != 0)
1254                         goto fail;
1255
1256                 status = ixgbe_get_i2c_ack(hw);
1257                 if (status != 0)
1258                         goto fail;
1259
1260                 status = ixgbe_clock_in_i2c_byte(hw, data);
1261                 if (status != 0)
1262                         goto fail;
1263
1264                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1265                 if (status != 0)
1266                         goto fail;
1267
1268                 ixgbe_i2c_stop(hw);
1269                 break;
1270
1271 fail:
1272                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1273                 msleep(100);
1274                 ixgbe_i2c_bus_clear(hw);
1275                 retry++;
1276                 if (retry < max_retry)
1277                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1278                 else
1279                         hw_dbg(hw, "I2C byte read error.\n");
1280
1281         } while (retry < max_retry);
1282
1283         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1284
1285 read_byte_out:
1286         return status;
1287 }
1288
1289 /**
1290  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1291  *  @hw: pointer to hardware structure
1292  *  @byte_offset: byte offset to write
1293  *  @data: value to write
1294  *
1295  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1296  *  a specified device address.
1297  **/
1298 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1299                                  u8 dev_addr, u8 data)
1300 {
1301         s32 status = 0;
1302         u32 max_retry = 1;
1303         u32 retry = 0;
1304         u16 swfw_mask = 0;
1305
1306         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1307                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1308         else
1309                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1310
1311         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
1312                 status = IXGBE_ERR_SWFW_SYNC;
1313                 goto write_byte_out;
1314         }
1315
1316         do {
1317                 ixgbe_i2c_start(hw);
1318
1319                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1320                 if (status != 0)
1321                         goto fail;
1322
1323                 status = ixgbe_get_i2c_ack(hw);
1324                 if (status != 0)
1325                         goto fail;
1326
1327                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1328                 if (status != 0)
1329                         goto fail;
1330
1331                 status = ixgbe_get_i2c_ack(hw);
1332                 if (status != 0)
1333                         goto fail;
1334
1335                 status = ixgbe_clock_out_i2c_byte(hw, data);
1336                 if (status != 0)
1337                         goto fail;
1338
1339                 status = ixgbe_get_i2c_ack(hw);
1340                 if (status != 0)
1341                         goto fail;
1342
1343                 ixgbe_i2c_stop(hw);
1344                 break;
1345
1346 fail:
1347                 ixgbe_i2c_bus_clear(hw);
1348                 retry++;
1349                 if (retry < max_retry)
1350                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1351                 else
1352                         hw_dbg(hw, "I2C byte write error.\n");
1353         } while (retry < max_retry);
1354
1355         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1356
1357 write_byte_out:
1358         return status;
1359 }
1360
1361 /**
1362  *  ixgbe_i2c_start - Sets I2C start condition
1363  *  @hw: pointer to hardware structure
1364  *
1365  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1366  **/
1367 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1368 {
1369         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1370
1371         /* Start condition must begin with data and clock high */
1372         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1373         ixgbe_raise_i2c_clk(hw, &i2cctl);
1374
1375         /* Setup time for start condition (4.7us) */
1376         udelay(IXGBE_I2C_T_SU_STA);
1377
1378         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1379
1380         /* Hold time for start condition (4us) */
1381         udelay(IXGBE_I2C_T_HD_STA);
1382
1383         ixgbe_lower_i2c_clk(hw, &i2cctl);
1384
1385         /* Minimum low period of clock is 4.7 us */
1386         udelay(IXGBE_I2C_T_LOW);
1387
1388 }
1389
1390 /**
1391  *  ixgbe_i2c_stop - Sets I2C stop condition
1392  *  @hw: pointer to hardware structure
1393  *
1394  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1395  **/
1396 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1397 {
1398         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1399
1400         /* Stop condition must begin with data low and clock high */
1401         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1402         ixgbe_raise_i2c_clk(hw, &i2cctl);
1403
1404         /* Setup time for stop condition (4us) */
1405         udelay(IXGBE_I2C_T_SU_STO);
1406
1407         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1408
1409         /* bus free time between stop and start (4.7us)*/
1410         udelay(IXGBE_I2C_T_BUF);
1411 }
1412
1413 /**
1414  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1415  *  @hw: pointer to hardware structure
1416  *  @data: data byte to clock in
1417  *
1418  *  Clocks in one byte data via I2C data/clock
1419  **/
1420 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1421 {
1422         s32 status = 0;
1423         s32 i;
1424         bool bit = 0;
1425
1426         for (i = 7; i >= 0; i--) {
1427                 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1428                 *data |= bit << i;
1429
1430                 if (status != 0)
1431                         break;
1432         }
1433
1434         return status;
1435 }
1436
1437 /**
1438  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1439  *  @hw: pointer to hardware structure
1440  *  @data: data byte clocked out
1441  *
1442  *  Clocks out one byte data via I2C data/clock
1443  **/
1444 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1445 {
1446         s32 status = 0;
1447         s32 i;
1448         u32 i2cctl;
1449         bool bit = 0;
1450
1451         for (i = 7; i >= 0; i--) {
1452                 bit = (data >> i) & 0x1;
1453                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1454
1455                 if (status != 0)
1456                         break;
1457         }
1458
1459         /* Release SDA line (set high) */
1460         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1461         i2cctl |= IXGBE_I2C_DATA_OUT;
1462         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1463
1464         return status;
1465 }
1466
1467 /**
1468  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1469  *  @hw: pointer to hardware structure
1470  *
1471  *  Clocks in/out one bit via I2C data/clock
1472  **/
1473 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1474 {
1475         s32 status;
1476         u32 i = 0;
1477         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1478         u32 timeout = 10;
1479         bool ack = 1;
1480
1481         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1482
1483         if (status != 0)
1484                 goto out;
1485
1486         /* Minimum high period of clock is 4us */
1487         udelay(IXGBE_I2C_T_HIGH);
1488
1489         /* Poll for ACK.  Note that ACK in I2C spec is
1490          * transition from 1 to 0 */
1491         for (i = 0; i < timeout; i++) {
1492                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1493                 ack = ixgbe_get_i2c_data(&i2cctl);
1494
1495                 udelay(1);
1496                 if (ack == 0)
1497                         break;
1498         }
1499
1500         if (ack == 1) {
1501                 hw_dbg(hw, "I2C ack was not received.\n");
1502                 status = IXGBE_ERR_I2C;
1503         }
1504
1505         ixgbe_lower_i2c_clk(hw, &i2cctl);
1506
1507         /* Minimum low period of clock is 4.7 us */
1508         udelay(IXGBE_I2C_T_LOW);
1509
1510 out:
1511         return status;
1512 }
1513
1514 /**
1515  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1516  *  @hw: pointer to hardware structure
1517  *  @data: read data value
1518  *
1519  *  Clocks in one bit via I2C data/clock
1520  **/
1521 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1522 {
1523         s32 status;
1524         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1525
1526         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1527
1528         /* Minimum high period of clock is 4us */
1529         udelay(IXGBE_I2C_T_HIGH);
1530
1531         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1532         *data = ixgbe_get_i2c_data(&i2cctl);
1533
1534         ixgbe_lower_i2c_clk(hw, &i2cctl);
1535
1536         /* Minimum low period of clock is 4.7 us */
1537         udelay(IXGBE_I2C_T_LOW);
1538
1539         return status;
1540 }
1541
1542 /**
1543  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1544  *  @hw: pointer to hardware structure
1545  *  @data: data value to write
1546  *
1547  *  Clocks out one bit via I2C data/clock
1548  **/
1549 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1550 {
1551         s32 status;
1552         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1553
1554         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1555         if (status == 0) {
1556                 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1557
1558                 /* Minimum high period of clock is 4us */
1559                 udelay(IXGBE_I2C_T_HIGH);
1560
1561                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1562
1563                 /* Minimum low period of clock is 4.7 us.
1564                  * This also takes care of the data hold time.
1565                  */
1566                 udelay(IXGBE_I2C_T_LOW);
1567         } else {
1568                 status = IXGBE_ERR_I2C;
1569                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1570         }
1571
1572         return status;
1573 }
1574 /**
1575  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1576  *  @hw: pointer to hardware structure
1577  *  @i2cctl: Current value of I2CCTL register
1578  *
1579  *  Raises the I2C clock line '0'->'1'
1580  **/
1581 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1582 {
1583         s32 status = 0;
1584
1585         *i2cctl |= IXGBE_I2C_CLK_OUT;
1586
1587         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1588         IXGBE_WRITE_FLUSH(hw);
1589
1590         /* SCL rise time (1000ns) */
1591         udelay(IXGBE_I2C_T_RISE);
1592
1593         return status;
1594 }
1595
1596 /**
1597  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1598  *  @hw: pointer to hardware structure
1599  *  @i2cctl: Current value of I2CCTL register
1600  *
1601  *  Lowers the I2C clock line '1'->'0'
1602  **/
1603 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1604 {
1605
1606         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1607
1608         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1609         IXGBE_WRITE_FLUSH(hw);
1610
1611         /* SCL fall time (300ns) */
1612         udelay(IXGBE_I2C_T_FALL);
1613 }
1614
1615 /**
1616  *  ixgbe_set_i2c_data - Sets the I2C data bit
1617  *  @hw: pointer to hardware structure
1618  *  @i2cctl: Current value of I2CCTL register
1619  *  @data: I2C data value (0 or 1) to set
1620  *
1621  *  Sets the I2C data bit
1622  **/
1623 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1624 {
1625         s32 status = 0;
1626
1627         if (data)
1628                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1629         else
1630                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1631
1632         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1633         IXGBE_WRITE_FLUSH(hw);
1634
1635         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1636         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1637
1638         /* Verify data was set correctly */
1639         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1640         if (data != ixgbe_get_i2c_data(i2cctl)) {
1641                 status = IXGBE_ERR_I2C;
1642                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1643         }
1644
1645         return status;
1646 }
1647
1648 /**
1649  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1650  *  @hw: pointer to hardware structure
1651  *  @i2cctl: Current value of I2CCTL register
1652  *
1653  *  Returns the I2C data bit value
1654  **/
1655 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1656 {
1657         bool data;
1658
1659         if (*i2cctl & IXGBE_I2C_DATA_IN)
1660                 data = 1;
1661         else
1662                 data = 0;
1663
1664         return data;
1665 }
1666
1667 /**
1668  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1669  *  @hw: pointer to hardware structure
1670  *
1671  *  Clears the I2C bus by sending nine clock pulses.
1672  *  Used when data line is stuck low.
1673  **/
1674 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1675 {
1676         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1677         u32 i;
1678
1679         ixgbe_i2c_start(hw);
1680
1681         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1682
1683         for (i = 0; i < 9; i++) {
1684                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1685
1686                 /* Min high period of clock is 4us */
1687                 udelay(IXGBE_I2C_T_HIGH);
1688
1689                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1690
1691                 /* Min low period of clock is 4.7us*/
1692                 udelay(IXGBE_I2C_T_LOW);
1693         }
1694
1695         ixgbe_i2c_start(hw);
1696
1697         /* Put the i2c bus back to default state */
1698         ixgbe_i2c_stop(hw);
1699 }
1700
1701 /**
1702  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1703  *  @hw: pointer to hardware structure
1704  *
1705  *  Checks if the LASI temp alarm status was triggered due to overtemp
1706  **/
1707 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1708 {
1709         s32 status = 0;
1710         u16 phy_data = 0;
1711
1712         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1713                 goto out;
1714
1715         /* Check that the LASI temp alarm status was triggered */
1716         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1717                              MDIO_MMD_PMAPMD, &phy_data);
1718
1719         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1720                 goto out;
1721
1722         status = IXGBE_ERR_OVERTEMP;
1723 out:
1724         return status;
1725 }