drivers/net/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe_common.h"
  33 #include "ixgbe_phy.h"
  34
  35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  49
  50 /**
  51  *  ixgbe_identify_phy_generic - Get physical layer module
  52  *  @hw: pointer to hardware structure
  53  *
  54  *  Determines the physical layer module found on the current adapter.
  55  **/
  56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  57 {
  58         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  59         u32 phy_addr;
  60         u16 ext_ability = 0;
  61
  62         if (hw->phy.type == ixgbe_phy_unknown) {
  63                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  64                         hw->phy.mdio.prtad = phy_addr;
  65                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  66                                 ixgbe_get_phy_id(hw);
  67                                 hw->phy.type =
  68                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  69
  70                                 if (hw->phy.type == ixgbe_phy_unknown) {
  71                                         hw->phy.ops.read_reg(hw,
  72                                                              MDIO_PMA_EXTABLE,
  73                                                              MDIO_MMD_PMAPMD,
  74                                                              &ext_ability);
  75                                         if (ext_ability &
  76                                             (MDIO_PMA_EXTABLE_10GBT |
  77                                              MDIO_PMA_EXTABLE_1000BT))
  78                                                 hw->phy.type =
  79                                                          ixgbe_phy_cu_unknown;
  80                                         else
  81                                                 hw->phy.type =
  82                                                          ixgbe_phy_generic;
  83                                 }
  84
  85                                 status = 0;
  86                                 break;
  87                         }
  88                 }
  89                 /* clear value if nothing found */
  90                 if (status != 0)
  91                         hw->phy.mdio.prtad = 0;
  92         } else {
  93                 status = 0;
  94         }
  95
  96         return status;
  97 }
  98
  99 /**
 100  *  ixgbe_get_phy_id - Get the phy type
 101  *  @hw: pointer to hardware structure
 102  *
 103  **/
 104 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 105 {
 106         u32 status;
 107         u16 phy_id_high = 0;
 108         u16 phy_id_low = 0;
 109
 110         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 111                                       &phy_id_high);
 112
 113         if (status == 0) {
 114                 hw->phy.id = (u32)(phy_id_high << 16);
 115                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 116                                               &phy_id_low);
 117                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 118                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 119         }
 120         return status;
 121 }
 122
 123 /**
 124  *  ixgbe_get_phy_type_from_id - Get the phy type
 125  *  @hw: pointer to hardware structure
 126  *
 127  **/
 128 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 129 {
 130         enum ixgbe_phy_type phy_type;
 131
 132         switch (phy_id) {
 133         case TN1010_PHY_ID:
 134                 phy_type = ixgbe_phy_tn;
 135                 break;
 136         case X540_PHY_ID:
 137                 phy_type = ixgbe_phy_aq;
 138                 break;
 139         case QT2022_PHY_ID:
 140                 phy_type = ixgbe_phy_qt;
 141                 break;
 142         case ATH_PHY_ID:
 143                 phy_type = ixgbe_phy_nl;
 144                 break;
 145         default:
 146                 phy_type = ixgbe_phy_unknown;
 147                 break;
 148         }
 149
 150         return phy_type;
 151 }
 152
 153 /**
 154  *  ixgbe_reset_phy_generic - Performs a PHY reset
 155  *  @hw: pointer to hardware structure
 156  **/
 157 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 158 {
 159         u32 i;
 160         u16 ctrl = 0;
 161         s32 status = 0;
 162
 163         if (hw->phy.type == ixgbe_phy_unknown)
 164                 status = ixgbe_identify_phy_generic(hw);
 165
 166         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 167                 goto out;
 168
 169         /* Don't reset PHY if it's shut down due to overtemp. */
 170         if (!hw->phy.reset_if_overtemp &&
 171             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 172                 goto out;
 173
 174         /*
 175          * Perform soft PHY reset to the PHY_XS.
 176          * This will cause a soft reset to the PHY
 177          */
 178         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 179                               MDIO_MMD_PHYXS,
 180                               MDIO_CTRL1_RESET);
 181
 182         /*
 183          * Poll for reset bit to self-clear indicating reset is complete.
 184          * Some PHYs could take up to 3 seconds to complete and need about
 185          * 1.7 usec delay after the reset is complete.
 186          */
 187         for (i = 0; i < 30; i++) {
 188                 msleep(100);
 189                 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 190                                      MDIO_MMD_PHYXS, &ctrl);
 191                 if (!(ctrl & MDIO_CTRL1_RESET)) {
 192                         udelay(2);
 193                         break;
 194                 }
 195         }
 196
 197         if (ctrl & MDIO_CTRL1_RESET) {
 198                 status = IXGBE_ERR_RESET_FAILED;
 199                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 200         }
 201
 202 out:
 203         return status;
 204 }
 205
 206 /**
 207  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 208  *  @hw: pointer to hardware structure
 209  *  @reg_addr: 32 bit address of PHY register to read
 210  *  @phy_data: Pointer to read data from PHY register
 211  **/
 212 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 213                                u32 device_type, u16 *phy_data)
 214 {
 215         u32 command;
 216         u32 i;
 217         u32 data;
 218         s32 status = 0;
 219         u16 gssr;
 220
 221         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 222                 gssr = IXGBE_GSSR_PHY1_SM;
 223         else
 224                 gssr = IXGBE_GSSR_PHY0_SM;
 225
 226         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
 227                 status = IXGBE_ERR_SWFW_SYNC;
 228
 229         if (status == 0) {
 230                 /* Setup and write the address cycle command */
 231                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 232                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 233                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 234                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 235
 236                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 237
 238                 /*
 239                  * Check every 10 usec to see if the address cycle completed.
 240                  * The MDI Command bit will clear when the operation is
 241                  * complete
 242                  */
 243                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 244                         udelay(10);
 245
 246                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 247
 248                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 249                                 break;
 250                 }
 251
 252                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 253                         hw_dbg(hw, "PHY address command did not complete.\n");
 254                         status = IXGBE_ERR_PHY;
 255                 }
 256
 257                 if (status == 0) {
 258                         /*
 259                          * Address cycle complete, setup and write the read
 260                          * command
 261                          */
 262                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 263                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 264                                    (hw->phy.mdio.prtad <<
 265                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 266                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 267
 268                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 269
 270                         /*
 271                          * Check every 10 usec to see if the address cycle
 272                          * completed. The MDI Command bit will clear when the
 273                          * operation is complete
 274                          */
 275                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 276                                 udelay(10);
 277
 278                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 279
 280                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 281                                         break;
 282                         }
 283
 284                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 285                                 hw_dbg(hw, "PHY read command didn't complete\n");
 286                                 status = IXGBE_ERR_PHY;
 287                         } else {
 288                                 /*
 289                                  * Read operation is complete.  Get the data
 290                                  * from MSRWD
 291                                  */
 292                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 293                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 294                                 *phy_data = (u16)(data);
 295                         }
 296                 }
 297
 298                 hw->mac.ops.release_swfw_sync(hw, gssr);
 299         }
 300
 301         return status;
 302 }
 303
 304 /**
 305  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 306  *  @hw: pointer to hardware structure
 307  *  @reg_addr: 32 bit PHY register to write
 308  *  @device_type: 5 bit device type
 309  *  @phy_data: Data to write to the PHY register
 310  **/
 311 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 312                                 u32 device_type, u16 phy_data)
 313 {
 314         u32 command;
 315         u32 i;
 316         s32 status = 0;
 317         u16 gssr;
 318
 319         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 320                 gssr = IXGBE_GSSR_PHY1_SM;
 321         else
 322                 gssr = IXGBE_GSSR_PHY0_SM;
 323
 324         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
 325                 status = IXGBE_ERR_SWFW_SYNC;
 326
 327         if (status == 0) {
 328                 /* Put the data in the MDI single read and write data register*/
 329                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 330
 331                 /* Setup and write the address cycle command */
 332                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 333                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 334                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 335                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 336
 337                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 338
 339                 /*
 340                  * Check every 10 usec to see if the address cycle completed.
 341                  * The MDI Command bit will clear when the operation is
 342                  * complete
 343                  */
 344                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 345                         udelay(10);
 346
 347                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 348
 349                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 350                                 break;
 351                 }
 352
 353                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 354                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 355                         status = IXGBE_ERR_PHY;
 356                 }
 357
 358                 if (status == 0) {
 359                         /*
 360                          * Address cycle complete, setup and write the write
 361                          * command
 362                          */
 363                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 364                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 365                                    (hw->phy.mdio.prtad <<
 366                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 367                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 368
 369                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 370
 371                         /*
 372                          * Check every 10 usec to see if the address cycle
 373                          * completed. The MDI Command bit will clear when the
 374                          * operation is complete
 375                          */
 376                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 377                                 udelay(10);
 378
 379                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 380
 381                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 382                                         break;
 383                         }
 384
 385                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 386                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 387                                 status = IXGBE_ERR_PHY;
 388                         }
 389                 }
 390
 391                 hw->mac.ops.release_swfw_sync(hw, gssr);
 392         }
 393
 394         return status;
 395 }
 396
 397 /**
 398  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 399  *  @hw: pointer to hardware structure
 400  *
 401  *  Restart autonegotiation and PHY and waits for completion.
 402  **/
 403 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 404 {
 405         s32 status = 0;
 406         u32 time_out;
 407         u32 max_time_out = 10;
 408         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 409         bool autoneg = false;
 410         ixgbe_link_speed speed;
 411
 412         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 413
 414         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 415                 /* Set or unset auto-negotiation 10G advertisement */
 416                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 417                                      MDIO_MMD_AN,
 418                                      &autoneg_reg);
 419
 420                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 421                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 422                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 423
 424                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 425                                       MDIO_MMD_AN,
 426                                       autoneg_reg);
 427         }
 428
 429         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 430                 /* Set or unset auto-negotiation 1G advertisement */
 431                 hw->phy.ops.read_reg(hw,
 432                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 433                                      MDIO_MMD_AN,
 434                                      &autoneg_reg);
 435
 436                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 437                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 438                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 439
 440                 hw->phy.ops.write_reg(hw,
 441                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 442                                       MDIO_MMD_AN,
 443                                       autoneg_reg);
 444         }
 445
 446         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 447                 /* Set or unset auto-negotiation 100M advertisement */
 448                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 449                                      MDIO_MMD_AN,
 450                                      &autoneg_reg);
 451
 452                 autoneg_reg &= ~ADVERTISE_100FULL;
 453                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 454                         autoneg_reg |= ADVERTISE_100FULL;
 455
 456                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 457                                       MDIO_MMD_AN,
 458                                       autoneg_reg);
 459         }
 460
 461         /* Restart PHY autonegotiation and wait for completion */
 462         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 463                              MDIO_MMD_AN, &autoneg_reg);
 464
 465         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 466
 467         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 468                               MDIO_MMD_AN, autoneg_reg);
 469
 470         /* Wait for autonegotiation to finish */
 471         for (time_out = 0; time_out < max_time_out; time_out++) {
 472                 udelay(10);
 473                 /* Restart PHY autonegotiation and wait for completion */
 474                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
 475                                               MDIO_MMD_AN,
 476                                               &autoneg_reg);
 477
 478                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 479                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
 480                         break;
 481                 }
 482         }
 483
 484         if (time_out == max_time_out) {
 485                 status = IXGBE_ERR_LINK_SETUP;
 486                 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
 487         }
 488
 489         return status;
 490 }
 491
 492 /**
 493  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 494  *  @hw: pointer to hardware structure
 495  *  @speed: new link speed
 496  *  @autoneg: true if autonegotiation enabled
 497  **/
 498 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 499                                        ixgbe_link_speed speed,
 500                                        bool autoneg,
 501                                        bool autoneg_wait_to_complete)
 502 {
 503
 504         /*
 505          * Clear autoneg_advertised and set new values based on input link
 506          * speed.
 507          */
 508         hw->phy.autoneg_advertised = 0;
 509
 510         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 511                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 512
 513         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 514                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 515
 516         if (speed & IXGBE_LINK_SPEED_100_FULL)
 517                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 518
 519         /* Setup link based on the new speed settings */
 520         hw->phy.ops.setup_link(hw);
 521
 522         return 0;
 523 }
 524
 525 /**
 526  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 527  * @hw: pointer to hardware structure
 528  * @speed: pointer to link speed
 529  * @autoneg: boolean auto-negotiation value
 530  *
 531  * Determines the link capabilities by reading the AUTOC register.
 532  */
 533 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 534                                                ixgbe_link_speed *speed,
 535                                                bool *autoneg)
 536 {
 537         s32 status = IXGBE_ERR_LINK_SETUP;
 538         u16 speed_ability;
 539
 540         *speed = 0;
 541         *autoneg = true;
 542
 543         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 544                                       &speed_ability);
 545
 546         if (status == 0) {
 547                 if (speed_ability & MDIO_SPEED_10G)
 548                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 549                 if (speed_ability & MDIO_PMA_SPEED_1000)
 550                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 551                 if (speed_ability & MDIO_PMA_SPEED_100)
 552                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 553         }
 554
 555         return status;
 556 }
 557
 558 /**
 559  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 560  *  @hw: pointer to hardware structure
 561  *
 562  *  Reads the VS1 register to determine if link is up and the current speed for
 563  *  the PHY.
 564  **/
 565 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 566                              bool *link_up)
 567 {
 568         s32 status = 0;
 569         u32 time_out;
 570         u32 max_time_out = 10;
 571         u16 phy_link = 0;
 572         u16 phy_speed = 0;
 573         u16 phy_data = 0;
 574
 575         /* Initialize speed and link to default case */
 576         *link_up = false;
 577         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 578
 579         /*
 580          * Check current speed and link status of the PHY register.
 581          * This is a vendor specific register and may have to
 582          * be changed for other copper PHYs.
 583          */
 584         for (time_out = 0; time_out < max_time_out; time_out++) {
 585                 udelay(10);
 586                 status = hw->phy.ops.read_reg(hw,
 587                                               MDIO_STAT1,
 588                                               MDIO_MMD_VEND1,
 589                                               &phy_data);
 590                 phy_link = phy_data &
 591                             IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 592                 phy_speed = phy_data &
 593                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 594                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 595                         *link_up = true;
 596                         if (phy_speed ==
 597                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 598                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 599                         break;
 600                 }
 601         }
 602
 603         return status;
 604 }
 605
 606 /**
 607  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 608  *      @hw: pointer to hardware structure
 609  *
 610  *      Restart autonegotiation and PHY and waits for completion.
 611  **/
 612 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 613 {
 614         s32 status = 0;
 615         u32 time_out;
 616         u32 max_time_out = 10;
 617         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 618         bool autoneg = false;
 619         ixgbe_link_speed speed;
 620
 621         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 622
 623         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 624                 /* Set or unset auto-negotiation 10G advertisement */
 625                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 626                                      MDIO_MMD_AN,
 627                                      &autoneg_reg);
 628
 629                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 630                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 631                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 632
 633                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 634                                       MDIO_MMD_AN,
 635                                       autoneg_reg);
 636         }
 637
 638         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 639                 /* Set or unset auto-negotiation 1G advertisement */
 640                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 641                                      MDIO_MMD_AN,
 642                                      &autoneg_reg);
 643
 644                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 645                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 646                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 647
 648                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 649                                       MDIO_MMD_AN,
 650                                       autoneg_reg);
 651         }
 652
 653         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 654                 /* Set or unset auto-negotiation 100M advertisement */
 655                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 656                                      MDIO_MMD_AN,
 657                                      &autoneg_reg);
 658
 659                 autoneg_reg &= ~ADVERTISE_100FULL;
 660                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 661                         autoneg_reg |= ADVERTISE_100FULL;
 662
 663                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 664                                       MDIO_MMD_AN,
 665                                       autoneg_reg);
 666         }
 667
 668         /* Restart PHY autonegotiation and wait for completion */
 669         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 670                              MDIO_MMD_AN, &autoneg_reg);
 671
 672         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 673
 674         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 675                               MDIO_MMD_AN, autoneg_reg);
 676
 677         /* Wait for autonegotiation to finish */
 678         for (time_out = 0; time_out < max_time_out; time_out++) {
 679                 udelay(10);
 680                 /* Restart PHY autonegotiation and wait for completion */
 681                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
 682                                               MDIO_MMD_AN,
 683                                               &autoneg_reg);
 684
 685                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 686                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
 687                         break;
 688         }
 689
 690         if (time_out == max_time_out) {
 691                 status = IXGBE_ERR_LINK_SETUP;
 692                 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
 693         }
 694
 695         return status;
 696 }
 697
 698 /**
 699  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 700  *  @hw: pointer to hardware structure
 701  *  @firmware_version: pointer to the PHY Firmware Version
 702  **/
 703 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 704                                        u16 *firmware_version)
 705 {
 706         s32 status = 0;
 707
 708         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 709                                       MDIO_MMD_VEND1,
 710                                       firmware_version);
 711
 712         return status;
 713 }
 714
 715 /**
 716  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 717  *  @hw: pointer to hardware structure
 718  *  @firmware_version: pointer to the PHY Firmware Version
 719  **/
 720 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 721                                            u16 *firmware_version)
 722 {
 723         s32 status = 0;
 724
 725         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 726                                       MDIO_MMD_VEND1,
 727                                       firmware_version);
 728
 729         return status;
 730 }
 731
 732 /**
 733  *  ixgbe_reset_phy_nl - Performs a PHY reset
 734  *  @hw: pointer to hardware structure
 735  **/
 736 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 737 {
 738         u16 phy_offset, control, eword, edata, block_crc;
 739         bool end_data = false;
 740         u16 list_offset, data_offset;
 741         u16 phy_data = 0;
 742         s32 ret_val = 0;
 743         u32 i;
 744
 745         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 746
 747         /* reset the PHY and poll for completion */
 748         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 749                               (phy_data | MDIO_CTRL1_RESET));
 750
 751         for (i = 0; i < 100; i++) {
 752                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 753                                      &phy_data);
 754                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 755                         break;
 756                 msleep(10);
 757         }
 758
 759         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 760                 hw_dbg(hw, "PHY reset did not complete.\n");
 761                 ret_val = IXGBE_ERR_PHY;
 762                 goto out;
 763         }
 764
 765         /* Get init offsets */
 766         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 767                                                       &data_offset);
 768         if (ret_val != 0)
 769                 goto out;
 770
 771         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 772         data_offset++;
 773         while (!end_data) {
 774                 /*
 775                  * Read control word from PHY init contents offset
 776                  */
 777                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 778                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 779                            IXGBE_CONTROL_SHIFT_NL;
 780                 edata = eword & IXGBE_DATA_MASK_NL;
 781                 switch (control) {
 782                 case IXGBE_DELAY_NL:
 783                         data_offset++;
 784                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 785                         msleep(edata);
 786                         break;
 787                 case IXGBE_DATA_NL:
 788                         hw_dbg(hw, "DATA:\n");
 789                         data_offset++;
 790                         hw->eeprom.ops.read(hw, data_offset++,
 791                                             &phy_offset);
 792                         for (i = 0; i < edata; i++) {
 793                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 794                                 hw->phy.ops.write_reg(hw, phy_offset,
 795                                                       MDIO_MMD_PMAPMD, eword);
 796                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 797                                        phy_offset);
 798                                 data_offset++;
 799                                 phy_offset++;
 800                         }
 801                         break;
 802                 case IXGBE_CONTROL_NL:
 803                         data_offset++;
 804                         hw_dbg(hw, "CONTROL:\n");
 805                         if (edata == IXGBE_CONTROL_EOL_NL) {
 806                                 hw_dbg(hw, "EOL\n");
 807                                 end_data = true;
 808                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 809                                 hw_dbg(hw, "SOL\n");
 810                         } else {
 811                                 hw_dbg(hw, "Bad control value\n");
 812                                 ret_val = IXGBE_ERR_PHY;
 813                                 goto out;
 814                         }
 815                         break;
 816                 default:
 817                         hw_dbg(hw, "Bad control type\n");
 818                         ret_val = IXGBE_ERR_PHY;
 819                         goto out;
 820                 }
 821         }
 822
 823 out:
 824         return ret_val;
 825 }
 826
 827 /**
 828  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 829  *  @hw: pointer to hardware structure
 830  *
 831  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 832  **/
 833 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 834 {
 835         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 836         u32 vendor_oui = 0;
 837         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 838         u8 identifier = 0;
 839         u8 comp_codes_1g = 0;
 840         u8 comp_codes_10g = 0;
 841         u8 oui_bytes[3] = {0, 0, 0};
 842         u8 cable_tech = 0;
 843         u8 cable_spec = 0;
 844         u16 enforce_sfp = 0;
 845
 846         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 847                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 848                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 849                 goto out;
 850         }
 851
 852         status = hw->phy.ops.read_i2c_eeprom(hw,
 853                                              IXGBE_SFF_IDENTIFIER,
 854                                              &identifier);
 855
 856         if (status == IXGBE_ERR_SWFW_SYNC ||
 857             status == IXGBE_ERR_I2C ||
 858             status == IXGBE_ERR_SFP_NOT_PRESENT)
 859                 goto err_read_i2c_eeprom;
 860
 861         /* LAN ID is needed for sfp_type determination */
 862         hw->mac.ops.set_lan_id(hw);
 863
 864         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 865                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 866                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 867         } else {
 868                 status = hw->phy.ops.read_i2c_eeprom(hw,
 869                                                      IXGBE_SFF_1GBE_COMP_CODES,
 870                                                      &comp_codes_1g);
 871
 872                 if (status == IXGBE_ERR_SWFW_SYNC ||
 873                     status == IXGBE_ERR_I2C ||
 874                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 875                         goto err_read_i2c_eeprom;
 876
 877                 status = hw->phy.ops.read_i2c_eeprom(hw,
 878                                                      IXGBE_SFF_10GBE_COMP_CODES,
 879                                                      &comp_codes_10g);
 880
 881                 if (status == IXGBE_ERR_SWFW_SYNC ||
 882                     status == IXGBE_ERR_I2C ||
 883                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 884                         goto err_read_i2c_eeprom;
 885                 status = hw->phy.ops.read_i2c_eeprom(hw,
 886                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
 887                                                      &cable_tech);
 888
 889                 if (status == IXGBE_ERR_SWFW_SYNC ||
 890                     status == IXGBE_ERR_I2C ||
 891                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 892                         goto err_read_i2c_eeprom;
 893
 894                  /* ID Module
 895                   * =========
 896                   * 0   SFP_DA_CU
 897                   * 1   SFP_SR
 898                   * 2   SFP_LR
 899                   * 3   SFP_DA_CORE0 - 82599-specific
 900                   * 4   SFP_DA_CORE1 - 82599-specific
 901                   * 5   SFP_SR/LR_CORE0 - 82599-specific
 902                   * 6   SFP_SR/LR_CORE1 - 82599-specific
 903                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
 904                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
 905                   * 9   SFP_1g_cu_CORE0 - 82599-specific
 906                   * 10  SFP_1g_cu_CORE1 - 82599-specific
 907                   */
 908                 if (hw->mac.type == ixgbe_mac_82598EB) {
 909                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 910                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 911                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 912                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
 913                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 914                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
 915                         else
 916                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 917                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
 918                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 919                                 if (hw->bus.lan_id == 0)
 920                                         hw->phy.sfp_type =
 921                                                      ixgbe_sfp_type_da_cu_core0;
 922                                 else
 923                                         hw->phy.sfp_type =
 924                                                      ixgbe_sfp_type_da_cu_core1;
 925                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 926                                 hw->phy.ops.read_i2c_eeprom(
 927                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
 928                                                 &cable_spec);
 929                                 if (cable_spec &
 930                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 931                                         if (hw->bus.lan_id == 0)
 932                                                 hw->phy.sfp_type =
 933                                                 ixgbe_sfp_type_da_act_lmt_core0;
 934                                         else
 935                                                 hw->phy.sfp_type =
 936                                                 ixgbe_sfp_type_da_act_lmt_core1;
 937                                 } else {
 938                                         hw->phy.sfp_type =
 939                                                         ixgbe_sfp_type_unknown;
 940                                 }
 941                         } else if (comp_codes_10g &
 942                                    (IXGBE_SFF_10GBASESR_CAPABLE |
 943                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
 944                                 if (hw->bus.lan_id == 0)
 945                                         hw->phy.sfp_type =
 946                                                       ixgbe_sfp_type_srlr_core0;
 947                                 else
 948                                         hw->phy.sfp_type =
 949                                                       ixgbe_sfp_type_srlr_core1;
 950                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
 951                                 if (hw->bus.lan_id == 0)
 952                                         hw->phy.sfp_type =
 953                                                 ixgbe_sfp_type_1g_cu_core0;
 954                                 else
 955                                         hw->phy.sfp_type =
 956                                                 ixgbe_sfp_type_1g_cu_core1;
 957                         } else {
 958                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 959                         }
 960                 }
 961
 962                 if (hw->phy.sfp_type != stored_sfp_type)
 963                         hw->phy.sfp_setup_needed = true;
 964
 965                 /* Determine if the SFP+ PHY is dual speed or not. */
 966                 hw->phy.multispeed_fiber = false;
 967                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
 968                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
 969                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
 970                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
 971                         hw->phy.multispeed_fiber = true;
 972
 973                 /* Determine PHY vendor */
 974                 if (hw->phy.type != ixgbe_phy_nl) {
 975                         hw->phy.id = identifier;
 976                         status = hw->phy.ops.read_i2c_eeprom(hw,
 977                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
 978                                                     &oui_bytes[0]);
 979
 980                         if (status == IXGBE_ERR_SWFW_SYNC ||
 981                             status == IXGBE_ERR_I2C ||
 982                             status == IXGBE_ERR_SFP_NOT_PRESENT)
 983                                 goto err_read_i2c_eeprom;
 984
 985                         status = hw->phy.ops.read_i2c_eeprom(hw,
 986                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
 987                                                     &oui_bytes[1]);
 988
 989                         if (status == IXGBE_ERR_SWFW_SYNC ||
 990                             status == IXGBE_ERR_I2C ||
 991                             status == IXGBE_ERR_SFP_NOT_PRESENT)
 992                                 goto err_read_i2c_eeprom;
 993
 994                         status = hw->phy.ops.read_i2c_eeprom(hw,
 995                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
 996                                                     &oui_bytes[2]);
 997
 998                         if (status == IXGBE_ERR_SWFW_SYNC ||
 999                             status == IXGBE_ERR_I2C ||
1000                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1001                                 goto err_read_i2c_eeprom;
1002
1003                         vendor_oui =
1004                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1005                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1006                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1007
1008                         switch (vendor_oui) {
1009                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1010                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1011                                         hw->phy.type =
1012                                                     ixgbe_phy_sfp_passive_tyco;
1013                                 break;
1014                         case IXGBE_SFF_VENDOR_OUI_FTL:
1015                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1016                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1017                                 else
1018                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1019                                 break;
1020                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1021                                 hw->phy.type = ixgbe_phy_sfp_avago;
1022                                 break;
1023                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1024                                 hw->phy.type = ixgbe_phy_sfp_intel;
1025                                 break;
1026                         default:
1027                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1028                                         hw->phy.type =
1029                                                  ixgbe_phy_sfp_passive_unknown;
1030                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1031                                         hw->phy.type =
1032                                                 ixgbe_phy_sfp_active_unknown;
1033                                 else
1034                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1035                                 break;
1036                         }
1037                 }
1038
1039                 /* Allow any DA cable vendor */
1040                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1041                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1042                         status = 0;
1043                         goto out;
1044                 }
1045
1046                 /* Verify supported 1G SFP modules */
1047                 if (comp_codes_10g == 0 &&
1048                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1049                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
1050                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1051                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1052                         goto out;
1053                 }
1054
1055                 /* Anything else 82598-based is supported */
1056                 if (hw->mac.type == ixgbe_mac_82598EB) {
1057                         status = 0;
1058                         goto out;
1059                 }
1060
1061                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1062                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1063                     !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1064                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
1065                         /* Make sure we're a supported PHY type */
1066                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1067                                 status = 0;
1068                         } else {
1069                                 hw_dbg(hw, "SFP+ module not supported\n");
1070                                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1071                                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1072                         }
1073                 } else {
1074                         status = 0;
1075                 }
1076         }
1077
1078 out:
1079         return status;
1080
1081 err_read_i2c_eeprom:
1082         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1083         if (hw->phy.type != ixgbe_phy_nl) {
1084                 hw->phy.id = 0;
1085                 hw->phy.type = ixgbe_phy_unknown;
1086         }
1087         return IXGBE_ERR_SFP_NOT_PRESENT;
1088 }
1089
1090 /**
1091  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1092  *  @hw: pointer to hardware structure
1093  *  @list_offset: offset to the SFP ID list
1094  *  @data_offset: offset to the SFP data block
1095  *
1096  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1097  *  so it returns the offsets to the phy init sequence block.
1098  **/
1099 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1100                                         u16 *list_offset,
1101                                         u16 *data_offset)
1102 {
1103         u16 sfp_id;
1104         u16 sfp_type = hw->phy.sfp_type;
1105
1106         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1107                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1108
1109         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1110                 return IXGBE_ERR_SFP_NOT_PRESENT;
1111
1112         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1113             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1114                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1115
1116         /*
1117          * Limiting active cables and 1G Phys must be initialized as
1118          * SR modules
1119          */
1120         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1121             sfp_type == ixgbe_sfp_type_1g_cu_core0)
1122                 sfp_type = ixgbe_sfp_type_srlr_core0;
1123         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1124                  sfp_type == ixgbe_sfp_type_1g_cu_core1)
1125                 sfp_type = ixgbe_sfp_type_srlr_core1;
1126
1127         /* Read offset to PHY init contents */
1128         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1129
1130         if ((!*list_offset) || (*list_offset == 0xFFFF))
1131                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1132
1133         /* Shift offset to first ID word */
1134         (*list_offset)++;
1135
1136         /*
1137          * Find the matching SFP ID in the EEPROM
1138          * and program the init sequence
1139          */
1140         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1141
1142         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1143                 if (sfp_id == sfp_type) {
1144                         (*list_offset)++;
1145                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
1146                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1147                                 hw_dbg(hw, "SFP+ module not supported\n");
1148                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1149                         } else {
1150                                 break;
1151                         }
1152                 } else {
1153                         (*list_offset) += 2;
1154                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1155                                 return IXGBE_ERR_PHY;
1156                 }
1157         }
1158
1159         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1160                 hw_dbg(hw, "No matching SFP+ module found\n");
1161                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1162         }
1163
1164         return 0;
1165 }
1166
1167 /**
1168  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1169  *  @hw: pointer to hardware structure
1170  *  @byte_offset: EEPROM byte offset to read
1171  *  @eeprom_data: value read
1172  *
1173  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1174  **/
1175 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1176                                   u8 *eeprom_data)
1177 {
1178         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1179                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1180                                          eeprom_data);
1181 }
1182
1183 /**
1184  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1185  *  @hw: pointer to hardware structure
1186  *  @byte_offset: EEPROM byte offset to write
1187  *  @eeprom_data: value to write
1188  *
1189  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1190  **/
1191 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1192                                    u8 eeprom_data)
1193 {
1194         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1195                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1196                                           eeprom_data);
1197 }
1198
1199 /**
1200  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1201  *  @hw: pointer to hardware structure
1202  *  @byte_offset: byte offset to read
1203  *  @data: value read
1204  *
1205  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1206  *  a specified deivce address.
1207  **/
1208 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1209                                 u8 dev_addr, u8 *data)
1210 {
1211         s32 status = 0;
1212         u32 max_retry = 10;
1213         u32 retry = 0;
1214         u16 swfw_mask = 0;
1215         bool nack = 1;
1216
1217         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1218                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1219         else
1220                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1221
1222         do {
1223                 if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
1224                         status = IXGBE_ERR_SWFW_SYNC;
1225                         goto read_byte_out;
1226                 }
1227
1228                 ixgbe_i2c_start(hw);
1229
1230                 /* Device Address and write indication */
1231                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1232                 if (status != 0)
1233                         goto fail;
1234
1235                 status = ixgbe_get_i2c_ack(hw);
1236                 if (status != 0)
1237                         goto fail;
1238
1239                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1240                 if (status != 0)
1241                         goto fail;
1242
1243                 status = ixgbe_get_i2c_ack(hw);
1244                 if (status != 0)
1245                         goto fail;
1246
1247                 ixgbe_i2c_start(hw);
1248
1249                 /* Device Address and read indication */
1250                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1251                 if (status != 0)
1252                         goto fail;
1253
1254                 status = ixgbe_get_i2c_ack(hw);
1255                 if (status != 0)
1256                         goto fail;
1257
1258                 status = ixgbe_clock_in_i2c_byte(hw, data);
1259                 if (status != 0)
1260                         goto fail;
1261
1262                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1263                 if (status != 0)
1264                         goto fail;
1265
1266                 ixgbe_i2c_stop(hw);
1267                 break;
1268
1269 fail:
1270                 ixgbe_release_swfw_sync(hw, swfw_mask);
1271                 msleep(100);
1272                 ixgbe_i2c_bus_clear(hw);
1273                 retry++;
1274                 if (retry < max_retry)
1275                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1276                 else
1277                         hw_dbg(hw, "I2C byte read error.\n");
1278
1279         } while (retry < max_retry);
1280
1281         ixgbe_release_swfw_sync(hw, swfw_mask);
1282
1283 read_byte_out:
1284         return status;
1285 }
1286
1287 /**
1288  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1289  *  @hw: pointer to hardware structure
1290  *  @byte_offset: byte offset to write
1291  *  @data: value to write
1292  *
1293  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1294  *  a specified device address.
1295  **/
1296 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1297                                  u8 dev_addr, u8 data)
1298 {
1299         s32 status = 0;
1300         u32 max_retry = 1;
1301         u32 retry = 0;
1302         u16 swfw_mask = 0;
1303
1304         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1305                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1306         else
1307                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1308
1309         if (ixgbe_acquire_swfw_sync(hw, swfw_mask) != 0) {
1310                 status = IXGBE_ERR_SWFW_SYNC;
1311                 goto write_byte_out;
1312         }
1313
1314         do {
1315                 ixgbe_i2c_start(hw);
1316
1317                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1318                 if (status != 0)
1319                         goto fail;
1320
1321                 status = ixgbe_get_i2c_ack(hw);
1322                 if (status != 0)
1323                         goto fail;
1324
1325                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1326                 if (status != 0)
1327                         goto fail;
1328
1329                 status = ixgbe_get_i2c_ack(hw);
1330                 if (status != 0)
1331                         goto fail;
1332
1333                 status = ixgbe_clock_out_i2c_byte(hw, data);
1334                 if (status != 0)
1335                         goto fail;
1336
1337                 status = ixgbe_get_i2c_ack(hw);
1338                 if (status != 0)
1339                         goto fail;
1340
1341                 ixgbe_i2c_stop(hw);
1342                 break;
1343
1344 fail:
1345                 ixgbe_i2c_bus_clear(hw);
1346                 retry++;
1347                 if (retry < max_retry)
1348                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1349                 else
1350                         hw_dbg(hw, "I2C byte write error.\n");
1351         } while (retry < max_retry);
1352
1353         ixgbe_release_swfw_sync(hw, swfw_mask);
1354
1355 write_byte_out:
1356         return status;
1357 }
1358
1359 /**
1360  *  ixgbe_i2c_start - Sets I2C start condition
1361  *  @hw: pointer to hardware structure
1362  *
1363  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1364  **/
1365 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1366 {
1367         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1368
1369         /* Start condition must begin with data and clock high */
1370         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1371         ixgbe_raise_i2c_clk(hw, &i2cctl);
1372
1373         /* Setup time for start condition (4.7us) */
1374         udelay(IXGBE_I2C_T_SU_STA);
1375
1376         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1377
1378         /* Hold time for start condition (4us) */
1379         udelay(IXGBE_I2C_T_HD_STA);
1380
1381         ixgbe_lower_i2c_clk(hw, &i2cctl);
1382
1383         /* Minimum low period of clock is 4.7 us */
1384         udelay(IXGBE_I2C_T_LOW);
1385
1386 }
1387
1388 /**
1389  *  ixgbe_i2c_stop - Sets I2C stop condition
1390  *  @hw: pointer to hardware structure
1391  *
1392  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1393  **/
1394 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1395 {
1396         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1397
1398         /* Stop condition must begin with data low and clock high */
1399         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1400         ixgbe_raise_i2c_clk(hw, &i2cctl);
1401
1402         /* Setup time for stop condition (4us) */
1403         udelay(IXGBE_I2C_T_SU_STO);
1404
1405         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1406
1407         /* bus free time between stop and start (4.7us)*/
1408         udelay(IXGBE_I2C_T_BUF);
1409 }
1410
1411 /**
1412  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1413  *  @hw: pointer to hardware structure
1414  *  @data: data byte to clock in
1415  *
1416  *  Clocks in one byte data via I2C data/clock
1417  **/
1418 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1419 {
1420         s32 status = 0;
1421         s32 i;
1422         bool bit = 0;
1423
1424         for (i = 7; i >= 0; i--) {
1425                 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1426                 *data |= bit << i;
1427
1428                 if (status != 0)
1429                         break;
1430         }
1431
1432         return status;
1433 }
1434
1435 /**
1436  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1437  *  @hw: pointer to hardware structure
1438  *  @data: data byte clocked out
1439  *
1440  *  Clocks out one byte data via I2C data/clock
1441  **/
1442 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1443 {
1444         s32 status = 0;
1445         s32 i;
1446         u32 i2cctl;
1447         bool bit = 0;
1448
1449         for (i = 7; i >= 0; i--) {
1450                 bit = (data >> i) & 0x1;
1451                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1452
1453                 if (status != 0)
1454                         break;
1455         }
1456
1457         /* Release SDA line (set high) */
1458         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1459         i2cctl |= IXGBE_I2C_DATA_OUT;
1460         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1461
1462         return status;
1463 }
1464
1465 /**
1466  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1467  *  @hw: pointer to hardware structure
1468  *
1469  *  Clocks in/out one bit via I2C data/clock
1470  **/
1471 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1472 {
1473         s32 status;
1474         u32 i = 0;
1475         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1476         u32 timeout = 10;
1477         bool ack = 1;
1478
1479         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1480
1481         if (status != 0)
1482                 goto out;
1483
1484         /* Minimum high period of clock is 4us */
1485         udelay(IXGBE_I2C_T_HIGH);
1486
1487         /* Poll for ACK.  Note that ACK in I2C spec is
1488          * transition from 1 to 0 */
1489         for (i = 0; i < timeout; i++) {
1490                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1491                 ack = ixgbe_get_i2c_data(&i2cctl);
1492
1493                 udelay(1);
1494                 if (ack == 0)
1495                         break;
1496         }
1497
1498         if (ack == 1) {
1499                 hw_dbg(hw, "I2C ack was not received.\n");
1500                 status = IXGBE_ERR_I2C;
1501         }
1502
1503         ixgbe_lower_i2c_clk(hw, &i2cctl);
1504
1505         /* Minimum low period of clock is 4.7 us */
1506         udelay(IXGBE_I2C_T_LOW);
1507
1508 out:
1509         return status;
1510 }
1511
1512 /**
1513  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1514  *  @hw: pointer to hardware structure
1515  *  @data: read data value
1516  *
1517  *  Clocks in one bit via I2C data/clock
1518  **/
1519 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1520 {
1521         s32 status;
1522         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1523
1524         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1525
1526         /* Minimum high period of clock is 4us */
1527         udelay(IXGBE_I2C_T_HIGH);
1528
1529         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1530         *data = ixgbe_get_i2c_data(&i2cctl);
1531
1532         ixgbe_lower_i2c_clk(hw, &i2cctl);
1533
1534         /* Minimum low period of clock is 4.7 us */
1535         udelay(IXGBE_I2C_T_LOW);
1536
1537         return status;
1538 }
1539
1540 /**
1541  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1542  *  @hw: pointer to hardware structure
1543  *  @data: data value to write
1544  *
1545  *  Clocks out one bit via I2C data/clock
1546  **/
1547 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1548 {
1549         s32 status;
1550         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1551
1552         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1553         if (status == 0) {
1554                 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1555
1556                 /* Minimum high period of clock is 4us */
1557                 udelay(IXGBE_I2C_T_HIGH);
1558
1559                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1560
1561                 /* Minimum low period of clock is 4.7 us.
1562                  * This also takes care of the data hold time.
1563                  */
1564                 udelay(IXGBE_I2C_T_LOW);
1565         } else {
1566                 status = IXGBE_ERR_I2C;
1567                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1568         }
1569
1570         return status;
1571 }
1572 /**
1573  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1574  *  @hw: pointer to hardware structure
1575  *  @i2cctl: Current value of I2CCTL register
1576  *
1577  *  Raises the I2C clock line '0'->'1'
1578  **/
1579 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1580 {
1581         s32 status = 0;
1582
1583         *i2cctl |= IXGBE_I2C_CLK_OUT;
1584
1585         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1586
1587         /* SCL rise time (1000ns) */
1588         udelay(IXGBE_I2C_T_RISE);
1589
1590         return status;
1591 }
1592
1593 /**
1594  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1595  *  @hw: pointer to hardware structure
1596  *  @i2cctl: Current value of I2CCTL register
1597  *
1598  *  Lowers the I2C clock line '1'->'0'
1599  **/
1600 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1601 {
1602
1603         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1604
1605         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1606
1607         /* SCL fall time (300ns) */
1608         udelay(IXGBE_I2C_T_FALL);
1609 }
1610
1611 /**
1612  *  ixgbe_set_i2c_data - Sets the I2C data bit
1613  *  @hw: pointer to hardware structure
1614  *  @i2cctl: Current value of I2CCTL register
1615  *  @data: I2C data value (0 or 1) to set
1616  *
1617  *  Sets the I2C data bit
1618  **/
1619 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1620 {
1621         s32 status = 0;
1622
1623         if (data)
1624                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1625         else
1626                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1627
1628         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1629
1630         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1631         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1632
1633         /* Verify data was set correctly */
1634         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1635         if (data != ixgbe_get_i2c_data(i2cctl)) {
1636                 status = IXGBE_ERR_I2C;
1637                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1638         }
1639
1640         return status;
1641 }
1642
1643 /**
1644  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1645  *  @hw: pointer to hardware structure
1646  *  @i2cctl: Current value of I2CCTL register
1647  *
1648  *  Returns the I2C data bit value
1649  **/
1650 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1651 {
1652         bool data;
1653
1654         if (*i2cctl & IXGBE_I2C_DATA_IN)
1655                 data = 1;
1656         else
1657                 data = 0;
1658
1659         return data;
1660 }
1661
1662 /**
1663  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1664  *  @hw: pointer to hardware structure
1665  *
1666  *  Clears the I2C bus by sending nine clock pulses.
1667  *  Used when data line is stuck low.
1668  **/
1669 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1670 {
1671         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1672         u32 i;
1673
1674         ixgbe_i2c_start(hw);
1675
1676         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1677
1678         for (i = 0; i < 9; i++) {
1679                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1680
1681                 /* Min high period of clock is 4us */
1682                 udelay(IXGBE_I2C_T_HIGH);
1683
1684                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1685
1686                 /* Min low period of clock is 4.7us*/
1687                 udelay(IXGBE_I2C_T_LOW);
1688         }
1689
1690         ixgbe_i2c_start(hw);
1691
1692         /* Put the i2c bus back to default state */
1693         ixgbe_i2c_stop(hw);
1694 }
1695
1696 /**
1697  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1698  *  @hw: pointer to hardware structure
1699  *
1700  *  Checks if the LASI temp alarm status was triggered due to overtemp
1701  **/
1702 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1703 {
1704         s32 status = 0;
1705         u16 phy_data = 0;
1706
1707         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1708                 goto out;
1709
1710         /* Check that the LASI temp alarm status was triggered */
1711         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1712                              MDIO_MMD_PMAPMD, &phy_data);
1713
1714         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1715                 goto out;
1716
1717         status = IXGBE_ERR_OVERTEMP;
1718 out:
1719         return status;
1720 }