drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/sctp.h>
  39 #include <linux/pkt_sched.h>
  40 #include <linux/ipv6.h>
  41 #include <linux/slab.h>
  42 #include <net/checksum.h>
  43 #include <net/ip6_checksum.h>
  44 #include <linux/ethtool.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/prefetch.h>
  47 #include <scsi/fc/fc_fcoe.h>
  48
  49 #include "ixgbe.h"
  50 #include "ixgbe_common.h"
  51 #include "ixgbe_dcb_82599.h"
  52 #include "ixgbe_sriov.h"
  53
  54 char ixgbe_driver_name[] = "ixgbe";
  55 static const char ixgbe_driver_string[] =
  56                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  57 #define MAJ 3
  58 #define MIN 4
  59 #define BUILD 8
  60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  61         __stringify(BUILD) "-k"
  62 const char ixgbe_driver_version[] = DRV_VERSION;
  63 static const char ixgbe_copyright[] =
  64                                 "Copyright (c) 1999-2011 Intel Corporation.";
  65
  66 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  67         [board_82598] = &ixgbe_82598_info,
  68         [board_82599] = &ixgbe_82599_info,
  69         [board_X540] = &ixgbe_X540_info,
  70 };
  71
  72 /* ixgbe_pci_tbl - PCI Device ID Table
  73  *
  74  * Wildcard entries (PCI_ANY_ID) should come last
  75  * Last entry must be all 0s
  76  *
  77  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  78  *   Class, Class Mask, private data (not used) }
  79  */
  80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  98          board_82598 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
 100          board_82598 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 102          board_82598 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 104          board_82598 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 114          board_82599 },
 115         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 116          board_82599 },
 117         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 118          board_82599 },
 119         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 120          board_82599 },
 121         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 122          board_82599 },
 123         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 124          board_82599 },
 125         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 126          board_82599 },
 127         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 128          board_X540 },
 129         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 130          board_82599 },
 131         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
 132          board_82599 },
 133
 134         /* required last entry */
 135         {0, }
 136 };
 137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 138
 139 #ifdef CONFIG_IXGBE_DCA
 140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 141                             void *p);
 142 static struct notifier_block dca_notifier = {
 143         .notifier_call = ixgbe_notify_dca,
 144         .next          = NULL,
 145         .priority      = 0
 146 };
 147 #endif
 148
 149 #ifdef CONFIG_PCI_IOV
 150 static unsigned int max_vfs;
 151 module_param(max_vfs, uint, 0);
 152 MODULE_PARM_DESC(max_vfs,
 153                  "Maximum number of virtual functions to allocate per physical function");
 154 #endif /* CONFIG_PCI_IOV */
 155
 156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 158 MODULE_LICENSE("GPL");
 159 MODULE_VERSION(DRV_VERSION);
 160
 161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 162
 163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 164 {
 165         struct ixgbe_hw *hw = &adapter->hw;
 166         u32 gcr;
 167         u32 gpie;
 168         u32 vmdctl;
 169
 170 #ifdef CONFIG_PCI_IOV
 171         /* disable iov and allow time for transactions to clear */
 172         pci_disable_sriov(adapter->pdev);
 173 #endif
 174
 175         /* turn off device IOV mode */
 176         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 177         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 178         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 179         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 180         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 181         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 182
 183         /* set default pool back to 0 */
 184         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 185         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 186         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 187         IXGBE_WRITE_FLUSH(hw);
 188
 189         /* take a breather then clean up driver data */
 190         msleep(100);
 191
 192         kfree(adapter->vfinfo);
 193         adapter->vfinfo = NULL;
 194
 195         adapter->num_vfs = 0;
 196         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 197 }
 198
 199 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 200 {
 201         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 202             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 203                 schedule_work(&adapter->service_task);
 204 }
 205
 206 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 207 {
 208         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 209
 210         /* flush memory to make sure state is correct before next watchog */
 211         smp_mb__before_clear_bit();
 212         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 213 }
 214
 215 struct ixgbe_reg_info {
 216         u32 ofs;
 217         char *name;
 218 };
 219
 220 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 221
 222         /* General Registers */
 223         {IXGBE_CTRL, "CTRL"},
 224         {IXGBE_STATUS, "STATUS"},
 225         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 226
 227         /* Interrupt Registers */
 228         {IXGBE_EICR, "EICR"},
 229
 230         /* RX Registers */
 231         {IXGBE_SRRCTL(0), "SRRCTL"},
 232         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 233         {IXGBE_RDLEN(0), "RDLEN"},
 234         {IXGBE_RDH(0), "RDH"},
 235         {IXGBE_RDT(0), "RDT"},
 236         {IXGBE_RXDCTL(0), "RXDCTL"},
 237         {IXGBE_RDBAL(0), "RDBAL"},
 238         {IXGBE_RDBAH(0), "RDBAH"},
 239
 240         /* TX Registers */
 241         {IXGBE_TDBAL(0), "TDBAL"},
 242         {IXGBE_TDBAH(0), "TDBAH"},
 243         {IXGBE_TDLEN(0), "TDLEN"},
 244         {IXGBE_TDH(0), "TDH"},
 245         {IXGBE_TDT(0), "TDT"},
 246         {IXGBE_TXDCTL(0), "TXDCTL"},
 247
 248         /* List Terminator */
 249         {}
 250 };
 251
 252
 253 /*
 254  * ixgbe_regdump - register printout routine
 255  */
 256 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 257 {
 258         int i = 0, j = 0;
 259         char rname[16];
 260         u32 regs[64];
 261
 262         switch (reginfo->ofs) {
 263         case IXGBE_SRRCTL(0):
 264                 for (i = 0; i < 64; i++)
 265                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 266                 break;
 267         case IXGBE_DCA_RXCTRL(0):
 268                 for (i = 0; i < 64; i++)
 269                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 270                 break;
 271         case IXGBE_RDLEN(0):
 272                 for (i = 0; i < 64; i++)
 273                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 274                 break;
 275         case IXGBE_RDH(0):
 276                 for (i = 0; i < 64; i++)
 277                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 278                 break;
 279         case IXGBE_RDT(0):
 280                 for (i = 0; i < 64; i++)
 281                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 282                 break;
 283         case IXGBE_RXDCTL(0):
 284                 for (i = 0; i < 64; i++)
 285                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 286                 break;
 287         case IXGBE_RDBAL(0):
 288                 for (i = 0; i < 64; i++)
 289                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 290                 break;
 291         case IXGBE_RDBAH(0):
 292                 for (i = 0; i < 64; i++)
 293                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 294                 break;
 295         case IXGBE_TDBAL(0):
 296                 for (i = 0; i < 64; i++)
 297                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 298                 break;
 299         case IXGBE_TDBAH(0):
 300                 for (i = 0; i < 64; i++)
 301                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 302                 break;
 303         case IXGBE_TDLEN(0):
 304                 for (i = 0; i < 64; i++)
 305                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 306                 break;
 307         case IXGBE_TDH(0):
 308                 for (i = 0; i < 64; i++)
 309                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 310                 break;
 311         case IXGBE_TDT(0):
 312                 for (i = 0; i < 64; i++)
 313                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 314                 break;
 315         case IXGBE_TXDCTL(0):
 316                 for (i = 0; i < 64; i++)
 317                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 318                 break;
 319         default:
 320                 pr_info("%-15s %08x\n", reginfo->name,
 321                         IXGBE_READ_REG(hw, reginfo->ofs));
 322                 return;
 323         }
 324
 325         for (i = 0; i < 8; i++) {
 326                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 327                 pr_err("%-15s", rname);
 328                 for (j = 0; j < 8; j++)
 329                         pr_cont(" %08x", regs[i*8+j]);
 330                 pr_cont("\n");
 331         }
 332
 333 }
 334
 335 /*
 336  * ixgbe_dump - Print registers, tx-rings and rx-rings
 337  */
 338 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 339 {
 340         struct net_device *netdev = adapter->netdev;
 341         struct ixgbe_hw *hw = &adapter->hw;
 342         struct ixgbe_reg_info *reginfo;
 343         int n = 0;
 344         struct ixgbe_ring *tx_ring;
 345         struct ixgbe_tx_buffer *tx_buffer_info;
 346         union ixgbe_adv_tx_desc *tx_desc;
 347         struct my_u0 { u64 a; u64 b; } *u0;
 348         struct ixgbe_ring *rx_ring;
 349         union ixgbe_adv_rx_desc *rx_desc;
 350         struct ixgbe_rx_buffer *rx_buffer_info;
 351         u32 staterr;
 352         int i = 0;
 353
 354         if (!netif_msg_hw(adapter))
 355                 return;
 356
 357         /* Print netdevice Info */
 358         if (netdev) {
 359                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 360                 pr_info("Device Name     state            "
 361                         "trans_start      last_rx\n");
 362                 pr_info("%-15s %016lX %016lX %016lX\n",
 363                         netdev->name,
 364                         netdev->state,
 365                         netdev->trans_start,
 366                         netdev->last_rx);
 367         }
 368
 369         /* Print Registers */
 370         dev_info(&adapter->pdev->dev, "Register Dump\n");
 371         pr_info(" Register Name   Value\n");
 372         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 373              reginfo->name; reginfo++) {
 374                 ixgbe_regdump(hw, reginfo);
 375         }
 376
 377         /* Print TX Ring Summary */
 378         if (!netdev || !netif_running(netdev))
 379                 goto exit;
 380
 381         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 382         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 383         for (n = 0; n < adapter->num_tx_queues; n++) {
 384                 tx_ring = adapter->tx_ring[n];
 385                 tx_buffer_info =
 386                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 387                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 388                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 389                            (u64)tx_buffer_info->dma,
 390                            tx_buffer_info->length,
 391                            tx_buffer_info->next_to_watch,
 392                            (u64)tx_buffer_info->time_stamp);
 393         }
 394
 395         /* Print TX Rings */
 396         if (!netif_msg_tx_done(adapter))
 397                 goto rx_ring_summary;
 398
 399         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 400
 401         /* Transmit Descriptor Formats
 402          *
 403          * Advanced Transmit Descriptor
 404          *   +--------------------------------------------------------------+
 405          * 0 |         Buffer Address [63:0]                                |
 406          *   +--------------------------------------------------------------+
 407          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 408          *   +--------------------------------------------------------------+
 409          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 410          */
 411
 412         for (n = 0; n < adapter->num_tx_queues; n++) {
 413                 tx_ring = adapter->tx_ring[n];
 414                 pr_info("------------------------------------\n");
 415                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 416                 pr_info("------------------------------------\n");
 417                 pr_info("T [desc]     [address 63:0  ] "
 418                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 419                         "leng  ntw timestamp        bi->skb\n");
 420
 421                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 422                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 423                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 424                         u0 = (struct my_u0 *)tx_desc;
 425                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 426                                 " %04X  %3X %016llX %p", i,
 427                                 le64_to_cpu(u0->a),
 428                                 le64_to_cpu(u0->b),
 429                                 (u64)tx_buffer_info->dma,
 430                                 tx_buffer_info->length,
 431                                 tx_buffer_info->next_to_watch,
 432                                 (u64)tx_buffer_info->time_stamp,
 433                                 tx_buffer_info->skb);
 434                         if (i == tx_ring->next_to_use &&
 435                                 i == tx_ring->next_to_clean)
 436                                 pr_cont(" NTC/U\n");
 437                         else if (i == tx_ring->next_to_use)
 438                                 pr_cont(" NTU\n");
 439                         else if (i == tx_ring->next_to_clean)
 440                                 pr_cont(" NTC\n");
 441                         else
 442                                 pr_cont("\n");
 443
 444                         if (netif_msg_pktdata(adapter) &&
 445                                 tx_buffer_info->dma != 0)
 446                                 print_hex_dump(KERN_INFO, "",
 447                                         DUMP_PREFIX_ADDRESS, 16, 1,
 448                                         phys_to_virt(tx_buffer_info->dma),
 449                                         tx_buffer_info->length, true);
 450                 }
 451         }
 452
 453         /* Print RX Rings Summary */
 454 rx_ring_summary:
 455         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 456         pr_info("Queue [NTU] [NTC]\n");
 457         for (n = 0; n < adapter->num_rx_queues; n++) {
 458                 rx_ring = adapter->rx_ring[n];
 459                 pr_info("%5d %5X %5X\n",
 460                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 461         }
 462
 463         /* Print RX Rings */
 464         if (!netif_msg_rx_status(adapter))
 465                 goto exit;
 466
 467         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 468
 469         /* Advanced Receive Descriptor (Read) Format
 470          *    63                                           1        0
 471          *    +-----------------------------------------------------+
 472          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 473          *    +----------------------------------------------+------+
 474          *  8 |       Header Buffer Address [63:1]           |  DD  |
 475          *    +-----------------------------------------------------+
 476          *
 477          *
 478          * Advanced Receive Descriptor (Write-Back) Format
 479          *
 480          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 481          *   +------------------------------------------------------+
 482          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 483          *   | Checksum   Ident  |   |           |    | Type | Type |
 484          *   +------------------------------------------------------+
 485          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 486          *   +------------------------------------------------------+
 487          *   63       48 47    32 31            20 19               0
 488          */
 489         for (n = 0; n < adapter->num_rx_queues; n++) {
 490                 rx_ring = adapter->rx_ring[n];
 491                 pr_info("------------------------------------\n");
 492                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 493                 pr_info("------------------------------------\n");
 494                 pr_info("R  [desc]      [ PktBuf     A0] "
 495                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 496                         "<-- Adv Rx Read format\n");
 497                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 498                         "[vl er S cks ln] ---------------- [bi->skb] "
 499                         "<-- Adv Rx Write-Back format\n");
 500
 501                 for (i = 0; i < rx_ring->count; i++) {
 502                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 503                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 504                         u0 = (struct my_u0 *)rx_desc;
 505                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 506                         if (staterr & IXGBE_RXD_STAT_DD) {
 507                                 /* Descriptor Done */
 508                                 pr_info("RWB[0x%03X]     %016llX "
 509                                         "%016llX ---------------- %p", i,
 510                                         le64_to_cpu(u0->a),
 511                                         le64_to_cpu(u0->b),
 512                                         rx_buffer_info->skb);
 513                         } else {
 514                                 pr_info("R  [0x%03X]     %016llX "
 515                                         "%016llX %016llX %p", i,
 516                                         le64_to_cpu(u0->a),
 517                                         le64_to_cpu(u0->b),
 518                                         (u64)rx_buffer_info->dma,
 519                                         rx_buffer_info->skb);
 520
 521                                 if (netif_msg_pktdata(adapter)) {
 522                                         print_hex_dump(KERN_INFO, "",
 523                                            DUMP_PREFIX_ADDRESS, 16, 1,
 524                                            phys_to_virt(rx_buffer_info->dma),
 525                                            rx_ring->rx_buf_len, true);
 526
 527                                         if (rx_ring->rx_buf_len
 528                                                 < IXGBE_RXBUFFER_2048)
 529                                                 print_hex_dump(KERN_INFO, "",
 530                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 531                                                   phys_to_virt(
 532                                                     rx_buffer_info->page_dma +
 533                                                     rx_buffer_info->page_offset
 534                                                   ),
 535                                                   PAGE_SIZE/2, true);
 536                                 }
 537                         }
 538
 539                         if (i == rx_ring->next_to_use)
 540                                 pr_cont(" NTU\n");
 541                         else if (i == rx_ring->next_to_clean)
 542                                 pr_cont(" NTC\n");
 543                         else
 544                                 pr_cont("\n");
 545
 546                 }
 547         }
 548
 549 exit:
 550         return;
 551 }
 552
 553 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 554 {
 555         u32 ctrl_ext;
 556
 557         /* Let firmware take over control of h/w */
 558         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 559         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 560                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 561 }
 562
 563 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 564 {
 565         u32 ctrl_ext;
 566
 567         /* Let firmware know the driver has taken over */
 568         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 569         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 570                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 571 }
 572
 573 /*
 574  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 575  * @adapter: pointer to adapter struct
 576  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 577  * @queue: queue to map the corresponding interrupt to
 578  * @msix_vector: the vector to map to the corresponding queue
 579  *
 580  */
 581 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 582                            u8 queue, u8 msix_vector)
 583 {
 584         u32 ivar, index;
 585         struct ixgbe_hw *hw = &adapter->hw;
 586         switch (hw->mac.type) {
 587         case ixgbe_mac_82598EB:
 588                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 589                 if (direction == -1)
 590                         direction = 0;
 591                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 592                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 593                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 594                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 595                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 596                 break;
 597         case ixgbe_mac_82599EB:
 598         case ixgbe_mac_X540:
 599                 if (direction == -1) {
 600                         /* other causes */
 601                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 602                         index = ((queue & 1) * 8);
 603                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 604                         ivar &= ~(0xFF << index);
 605                         ivar |= (msix_vector << index);
 606                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 607                         break;
 608                 } else {
 609                         /* tx or rx causes */
 610                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 611                         index = ((16 * (queue & 1)) + (8 * direction));
 612                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 613                         ivar &= ~(0xFF << index);
 614                         ivar |= (msix_vector << index);
 615                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 616                         break;
 617                 }
 618         default:
 619                 break;
 620         }
 621 }
 622
 623 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 624                                           u64 qmask)
 625 {
 626         u32 mask;
 627
 628         switch (adapter->hw.mac.type) {
 629         case ixgbe_mac_82598EB:
 630                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 631                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 632                 break;
 633         case ixgbe_mac_82599EB:
 634         case ixgbe_mac_X540:
 635                 mask = (qmask & 0xFFFFFFFF);
 636                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 637                 mask = (qmask >> 32);
 638                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 639                 break;
 640         default:
 641                 break;
 642         }
 643 }
 644
 645 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 646                                       struct ixgbe_tx_buffer *tx_buffer_info)
 647 {
 648         if (tx_buffer_info->dma) {
 649                 if (tx_buffer_info->mapped_as_page)
 650                         dma_unmap_page(tx_ring->dev,
 651                                        tx_buffer_info->dma,
 652                                        tx_buffer_info->length,
 653                                        DMA_TO_DEVICE);
 654                 else
 655                         dma_unmap_single(tx_ring->dev,
 656                                          tx_buffer_info->dma,
 657                                          tx_buffer_info->length,
 658                                          DMA_TO_DEVICE);
 659                 tx_buffer_info->dma = 0;
 660         }
 661         if (tx_buffer_info->skb) {
 662                 dev_kfree_skb_any(tx_buffer_info->skb);
 663                 tx_buffer_info->skb = NULL;
 664         }
 665         tx_buffer_info->time_stamp = 0;
 666         /* tx_buffer_info must be completely set up in the transmit path */
 667 }
 668
 669 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 670 {
 671         struct ixgbe_hw *hw = &adapter->hw;
 672         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 673         u32 data = 0;
 674         u32 xoff[8] = {0};
 675         int i;
 676
 677         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 678             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 679                 switch (hw->mac.type) {
 680                 case ixgbe_mac_82598EB:
 681                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 682                         break;
 683                 default:
 684                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 685                 }
 686                 hwstats->lxoffrxc += data;
 687
 688                 /* refill credits (no tx hang) if we received xoff */
 689                 if (!data)
 690                         return;
 691
 692                 for (i = 0; i < adapter->num_tx_queues; i++)
 693                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 694                                   &adapter->tx_ring[i]->state);
 695                 return;
 696         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 697                 return;
 698
 699         /* update stats for each tc, only valid with PFC enabled */
 700         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 701                 switch (hw->mac.type) {
 702                 case ixgbe_mac_82598EB:
 703                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 704                         break;
 705                 default:
 706                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 707                 }
 708                 hwstats->pxoffrxc[i] += xoff[i];
 709         }
 710
 711         /* disarm tx queues that have received xoff frames */
 712         for (i = 0; i < adapter->num_tx_queues; i++) {
 713                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 714                 u8 tc = tx_ring->dcb_tc;
 715
 716                 if (xoff[tc])
 717                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 718         }
 719 }
 720
 721 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 722 {
 723         return ring->tx_stats.completed;
 724 }
 725
 726 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 727 {
 728         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 729         struct ixgbe_hw *hw = &adapter->hw;
 730
 731         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 732         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 733
 734         if (head != tail)
 735                 return (head < tail) ?
 736                         tail - head : (tail + ring->count - head);
 737
 738         return 0;
 739 }
 740
 741 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 742 {
 743         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 744         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 745         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 746         bool ret = false;
 747
 748         clear_check_for_tx_hang(tx_ring);
 749
 750         /*
 751          * Check for a hung queue, but be thorough. This verifies
 752          * that a transmit has been completed since the previous
 753          * check AND there is at least one packet pending. The
 754          * ARMED bit is set to indicate a potential hang. The
 755          * bit is cleared if a pause frame is received to remove
 756          * false hang detection due to PFC or 802.3x frames. By
 757          * requiring this to fail twice we avoid races with
 758          * pfc clearing the ARMED bit and conditions where we
 759          * run the check_tx_hang logic with a transmit completion
 760          * pending but without time to complete it yet.
 761          */
 762         if ((tx_done_old == tx_done) && tx_pending) {
 763                 /* make sure it is true for two checks in a row */
 764                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 765                                        &tx_ring->state);
 766         } else {
 767                 /* update completed stats and continue */
 768                 tx_ring->tx_stats.tx_done_old = tx_done;
 769                 /* reset the countdown */
 770                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 771         }
 772
 773         return ret;
 774 }
 775
 776 /**
 777  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 778  * @adapter: driver private struct
 779  **/
 780 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 781 {
 782
 783         /* Do the reset outside of interrupt context */
 784         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 785                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 786                 ixgbe_service_event_schedule(adapter);
 787         }
 788 }
 789
 790 /**
 791  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 792  * @q_vector: structure containing interrupt and ring information
 793  * @tx_ring: tx ring to clean
 794  **/
 795 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 796                                struct ixgbe_ring *tx_ring)
 797 {
 798         struct ixgbe_adapter *adapter = q_vector->adapter;
 799         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 800         struct ixgbe_tx_buffer *tx_buffer_info;
 801         unsigned int total_bytes = 0, total_packets = 0;
 802         u16 i, eop, count = 0;
 803
 804         i = tx_ring->next_to_clean;
 805         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 806         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 807
 808         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 809                (count < q_vector->tx.work_limit)) {
 810                 bool cleaned = false;
 811                 rmb(); /* read buffer_info after eop_desc */
 812                 for ( ; !cleaned; count++) {
 813                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 814                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 815
 816                         tx_desc->wb.status = 0;
 817                         cleaned = (i == eop);
 818
 819                         i++;
 820                         if (i == tx_ring->count)
 821                                 i = 0;
 822
 823                         if (cleaned && tx_buffer_info->skb) {
 824                                 total_bytes += tx_buffer_info->bytecount;
 825                                 total_packets += tx_buffer_info->gso_segs;
 826                         }
 827
 828                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 829                                                          tx_buffer_info);
 830                 }
 831
 832                 tx_ring->tx_stats.completed++;
 833                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 834                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 835         }
 836
 837         tx_ring->next_to_clean = i;
 838         tx_ring->stats.bytes += total_bytes;
 839         tx_ring->stats.packets += total_packets;
 840         u64_stats_update_begin(&tx_ring->syncp);
 841         q_vector->tx.total_bytes += total_bytes;
 842         q_vector->tx.total_packets += total_packets;
 843         u64_stats_update_end(&tx_ring->syncp);
 844
 845         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 846                 /* schedule immediate reset if we believe we hung */
 847                 struct ixgbe_hw *hw = &adapter->hw;
 848                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 849                 e_err(drv, "Detected Tx Unit Hang\n"
 850                         "  Tx Queue             <%d>\n"
 851                         "  TDH, TDT             <%x>, <%x>\n"
 852                         "  next_to_use          <%x>\n"
 853                         "  next_to_clean        <%x>\n"
 854                         "tx_buffer_info[next_to_clean]\n"
 855                         "  time_stamp           <%lx>\n"
 856                         "  jiffies              <%lx>\n",
 857                         tx_ring->queue_index,
 858                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 859                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 860                         tx_ring->next_to_use, eop,
 861                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 862
 863                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 864
 865                 e_info(probe,
 866                        "tx hang %d detected on queue %d, resetting adapter\n",
 867                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 868
 869                 /* schedule immediate reset if we believe we hung */
 870                 ixgbe_tx_timeout_reset(adapter);
 871
 872                 /* the adapter is about to reset, no point in enabling stuff */
 873                 return true;
 874         }
 875
 876 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 877         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 878                      (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
 879                 /* Make sure that anybody stopping the queue after this
 880                  * sees the new next_to_clean.
 881                  */
 882                 smp_mb();
 883                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 884                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 885                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 886                         ++tx_ring->tx_stats.restart_queue;
 887                 }
 888         }
 889
 890         return count < q_vector->tx.work_limit;
 891 }
 892
 893 #ifdef CONFIG_IXGBE_DCA
 894 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 895                                 struct ixgbe_ring *rx_ring,
 896                                 int cpu)
 897 {
 898         struct ixgbe_hw *hw = &adapter->hw;
 899         u32 rxctrl;
 900         u8 reg_idx = rx_ring->reg_idx;
 901
 902         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 903         switch (hw->mac.type) {
 904         case ixgbe_mac_82598EB:
 905                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 906                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 907                 break;
 908         case ixgbe_mac_82599EB:
 909         case ixgbe_mac_X540:
 910                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 911                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 912                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 913                 break;
 914         default:
 915                 break;
 916         }
 917         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 918         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 919         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 920         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 921 }
 922
 923 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 924                                 struct ixgbe_ring *tx_ring,
 925                                 int cpu)
 926 {
 927         struct ixgbe_hw *hw = &adapter->hw;
 928         u32 txctrl;
 929         u8 reg_idx = tx_ring->reg_idx;
 930
 931         switch (hw->mac.type) {
 932         case ixgbe_mac_82598EB:
 933                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 934                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 935                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 936                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 937                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 938                 break;
 939         case ixgbe_mac_82599EB:
 940         case ixgbe_mac_X540:
 941                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 942                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 943                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 944                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 945                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 946                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 947                 break;
 948         default:
 949                 break;
 950         }
 951 }
 952
 953 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 954 {
 955         struct ixgbe_adapter *adapter = q_vector->adapter;
 956         int cpu = get_cpu();
 957         long r_idx;
 958         int i;
 959
 960         if (q_vector->cpu == cpu)
 961                 goto out_no_update;
 962
 963         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
 964         for (i = 0; i < q_vector->tx.count; i++) {
 965                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 966                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
 967                                       r_idx + 1);
 968         }
 969
 970         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
 971         for (i = 0; i < q_vector->rx.count; i++) {
 972                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 973                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
 974                                       r_idx + 1);
 975         }
 976
 977         q_vector->cpu = cpu;
 978 out_no_update:
 979         put_cpu();
 980 }
 981
 982 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 983 {
 984         int num_q_vectors;
 985         int i;
 986
 987         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 988                 return;
 989
 990         /* always use CB2 mode, difference is masked in the CB driver */
 991         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 992
 993         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 994                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 995         else
 996                 num_q_vectors = 1;
 997
 998         for (i = 0; i < num_q_vectors; i++) {
 999                 adapter->q_vector[i]->cpu = -1;
1000                 ixgbe_update_dca(adapter->q_vector[i]);
1001         }
1002 }
1003
1004 static int __ixgbe_notify_dca(struct device *dev, void *data)
1005 {
1006         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1007         unsigned long event = *(unsigned long *)data;
1008
1009         if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1010                 return 0;
1011
1012         switch (event) {
1013         case DCA_PROVIDER_ADD:
1014                 /* if we're already enabled, don't do it again */
1015                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1016                         break;
1017                 if (dca_add_requester(dev) == 0) {
1018                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1019                         ixgbe_setup_dca(adapter);
1020                         break;
1021                 }
1022                 /* Fall Through since DCA is disabled. */
1023         case DCA_PROVIDER_REMOVE:
1024                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1025                         dca_remove_requester(dev);
1026                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1027                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1028                 }
1029                 break;
1030         }
1031
1032         return 0;
1033 }
1034 #endif /* CONFIG_IXGBE_DCA */
1035
1036 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1037                                  struct sk_buff *skb)
1038 {
1039         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1040 }
1041
1042 /**
1043  * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1044  * @adapter: address of board private structure
1045  * @rx_desc: advanced rx descriptor
1046  *
1047  * Returns : true if it is FCoE pkt
1048  */
1049 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1050                                     union ixgbe_adv_rx_desc *rx_desc)
1051 {
1052         __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1053
1054         return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1055                ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1056                 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1057                              IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1058 }
1059
1060 /**
1061  * ixgbe_receive_skb - Send a completed packet up the stack
1062  * @adapter: board private structure
1063  * @skb: packet to send up
1064  * @status: hardware indication of status of receive
1065  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1066  * @rx_desc: rx descriptor
1067  **/
1068 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1069                               struct sk_buff *skb, u8 status,
1070                               struct ixgbe_ring *ring,
1071                               union ixgbe_adv_rx_desc *rx_desc)
1072 {
1073         struct ixgbe_adapter *adapter = q_vector->adapter;
1074         struct napi_struct *napi = &q_vector->napi;
1075         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1076         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1077
1078         if (is_vlan && (tag & VLAN_VID_MASK))
1079                 __vlan_hwaccel_put_tag(skb, tag);
1080
1081         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1082                 napi_gro_receive(napi, skb);
1083         else
1084                 netif_rx(skb);
1085 }
1086
1087 /**
1088  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1089  * @adapter: address of board private structure
1090  * @status_err: hardware indication of status of receive
1091  * @skb: skb currently being received and modified
1092  * @status_err: status error value of last descriptor in packet
1093  **/
1094 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1095                                      union ixgbe_adv_rx_desc *rx_desc,
1096                                      struct sk_buff *skb,
1097                                      u32 status_err)
1098 {
1099         skb->ip_summed = CHECKSUM_NONE;
1100
1101         /* Rx csum disabled */
1102         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1103                 return;
1104
1105         /* if IP and error */
1106         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1107             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1108                 adapter->hw_csum_rx_error++;
1109                 return;
1110         }
1111
1112         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1113                 return;
1114
1115         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1116                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1117
1118                 /*
1119                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1120                  * checksum errors.
1121                  */
1122                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1123                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1124                         return;
1125
1126                 adapter->hw_csum_rx_error++;
1127                 return;
1128         }
1129
1130         /* It must be a TCP or UDP packet with a valid checksum */
1131         skb->ip_summed = CHECKSUM_UNNECESSARY;
1132 }
1133
1134 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1135 {
1136         /*
1137          * Force memory writes to complete before letting h/w
1138          * know there are new descriptors to fetch.  (Only
1139          * applicable for weak-ordered memory model archs,
1140          * such as IA-64).
1141          */
1142         wmb();
1143         writel(val, rx_ring->tail);
1144 }
1145
1146 /**
1147  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1148  * @rx_ring: ring to place buffers on
1149  * @cleaned_count: number of buffers to replace
1150  **/
1151 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1152 {
1153         union ixgbe_adv_rx_desc *rx_desc;
1154         struct ixgbe_rx_buffer *bi;
1155         struct sk_buff *skb;
1156         u16 i = rx_ring->next_to_use;
1157
1158         /* do nothing if no valid netdev defined */
1159         if (!rx_ring->netdev)
1160                 return;
1161
1162         while (cleaned_count--) {
1163                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1164                 bi = &rx_ring->rx_buffer_info[i];
1165                 skb = bi->skb;
1166
1167                 if (!skb) {
1168                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1169                                                         rx_ring->rx_buf_len);
1170                         if (!skb) {
1171                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1172                                 goto no_buffers;
1173                         }
1174                         /* initialize queue mapping */
1175                         skb_record_rx_queue(skb, rx_ring->queue_index);
1176                         bi->skb = skb;
1177                 }
1178
1179                 if (!bi->dma) {
1180                         bi->dma = dma_map_single(rx_ring->dev,
1181                                                  skb->data,
1182                                                  rx_ring->rx_buf_len,
1183                                                  DMA_FROM_DEVICE);
1184                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1185                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1186                                 bi->dma = 0;
1187                                 goto no_buffers;
1188                         }
1189                 }
1190
1191                 if (ring_is_ps_enabled(rx_ring)) {
1192                         if (!bi->page) {
1193                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1194                                 if (!bi->page) {
1195                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1196                                         goto no_buffers;
1197                                 }
1198                         }
1199
1200                         if (!bi->page_dma) {
1201                                 /* use a half page if we're re-using */
1202                                 bi->page_offset ^= PAGE_SIZE / 2;
1203                                 bi->page_dma = dma_map_page(rx_ring->dev,
1204                                                             bi->page,
1205                                                             bi->page_offset,
1206                                                             PAGE_SIZE / 2,
1207                                                             DMA_FROM_DEVICE);
1208                                 if (dma_mapping_error(rx_ring->dev,
1209                                                       bi->page_dma)) {
1210                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1211                                         bi->page_dma = 0;
1212                                         goto no_buffers;
1213                                 }
1214                         }
1215
1216                         /* Refresh the desc even if buffer_addrs didn't change
1217                          * because each write-back erases this info. */
1218                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1219                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1220                 } else {
1221                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1222                         rx_desc->read.hdr_addr = 0;
1223                 }
1224
1225                 i++;
1226                 if (i == rx_ring->count)
1227                         i = 0;
1228         }
1229
1230 no_buffers:
1231         if (rx_ring->next_to_use != i) {
1232                 rx_ring->next_to_use = i;
1233                 ixgbe_release_rx_desc(rx_ring, i);
1234         }
1235 }
1236
1237 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1238 {
1239         /* HW will not DMA in data larger than the given buffer, even if it
1240          * parses the (NFS, of course) header to be larger.  In that case, it
1241          * fills the header buffer and spills the rest into the page.
1242          */
1243         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1244         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1245                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1246         if (hlen > IXGBE_RX_HDR_SIZE)
1247                 hlen = IXGBE_RX_HDR_SIZE;
1248         return hlen;
1249 }
1250
1251 /**
1252  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1253  * @skb: pointer to the last skb in the rsc queue
1254  *
1255  * This function changes a queue full of hw rsc buffers into a completed
1256  * packet.  It uses the ->prev pointers to find the first packet and then
1257  * turns it into the frag list owner.
1258  **/
1259 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1260 {
1261         unsigned int frag_list_size = 0;
1262         unsigned int skb_cnt = 1;
1263
1264         while (skb->prev) {
1265                 struct sk_buff *prev = skb->prev;
1266                 frag_list_size += skb->len;
1267                 skb->prev = NULL;
1268                 skb = prev;
1269                 skb_cnt++;
1270         }
1271
1272         skb_shinfo(skb)->frag_list = skb->next;
1273         skb->next = NULL;
1274         skb->len += frag_list_size;
1275         skb->data_len += frag_list_size;
1276         skb->truesize += frag_list_size;
1277         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1278
1279         return skb;
1280 }
1281
1282 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1283 {
1284         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1285                 IXGBE_RXDADV_RSCCNT_MASK);
1286 }
1287
1288 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1289                                struct ixgbe_ring *rx_ring,
1290                                int *work_done, int work_to_do)
1291 {
1292         struct ixgbe_adapter *adapter = q_vector->adapter;
1293         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1294         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1295         struct sk_buff *skb;
1296         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1297         const int current_node = numa_node_id();
1298 #ifdef IXGBE_FCOE
1299         int ddp_bytes = 0;
1300 #endif /* IXGBE_FCOE */
1301         u32 staterr;
1302         u16 i;
1303         u16 cleaned_count = 0;
1304         bool pkt_is_rsc = false;
1305
1306         i = rx_ring->next_to_clean;
1307         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1308         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1309
1310         while (staterr & IXGBE_RXD_STAT_DD) {
1311                 u32 upper_len = 0;
1312
1313                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1314
1315                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1316
1317                 skb = rx_buffer_info->skb;
1318                 rx_buffer_info->skb = NULL;
1319                 prefetch(skb->data);
1320
1321                 if (ring_is_rsc_enabled(rx_ring))
1322                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1323
1324                 /* linear means we are building an skb from multiple pages */
1325                 if (!skb_is_nonlinear(skb)) {
1326                         u16 hlen;
1327                         if (pkt_is_rsc &&
1328                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1329                             !skb->prev) {
1330                                 /*
1331                                  * When HWRSC is enabled, delay unmapping
1332                                  * of the first packet. It carries the
1333                                  * header information, HW may still
1334                                  * access the header after the writeback.
1335                                  * Only unmap it when EOP is reached
1336                                  */
1337                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1338                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1339                         } else {
1340                                 dma_unmap_single(rx_ring->dev,
1341                                                  rx_buffer_info->dma,
1342                                                  rx_ring->rx_buf_len,
1343                                                  DMA_FROM_DEVICE);
1344                         }
1345                         rx_buffer_info->dma = 0;
1346
1347                         if (ring_is_ps_enabled(rx_ring)) {
1348                                 hlen = ixgbe_get_hlen(rx_desc);
1349                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1350                         } else {
1351                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1352                         }
1353
1354                         skb_put(skb, hlen);
1355                 } else {
1356                         /* assume packet split since header is unmapped */
1357                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1358                 }
1359
1360                 if (upper_len) {
1361                         dma_unmap_page(rx_ring->dev,
1362                                        rx_buffer_info->page_dma,
1363                                        PAGE_SIZE / 2,
1364                                        DMA_FROM_DEVICE);
1365                         rx_buffer_info->page_dma = 0;
1366                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1367                                            rx_buffer_info->page,
1368                                            rx_buffer_info->page_offset,
1369                                            upper_len);
1370
1371                         if ((page_count(rx_buffer_info->page) == 1) &&
1372                             (page_to_nid(rx_buffer_info->page) == current_node))
1373                                 get_page(rx_buffer_info->page);
1374                         else
1375                                 rx_buffer_info->page = NULL;
1376
1377                         skb->len += upper_len;
1378                         skb->data_len += upper_len;
1379                         skb->truesize += upper_len;
1380                 }
1381
1382                 i++;
1383                 if (i == rx_ring->count)
1384                         i = 0;
1385
1386                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1387                 prefetch(next_rxd);
1388                 cleaned_count++;
1389
1390                 if (pkt_is_rsc) {
1391                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1392                                      IXGBE_RXDADV_NEXTP_SHIFT;
1393                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1394                 } else {
1395                         next_buffer = &rx_ring->rx_buffer_info[i];
1396                 }
1397
1398                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1399                         if (ring_is_ps_enabled(rx_ring)) {
1400                                 rx_buffer_info->skb = next_buffer->skb;
1401                                 rx_buffer_info->dma = next_buffer->dma;
1402                                 next_buffer->skb = skb;
1403                                 next_buffer->dma = 0;
1404                         } else {
1405                                 skb->next = next_buffer->skb;
1406                                 skb->next->prev = skb;
1407                         }
1408                         rx_ring->rx_stats.non_eop_descs++;
1409                         goto next_desc;
1410                 }
1411
1412                 if (skb->prev) {
1413                         skb = ixgbe_transform_rsc_queue(skb);
1414                         /* if we got here without RSC the packet is invalid */
1415                         if (!pkt_is_rsc) {
1416                                 __pskb_trim(skb, 0);
1417                                 rx_buffer_info->skb = skb;
1418                                 goto next_desc;
1419                         }
1420                 }
1421
1422                 if (ring_is_rsc_enabled(rx_ring)) {
1423                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1424                                 dma_unmap_single(rx_ring->dev,
1425                                                  IXGBE_RSC_CB(skb)->dma,
1426                                                  rx_ring->rx_buf_len,
1427                                                  DMA_FROM_DEVICE);
1428                                 IXGBE_RSC_CB(skb)->dma = 0;
1429                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1430                         }
1431                 }
1432                 if (pkt_is_rsc) {
1433                         if (ring_is_ps_enabled(rx_ring))
1434                                 rx_ring->rx_stats.rsc_count +=
1435                                         skb_shinfo(skb)->nr_frags;
1436                         else
1437                                 rx_ring->rx_stats.rsc_count +=
1438                                         IXGBE_RSC_CB(skb)->skb_cnt;
1439                         rx_ring->rx_stats.rsc_flush++;
1440                 }
1441
1442                 /* ERR_MASK will only have valid bits if EOP set */
1443                 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1444                         dev_kfree_skb_any(skb);
1445                         goto next_desc;
1446                 }
1447
1448                 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1449                 if (adapter->netdev->features & NETIF_F_RXHASH)
1450                         ixgbe_rx_hash(rx_desc, skb);
1451
1452                 /* probably a little skewed due to removing CRC */
1453                 total_rx_bytes += skb->len;
1454                 total_rx_packets++;
1455
1456                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1457 #ifdef IXGBE_FCOE
1458                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1459                 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1460                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1461                                                    staterr);
1462                         if (!ddp_bytes) {
1463                                 dev_kfree_skb_any(skb);
1464                                 goto next_desc;
1465                         }
1466                 }
1467 #endif /* IXGBE_FCOE */
1468                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1469
1470 next_desc:
1471                 rx_desc->wb.upper.status_error = 0;
1472
1473                 (*work_done)++;
1474                 if (*work_done >= work_to_do)
1475                         break;
1476
1477                 /* return some buffers to hardware, one at a time is too slow */
1478                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1479                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1480                         cleaned_count = 0;
1481                 }
1482
1483                 /* use prefetched values */
1484                 rx_desc = next_rxd;
1485                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1486         }
1487
1488         rx_ring->next_to_clean = i;
1489         cleaned_count = ixgbe_desc_unused(rx_ring);
1490
1491         if (cleaned_count)
1492                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1493
1494 #ifdef IXGBE_FCOE
1495         /* include DDPed FCoE data */
1496         if (ddp_bytes > 0) {
1497                 unsigned int mss;
1498
1499                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1500                         sizeof(struct fc_frame_header) -
1501                         sizeof(struct fcoe_crc_eof);
1502                 if (mss > 512)
1503                         mss &= ~511;
1504                 total_rx_bytes += ddp_bytes;
1505                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1506         }
1507 #endif /* IXGBE_FCOE */
1508
1509         u64_stats_update_begin(&rx_ring->syncp);
1510         rx_ring->stats.packets += total_rx_packets;
1511         rx_ring->stats.bytes += total_rx_bytes;
1512         u64_stats_update_end(&rx_ring->syncp);
1513         q_vector->rx.total_packets += total_rx_packets;
1514         q_vector->rx.total_bytes += total_rx_bytes;
1515 }
1516
1517 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1518 /**
1519  * ixgbe_configure_msix - Configure MSI-X hardware
1520  * @adapter: board private structure
1521  *
1522  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1523  * interrupts.
1524  **/
1525 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1526 {
1527         struct ixgbe_q_vector *q_vector;
1528         int i, q_vectors, v_idx, r_idx;
1529         u32 mask;
1530
1531         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1532
1533         /*
1534          * Populate the IVAR table and set the ITR values to the
1535          * corresponding register.
1536          */
1537         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1538                 q_vector = adapter->q_vector[v_idx];
1539                 /* XXX for_each_set_bit(...) */
1540                 r_idx = find_first_bit(q_vector->rx.idx,
1541                                        adapter->num_rx_queues);
1542
1543                 for (i = 0; i < q_vector->rx.count; i++) {
1544                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1545                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1546                         r_idx = find_next_bit(q_vector->rx.idx,
1547                                               adapter->num_rx_queues,
1548                                               r_idx + 1);
1549                 }
1550                 r_idx = find_first_bit(q_vector->tx.idx,
1551                                        adapter->num_tx_queues);
1552
1553                 for (i = 0; i < q_vector->tx.count; i++) {
1554                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1555                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1556                         r_idx = find_next_bit(q_vector->tx.idx,
1557                                               adapter->num_tx_queues,
1558                                               r_idx + 1);
1559                 }
1560
1561                 if (q_vector->tx.count && !q_vector->rx.count)
1562                         /* tx only */
1563                         q_vector->eitr = adapter->tx_eitr_param;
1564                 else if (q_vector->rx.count)
1565                         /* rx or mixed */
1566                         q_vector->eitr = adapter->rx_eitr_param;
1567
1568                 ixgbe_write_eitr(q_vector);
1569                 /* If ATR is enabled, set interrupt affinity */
1570                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1571                         /*
1572                          * Allocate the affinity_hint cpumask, assign the mask
1573                          * for this vector, and set our affinity_hint for
1574                          * this irq.
1575                          */
1576                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1577                                                GFP_KERNEL))
1578                                 return;
1579                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1580                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1581                                               q_vector->affinity_mask);
1582                 }
1583         }
1584
1585         switch (adapter->hw.mac.type) {
1586         case ixgbe_mac_82598EB:
1587                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1588                                v_idx);
1589                 break;
1590         case ixgbe_mac_82599EB:
1591         case ixgbe_mac_X540:
1592                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1593                 break;
1594
1595         default:
1596                 break;
1597         }
1598         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1599
1600         /* set up to autoclear timer, and the vectors */
1601         mask = IXGBE_EIMS_ENABLE_MASK;
1602         if (adapter->num_vfs)
1603                 mask &= ~(IXGBE_EIMS_OTHER |
1604                           IXGBE_EIMS_MAILBOX |
1605                           IXGBE_EIMS_LSC);
1606         else
1607                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1608         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1609 }
1610
1611 enum latency_range {
1612         lowest_latency = 0,
1613         low_latency = 1,
1614         bulk_latency = 2,
1615         latency_invalid = 255
1616 };
1617
1618 /**
1619  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1620  * @q_vector: structure containing interrupt and ring information
1621  * @ring_container: structure containing ring performance data
1622  *
1623  *      Stores a new ITR value based on packets and byte
1624  *      counts during the last interrupt.  The advantage of per interrupt
1625  *      computation is faster updates and more accurate ITR for the current
1626  *      traffic pattern.  Constants in this function were computed
1627  *      based on theoretical maximum wire speed and thresholds were set based
1628  *      on testing data as well as attempting to minimize response time
1629  *      while increasing bulk throughput.
1630  *      this functionality is controlled by the InterruptThrottleRate module
1631  *      parameter (see ixgbe_param.c)
1632  **/
1633 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1634                              struct ixgbe_ring_container *ring_container)
1635 {
1636         u64 bytes_perint;
1637         struct ixgbe_adapter *adapter = q_vector->adapter;
1638         int bytes = ring_container->total_bytes;
1639         int packets = ring_container->total_packets;
1640         u32 timepassed_us;
1641         u8 itr_setting = ring_container->itr;
1642
1643         if (packets == 0)
1644                 return;
1645
1646         /* simple throttlerate management
1647          *    0-20MB/s lowest (100000 ints/s)
1648          *   20-100MB/s low   (20000 ints/s)
1649          *  100-1249MB/s bulk (8000 ints/s)
1650          */
1651         /* what was last interrupt timeslice? */
1652         timepassed_us = 1000000/q_vector->eitr;
1653         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1654
1655         switch (itr_setting) {
1656         case lowest_latency:
1657                 if (bytes_perint > adapter->eitr_low)
1658                         itr_setting = low_latency;
1659                 break;
1660         case low_latency:
1661                 if (bytes_perint > adapter->eitr_high)
1662                         itr_setting = bulk_latency;
1663                 else if (bytes_perint <= adapter->eitr_low)
1664                         itr_setting = lowest_latency;
1665                 break;
1666         case bulk_latency:
1667                 if (bytes_perint <= adapter->eitr_high)
1668                         itr_setting = low_latency;
1669                 break;
1670         }
1671
1672         /* clear work counters since we have the values we need */
1673         ring_container->total_bytes = 0;
1674         ring_container->total_packets = 0;
1675
1676         /* write updated itr to ring container */
1677         ring_container->itr = itr_setting;
1678 }
1679
1680 /**
1681  * ixgbe_write_eitr - write EITR register in hardware specific way
1682  * @q_vector: structure containing interrupt and ring information
1683  *
1684  * This function is made to be called by ethtool and by the driver
1685  * when it needs to update EITR registers at runtime.  Hardware
1686  * specific quirks/differences are taken care of here.
1687  */
1688 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1689 {
1690         struct ixgbe_adapter *adapter = q_vector->adapter;
1691         struct ixgbe_hw *hw = &adapter->hw;
1692         int v_idx = q_vector->v_idx;
1693         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1694
1695         switch (adapter->hw.mac.type) {
1696         case ixgbe_mac_82598EB:
1697                 /* must write high and low 16 bits to reset counter */
1698                 itr_reg |= (itr_reg << 16);
1699                 break;
1700         case ixgbe_mac_82599EB:
1701         case ixgbe_mac_X540:
1702                 /*
1703                  * 82599 and X540 can support a value of zero, so allow it for
1704                  * max interrupt rate, but there is an errata where it can
1705                  * not be zero with RSC
1706                  */
1707                 if (itr_reg == 8 &&
1708                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1709                         itr_reg = 0;
1710
1711                 /*
1712                  * set the WDIS bit to not clear the timer bits and cause an
1713                  * immediate assertion of the interrupt
1714                  */
1715                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1716                 break;
1717         default:
1718                 break;
1719         }
1720         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1721 }
1722
1723 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1724 {
1725         u32 new_itr = q_vector->eitr;
1726         u8 current_itr;
1727
1728         ixgbe_update_itr(q_vector, &q_vector->tx);
1729         ixgbe_update_itr(q_vector, &q_vector->rx);
1730
1731         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1732
1733         switch (current_itr) {
1734         /* counts and packets in update_itr are dependent on these numbers */
1735         case lowest_latency:
1736                 new_itr = 100000;
1737                 break;
1738         case low_latency:
1739                 new_itr = 20000; /* aka hwitr = ~200 */
1740                 break;
1741         case bulk_latency:
1742                 new_itr = 8000;
1743                 break;
1744         default:
1745                 break;
1746         }
1747
1748         if (new_itr != q_vector->eitr) {
1749                 /* do an exponential smoothing */
1750                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1751
1752                 /* save the algorithm value here */
1753                 q_vector->eitr = new_itr;
1754
1755                 ixgbe_write_eitr(q_vector);
1756         }
1757 }
1758
1759 /**
1760  * ixgbe_check_overtemp_subtask - check for over tempurature
1761  * @adapter: pointer to adapter
1762  **/
1763 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1764 {
1765         struct ixgbe_hw *hw = &adapter->hw;
1766         u32 eicr = adapter->interrupt_event;
1767
1768         if (test_bit(__IXGBE_DOWN, &adapter->state))
1769                 return;
1770
1771         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1772             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1773                 return;
1774
1775         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1776
1777         switch (hw->device_id) {
1778         case IXGBE_DEV_ID_82599_T3_LOM:
1779                 /*
1780                  * Since the warning interrupt is for both ports
1781                  * we don't have to check if:
1782                  *  - This interrupt wasn't for our port.
1783                  *  - We may have missed the interrupt so always have to
1784                  *    check if we  got a LSC
1785                  */
1786                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1787                     !(eicr & IXGBE_EICR_LSC))
1788                         return;
1789
1790                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1791                         u32 autoneg;
1792                         bool link_up = false;
1793
1794                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1795
1796                         if (link_up)
1797                                 return;
1798                 }
1799
1800                 /* Check if this is not due to overtemp */
1801                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1802                         return;
1803
1804                 break;
1805         default:
1806                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1807                         return;
1808                 break;
1809         }
1810         e_crit(drv,
1811                "Network adapter has been stopped because it has over heated. "
1812                "Restart the computer. If the problem persists, "
1813                "power off the system and replace the adapter\n");
1814
1815         adapter->interrupt_event = 0;
1816 }
1817
1818 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1819 {
1820         struct ixgbe_hw *hw = &adapter->hw;
1821
1822         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1823             (eicr & IXGBE_EICR_GPI_SDP1)) {
1824                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1825                 /* write to clear the interrupt */
1826                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1827         }
1828 }
1829
1830 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1831 {
1832         struct ixgbe_hw *hw = &adapter->hw;
1833
1834         if (eicr & IXGBE_EICR_GPI_SDP2) {
1835                 /* Clear the interrupt */
1836                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1837                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1838                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1839                         ixgbe_service_event_schedule(adapter);
1840                 }
1841         }
1842
1843         if (eicr & IXGBE_EICR_GPI_SDP1) {
1844                 /* Clear the interrupt */
1845                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1846                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1847                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1848                         ixgbe_service_event_schedule(adapter);
1849                 }
1850         }
1851 }
1852
1853 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1854 {
1855         struct ixgbe_hw *hw = &adapter->hw;
1856
1857         adapter->lsc_int++;
1858         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1859         adapter->link_check_timeout = jiffies;
1860         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1862                 IXGBE_WRITE_FLUSH(hw);
1863                 ixgbe_service_event_schedule(adapter);
1864         }
1865 }
1866
1867 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1868 {
1869         struct ixgbe_adapter *adapter = data;
1870         struct ixgbe_hw *hw = &adapter->hw;
1871         u32 eicr;
1872
1873         /*
1874          * Workaround for Silicon errata.  Use clear-by-write instead
1875          * of clear-by-read.  Reading with EICS will return the
1876          * interrupt causes without clearing, which later be done
1877          * with the write to EICR.
1878          */
1879         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1880         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1881
1882         if (eicr & IXGBE_EICR_LSC)
1883                 ixgbe_check_lsc(adapter);
1884
1885         if (eicr & IXGBE_EICR_MAILBOX)
1886                 ixgbe_msg_task(adapter);
1887
1888         switch (hw->mac.type) {
1889         case ixgbe_mac_82599EB:
1890         case ixgbe_mac_X540:
1891                 /* Handle Flow Director Full threshold interrupt */
1892                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1893                         int reinit_count = 0;
1894                         int i;
1895                         for (i = 0; i < adapter->num_tx_queues; i++) {
1896                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1897                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1898                                                        &ring->state))
1899                                         reinit_count++;
1900                         }
1901                         if (reinit_count) {
1902                                 /* no more flow director interrupts until after init */
1903                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1904                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1905                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1906                                 ixgbe_service_event_schedule(adapter);
1907                         }
1908                 }
1909                 ixgbe_check_sfp_event(adapter, eicr);
1910                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1911                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1912                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1913                                 adapter->interrupt_event = eicr;
1914                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1915                                 ixgbe_service_event_schedule(adapter);
1916                         }
1917                 }
1918                 break;
1919         default:
1920                 break;
1921         }
1922
1923         ixgbe_check_fan_failure(adapter, eicr);
1924
1925         /* re-enable the original interrupt state, no lsc, no queues */
1926         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1927                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1928                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1929
1930         return IRQ_HANDLED;
1931 }
1932
1933 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1934                                            u64 qmask)
1935 {
1936         u32 mask;
1937         struct ixgbe_hw *hw = &adapter->hw;
1938
1939         switch (hw->mac.type) {
1940         case ixgbe_mac_82598EB:
1941                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1942                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1943                 break;
1944         case ixgbe_mac_82599EB:
1945         case ixgbe_mac_X540:
1946                 mask = (qmask & 0xFFFFFFFF);
1947                 if (mask)
1948                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1949                 mask = (qmask >> 32);
1950                 if (mask)
1951                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1952                 break;
1953         default:
1954                 break;
1955         }
1956         /* skip the flush */
1957 }
1958
1959 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1960                                             u64 qmask)
1961 {
1962         u32 mask;
1963         struct ixgbe_hw *hw = &adapter->hw;
1964
1965         switch (hw->mac.type) {
1966         case ixgbe_mac_82598EB:
1967                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1968                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1969                 break;
1970         case ixgbe_mac_82599EB:
1971         case ixgbe_mac_X540:
1972                 mask = (qmask & 0xFFFFFFFF);
1973                 if (mask)
1974                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1975                 mask = (qmask >> 32);
1976                 if (mask)
1977                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1978                 break;
1979         default:
1980                 break;
1981         }
1982         /* skip the flush */
1983 }
1984
1985 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1986 {
1987         struct ixgbe_q_vector *q_vector = data;
1988         struct ixgbe_adapter  *adapter = q_vector->adapter;
1989         struct ixgbe_ring     *tx_ring;
1990         int i, r_idx;
1991
1992         if (!q_vector->tx.count)
1993                 return IRQ_HANDLED;
1994
1995         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
1996         for (i = 0; i < q_vector->tx.count; i++) {
1997                 tx_ring = adapter->tx_ring[r_idx];
1998                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
1999                                       r_idx + 1);
2000         }
2001
2002         /* EIAM disabled interrupts (on this vector) for us */
2003         napi_schedule(&q_vector->napi);
2004
2005         return IRQ_HANDLED;
2006 }
2007
2008 /**
2009  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2010  * @irq: unused
2011  * @data: pointer to our q_vector struct for this interrupt vector
2012  **/
2013 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2014 {
2015         struct ixgbe_q_vector *q_vector = data;
2016         struct ixgbe_adapter  *adapter = q_vector->adapter;
2017         struct ixgbe_ring  *rx_ring;
2018         int r_idx;
2019         int i;
2020
2021 #ifdef CONFIG_IXGBE_DCA
2022         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2023                 ixgbe_update_dca(q_vector);
2024 #endif
2025
2026         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2027         for (i = 0; i < q_vector->rx.count; i++) {
2028                 rx_ring = adapter->rx_ring[r_idx];
2029                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2030                                       r_idx + 1);
2031         }
2032
2033         if (!q_vector->rx.count)
2034                 return IRQ_HANDLED;
2035
2036         /* EIAM disabled interrupts (on this vector) for us */
2037         napi_schedule(&q_vector->napi);
2038
2039         return IRQ_HANDLED;
2040 }
2041
2042 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2043 {
2044         struct ixgbe_q_vector *q_vector = data;
2045         struct ixgbe_adapter  *adapter = q_vector->adapter;
2046         struct ixgbe_ring  *ring;
2047         int r_idx;
2048         int i;
2049
2050         if (!q_vector->tx.count && !q_vector->rx.count)
2051                 return IRQ_HANDLED;
2052
2053         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2054         for (i = 0; i < q_vector->tx.count; i++) {
2055                 ring = adapter->tx_ring[r_idx];
2056                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2057                                       r_idx + 1);
2058         }
2059
2060         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2061         for (i = 0; i < q_vector->rx.count; i++) {
2062                 ring = adapter->rx_ring[r_idx];
2063                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2064                                       r_idx + 1);
2065         }
2066
2067         /* EIAM disabled interrupts (on this vector) for us */
2068         napi_schedule(&q_vector->napi);
2069
2070         return IRQ_HANDLED;
2071 }
2072
2073 /**
2074  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2075  * @napi: napi struct with our devices info in it
2076  * @budget: amount of work driver is allowed to do this pass, in packets
2077  *
2078  * This function is optimized for cleaning one queue only on a single
2079  * q_vector!!!
2080  **/
2081 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2082 {
2083         struct ixgbe_q_vector *q_vector =
2084                                container_of(napi, struct ixgbe_q_vector, napi);
2085         struct ixgbe_adapter *adapter = q_vector->adapter;
2086         struct ixgbe_ring *rx_ring = NULL;
2087         int work_done = 0;
2088         long r_idx;
2089
2090 #ifdef CONFIG_IXGBE_DCA
2091         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2092                 ixgbe_update_dca(q_vector);
2093 #endif
2094
2095         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2096         rx_ring = adapter->rx_ring[r_idx];
2097
2098         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2099
2100         /* If all Rx work done, exit the polling mode */
2101         if (work_done < budget) {
2102                 napi_complete(napi);
2103                 if (adapter->rx_itr_setting & 1)
2104                         ixgbe_set_itr(q_vector);
2105                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2106                         ixgbe_irq_enable_queues(adapter,
2107                                                 ((u64)1 << q_vector->v_idx));
2108         }
2109
2110         return work_done;
2111 }
2112
2113 /**
2114  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2115  * @napi: napi struct with our devices info in it
2116  * @budget: amount of work driver is allowed to do this pass, in packets
2117  *
2118  * This function will clean more than one rx queue associated with a
2119  * q_vector.
2120  **/
2121 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2122 {
2123         struct ixgbe_q_vector *q_vector =
2124                                container_of(napi, struct ixgbe_q_vector, napi);
2125         struct ixgbe_adapter *adapter = q_vector->adapter;
2126         struct ixgbe_ring *ring = NULL;
2127         int work_done = 0, i;
2128         long r_idx;
2129         bool tx_clean_complete = true;
2130
2131 #ifdef CONFIG_IXGBE_DCA
2132         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2133                 ixgbe_update_dca(q_vector);
2134 #endif
2135
2136         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2137         for (i = 0; i < q_vector->tx.count; i++) {
2138                 ring = adapter->tx_ring[r_idx];
2139                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2140                 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2141                                       r_idx + 1);
2142         }
2143
2144         /* attempt to distribute budget to each queue fairly, but don't allow
2145          * the budget to go below 1 because we'll exit polling */
2146         budget /= (q_vector->rx.count ?: 1);
2147         budget = max(budget, 1);
2148         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2149         for (i = 0; i < q_vector->rx.count; i++) {
2150                 ring = adapter->rx_ring[r_idx];
2151                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2152                 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2153                                       r_idx + 1);
2154         }
2155
2156         r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2157         ring = adapter->rx_ring[r_idx];
2158         /* If all Rx work done, exit the polling mode */
2159         if (work_done < budget) {
2160                 napi_complete(napi);
2161                 if (adapter->rx_itr_setting & 1)
2162                         ixgbe_set_itr(q_vector);
2163                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2164                         ixgbe_irq_enable_queues(adapter,
2165                                                 ((u64)1 << q_vector->v_idx));
2166                 return 0;
2167         }
2168
2169         return work_done;
2170 }
2171
2172 /**
2173  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2174  * @napi: napi struct with our devices info in it
2175  * @budget: amount of work driver is allowed to do this pass, in packets
2176  *
2177  * This function is optimized for cleaning one queue only on a single
2178  * q_vector!!!
2179  **/
2180 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2181 {
2182         struct ixgbe_q_vector *q_vector =
2183                                container_of(napi, struct ixgbe_q_vector, napi);
2184         struct ixgbe_adapter *adapter = q_vector->adapter;
2185         struct ixgbe_ring *tx_ring = NULL;
2186         int work_done = 0;
2187         long r_idx;
2188
2189 #ifdef CONFIG_IXGBE_DCA
2190         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2191                 ixgbe_update_dca(q_vector);
2192 #endif
2193
2194         r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2195         tx_ring = adapter->tx_ring[r_idx];
2196
2197         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2198                 work_done = budget;
2199
2200         /* If all Tx work done, exit the polling mode */
2201         if (work_done < budget) {
2202                 napi_complete(napi);
2203                 if (adapter->tx_itr_setting & 1)
2204                         ixgbe_set_itr(q_vector);
2205                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2206                         ixgbe_irq_enable_queues(adapter,
2207                                                 ((u64)1 << q_vector->v_idx));
2208         }
2209
2210         return work_done;
2211 }
2212
2213 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2214                                      int r_idx)
2215 {
2216         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2217         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2218
2219         set_bit(r_idx, q_vector->rx.idx);
2220         q_vector->rx.count++;
2221         rx_ring->q_vector = q_vector;
2222 }
2223
2224 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2225                                      int t_idx)
2226 {
2227         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2228         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2229
2230         set_bit(t_idx, q_vector->tx.idx);
2231         q_vector->tx.count++;
2232         tx_ring->q_vector = q_vector;
2233         q_vector->tx.work_limit = a->tx_work_limit;
2234 }
2235
2236 /**
2237  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2238  * @adapter: board private structure to initialize
2239  *
2240  * This function maps descriptor rings to the queue-specific vectors
2241  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2242  * one vector per ring/queue, but on a constrained vector budget, we
2243  * group the rings as "efficiently" as possible.  You would add new
2244  * mapping configurations in here.
2245  **/
2246 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2247 {
2248         int q_vectors;
2249         int v_start = 0;
2250         int rxr_idx = 0, txr_idx = 0;
2251         int rxr_remaining = adapter->num_rx_queues;
2252         int txr_remaining = adapter->num_tx_queues;
2253         int i, j;
2254         int rqpv, tqpv;
2255         int err = 0;
2256
2257         /* No mapping required if MSI-X is disabled. */
2258         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2259                 goto out;
2260
2261         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2262
2263         /*
2264          * The ideal configuration...
2265          * We have enough vectors to map one per queue.
2266          */
2267         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2268                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2269                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2270
2271                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2272                         map_vector_to_txq(adapter, v_start, txr_idx);
2273
2274                 goto out;
2275         }
2276
2277         /*
2278          * If we don't have enough vectors for a 1-to-1
2279          * mapping, we'll have to group them so there are
2280          * multiple queues per vector.
2281          */
2282         /* Re-adjusting *qpv takes care of the remainder. */
2283         for (i = v_start; i < q_vectors; i++) {
2284                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2285                 for (j = 0; j < rqpv; j++) {
2286                         map_vector_to_rxq(adapter, i, rxr_idx);
2287                         rxr_idx++;
2288                         rxr_remaining--;
2289                 }
2290                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2291                 for (j = 0; j < tqpv; j++) {
2292                         map_vector_to_txq(adapter, i, txr_idx);
2293                         txr_idx++;
2294                         txr_remaining--;
2295                 }
2296         }
2297 out:
2298         return err;
2299 }
2300
2301 /**
2302  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2303  * @adapter: board private structure
2304  *
2305  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2306  * interrupts from the kernel.
2307  **/
2308 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2309 {
2310         struct net_device *netdev = adapter->netdev;
2311         irqreturn_t (*handler)(int, void *);
2312         int i, vector, q_vectors, err;
2313         int ri = 0, ti = 0;
2314
2315         /* Decrement for Other and TCP Timer vectors */
2316         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2317
2318         err = ixgbe_map_rings_to_vectors(adapter);
2319         if (err)
2320                 return err;
2321
2322 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count)        \
2323                                           ? &ixgbe_msix_clean_many : \
2324                           (_v)->rx.count ? &ixgbe_msix_clean_rx   : \
2325                           (_v)->tx.count ? &ixgbe_msix_clean_tx   : \
2326                           NULL)
2327         for (vector = 0; vector < q_vectors; vector++) {
2328                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2329                 handler = SET_HANDLER(q_vector);
2330
2331                 if (handler == &ixgbe_msix_clean_rx) {
2332                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2333                                  "%s-%s-%d", netdev->name, "rx", ri++);
2334                 } else if (handler == &ixgbe_msix_clean_tx) {
2335                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2336                                  "%s-%s-%d", netdev->name, "tx", ti++);
2337                 } else if (handler == &ixgbe_msix_clean_many) {
2338                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2339                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2340                         ti++;
2341                 } else {
2342                         /* skip this unused q_vector */
2343                         continue;
2344                 }
2345                 err = request_irq(adapter->msix_entries[vector].vector,
2346                                   handler, 0, q_vector->name,
2347                                   q_vector);
2348                 if (err) {
2349                         e_err(probe, "request_irq failed for MSIX interrupt "
2350                               "Error: %d\n", err);
2351                         goto free_queue_irqs;
2352                 }
2353         }
2354
2355         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2356         err = request_irq(adapter->msix_entries[vector].vector,
2357                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2358         if (err) {
2359                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2360                 goto free_queue_irqs;
2361         }
2362
2363         return 0;
2364
2365 free_queue_irqs:
2366         for (i = vector - 1; i >= 0; i--)
2367                 free_irq(adapter->msix_entries[--vector].vector,
2368                          adapter->q_vector[i]);
2369         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2370         pci_disable_msix(adapter->pdev);
2371         kfree(adapter->msix_entries);
2372         adapter->msix_entries = NULL;
2373         return err;
2374 }
2375
2376 /**
2377  * ixgbe_irq_enable - Enable default interrupt generation settings
2378  * @adapter: board private structure
2379  **/
2380 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2381                                     bool flush)
2382 {
2383         u32 mask;
2384
2385         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2386         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2387                 mask |= IXGBE_EIMS_GPI_SDP0;
2388         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2389                 mask |= IXGBE_EIMS_GPI_SDP1;
2390         switch (adapter->hw.mac.type) {
2391         case ixgbe_mac_82599EB:
2392         case ixgbe_mac_X540:
2393                 mask |= IXGBE_EIMS_ECC;
2394                 mask |= IXGBE_EIMS_GPI_SDP1;
2395                 mask |= IXGBE_EIMS_GPI_SDP2;
2396                 if (adapter->num_vfs)
2397                         mask |= IXGBE_EIMS_MAILBOX;
2398                 break;
2399         default:
2400                 break;
2401         }
2402         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2403                 mask |= IXGBE_EIMS_FLOW_DIR;
2404
2405         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2406         if (queues)
2407                 ixgbe_irq_enable_queues(adapter, ~0);
2408         if (flush)
2409                 IXGBE_WRITE_FLUSH(&adapter->hw);
2410
2411         if (adapter->num_vfs > 32) {
2412                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2413                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2414         }
2415 }
2416
2417 /**
2418  * ixgbe_intr - legacy mode Interrupt Handler
2419  * @irq: interrupt number
2420  * @data: pointer to a network interface device structure
2421  **/
2422 static irqreturn_t ixgbe_intr(int irq, void *data)
2423 {
2424         struct ixgbe_adapter *adapter = data;
2425         struct ixgbe_hw *hw = &adapter->hw;
2426         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2427         u32 eicr;
2428
2429         /*
2430          * Workaround for silicon errata on 82598.  Mask the interrupts
2431          * before the read of EICR.
2432          */
2433         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2434
2435         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2436          * therefore no explict interrupt disable is necessary */
2437         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2438         if (!eicr) {
2439                 /*
2440                  * shared interrupt alert!
2441                  * make sure interrupts are enabled because the read will
2442                  * have disabled interrupts due to EIAM
2443                  * finish the workaround of silicon errata on 82598.  Unmask
2444                  * the interrupt that we masked before the EICR read.
2445                  */
2446                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2447                         ixgbe_irq_enable(adapter, true, true);
2448                 return IRQ_NONE;        /* Not our interrupt */
2449         }
2450
2451         if (eicr & IXGBE_EICR_LSC)
2452                 ixgbe_check_lsc(adapter);
2453
2454         switch (hw->mac.type) {
2455         case ixgbe_mac_82599EB:
2456                 ixgbe_check_sfp_event(adapter, eicr);
2457                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2458                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2459                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2460                                 adapter->interrupt_event = eicr;
2461                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2462                                 ixgbe_service_event_schedule(adapter);
2463                         }
2464                 }
2465                 break;
2466         default:
2467                 break;
2468         }
2469
2470         ixgbe_check_fan_failure(adapter, eicr);
2471
2472         if (napi_schedule_prep(&(q_vector->napi))) {
2473                 /* would disable interrupts here but EIAM disabled it */
2474                 __napi_schedule(&(q_vector->napi));
2475         }
2476
2477         /*
2478          * re-enable link(maybe) and non-queue interrupts, no flush.
2479          * ixgbe_poll will re-enable the queue interrupts
2480          */
2481
2482         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2483                 ixgbe_irq_enable(adapter, false, false);
2484
2485         return IRQ_HANDLED;
2486 }
2487
2488 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2489 {
2490         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2491
2492         for (i = 0; i < q_vectors; i++) {
2493                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2494                 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2495                 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2496                 q_vector->rx.count = 0;
2497                 q_vector->tx.count = 0;
2498         }
2499 }
2500
2501 /**
2502  * ixgbe_request_irq - initialize interrupts
2503  * @adapter: board private structure
2504  *
2505  * Attempts to configure interrupts using the best available
2506  * capabilities of the hardware and kernel.
2507  **/
2508 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2509 {
2510         struct net_device *netdev = adapter->netdev;
2511         int err;
2512
2513         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2514                 err = ixgbe_request_msix_irqs(adapter);
2515         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2516                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2517                                   netdev->name, adapter);
2518         } else {
2519                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2520                                   netdev->name, adapter);
2521         }
2522
2523         if (err)
2524                 e_err(probe, "request_irq failed, Error %d\n", err);
2525
2526         return err;
2527 }
2528
2529 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2530 {
2531         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2532                 int i, q_vectors;
2533
2534                 q_vectors = adapter->num_msix_vectors;
2535
2536                 i = q_vectors - 1;
2537                 free_irq(adapter->msix_entries[i].vector, adapter);
2538
2539                 i--;
2540                 for (; i >= 0; i--) {
2541                         /* free only the irqs that were actually requested */
2542                         if (!adapter->q_vector[i]->rx.count &&
2543                             !adapter->q_vector[i]->tx.count)
2544                                 continue;
2545
2546                         free_irq(adapter->msix_entries[i].vector,
2547                                  adapter->q_vector[i]);
2548                 }
2549
2550                 ixgbe_reset_q_vectors(adapter);
2551         } else {
2552                 free_irq(adapter->pdev->irq, adapter);
2553         }
2554 }
2555
2556 /**
2557  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2558  * @adapter: board private structure
2559  **/
2560 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2561 {
2562         switch (adapter->hw.mac.type) {
2563         case ixgbe_mac_82598EB:
2564                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2565                 break;
2566         case ixgbe_mac_82599EB:
2567         case ixgbe_mac_X540:
2568                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2569                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2570                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2571                 if (adapter->num_vfs > 32)
2572                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2573                 break;
2574         default:
2575                 break;
2576         }
2577         IXGBE_WRITE_FLUSH(&adapter->hw);
2578         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2579                 int i;
2580                 for (i = 0; i < adapter->num_msix_vectors; i++)
2581                         synchronize_irq(adapter->msix_entries[i].vector);
2582         } else {
2583                 synchronize_irq(adapter->pdev->irq);
2584         }
2585 }
2586
2587 /**
2588  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2589  *
2590  **/
2591 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2592 {
2593         struct ixgbe_hw *hw = &adapter->hw;
2594
2595         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2596                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2597
2598         ixgbe_set_ivar(adapter, 0, 0, 0);
2599         ixgbe_set_ivar(adapter, 1, 0, 0);
2600
2601         map_vector_to_rxq(adapter, 0, 0);
2602         map_vector_to_txq(adapter, 0, 0);
2603
2604         e_info(hw, "Legacy interrupt IVAR setup done\n");
2605 }
2606
2607 /**
2608  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2609  * @adapter: board private structure
2610  * @ring: structure containing ring specific data
2611  *
2612  * Configure the Tx descriptor ring after a reset.
2613  **/
2614 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2615                              struct ixgbe_ring *ring)
2616 {
2617         struct ixgbe_hw *hw = &adapter->hw;
2618         u64 tdba = ring->dma;
2619         int wait_loop = 10;
2620         u32 txdctl;
2621         u8 reg_idx = ring->reg_idx;
2622
2623         /* disable queue to avoid issues while updating state */
2624         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2625         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2626                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2627         IXGBE_WRITE_FLUSH(hw);
2628
2629         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2630                         (tdba & DMA_BIT_MASK(32)));
2631         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2632         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2633                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2634         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2635         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2636         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2637
2638         /* configure fetching thresholds */
2639         if (adapter->rx_itr_setting == 0) {
2640                 /* cannot set wthresh when itr==0 */
2641                 txdctl &= ~0x007F0000;
2642         } else {
2643                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2644                 txdctl |= (8 << 16);
2645         }
2646         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2647                 /* PThresh workaround for Tx hang with DFP enabled. */
2648                 txdctl |= 32;
2649         }
2650
2651         /* reinitialize flowdirector state */
2652         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2653             adapter->atr_sample_rate) {
2654                 ring->atr_sample_rate = adapter->atr_sample_rate;
2655                 ring->atr_count = 0;
2656                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2657         } else {
2658                 ring->atr_sample_rate = 0;
2659         }
2660
2661         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2662
2663         /* enable queue */
2664         txdctl |= IXGBE_TXDCTL_ENABLE;
2665         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2666
2667         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2668         if (hw->mac.type == ixgbe_mac_82598EB &&
2669             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2670                 return;
2671
2672         /* poll to verify queue is enabled */
2673         do {
2674                 usleep_range(1000, 2000);
2675                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2676         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2677         if (!wait_loop)
2678                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2679 }
2680
2681 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2682 {
2683         struct ixgbe_hw *hw = &adapter->hw;
2684         u32 rttdcs;
2685         u32 reg;
2686         u8 tcs = netdev_get_num_tc(adapter->netdev);
2687
2688         if (hw->mac.type == ixgbe_mac_82598EB)
2689                 return;
2690
2691         /* disable the arbiter while setting MTQC */
2692         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2693         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2694         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2695
2696         /* set transmit pool layout */
2697         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2698         case (IXGBE_FLAG_SRIOV_ENABLED):
2699                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2700                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2701                 break;
2702         default:
2703                 if (!tcs)
2704                         reg = IXGBE_MTQC_64Q_1PB;
2705                 else if (tcs <= 4)
2706                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2707                 else
2708                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2709
2710                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2711
2712                 /* Enable Security TX Buffer IFG for multiple pb */
2713                 if (tcs) {
2714                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2715                         reg |= IXGBE_SECTX_DCB;
2716                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2717                 }
2718                 break;
2719         }
2720
2721         /* re-enable the arbiter */
2722         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2723         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2724 }
2725
2726 /**
2727  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2728  * @adapter: board private structure
2729  *
2730  * Configure the Tx unit of the MAC after a reset.
2731  **/
2732 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2733 {
2734         struct ixgbe_hw *hw = &adapter->hw;
2735         u32 dmatxctl;
2736         u32 i;
2737
2738         ixgbe_setup_mtqc(adapter);
2739
2740         if (hw->mac.type != ixgbe_mac_82598EB) {
2741                 /* DMATXCTL.EN must be before Tx queues are enabled */
2742                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2743                 dmatxctl |= IXGBE_DMATXCTL_TE;
2744                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2745         }
2746
2747         /* Setup the HW Tx Head and Tail descriptor pointers */
2748         for (i = 0; i < adapter->num_tx_queues; i++)
2749                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2750 }
2751
2752 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2753
2754 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2755                                    struct ixgbe_ring *rx_ring)
2756 {
2757         u32 srrctl;
2758         u8 reg_idx = rx_ring->reg_idx;
2759
2760         switch (adapter->hw.mac.type) {
2761         case ixgbe_mac_82598EB: {
2762                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2763                 const int mask = feature[RING_F_RSS].mask;
2764                 reg_idx = reg_idx & mask;
2765         }
2766                 break;
2767         case ixgbe_mac_82599EB:
2768         case ixgbe_mac_X540:
2769         default:
2770                 break;
2771         }
2772
2773         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2774
2775         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2776         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2777         if (adapter->num_vfs)
2778                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2779
2780         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2781                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2782
2783         if (ring_is_ps_enabled(rx_ring)) {
2784 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2785                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2786 #else
2787                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2788 #endif
2789                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2790         } else {
2791                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2792                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2793                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2794         }
2795
2796         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2797 }
2798
2799 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2800 {
2801         struct ixgbe_hw *hw = &adapter->hw;
2802         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2803                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2804                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2805         u32 mrqc = 0, reta = 0;
2806         u32 rxcsum;
2807         int i, j;
2808         u8 tcs = netdev_get_num_tc(adapter->netdev);
2809         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2810
2811         if (tcs)
2812                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2813
2814         /* Fill out hash function seeds */
2815         for (i = 0; i < 10; i++)
2816                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2817
2818         /* Fill out redirection table */
2819         for (i = 0, j = 0; i < 128; i++, j++) {
2820                 if (j == maxq)
2821                         j = 0;
2822                 /* reta = 4-byte sliding window of
2823                  * 0x00..(indices-1)(indices-1)00..etc. */
2824                 reta = (reta << 8) | (j * 0x11);
2825                 if ((i & 3) == 3)
2826                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2827         }
2828
2829         /* Disable indicating checksum in descriptor, enables RSS hash */
2830         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2831         rxcsum |= IXGBE_RXCSUM_PCSD;
2832         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2833
2834         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2835             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2836                 mrqc = IXGBE_MRQC_RSSEN;
2837         } else {
2838                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2839                                              | IXGBE_FLAG_SRIOV_ENABLED);
2840
2841                 switch (mask) {
2842                 case (IXGBE_FLAG_RSS_ENABLED):
2843                         if (!tcs)
2844                                 mrqc = IXGBE_MRQC_RSSEN;
2845                         else if (tcs <= 4)
2846                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2847                         else
2848                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2849                         break;
2850                 case (IXGBE_FLAG_SRIOV_ENABLED):
2851                         mrqc = IXGBE_MRQC_VMDQEN;
2852                         break;
2853                 default:
2854                         break;
2855                 }
2856         }
2857
2858         /* Perform hash on these packet types */
2859         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2860               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2861               | IXGBE_MRQC_RSS_FIELD_IPV6
2862               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2863
2864         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2865 }
2866
2867 /**
2868  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2869  * @adapter:    address of board private structure
2870  * @index:      index of ring to set
2871  **/
2872 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2873                                    struct ixgbe_ring *ring)
2874 {
2875         struct ixgbe_hw *hw = &adapter->hw;
2876         u32 rscctrl;
2877         int rx_buf_len;
2878         u8 reg_idx = ring->reg_idx;
2879
2880         if (!ring_is_rsc_enabled(ring))
2881                 return;
2882
2883         rx_buf_len = ring->rx_buf_len;
2884         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2885         rscctrl |= IXGBE_RSCCTL_RSCEN;
2886         /*
2887          * we must limit the number of descriptors so that the
2888          * total size of max desc * buf_len is not greater
2889          * than 65535
2890          */
2891         if (ring_is_ps_enabled(ring)) {
2892 #if (MAX_SKB_FRAGS > 16)
2893                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2894 #elif (MAX_SKB_FRAGS > 8)
2895                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2896 #elif (MAX_SKB_FRAGS > 4)
2897                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2898 #else
2899                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2900 #endif
2901         } else {
2902                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2903                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2904                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2905                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2906                 else
2907                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2908         }
2909         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2910 }
2911
2912 /**
2913  *  ixgbe_set_uta - Set unicast filter table address
2914  *  @adapter: board private structure
2915  *
2916  *  The unicast table address is a register array of 32-bit registers.
2917  *  The table is meant to be used in a way similar to how the MTA is used
2918  *  however due to certain limitations in the hardware it is necessary to
2919  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2920  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2921  **/
2922 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2923 {
2924         struct ixgbe_hw *hw = &adapter->hw;
2925         int i;
2926
2927         /* The UTA table only exists on 82599 hardware and newer */
2928         if (hw->mac.type < ixgbe_mac_82599EB)
2929                 return;
2930
2931         /* we only need to do this if VMDq is enabled */
2932         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2933                 return;
2934
2935         for (i = 0; i < 128; i++)
2936                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2937 }
2938
2939 #define IXGBE_MAX_RX_DESC_POLL 10
2940 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2941                                        struct ixgbe_ring *ring)
2942 {
2943         struct ixgbe_hw *hw = &adapter->hw;
2944         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2945         u32 rxdctl;
2946         u8 reg_idx = ring->reg_idx;
2947
2948         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2949         if (hw->mac.type == ixgbe_mac_82598EB &&
2950             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2951                 return;
2952
2953         do {
2954                 usleep_range(1000, 2000);
2955                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2956         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2957
2958         if (!wait_loop) {
2959                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2960                       "the polling period\n", reg_idx);
2961         }
2962 }
2963
2964 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2965                             struct ixgbe_ring *ring)
2966 {
2967         struct ixgbe_hw *hw = &adapter->hw;
2968         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2969         u32 rxdctl;
2970         u8 reg_idx = ring->reg_idx;
2971
2972         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2973         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2974
2975         /* write value back with RXDCTL.ENABLE bit cleared */
2976         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2977
2978         if (hw->mac.type == ixgbe_mac_82598EB &&
2979             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2980                 return;
2981
2982         /* the hardware may take up to 100us to really disable the rx queue */
2983         do {
2984                 udelay(10);
2985                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2986         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2987
2988         if (!wait_loop) {
2989                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2990                       "the polling period\n", reg_idx);
2991         }
2992 }
2993
2994 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2995                              struct ixgbe_ring *ring)
2996 {
2997         struct ixgbe_hw *hw = &adapter->hw;
2998         u64 rdba = ring->dma;
2999         u32 rxdctl;
3000         u8 reg_idx = ring->reg_idx;
3001
3002         /* disable queue to avoid issues while updating state */
3003         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3004         ixgbe_disable_rx_queue(adapter, ring);
3005
3006         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3007         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3008         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3009                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3010         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3011         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3012         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3013
3014         ixgbe_configure_srrctl(adapter, ring);
3015         ixgbe_configure_rscctl(adapter, ring);
3016
3017         /* If operating in IOV mode set RLPML for X540 */
3018         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3019             hw->mac.type == ixgbe_mac_X540) {
3020                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3021                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3022                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3023         }
3024
3025         if (hw->mac.type == ixgbe_mac_82598EB) {
3026                 /*
3027                  * enable cache line friendly hardware writes:
3028                  * PTHRESH=32 descriptors (half the internal cache),
3029                  * this also removes ugly rx_no_buffer_count increment
3030                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3031                  * WTHRESH=8 burst writeback up to two cache lines
3032                  */
3033                 rxdctl &= ~0x3FFFFF;
3034                 rxdctl |=  0x080420;
3035         }
3036
3037         /* enable receive descriptor ring */
3038         rxdctl |= IXGBE_RXDCTL_ENABLE;
3039         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3040
3041         ixgbe_rx_desc_queue_enable(adapter, ring);
3042         ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3043 }
3044
3045 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3046 {
3047         struct ixgbe_hw *hw = &adapter->hw;
3048         int p;
3049
3050         /* PSRTYPE must be initialized in non 82598 adapters */
3051         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3052                       IXGBE_PSRTYPE_UDPHDR |
3053                       IXGBE_PSRTYPE_IPV4HDR |
3054                       IXGBE_PSRTYPE_L2HDR |
3055                       IXGBE_PSRTYPE_IPV6HDR;
3056
3057         if (hw->mac.type == ixgbe_mac_82598EB)
3058                 return;
3059
3060         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3061                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3062
3063         for (p = 0; p < adapter->num_rx_pools; p++)
3064                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3065                                 psrtype);
3066 }
3067
3068 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3069 {
3070         struct ixgbe_hw *hw = &adapter->hw;
3071         u32 gcr_ext;
3072         u32 vt_reg_bits;
3073         u32 reg_offset, vf_shift;
3074         u32 vmdctl;
3075
3076         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3077                 return;
3078
3079         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3080         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3081         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3082         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3083
3084         vf_shift = adapter->num_vfs % 32;
3085         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3086
3087         /* Enable only the PF's pool for Tx/Rx */
3088         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3089         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3090         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3091         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3092         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3093
3094         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3095         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3096
3097         /*
3098          * Set up VF register offsets for selected VT Mode,
3099          * i.e. 32 or 64 VFs for SR-IOV
3100          */
3101         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3102         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3103         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3104         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3105
3106         /* enable Tx loopback for VF/PF communication */
3107         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3108         /* Enable MAC Anti-Spoofing */
3109         hw->mac.ops.set_mac_anti_spoofing(hw,
3110                                           (adapter->antispoofing_enabled =
3111                                            (adapter->num_vfs != 0)),
3112                                           adapter->num_vfs);
3113 }
3114
3115 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3116 {
3117         struct ixgbe_hw *hw = &adapter->hw;
3118         struct net_device *netdev = adapter->netdev;
3119         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3120         int rx_buf_len;
3121         struct ixgbe_ring *rx_ring;
3122         int i;
3123         u32 mhadd, hlreg0;
3124
3125         /* Decide whether to use packet split mode or not */
3126         /* On by default */
3127         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3128
3129         /* Do not use packet split if we're in SR-IOV Mode */
3130         if (adapter->num_vfs)
3131                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3132
3133         /* Disable packet split due to 82599 erratum #45 */
3134         if (hw->mac.type == ixgbe_mac_82599EB)
3135                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3136
3137         /* Set the RX buffer length according to the mode */
3138         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3139                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3140         } else {
3141                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3142                     (netdev->mtu <= ETH_DATA_LEN))
3143                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3144                 else
3145                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3146         }
3147
3148 #ifdef IXGBE_FCOE
3149         /* adjust max frame to be able to do baby jumbo for FCoE */
3150         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3151             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3152                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3153
3154 #endif /* IXGBE_FCOE */
3155         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3156         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3157                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3158                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3159
3160                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3161         }
3162
3163         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3164         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3165         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3166         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3167
3168         /*
3169          * Setup the HW Rx Head and Tail Descriptor Pointers and
3170          * the Base and Length of the Rx Descriptor Ring
3171          */
3172         for (i = 0; i < adapter->num_rx_queues; i++) {
3173                 rx_ring = adapter->rx_ring[i];
3174                 rx_ring->rx_buf_len = rx_buf_len;
3175
3176                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3177                         set_ring_ps_enabled(rx_ring);
3178                 else
3179                         clear_ring_ps_enabled(rx_ring);
3180
3181                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3182                         set_ring_rsc_enabled(rx_ring);
3183                 else
3184                         clear_ring_rsc_enabled(rx_ring);
3185
3186 #ifdef IXGBE_FCOE
3187                 if (netdev->features & NETIF_F_FCOE_MTU) {
3188                         struct ixgbe_ring_feature *f;
3189                         f = &adapter->ring_feature[RING_F_FCOE];
3190                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3191                                 clear_ring_ps_enabled(rx_ring);
3192                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3193                                         rx_ring->rx_buf_len =
3194                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3195                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3196                                    !ring_is_ps_enabled(rx_ring)) {
3197                                 rx_ring->rx_buf_len =
3198                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3199                         }
3200                 }
3201 #endif /* IXGBE_FCOE */
3202         }
3203 }
3204
3205 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3206 {
3207         struct ixgbe_hw *hw = &adapter->hw;
3208         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3209
3210         switch (hw->mac.type) {
3211         case ixgbe_mac_82598EB:
3212                 /*
3213                  * For VMDq support of different descriptor types or
3214                  * buffer sizes through the use of multiple SRRCTL
3215                  * registers, RDRXCTL.MVMEN must be set to 1
3216                  *
3217                  * also, the manual doesn't mention it clearly but DCA hints
3218                  * will only use queue 0's tags unless this bit is set.  Side
3219                  * effects of setting this bit are only that SRRCTL must be
3220                  * fully programmed [0..15]
3221                  */
3222                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3223                 break;
3224         case ixgbe_mac_82599EB:
3225         case ixgbe_mac_X540:
3226                 /* Disable RSC for ACK packets */
3227                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3228                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3229                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3230                 /* hardware requires some bits to be set by default */
3231                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3232                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3233                 break;
3234         default:
3235                 /* We should do nothing since we don't know this hardware */
3236                 return;
3237         }
3238
3239         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3240 }
3241
3242 /**
3243  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3244  * @adapter: board private structure
3245  *
3246  * Configure the Rx unit of the MAC after a reset.
3247  **/
3248 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3249 {
3250         struct ixgbe_hw *hw = &adapter->hw;
3251         int i;
3252         u32 rxctrl;
3253
3254         /* disable receives while setting up the descriptors */
3255         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3256         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3257
3258         ixgbe_setup_psrtype(adapter);
3259         ixgbe_setup_rdrxctl(adapter);
3260
3261         /* Program registers for the distribution of queues */
3262         ixgbe_setup_mrqc(adapter);
3263
3264         ixgbe_set_uta(adapter);
3265
3266         /* set_rx_buffer_len must be called before ring initialization */
3267         ixgbe_set_rx_buffer_len(adapter);
3268
3269         /*
3270          * Setup the HW Rx Head and Tail Descriptor Pointers and
3271          * the Base and Length of the Rx Descriptor Ring
3272          */
3273         for (i = 0; i < adapter->num_rx_queues; i++)
3274                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3275
3276         /* disable drop enable for 82598 parts */
3277         if (hw->mac.type == ixgbe_mac_82598EB)
3278                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3279
3280         /* enable all receives */
3281         rxctrl |= IXGBE_RXCTRL_RXEN;
3282         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3283 }
3284
3285 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3286 {
3287         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3288         struct ixgbe_hw *hw = &adapter->hw;
3289         int pool_ndx = adapter->num_vfs;
3290
3291         /* add VID to filter table */
3292         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3293         set_bit(vid, adapter->active_vlans);
3294 }
3295
3296 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3297 {
3298         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3299         struct ixgbe_hw *hw = &adapter->hw;
3300         int pool_ndx = adapter->num_vfs;
3301
3302         /* remove VID from filter table */
3303         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3304         clear_bit(vid, adapter->active_vlans);
3305 }
3306
3307 /**
3308  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3309  * @adapter: driver data
3310  */
3311 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3312 {
3313         struct ixgbe_hw *hw = &adapter->hw;
3314         u32 vlnctrl;
3315
3316         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3317         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3318         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3319 }
3320
3321 /**
3322  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3323  * @adapter: driver data
3324  */
3325 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3326 {
3327         struct ixgbe_hw *hw = &adapter->hw;
3328         u32 vlnctrl;
3329
3330         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3331         vlnctrl |= IXGBE_VLNCTRL_VFE;
3332         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3333         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3334 }
3335
3336 /**
3337  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3338  * @adapter: driver data
3339  */
3340 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3341 {
3342         struct ixgbe_hw *hw = &adapter->hw;
3343         u32 vlnctrl;
3344         int i, j;
3345
3346         switch (hw->mac.type) {
3347         case ixgbe_mac_82598EB:
3348                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3349                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3350                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3351                 break;
3352         case ixgbe_mac_82599EB:
3353         case ixgbe_mac_X540:
3354                 for (i = 0; i < adapter->num_rx_queues; i++) {
3355                         j = adapter->rx_ring[i]->reg_idx;
3356                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3357                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3358                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3359                 }
3360                 break;
3361         default:
3362                 break;
3363         }
3364 }
3365
3366 /**
3367  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3368  * @adapter: driver data
3369  */
3370 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3371 {
3372         struct ixgbe_hw *hw = &adapter->hw;
3373         u32 vlnctrl;
3374         int i, j;
3375
3376         switch (hw->mac.type) {
3377         case ixgbe_mac_82598EB:
3378                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3379                 vlnctrl |= IXGBE_VLNCTRL_VME;
3380                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3381                 break;
3382         case ixgbe_mac_82599EB:
3383         case ixgbe_mac_X540:
3384                 for (i = 0; i < adapter->num_rx_queues; i++) {
3385                         j = adapter->rx_ring[i]->reg_idx;
3386                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3387                         vlnctrl |= IXGBE_RXDCTL_VME;
3388                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3389                 }
3390                 break;
3391         default:
3392                 break;
3393         }
3394 }
3395
3396 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3397 {
3398         u16 vid;
3399
3400         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3401
3402         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3403                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3404 }
3405
3406 /**
3407  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3408  * @netdev: network interface device structure
3409  *
3410  * Writes unicast address list to the RAR table.
3411  * Returns: -ENOMEM on failure/insufficient address space
3412  *                0 on no addresses written
3413  *                X on writing X addresses to the RAR table
3414  **/
3415 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3416 {
3417         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3418         struct ixgbe_hw *hw = &adapter->hw;
3419         unsigned int vfn = adapter->num_vfs;
3420         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3421         int count = 0;
3422
3423         /* return ENOMEM indicating insufficient memory for addresses */
3424         if (netdev_uc_count(netdev) > rar_entries)
3425                 return -ENOMEM;
3426
3427         if (!netdev_uc_empty(netdev) && rar_entries) {
3428                 struct netdev_hw_addr *ha;
3429                 /* return error if we do not support writing to RAR table */
3430                 if (!hw->mac.ops.set_rar)
3431                         return -ENOMEM;
3432
3433                 netdev_for_each_uc_addr(ha, netdev) {
3434                         if (!rar_entries)
3435                                 break;
3436                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3437                                             vfn, IXGBE_RAH_AV);
3438                         count++;
3439                 }
3440         }
3441         /* write the addresses in reverse order to avoid write combining */
3442         for (; rar_entries > 0 ; rar_entries--)
3443                 hw->mac.ops.clear_rar(hw, rar_entries);
3444
3445         return count;
3446 }
3447
3448 /**
3449  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3450  * @netdev: network interface device structure
3451  *
3452  * The set_rx_method entry point is called whenever the unicast/multicast
3453  * address list or the network interface flags are updated.  This routine is
3454  * responsible for configuring the hardware for proper unicast, multicast and
3455  * promiscuous mode.
3456  **/
3457 void ixgbe_set_rx_mode(struct net_device *netdev)
3458 {
3459         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3460         struct ixgbe_hw *hw = &adapter->hw;
3461         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3462         int count;
3463
3464         /* Check for Promiscuous and All Multicast modes */
3465
3466         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3467
3468         /* set all bits that we expect to always be set */
3469         fctrl |= IXGBE_FCTRL_BAM;
3470         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3471         fctrl |= IXGBE_FCTRL_PMCF;
3472
3473         /* clear the bits we are changing the status of */
3474         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3475
3476         if (netdev->flags & IFF_PROMISC) {
3477                 hw->addr_ctrl.user_set_promisc = true;
3478                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3479                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3480                 /* don't hardware filter vlans in promisc mode */
3481                 ixgbe_vlan_filter_disable(adapter);
3482         } else {
3483                 if (netdev->flags & IFF_ALLMULTI) {
3484                         fctrl |= IXGBE_FCTRL_MPE;
3485                         vmolr |= IXGBE_VMOLR_MPE;
3486                 } else {
3487                         /*
3488                          * Write addresses to the MTA, if the attempt fails
3489                          * then we should just turn on promiscuous mode so
3490                          * that we can at least receive multicast traffic
3491                          */
3492                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3493                         vmolr |= IXGBE_VMOLR_ROMPE;
3494                 }
3495                 ixgbe_vlan_filter_enable(adapter);
3496                 hw->addr_ctrl.user_set_promisc = false;
3497                 /*
3498                  * Write addresses to available RAR registers, if there is not
3499                  * sufficient space to store all the addresses then enable
3500                  * unicast promiscuous mode
3501                  */
3502                 count = ixgbe_write_uc_addr_list(netdev);
3503                 if (count < 0) {
3504                         fctrl |= IXGBE_FCTRL_UPE;
3505                         vmolr |= IXGBE_VMOLR_ROPE;
3506                 }
3507         }
3508
3509         if (adapter->num_vfs) {
3510                 ixgbe_restore_vf_multicasts(adapter);
3511                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3512                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3513                            IXGBE_VMOLR_ROPE);
3514                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3515         }
3516
3517         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3518
3519         if (netdev->features & NETIF_F_HW_VLAN_RX)
3520                 ixgbe_vlan_strip_enable(adapter);
3521         else
3522                 ixgbe_vlan_strip_disable(adapter);
3523 }
3524
3525 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3526 {
3527         int q_idx;
3528         struct ixgbe_q_vector *q_vector;
3529         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3530
3531         /* legacy and MSI only use one vector */
3532         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3533                 q_vectors = 1;
3534
3535         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3536                 struct napi_struct *napi;
3537                 q_vector = adapter->q_vector[q_idx];
3538                 napi = &q_vector->napi;
3539                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3540                         if (!q_vector->rx.count || !q_vector->tx.count) {
3541                                 if (q_vector->tx.count == 1)
3542                                         napi->poll = &ixgbe_clean_txonly;
3543                                 else if (q_vector->rx.count == 1)
3544                                         napi->poll = &ixgbe_clean_rxonly;
3545                         }
3546                 }
3547
3548                 napi_enable(napi);
3549         }
3550 }
3551
3552 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3553 {
3554         int q_idx;
3555         struct ixgbe_q_vector *q_vector;
3556         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3557
3558         /* legacy and MSI only use one vector */
3559         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3560                 q_vectors = 1;
3561
3562         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3563                 q_vector = adapter->q_vector[q_idx];
3564                 napi_disable(&q_vector->napi);
3565         }
3566 }
3567
3568 #ifdef CONFIG_IXGBE_DCB
3569 /*
3570  * ixgbe_configure_dcb - Configure DCB hardware
3571  * @adapter: ixgbe adapter struct
3572  *
3573  * This is called by the driver on open to configure the DCB hardware.
3574  * This is also called by the gennetlink interface when reconfiguring
3575  * the DCB state.
3576  */
3577 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3578 {
3579         struct ixgbe_hw *hw = &adapter->hw;
3580         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3581
3582         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3583                 if (hw->mac.type == ixgbe_mac_82598EB)
3584                         netif_set_gso_max_size(adapter->netdev, 65536);
3585                 return;
3586         }
3587
3588         if (hw->mac.type == ixgbe_mac_82598EB)
3589                 netif_set_gso_max_size(adapter->netdev, 32768);
3590
3591
3592         /* Enable VLAN tag insert/strip */
3593         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3594
3595         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3596
3597         /* reconfigure the hardware */
3598         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3599 #ifdef CONFIG_FCOE
3600                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3601                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3602 #endif
3603                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3604                                                 DCB_TX_CONFIG);
3605                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3606                                                 DCB_RX_CONFIG);
3607                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3608         } else {
3609                 struct net_device *dev = adapter->netdev;
3610
3611                 if (adapter->ixgbe_ieee_ets)
3612                         dev->dcbnl_ops->ieee_setets(dev,
3613                                                     adapter->ixgbe_ieee_ets);
3614                 if (adapter->ixgbe_ieee_pfc)
3615                         dev->dcbnl_ops->ieee_setpfc(dev,
3616                                                     adapter->ixgbe_ieee_pfc);
3617         }
3618
3619         /* Enable RSS Hash per TC */
3620         if (hw->mac.type != ixgbe_mac_82598EB) {
3621                 int i;
3622                 u32 reg = 0;
3623
3624                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3625                         u8 msb = 0;
3626                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3627
3628                         while (cnt >>= 1)
3629                                 msb++;
3630
3631                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3632                 }
3633                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3634         }
3635 }
3636
3637 #endif
3638
3639 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3640 {
3641         int hdrm = 0;
3642         int num_tc = netdev_get_num_tc(adapter->netdev);
3643         struct ixgbe_hw *hw = &adapter->hw;
3644
3645         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3646             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3647                 hdrm = 64 << adapter->fdir_pballoc;
3648
3649         hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3650 }
3651
3652 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3653 {
3654         struct ixgbe_hw *hw = &adapter->hw;
3655         struct hlist_node *node, *node2;
3656         struct ixgbe_fdir_filter *filter;
3657
3658         spin_lock(&adapter->fdir_perfect_lock);
3659
3660         if (!hlist_empty(&adapter->fdir_filter_list))
3661                 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3662
3663         hlist_for_each_entry_safe(filter, node, node2,
3664                                   &adapter->fdir_filter_list, fdir_node) {
3665                 ixgbe_fdir_write_perfect_filter_82599(hw,
3666                                 &filter->filter,
3667                                 filter->sw_idx,
3668                                 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3669                                 IXGBE_FDIR_DROP_QUEUE :
3670                                 adapter->rx_ring[filter->action]->reg_idx);
3671         }
3672
3673         spin_unlock(&adapter->fdir_perfect_lock);
3674 }
3675
3676 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3677 {
3678         struct net_device *netdev = adapter->netdev;
3679         struct ixgbe_hw *hw = &adapter->hw;
3680         int i;
3681
3682         ixgbe_configure_pb(adapter);
3683 #ifdef CONFIG_IXGBE_DCB
3684         ixgbe_configure_dcb(adapter);
3685 #endif
3686
3687         ixgbe_set_rx_mode(netdev);
3688         ixgbe_restore_vlan(adapter);
3689
3690 #ifdef IXGBE_FCOE
3691         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3692                 ixgbe_configure_fcoe(adapter);
3693
3694 #endif /* IXGBE_FCOE */
3695         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3696                 for (i = 0; i < adapter->num_tx_queues; i++)
3697                         adapter->tx_ring[i]->atr_sample_rate =
3698                                                        adapter->atr_sample_rate;
3699                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3700         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3701                 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3702                                               adapter->fdir_pballoc);
3703                 ixgbe_fdir_filter_restore(adapter);
3704         }
3705         ixgbe_configure_virtualization(adapter);
3706
3707         ixgbe_configure_tx(adapter);
3708         ixgbe_configure_rx(adapter);
3709 }
3710
3711 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3712 {
3713         switch (hw->phy.type) {
3714         case ixgbe_phy_sfp_avago:
3715         case ixgbe_phy_sfp_ftl:
3716         case ixgbe_phy_sfp_intel:
3717         case ixgbe_phy_sfp_unknown:
3718         case ixgbe_phy_sfp_passive_tyco:
3719         case ixgbe_phy_sfp_passive_unknown:
3720         case ixgbe_phy_sfp_active_unknown:
3721         case ixgbe_phy_sfp_ftl_active:
3722                 return true;
3723         default:
3724                 return false;
3725         }
3726 }
3727
3728 /**
3729  * ixgbe_sfp_link_config - set up SFP+ link
3730  * @adapter: pointer to private adapter struct
3731  **/
3732 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3733 {
3734         /*
3735          * We are assuming the worst case scenerio here, and that
3736          * is that an SFP was inserted/removed after the reset
3737          * but before SFP detection was enabled.  As such the best
3738          * solution is to just start searching as soon as we start
3739          */
3740         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3741                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3742
3743         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3744 }
3745
3746 /**
3747  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3748  * @hw: pointer to private hardware struct
3749  *
3750  * Returns 0 on success, negative on failure
3751  **/
3752 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3753 {
3754         u32 autoneg;
3755         bool negotiation, link_up = false;
3756         u32 ret = IXGBE_ERR_LINK_SETUP;
3757
3758         if (hw->mac.ops.check_link)
3759                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3760
3761         if (ret)
3762                 goto link_cfg_out;
3763
3764         autoneg = hw->phy.autoneg_advertised;
3765         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3766                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3767                                                         &negotiation);
3768         if (ret)
3769                 goto link_cfg_out;
3770
3771         if (hw->mac.ops.setup_link)
3772                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3773 link_cfg_out:
3774         return ret;
3775 }
3776
3777 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3778 {
3779         struct ixgbe_hw *hw = &adapter->hw;
3780         u32 gpie = 0;
3781
3782         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3783                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3784                        IXGBE_GPIE_OCD;
3785                 gpie |= IXGBE_GPIE_EIAME;
3786                 /*
3787                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3788                  * this saves a register write for every interrupt
3789                  */
3790                 switch (hw->mac.type) {
3791                 case ixgbe_mac_82598EB:
3792                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3793                         break;
3794                 case ixgbe_mac_82599EB:
3795                 case ixgbe_mac_X540:
3796                 default:
3797                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3798                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3799                         break;
3800                 }
3801         } else {
3802                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3803                  * specifically only auto mask tx and rx interrupts */
3804                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3805         }
3806
3807         /* XXX: to interrupt immediately for EICS writes, enable this */
3808         /* gpie |= IXGBE_GPIE_EIMEN; */
3809
3810         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3811                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3812                 gpie |= IXGBE_GPIE_VTMODE_64;
3813         }
3814
3815         /* Enable fan failure interrupt */
3816         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3817                 gpie |= IXGBE_SDP1_GPIEN;
3818
3819         if (hw->mac.type == ixgbe_mac_82599EB) {
3820                 gpie |= IXGBE_SDP1_GPIEN;
3821                 gpie |= IXGBE_SDP2_GPIEN;
3822         }
3823
3824         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3825 }
3826
3827 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3828 {
3829         struct ixgbe_hw *hw = &adapter->hw;
3830         int err;
3831         u32 ctrl_ext;
3832
3833         ixgbe_get_hw_control(adapter);
3834         ixgbe_setup_gpie(adapter);
3835
3836         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3837                 ixgbe_configure_msix(adapter);
3838         else
3839                 ixgbe_configure_msi_and_legacy(adapter);
3840
3841         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3842         if (hw->mac.ops.enable_tx_laser &&
3843             ((hw->phy.multispeed_fiber) ||
3844              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3845               (hw->mac.type == ixgbe_mac_82599EB))))
3846                 hw->mac.ops.enable_tx_laser(hw);
3847
3848         clear_bit(__IXGBE_DOWN, &adapter->state);
3849         ixgbe_napi_enable_all(adapter);
3850
3851         if (ixgbe_is_sfp(hw)) {
3852                 ixgbe_sfp_link_config(adapter);
3853         } else {
3854                 err = ixgbe_non_sfp_link_config(hw);
3855                 if (err)
3856                         e_err(probe, "link_config FAILED %d\n", err);
3857         }
3858
3859         /* clear any pending interrupts, may auto mask */
3860         IXGBE_READ_REG(hw, IXGBE_EICR);
3861         ixgbe_irq_enable(adapter, true, true);
3862
3863         /*
3864          * If this adapter has a fan, check to see if we had a failure
3865          * before we enabled the interrupt.
3866          */
3867         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3868                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3869                 if (esdp & IXGBE_ESDP_SDP1)
3870                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3871         }
3872
3873         /* enable transmits */
3874         netif_tx_start_all_queues(adapter->netdev);
3875
3876         /* bring the link up in the watchdog, this could race with our first
3877          * link up interrupt but shouldn't be a problem */
3878         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3879         adapter->link_check_timeout = jiffies;
3880         mod_timer(&adapter->service_timer, jiffies);
3881
3882         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3883         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3884         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3885         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3886
3887         return 0;
3888 }
3889
3890 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3891 {
3892         WARN_ON(in_interrupt());
3893         /* put off any impending NetWatchDogTimeout */
3894         adapter->netdev->trans_start = jiffies;
3895
3896         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3897                 usleep_range(1000, 2000);
3898         ixgbe_down(adapter);
3899         /*
3900          * If SR-IOV enabled then wait a bit before bringing the adapter
3901          * back up to give the VFs time to respond to the reset.  The
3902          * two second wait is based upon the watchdog timer cycle in
3903          * the VF driver.
3904          */
3905         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3906                 msleep(2000);
3907         ixgbe_up(adapter);
3908         clear_bit(__IXGBE_RESETTING, &adapter->state);
3909 }
3910
3911 int ixgbe_up(struct ixgbe_adapter *adapter)
3912 {
3913         /* hardware has been reset, we need to reload some things */
3914         ixgbe_configure(adapter);
3915
3916         return ixgbe_up_complete(adapter);
3917 }
3918
3919 void ixgbe_reset(struct ixgbe_adapter *adapter)
3920 {
3921         struct ixgbe_hw *hw = &adapter->hw;
3922         int err;
3923
3924         /* lock SFP init bit to prevent race conditions with the watchdog */
3925         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3926                 usleep_range(1000, 2000);
3927
3928         /* clear all SFP and link config related flags while holding SFP_INIT */
3929         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3930                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3931         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3932
3933         err = hw->mac.ops.init_hw(hw);
3934         switch (err) {
3935         case 0:
3936         case IXGBE_ERR_SFP_NOT_PRESENT:
3937         case IXGBE_ERR_SFP_NOT_SUPPORTED:
3938                 break;
3939         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3940                 e_dev_err("master disable timed out\n");
3941                 break;
3942         case IXGBE_ERR_EEPROM_VERSION:
3943                 /* We are running on a pre-production device, log a warning */
3944                 e_dev_warn("This device is a pre-production adapter/LOM. "
3945                            "Please be aware there may be issuesassociated with "
3946                            "your hardware.  If you are experiencing problems "
3947                            "please contact your Intel or hardware "
3948                            "representative who provided you with this "
3949                            "hardware.\n");
3950                 break;
3951         default:
3952                 e_dev_err("Hardware Error: %d\n", err);
3953         }
3954
3955         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3956
3957         /* reprogram the RAR[0] in case user changed it. */
3958         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3959                             IXGBE_RAH_AV);
3960 }
3961
3962 /**
3963  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3964  * @rx_ring: ring to free buffers from
3965  **/
3966 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3967 {
3968         struct device *dev = rx_ring->dev;
3969         unsigned long size;
3970         u16 i;
3971
3972         /* ring already cleared, nothing to do */
3973         if (!rx_ring->rx_buffer_info)
3974                 return;
3975
3976         /* Free all the Rx ring sk_buffs */
3977         for (i = 0; i < rx_ring->count; i++) {
3978                 struct ixgbe_rx_buffer *rx_buffer_info;
3979
3980                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3981                 if (rx_buffer_info->dma) {
3982                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3983                                          rx_ring->rx_buf_len,
3984                                          DMA_FROM_DEVICE);
3985                         rx_buffer_info->dma = 0;
3986                 }
3987                 if (rx_buffer_info->skb) {
3988                         struct sk_buff *skb = rx_buffer_info->skb;
3989                         rx_buffer_info->skb = NULL;
3990                         do {
3991                                 struct sk_buff *this = skb;
3992                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3993                                         dma_unmap_single(dev,
3994                                                          IXGBE_RSC_CB(this)->dma,
3995                                                          rx_ring->rx_buf_len,
3996                                                          DMA_FROM_DEVICE);
3997                                         IXGBE_RSC_CB(this)->dma = 0;
3998                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3999                                 }
4000                                 skb = skb->prev;
4001                                 dev_kfree_skb(this);
4002                         } while (skb);
4003                 }
4004                 if (!rx_buffer_info->page)
4005                         continue;
4006                 if (rx_buffer_info->page_dma) {
4007                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4008                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4009                         rx_buffer_info->page_dma = 0;
4010                 }
4011                 put_page(rx_buffer_info->page);
4012                 rx_buffer_info->page = NULL;
4013                 rx_buffer_info->page_offset = 0;
4014         }
4015
4016         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4017         memset(rx_ring->rx_buffer_info, 0, size);
4018
4019         /* Zero out the descriptor ring */
4020         memset(rx_ring->desc, 0, rx_ring->size);
4021
4022         rx_ring->next_to_clean = 0;
4023         rx_ring->next_to_use = 0;
4024 }
4025
4026 /**
4027  * ixgbe_clean_tx_ring - Free Tx Buffers
4028  * @tx_ring: ring to be cleaned
4029  **/
4030 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4031 {
4032         struct ixgbe_tx_buffer *tx_buffer_info;
4033         unsigned long size;
4034         u16 i;
4035
4036         /* ring already cleared, nothing to do */
4037         if (!tx_ring->tx_buffer_info)
4038                 return;
4039
4040         /* Free all the Tx ring sk_buffs */
4041         for (i = 0; i < tx_ring->count; i++) {
4042                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4043                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4044         }
4045
4046         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4047         memset(tx_ring->tx_buffer_info, 0, size);
4048
4049         /* Zero out the descriptor ring */
4050         memset(tx_ring->desc, 0, tx_ring->size);
4051
4052         tx_ring->next_to_use = 0;
4053         tx_ring->next_to_clean = 0;
4054 }
4055
4056 /**
4057  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4058  * @adapter: board private structure
4059  **/
4060 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4061 {
4062         int i;
4063
4064         for (i = 0; i < adapter->num_rx_queues; i++)
4065                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4066 }
4067
4068 /**
4069  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4070  * @adapter: board private structure
4071  **/
4072 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4073 {
4074         int i;
4075
4076         for (i = 0; i < adapter->num_tx_queues; i++)
4077                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4078 }
4079
4080 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4081 {
4082         struct hlist_node *node, *node2;
4083         struct ixgbe_fdir_filter *filter;
4084
4085         spin_lock(&adapter->fdir_perfect_lock);
4086
4087         hlist_for_each_entry_safe(filter, node, node2,
4088                                   &adapter->fdir_filter_list, fdir_node) {
4089                 hlist_del(&filter->fdir_node);
4090                 kfree(filter);
4091         }
4092         adapter->fdir_filter_count = 0;
4093
4094         spin_unlock(&adapter->fdir_perfect_lock);
4095 }
4096
4097 void ixgbe_down(struct ixgbe_adapter *adapter)
4098 {
4099         struct net_device *netdev = adapter->netdev;
4100         struct ixgbe_hw *hw = &adapter->hw;
4101         u32 rxctrl;
4102         int i;
4103         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4104
4105         /* signal that we are down to the interrupt handler */
4106         set_bit(__IXGBE_DOWN, &adapter->state);
4107
4108         /* disable receives */
4109         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4110         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4111
4112         /* disable all enabled rx queues */
4113         for (i = 0; i < adapter->num_rx_queues; i++)
4114                 /* this call also flushes the previous write */
4115                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4116
4117         usleep_range(10000, 20000);
4118
4119         netif_tx_stop_all_queues(netdev);
4120
4121         /* call carrier off first to avoid false dev_watchdog timeouts */
4122         netif_carrier_off(netdev);
4123         netif_tx_disable(netdev);
4124
4125         ixgbe_irq_disable(adapter);
4126
4127         ixgbe_napi_disable_all(adapter);
4128
4129         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4130                              IXGBE_FLAG2_RESET_REQUESTED);
4131         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4132
4133         del_timer_sync(&adapter->service_timer);
4134
4135         /* disable receive for all VFs and wait one second */
4136         if (adapter->num_vfs) {
4137                 /* ping all the active vfs to let them know we are going down */
4138                 ixgbe_ping_all_vfs(adapter);
4139
4140                 /* Disable all VFTE/VFRE TX/RX */
4141                 ixgbe_disable_tx_rx(adapter);
4142
4143                 /* Mark all the VFs as inactive */
4144                 for (i = 0 ; i < adapter->num_vfs; i++)
4145                         adapter->vfinfo[i].clear_to_send = 0;
4146         }
4147
4148         /* Cleanup the affinity_hint CPU mask memory and callback */
4149         for (i = 0; i < num_q_vectors; i++) {
4150                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4151                 /* clear the affinity_mask in the IRQ descriptor */
4152                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4153                 /* release the CPU mask memory */
4154                 free_cpumask_var(q_vector->affinity_mask);
4155         }
4156
4157         /* disable transmits in the hardware now that interrupts are off */
4158         for (i = 0; i < adapter->num_tx_queues; i++) {
4159                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4160                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4161         }
4162
4163         /* Disable the Tx DMA engine on 82599 and X540 */
4164         switch (hw->mac.type) {
4165         case ixgbe_mac_82599EB:
4166         case ixgbe_mac_X540:
4167                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4168                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4169                                  ~IXGBE_DMATXCTL_TE));
4170                 break;
4171         default:
4172                 break;
4173         }
4174
4175         if (!pci_channel_offline(adapter->pdev))
4176                 ixgbe_reset(adapter);
4177
4178         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4179         if (hw->mac.ops.disable_tx_laser &&
4180             ((hw->phy.multispeed_fiber) ||
4181              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4182               (hw->mac.type == ixgbe_mac_82599EB))))
4183                 hw->mac.ops.disable_tx_laser(hw);
4184
4185         ixgbe_clean_all_tx_rings(adapter);
4186         ixgbe_clean_all_rx_rings(adapter);
4187
4188 #ifdef CONFIG_IXGBE_DCA
4189         /* since we reset the hardware DCA settings were cleared */
4190         ixgbe_setup_dca(adapter);
4191 #endif
4192 }
4193
4194 /**
4195  * ixgbe_poll - NAPI Rx polling callback
4196  * @napi: structure for representing this polling device
4197  * @budget: how many packets driver is allowed to clean
4198  *
4199  * This function is used for legacy and MSI, NAPI mode
4200  **/
4201 static int ixgbe_poll(struct napi_struct *napi, int budget)
4202 {
4203         struct ixgbe_q_vector *q_vector =
4204                                 container_of(napi, struct ixgbe_q_vector, napi);
4205         struct ixgbe_adapter *adapter = q_vector->adapter;
4206         int tx_clean_complete, work_done = 0;
4207
4208 #ifdef CONFIG_IXGBE_DCA
4209         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4210                 ixgbe_update_dca(q_vector);
4211 #endif
4212
4213         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4214         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4215
4216         if (!tx_clean_complete)
4217                 work_done = budget;
4218
4219         /* If budget not fully consumed, exit the polling mode */
4220         if (work_done < budget) {
4221                 napi_complete(napi);
4222                 if (adapter->rx_itr_setting & 1)
4223                         ixgbe_set_itr(q_vector);
4224                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4225                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4226         }
4227         return work_done;
4228 }
4229
4230 /**
4231  * ixgbe_tx_timeout - Respond to a Tx Hang
4232  * @netdev: network interface device structure
4233  **/
4234 static void ixgbe_tx_timeout(struct net_device *netdev)
4235 {
4236         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4237
4238         /* Do the reset outside of interrupt context */
4239         ixgbe_tx_timeout_reset(adapter);
4240 }
4241
4242 /**
4243  * ixgbe_set_rss_queues: Allocate queues for RSS
4244  * @adapter: board private structure to initialize
4245  *
4246  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4247  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4248  *
4249  **/
4250 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4251 {
4252         bool ret = false;
4253         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4254
4255         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4256                 f->mask = 0xF;
4257                 adapter->num_rx_queues = f->indices;
4258                 adapter->num_tx_queues = f->indices;
4259                 ret = true;
4260         } else {
4261                 ret = false;
4262         }
4263
4264         return ret;
4265 }
4266
4267 /**
4268  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4269  * @adapter: board private structure to initialize
4270  *
4271  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4272  * to the original CPU that initiated the Tx session.  This runs in addition
4273  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4274  * Rx load across CPUs using RSS.
4275  *
4276  **/
4277 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4278 {
4279         bool ret = false;
4280         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4281
4282         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4283         f_fdir->mask = 0;
4284
4285         /* Flow Director must have RSS enabled */
4286         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4287             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4288                 adapter->num_tx_queues = f_fdir->indices;
4289                 adapter->num_rx_queues = f_fdir->indices;
4290                 ret = true;
4291         } else {
4292                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4293         }
4294         return ret;
4295 }
4296
4297 #ifdef IXGBE_FCOE
4298 /**
4299  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4300  * @adapter: board private structure to initialize
4301  *
4302  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4303  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4304  * rx queues out of the max number of rx queues, instead, it is used as the
4305  * index of the first rx queue used by FCoE.
4306  *
4307  **/
4308 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4309 {
4310         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4311
4312         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4313                 return false;
4314
4315         f->indices = min((int)num_online_cpus(), f->indices);
4316
4317         adapter->num_rx_queues = 1;
4318         adapter->num_tx_queues = 1;
4319
4320         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4321                 e_info(probe, "FCoE enabled with RSS\n");
4322                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4323                         ixgbe_set_fdir_queues(adapter);
4324                 else
4325                         ixgbe_set_rss_queues(adapter);
4326         }
4327
4328         /* adding FCoE rx rings to the end */
4329         f->mask = adapter->num_rx_queues;
4330         adapter->num_rx_queues += f->indices;
4331         adapter->num_tx_queues += f->indices;
4332
4333         return true;
4334 }
4335 #endif /* IXGBE_FCOE */
4336
4337 /* Artificial max queue cap per traffic class in DCB mode */
4338 #define DCB_QUEUE_CAP 8
4339
4340 #ifdef CONFIG_IXGBE_DCB
4341 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4342 {
4343         int per_tc_q, q, i, offset = 0;
4344         struct net_device *dev = adapter->netdev;
4345         int tcs = netdev_get_num_tc(dev);
4346
4347         if (!tcs)
4348                 return false;
4349
4350         /* Map queue offset and counts onto allocated tx queues */
4351         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4352         q = min((int)num_online_cpus(), per_tc_q);
4353
4354         for (i = 0; i < tcs; i++) {
4355                 netdev_set_prio_tc_map(dev, i, i);
4356                 netdev_set_tc_queue(dev, i, q, offset);
4357                 offset += q;
4358         }
4359
4360         adapter->num_tx_queues = q * tcs;
4361         adapter->num_rx_queues = q * tcs;
4362
4363 #ifdef IXGBE_FCOE
4364         /* FCoE enabled queues require special configuration indexed
4365          * by feature specific indices and mask. Here we map FCoE
4366          * indices onto the DCB queue pairs allowing FCoE to own
4367          * configuration later.
4368          */
4369         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4370                 int tc;
4371                 struct ixgbe_ring_feature *f =
4372                                         &adapter->ring_feature[RING_F_FCOE];
4373
4374                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4375                 f->indices = dev->tc_to_txq[tc].count;
4376                 f->mask = dev->tc_to_txq[tc].offset;
4377         }
4378 #endif
4379
4380         return true;
4381 }
4382 #endif
4383
4384 /**
4385  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4386  * @adapter: board private structure to initialize
4387  *
4388  * IOV doesn't actually use anything, so just NAK the
4389  * request for now and let the other queue routines
4390  * figure out what to do.
4391  */
4392 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4393 {
4394         return false;
4395 }
4396
4397 /*
4398  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4399  * @adapter: board private structure to initialize
4400  *
4401  * This is the top level queue allocation routine.  The order here is very
4402  * important, starting with the "most" number of features turned on at once,
4403  * and ending with the smallest set of features.  This way large combinations
4404  * can be allocated if they're turned on, and smaller combinations are the
4405  * fallthrough conditions.
4406  *
4407  **/
4408 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4409 {
4410         /* Start with base case */
4411         adapter->num_rx_queues = 1;
4412         adapter->num_tx_queues = 1;
4413         adapter->num_rx_pools = adapter->num_rx_queues;
4414         adapter->num_rx_queues_per_pool = 1;
4415
4416         if (ixgbe_set_sriov_queues(adapter))
4417                 goto done;
4418
4419 #ifdef CONFIG_IXGBE_DCB
4420         if (ixgbe_set_dcb_queues(adapter))
4421                 goto done;
4422
4423 #endif
4424 #ifdef IXGBE_FCOE
4425         if (ixgbe_set_fcoe_queues(adapter))
4426                 goto done;
4427
4428 #endif /* IXGBE_FCOE */
4429         if (ixgbe_set_fdir_queues(adapter))
4430                 goto done;
4431
4432         if (ixgbe_set_rss_queues(adapter))
4433                 goto done;
4434
4435         /* fallback to base case */
4436         adapter->num_rx_queues = 1;
4437         adapter->num_tx_queues = 1;
4438
4439 done:
4440         /* Notify the stack of the (possibly) reduced queue counts. */
4441         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4442         return netif_set_real_num_rx_queues(adapter->netdev,
4443                                             adapter->num_rx_queues);
4444 }
4445
4446 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4447                                        int vectors)
4448 {
4449         int err, vector_threshold;
4450
4451         /* We'll want at least 3 (vector_threshold):
4452          * 1) TxQ[0] Cleanup
4453          * 2) RxQ[0] Cleanup
4454          * 3) Other (Link Status Change, etc.)
4455          * 4) TCP Timer (optional)
4456          */
4457         vector_threshold = MIN_MSIX_COUNT;
4458
4459         /* The more we get, the more we will assign to Tx/Rx Cleanup
4460          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4461          * Right now, we simply care about how many we'll get; we'll
4462          * set them up later while requesting irq's.
4463          */
4464         while (vectors >= vector_threshold) {
4465                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4466                                       vectors);
4467                 if (!err) /* Success in acquiring all requested vectors. */
4468                         break;
4469                 else if (err < 0)
4470                         vectors = 0; /* Nasty failure, quit now */
4471                 else /* err == number of vectors we should try again with */
4472                         vectors = err;
4473         }
4474
4475         if (vectors < vector_threshold) {
4476                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4477                  * This just means we'll go with either a single MSI
4478                  * vector or fall back to legacy interrupts.
4479                  */
4480                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4481                              "Unable to allocate MSI-X interrupts\n");
4482                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4483                 kfree(adapter->msix_entries);
4484                 adapter->msix_entries = NULL;
4485         } else {
4486                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4487                 /*
4488                  * Adjust for only the vectors we'll use, which is minimum
4489                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4490                  * vectors we were allocated.
4491                  */
4492                 adapter->num_msix_vectors = min(vectors,
4493                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4494         }
4495 }
4496
4497 /**
4498  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4499  * @adapter: board private structure to initialize
4500  *
4501  * Cache the descriptor ring offsets for RSS to the assigned rings.
4502  *
4503  **/
4504 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4505 {
4506         int i;
4507
4508         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4509                 return false;
4510
4511         for (i = 0; i < adapter->num_rx_queues; i++)
4512                 adapter->rx_ring[i]->reg_idx = i;
4513         for (i = 0; i < adapter->num_tx_queues; i++)
4514                 adapter->tx_ring[i]->reg_idx = i;
4515
4516         return true;
4517 }
4518
4519 #ifdef CONFIG_IXGBE_DCB
4520
4521 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4522 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4523                                     unsigned int *tx, unsigned int *rx)
4524 {
4525         struct net_device *dev = adapter->netdev;
4526         struct ixgbe_hw *hw = &adapter->hw;
4527         u8 num_tcs = netdev_get_num_tc(dev);
4528
4529         *tx = 0;
4530         *rx = 0;
4531
4532         switch (hw->mac.type) {
4533         case ixgbe_mac_82598EB:
4534                 *tx = tc << 2;
4535                 *rx = tc << 3;
4536                 break;
4537         case ixgbe_mac_82599EB:
4538         case ixgbe_mac_X540:
4539                 if (num_tcs == 8) {
4540                         if (tc < 3) {
4541                                 *tx = tc << 5;
4542                                 *rx = tc << 4;
4543                         } else if (tc <  5) {
4544                                 *tx = ((tc + 2) << 4);
4545                                 *rx = tc << 4;
4546                         } else if (tc < num_tcs) {
4547                                 *tx = ((tc + 8) << 3);
4548                                 *rx = tc << 4;
4549                         }
4550                 } else if (num_tcs == 4) {
4551                         *rx =  tc << 5;
4552                         switch (tc) {
4553                         case 0:
4554                                 *tx =  0;
4555                                 break;
4556                         case 1:
4557                                 *tx = 64;
4558                                 break;
4559                         case 2:
4560                                 *tx = 96;
4561                                 break;
4562                         case 3:
4563                                 *tx = 112;
4564                                 break;
4565                         default:
4566                                 break;
4567                         }
4568                 }
4569                 break;
4570         default:
4571                 break;
4572         }
4573 }
4574
4575 /**
4576  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4577  * @adapter: board private structure to initialize
4578  *
4579  * Cache the descriptor ring offsets for DCB to the assigned rings.
4580  *
4581  **/
4582 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4583 {
4584         struct net_device *dev = adapter->netdev;
4585         int i, j, k;
4586         u8 num_tcs = netdev_get_num_tc(dev);
4587
4588         if (!num_tcs)
4589                 return false;
4590
4591         for (i = 0, k = 0; i < num_tcs; i++) {
4592                 unsigned int tx_s, rx_s;
4593                 u16 count = dev->tc_to_txq[i].count;
4594
4595                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4596                 for (j = 0; j < count; j++, k++) {
4597                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4598                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4599                         adapter->tx_ring[k]->dcb_tc = i;
4600                         adapter->rx_ring[k]->dcb_tc = i;
4601                 }
4602         }
4603
4604         return true;
4605 }
4606 #endif
4607
4608 /**
4609  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4610  * @adapter: board private structure to initialize
4611  *
4612  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4613  *
4614  **/
4615 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4616 {
4617         int i;
4618         bool ret = false;
4619
4620         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4621             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4622                 for (i = 0; i < adapter->num_rx_queues; i++)
4623                         adapter->rx_ring[i]->reg_idx = i;
4624                 for (i = 0; i < adapter->num_tx_queues; i++)
4625                         adapter->tx_ring[i]->reg_idx = i;
4626                 ret = true;
4627         }
4628
4629         return ret;
4630 }
4631
4632 #ifdef IXGBE_FCOE
4633 /**
4634  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4635  * @adapter: board private structure to initialize
4636  *
4637  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4638  *
4639  */
4640 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4641 {
4642         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4643         int i;
4644         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4645
4646         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4647                 return false;
4648
4649         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4650                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4651                         ixgbe_cache_ring_fdir(adapter);
4652                 else
4653                         ixgbe_cache_ring_rss(adapter);
4654
4655                 fcoe_rx_i = f->mask;
4656                 fcoe_tx_i = f->mask;
4657         }
4658         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4659                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4660                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4661         }
4662         return true;
4663 }
4664
4665 #endif /* IXGBE_FCOE */
4666 /**
4667  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4668  * @adapter: board private structure to initialize
4669  *
4670  * SR-IOV doesn't use any descriptor rings but changes the default if
4671  * no other mapping is used.
4672  *
4673  */
4674 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4675 {
4676         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4677         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4678         if (adapter->num_vfs)
4679                 return true;
4680         else
4681                 return false;
4682 }
4683
4684 /**
4685  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4686  * @adapter: board private structure to initialize
4687  *
4688  * Once we know the feature-set enabled for the device, we'll cache
4689  * the register offset the descriptor ring is assigned to.
4690  *
4691  * Note, the order the various feature calls is important.  It must start with
4692  * the "most" features enabled at the same time, then trickle down to the
4693  * least amount of features turned on at once.
4694  **/
4695 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4696 {
4697         /* start with default case */
4698         adapter->rx_ring[0]->reg_idx = 0;
4699         adapter->tx_ring[0]->reg_idx = 0;
4700
4701         if (ixgbe_cache_ring_sriov(adapter))
4702                 return;
4703
4704 #ifdef CONFIG_IXGBE_DCB
4705         if (ixgbe_cache_ring_dcb(adapter))
4706                 return;
4707 #endif
4708
4709 #ifdef IXGBE_FCOE
4710         if (ixgbe_cache_ring_fcoe(adapter))
4711                 return;
4712 #endif /* IXGBE_FCOE */
4713
4714         if (ixgbe_cache_ring_fdir(adapter))
4715                 return;
4716
4717         if (ixgbe_cache_ring_rss(adapter))
4718                 return;
4719 }
4720
4721 /**
4722  * ixgbe_alloc_queues - Allocate memory for all rings
4723  * @adapter: board private structure to initialize
4724  *
4725  * We allocate one ring per queue at run-time since we don't know the
4726  * number of queues at compile-time.  The polling_netdev array is
4727  * intended for Multiqueue, but should work fine with a single queue.
4728  **/
4729 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4730 {
4731         int rx = 0, tx = 0, nid = adapter->node;
4732
4733         if (nid < 0 || !node_online(nid))
4734                 nid = first_online_node;
4735
4736         for (; tx < adapter->num_tx_queues; tx++) {
4737                 struct ixgbe_ring *ring;
4738
4739                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4740                 if (!ring)
4741                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4742                 if (!ring)
4743                         goto err_allocation;
4744                 ring->count = adapter->tx_ring_count;
4745                 ring->queue_index = tx;
4746                 ring->numa_node = nid;
4747                 ring->dev = &adapter->pdev->dev;
4748                 ring->netdev = adapter->netdev;
4749
4750                 adapter->tx_ring[tx] = ring;
4751         }
4752
4753         for (; rx < adapter->num_rx_queues; rx++) {
4754                 struct ixgbe_ring *ring;
4755
4756                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4757                 if (!ring)
4758                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4759                 if (!ring)
4760                         goto err_allocation;
4761                 ring->count = adapter->rx_ring_count;
4762                 ring->queue_index = rx;
4763                 ring->numa_node = nid;
4764                 ring->dev = &adapter->pdev->dev;
4765                 ring->netdev = adapter->netdev;
4766
4767                 adapter->rx_ring[rx] = ring;
4768         }
4769
4770         ixgbe_cache_ring_register(adapter);
4771
4772         return 0;
4773
4774 err_allocation:
4775         while (tx)
4776                 kfree(adapter->tx_ring[--tx]);
4777
4778         while (rx)
4779                 kfree(adapter->rx_ring[--rx]);
4780         return -ENOMEM;
4781 }
4782
4783 /**
4784  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4785  * @adapter: board private structure to initialize
4786  *
4787  * Attempt to configure the interrupts using the best available
4788  * capabilities of the hardware and the kernel.
4789  **/
4790 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4791 {
4792         struct ixgbe_hw *hw = &adapter->hw;
4793         int err = 0;
4794         int vector, v_budget;
4795
4796         /*
4797          * It's easy to be greedy for MSI-X vectors, but it really
4798          * doesn't do us much good if we have a lot more vectors
4799          * than CPU's.  So let's be conservative and only ask for
4800          * (roughly) the same number of vectors as there are CPU's.
4801          */
4802         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4803                        (int)num_online_cpus()) + NON_Q_VECTORS;
4804
4805         /*
4806          * At the same time, hardware can only support a maximum of
4807          * hw.mac->max_msix_vectors vectors.  With features
4808          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4809          * descriptor queues supported by our device.  Thus, we cap it off in
4810          * those rare cases where the cpu count also exceeds our vector limit.
4811          */
4812         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4813
4814         /* A failure in MSI-X entry allocation isn't fatal, but it does
4815          * mean we disable MSI-X capabilities of the adapter. */
4816         adapter->msix_entries = kcalloc(v_budget,
4817                                         sizeof(struct msix_entry), GFP_KERNEL);
4818         if (adapter->msix_entries) {
4819                 for (vector = 0; vector < v_budget; vector++)
4820                         adapter->msix_entries[vector].entry = vector;
4821
4822                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4823
4824                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4825                         goto out;
4826         }
4827
4828         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4829         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4830         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4831                 e_err(probe,
4832                       "ATR is not supported while multiple "
4833                       "queues are disabled.  Disabling Flow Director\n");
4834         }
4835         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4836         adapter->atr_sample_rate = 0;
4837         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4838                 ixgbe_disable_sriov(adapter);
4839
4840         err = ixgbe_set_num_queues(adapter);
4841         if (err)
4842                 return err;
4843
4844         err = pci_enable_msi(adapter->pdev);
4845         if (!err) {
4846                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4847         } else {
4848                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4849                              "Unable to allocate MSI interrupt, "
4850                              "falling back to legacy.  Error: %d\n", err);
4851                 /* reset err */
4852                 err = 0;
4853         }
4854
4855 out:
4856         return err;
4857 }
4858
4859 /**
4860  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4861  * @adapter: board private structure to initialize
4862  *
4863  * We allocate one q_vector per queue interrupt.  If allocation fails we
4864  * return -ENOMEM.
4865  **/
4866 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4867 {
4868         int q_idx, num_q_vectors;
4869         struct ixgbe_q_vector *q_vector;
4870         int (*poll)(struct napi_struct *, int);
4871
4872         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4873                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4874                 poll = &ixgbe_clean_rxtx_many;
4875         } else {
4876                 num_q_vectors = 1;
4877                 poll = &ixgbe_poll;
4878         }
4879
4880         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4881                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4882                                         GFP_KERNEL, adapter->node);
4883                 if (!q_vector)
4884                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4885                                            GFP_KERNEL);
4886                 if (!q_vector)
4887                         goto err_out;
4888                 q_vector->adapter = adapter;
4889                 if (q_vector->tx.count && !q_vector->rx.count)
4890                         q_vector->eitr = adapter->tx_eitr_param;
4891                 else
4892                         q_vector->eitr = adapter->rx_eitr_param;
4893                 q_vector->v_idx = q_idx;
4894                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4895                 adapter->q_vector[q_idx] = q_vector;
4896         }
4897
4898         return 0;
4899
4900 err_out:
4901         while (q_idx) {
4902                 q_idx--;
4903                 q_vector = adapter->q_vector[q_idx];
4904                 netif_napi_del(&q_vector->napi);
4905                 kfree(q_vector);
4906                 adapter->q_vector[q_idx] = NULL;
4907         }
4908         return -ENOMEM;
4909 }
4910
4911 /**
4912  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4913  * @adapter: board private structure to initialize
4914  *
4915  * This function frees the memory allocated to the q_vectors.  In addition if
4916  * NAPI is enabled it will delete any references to the NAPI struct prior
4917  * to freeing the q_vector.
4918  **/
4919 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4920 {
4921         int q_idx, num_q_vectors;
4922
4923         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4924                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4925         else
4926                 num_q_vectors = 1;
4927
4928         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4929                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4930                 adapter->q_vector[q_idx] = NULL;
4931                 netif_napi_del(&q_vector->napi);
4932                 kfree(q_vector);
4933         }
4934 }
4935
4936 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4937 {
4938         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4939                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4940                 pci_disable_msix(adapter->pdev);
4941                 kfree(adapter->msix_entries);
4942                 adapter->msix_entries = NULL;
4943         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4944                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4945                 pci_disable_msi(adapter->pdev);
4946         }
4947 }
4948
4949 /**
4950  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4951  * @adapter: board private structure to initialize
4952  *
4953  * We determine which interrupt scheme to use based on...
4954  * - Kernel support (MSI, MSI-X)
4955  *   - which can be user-defined (via MODULE_PARAM)
4956  * - Hardware queue count (num_*_queues)
4957  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4958  **/
4959 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4960 {
4961         int err;
4962
4963         /* Number of supported queues */
4964         err = ixgbe_set_num_queues(adapter);
4965         if (err)
4966                 return err;
4967
4968         err = ixgbe_set_interrupt_capability(adapter);
4969         if (err) {
4970                 e_dev_err("Unable to setup interrupt capabilities\n");
4971                 goto err_set_interrupt;
4972         }
4973
4974         err = ixgbe_alloc_q_vectors(adapter);
4975         if (err) {
4976                 e_dev_err("Unable to allocate memory for queue vectors\n");
4977                 goto err_alloc_q_vectors;
4978         }
4979
4980         err = ixgbe_alloc_queues(adapter);
4981         if (err) {
4982                 e_dev_err("Unable to allocate memory for queues\n");
4983                 goto err_alloc_queues;
4984         }
4985
4986         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4987                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4988                    adapter->num_rx_queues, adapter->num_tx_queues);
4989
4990         set_bit(__IXGBE_DOWN, &adapter->state);
4991
4992         return 0;
4993
4994 err_alloc_queues:
4995         ixgbe_free_q_vectors(adapter);
4996 err_alloc_q_vectors:
4997         ixgbe_reset_interrupt_capability(adapter);
4998 err_set_interrupt:
4999         return err;
5000 }
5001
5002 /**
5003  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5004  * @adapter: board private structure to clear interrupt scheme on
5005  *
5006  * We go through and clear interrupt specific resources and reset the structure
5007  * to pre-load conditions
5008  **/
5009 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5010 {
5011         int i;
5012
5013         for (i = 0; i < adapter->num_tx_queues; i++) {
5014                 kfree(adapter->tx_ring[i]);
5015                 adapter->tx_ring[i] = NULL;
5016         }
5017         for (i = 0; i < adapter->num_rx_queues; i++) {
5018                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5019
5020                 /* ixgbe_get_stats64() might access this ring, we must wait
5021                  * a grace period before freeing it.
5022                  */
5023                 kfree_rcu(ring, rcu);
5024                 adapter->rx_ring[i] = NULL;
5025         }
5026
5027         adapter->num_tx_queues = 0;
5028         adapter->num_rx_queues = 0;
5029
5030         ixgbe_free_q_vectors(adapter);
5031         ixgbe_reset_interrupt_capability(adapter);
5032 }
5033
5034 /**
5035  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5036  * @adapter: board private structure to initialize
5037  *
5038  * ixgbe_sw_init initializes the Adapter private data structure.
5039  * Fields are initialized based on PCI device information and
5040  * OS network device settings (MTU size).
5041  **/
5042 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5043 {
5044         struct ixgbe_hw *hw = &adapter->hw;
5045         struct pci_dev *pdev = adapter->pdev;
5046         struct net_device *dev = adapter->netdev;
5047         unsigned int rss;
5048 #ifdef CONFIG_IXGBE_DCB
5049         int j;
5050         struct tc_configuration *tc;
5051 #endif
5052         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5053
5054         /* PCI config space info */
5055
5056         hw->vendor_id = pdev->vendor;
5057         hw->device_id = pdev->device;
5058         hw->revision_id = pdev->revision;
5059         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5060         hw->subsystem_device_id = pdev->subsystem_device;
5061
5062         /* Set capability flags */
5063         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5064         adapter->ring_feature[RING_F_RSS].indices = rss;
5065         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5066         switch (hw->mac.type) {
5067         case ixgbe_mac_82598EB:
5068                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5069                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5070                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5071                 break;
5072         case ixgbe_mac_82599EB:
5073         case ixgbe_mac_X540:
5074                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5075                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5076                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5077                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5078                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5079                 /* Flow Director hash filters enabled */
5080                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5081                 adapter->atr_sample_rate = 20;
5082                 adapter->ring_feature[RING_F_FDIR].indices =
5083                                                          IXGBE_MAX_FDIR_INDICES;
5084                 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5085 #ifdef IXGBE_FCOE
5086                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5087                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5088                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5089 #ifdef CONFIG_IXGBE_DCB
5090                 /* Default traffic class to use for FCoE */
5091                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5092 #endif
5093 #endif /* IXGBE_FCOE */
5094                 break;
5095         default:
5096                 break;
5097         }
5098
5099         /* n-tuple support exists, always init our spinlock */
5100         spin_lock_init(&adapter->fdir_perfect_lock);
5101
5102 #ifdef CONFIG_IXGBE_DCB
5103         /* Configure DCB traffic classes */
5104         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5105                 tc = &adapter->dcb_cfg.tc_config[j];
5106                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5107                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5108                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5109                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5110                 tc->dcb_pfc = pfc_disabled;
5111         }
5112         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5113         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5114         adapter->dcb_cfg.pfc_mode_enable = false;
5115         adapter->dcb_set_bitmap = 0x00;
5116         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5117         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5118                            MAX_TRAFFIC_CLASS);
5119
5120 #endif
5121
5122         /* default flow control settings */
5123         hw->fc.requested_mode = ixgbe_fc_full;
5124         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5125 #ifdef CONFIG_DCB
5126         adapter->last_lfc_mode = hw->fc.current_mode;
5127 #endif
5128         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5129         hw->fc.low_water = FC_LOW_WATER(max_frame);
5130         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5131         hw->fc.send_xon = true;
5132         hw->fc.disable_fc_autoneg = false;
5133
5134         /* enable itr by default in dynamic mode */
5135         adapter->rx_itr_setting = 1;
5136         adapter->rx_eitr_param = 20000;
5137         adapter->tx_itr_setting = 1;
5138         adapter->tx_eitr_param = 10000;
5139
5140         /* set defaults for eitr in MegaBytes */
5141         adapter->eitr_low = 10;
5142         adapter->eitr_high = 20;
5143
5144         /* set default ring sizes */
5145         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5146         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5147
5148         /* set default work limits */
5149         adapter->tx_work_limit = adapter->tx_ring_count;
5150
5151         /* initialize eeprom parameters */
5152         if (ixgbe_init_eeprom_params_generic(hw)) {
5153                 e_dev_err("EEPROM initialization failed\n");
5154                 return -EIO;
5155         }
5156
5157         /* enable rx csum by default */
5158         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5159
5160         /* get assigned NUMA node */
5161         adapter->node = dev_to_node(&pdev->dev);
5162
5163         set_bit(__IXGBE_DOWN, &adapter->state);
5164
5165         return 0;
5166 }
5167
5168 /**
5169  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5170  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5171  *
5172  * Return 0 on success, negative on failure
5173  **/
5174 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5175 {
5176         struct device *dev = tx_ring->dev;
5177         int size;
5178
5179         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5180         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5181         if (!tx_ring->tx_buffer_info)
5182                 tx_ring->tx_buffer_info = vzalloc(size);
5183         if (!tx_ring->tx_buffer_info)
5184                 goto err;
5185
5186         /* round up to nearest 4K */
5187         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5188         tx_ring->size = ALIGN(tx_ring->size, 4096);
5189
5190         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5191                                            &tx_ring->dma, GFP_KERNEL);
5192         if (!tx_ring->desc)
5193                 goto err;
5194
5195         tx_ring->next_to_use = 0;
5196         tx_ring->next_to_clean = 0;
5197         return 0;
5198
5199 err:
5200         vfree(tx_ring->tx_buffer_info);
5201         tx_ring->tx_buffer_info = NULL;
5202         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5203         return -ENOMEM;
5204 }
5205
5206 /**
5207  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5208  * @adapter: board private structure
5209  *
5210  * If this function returns with an error, then it's possible one or
5211  * more of the rings is populated (while the rest are not).  It is the
5212  * callers duty to clean those orphaned rings.
5213  *
5214  * Return 0 on success, negative on failure
5215  **/
5216 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5217 {
5218         int i, err = 0;
5219
5220         for (i = 0; i < adapter->num_tx_queues; i++) {
5221                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5222                 if (!err)
5223                         continue;
5224                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5225                 break;
5226         }
5227
5228         return err;
5229 }
5230
5231 /**
5232  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5233  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5234  *
5235  * Returns 0 on success, negative on failure
5236  **/
5237 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5238 {
5239         struct device *dev = rx_ring->dev;
5240         int size;
5241
5242         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5243         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5244         if (!rx_ring->rx_buffer_info)
5245                 rx_ring->rx_buffer_info = vzalloc(size);
5246         if (!rx_ring->rx_buffer_info)
5247                 goto err;
5248
5249         /* Round up to nearest 4K */
5250         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5251         rx_ring->size = ALIGN(rx_ring->size, 4096);
5252
5253         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5254                                            &rx_ring->dma, GFP_KERNEL);
5255
5256         if (!rx_ring->desc)
5257                 goto err;
5258
5259         rx_ring->next_to_clean = 0;
5260         rx_ring->next_to_use = 0;
5261
5262         return 0;
5263 err:
5264         vfree(rx_ring->rx_buffer_info);
5265         rx_ring->rx_buffer_info = NULL;
5266         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5267         return -ENOMEM;
5268 }
5269
5270 /**
5271  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5272  * @adapter: board private structure
5273  *
5274  * If this function returns with an error, then it's possible one or
5275  * more of the rings is populated (while the rest are not).  It is the
5276  * callers duty to clean those orphaned rings.
5277  *
5278  * Return 0 on success, negative on failure
5279  **/
5280 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5281 {
5282         int i, err = 0;
5283
5284         for (i = 0; i < adapter->num_rx_queues; i++) {
5285                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5286                 if (!err)
5287                         continue;
5288                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5289                 break;
5290         }
5291
5292         return err;
5293 }
5294
5295 /**
5296  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5297  * @tx_ring: Tx descriptor ring for a specific queue
5298  *
5299  * Free all transmit software resources
5300  **/
5301 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5302 {
5303         ixgbe_clean_tx_ring(tx_ring);
5304
5305         vfree(tx_ring->tx_buffer_info);
5306         tx_ring->tx_buffer_info = NULL;
5307
5308         /* if not set, then don't free */
5309         if (!tx_ring->desc)
5310                 return;
5311
5312         dma_free_coherent(tx_ring->dev, tx_ring->size,
5313                           tx_ring->desc, tx_ring->dma);
5314
5315         tx_ring->desc = NULL;
5316 }
5317
5318 /**
5319  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5320  * @adapter: board private structure
5321  *
5322  * Free all transmit software resources
5323  **/
5324 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5325 {
5326         int i;
5327
5328         for (i = 0; i < adapter->num_tx_queues; i++)
5329                 if (adapter->tx_ring[i]->desc)
5330                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5331 }
5332
5333 /**
5334  * ixgbe_free_rx_resources - Free Rx Resources
5335  * @rx_ring: ring to clean the resources from
5336  *
5337  * Free all receive software resources
5338  **/
5339 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5340 {
5341         ixgbe_clean_rx_ring(rx_ring);
5342
5343         vfree(rx_ring->rx_buffer_info);
5344         rx_ring->rx_buffer_info = NULL;
5345
5346         /* if not set, then don't free */
5347         if (!rx_ring->desc)
5348                 return;
5349
5350         dma_free_coherent(rx_ring->dev, rx_ring->size,
5351                           rx_ring->desc, rx_ring->dma);
5352
5353         rx_ring->desc = NULL;
5354 }
5355
5356 /**
5357  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5358  * @adapter: board private structure
5359  *
5360  * Free all receive software resources
5361  **/
5362 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5363 {
5364         int i;
5365
5366         for (i = 0; i < adapter->num_rx_queues; i++)
5367                 if (adapter->rx_ring[i]->desc)
5368                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5369 }
5370
5371 /**
5372  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5373  * @netdev: network interface device structure
5374  * @new_mtu: new value for maximum frame size
5375  *
5376  * Returns 0 on success, negative on failure
5377  **/
5378 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5379 {
5380         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5381         struct ixgbe_hw *hw = &adapter->hw;
5382         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5383
5384         /* MTU < 68 is an error and causes problems on some kernels */
5385         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5386             hw->mac.type != ixgbe_mac_X540) {
5387                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5388                         return -EINVAL;
5389         } else {
5390                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5391                         return -EINVAL;
5392         }
5393
5394         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5395         /* must set new MTU before calling down or up */
5396         netdev->mtu = new_mtu;
5397
5398         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5399         hw->fc.low_water = FC_LOW_WATER(max_frame);
5400
5401         if (netif_running(netdev))
5402                 ixgbe_reinit_locked(adapter);
5403
5404         return 0;
5405 }
5406
5407 /**
5408  * ixgbe_open - Called when a network interface is made active
5409  * @netdev: network interface device structure
5410  *
5411  * Returns 0 on success, negative value on failure
5412  *
5413  * The open entry point is called when a network interface is made
5414  * active by the system (IFF_UP).  At this point all resources needed
5415  * for transmit and receive operations are allocated, the interrupt
5416  * handler is registered with the OS, the watchdog timer is started,
5417  * and the stack is notified that the interface is ready.
5418  **/
5419 static int ixgbe_open(struct net_device *netdev)
5420 {
5421         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5422         int err;
5423
5424         /* disallow open during test */
5425         if (test_bit(__IXGBE_TESTING, &adapter->state))
5426                 return -EBUSY;
5427
5428         netif_carrier_off(netdev);
5429
5430         /* allocate transmit descriptors */
5431         err = ixgbe_setup_all_tx_resources(adapter);
5432         if (err)
5433                 goto err_setup_tx;
5434
5435         /* allocate receive descriptors */
5436         err = ixgbe_setup_all_rx_resources(adapter);
5437         if (err)
5438                 goto err_setup_rx;
5439
5440         ixgbe_configure(adapter);
5441
5442         err = ixgbe_request_irq(adapter);
5443         if (err)
5444                 goto err_req_irq;
5445
5446         err = ixgbe_up_complete(adapter);
5447         if (err)
5448                 goto err_up;
5449
5450         netif_tx_start_all_queues(netdev);
5451
5452         return 0;
5453
5454 err_up:
5455         ixgbe_release_hw_control(adapter);
5456         ixgbe_free_irq(adapter);
5457 err_req_irq:
5458 err_setup_rx:
5459         ixgbe_free_all_rx_resources(adapter);
5460 err_setup_tx:
5461         ixgbe_free_all_tx_resources(adapter);
5462         ixgbe_reset(adapter);
5463
5464         return err;
5465 }
5466
5467 /**
5468  * ixgbe_close - Disables a network interface
5469  * @netdev: network interface device structure
5470  *
5471  * Returns 0, this is not allowed to fail
5472  *
5473  * The close entry point is called when an interface is de-activated
5474  * by the OS.  The hardware is still under the drivers control, but
5475  * needs to be disabled.  A global MAC reset is issued to stop the
5476  * hardware, and all transmit and receive resources are freed.
5477  **/
5478 static int ixgbe_close(struct net_device *netdev)
5479 {
5480         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5481
5482         ixgbe_down(adapter);
5483         ixgbe_free_irq(adapter);
5484
5485         ixgbe_fdir_filter_exit(adapter);
5486
5487         ixgbe_free_all_tx_resources(adapter);
5488         ixgbe_free_all_rx_resources(adapter);
5489
5490         ixgbe_release_hw_control(adapter);
5491
5492         return 0;
5493 }
5494
5495 #ifdef CONFIG_PM
5496 static int ixgbe_resume(struct pci_dev *pdev)
5497 {
5498         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5499         struct net_device *netdev = adapter->netdev;
5500         u32 err;
5501
5502         pci_set_power_state(pdev, PCI_D0);
5503         pci_restore_state(pdev);
5504         /*
5505          * pci_restore_state clears dev->state_saved so call
5506          * pci_save_state to restore it.
5507          */
5508         pci_save_state(pdev);
5509
5510         err = pci_enable_device_mem(pdev);
5511         if (err) {
5512                 e_dev_err("Cannot enable PCI device from suspend\n");
5513                 return err;
5514         }
5515         pci_set_master(pdev);
5516
5517         pci_wake_from_d3(pdev, false);
5518
5519         err = ixgbe_init_interrupt_scheme(adapter);
5520         if (err) {
5521                 e_dev_err("Cannot initialize interrupts for device\n");
5522                 return err;
5523         }
5524
5525         ixgbe_reset(adapter);
5526
5527         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5528
5529         if (netif_running(netdev)) {
5530                 err = ixgbe_open(netdev);
5531                 if (err)
5532                         return err;
5533         }
5534
5535         netif_device_attach(netdev);
5536
5537         return 0;
5538 }
5539 #endif /* CONFIG_PM */
5540
5541 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5542 {
5543         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5544         struct net_device *netdev = adapter->netdev;
5545         struct ixgbe_hw *hw = &adapter->hw;
5546         u32 ctrl, fctrl;
5547         u32 wufc = adapter->wol;
5548 #ifdef CONFIG_PM
5549         int retval = 0;
5550 #endif
5551
5552         netif_device_detach(netdev);
5553
5554         if (netif_running(netdev)) {
5555                 ixgbe_down(adapter);
5556                 ixgbe_free_irq(adapter);
5557                 ixgbe_free_all_tx_resources(adapter);
5558                 ixgbe_free_all_rx_resources(adapter);
5559         }
5560
5561         ixgbe_clear_interrupt_scheme(adapter);
5562 #ifdef CONFIG_DCB
5563         kfree(adapter->ixgbe_ieee_pfc);
5564         kfree(adapter->ixgbe_ieee_ets);
5565 #endif
5566
5567 #ifdef CONFIG_PM
5568         retval = pci_save_state(pdev);
5569         if (retval)
5570                 return retval;
5571
5572 #endif
5573         if (wufc) {
5574                 ixgbe_set_rx_mode(netdev);
5575
5576                 /* turn on all-multi mode if wake on multicast is enabled */
5577                 if (wufc & IXGBE_WUFC_MC) {
5578                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5579                         fctrl |= IXGBE_FCTRL_MPE;
5580                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5581                 }
5582
5583                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5584                 ctrl |= IXGBE_CTRL_GIO_DIS;
5585                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5586
5587                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5588         } else {
5589                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5590                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5591         }
5592
5593         switch (hw->mac.type) {
5594         case ixgbe_mac_82598EB:
5595                 pci_wake_from_d3(pdev, false);
5596                 break;
5597         case ixgbe_mac_82599EB:
5598         case ixgbe_mac_X540:
5599                 pci_wake_from_d3(pdev, !!wufc);
5600                 break;
5601         default:
5602                 break;
5603         }
5604
5605         *enable_wake = !!wufc;
5606
5607         ixgbe_release_hw_control(adapter);
5608
5609         pci_disable_device(pdev);
5610
5611         return 0;
5612 }
5613
5614 #ifdef CONFIG_PM
5615 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5616 {
5617         int retval;
5618         bool wake;
5619
5620         retval = __ixgbe_shutdown(pdev, &wake);
5621         if (retval)
5622                 return retval;
5623
5624         if (wake) {
5625                 pci_prepare_to_sleep(pdev);
5626         } else {
5627                 pci_wake_from_d3(pdev, false);
5628                 pci_set_power_state(pdev, PCI_D3hot);
5629         }
5630
5631         return 0;
5632 }
5633 #endif /* CONFIG_PM */
5634
5635 static void ixgbe_shutdown(struct pci_dev *pdev)
5636 {
5637         bool wake;
5638
5639         __ixgbe_shutdown(pdev, &wake);
5640
5641         if (system_state == SYSTEM_POWER_OFF) {
5642                 pci_wake_from_d3(pdev, wake);
5643                 pci_set_power_state(pdev, PCI_D3hot);
5644         }
5645 }
5646
5647 /**
5648  * ixgbe_update_stats - Update the board statistics counters.
5649  * @adapter: board private structure
5650  **/
5651 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5652 {
5653         struct net_device *netdev = adapter->netdev;
5654         struct ixgbe_hw *hw = &adapter->hw;
5655         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5656         u64 total_mpc = 0;
5657         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5658         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5659         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5660         u64 bytes = 0, packets = 0;
5661
5662         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5663             test_bit(__IXGBE_RESETTING, &adapter->state))
5664                 return;
5665
5666         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5667                 u64 rsc_count = 0;
5668                 u64 rsc_flush = 0;
5669                 for (i = 0; i < 16; i++)
5670                         adapter->hw_rx_no_dma_resources +=
5671                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5672                 for (i = 0; i < adapter->num_rx_queues; i++) {
5673                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5674                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5675                 }
5676                 adapter->rsc_total_count = rsc_count;
5677                 adapter->rsc_total_flush = rsc_flush;
5678         }
5679
5680         for (i = 0; i < adapter->num_rx_queues; i++) {
5681                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5682                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5683                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5684                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5685                 bytes += rx_ring->stats.bytes;
5686                 packets += rx_ring->stats.packets;
5687         }
5688         adapter->non_eop_descs = non_eop_descs;
5689         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5690         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5691         netdev->stats.rx_bytes = bytes;
5692         netdev->stats.rx_packets = packets;
5693
5694         bytes = 0;
5695         packets = 0;
5696         /* gather some stats to the adapter struct that are per queue */
5697         for (i = 0; i < adapter->num_tx_queues; i++) {
5698                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5699                 restart_queue += tx_ring->tx_stats.restart_queue;
5700                 tx_busy += tx_ring->tx_stats.tx_busy;
5701                 bytes += tx_ring->stats.bytes;
5702                 packets += tx_ring->stats.packets;
5703         }
5704         adapter->restart_queue = restart_queue;
5705         adapter->tx_busy = tx_busy;
5706         netdev->stats.tx_bytes = bytes;
5707         netdev->stats.tx_packets = packets;
5708
5709         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5710         for (i = 0; i < 8; i++) {
5711                 /* for packet buffers not used, the register should read 0 */
5712                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5713                 missed_rx += mpc;
5714                 hwstats->mpc[i] += mpc;
5715                 total_mpc += hwstats->mpc[i];
5716                 if (hw->mac.type == ixgbe_mac_82598EB)
5717                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5718                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5719                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5720                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5721                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5722                 switch (hw->mac.type) {
5723                 case ixgbe_mac_82598EB:
5724                         hwstats->pxonrxc[i] +=
5725                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5726                         break;
5727                 case ixgbe_mac_82599EB:
5728                 case ixgbe_mac_X540:
5729                         hwstats->pxonrxc[i] +=
5730                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5731                         break;
5732                 default:
5733                         break;
5734                 }
5735                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5736                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5737         }
5738         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5739         /* work around hardware counting issue */
5740         hwstats->gprc -= missed_rx;
5741
5742         ixgbe_update_xoff_received(adapter);
5743
5744         /* 82598 hardware only has a 32 bit counter in the high register */
5745         switch (hw->mac.type) {
5746         case ixgbe_mac_82598EB:
5747                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5748                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5749                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5750                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5751                 break;
5752         case ixgbe_mac_X540:
5753                 /* OS2BMC stats are X540 only*/
5754                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5755                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5756                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5757                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5758         case ixgbe_mac_82599EB:
5759                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5760                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5761                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5762                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5763                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5764                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5765                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5766                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5767                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5768 #ifdef IXGBE_FCOE
5769                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5770                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5771                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5772                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5773                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5774                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5775 #endif /* IXGBE_FCOE */
5776                 break;
5777         default:
5778                 break;
5779         }
5780         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5781         hwstats->bprc += bprc;
5782         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5783         if (hw->mac.type == ixgbe_mac_82598EB)
5784                 hwstats->mprc -= bprc;
5785         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5786         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5787         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5788         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5789         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5790         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5791         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5792         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5793         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5794         hwstats->lxontxc += lxon;
5795         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5796         hwstats->lxofftxc += lxoff;
5797         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5798         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5799         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5800         /*
5801          * 82598 errata - tx of flow control packets is included in tx counters
5802          */
5803         xon_off_tot = lxon + lxoff;
5804         hwstats->gptc -= xon_off_tot;
5805         hwstats->mptc -= xon_off_tot;
5806         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5807         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5808         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5809         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5810         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5811         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5812         hwstats->ptc64 -= xon_off_tot;
5813         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5814         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5815         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5816         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5817         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5818         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5819
5820         /* Fill out the OS statistics structure */
5821         netdev->stats.multicast = hwstats->mprc;
5822
5823         /* Rx Errors */
5824         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5825         netdev->stats.rx_dropped = 0;
5826         netdev->stats.rx_length_errors = hwstats->rlec;
5827         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5828         netdev->stats.rx_missed_errors = total_mpc;
5829 }
5830
5831 /**
5832  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5833  * @adapter - pointer to the device adapter structure
5834  **/
5835 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5836 {
5837         struct ixgbe_hw *hw = &adapter->hw;
5838         int i;
5839
5840         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5841                 return;
5842
5843         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5844
5845         /* if interface is down do nothing */
5846         if (test_bit(__IXGBE_DOWN, &adapter->state))
5847                 return;
5848
5849         /* do nothing if we are not using signature filters */
5850         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5851                 return;
5852
5853         adapter->fdir_overflow++;
5854
5855         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5856                 for (i = 0; i < adapter->num_tx_queues; i++)
5857                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5858                                 &(adapter->tx_ring[i]->state));
5859                 /* re-enable flow director interrupts */
5860                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5861         } else {
5862                 e_err(probe, "failed to finish FDIR re-initialization, "
5863                       "ignored adding FDIR ATR filters\n");
5864         }
5865 }
5866
5867 /**
5868  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5869  * @adapter - pointer to the device adapter structure
5870  *
5871  * This function serves two purposes.  First it strobes the interrupt lines
5872  * in order to make certain interrupts are occuring.  Secondly it sets the
5873  * bits needed to check for TX hangs.  As a result we should immediately
5874  * determine if a hang has occured.
5875  */
5876 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5877 {
5878         struct ixgbe_hw *hw = &adapter->hw;
5879         u64 eics = 0;
5880         int i;
5881
5882         /* If we're down or resetting, just bail */
5883         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5884             test_bit(__IXGBE_RESETTING, &adapter->state))
5885                 return;
5886
5887         /* Force detection of hung controller */
5888         if (netif_carrier_ok(adapter->netdev)) {
5889                 for (i = 0; i < adapter->num_tx_queues; i++)
5890                         set_check_for_tx_hang(adapter->tx_ring[i]);
5891         }
5892
5893         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5894                 /*
5895                  * for legacy and MSI interrupts don't set any bits
5896                  * that are enabled for EIAM, because this operation
5897                  * would set *both* EIMS and EICS for any bit in EIAM
5898                  */
5899                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5900                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5901         } else {
5902                 /* get one bit for every active tx/rx interrupt vector */
5903                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5904                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5905                         if (qv->rx.count || qv->tx.count)
5906                                 eics |= ((u64)1 << i);
5907                 }
5908         }
5909
5910         /* Cause software interrupt to ensure rings are cleaned */
5911         ixgbe_irq_rearm_queues(adapter, eics);
5912
5913 }
5914
5915 /**
5916  * ixgbe_watchdog_update_link - update the link status
5917  * @adapter - pointer to the device adapter structure
5918  * @link_speed - pointer to a u32 to store the link_speed
5919  **/
5920 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5921 {
5922         struct ixgbe_hw *hw = &adapter->hw;
5923         u32 link_speed = adapter->link_speed;
5924         bool link_up = adapter->link_up;
5925         int i;
5926
5927         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5928                 return;
5929
5930         if (hw->mac.ops.check_link) {
5931                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5932         } else {
5933                 /* always assume link is up, if no check link function */
5934                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5935                 link_up = true;
5936         }
5937         if (link_up) {
5938                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5939                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5940                                 hw->mac.ops.fc_enable(hw, i);
5941                 } else {
5942                         hw->mac.ops.fc_enable(hw, 0);
5943                 }
5944         }
5945
5946         if (link_up ||
5947             time_after(jiffies, (adapter->link_check_timeout +
5948                                  IXGBE_TRY_LINK_TIMEOUT))) {
5949                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5950                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5951                 IXGBE_WRITE_FLUSH(hw);
5952         }
5953
5954         adapter->link_up = link_up;
5955         adapter->link_speed = link_speed;
5956 }
5957
5958 /**
5959  * ixgbe_watchdog_link_is_up - update netif_carrier status and
5960  *                             print link up message
5961  * @adapter - pointer to the device adapter structure
5962  **/
5963 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5964 {
5965         struct net_device *netdev = adapter->netdev;
5966         struct ixgbe_hw *hw = &adapter->hw;
5967         u32 link_speed = adapter->link_speed;
5968         bool flow_rx, flow_tx;
5969
5970         /* only continue if link was previously down */
5971         if (netif_carrier_ok(netdev))
5972                 return;
5973
5974         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5975
5976         switch (hw->mac.type) {
5977         case ixgbe_mac_82598EB: {
5978                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5979                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5980                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5981                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5982         }
5983                 break;
5984         case ixgbe_mac_X540:
5985         case ixgbe_mac_82599EB: {
5986                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5987                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5988                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5989                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5990         }
5991                 break;
5992         default:
5993                 flow_tx = false;
5994                 flow_rx = false;
5995                 break;
5996         }
5997         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5998                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5999                "10 Gbps" :
6000                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6001                "1 Gbps" :
6002                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6003                "100 Mbps" :
6004                "unknown speed"))),
6005                ((flow_rx && flow_tx) ? "RX/TX" :
6006                (flow_rx ? "RX" :
6007                (flow_tx ? "TX" : "None"))));
6008
6009         netif_carrier_on(netdev);
6010         ixgbe_check_vf_rate_limit(adapter);
6011 }
6012
6013 /**
6014  * ixgbe_watchdog_link_is_down - update netif_carrier status and
6015  *                               print link down message
6016  * @adapter - pointer to the adapter structure
6017  **/
6018 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6019 {
6020         struct net_device *netdev = adapter->netdev;
6021         struct ixgbe_hw *hw = &adapter->hw;
6022
6023         adapter->link_up = false;
6024         adapter->link_speed = 0;
6025
6026         /* only continue if link was up previously */
6027         if (!netif_carrier_ok(netdev))
6028                 return;
6029
6030         /* poll for SFP+ cable when link is down */
6031         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6032                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6033
6034         e_info(drv, "NIC Link is Down\n");
6035         netif_carrier_off(netdev);
6036 }
6037
6038 /**
6039  * ixgbe_watchdog_flush_tx - flush queues on link down
6040  * @adapter - pointer to the device adapter structure
6041  **/
6042 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6043 {
6044         int i;
6045         int some_tx_pending = 0;
6046
6047         if (!netif_carrier_ok(adapter->netdev)) {
6048                 for (i = 0; i < adapter->num_tx_queues; i++) {
6049                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6050                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6051                                 some_tx_pending = 1;
6052                                 break;
6053                         }
6054                 }
6055
6056                 if (some_tx_pending) {
6057                         /* We've lost link, so the controller stops DMA,
6058                          * but we've got queued Tx work that's never going
6059                          * to get done, so reset controller to flush Tx.
6060                          * (Do the reset outside of interrupt context).
6061                          */
6062                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6063                 }
6064         }
6065 }
6066
6067 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6068 {
6069         u32 ssvpc;
6070
6071         /* Do not perform spoof check for 82598 */
6072         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6073                 return;
6074
6075         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6076
6077         /*
6078          * ssvpc register is cleared on read, if zero then no
6079          * spoofed packets in the last interval.
6080          */
6081         if (!ssvpc)
6082                 return;
6083
6084         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6085 }
6086
6087 /**
6088  * ixgbe_watchdog_subtask - check and bring link up
6089  * @adapter - pointer to the device adapter structure
6090  **/
6091 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6092 {
6093         /* if interface is down do nothing */
6094         if (test_bit(__IXGBE_DOWN, &adapter->state))
6095                 return;
6096
6097         ixgbe_watchdog_update_link(adapter);
6098
6099         if (adapter->link_up)
6100                 ixgbe_watchdog_link_is_up(adapter);
6101         else
6102                 ixgbe_watchdog_link_is_down(adapter);
6103
6104         ixgbe_spoof_check(adapter);
6105         ixgbe_update_stats(adapter);
6106
6107         ixgbe_watchdog_flush_tx(adapter);
6108 }
6109
6110 /**
6111  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6112  * @adapter - the ixgbe adapter structure
6113  **/
6114 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6115 {
6116         struct ixgbe_hw *hw = &adapter->hw;
6117         s32 err;
6118
6119         /* not searching for SFP so there is nothing to do here */
6120         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6121             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6122                 return;
6123
6124         /* someone else is in init, wait until next service event */
6125         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6126                 return;
6127
6128         err = hw->phy.ops.identify_sfp(hw);
6129         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6130                 goto sfp_out;
6131
6132         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6133                 /* If no cable is present, then we need to reset
6134                  * the next time we find a good cable. */
6135                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6136         }
6137
6138         /* exit on error */
6139         if (err)
6140                 goto sfp_out;
6141
6142         /* exit if reset not needed */
6143         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6144                 goto sfp_out;
6145
6146         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6147
6148         /*
6149          * A module may be identified correctly, but the EEPROM may not have
6150          * support for that module.  setup_sfp() will fail in that case, so
6151          * we should not allow that module to load.
6152          */
6153         if (hw->mac.type == ixgbe_mac_82598EB)
6154                 err = hw->phy.ops.reset(hw);
6155         else
6156                 err = hw->mac.ops.setup_sfp(hw);
6157
6158         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6159                 goto sfp_out;
6160
6161         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6162         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6163
6164 sfp_out:
6165         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6166
6167         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6168             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6169                 e_dev_err("failed to initialize because an unsupported "
6170                           "SFP+ module type was detected.\n");
6171                 e_dev_err("Reload the driver after installing a "
6172                           "supported module.\n");
6173                 unregister_netdev(adapter->netdev);
6174         }
6175 }
6176
6177 /**
6178  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6179  * @adapter - the ixgbe adapter structure
6180  **/
6181 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6182 {
6183         struct ixgbe_hw *hw = &adapter->hw;
6184         u32 autoneg;
6185         bool negotiation;
6186
6187         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6188                 return;
6189
6190         /* someone else is in init, wait until next service event */
6191         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6192                 return;
6193
6194         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6195
6196         autoneg = hw->phy.autoneg_advertised;
6197         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6198                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6199         hw->mac.autotry_restart = false;
6200         if (hw->mac.ops.setup_link)
6201                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6202
6203         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6204         adapter->link_check_timeout = jiffies;
6205         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6206 }
6207
6208 /**
6209  * ixgbe_service_timer - Timer Call-back
6210  * @data: pointer to adapter cast into an unsigned long
6211  **/
6212 static void ixgbe_service_timer(unsigned long data)
6213 {
6214         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6215         unsigned long next_event_offset;
6216
6217         /* poll faster when waiting for link */
6218         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6219                 next_event_offset = HZ / 10;
6220         else
6221                 next_event_offset = HZ * 2;
6222
6223         /* Reset the timer */
6224         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6225
6226         ixgbe_service_event_schedule(adapter);
6227 }
6228
6229 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6230 {
6231         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6232                 return;
6233
6234         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6235
6236         /* If we're already down or resetting, just bail */
6237         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6238             test_bit(__IXGBE_RESETTING, &adapter->state))
6239                 return;
6240
6241         ixgbe_dump(adapter);
6242         netdev_err(adapter->netdev, "Reset adapter\n");
6243         adapter->tx_timeout_count++;
6244
6245         ixgbe_reinit_locked(adapter);
6246 }
6247
6248 /**
6249  * ixgbe_service_task - manages and runs subtasks
6250  * @work: pointer to work_struct containing our data
6251  **/
6252 static void ixgbe_service_task(struct work_struct *work)
6253 {
6254         struct ixgbe_adapter *adapter = container_of(work,
6255                                                      struct ixgbe_adapter,
6256                                                      service_task);
6257
6258         ixgbe_reset_subtask(adapter);
6259         ixgbe_sfp_detection_subtask(adapter);
6260         ixgbe_sfp_link_config_subtask(adapter);
6261         ixgbe_check_overtemp_subtask(adapter);
6262         ixgbe_watchdog_subtask(adapter);
6263         ixgbe_fdir_reinit_subtask(adapter);
6264         ixgbe_check_hang_subtask(adapter);
6265
6266         ixgbe_service_event_complete(adapter);
6267 }
6268
6269 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6270                        u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6271 {
6272         struct ixgbe_adv_tx_context_desc *context_desc;
6273         u16 i = tx_ring->next_to_use;
6274
6275         context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6276
6277         i++;
6278         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6279
6280         /* set bits to identify this as an advanced context descriptor */
6281         type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6282
6283         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
6284         context_desc->seqnum_seed       = cpu_to_le32(fcoe_sof_eof);
6285         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
6286         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
6287 }
6288
6289 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6290                      u32 tx_flags, __be16 protocol, u8 *hdr_len)
6291 {
6292         int err;
6293         u32 vlan_macip_lens, type_tucmd;
6294         u32 mss_l4len_idx, l4len;
6295
6296         if (!skb_is_gso(skb))
6297                 return 0;
6298
6299         if (skb_header_cloned(skb)) {
6300                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6301                 if (err)
6302                         return err;
6303         }
6304
6305         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6306         type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6307
6308         if (protocol == __constant_htons(ETH_P_IP)) {
6309                 struct iphdr *iph = ip_hdr(skb);
6310                 iph->tot_len = 0;
6311                 iph->check = 0;
6312                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6313                                                          iph->daddr, 0,
6314                                                          IPPROTO_TCP,
6315                                                          0);
6316                 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6317         } else if (skb_is_gso_v6(skb)) {
6318                 ipv6_hdr(skb)->payload_len = 0;
6319                 tcp_hdr(skb)->check =
6320                     ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6321                                      &ipv6_hdr(skb)->daddr,
6322                                      0, IPPROTO_TCP, 0);
6323         }
6324
6325         l4len = tcp_hdrlen(skb);
6326         *hdr_len = skb_transport_offset(skb) + l4len;
6327
6328         /* mss_l4len_id: use 1 as index for TSO */
6329         mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6330         mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6331         mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6332
6333         /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6334         vlan_macip_lens = skb_network_header_len(skb);
6335         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6336         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6337
6338         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6339                           mss_l4len_idx);
6340
6341         return 1;
6342 }
6343
6344 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6345                           struct sk_buff *skb, u32 tx_flags,
6346                           __be16 protocol)
6347 {
6348         u32 vlan_macip_lens = 0;
6349         u32 mss_l4len_idx = 0;
6350         u32 type_tucmd = 0;
6351
6352         if (skb->ip_summed != CHECKSUM_PARTIAL) {
6353             if (!(tx_flags & IXGBE_TX_FLAGS_VLAN))
6354                         return false;
6355         } else {
6356                 u8 l4_hdr = 0;
6357                 switch (protocol) {
6358                 case __constant_htons(ETH_P_IP):
6359                         vlan_macip_lens |= skb_network_header_len(skb);
6360                         type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6361                         l4_hdr = ip_hdr(skb)->protocol;
6362                         break;
6363                 case __constant_htons(ETH_P_IPV6):
6364                         vlan_macip_lens |= skb_network_header_len(skb);
6365                         l4_hdr = ipv6_hdr(skb)->nexthdr;
6366                         break;
6367                 default:
6368                         if (unlikely(net_ratelimit())) {
6369                                 dev_warn(tx_ring->dev,
6370                                  "partial checksum but proto=%x!\n",
6371                                  skb->protocol);
6372                         }
6373                         break;
6374                 }
6375
6376                 switch (l4_hdr) {
6377                 case IPPROTO_TCP:
6378                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6379                         mss_l4len_idx = tcp_hdrlen(skb) <<
6380                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6381                         break;
6382                 case IPPROTO_SCTP:
6383                         type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6384                         mss_l4len_idx = sizeof(struct sctphdr) <<
6385                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6386                         break;
6387                 case IPPROTO_UDP:
6388                         mss_l4len_idx = sizeof(struct udphdr) <<
6389                                         IXGBE_ADVTXD_L4LEN_SHIFT;
6390                         break;
6391                 default:
6392                         if (unlikely(net_ratelimit())) {
6393                                 dev_warn(tx_ring->dev,
6394                                  "partial checksum but l4 proto=%x!\n",
6395                                  skb->protocol);
6396                         }
6397                         break;
6398                 }
6399         }
6400
6401         vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6402         vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6403
6404         ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6405                           type_tucmd, mss_l4len_idx);
6406
6407         return (skb->ip_summed == CHECKSUM_PARTIAL);
6408 }
6409
6410 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6411                         struct ixgbe_ring *tx_ring,
6412                         struct sk_buff *skb, u32 tx_flags,
6413                         unsigned int first, const u8 hdr_len)
6414 {
6415         struct device *dev = tx_ring->dev;
6416         struct ixgbe_tx_buffer *tx_buffer_info;
6417         unsigned int len;
6418         unsigned int total = skb->len;
6419         unsigned int offset = 0, size, count = 0;
6420         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6421         unsigned int f;
6422         unsigned int bytecount = skb->len;
6423         u16 gso_segs = 1;
6424         u16 i;
6425
6426         i = tx_ring->next_to_use;
6427
6428         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6429                 /* excluding fcoe_crc_eof for FCoE */
6430                 total -= sizeof(struct fcoe_crc_eof);
6431
6432         len = min(skb_headlen(skb), total);
6433         while (len) {
6434                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6435                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6436
6437                 tx_buffer_info->length = size;
6438                 tx_buffer_info->mapped_as_page = false;
6439                 tx_buffer_info->dma = dma_map_single(dev,
6440                                                      skb->data + offset,
6441                                                      size, DMA_TO_DEVICE);
6442                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6443                         goto dma_error;
6444                 tx_buffer_info->time_stamp = jiffies;
6445                 tx_buffer_info->next_to_watch = i;
6446
6447                 len -= size;
6448                 total -= size;
6449                 offset += size;
6450                 count++;
6451
6452                 if (len) {
6453                         i++;
6454                         if (i == tx_ring->count)
6455                                 i = 0;
6456                 }
6457         }
6458
6459         for (f = 0; f < nr_frags; f++) {
6460                 struct skb_frag_struct *frag;
6461
6462                 frag = &skb_shinfo(skb)->frags[f];
6463                 len = min((unsigned int)frag->size, total);
6464                 offset = frag->page_offset;
6465
6466                 while (len) {
6467                         i++;
6468                         if (i == tx_ring->count)
6469                                 i = 0;
6470
6471                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6472                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6473
6474                         tx_buffer_info->length = size;
6475                         tx_buffer_info->dma = dma_map_page(dev,
6476                                                            frag->page,
6477                                                            offset, size,
6478                                                            DMA_TO_DEVICE);
6479                         tx_buffer_info->mapped_as_page = true;
6480                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6481                                 goto dma_error;
6482                         tx_buffer_info->time_stamp = jiffies;
6483                         tx_buffer_info->next_to_watch = i;
6484
6485                         len -= size;
6486                         total -= size;
6487                         offset += size;
6488                         count++;
6489                 }
6490                 if (total == 0)
6491                         break;
6492         }
6493
6494         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6495                 gso_segs = skb_shinfo(skb)->gso_segs;
6496 #ifdef IXGBE_FCOE
6497         /* adjust for FCoE Sequence Offload */
6498         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6499                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6500                                         skb_shinfo(skb)->gso_size);
6501 #endif /* IXGBE_FCOE */
6502         bytecount += (gso_segs - 1) * hdr_len;
6503
6504         /* multiply data chunks by size of headers */
6505         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6506         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6507         tx_ring->tx_buffer_info[i].skb = skb;
6508         tx_ring->tx_buffer_info[first].next_to_watch = i;
6509
6510         return count;
6511
6512 dma_error:
6513         e_dev_err("TX DMA map failed\n");
6514
6515         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6516         tx_buffer_info->dma = 0;
6517         tx_buffer_info->time_stamp = 0;
6518         tx_buffer_info->next_to_watch = 0;
6519         if (count)
6520                 count--;
6521
6522         /* clear timestamp and dma mappings for remaining portion of packet */
6523         while (count--) {
6524                 if (i == 0)
6525                         i += tx_ring->count;
6526                 i--;
6527                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6528                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6529         }
6530
6531         return 0;
6532 }
6533
6534 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6535                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6536 {
6537         union ixgbe_adv_tx_desc *tx_desc = NULL;
6538         struct ixgbe_tx_buffer *tx_buffer_info;
6539         u32 olinfo_status = 0, cmd_type_len = 0;
6540         unsigned int i;
6541         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6542
6543         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6544
6545         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6546
6547         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6548                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6549
6550         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6551                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6552
6553                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6554                                  IXGBE_ADVTXD_POPTS_SHIFT;
6555
6556                 /* use index 1 context for tso */
6557                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6558                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6559                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6560                                          IXGBE_ADVTXD_POPTS_SHIFT;
6561
6562         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6563                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6564                                  IXGBE_ADVTXD_POPTS_SHIFT;
6565
6566         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6567                 olinfo_status |= IXGBE_ADVTXD_CC;
6568                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6569                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6570                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6571         }
6572
6573         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6574
6575         i = tx_ring->next_to_use;
6576         while (count--) {
6577                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6578                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6579                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6580                 tx_desc->read.cmd_type_len =
6581                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6582                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6583                 i++;
6584                 if (i == tx_ring->count)
6585                         i = 0;
6586         }
6587
6588         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6589
6590         /*
6591          * Force memory writes to complete before letting h/w
6592          * know there are new descriptors to fetch.  (Only
6593          * applicable for weak-ordered memory model archs,
6594          * such as IA-64).
6595          */
6596         wmb();
6597
6598         tx_ring->next_to_use = i;
6599         writel(i, tx_ring->tail);
6600 }
6601
6602 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6603                       u32 tx_flags, __be16 protocol)
6604 {
6605         struct ixgbe_q_vector *q_vector = ring->q_vector;
6606         union ixgbe_atr_hash_dword input = { .dword = 0 };
6607         union ixgbe_atr_hash_dword common = { .dword = 0 };
6608         union {
6609                 unsigned char *network;
6610                 struct iphdr *ipv4;
6611                 struct ipv6hdr *ipv6;
6612         } hdr;
6613         struct tcphdr *th;
6614         __be16 vlan_id;
6615
6616         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6617         if (!q_vector)
6618                 return;
6619
6620         /* do nothing if sampling is disabled */
6621         if (!ring->atr_sample_rate)
6622                 return;
6623
6624         ring->atr_count++;
6625
6626         /* snag network header to get L4 type and address */
6627         hdr.network = skb_network_header(skb);
6628
6629         /* Currently only IPv4/IPv6 with TCP is supported */
6630         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6631              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6632             (protocol != __constant_htons(ETH_P_IP) ||
6633              hdr.ipv4->protocol != IPPROTO_TCP))
6634                 return;
6635
6636         th = tcp_hdr(skb);
6637
6638         /* skip this packet since the socket is closing */
6639         if (th->fin)
6640                 return;
6641
6642         /* sample on all syn packets or once every atr sample count */
6643         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6644                 return;
6645
6646         /* reset sample count */
6647         ring->atr_count = 0;
6648
6649         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6650
6651         /*
6652          * src and dst are inverted, think how the receiver sees them
6653          *
6654          * The input is broken into two sections, a non-compressed section
6655          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6656          * is XORed together and stored in the compressed dword.
6657          */
6658         input.formatted.vlan_id = vlan_id;
6659
6660         /*
6661          * since src port and flex bytes occupy the same word XOR them together
6662          * and write the value to source port portion of compressed dword
6663          */
6664         if (vlan_id)
6665                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6666         else
6667                 common.port.src ^= th->dest ^ protocol;
6668         common.port.dst ^= th->source;
6669
6670         if (protocol == __constant_htons(ETH_P_IP)) {
6671                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6672                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6673         } else {
6674                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6675                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6676                              hdr.ipv6->saddr.s6_addr32[1] ^
6677                              hdr.ipv6->saddr.s6_addr32[2] ^
6678                              hdr.ipv6->saddr.s6_addr32[3] ^
6679                              hdr.ipv6->daddr.s6_addr32[0] ^
6680                              hdr.ipv6->daddr.s6_addr32[1] ^
6681                              hdr.ipv6->daddr.s6_addr32[2] ^
6682                              hdr.ipv6->daddr.s6_addr32[3];
6683         }
6684
6685         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6686         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6687                                               input, common, ring->queue_index);
6688 }
6689
6690 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6691 {
6692         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6693         /* Herbert's original patch had:
6694          *  smp_mb__after_netif_stop_queue();
6695          * but since that doesn't exist yet, just open code it. */
6696         smp_mb();
6697
6698         /* We need to check again in a case another CPU has just
6699          * made room available. */
6700         if (likely(ixgbe_desc_unused(tx_ring) < size))
6701                 return -EBUSY;
6702
6703         /* A reprieve! - use start_queue because it doesn't call schedule */
6704         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6705         ++tx_ring->tx_stats.restart_queue;
6706         return 0;
6707 }
6708
6709 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6710 {
6711         if (likely(ixgbe_desc_unused(tx_ring) >= size))
6712                 return 0;
6713         return __ixgbe_maybe_stop_tx(tx_ring, size);
6714 }
6715
6716 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6717 {
6718         struct ixgbe_adapter *adapter = netdev_priv(dev);
6719         int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6720                                                smp_processor_id();
6721 #ifdef IXGBE_FCOE
6722         __be16 protocol = vlan_get_protocol(skb);
6723
6724         if (((protocol == htons(ETH_P_FCOE)) ||
6725             (protocol == htons(ETH_P_FIP))) &&
6726             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6727                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6728                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6729                 return txq;
6730         }
6731 #endif
6732
6733         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6734                 while (unlikely(txq >= dev->real_num_tx_queues))
6735                         txq -= dev->real_num_tx_queues;
6736                 return txq;
6737         }
6738
6739         return skb_tx_hash(dev, skb);
6740 }
6741
6742 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6743                           struct ixgbe_adapter *adapter,
6744                           struct ixgbe_ring *tx_ring)
6745 {
6746         int tso;
6747         u32  tx_flags = 0;
6748 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6749         unsigned short f;
6750 #endif
6751         u16 first;
6752         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6753         __be16 protocol;
6754         u8 hdr_len = 0;
6755
6756         /*
6757          * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6758          *       + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6759          *       + 2 desc gap to keep tail from touching head,
6760          *       + 1 desc for context descriptor,
6761          * otherwise try next time
6762          */
6763 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6764         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6765                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6766 #else
6767         count += skb_shinfo(skb)->nr_frags;
6768 #endif
6769         if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6770                 tx_ring->tx_stats.tx_busy++;
6771                 return NETDEV_TX_BUSY;
6772         }
6773
6774         protocol = vlan_get_protocol(skb);
6775
6776         if (vlan_tx_tag_present(skb)) {
6777                 tx_flags |= vlan_tx_tag_get(skb);
6778                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6779                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6780                         tx_flags |= tx_ring->dcb_tc << 13;
6781                 }
6782                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6783                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6784         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6785                    skb->priority != TC_PRIO_CONTROL) {
6786                 tx_flags |= tx_ring->dcb_tc << 13;
6787                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6788                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6789         }
6790
6791 #ifdef IXGBE_FCOE
6792         /* for FCoE with DCB, we force the priority to what
6793          * was specified by the switch */
6794         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6795             (protocol == htons(ETH_P_FCOE)))
6796                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6797
6798 #endif
6799         /* record the location of the first descriptor for this packet */
6800         first = tx_ring->next_to_use;
6801
6802         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6803 #ifdef IXGBE_FCOE
6804                 /* setup tx offload for FCoE */
6805                 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6806                 if (tso < 0)
6807                         goto out_drop;
6808                 else if (tso)
6809                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6810 #endif /* IXGBE_FCOE */
6811         } else {
6812                 if (protocol == htons(ETH_P_IP))
6813                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6814                 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6815                 if (tso < 0)
6816                         goto out_drop;
6817                 else if (tso)
6818                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6819                 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6820                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6821         }
6822
6823         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6824         if (count) {
6825                 /* add the ATR filter if ATR is on */
6826                 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6827                         ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6828                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6829                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6830
6831         } else {
6832                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6833                 tx_ring->next_to_use = first;
6834                 goto out_drop;
6835         }
6836
6837         return NETDEV_TX_OK;
6838
6839 out_drop:
6840         dev_kfree_skb_any(skb);
6841         return NETDEV_TX_OK;
6842 }
6843
6844 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6845 {
6846         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6847         struct ixgbe_ring *tx_ring;
6848
6849         tx_ring = adapter->tx_ring[skb->queue_mapping];
6850         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6851 }
6852
6853 /**
6854  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6855  * @netdev: network interface device structure
6856  * @p: pointer to an address structure
6857  *
6858  * Returns 0 on success, negative on failure
6859  **/
6860 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6861 {
6862         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6863         struct ixgbe_hw *hw = &adapter->hw;
6864         struct sockaddr *addr = p;
6865
6866         if (!is_valid_ether_addr(addr->sa_data))
6867                 return -EADDRNOTAVAIL;
6868
6869         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6870         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6871
6872         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6873                             IXGBE_RAH_AV);
6874
6875         return 0;
6876 }
6877
6878 static int
6879 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6880 {
6881         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6882         struct ixgbe_hw *hw = &adapter->hw;
6883         u16 value;
6884         int rc;
6885
6886         if (prtad != hw->phy.mdio.prtad)
6887                 return -EINVAL;
6888         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6889         if (!rc)
6890                 rc = value;
6891         return rc;
6892 }
6893
6894 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6895                             u16 addr, u16 value)
6896 {
6897         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6898         struct ixgbe_hw *hw = &adapter->hw;
6899
6900         if (prtad != hw->phy.mdio.prtad)
6901                 return -EINVAL;
6902         return hw->phy.ops.write_reg(hw, addr, devad, value);
6903 }
6904
6905 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6906 {
6907         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6908
6909         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6910 }
6911
6912 /**
6913  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6914  * netdev->dev_addrs
6915  * @netdev: network interface device structure
6916  *
6917  * Returns non-zero on failure
6918  **/
6919 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6920 {
6921         int err = 0;
6922         struct ixgbe_adapter *adapter = netdev_priv(dev);
6923         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6924
6925         if (is_valid_ether_addr(mac->san_addr)) {
6926                 rtnl_lock();
6927                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6928                 rtnl_unlock();
6929         }
6930         return err;
6931 }
6932
6933 /**
6934  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6935  * netdev->dev_addrs
6936  * @netdev: network interface device structure
6937  *
6938  * Returns non-zero on failure
6939  **/
6940 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6941 {
6942         int err = 0;
6943         struct ixgbe_adapter *adapter = netdev_priv(dev);
6944         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6945
6946         if (is_valid_ether_addr(mac->san_addr)) {
6947                 rtnl_lock();
6948                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6949                 rtnl_unlock();
6950         }
6951         return err;
6952 }
6953
6954 #ifdef CONFIG_NET_POLL_CONTROLLER
6955 /*
6956  * Polling 'interrupt' - used by things like netconsole to send skbs
6957  * without having to re-enable interrupts. It's not called while
6958  * the interrupt routine is executing.
6959  */
6960 static void ixgbe_netpoll(struct net_device *netdev)
6961 {
6962         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6963         int i;
6964
6965         /* if interface is down do nothing */
6966         if (test_bit(__IXGBE_DOWN, &adapter->state))
6967                 return;
6968
6969         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6970         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6971                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6972                 for (i = 0; i < num_q_vectors; i++) {
6973                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6974                         ixgbe_msix_clean_many(0, q_vector);
6975                 }
6976         } else {
6977                 ixgbe_intr(adapter->pdev->irq, netdev);
6978         }
6979         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6980 }
6981 #endif
6982
6983 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6984                                                    struct rtnl_link_stats64 *stats)
6985 {
6986         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6987         int i;
6988
6989         rcu_read_lock();
6990         for (i = 0; i < adapter->num_rx_queues; i++) {
6991                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6992                 u64 bytes, packets;
6993                 unsigned int start;
6994
6995                 if (ring) {
6996                         do {
6997                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6998                                 packets = ring->stats.packets;
6999                                 bytes   = ring->stats.bytes;
7000                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7001                         stats->rx_packets += packets;
7002                         stats->rx_bytes   += bytes;
7003                 }
7004         }
7005
7006         for (i = 0; i < adapter->num_tx_queues; i++) {
7007                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7008                 u64 bytes, packets;
7009                 unsigned int start;
7010
7011                 if (ring) {
7012                         do {
7013                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7014                                 packets = ring->stats.packets;
7015                                 bytes   = ring->stats.bytes;
7016                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7017                         stats->tx_packets += packets;
7018                         stats->tx_bytes   += bytes;
7019                 }
7020         }
7021         rcu_read_unlock();
7022         /* following stats updated by ixgbe_watchdog_task() */
7023         stats->multicast        = netdev->stats.multicast;
7024         stats->rx_errors        = netdev->stats.rx_errors;
7025         stats->rx_length_errors = netdev->stats.rx_length_errors;
7026         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7027         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7028         return stats;
7029 }
7030
7031 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7032  * #adapter: pointer to ixgbe_adapter
7033  * @tc: number of traffic classes currently enabled
7034  *
7035  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7036  * 802.1Q priority maps to a packet buffer that exists.
7037  */
7038 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7039 {
7040         struct ixgbe_hw *hw = &adapter->hw;
7041         u32 reg, rsave;
7042         int i;
7043
7044         /* 82598 have a static priority to TC mapping that can not
7045          * be changed so no validation is needed.
7046          */
7047         if (hw->mac.type == ixgbe_mac_82598EB)
7048                 return;
7049
7050         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7051         rsave = reg;
7052
7053         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7054                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7055
7056                 /* If up2tc is out of bounds default to zero */
7057                 if (up2tc > tc)
7058                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7059         }
7060
7061         if (reg != rsave)
7062                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7063
7064         return;
7065 }
7066
7067
7068 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7069  * classes.
7070  *
7071  * @netdev: net device to configure
7072  * @tc: number of traffic classes to enable
7073  */
7074 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7075 {
7076         struct ixgbe_adapter *adapter = netdev_priv(dev);
7077         struct ixgbe_hw *hw = &adapter->hw;
7078
7079         /* If DCB is anabled do not remove traffic classes, multiple
7080          * traffic classes are required to implement DCB
7081          */
7082         if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7083                 return 0;
7084
7085         /* Hardware supports up to 8 traffic classes */
7086         if (tc > MAX_TRAFFIC_CLASS ||
7087             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7088                 return -EINVAL;
7089
7090         /* Hardware has to reinitialize queues and interrupts to
7091          * match packet buffer alignment. Unfortunantly, the
7092          * hardware is not flexible enough to do this dynamically.
7093          */
7094         if (netif_running(dev))
7095                 ixgbe_close(dev);
7096         ixgbe_clear_interrupt_scheme(adapter);
7097
7098         if (tc)
7099                 netdev_set_num_tc(dev, tc);
7100         else
7101                 netdev_reset_tc(dev);
7102
7103         ixgbe_init_interrupt_scheme(adapter);
7104         ixgbe_validate_rtr(adapter, tc);
7105         if (netif_running(dev))
7106                 ixgbe_open(dev);
7107
7108         return 0;
7109 }
7110
7111 void ixgbe_do_reset(struct net_device *netdev)
7112 {
7113         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7114
7115         if (netif_running(netdev))
7116                 ixgbe_reinit_locked(adapter);
7117         else
7118                 ixgbe_reset(adapter);
7119 }
7120
7121 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7122 {
7123         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7124
7125 #ifdef CONFIG_DCB
7126         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7127                 data &= ~NETIF_F_HW_VLAN_RX;
7128 #endif
7129
7130         /* return error if RXHASH is being enabled when RSS is not supported */
7131         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7132                 data &= ~NETIF_F_RXHASH;
7133
7134         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7135         if (!(data & NETIF_F_RXCSUM))
7136                 data &= ~NETIF_F_LRO;
7137
7138         /* Turn off LRO if not RSC capable or invalid ITR settings */
7139         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7140                 data &= ~NETIF_F_LRO;
7141         } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7142                    (adapter->rx_itr_setting != 1 &&
7143                     adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7144                 data &= ~NETIF_F_LRO;
7145                 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7146         }
7147
7148         return data;
7149 }
7150
7151 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7152 {
7153         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7154         bool need_reset = false;
7155
7156         /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7157         if (!(data & NETIF_F_RXCSUM))
7158                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7159         else
7160                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7161
7162         /* Make sure RSC matches LRO, reset if change */
7163         if (!!(data & NETIF_F_LRO) !=
7164              !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7165                 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7166                 switch (adapter->hw.mac.type) {
7167                 case ixgbe_mac_X540:
7168                 case ixgbe_mac_82599EB:
7169                         need_reset = true;
7170                         break;
7171                 default:
7172                         break;
7173                 }
7174         }
7175
7176         /*
7177          * Check if Flow Director n-tuple support was enabled or disabled.  If
7178          * the state changed, we need to reset.
7179          */
7180         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7181                 /* turn off ATR, enable perfect filters and reset */
7182                 if (data & NETIF_F_NTUPLE) {
7183                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7184                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7185                         need_reset = true;
7186                 }
7187         } else if (!(data & NETIF_F_NTUPLE)) {
7188                 /* turn off Flow Director, set ATR and reset */
7189                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7190                 if ((adapter->flags &  IXGBE_FLAG_RSS_ENABLED) &&
7191                     !(adapter->flags &  IXGBE_FLAG_DCB_ENABLED))
7192                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7193                 need_reset = true;
7194         }
7195
7196         if (need_reset)
7197                 ixgbe_do_reset(netdev);
7198
7199         return 0;
7200
7201 }
7202
7203 static const struct net_device_ops ixgbe_netdev_ops = {
7204         .ndo_open               = ixgbe_open,
7205         .ndo_stop               = ixgbe_close,
7206         .ndo_start_xmit         = ixgbe_xmit_frame,
7207         .ndo_select_queue       = ixgbe_select_queue,
7208         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7209         .ndo_set_multicast_list = ixgbe_set_rx_mode,
7210         .ndo_validate_addr      = eth_validate_addr,
7211         .ndo_set_mac_address    = ixgbe_set_mac,
7212         .ndo_change_mtu         = ixgbe_change_mtu,
7213         .ndo_tx_timeout         = ixgbe_tx_timeout,
7214         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7215         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7216         .ndo_do_ioctl           = ixgbe_ioctl,
7217         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7218         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7219         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7220         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7221         .ndo_get_stats64        = ixgbe_get_stats64,
7222         .ndo_setup_tc           = ixgbe_setup_tc,
7223 #ifdef CONFIG_NET_POLL_CONTROLLER
7224         .ndo_poll_controller    = ixgbe_netpoll,
7225 #endif
7226 #ifdef IXGBE_FCOE
7227         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7228         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7229         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7230         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7231         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7232         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7233 #endif /* IXGBE_FCOE */
7234         .ndo_set_features = ixgbe_set_features,
7235         .ndo_fix_features = ixgbe_fix_features,
7236 };
7237
7238 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7239                            const struct ixgbe_info *ii)
7240 {
7241 #ifdef CONFIG_PCI_IOV
7242         struct ixgbe_hw *hw = &adapter->hw;
7243         int err;
7244         int num_vf_macvlans, i;
7245         struct vf_macvlans *mv_list;
7246
7247         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7248                 return;
7249
7250         /* The 82599 supports up to 64 VFs per physical function
7251          * but this implementation limits allocation to 63 so that
7252          * basic networking resources are still available to the
7253          * physical function
7254          */
7255         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7256         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7257         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7258         if (err) {
7259                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7260                 goto err_novfs;
7261         }
7262
7263         num_vf_macvlans = hw->mac.num_rar_entries -
7264                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7265
7266         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7267                                              sizeof(struct vf_macvlans),
7268                                              GFP_KERNEL);
7269         if (mv_list) {
7270                 /* Initialize list of VF macvlans */
7271                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7272                 for (i = 0; i < num_vf_macvlans; i++) {
7273                         mv_list->vf = -1;
7274                         mv_list->free = true;
7275                         mv_list->rar_entry = hw->mac.num_rar_entries -
7276                                 (i + adapter->num_vfs + 1);
7277                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7278                         mv_list++;
7279                 }
7280         }
7281
7282         /* If call to enable VFs succeeded then allocate memory
7283          * for per VF control structures.
7284          */
7285         adapter->vfinfo =
7286                 kcalloc(adapter->num_vfs,
7287                         sizeof(struct vf_data_storage), GFP_KERNEL);
7288         if (adapter->vfinfo) {
7289                 /* Now that we're sure SR-IOV is enabled
7290                  * and memory allocated set up the mailbox parameters
7291                  */
7292                 ixgbe_init_mbx_params_pf(hw);
7293                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7294                        sizeof(hw->mbx.ops));
7295
7296                 /* Disable RSC when in SR-IOV mode */
7297                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7298                                      IXGBE_FLAG2_RSC_ENABLED);
7299                 return;
7300         }
7301
7302         /* Oh oh */
7303         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7304               "SRIOV disabled\n");
7305         pci_disable_sriov(adapter->pdev);
7306
7307 err_novfs:
7308         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7309         adapter->num_vfs = 0;
7310 #endif /* CONFIG_PCI_IOV */
7311 }
7312
7313 /**
7314  * ixgbe_probe - Device Initialization Routine
7315  * @pdev: PCI device information struct
7316  * @ent: entry in ixgbe_pci_tbl
7317  *
7318  * Returns 0 on success, negative on failure
7319  *
7320  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7321  * The OS initialization, configuring of the adapter private structure,
7322  * and a hardware reset occur.
7323  **/
7324 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7325                                  const struct pci_device_id *ent)
7326 {
7327         struct net_device *netdev;
7328         struct ixgbe_adapter *adapter = NULL;
7329         struct ixgbe_hw *hw;
7330         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7331         static int cards_found;
7332         int i, err, pci_using_dac;
7333         u8 part_str[IXGBE_PBANUM_LENGTH];
7334         unsigned int indices = num_possible_cpus();
7335 #ifdef IXGBE_FCOE
7336         u16 device_caps;
7337 #endif
7338         u32 eec;
7339
7340         /* Catch broken hardware that put the wrong VF device ID in
7341          * the PCIe SR-IOV capability.
7342          */
7343         if (pdev->is_virtfn) {
7344                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7345                      pci_name(pdev), pdev->vendor, pdev->device);
7346                 return -EINVAL;
7347         }
7348
7349         err = pci_enable_device_mem(pdev);
7350         if (err)
7351                 return err;
7352
7353         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7354             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7355                 pci_using_dac = 1;
7356         } else {
7357                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7358                 if (err) {
7359                         err = dma_set_coherent_mask(&pdev->dev,
7360                                                     DMA_BIT_MASK(32));
7361                         if (err) {
7362                                 dev_err(&pdev->dev,
7363                                         "No usable DMA configuration, aborting\n");
7364                                 goto err_dma;
7365                         }
7366                 }
7367                 pci_using_dac = 0;
7368         }
7369
7370         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7371                                            IORESOURCE_MEM), ixgbe_driver_name);
7372         if (err) {
7373                 dev_err(&pdev->dev,
7374                         "pci_request_selected_regions failed 0x%x\n", err);
7375                 goto err_pci_reg;
7376         }
7377
7378         pci_enable_pcie_error_reporting(pdev);
7379
7380         pci_set_master(pdev);
7381         pci_save_state(pdev);
7382
7383 #ifdef CONFIG_IXGBE_DCB
7384         indices *= MAX_TRAFFIC_CLASS;
7385 #endif
7386
7387         if (ii->mac == ixgbe_mac_82598EB)
7388                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7389         else
7390                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7391
7392 #ifdef IXGBE_FCOE
7393         indices += min_t(unsigned int, num_possible_cpus(),
7394                          IXGBE_MAX_FCOE_INDICES);
7395 #endif
7396         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7397         if (!netdev) {
7398                 err = -ENOMEM;
7399                 goto err_alloc_etherdev;
7400         }
7401
7402         SET_NETDEV_DEV(netdev, &pdev->dev);
7403
7404         adapter = netdev_priv(netdev);
7405         pci_set_drvdata(pdev, adapter);
7406
7407         adapter->netdev = netdev;
7408         adapter->pdev = pdev;
7409         hw = &adapter->hw;
7410         hw->back = adapter;
7411         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7412
7413         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7414                               pci_resource_len(pdev, 0));
7415         if (!hw->hw_addr) {
7416                 err = -EIO;
7417                 goto err_ioremap;
7418         }
7419
7420         for (i = 1; i <= 5; i++) {
7421                 if (pci_resource_len(pdev, i) == 0)
7422                         continue;
7423         }
7424
7425         netdev->netdev_ops = &ixgbe_netdev_ops;
7426         ixgbe_set_ethtool_ops(netdev);
7427         netdev->watchdog_timeo = 5 * HZ;
7428         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7429
7430         adapter->bd_number = cards_found;
7431
7432         /* Setup hw api */
7433         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7434         hw->mac.type  = ii->mac;
7435
7436         /* EEPROM */
7437         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7438         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7439         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7440         if (!(eec & (1 << 8)))
7441                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7442
7443         /* PHY */
7444         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7445         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7446         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7447         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7448         hw->phy.mdio.mmds = 0;
7449         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7450         hw->phy.mdio.dev = netdev;
7451         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7452         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7453
7454         ii->get_invariants(hw);
7455
7456         /* setup the private structure */
7457         err = ixgbe_sw_init(adapter);
7458         if (err)
7459                 goto err_sw_init;
7460
7461         /* Make it possible the adapter to be woken up via WOL */
7462         switch (adapter->hw.mac.type) {
7463         case ixgbe_mac_82599EB:
7464         case ixgbe_mac_X540:
7465                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7466                 break;
7467         default:
7468                 break;
7469         }
7470
7471         /*
7472          * If there is a fan on this device and it has failed log the
7473          * failure.
7474          */
7475         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7476                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7477                 if (esdp & IXGBE_ESDP_SDP1)
7478                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7479         }
7480
7481         /* reset_hw fills in the perm_addr as well */
7482         hw->phy.reset_if_overtemp = true;
7483         err = hw->mac.ops.reset_hw(hw);
7484         hw->phy.reset_if_overtemp = false;
7485         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7486             hw->mac.type == ixgbe_mac_82598EB) {
7487                 err = 0;
7488         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7489                 e_dev_err("failed to load because an unsupported SFP+ "
7490                           "module type was detected.\n");
7491                 e_dev_err("Reload the driver after installing a supported "
7492                           "module.\n");
7493                 goto err_sw_init;
7494         } else if (err) {
7495                 e_dev_err("HW Init failed: %d\n", err);
7496                 goto err_sw_init;
7497         }
7498
7499         ixgbe_probe_vf(adapter, ii);
7500
7501         netdev->features = NETIF_F_SG |
7502                            NETIF_F_IP_CSUM |
7503                            NETIF_F_IPV6_CSUM |
7504                            NETIF_F_HW_VLAN_TX |
7505                            NETIF_F_HW_VLAN_RX |
7506                            NETIF_F_HW_VLAN_FILTER |
7507                            NETIF_F_TSO |
7508                            NETIF_F_TSO6 |
7509                            NETIF_F_GRO |
7510                            NETIF_F_RXHASH |
7511                            NETIF_F_RXCSUM;
7512
7513         netdev->hw_features = netdev->features;
7514
7515         switch (adapter->hw.mac.type) {
7516         case ixgbe_mac_82599EB:
7517         case ixgbe_mac_X540:
7518                 netdev->features |= NETIF_F_SCTP_CSUM;
7519                 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7520                                        NETIF_F_NTUPLE;
7521                 break;
7522         default:
7523                 break;
7524         }
7525
7526         netdev->vlan_features |= NETIF_F_TSO;
7527         netdev->vlan_features |= NETIF_F_TSO6;
7528         netdev->vlan_features |= NETIF_F_IP_CSUM;
7529         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7530         netdev->vlan_features |= NETIF_F_SG;
7531
7532         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7533                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7534                                     IXGBE_FLAG_DCB_ENABLED);
7535
7536 #ifdef CONFIG_IXGBE_DCB
7537         netdev->dcbnl_ops = &dcbnl_ops;
7538 #endif
7539
7540 #ifdef IXGBE_FCOE
7541         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7542                 if (hw->mac.ops.get_device_caps) {
7543                         hw->mac.ops.get_device_caps(hw, &device_caps);
7544                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7545                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7546                 }
7547         }
7548         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7549                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7550                 netdev->vlan_features |= NETIF_F_FSO;
7551                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7552         }
7553 #endif /* IXGBE_FCOE */
7554         if (pci_using_dac) {
7555                 netdev->features |= NETIF_F_HIGHDMA;
7556                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7557         }
7558
7559         if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7560                 netdev->hw_features |= NETIF_F_LRO;
7561         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7562                 netdev->features |= NETIF_F_LRO;
7563
7564         /* make sure the EEPROM is good */
7565         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7566                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7567                 err = -EIO;
7568                 goto err_eeprom;
7569         }
7570
7571         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7572         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7573
7574         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7575                 e_dev_err("invalid MAC address\n");
7576                 err = -EIO;
7577                 goto err_eeprom;
7578         }
7579
7580         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7581         if (hw->mac.ops.disable_tx_laser &&
7582             ((hw->phy.multispeed_fiber) ||
7583              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7584               (hw->mac.type == ixgbe_mac_82599EB))))
7585                 hw->mac.ops.disable_tx_laser(hw);
7586
7587         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7588                     (unsigned long) adapter);
7589
7590         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7591         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7592
7593         err = ixgbe_init_interrupt_scheme(adapter);
7594         if (err)
7595                 goto err_sw_init;
7596
7597         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7598                 netdev->hw_features &= ~NETIF_F_RXHASH;
7599                 netdev->features &= ~NETIF_F_RXHASH;
7600         }
7601
7602         switch (pdev->device) {
7603         case IXGBE_DEV_ID_82599_SFP:
7604                 /* Only this subdevice supports WOL */
7605                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7606                         adapter->wol = IXGBE_WUFC_MAG;
7607                 break;
7608         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7609                 /* All except this subdevice support WOL */
7610                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7611                         adapter->wol = IXGBE_WUFC_MAG;
7612                 break;
7613         case IXGBE_DEV_ID_82599_KX4:
7614                 adapter->wol = IXGBE_WUFC_MAG;
7615                 break;
7616         default:
7617                 adapter->wol = 0;
7618                 break;
7619         }
7620         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7621
7622         /* pick up the PCI bus settings for reporting later */
7623         hw->mac.ops.get_bus_info(hw);
7624
7625         /* print bus type/speed/width info */
7626         e_dev_info("(PCI Express:%s:%s) %pM\n",
7627                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7628                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7629                     "Unknown"),
7630                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7631                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7632                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7633                     "Unknown"),
7634                    netdev->dev_addr);
7635
7636         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7637         if (err)
7638                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7639         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7640                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7641                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7642                            part_str);
7643         else
7644                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7645                            hw->mac.type, hw->phy.type, part_str);
7646
7647         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7648                 e_dev_warn("PCI-Express bandwidth available for this card is "
7649                            "not sufficient for optimal performance.\n");
7650                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7651                            "is required.\n");
7652         }
7653
7654         /* save off EEPROM version number */
7655         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7656
7657         /* reset the hardware with the new settings */
7658         err = hw->mac.ops.start_hw(hw);
7659
7660         if (err == IXGBE_ERR_EEPROM_VERSION) {
7661                 /* We are running on a pre-production device, log a warning */
7662                 e_dev_warn("This device is a pre-production adapter/LOM. "
7663                            "Please be aware there may be issues associated "
7664                            "with your hardware.  If you are experiencing "
7665                            "problems please contact your Intel or hardware "
7666                            "representative who provided you with this "
7667                            "hardware.\n");
7668         }
7669         strcpy(netdev->name, "eth%d");
7670         err = register_netdev(netdev);
7671         if (err)
7672                 goto err_register;
7673
7674         /* carrier off reporting is important to ethtool even BEFORE open */
7675         netif_carrier_off(netdev);
7676
7677 #ifdef CONFIG_IXGBE_DCA
7678         if (dca_add_requester(&pdev->dev) == 0) {
7679                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7680                 ixgbe_setup_dca(adapter);
7681         }
7682 #endif
7683         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7684                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7685                 for (i = 0; i < adapter->num_vfs; i++)
7686                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7687         }
7688
7689         /* Inform firmware of driver version */
7690         if (hw->mac.ops.set_fw_drv_ver)
7691                 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7692                                            FW_CEM_UNUSED_VER);
7693
7694         /* add san mac addr to netdev */
7695         ixgbe_add_sanmac_netdev(netdev);
7696
7697         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7698         cards_found++;
7699         return 0;
7700
7701 err_register:
7702         ixgbe_release_hw_control(adapter);
7703         ixgbe_clear_interrupt_scheme(adapter);
7704 err_sw_init:
7705 err_eeprom:
7706         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7707                 ixgbe_disable_sriov(adapter);
7708         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7709         iounmap(hw->hw_addr);
7710 err_ioremap:
7711         free_netdev(netdev);
7712 err_alloc_etherdev:
7713         pci_release_selected_regions(pdev,
7714                                      pci_select_bars(pdev, IORESOURCE_MEM));
7715 err_pci_reg:
7716 err_dma:
7717         pci_disable_device(pdev);
7718         return err;
7719 }
7720
7721 /**
7722  * ixgbe_remove - Device Removal Routine
7723  * @pdev: PCI device information struct
7724  *
7725  * ixgbe_remove is called by the PCI subsystem to alert the driver
7726  * that it should release a PCI device.  The could be caused by a
7727  * Hot-Plug event, or because the driver is going to be removed from
7728  * memory.
7729  **/
7730 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7731 {
7732         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7733         struct net_device *netdev = adapter->netdev;
7734
7735         set_bit(__IXGBE_DOWN, &adapter->state);
7736         cancel_work_sync(&adapter->service_task);
7737
7738 #ifdef CONFIG_IXGBE_DCA
7739         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7740                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7741                 dca_remove_requester(&pdev->dev);
7742                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7743         }
7744
7745 #endif
7746 #ifdef IXGBE_FCOE
7747         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7748                 ixgbe_cleanup_fcoe(adapter);
7749
7750 #endif /* IXGBE_FCOE */
7751
7752         /* remove the added san mac */
7753         ixgbe_del_sanmac_netdev(netdev);
7754
7755         if (netdev->reg_state == NETREG_REGISTERED)
7756                 unregister_netdev(netdev);
7757
7758         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7759                 ixgbe_disable_sriov(adapter);
7760
7761         ixgbe_clear_interrupt_scheme(adapter);
7762
7763         ixgbe_release_hw_control(adapter);
7764
7765         iounmap(adapter->hw.hw_addr);
7766         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7767                                      IORESOURCE_MEM));
7768
7769         e_dev_info("complete\n");
7770
7771         free_netdev(netdev);
7772
7773         pci_disable_pcie_error_reporting(pdev);
7774
7775         pci_disable_device(pdev);
7776 }
7777
7778 /**
7779  * ixgbe_io_error_detected - called when PCI error is detected
7780  * @pdev: Pointer to PCI device
7781  * @state: The current pci connection state
7782  *
7783  * This function is called after a PCI bus error affecting
7784  * this device has been detected.
7785  */
7786 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7787                                                 pci_channel_state_t state)
7788 {
7789         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7790         struct net_device *netdev = adapter->netdev;
7791
7792         netif_device_detach(netdev);
7793
7794         if (state == pci_channel_io_perm_failure)
7795                 return PCI_ERS_RESULT_DISCONNECT;
7796
7797         if (netif_running(netdev))
7798                 ixgbe_down(adapter);
7799         pci_disable_device(pdev);
7800
7801         /* Request a slot reset. */
7802         return PCI_ERS_RESULT_NEED_RESET;
7803 }
7804
7805 /**
7806  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7807  * @pdev: Pointer to PCI device
7808  *
7809  * Restart the card from scratch, as if from a cold-boot.
7810  */
7811 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7812 {
7813         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7814         pci_ers_result_t result;
7815         int err;
7816
7817         if (pci_enable_device_mem(pdev)) {
7818                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7819                 result = PCI_ERS_RESULT_DISCONNECT;
7820         } else {
7821                 pci_set_master(pdev);
7822                 pci_restore_state(pdev);
7823                 pci_save_state(pdev);
7824
7825                 pci_wake_from_d3(pdev, false);
7826
7827                 ixgbe_reset(adapter);
7828                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7829                 result = PCI_ERS_RESULT_RECOVERED;
7830         }
7831
7832         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7833         if (err) {
7834                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7835                           "failed 0x%0x\n", err);
7836                 /* non-fatal, continue */
7837         }
7838
7839         return result;
7840 }
7841
7842 /**
7843  * ixgbe_io_resume - called when traffic can start flowing again.
7844  * @pdev: Pointer to PCI device
7845  *
7846  * This callback is called when the error recovery driver tells us that
7847  * its OK to resume normal operation.
7848  */
7849 static void ixgbe_io_resume(struct pci_dev *pdev)
7850 {
7851         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7852         struct net_device *netdev = adapter->netdev;
7853
7854         if (netif_running(netdev)) {
7855                 if (ixgbe_up(adapter)) {
7856                         e_info(probe, "ixgbe_up failed after reset\n");
7857                         return;
7858                 }
7859         }
7860
7861         netif_device_attach(netdev);
7862 }
7863
7864 static struct pci_error_handlers ixgbe_err_handler = {
7865         .error_detected = ixgbe_io_error_detected,
7866         .slot_reset = ixgbe_io_slot_reset,
7867         .resume = ixgbe_io_resume,
7868 };
7869
7870 static struct pci_driver ixgbe_driver = {
7871         .name     = ixgbe_driver_name,
7872         .id_table = ixgbe_pci_tbl,
7873         .probe    = ixgbe_probe,
7874         .remove   = __devexit_p(ixgbe_remove),
7875 #ifdef CONFIG_PM
7876         .suspend  = ixgbe_suspend,
7877         .resume   = ixgbe_resume,
7878 #endif
7879         .shutdown = ixgbe_shutdown,
7880         .err_handler = &ixgbe_err_handler
7881 };
7882
7883 /**
7884  * ixgbe_init_module - Driver Registration Routine
7885  *
7886  * ixgbe_init_module is the first routine called when the driver is
7887  * loaded. All it does is register with the PCI subsystem.
7888  **/
7889 static int __init ixgbe_init_module(void)
7890 {
7891         int ret;
7892         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7893         pr_info("%s\n", ixgbe_copyright);
7894
7895 #ifdef CONFIG_IXGBE_DCA
7896         dca_register_notify(&dca_notifier);
7897 #endif
7898
7899         ret = pci_register_driver(&ixgbe_driver);
7900         return ret;
7901 }
7902
7903 module_init(ixgbe_init_module);
7904
7905 /**
7906  * ixgbe_exit_module - Driver Exit Cleanup Routine
7907  *
7908  * ixgbe_exit_module is called just before the driver is removed
7909  * from memory.
7910  **/
7911 static void __exit ixgbe_exit_module(void)
7912 {
7913 #ifdef CONFIG_IXGBE_DCA
7914         dca_unregister_notify(&dca_notifier);
7915 #endif
7916         pci_unregister_driver(&ixgbe_driver);
7917         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7918 }
7919
7920 #ifdef CONFIG_IXGBE_DCA
7921 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7922                             void *p)
7923 {
7924         int ret_val;
7925
7926         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7927                                          __ixgbe_notify_dca);
7928
7929         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7930 }
7931
7932 #endif /* CONFIG_IXGBE_DCA */
7933
7934 module_exit(ixgbe_exit_module);
7935
7936 /* ixgbe_main.c */