drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47
  48 char ixgbe_driver_name[] = "ixgbe";
  49 static const char ixgbe_driver_string[] =
  50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  51
  52 #define DRV_VERSION "2.0.34-k2"
  53 const char ixgbe_driver_version[] = DRV_VERSION;
  54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598] = &ixgbe_82598_info,
  58         [board_82599] = &ixgbe_82599_info,
  59 };
  60
  61 /* ixgbe_pci_tbl - PCI Device ID Table
  62  *
  63  * Wildcard entries (PCI_ANY_ID) should come last
  64  * Last entry must be all 0s
  65  *
  66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  67  *   Class, Class Mask, private data (not used) }
  68  */
  69 static struct pci_device_id ixgbe_pci_tbl[] = {
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  93          board_82599 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  95          board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  97          board_82599 },
  98
  99         /* required last entry */
 100         {0, }
 101 };
 102 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 103
 104 #ifdef CONFIG_IXGBE_DCA
 105 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 106                             void *p);
 107 static struct notifier_block dca_notifier = {
 108         .notifier_call = ixgbe_notify_dca,
 109         .next          = NULL,
 110         .priority      = 0
 111 };
 112 #endif
 113
 114 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 115 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 116 MODULE_LICENSE("GPL");
 117 MODULE_VERSION(DRV_VERSION);
 118
 119 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 120
 121 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 122 {
 123         u32 ctrl_ext;
 124
 125         /* Let firmware take over control of h/w */
 126         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 127         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 128                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 129 }
 130
 131 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 132 {
 133         u32 ctrl_ext;
 134
 135         /* Let firmware know the driver has taken over */
 136         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 137         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 138                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 139 }
 140
 141 /*
 142  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 143  * @adapter: pointer to adapter struct
 144  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 145  * @queue: queue to map the corresponding interrupt to
 146  * @msix_vector: the vector to map to the corresponding queue
 147  *
 148  */
 149 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 150                            u8 queue, u8 msix_vector)
 151 {
 152         u32 ivar, index;
 153         struct ixgbe_hw *hw = &adapter->hw;
 154         switch (hw->mac.type) {
 155         case ixgbe_mac_82598EB:
 156                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 157                 if (direction == -1)
 158                         direction = 0;
 159                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 160                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 161                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 162                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 163                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 164                 break;
 165         case ixgbe_mac_82599EB:
 166                 if (direction == -1) {
 167                         /* other causes */
 168                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 169                         index = ((queue & 1) * 8);
 170                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 171                         ivar &= ~(0xFF << index);
 172                         ivar |= (msix_vector << index);
 173                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 174                         break;
 175                 } else {
 176                         /* tx or rx causes */
 177                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 178                         index = ((16 * (queue & 1)) + (8 * direction));
 179                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 180                         ivar &= ~(0xFF << index);
 181                         ivar |= (msix_vector << index);
 182                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 183                         break;
 184                 }
 185         default:
 186                 break;
 187         }
 188 }
 189
 190 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 191                                           u64 qmask)
 192 {
 193         u32 mask;
 194
 195         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 196                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 197                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 198         } else {
 199                 mask = (qmask & 0xFFFFFFFF);
 200                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 201                 mask = (qmask >> 32);
 202                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 203         }
 204 }
 205
 206 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 207                                              struct ixgbe_tx_buffer
 208                                              *tx_buffer_info)
 209 {
 210         tx_buffer_info->dma = 0;
 211         if (tx_buffer_info->skb) {
 212                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 213                               DMA_TO_DEVICE);
 214                 dev_kfree_skb_any(tx_buffer_info->skb);
 215                 tx_buffer_info->skb = NULL;
 216         }
 217         tx_buffer_info->time_stamp = 0;
 218         /* tx_buffer_info must be completely set up in the transmit path */
 219 }
 220
 221 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 222                                        struct ixgbe_ring *tx_ring,
 223                                        unsigned int eop)
 224 {
 225         struct ixgbe_hw *hw = &adapter->hw;
 226
 227         /* Detect a transmit hang in hardware, this serializes the
 228          * check with the clearing of time_stamp and movement of eop */
 229         adapter->detect_tx_hung = false;
 230         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 231             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 232             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 233                 /* detected Tx unit hang */
 234                 union ixgbe_adv_tx_desc *tx_desc;
 235                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 236                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 237                         "  Tx Queue             <%d>\n"
 238                         "  TDH, TDT             <%x>, <%x>\n"
 239                         "  next_to_use          <%x>\n"
 240                         "  next_to_clean        <%x>\n"
 241                         "tx_buffer_info[next_to_clean]\n"
 242                         "  time_stamp           <%lx>\n"
 243                         "  jiffies              <%lx>\n",
 244                         tx_ring->queue_index,
 245                         IXGBE_READ_REG(hw, tx_ring->head),
 246                         IXGBE_READ_REG(hw, tx_ring->tail),
 247                         tx_ring->next_to_use, eop,
 248                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 249                 return true;
 250         }
 251
 252         return false;
 253 }
 254
 255 #define IXGBE_MAX_TXD_PWR       14
 256 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 257
 258 /* Tx Descriptors needed, worst case */
 259 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 260                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 261 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 262         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 263
 264 static void ixgbe_tx_timeout(struct net_device *netdev);
 265
 266 /**
 267  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 268  * @q_vector: structure containing interrupt and ring information
 269  * @tx_ring: tx ring to clean
 270  **/
 271 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 272                                struct ixgbe_ring *tx_ring)
 273 {
 274         struct ixgbe_adapter *adapter = q_vector->adapter;
 275         struct net_device *netdev = adapter->netdev;
 276         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 277         struct ixgbe_tx_buffer *tx_buffer_info;
 278         unsigned int i, eop, count = 0;
 279         unsigned int total_bytes = 0, total_packets = 0;
 280
 281         i = tx_ring->next_to_clean;
 282         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 283         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 284
 285         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 286                (count < tx_ring->work_limit)) {
 287                 bool cleaned = false;
 288                 for ( ; !cleaned; count++) {
 289                         struct sk_buff *skb;
 290                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 291                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 292                         cleaned = (i == eop);
 293                         skb = tx_buffer_info->skb;
 294
 295                         if (cleaned && skb) {
 296                                 unsigned int segs, bytecount;
 297                                 unsigned int hlen = skb_headlen(skb);
 298
 299                                 /* gso_segs is currently only valid for tcp */
 300                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 301 #ifdef IXGBE_FCOE
 302                                 /* adjust for FCoE Sequence Offload */
 303                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 304                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 305                                     skb_is_gso(skb)) {
 306                                         hlen = skb_transport_offset(skb) +
 307                                                 sizeof(struct fc_frame_header) +
 308                                                 sizeof(struct fcoe_crc_eof);
 309                                         segs = DIV_ROUND_UP(skb->len - hlen,
 310                                                 skb_shinfo(skb)->gso_size);
 311                                 }
 312 #endif /* IXGBE_FCOE */
 313                                 /* multiply data chunks by size of headers */
 314                                 bytecount = ((segs - 1) * hlen) + skb->len;
 315                                 total_packets += segs;
 316                                 total_bytes += bytecount;
 317                         }
 318
 319                         ixgbe_unmap_and_free_tx_resource(adapter,
 320                                                          tx_buffer_info);
 321
 322                         tx_desc->wb.status = 0;
 323
 324                         i++;
 325                         if (i == tx_ring->count)
 326                                 i = 0;
 327                 }
 328
 329                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 330                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 331         }
 332
 333         tx_ring->next_to_clean = i;
 334
 335 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 336         if (unlikely(count && netif_carrier_ok(netdev) &&
 337                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 338                 /* Make sure that anybody stopping the queue after this
 339                  * sees the new next_to_clean.
 340                  */
 341                 smp_mb();
 342                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 343                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 344                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 345                         ++adapter->restart_queue;
 346                 }
 347         }
 348
 349         if (adapter->detect_tx_hung) {
 350                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 351                         /* schedule immediate reset if we believe we hung */
 352                         DPRINTK(PROBE, INFO,
 353                                 "tx hang %d detected, resetting adapter\n",
 354                                 adapter->tx_timeout_count + 1);
 355                         ixgbe_tx_timeout(adapter->netdev);
 356                 }
 357         }
 358
 359         /* re-arm the interrupt */
 360         if (count >= tx_ring->work_limit)
 361                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 362
 363         tx_ring->total_bytes += total_bytes;
 364         tx_ring->total_packets += total_packets;
 365         tx_ring->stats.packets += total_packets;
 366         tx_ring->stats.bytes += total_bytes;
 367         adapter->net_stats.tx_bytes += total_bytes;
 368         adapter->net_stats.tx_packets += total_packets;
 369         return (count < tx_ring->work_limit);
 370 }
 371
 372 #ifdef CONFIG_IXGBE_DCA
 373 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 374                                 struct ixgbe_ring *rx_ring)
 375 {
 376         u32 rxctrl;
 377         int cpu = get_cpu();
 378         int q = rx_ring - adapter->rx_ring;
 379
 380         if (rx_ring->cpu != cpu) {
 381                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 382                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 383                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 384                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 385                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 386                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 387                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 388                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 389                 }
 390                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 391                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 392                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 393                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 394                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 395                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 396                 rx_ring->cpu = cpu;
 397         }
 398         put_cpu();
 399 }
 400
 401 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 402                                 struct ixgbe_ring *tx_ring)
 403 {
 404         u32 txctrl;
 405         int cpu = get_cpu();
 406         int q = tx_ring - adapter->tx_ring;
 407
 408         if (tx_ring->cpu != cpu) {
 409                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 410                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 411                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 412                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 413                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 414                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 415                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 416                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 417                 }
 418                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 419                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 420                 tx_ring->cpu = cpu;
 421         }
 422         put_cpu();
 423 }
 424
 425 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 426 {
 427         int i;
 428
 429         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 430                 return;
 431
 432         /* always use CB2 mode, difference is masked in the CB driver */
 433         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 434
 435         for (i = 0; i < adapter->num_tx_queues; i++) {
 436                 adapter->tx_ring[i].cpu = -1;
 437                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 438         }
 439         for (i = 0; i < adapter->num_rx_queues; i++) {
 440                 adapter->rx_ring[i].cpu = -1;
 441                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 442         }
 443 }
 444
 445 static int __ixgbe_notify_dca(struct device *dev, void *data)
 446 {
 447         struct net_device *netdev = dev_get_drvdata(dev);
 448         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 449         unsigned long event = *(unsigned long *)data;
 450
 451         switch (event) {
 452         case DCA_PROVIDER_ADD:
 453                 /* if we're already enabled, don't do it again */
 454                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 455                         break;
 456                 if (dca_add_requester(dev) == 0) {
 457                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 458                         ixgbe_setup_dca(adapter);
 459                         break;
 460                 }
 461                 /* Fall Through since DCA is disabled. */
 462         case DCA_PROVIDER_REMOVE:
 463                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 464                         dca_remove_requester(dev);
 465                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 466                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 467                 }
 468                 break;
 469         }
 470
 471         return 0;
 472 }
 473
 474 #endif /* CONFIG_IXGBE_DCA */
 475 /**
 476  * ixgbe_receive_skb - Send a completed packet up the stack
 477  * @adapter: board private structure
 478  * @skb: packet to send up
 479  * @status: hardware indication of status of receive
 480  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 481  * @rx_desc: rx descriptor
 482  **/
 483 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 484                               struct sk_buff *skb, u8 status,
 485                               struct ixgbe_ring *ring,
 486                               union ixgbe_adv_rx_desc *rx_desc)
 487 {
 488         struct ixgbe_adapter *adapter = q_vector->adapter;
 489         struct napi_struct *napi = &q_vector->napi;
 490         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 491         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 492
 493         skb_record_rx_queue(skb, ring->queue_index);
 494         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 495                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 496                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 497                 else
 498                         napi_gro_receive(napi, skb);
 499         } else {
 500                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 501                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 502                 else
 503                         netif_rx(skb);
 504         }
 505 }
 506
 507 /**
 508  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 509  * @adapter: address of board private structure
 510  * @status_err: hardware indication of status of receive
 511  * @skb: skb currently being received and modified
 512  **/
 513 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 514                                      union ixgbe_adv_rx_desc *rx_desc,
 515                                      struct sk_buff *skb)
 516 {
 517         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 518
 519         skb->ip_summed = CHECKSUM_NONE;
 520
 521         /* Rx csum disabled */
 522         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 523                 return;
 524
 525         /* if IP and error */
 526         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 527             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 528                 adapter->hw_csum_rx_error++;
 529                 return;
 530         }
 531
 532         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 533                 return;
 534
 535         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 536                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 537
 538                 /*
 539                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 540                  * checksum errors.
 541                  */
 542                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 543                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 544                         return;
 545
 546                 adapter->hw_csum_rx_error++;
 547                 return;
 548         }
 549
 550         /* It must be a TCP or UDP packet with a valid checksum */
 551         skb->ip_summed = CHECKSUM_UNNECESSARY;
 552         adapter->hw_csum_rx_good++;
 553 }
 554
 555 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 556                                          struct ixgbe_ring *rx_ring, u32 val)
 557 {
 558         /*
 559          * Force memory writes to complete before letting h/w
 560          * know there are new descriptors to fetch.  (Only
 561          * applicable for weak-ordered memory model archs,
 562          * such as IA-64).
 563          */
 564         wmb();
 565         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 566 }
 567
 568 /**
 569  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 570  * @adapter: address of board private structure
 571  **/
 572 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 573                                    struct ixgbe_ring *rx_ring,
 574                                    int cleaned_count)
 575 {
 576         struct pci_dev *pdev = adapter->pdev;
 577         union ixgbe_adv_rx_desc *rx_desc;
 578         struct ixgbe_rx_buffer *bi;
 579         unsigned int i;
 580
 581         i = rx_ring->next_to_use;
 582         bi = &rx_ring->rx_buffer_info[i];
 583
 584         while (cleaned_count--) {
 585                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 586
 587                 if (!bi->page_dma &&
 588                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 589                         if (!bi->page) {
 590                                 bi->page = alloc_page(GFP_ATOMIC);
 591                                 if (!bi->page) {
 592                                         adapter->alloc_rx_page_failed++;
 593                                         goto no_buffers;
 594                                 }
 595                                 bi->page_offset = 0;
 596                         } else {
 597                                 /* use a half page if we're re-using */
 598                                 bi->page_offset ^= (PAGE_SIZE / 2);
 599                         }
 600
 601                         bi->page_dma = pci_map_page(pdev, bi->page,
 602                                                     bi->page_offset,
 603                                                     (PAGE_SIZE / 2),
 604                                                     PCI_DMA_FROMDEVICE);
 605                 }
 606
 607                 if (!bi->skb) {
 608                         struct sk_buff *skb;
 609                         skb = netdev_alloc_skb(adapter->netdev,
 610                                                (rx_ring->rx_buf_len +
 611                                                 NET_IP_ALIGN));
 612
 613                         if (!skb) {
 614                                 adapter->alloc_rx_buff_failed++;
 615                                 goto no_buffers;
 616                         }
 617
 618                         /*
 619                          * Make buffer alignment 2 beyond a 16 byte boundary
 620                          * this will result in a 16 byte aligned IP header after
 621                          * the 14 byte MAC header is removed
 622                          */
 623                         skb_reserve(skb, NET_IP_ALIGN);
 624
 625                         bi->skb = skb;
 626                         bi->dma = pci_map_single(pdev, skb->data,
 627                                                  rx_ring->rx_buf_len,
 628                                                  PCI_DMA_FROMDEVICE);
 629                 }
 630                 /* Refresh the desc even if buffer_addrs didn't change because
 631                  * each write-back erases this info. */
 632                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 633                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 634                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 635                 } else {
 636                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 637                 }
 638
 639                 i++;
 640                 if (i == rx_ring->count)
 641                         i = 0;
 642                 bi = &rx_ring->rx_buffer_info[i];
 643         }
 644
 645 no_buffers:
 646         if (rx_ring->next_to_use != i) {
 647                 rx_ring->next_to_use = i;
 648                 if (i-- == 0)
 649                         i = (rx_ring->count - 1);
 650
 651                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 652         }
 653 }
 654
 655 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 656 {
 657         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 658 }
 659
 660 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 661 {
 662         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 663 }
 664
 665 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 666 {
 667         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 668                 IXGBE_RXDADV_RSCCNT_MASK) >>
 669                 IXGBE_RXDADV_RSCCNT_SHIFT;
 670 }
 671
 672 /**
 673  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 674  * @skb: pointer to the last skb in the rsc queue
 675  *
 676  * This function changes a queue full of hw rsc buffers into a completed
 677  * packet.  It uses the ->prev pointers to find the first packet and then
 678  * turns it into the frag list owner.
 679  **/
 680 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 681 {
 682         unsigned int frag_list_size = 0;
 683
 684         while (skb->prev) {
 685                 struct sk_buff *prev = skb->prev;
 686                 frag_list_size += skb->len;
 687                 skb->prev = NULL;
 688                 skb = prev;
 689         }
 690
 691         skb_shinfo(skb)->frag_list = skb->next;
 692         skb->next = NULL;
 693         skb->len += frag_list_size;
 694         skb->data_len += frag_list_size;
 695         skb->truesize += frag_list_size;
 696         return skb;
 697 }
 698
 699 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 700                                struct ixgbe_ring *rx_ring,
 701                                int *work_done, int work_to_do)
 702 {
 703         struct ixgbe_adapter *adapter = q_vector->adapter;
 704         struct pci_dev *pdev = adapter->pdev;
 705         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 706         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 707         struct sk_buff *skb;
 708         unsigned int i, rsc_count = 0;
 709         u32 len, staterr;
 710         u16 hdr_info;
 711         bool cleaned = false;
 712         int cleaned_count = 0;
 713         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 714 #ifdef IXGBE_FCOE
 715         int ddp_bytes = 0;
 716 #endif /* IXGBE_FCOE */
 717
 718         i = rx_ring->next_to_clean;
 719         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 720         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 721         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 722
 723         while (staterr & IXGBE_RXD_STAT_DD) {
 724                 u32 upper_len = 0;
 725                 if (*work_done >= work_to_do)
 726                         break;
 727                 (*work_done)++;
 728
 729                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 730                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 731                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 732                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 733                         if (hdr_info & IXGBE_RXDADV_SPH)
 734                                 adapter->rx_hdr_split++;
 735                         if (len > IXGBE_RX_HDR_SIZE)
 736                                 len = IXGBE_RX_HDR_SIZE;
 737                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 738                 } else {
 739                         len = le16_to_cpu(rx_desc->wb.upper.length);
 740                 }
 741
 742                 cleaned = true;
 743                 skb = rx_buffer_info->skb;
 744                 prefetch(skb->data - NET_IP_ALIGN);
 745                 rx_buffer_info->skb = NULL;
 746
 747                 if (rx_buffer_info->dma) {
 748                         pci_unmap_single(pdev, rx_buffer_info->dma,
 749                                          rx_ring->rx_buf_len,
 750                                          PCI_DMA_FROMDEVICE);
 751                         rx_buffer_info->dma = 0;
 752                         skb_put(skb, len);
 753                 }
 754
 755                 if (upper_len) {
 756                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 757                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 758                         rx_buffer_info->page_dma = 0;
 759                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 760                                            rx_buffer_info->page,
 761                                            rx_buffer_info->page_offset,
 762                                            upper_len);
 763
 764                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 765                             (page_count(rx_buffer_info->page) != 1))
 766                                 rx_buffer_info->page = NULL;
 767                         else
 768                                 get_page(rx_buffer_info->page);
 769
 770                         skb->len += upper_len;
 771                         skb->data_len += upper_len;
 772                         skb->truesize += upper_len;
 773                 }
 774
 775                 i++;
 776                 if (i == rx_ring->count)
 777                         i = 0;
 778
 779                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 780                 prefetch(next_rxd);
 781                 cleaned_count++;
 782
 783                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 784                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 785
 786                 if (rsc_count) {
 787                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 788                                      IXGBE_RXDADV_NEXTP_SHIFT;
 789                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 790                         rx_ring->rsc_count += (rsc_count - 1);
 791                 } else {
 792                         next_buffer = &rx_ring->rx_buffer_info[i];
 793                 }
 794
 795                 if (staterr & IXGBE_RXD_STAT_EOP) {
 796                         if (skb->prev)
 797                                 skb = ixgbe_transform_rsc_queue(skb);
 798                         rx_ring->stats.packets++;
 799                         rx_ring->stats.bytes += skb->len;
 800                 } else {
 801                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 802                                 rx_buffer_info->skb = next_buffer->skb;
 803                                 rx_buffer_info->dma = next_buffer->dma;
 804                                 next_buffer->skb = skb;
 805                                 next_buffer->dma = 0;
 806                         } else {
 807                                 skb->next = next_buffer->skb;
 808                                 skb->next->prev = skb;
 809                         }
 810                         adapter->non_eop_descs++;
 811                         goto next_desc;
 812                 }
 813
 814                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 815                         dev_kfree_skb_irq(skb);
 816                         goto next_desc;
 817                 }
 818
 819                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 820
 821                 /* probably a little skewed due to removing CRC */
 822                 total_rx_bytes += skb->len;
 823                 total_rx_packets++;
 824
 825                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 826 #ifdef IXGBE_FCOE
 827                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 828                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 829                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 830                         if (!ddp_bytes)
 831                                 goto next_desc;
 832                 }
 833 #endif /* IXGBE_FCOE */
 834                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 835
 836 next_desc:
 837                 rx_desc->wb.upper.status_error = 0;
 838
 839                 /* return some buffers to hardware, one at a time is too slow */
 840                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 841                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 842                         cleaned_count = 0;
 843                 }
 844
 845                 /* use prefetched values */
 846                 rx_desc = next_rxd;
 847                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 848
 849                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 850         }
 851
 852         rx_ring->next_to_clean = i;
 853         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 854
 855         if (cleaned_count)
 856                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 857
 858 #ifdef IXGBE_FCOE
 859         /* include DDPed FCoE data */
 860         if (ddp_bytes > 0) {
 861                 unsigned int mss;
 862
 863                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 864                         sizeof(struct fc_frame_header) -
 865                         sizeof(struct fcoe_crc_eof);
 866                 if (mss > 512)
 867                         mss &= ~511;
 868                 total_rx_bytes += ddp_bytes;
 869                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 870         }
 871 #endif /* IXGBE_FCOE */
 872
 873         rx_ring->total_packets += total_rx_packets;
 874         rx_ring->total_bytes += total_rx_bytes;
 875         adapter->net_stats.rx_bytes += total_rx_bytes;
 876         adapter->net_stats.rx_packets += total_rx_packets;
 877
 878         return cleaned;
 879 }
 880
 881 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 882 /**
 883  * ixgbe_configure_msix - Configure MSI-X hardware
 884  * @adapter: board private structure
 885  *
 886  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 887  * interrupts.
 888  **/
 889 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 890 {
 891         struct ixgbe_q_vector *q_vector;
 892         int i, j, q_vectors, v_idx, r_idx;
 893         u32 mask;
 894
 895         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 896
 897         /*
 898          * Populate the IVAR table and set the ITR values to the
 899          * corresponding register.
 900          */
 901         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 902                 q_vector = adapter->q_vector[v_idx];
 903                 /* XXX for_each_bit(...) */
 904                 r_idx = find_first_bit(q_vector->rxr_idx,
 905                                        adapter->num_rx_queues);
 906
 907                 for (i = 0; i < q_vector->rxr_count; i++) {
 908                         j = adapter->rx_ring[r_idx].reg_idx;
 909                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 910                         r_idx = find_next_bit(q_vector->rxr_idx,
 911                                               adapter->num_rx_queues,
 912                                               r_idx + 1);
 913                 }
 914                 r_idx = find_first_bit(q_vector->txr_idx,
 915                                        adapter->num_tx_queues);
 916
 917                 for (i = 0; i < q_vector->txr_count; i++) {
 918                         j = adapter->tx_ring[r_idx].reg_idx;
 919                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 920                         r_idx = find_next_bit(q_vector->txr_idx,
 921                                               adapter->num_tx_queues,
 922                                               r_idx + 1);
 923                 }
 924
 925                 /* if this is a tx only vector halve the interrupt rate */
 926                 if (q_vector->txr_count && !q_vector->rxr_count)
 927                         q_vector->eitr = (adapter->eitr_param >> 1);
 928                 else if (q_vector->rxr_count)
 929                         /* rx only */
 930                         q_vector->eitr = adapter->eitr_param;
 931
 932                 ixgbe_write_eitr(q_vector);
 933         }
 934
 935         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 936                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 937                                v_idx);
 938         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 939                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 940         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 941
 942         /* set up to autoclear timer, and the vectors */
 943         mask = IXGBE_EIMS_ENABLE_MASK;
 944         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 945         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 946 }
 947
 948 enum latency_range {
 949         lowest_latency = 0,
 950         low_latency = 1,
 951         bulk_latency = 2,
 952         latency_invalid = 255
 953 };
 954
 955 /**
 956  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 957  * @adapter: pointer to adapter
 958  * @eitr: eitr setting (ints per sec) to give last timeslice
 959  * @itr_setting: current throttle rate in ints/second
 960  * @packets: the number of packets during this measurement interval
 961  * @bytes: the number of bytes during this measurement interval
 962  *
 963  *      Stores a new ITR value based on packets and byte
 964  *      counts during the last interrupt.  The advantage of per interrupt
 965  *      computation is faster updates and more accurate ITR for the current
 966  *      traffic pattern.  Constants in this function were computed
 967  *      based on theoretical maximum wire speed and thresholds were set based
 968  *      on testing data as well as attempting to minimize response time
 969  *      while increasing bulk throughput.
 970  *      this functionality is controlled by the InterruptThrottleRate module
 971  *      parameter (see ixgbe_param.c)
 972  **/
 973 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 974                            u32 eitr, u8 itr_setting,
 975                            int packets, int bytes)
 976 {
 977         unsigned int retval = itr_setting;
 978         u32 timepassed_us;
 979         u64 bytes_perint;
 980
 981         if (packets == 0)
 982                 goto update_itr_done;
 983
 984
 985         /* simple throttlerate management
 986          *    0-20MB/s lowest (100000 ints/s)
 987          *   20-100MB/s low   (20000 ints/s)
 988          *  100-1249MB/s bulk (8000 ints/s)
 989          */
 990         /* what was last interrupt timeslice? */
 991         timepassed_us = 1000000/eitr;
 992         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 993
 994         switch (itr_setting) {
 995         case lowest_latency:
 996                 if (bytes_perint > adapter->eitr_low)
 997                         retval = low_latency;
 998                 break;
 999         case low_latency:
1000                 if (bytes_perint > adapter->eitr_high)
1001                         retval = bulk_latency;
1002                 else if (bytes_perint <= adapter->eitr_low)
1003                         retval = lowest_latency;
1004                 break;
1005         case bulk_latency:
1006                 if (bytes_perint <= adapter->eitr_high)
1007                         retval = low_latency;
1008                 break;
1009         }
1010
1011 update_itr_done:
1012         return retval;
1013 }
1014
1015 /**
1016  * ixgbe_write_eitr - write EITR register in hardware specific way
1017  * @q_vector: structure containing interrupt and ring information
1018  *
1019  * This function is made to be called by ethtool and by the driver
1020  * when it needs to update EITR registers at runtime.  Hardware
1021  * specific quirks/differences are taken care of here.
1022  */
1023 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1024 {
1025         struct ixgbe_adapter *adapter = q_vector->adapter;
1026         struct ixgbe_hw *hw = &adapter->hw;
1027         int v_idx = q_vector->v_idx;
1028         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1029
1030         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1031                 /* must write high and low 16 bits to reset counter */
1032                 itr_reg |= (itr_reg << 16);
1033         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1034                 /*
1035                  * set the WDIS bit to not clear the timer bits and cause an
1036                  * immediate assertion of the interrupt
1037                  */
1038                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1039         }
1040         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1041 }
1042
1043 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1044 {
1045         struct ixgbe_adapter *adapter = q_vector->adapter;
1046         u32 new_itr;
1047         u8 current_itr, ret_itr;
1048         int i, r_idx;
1049         struct ixgbe_ring *rx_ring, *tx_ring;
1050
1051         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1052         for (i = 0; i < q_vector->txr_count; i++) {
1053                 tx_ring = &(adapter->tx_ring[r_idx]);
1054                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1055                                            q_vector->tx_itr,
1056                                            tx_ring->total_packets,
1057                                            tx_ring->total_bytes);
1058                 /* if the result for this queue would decrease interrupt
1059                  * rate for this vector then use that result */
1060                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1061                                     q_vector->tx_itr - 1 : ret_itr);
1062                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1063                                       r_idx + 1);
1064         }
1065
1066         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1067         for (i = 0; i < q_vector->rxr_count; i++) {
1068                 rx_ring = &(adapter->rx_ring[r_idx]);
1069                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1070                                            q_vector->rx_itr,
1071                                            rx_ring->total_packets,
1072                                            rx_ring->total_bytes);
1073                 /* if the result for this queue would decrease interrupt
1074                  * rate for this vector then use that result */
1075                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1076                                     q_vector->rx_itr - 1 : ret_itr);
1077                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1078                                       r_idx + 1);
1079         }
1080
1081         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1082
1083         switch (current_itr) {
1084         /* counts and packets in update_itr are dependent on these numbers */
1085         case lowest_latency:
1086                 new_itr = 100000;
1087                 break;
1088         case low_latency:
1089                 new_itr = 20000; /* aka hwitr = ~200 */
1090                 break;
1091         case bulk_latency:
1092         default:
1093                 new_itr = 8000;
1094                 break;
1095         }
1096
1097         if (new_itr != q_vector->eitr) {
1098                 /* do an exponential smoothing */
1099                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1100
1101                 /* save the algorithm value here, not the smoothed one */
1102                 q_vector->eitr = new_itr;
1103
1104                 ixgbe_write_eitr(q_vector);
1105         }
1106
1107         return;
1108 }
1109
1110 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1111 {
1112         struct ixgbe_hw *hw = &adapter->hw;
1113
1114         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1115             (eicr & IXGBE_EICR_GPI_SDP1)) {
1116                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1117                 /* write to clear the interrupt */
1118                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1119         }
1120 }
1121
1122 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1123 {
1124         struct ixgbe_hw *hw = &adapter->hw;
1125
1126         if (eicr & IXGBE_EICR_GPI_SDP1) {
1127                 /* Clear the interrupt */
1128                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1129                 schedule_work(&adapter->multispeed_fiber_task);
1130         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1131                 /* Clear the interrupt */
1132                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1133                 schedule_work(&adapter->sfp_config_module_task);
1134         } else {
1135                 /* Interrupt isn't for us... */
1136                 return;
1137         }
1138 }
1139
1140 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1141 {
1142         struct ixgbe_hw *hw = &adapter->hw;
1143
1144         adapter->lsc_int++;
1145         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1146         adapter->link_check_timeout = jiffies;
1147         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1148                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1149                 schedule_work(&adapter->watchdog_task);
1150         }
1151 }
1152
1153 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1154 {
1155         struct net_device *netdev = data;
1156         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1157         struct ixgbe_hw *hw = &adapter->hw;
1158         u32 eicr;
1159
1160         /*
1161          * Workaround for Silicon errata.  Use clear-by-write instead
1162          * of clear-by-read.  Reading with EICS will return the
1163          * interrupt causes without clearing, which later be done
1164          * with the write to EICR.
1165          */
1166         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1167         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1168
1169         if (eicr & IXGBE_EICR_LSC)
1170                 ixgbe_check_lsc(adapter);
1171
1172         if (hw->mac.type == ixgbe_mac_82598EB)
1173                 ixgbe_check_fan_failure(adapter, eicr);
1174
1175         if (hw->mac.type == ixgbe_mac_82599EB) {
1176                 ixgbe_check_sfp_event(adapter, eicr);
1177
1178                 /* Handle Flow Director Full threshold interrupt */
1179                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1180                         int i;
1181                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1182                         /* Disable transmits before FDIR Re-initialization */
1183                         netif_tx_stop_all_queues(netdev);
1184                         for (i = 0; i < adapter->num_tx_queues; i++) {
1185                                 struct ixgbe_ring *tx_ring =
1186                                                            &adapter->tx_ring[i];
1187                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1188                                                        &tx_ring->reinit_state))
1189                                         schedule_work(&adapter->fdir_reinit_task);
1190                         }
1191                 }
1192         }
1193         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1194                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1195
1196         return IRQ_HANDLED;
1197 }
1198
1199 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1200                                            u64 qmask)
1201 {
1202         u32 mask;
1203
1204         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1205                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1206                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1207         } else {
1208                 mask = (qmask & 0xFFFFFFFF);
1209                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1210                 mask = (qmask >> 32);
1211                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1212         }
1213         /* skip the flush */
1214 }
1215
1216 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1217                                             u64 qmask)
1218 {
1219         u32 mask;
1220
1221         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1222                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1223                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1224         } else {
1225                 mask = (qmask & 0xFFFFFFFF);
1226                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1227                 mask = (qmask >> 32);
1228                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1229         }
1230         /* skip the flush */
1231 }
1232
1233 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1234 {
1235         struct ixgbe_q_vector *q_vector = data;
1236         struct ixgbe_adapter  *adapter = q_vector->adapter;
1237         struct ixgbe_ring     *tx_ring;
1238         int i, r_idx;
1239
1240         if (!q_vector->txr_count)
1241                 return IRQ_HANDLED;
1242
1243         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1244         for (i = 0; i < q_vector->txr_count; i++) {
1245                 tx_ring = &(adapter->tx_ring[r_idx]);
1246                 tx_ring->total_bytes = 0;
1247                 tx_ring->total_packets = 0;
1248                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1249                                       r_idx + 1);
1250         }
1251
1252         /* disable interrupts on this vector only */
1253         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1254         napi_schedule(&q_vector->napi);
1255
1256         return IRQ_HANDLED;
1257 }
1258
1259 /**
1260  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1261  * @irq: unused
1262  * @data: pointer to our q_vector struct for this interrupt vector
1263  **/
1264 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1265 {
1266         struct ixgbe_q_vector *q_vector = data;
1267         struct ixgbe_adapter  *adapter = q_vector->adapter;
1268         struct ixgbe_ring  *rx_ring;
1269         int r_idx;
1270         int i;
1271
1272         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1273         for (i = 0;  i < q_vector->rxr_count; i++) {
1274                 rx_ring = &(adapter->rx_ring[r_idx]);
1275                 rx_ring->total_bytes = 0;
1276                 rx_ring->total_packets = 0;
1277                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1278                                       r_idx + 1);
1279         }
1280
1281         if (!q_vector->rxr_count)
1282                 return IRQ_HANDLED;
1283
1284         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1285         rx_ring = &(adapter->rx_ring[r_idx]);
1286         /* disable interrupts on this vector only */
1287         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1288         napi_schedule(&q_vector->napi);
1289
1290         return IRQ_HANDLED;
1291 }
1292
1293 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1294 {
1295         struct ixgbe_q_vector *q_vector = data;
1296         struct ixgbe_adapter  *adapter = q_vector->adapter;
1297         struct ixgbe_ring  *ring;
1298         int r_idx;
1299         int i;
1300
1301         if (!q_vector->txr_count && !q_vector->rxr_count)
1302                 return IRQ_HANDLED;
1303
1304         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1305         for (i = 0; i < q_vector->txr_count; i++) {
1306                 ring = &(adapter->tx_ring[r_idx]);
1307                 ring->total_bytes = 0;
1308                 ring->total_packets = 0;
1309                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1310                                       r_idx + 1);
1311         }
1312
1313         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1314         for (i = 0; i < q_vector->rxr_count; i++) {
1315                 ring = &(adapter->rx_ring[r_idx]);
1316                 ring->total_bytes = 0;
1317                 ring->total_packets = 0;
1318                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1319                                       r_idx + 1);
1320         }
1321
1322         /* disable interrupts on this vector only */
1323         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1324         napi_schedule(&q_vector->napi);
1325
1326         return IRQ_HANDLED;
1327 }
1328
1329 /**
1330  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1331  * @napi: napi struct with our devices info in it
1332  * @budget: amount of work driver is allowed to do this pass, in packets
1333  *
1334  * This function is optimized for cleaning one queue only on a single
1335  * q_vector!!!
1336  **/
1337 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1338 {
1339         struct ixgbe_q_vector *q_vector =
1340                                container_of(napi, struct ixgbe_q_vector, napi);
1341         struct ixgbe_adapter *adapter = q_vector->adapter;
1342         struct ixgbe_ring *rx_ring = NULL;
1343         int work_done = 0;
1344         long r_idx;
1345
1346         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1347         rx_ring = &(adapter->rx_ring[r_idx]);
1348 #ifdef CONFIG_IXGBE_DCA
1349         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1350                 ixgbe_update_rx_dca(adapter, rx_ring);
1351 #endif
1352
1353         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1354
1355         /* If all Rx work done, exit the polling mode */
1356         if (work_done < budget) {
1357                 napi_complete(napi);
1358                 if (adapter->itr_setting & 1)
1359                         ixgbe_set_itr_msix(q_vector);
1360                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1361                         ixgbe_irq_enable_queues(adapter,
1362                                                 ((u64)1 << q_vector->v_idx));
1363         }
1364
1365         return work_done;
1366 }
1367
1368 /**
1369  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1370  * @napi: napi struct with our devices info in it
1371  * @budget: amount of work driver is allowed to do this pass, in packets
1372  *
1373  * This function will clean more than one rx queue associated with a
1374  * q_vector.
1375  **/
1376 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1377 {
1378         struct ixgbe_q_vector *q_vector =
1379                                container_of(napi, struct ixgbe_q_vector, napi);
1380         struct ixgbe_adapter *adapter = q_vector->adapter;
1381         struct ixgbe_ring *ring = NULL;
1382         int work_done = 0, i;
1383         long r_idx;
1384         bool tx_clean_complete = true;
1385
1386         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1387         for (i = 0; i < q_vector->txr_count; i++) {
1388                 ring = &(adapter->tx_ring[r_idx]);
1389 #ifdef CONFIG_IXGBE_DCA
1390                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1391                         ixgbe_update_tx_dca(adapter, ring);
1392 #endif
1393                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1394                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1395                                       r_idx + 1);
1396         }
1397
1398         /* attempt to distribute budget to each queue fairly, but don't allow
1399          * the budget to go below 1 because we'll exit polling */
1400         budget /= (q_vector->rxr_count ?: 1);
1401         budget = max(budget, 1);
1402         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1403         for (i = 0; i < q_vector->rxr_count; i++) {
1404                 ring = &(adapter->rx_ring[r_idx]);
1405 #ifdef CONFIG_IXGBE_DCA
1406                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1407                         ixgbe_update_rx_dca(adapter, ring);
1408 #endif
1409                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1410                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1411                                       r_idx + 1);
1412         }
1413
1414         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1415         ring = &(adapter->rx_ring[r_idx]);
1416         /* If all Rx work done, exit the polling mode */
1417         if (work_done < budget) {
1418                 napi_complete(napi);
1419                 if (adapter->itr_setting & 1)
1420                         ixgbe_set_itr_msix(q_vector);
1421                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1422                         ixgbe_irq_enable_queues(adapter,
1423                                                 ((u64)1 << q_vector->v_idx));
1424                 return 0;
1425         }
1426
1427         return work_done;
1428 }
1429
1430 /**
1431  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1432  * @napi: napi struct with our devices info in it
1433  * @budget: amount of work driver is allowed to do this pass, in packets
1434  *
1435  * This function is optimized for cleaning one queue only on a single
1436  * q_vector!!!
1437  **/
1438 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1439 {
1440         struct ixgbe_q_vector *q_vector =
1441                                container_of(napi, struct ixgbe_q_vector, napi);
1442         struct ixgbe_adapter *adapter = q_vector->adapter;
1443         struct ixgbe_ring *tx_ring = NULL;
1444         int work_done = 0;
1445         long r_idx;
1446
1447         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1448         tx_ring = &(adapter->tx_ring[r_idx]);
1449 #ifdef CONFIG_IXGBE_DCA
1450         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1451                 ixgbe_update_tx_dca(adapter, tx_ring);
1452 #endif
1453
1454         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1455                 work_done = budget;
1456
1457         /* If all Rx work done, exit the polling mode */
1458         if (work_done < budget) {
1459                 napi_complete(napi);
1460                 if (adapter->itr_setting & 1)
1461                         ixgbe_set_itr_msix(q_vector);
1462                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1463                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1464         }
1465
1466         return work_done;
1467 }
1468
1469 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1470                                      int r_idx)
1471 {
1472         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1473
1474         set_bit(r_idx, q_vector->rxr_idx);
1475         q_vector->rxr_count++;
1476 }
1477
1478 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1479                                      int t_idx)
1480 {
1481         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1482
1483         set_bit(t_idx, q_vector->txr_idx);
1484         q_vector->txr_count++;
1485 }
1486
1487 /**
1488  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1489  * @adapter: board private structure to initialize
1490  * @vectors: allotted vector count for descriptor rings
1491  *
1492  * This function maps descriptor rings to the queue-specific vectors
1493  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1494  * one vector per ring/queue, but on a constrained vector budget, we
1495  * group the rings as "efficiently" as possible.  You would add new
1496  * mapping configurations in here.
1497  **/
1498 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1499                                       int vectors)
1500 {
1501         int v_start = 0;
1502         int rxr_idx = 0, txr_idx = 0;
1503         int rxr_remaining = adapter->num_rx_queues;
1504         int txr_remaining = adapter->num_tx_queues;
1505         int i, j;
1506         int rqpv, tqpv;
1507         int err = 0;
1508
1509         /* No mapping required if MSI-X is disabled. */
1510         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1511                 goto out;
1512
1513         /*
1514          * The ideal configuration...
1515          * We have enough vectors to map one per queue.
1516          */
1517         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1518                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1519                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1520
1521                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1522                         map_vector_to_txq(adapter, v_start, txr_idx);
1523
1524                 goto out;
1525         }
1526
1527         /*
1528          * If we don't have enough vectors for a 1-to-1
1529          * mapping, we'll have to group them so there are
1530          * multiple queues per vector.
1531          */
1532         /* Re-adjusting *qpv takes care of the remainder. */
1533         for (i = v_start; i < vectors; i++) {
1534                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1535                 for (j = 0; j < rqpv; j++) {
1536                         map_vector_to_rxq(adapter, i, rxr_idx);
1537                         rxr_idx++;
1538                         rxr_remaining--;
1539                 }
1540         }
1541         for (i = v_start; i < vectors; i++) {
1542                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1543                 for (j = 0; j < tqpv; j++) {
1544                         map_vector_to_txq(adapter, i, txr_idx);
1545                         txr_idx++;
1546                         txr_remaining--;
1547                 }
1548         }
1549
1550 out:
1551         return err;
1552 }
1553
1554 /**
1555  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1556  * @adapter: board private structure
1557  *
1558  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1559  * interrupts from the kernel.
1560  **/
1561 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1562 {
1563         struct net_device *netdev = adapter->netdev;
1564         irqreturn_t (*handler)(int, void *);
1565         int i, vector, q_vectors, err;
1566         int ri=0, ti=0;
1567
1568         /* Decrement for Other and TCP Timer vectors */
1569         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1570
1571         /* Map the Tx/Rx rings to the vectors we were allotted. */
1572         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1573         if (err)
1574                 goto out;
1575
1576 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1577                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1578                          &ixgbe_msix_clean_many)
1579         for (vector = 0; vector < q_vectors; vector++) {
1580                 handler = SET_HANDLER(adapter->q_vector[vector]);
1581
1582                 if(handler == &ixgbe_msix_clean_rx) {
1583                         sprintf(adapter->name[vector], "%s-%s-%d",
1584                                 netdev->name, "rx", ri++);
1585                 }
1586                 else if(handler == &ixgbe_msix_clean_tx) {
1587                         sprintf(adapter->name[vector], "%s-%s-%d",
1588                                 netdev->name, "tx", ti++);
1589                 }
1590                 else
1591                         sprintf(adapter->name[vector], "%s-%s-%d",
1592                                 netdev->name, "TxRx", vector);
1593
1594                 err = request_irq(adapter->msix_entries[vector].vector,
1595                                   handler, 0, adapter->name[vector],
1596                                   adapter->q_vector[vector]);
1597                 if (err) {
1598                         DPRINTK(PROBE, ERR,
1599                                 "request_irq failed for MSIX interrupt "
1600                                 "Error: %d\n", err);
1601                         goto free_queue_irqs;
1602                 }
1603         }
1604
1605         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1606         err = request_irq(adapter->msix_entries[vector].vector,
1607                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1608         if (err) {
1609                 DPRINTK(PROBE, ERR,
1610                         "request_irq for msix_lsc failed: %d\n", err);
1611                 goto free_queue_irqs;
1612         }
1613
1614         return 0;
1615
1616 free_queue_irqs:
1617         for (i = vector - 1; i >= 0; i--)
1618                 free_irq(adapter->msix_entries[--vector].vector,
1619                          adapter->q_vector[i]);
1620         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1621         pci_disable_msix(adapter->pdev);
1622         kfree(adapter->msix_entries);
1623         adapter->msix_entries = NULL;
1624 out:
1625         return err;
1626 }
1627
1628 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1629 {
1630         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1631         u8 current_itr;
1632         u32 new_itr = q_vector->eitr;
1633         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1634         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1635
1636         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1637                                             q_vector->tx_itr,
1638                                             tx_ring->total_packets,
1639                                             tx_ring->total_bytes);
1640         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1641                                             q_vector->rx_itr,
1642                                             rx_ring->total_packets,
1643                                             rx_ring->total_bytes);
1644
1645         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1646
1647         switch (current_itr) {
1648         /* counts and packets in update_itr are dependent on these numbers */
1649         case lowest_latency:
1650                 new_itr = 100000;
1651                 break;
1652         case low_latency:
1653                 new_itr = 20000; /* aka hwitr = ~200 */
1654                 break;
1655         case bulk_latency:
1656                 new_itr = 8000;
1657                 break;
1658         default:
1659                 break;
1660         }
1661
1662         if (new_itr != q_vector->eitr) {
1663                 /* do an exponential smoothing */
1664                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1665
1666                 /* save the algorithm value here, not the smoothed one */
1667                 q_vector->eitr = new_itr;
1668
1669                 ixgbe_write_eitr(q_vector);
1670         }
1671
1672         return;
1673 }
1674
1675 /**
1676  * ixgbe_irq_enable - Enable default interrupt generation settings
1677  * @adapter: board private structure
1678  **/
1679 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1680 {
1681         u32 mask;
1682
1683         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1684         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1685                 mask |= IXGBE_EIMS_GPI_SDP1;
1686         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1687                 mask |= IXGBE_EIMS_ECC;
1688                 mask |= IXGBE_EIMS_GPI_SDP1;
1689                 mask |= IXGBE_EIMS_GPI_SDP2;
1690         }
1691         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1692             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1693                 mask |= IXGBE_EIMS_FLOW_DIR;
1694
1695         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1696         ixgbe_irq_enable_queues(adapter, ~0);
1697         IXGBE_WRITE_FLUSH(&adapter->hw);
1698 }
1699
1700 /**
1701  * ixgbe_intr - legacy mode Interrupt Handler
1702  * @irq: interrupt number
1703  * @data: pointer to a network interface device structure
1704  **/
1705 static irqreturn_t ixgbe_intr(int irq, void *data)
1706 {
1707         struct net_device *netdev = data;
1708         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1709         struct ixgbe_hw *hw = &adapter->hw;
1710         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1711         u32 eicr;
1712
1713         /*
1714          * Workaround for silicon errata.  Mask the interrupts
1715          * before the read of EICR.
1716          */
1717         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1718
1719         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1720          * therefore no explict interrupt disable is necessary */
1721         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1722         if (!eicr) {
1723                 /* shared interrupt alert!
1724                  * make sure interrupts are enabled because the read will
1725                  * have disabled interrupts due to EIAM */
1726                 ixgbe_irq_enable(adapter);
1727                 return IRQ_NONE;        /* Not our interrupt */
1728         }
1729
1730         if (eicr & IXGBE_EICR_LSC)
1731                 ixgbe_check_lsc(adapter);
1732
1733         if (hw->mac.type == ixgbe_mac_82599EB)
1734                 ixgbe_check_sfp_event(adapter, eicr);
1735
1736         ixgbe_check_fan_failure(adapter, eicr);
1737
1738         if (napi_schedule_prep(&(q_vector->napi))) {
1739                 adapter->tx_ring[0].total_packets = 0;
1740                 adapter->tx_ring[0].total_bytes = 0;
1741                 adapter->rx_ring[0].total_packets = 0;
1742                 adapter->rx_ring[0].total_bytes = 0;
1743                 /* would disable interrupts here but EIAM disabled it */
1744                 __napi_schedule(&(q_vector->napi));
1745         }
1746
1747         return IRQ_HANDLED;
1748 }
1749
1750 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1751 {
1752         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1753
1754         for (i = 0; i < q_vectors; i++) {
1755                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1756                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1757                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1758                 q_vector->rxr_count = 0;
1759                 q_vector->txr_count = 0;
1760         }
1761 }
1762
1763 /**
1764  * ixgbe_request_irq - initialize interrupts
1765  * @adapter: board private structure
1766  *
1767  * Attempts to configure interrupts using the best available
1768  * capabilities of the hardware and kernel.
1769  **/
1770 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1771 {
1772         struct net_device *netdev = adapter->netdev;
1773         int err;
1774
1775         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1776                 err = ixgbe_request_msix_irqs(adapter);
1777         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1778                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1779                                   netdev->name, netdev);
1780         } else {
1781                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1782                                   netdev->name, netdev);
1783         }
1784
1785         if (err)
1786                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1787
1788         return err;
1789 }
1790
1791 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1792 {
1793         struct net_device *netdev = adapter->netdev;
1794
1795         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1796                 int i, q_vectors;
1797
1798                 q_vectors = adapter->num_msix_vectors;
1799
1800                 i = q_vectors - 1;
1801                 free_irq(adapter->msix_entries[i].vector, netdev);
1802
1803                 i--;
1804                 for (; i >= 0; i--) {
1805                         free_irq(adapter->msix_entries[i].vector,
1806                                  adapter->q_vector[i]);
1807                 }
1808
1809                 ixgbe_reset_q_vectors(adapter);
1810         } else {
1811                 free_irq(adapter->pdev->irq, netdev);
1812         }
1813 }
1814
1815 /**
1816  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1817  * @adapter: board private structure
1818  **/
1819 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1820 {
1821         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1822                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1823         } else {
1824                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1825                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1826                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1827         }
1828         IXGBE_WRITE_FLUSH(&adapter->hw);
1829         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1830                 int i;
1831                 for (i = 0; i < adapter->num_msix_vectors; i++)
1832                         synchronize_irq(adapter->msix_entries[i].vector);
1833         } else {
1834                 synchronize_irq(adapter->pdev->irq);
1835         }
1836 }
1837
1838 /**
1839  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1840  *
1841  **/
1842 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1843 {
1844         struct ixgbe_hw *hw = &adapter->hw;
1845
1846         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1847                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1848
1849         ixgbe_set_ivar(adapter, 0, 0, 0);
1850         ixgbe_set_ivar(adapter, 1, 0, 0);
1851
1852         map_vector_to_rxq(adapter, 0, 0);
1853         map_vector_to_txq(adapter, 0, 0);
1854
1855         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1856 }
1857
1858 /**
1859  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1860  * @adapter: board private structure
1861  *
1862  * Configure the Tx unit of the MAC after a reset.
1863  **/
1864 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1865 {
1866         u64 tdba;
1867         struct ixgbe_hw *hw = &adapter->hw;
1868         u32 i, j, tdlen, txctrl;
1869
1870         /* Setup the HW Tx Head and Tail descriptor pointers */
1871         for (i = 0; i < adapter->num_tx_queues; i++) {
1872                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1873                 j = ring->reg_idx;
1874                 tdba = ring->dma;
1875                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1876                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1877                                 (tdba & DMA_BIT_MASK(32)));
1878                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1879                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1880                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1881                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1882                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1883                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1884                 /* Disable Tx Head Writeback RO bit, since this hoses
1885                  * bookkeeping if things aren't delivered in order.
1886                  */
1887                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1888                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1889                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1890         }
1891         if (hw->mac.type == ixgbe_mac_82599EB) {
1892                 /* We enable 8 traffic classes, DCB only */
1893                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1894                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1895                                         IXGBE_MTQC_8TC_8TQ));
1896         }
1897 }
1898
1899 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1900
1901 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1902                                    struct ixgbe_ring *rx_ring)
1903 {
1904         u32 srrctl;
1905         int index;
1906         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1907
1908         index = rx_ring->reg_idx;
1909         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1910                 unsigned long mask;
1911                 mask = (unsigned long) feature[RING_F_RSS].mask;
1912                 index = index & mask;
1913         }
1914         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1915
1916         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1917         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1918
1919         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1920                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1921
1922         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1923 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1924                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1925 #else
1926                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1927 #endif
1928                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1929         } else {
1930                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1931                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1932                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1933         }
1934
1935         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1936 }
1937
1938 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1939 {
1940         u32 mrqc = 0;
1941         int mask;
1942
1943         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1944                 return mrqc;
1945
1946         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1947 #ifdef CONFIG_IXGBE_DCB
1948                                  | IXGBE_FLAG_DCB_ENABLED
1949 #endif
1950                                 );
1951
1952         switch (mask) {
1953         case (IXGBE_FLAG_RSS_ENABLED):
1954                 mrqc = IXGBE_MRQC_RSSEN;
1955                 break;
1956 #ifdef CONFIG_IXGBE_DCB
1957         case (IXGBE_FLAG_DCB_ENABLED):
1958                 mrqc = IXGBE_MRQC_RT8TCEN;
1959                 break;
1960 #endif /* CONFIG_IXGBE_DCB */
1961         default:
1962                 break;
1963         }
1964
1965         return mrqc;
1966 }
1967
1968 /**
1969  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1970  * @adapter: board private structure
1971  *
1972  * Configure the Rx unit of the MAC after a reset.
1973  **/
1974 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1975 {
1976         u64 rdba;
1977         struct ixgbe_hw *hw = &adapter->hw;
1978         struct ixgbe_ring *rx_ring;
1979         struct net_device *netdev = adapter->netdev;
1980         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1981         int i, j;
1982         u32 rdlen, rxctrl, rxcsum;
1983         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1984                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1985                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1986         u32 fctrl, hlreg0;
1987         u32 reta = 0, mrqc = 0;
1988         u32 rdrxctl;
1989         u32 rscctrl;
1990         int rx_buf_len;
1991
1992         /* Decide whether to use packet split mode or not */
1993         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1994
1995         /* Set the RX buffer length according to the mode */
1996         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1997                 rx_buf_len = IXGBE_RX_HDR_SIZE;
1998                 if (hw->mac.type == ixgbe_mac_82599EB) {
1999                         /* PSRTYPE must be initialized in 82599 */
2000                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2001                                       IXGBE_PSRTYPE_UDPHDR |
2002                                       IXGBE_PSRTYPE_IPV4HDR |
2003                                       IXGBE_PSRTYPE_IPV6HDR |
2004                                       IXGBE_PSRTYPE_L2HDR;
2005                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2006                 }
2007         } else {
2008                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2009                     (netdev->mtu <= ETH_DATA_LEN))
2010                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2011                 else
2012                         rx_buf_len = ALIGN(max_frame, 1024);
2013         }
2014
2015         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2016         fctrl |= IXGBE_FCTRL_BAM;
2017         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2018         fctrl |= IXGBE_FCTRL_PMCF;
2019         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2020
2021         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2022         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2023                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2024         else
2025                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2026 #ifdef IXGBE_FCOE
2027         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2028                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2029 #endif
2030         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2031
2032         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2033         /* disable receives while setting up the descriptors */
2034         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2035         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2036
2037         /*
2038          * Setup the HW Rx Head and Tail Descriptor Pointers and
2039          * the Base and Length of the Rx Descriptor Ring
2040          */
2041         for (i = 0; i < adapter->num_rx_queues; i++) {
2042                 rx_ring = &adapter->rx_ring[i];
2043                 rdba = rx_ring->dma;
2044                 j = rx_ring->reg_idx;
2045                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2046                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2047                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2048                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2049                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2050                 rx_ring->head = IXGBE_RDH(j);
2051                 rx_ring->tail = IXGBE_RDT(j);
2052                 rx_ring->rx_buf_len = rx_buf_len;
2053
2054                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2055                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2056
2057 #ifdef IXGBE_FCOE
2058                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
2059                         struct ixgbe_ring_feature *f;
2060                         f = &adapter->ring_feature[RING_F_FCOE];
2061                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2062                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2063                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2064                                         rx_ring->rx_buf_len =
2065                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2066                         }
2067                 }
2068
2069 #endif /* IXGBE_FCOE */
2070                 ixgbe_configure_srrctl(adapter, rx_ring);
2071         }
2072
2073         if (hw->mac.type == ixgbe_mac_82598EB) {
2074                 /*
2075                  * For VMDq support of different descriptor types or
2076                  * buffer sizes through the use of multiple SRRCTL
2077                  * registers, RDRXCTL.MVMEN must be set to 1
2078                  *
2079                  * also, the manual doesn't mention it clearly but DCA hints
2080                  * will only use queue 0's tags unless this bit is set.  Side
2081                  * effects of setting this bit are only that SRRCTL must be
2082                  * fully programmed [0..15]
2083                  */
2084                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2085                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2086                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2087         }
2088
2089         /* Program MRQC for the distribution of queues */
2090         mrqc = ixgbe_setup_mrqc(adapter);
2091
2092         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2093                 /* Fill out redirection table */
2094                 for (i = 0, j = 0; i < 128; i++, j++) {
2095                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2096                                 j = 0;
2097                         /* reta = 4-byte sliding window of
2098                          * 0x00..(indices-1)(indices-1)00..etc. */
2099                         reta = (reta << 8) | (j * 0x11);
2100                         if ((i & 3) == 3)
2101                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2102                 }
2103
2104                 /* Fill out hash function seeds */
2105                 for (i = 0; i < 10; i++)
2106                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2107
2108                 if (hw->mac.type == ixgbe_mac_82598EB)
2109                         mrqc |= IXGBE_MRQC_RSSEN;
2110                     /* Perform hash on these packet types */
2111                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2112                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2113                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2114                       | IXGBE_MRQC_RSS_FIELD_IPV6
2115                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2116                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2117         }
2118         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2119
2120         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2121
2122         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2123             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2124                 /* Disable indicating checksum in descriptor, enables
2125                  * RSS hash */
2126                 rxcsum |= IXGBE_RXCSUM_PCSD;
2127         }
2128         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2129                 /* Enable IPv4 payload checksum for UDP fragments
2130                  * if PCSD is not set */
2131                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2132         }
2133
2134         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2135
2136         if (hw->mac.type == ixgbe_mac_82599EB) {
2137                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2138                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2139                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2140                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2141         }
2142
2143         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2144                 /* Enable 82599 HW-RSC */
2145                 for (i = 0; i < adapter->num_rx_queues; i++) {
2146                         rx_ring = &adapter->rx_ring[i];
2147                         j = rx_ring->reg_idx;
2148                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2149                         rscctrl |= IXGBE_RSCCTL_RSCEN;
2150                         /*
2151                          * we must limit the number of descriptors so that the
2152                          * total size of max desc * buf_len is not greater
2153                          * than 65535
2154                          */
2155                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2156 #if (MAX_SKB_FRAGS > 16)
2157                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2158 #elif (MAX_SKB_FRAGS > 8)
2159                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2160 #elif (MAX_SKB_FRAGS > 4)
2161                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2162 #else
2163                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2164 #endif
2165                         } else {
2166                                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2167                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2168                                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2169                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2170                                 else
2171                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2172                         }
2173                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2174                 }
2175                 /* Disable RSC for ACK packets */
2176                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2177                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2178         }
2179 }
2180
2181 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2182 {
2183         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2184         struct ixgbe_hw *hw = &adapter->hw;
2185
2186         /* add VID to filter table */
2187         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2188 }
2189
2190 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2191 {
2192         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2193         struct ixgbe_hw *hw = &adapter->hw;
2194
2195         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2196                 ixgbe_irq_disable(adapter);
2197
2198         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2199
2200         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2201                 ixgbe_irq_enable(adapter);
2202
2203         /* remove VID from filter table */
2204         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2205 }
2206
2207 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2208                                    struct vlan_group *grp)
2209 {
2210         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2211         u32 ctrl;
2212         int i, j;
2213
2214         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2215                 ixgbe_irq_disable(adapter);
2216         adapter->vlgrp = grp;
2217
2218         /*
2219          * For a DCB driver, always enable VLAN tag stripping so we can
2220          * still receive traffic from a DCB-enabled host even if we're
2221          * not in DCB mode.
2222          */
2223         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2224         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2225                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2226                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2227                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2228         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2229                 ctrl |= IXGBE_VLNCTRL_VFE;
2230                 /* enable VLAN tag insert/strip */
2231                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2232                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2233                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2234                 for (i = 0; i < adapter->num_rx_queues; i++) {
2235                         j = adapter->rx_ring[i].reg_idx;
2236                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2237                         ctrl |= IXGBE_RXDCTL_VME;
2238                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2239                 }
2240         }
2241         ixgbe_vlan_rx_add_vid(netdev, 0);
2242
2243         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2244                 ixgbe_irq_enable(adapter);
2245 }
2246
2247 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2248 {
2249         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2250
2251         if (adapter->vlgrp) {
2252                 u16 vid;
2253                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2254                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2255                                 continue;
2256                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2257                 }
2258         }
2259 }
2260
2261 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2262 {
2263         struct dev_mc_list *mc_ptr;
2264         u8 *addr = *mc_addr_ptr;
2265         *vmdq = 0;
2266
2267         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2268         if (mc_ptr->next)
2269                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2270         else
2271                 *mc_addr_ptr = NULL;
2272
2273         return addr;
2274 }
2275
2276 /**
2277  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2278  * @netdev: network interface device structure
2279  *
2280  * The set_rx_method entry point is called whenever the unicast/multicast
2281  * address list or the network interface flags are updated.  This routine is
2282  * responsible for configuring the hardware for proper unicast, multicast and
2283  * promiscuous mode.
2284  **/
2285 static void ixgbe_set_rx_mode(struct net_device *netdev)
2286 {
2287         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2288         struct ixgbe_hw *hw = &adapter->hw;
2289         u32 fctrl, vlnctrl;
2290         u8 *addr_list = NULL;
2291         int addr_count = 0;
2292
2293         /* Check for Promiscuous and All Multicast modes */
2294
2295         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2296         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2297
2298         if (netdev->flags & IFF_PROMISC) {
2299                 hw->addr_ctrl.user_set_promisc = 1;
2300                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2301                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2302         } else {
2303                 if (netdev->flags & IFF_ALLMULTI) {
2304                         fctrl |= IXGBE_FCTRL_MPE;
2305                         fctrl &= ~IXGBE_FCTRL_UPE;
2306                 } else {
2307                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2308                 }
2309                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2310                 hw->addr_ctrl.user_set_promisc = 0;
2311         }
2312
2313         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2314         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2315
2316         /* reprogram secondary unicast list */
2317         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2318
2319         /* reprogram multicast list */
2320         addr_count = netdev->mc_count;
2321         if (addr_count)
2322                 addr_list = netdev->mc_list->dmi_addr;
2323         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2324                                         ixgbe_addr_list_itr);
2325 }
2326
2327 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2328 {
2329         int q_idx;
2330         struct ixgbe_q_vector *q_vector;
2331         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2332
2333         /* legacy and MSI only use one vector */
2334         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2335                 q_vectors = 1;
2336
2337         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2338                 struct napi_struct *napi;
2339                 q_vector = adapter->q_vector[q_idx];
2340                 napi = &q_vector->napi;
2341                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2342                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2343                                 if (q_vector->txr_count == 1)
2344                                         napi->poll = &ixgbe_clean_txonly;
2345                                 else if (q_vector->rxr_count == 1)
2346                                         napi->poll = &ixgbe_clean_rxonly;
2347                         }
2348                 }
2349
2350                 napi_enable(napi);
2351         }
2352 }
2353
2354 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2355 {
2356         int q_idx;
2357         struct ixgbe_q_vector *q_vector;
2358         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2359
2360         /* legacy and MSI only use one vector */
2361         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2362                 q_vectors = 1;
2363
2364         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2365                 q_vector = adapter->q_vector[q_idx];
2366                 napi_disable(&q_vector->napi);
2367         }
2368 }
2369
2370 #ifdef CONFIG_IXGBE_DCB
2371 /*
2372  * ixgbe_configure_dcb - Configure DCB hardware
2373  * @adapter: ixgbe adapter struct
2374  *
2375  * This is called by the driver on open to configure the DCB hardware.
2376  * This is also called by the gennetlink interface when reconfiguring
2377  * the DCB state.
2378  */
2379 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2380 {
2381         struct ixgbe_hw *hw = &adapter->hw;
2382         u32 txdctl, vlnctrl;
2383         int i, j;
2384
2385         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2386         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2387         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2388
2389         /* reconfigure the hardware */
2390         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2391
2392         for (i = 0; i < adapter->num_tx_queues; i++) {
2393                 j = adapter->tx_ring[i].reg_idx;
2394                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2395                 /* PThresh workaround for Tx hang with DFP enabled. */
2396                 txdctl |= 32;
2397                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2398         }
2399         /* Enable VLAN tag insert/strip */
2400         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2401         if (hw->mac.type == ixgbe_mac_82598EB) {
2402                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2403                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2404                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2405         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2406                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2407                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2408                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2409                 for (i = 0; i < adapter->num_rx_queues; i++) {
2410                         j = adapter->rx_ring[i].reg_idx;
2411                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2412                         vlnctrl |= IXGBE_RXDCTL_VME;
2413                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2414                 }
2415         }
2416         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2417 }
2418
2419 #endif
2420 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2421 {
2422         struct net_device *netdev = adapter->netdev;
2423         struct ixgbe_hw *hw = &adapter->hw;
2424         int i;
2425
2426         ixgbe_set_rx_mode(netdev);
2427
2428         ixgbe_restore_vlan(adapter);
2429 #ifdef CONFIG_IXGBE_DCB
2430         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2431                 netif_set_gso_max_size(netdev, 32768);
2432                 ixgbe_configure_dcb(adapter);
2433         } else {
2434                 netif_set_gso_max_size(netdev, 65536);
2435         }
2436 #else
2437         netif_set_gso_max_size(netdev, 65536);
2438 #endif
2439
2440 #ifdef IXGBE_FCOE
2441         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2442                 ixgbe_configure_fcoe(adapter);
2443
2444 #endif /* IXGBE_FCOE */
2445         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2446                 for (i = 0; i < adapter->num_tx_queues; i++)
2447                         adapter->tx_ring[i].atr_sample_rate =
2448                                                        adapter->atr_sample_rate;
2449                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2450         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2451                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2452         }
2453
2454         ixgbe_configure_tx(adapter);
2455         ixgbe_configure_rx(adapter);
2456         for (i = 0; i < adapter->num_rx_queues; i++)
2457                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2458                                        (adapter->rx_ring[i].count - 1));
2459 }
2460
2461 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2462 {
2463         switch (hw->phy.type) {
2464         case ixgbe_phy_sfp_avago:
2465         case ixgbe_phy_sfp_ftl:
2466         case ixgbe_phy_sfp_intel:
2467         case ixgbe_phy_sfp_unknown:
2468         case ixgbe_phy_tw_tyco:
2469         case ixgbe_phy_tw_unknown:
2470                 return true;
2471         default:
2472                 return false;
2473         }
2474 }
2475
2476 /**
2477  * ixgbe_sfp_link_config - set up SFP+ link
2478  * @adapter: pointer to private adapter struct
2479  **/
2480 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2481 {
2482         struct ixgbe_hw *hw = &adapter->hw;
2483
2484                 if (hw->phy.multispeed_fiber) {
2485                         /*
2486                          * In multispeed fiber setups, the device may not have
2487                          * had a physical connection when the driver loaded.
2488                          * If that's the case, the initial link configuration
2489                          * couldn't get the MAC into 10G or 1G mode, so we'll
2490                          * never have a link status change interrupt fire.
2491                          * We need to try and force an autonegotiation
2492                          * session, then bring up link.
2493                          */
2494                         hw->mac.ops.setup_sfp(hw);
2495                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2496                                 schedule_work(&adapter->multispeed_fiber_task);
2497                 } else {
2498                         /*
2499                          * Direct Attach Cu and non-multispeed fiber modules
2500                          * still need to be configured properly prior to
2501                          * attempting link.
2502                          */
2503                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2504                                 schedule_work(&adapter->sfp_config_module_task);
2505                 }
2506 }
2507
2508 /**
2509  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2510  * @hw: pointer to private hardware struct
2511  *
2512  * Returns 0 on success, negative on failure
2513  **/
2514 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2515 {
2516         u32 autoneg;
2517         bool link_up = false;
2518         u32 ret = IXGBE_ERR_LINK_SETUP;
2519
2520         if (hw->mac.ops.check_link)
2521                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2522
2523         if (ret)
2524                 goto link_cfg_out;
2525
2526         if (hw->mac.ops.get_link_capabilities)
2527                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
2528                                                         &hw->mac.autoneg);
2529         if (ret)
2530                 goto link_cfg_out;
2531
2532         if (hw->mac.ops.setup_link_speed)
2533                 ret = hw->mac.ops.setup_link_speed(hw, autoneg, true, link_up);
2534 link_cfg_out:
2535         return ret;
2536 }
2537
2538 #define IXGBE_MAX_RX_DESC_POLL 10
2539 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2540                                               int rxr)
2541 {
2542         int j = adapter->rx_ring[rxr].reg_idx;
2543         int k;
2544
2545         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2546                 if (IXGBE_READ_REG(&adapter->hw,
2547                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2548                         break;
2549                 else
2550                         msleep(1);
2551         }
2552         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2553                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2554                         "not set within the polling period\n", rxr);
2555         }
2556         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2557                               (adapter->rx_ring[rxr].count - 1));
2558 }
2559
2560 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2561 {
2562         struct net_device *netdev = adapter->netdev;
2563         struct ixgbe_hw *hw = &adapter->hw;
2564         int i, j = 0;
2565         int num_rx_rings = adapter->num_rx_queues;
2566         int err;
2567         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2568         u32 txdctl, rxdctl, mhadd;
2569         u32 dmatxctl;
2570         u32 gpie;
2571
2572         ixgbe_get_hw_control(adapter);
2573
2574         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2575             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2576                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2577                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2578                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2579                 } else {
2580                         /* MSI only */
2581                         gpie = 0;
2582                 }
2583                 /* XXX: to interrupt immediately for EICS writes, enable this */
2584                 /* gpie |= IXGBE_GPIE_EIMEN; */
2585                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2586         }
2587
2588         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2589                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2590                  * specifically only auto mask tx and rx interrupts */
2591                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2592         }
2593
2594         /* Enable fan failure interrupt if media type is copper */
2595         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2596                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2597                 gpie |= IXGBE_SDP1_GPIEN;
2598                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2599         }
2600
2601         if (hw->mac.type == ixgbe_mac_82599EB) {
2602                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2603                 gpie |= IXGBE_SDP1_GPIEN;
2604                 gpie |= IXGBE_SDP2_GPIEN;
2605                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2606         }
2607
2608 #ifdef IXGBE_FCOE
2609         /* adjust max frame to be able to do baby jumbo for FCoE */
2610         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2611             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2612                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2613
2614 #endif /* IXGBE_FCOE */
2615         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2616         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2617                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2618                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2619
2620                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2621         }
2622
2623         for (i = 0; i < adapter->num_tx_queues; i++) {
2624                 j = adapter->tx_ring[i].reg_idx;
2625                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2626                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2627                 txdctl |= (8 << 16);
2628                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2629         }
2630
2631         if (hw->mac.type == ixgbe_mac_82599EB) {
2632                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2633                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2634                 dmatxctl |= IXGBE_DMATXCTL_TE;
2635                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2636         }
2637         for (i = 0; i < adapter->num_tx_queues; i++) {
2638                 j = adapter->tx_ring[i].reg_idx;
2639                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2640                 txdctl |= IXGBE_TXDCTL_ENABLE;
2641                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2642         }
2643
2644         for (i = 0; i < num_rx_rings; i++) {
2645                 j = adapter->rx_ring[i].reg_idx;
2646                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2647                 /* enable PTHRESH=32 descriptors (half the internal cache)
2648                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2649                  * this also removes a pesky rx_no_buffer_count increment */
2650                 rxdctl |= 0x0020;
2651                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2652                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2653                 if (hw->mac.type == ixgbe_mac_82599EB)
2654                         ixgbe_rx_desc_queue_enable(adapter, i);
2655         }
2656         /* enable all receives */
2657         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2658         if (hw->mac.type == ixgbe_mac_82598EB)
2659                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2660         else
2661                 rxdctl |= IXGBE_RXCTRL_RXEN;
2662         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2663
2664         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2665                 ixgbe_configure_msix(adapter);
2666         else
2667                 ixgbe_configure_msi_and_legacy(adapter);
2668
2669         clear_bit(__IXGBE_DOWN, &adapter->state);
2670         ixgbe_napi_enable_all(adapter);
2671
2672         /* clear any pending interrupts, may auto mask */
2673         IXGBE_READ_REG(hw, IXGBE_EICR);
2674
2675         ixgbe_irq_enable(adapter);
2676
2677         /*
2678          * If this adapter has a fan, check to see if we had a failure
2679          * before we enabled the interrupt.
2680          */
2681         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2682                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2683                 if (esdp & IXGBE_ESDP_SDP1)
2684                         DPRINTK(DRV, CRIT,
2685                                 "Fan has stopped, replace the adapter\n");
2686         }
2687
2688         /*
2689          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2690          * arrived before interrupts were enabled but after probe.  Such
2691          * devices wouldn't have their type identified yet. We need to
2692          * kick off the SFP+ module setup first, then try to bring up link.
2693          * If we're not hot-pluggable SFP+, we just need to configure link
2694          * and bring it up.
2695          */
2696         if (hw->phy.type == ixgbe_phy_unknown) {
2697                 err = hw->phy.ops.identify(hw);
2698                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2699                         /*
2700                          * Take the device down and schedule the sfp tasklet
2701                          * which will unregister_netdev and log it.
2702                          */
2703                         ixgbe_down(adapter);
2704                         schedule_work(&adapter->sfp_config_module_task);
2705                         return err;
2706                 }
2707         }
2708
2709         if (ixgbe_is_sfp(hw)) {
2710                 ixgbe_sfp_link_config(adapter);
2711         } else {
2712                 err = ixgbe_non_sfp_link_config(hw);
2713                 if (err)
2714                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2715         }
2716
2717         for (i = 0; i < adapter->num_tx_queues; i++)
2718                 set_bit(__IXGBE_FDIR_INIT_DONE,
2719                         &(adapter->tx_ring[i].reinit_state));
2720
2721         /* enable transmits */
2722         netif_tx_start_all_queues(netdev);
2723
2724         /* bring the link up in the watchdog, this could race with our first
2725          * link up interrupt but shouldn't be a problem */
2726         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2727         adapter->link_check_timeout = jiffies;
2728         mod_timer(&adapter->watchdog_timer, jiffies);
2729         return 0;
2730 }
2731
2732 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2733 {
2734         WARN_ON(in_interrupt());
2735         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2736                 msleep(1);
2737         ixgbe_down(adapter);
2738         ixgbe_up(adapter);
2739         clear_bit(__IXGBE_RESETTING, &adapter->state);
2740 }
2741
2742 int ixgbe_up(struct ixgbe_adapter *adapter)
2743 {
2744         /* hardware has been reset, we need to reload some things */
2745         ixgbe_configure(adapter);
2746
2747         return ixgbe_up_complete(adapter);
2748 }
2749
2750 void ixgbe_reset(struct ixgbe_adapter *adapter)
2751 {
2752         struct ixgbe_hw *hw = &adapter->hw;
2753         int err;
2754
2755         err = hw->mac.ops.init_hw(hw);
2756         switch (err) {
2757         case 0:
2758         case IXGBE_ERR_SFP_NOT_PRESENT:
2759                 break;
2760         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2761                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2762                 break;
2763         case IXGBE_ERR_EEPROM_VERSION:
2764                 /* We are running on a pre-production device, log a warning */
2765                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2766                          "adapter/LOM.  Please be aware there may be issues "
2767                          "associated with your hardware.  If you are "
2768                          "experiencing problems please contact your Intel or "
2769                          "hardware representative who provided you with this "
2770                          "hardware.\n");
2771                 break;
2772         default:
2773                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2774         }
2775
2776         /* reprogram the RAR[0] in case user changed it. */
2777         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2778 }
2779
2780 /**
2781  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2782  * @adapter: board private structure
2783  * @rx_ring: ring to free buffers from
2784  **/
2785 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2786                                 struct ixgbe_ring *rx_ring)
2787 {
2788         struct pci_dev *pdev = adapter->pdev;
2789         unsigned long size;
2790         unsigned int i;
2791
2792         /* Free all the Rx ring sk_buffs */
2793
2794         for (i = 0; i < rx_ring->count; i++) {
2795                 struct ixgbe_rx_buffer *rx_buffer_info;
2796
2797                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2798                 if (rx_buffer_info->dma) {
2799                         pci_unmap_single(pdev, rx_buffer_info->dma,
2800                                          rx_ring->rx_buf_len,
2801                                          PCI_DMA_FROMDEVICE);
2802                         rx_buffer_info->dma = 0;
2803                 }
2804                 if (rx_buffer_info->skb) {
2805                         struct sk_buff *skb = rx_buffer_info->skb;
2806                         rx_buffer_info->skb = NULL;
2807                         do {
2808                                 struct sk_buff *this = skb;
2809                                 skb = skb->prev;
2810                                 dev_kfree_skb(this);
2811                         } while (skb);
2812                 }
2813                 if (!rx_buffer_info->page)
2814                         continue;
2815                 if (rx_buffer_info->page_dma) {
2816                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2817                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2818                         rx_buffer_info->page_dma = 0;
2819                 }
2820                 put_page(rx_buffer_info->page);
2821                 rx_buffer_info->page = NULL;
2822                 rx_buffer_info->page_offset = 0;
2823         }
2824
2825         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2826         memset(rx_ring->rx_buffer_info, 0, size);
2827
2828         /* Zero out the descriptor ring */
2829         memset(rx_ring->desc, 0, rx_ring->size);
2830
2831         rx_ring->next_to_clean = 0;
2832         rx_ring->next_to_use = 0;
2833
2834         if (rx_ring->head)
2835                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2836         if (rx_ring->tail)
2837                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2838 }
2839
2840 /**
2841  * ixgbe_clean_tx_ring - Free Tx Buffers
2842  * @adapter: board private structure
2843  * @tx_ring: ring to be cleaned
2844  **/
2845 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2846                                 struct ixgbe_ring *tx_ring)
2847 {
2848         struct ixgbe_tx_buffer *tx_buffer_info;
2849         unsigned long size;
2850         unsigned int i;
2851
2852         /* Free all the Tx ring sk_buffs */
2853
2854         for (i = 0; i < tx_ring->count; i++) {
2855                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2856                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2857         }
2858
2859         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2860         memset(tx_ring->tx_buffer_info, 0, size);
2861
2862         /* Zero out the descriptor ring */
2863         memset(tx_ring->desc, 0, tx_ring->size);
2864
2865         tx_ring->next_to_use = 0;
2866         tx_ring->next_to_clean = 0;
2867
2868         if (tx_ring->head)
2869                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2870         if (tx_ring->tail)
2871                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2872 }
2873
2874 /**
2875  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2876  * @adapter: board private structure
2877  **/
2878 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2879 {
2880         int i;
2881
2882         for (i = 0; i < adapter->num_rx_queues; i++)
2883                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2884 }
2885
2886 /**
2887  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2888  * @adapter: board private structure
2889  **/
2890 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2891 {
2892         int i;
2893
2894         for (i = 0; i < adapter->num_tx_queues; i++)
2895                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2896 }
2897
2898 void ixgbe_down(struct ixgbe_adapter *adapter)
2899 {
2900         struct net_device *netdev = adapter->netdev;
2901         struct ixgbe_hw *hw = &adapter->hw;
2902         u32 rxctrl;
2903         u32 txdctl;
2904         int i, j;
2905
2906         /* signal that we are down to the interrupt handler */
2907         set_bit(__IXGBE_DOWN, &adapter->state);
2908
2909         /* disable receives */
2910         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2911         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2912
2913         netif_tx_disable(netdev);
2914
2915         IXGBE_WRITE_FLUSH(hw);
2916         msleep(10);
2917
2918         netif_tx_stop_all_queues(netdev);
2919
2920         ixgbe_irq_disable(adapter);
2921
2922         ixgbe_napi_disable_all(adapter);
2923
2924         del_timer_sync(&adapter->watchdog_timer);
2925         cancel_work_sync(&adapter->watchdog_task);
2926
2927         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2928             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2929                 cancel_work_sync(&adapter->fdir_reinit_task);
2930
2931         /* disable transmits in the hardware now that interrupts are off */
2932         for (i = 0; i < adapter->num_tx_queues; i++) {
2933                 j = adapter->tx_ring[i].reg_idx;
2934                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2935                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2936                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2937         }
2938         /* Disable the Tx DMA engine on 82599 */
2939         if (hw->mac.type == ixgbe_mac_82599EB)
2940                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2941                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2942                                  ~IXGBE_DMATXCTL_TE));
2943
2944         netif_carrier_off(netdev);
2945
2946         if (!pci_channel_offline(adapter->pdev))
2947                 ixgbe_reset(adapter);
2948         ixgbe_clean_all_tx_rings(adapter);
2949         ixgbe_clean_all_rx_rings(adapter);
2950
2951 #ifdef CONFIG_IXGBE_DCA
2952         /* since we reset the hardware DCA settings were cleared */
2953         ixgbe_setup_dca(adapter);
2954 #endif
2955 }
2956
2957 /**
2958  * ixgbe_poll - NAPI Rx polling callback
2959  * @napi: structure for representing this polling device
2960  * @budget: how many packets driver is allowed to clean
2961  *
2962  * This function is used for legacy and MSI, NAPI mode
2963  **/
2964 static int ixgbe_poll(struct napi_struct *napi, int budget)
2965 {
2966         struct ixgbe_q_vector *q_vector =
2967                                 container_of(napi, struct ixgbe_q_vector, napi);
2968         struct ixgbe_adapter *adapter = q_vector->adapter;
2969         int tx_clean_complete, work_done = 0;
2970
2971 #ifdef CONFIG_IXGBE_DCA
2972         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2973                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2974                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2975         }
2976 #endif
2977
2978         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
2979         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2980
2981         if (!tx_clean_complete)
2982                 work_done = budget;
2983
2984         /* If budget not fully consumed, exit the polling mode */
2985         if (work_done < budget) {
2986                 napi_complete(napi);
2987                 if (adapter->itr_setting & 1)
2988                         ixgbe_set_itr(adapter);
2989                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2990                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2991         }
2992         return work_done;
2993 }
2994
2995 /**
2996  * ixgbe_tx_timeout - Respond to a Tx Hang
2997  * @netdev: network interface device structure
2998  **/
2999 static void ixgbe_tx_timeout(struct net_device *netdev)
3000 {
3001         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3002
3003         /* Do the reset outside of interrupt context */
3004         schedule_work(&adapter->reset_task);
3005 }
3006
3007 static void ixgbe_reset_task(struct work_struct *work)
3008 {
3009         struct ixgbe_adapter *adapter;
3010         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3011
3012         /* If we're already down or resetting, just bail */
3013         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3014             test_bit(__IXGBE_RESETTING, &adapter->state))
3015                 return;
3016
3017         adapter->tx_timeout_count++;
3018
3019         ixgbe_reinit_locked(adapter);
3020 }
3021
3022 #ifdef CONFIG_IXGBE_DCB
3023 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3024 {
3025         bool ret = false;
3026         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3027
3028         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3029                 return ret;
3030
3031         f->mask = 0x7 << 3;
3032         adapter->num_rx_queues = f->indices;
3033         adapter->num_tx_queues = f->indices;
3034         ret = true;
3035
3036         return ret;
3037 }
3038 #endif
3039
3040 /**
3041  * ixgbe_set_rss_queues: Allocate queues for RSS
3042  * @adapter: board private structure to initialize
3043  *
3044  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3045  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3046  *
3047  **/
3048 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3049 {
3050         bool ret = false;
3051         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3052
3053         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3054                 f->mask = 0xF;
3055                 adapter->num_rx_queues = f->indices;
3056                 adapter->num_tx_queues = f->indices;
3057                 ret = true;
3058         } else {
3059                 ret = false;
3060         }
3061
3062         return ret;
3063 }
3064
3065 /**
3066  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3067  * @adapter: board private structure to initialize
3068  *
3069  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3070  * to the original CPU that initiated the Tx session.  This runs in addition
3071  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3072  * Rx load across CPUs using RSS.
3073  *
3074  **/
3075 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3076 {
3077         bool ret = false;
3078         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3079
3080         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3081         f_fdir->mask = 0;
3082
3083         /* Flow Director must have RSS enabled */
3084         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3085             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3086              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3087                 adapter->num_tx_queues = f_fdir->indices;
3088                 adapter->num_rx_queues = f_fdir->indices;
3089                 ret = true;
3090         } else {
3091                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3092                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3093         }
3094         return ret;
3095 }
3096
3097 #ifdef IXGBE_FCOE
3098 /**
3099  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3100  * @adapter: board private structure to initialize
3101  *
3102  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3103  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3104  * rx queues out of the max number of rx queues, instead, it is used as the
3105  * index of the first rx queue used by FCoE.
3106  *
3107  **/
3108 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3109 {
3110         bool ret = false;
3111         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3112
3113         f->indices = min((int)num_online_cpus(), f->indices);
3114         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3115 #ifdef CONFIG_IXGBE_DCB
3116                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3117                         DPRINTK(PROBE, INFO, "FCOE enabled with DCB \n");
3118                         ixgbe_set_dcb_queues(adapter);
3119                 }
3120 #endif
3121                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3122                         DPRINTK(PROBE, INFO, "FCOE enabled with RSS \n");
3123                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3124                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3125                                 ixgbe_set_fdir_queues(adapter);
3126                         else
3127                                 ixgbe_set_rss_queues(adapter);
3128                 }
3129                 /* adding FCoE rx rings to the end */
3130                 f->mask = adapter->num_rx_queues;
3131                 adapter->num_rx_queues += f->indices;
3132                 if (adapter->num_tx_queues == 0)
3133                         adapter->num_tx_queues = f->indices;
3134
3135                 ret = true;
3136         }
3137
3138         return ret;
3139 }
3140
3141 #endif /* IXGBE_FCOE */
3142 /*
3143  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3144  * @adapter: board private structure to initialize
3145  *
3146  * This is the top level queue allocation routine.  The order here is very
3147  * important, starting with the "most" number of features turned on at once,
3148  * and ending with the smallest set of features.  This way large combinations
3149  * can be allocated if they're turned on, and smaller combinations are the
3150  * fallthrough conditions.
3151  *
3152  **/
3153 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3154 {
3155 #ifdef IXGBE_FCOE
3156         if (ixgbe_set_fcoe_queues(adapter))
3157                 goto done;
3158
3159 #endif /* IXGBE_FCOE */
3160 #ifdef CONFIG_IXGBE_DCB
3161         if (ixgbe_set_dcb_queues(adapter))
3162                 goto done;
3163
3164 #endif
3165         if (ixgbe_set_fdir_queues(adapter))
3166                 goto done;
3167
3168         if (ixgbe_set_rss_queues(adapter))
3169                 goto done;
3170
3171         /* fallback to base case */
3172         adapter->num_rx_queues = 1;
3173         adapter->num_tx_queues = 1;
3174
3175 done:
3176         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3177         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3178 }
3179
3180 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3181                                        int vectors)
3182 {
3183         int err, vector_threshold;
3184
3185         /* We'll want at least 3 (vector_threshold):
3186          * 1) TxQ[0] Cleanup
3187          * 2) RxQ[0] Cleanup
3188          * 3) Other (Link Status Change, etc.)
3189          * 4) TCP Timer (optional)
3190          */
3191         vector_threshold = MIN_MSIX_COUNT;
3192
3193         /* The more we get, the more we will assign to Tx/Rx Cleanup
3194          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3195          * Right now, we simply care about how many we'll get; we'll
3196          * set them up later while requesting irq's.
3197          */
3198         while (vectors >= vector_threshold) {
3199                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3200                                       vectors);
3201                 if (!err) /* Success in acquiring all requested vectors. */
3202                         break;
3203                 else if (err < 0)
3204                         vectors = 0; /* Nasty failure, quit now */
3205                 else /* err == number of vectors we should try again with */
3206                         vectors = err;
3207         }
3208
3209         if (vectors < vector_threshold) {
3210                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3211                  * This just means we'll go with either a single MSI
3212                  * vector or fall back to legacy interrupts.
3213                  */
3214                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3215                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3216                 kfree(adapter->msix_entries);
3217                 adapter->msix_entries = NULL;
3218         } else {
3219                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3220                 /*
3221                  * Adjust for only the vectors we'll use, which is minimum
3222                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3223                  * vectors we were allocated.
3224                  */
3225                 adapter->num_msix_vectors = min(vectors,
3226                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3227         }
3228 }
3229
3230 /**
3231  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3232  * @adapter: board private structure to initialize
3233  *
3234  * Cache the descriptor ring offsets for RSS to the assigned rings.
3235  *
3236  **/
3237 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3238 {
3239         int i;
3240         bool ret = false;
3241
3242         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3243                 for (i = 0; i < adapter->num_rx_queues; i++)
3244                         adapter->rx_ring[i].reg_idx = i;
3245                 for (i = 0; i < adapter->num_tx_queues; i++)
3246                         adapter->tx_ring[i].reg_idx = i;
3247                 ret = true;
3248         } else {
3249                 ret = false;
3250         }
3251
3252         return ret;
3253 }
3254
3255 #ifdef CONFIG_IXGBE_DCB
3256 /**
3257  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3258  * @adapter: board private structure to initialize
3259  *
3260  * Cache the descriptor ring offsets for DCB to the assigned rings.
3261  *
3262  **/
3263 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3264 {
3265         int i;
3266         bool ret = false;
3267         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3268
3269         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3270                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3271                         /* the number of queues is assumed to be symmetric */
3272                         for (i = 0; i < dcb_i; i++) {
3273                                 adapter->rx_ring[i].reg_idx = i << 3;
3274                                 adapter->tx_ring[i].reg_idx = i << 2;
3275                         }
3276                         ret = true;
3277                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3278                         if (dcb_i == 8) {
3279                                 /*
3280                                  * Tx TC0 starts at: descriptor queue 0
3281                                  * Tx TC1 starts at: descriptor queue 32
3282                                  * Tx TC2 starts at: descriptor queue 64
3283                                  * Tx TC3 starts at: descriptor queue 80
3284                                  * Tx TC4 starts at: descriptor queue 96
3285                                  * Tx TC5 starts at: descriptor queue 104
3286                                  * Tx TC6 starts at: descriptor queue 112
3287                                  * Tx TC7 starts at: descriptor queue 120
3288                                  *
3289                                  * Rx TC0-TC7 are offset by 16 queues each
3290                                  */
3291                                 for (i = 0; i < 3; i++) {
3292                                         adapter->tx_ring[i].reg_idx = i << 5;
3293                                         adapter->rx_ring[i].reg_idx = i << 4;
3294                                 }
3295                                 for ( ; i < 5; i++) {
3296                                         adapter->tx_ring[i].reg_idx =
3297                                                                  ((i + 2) << 4);
3298                                         adapter->rx_ring[i].reg_idx = i << 4;
3299                                 }
3300                                 for ( ; i < dcb_i; i++) {
3301                                         adapter->tx_ring[i].reg_idx =
3302                                                                  ((i + 8) << 3);
3303                                         adapter->rx_ring[i].reg_idx = i << 4;
3304                                 }
3305
3306                                 ret = true;
3307                         } else if (dcb_i == 4) {
3308                                 /*
3309                                  * Tx TC0 starts at: descriptor queue 0
3310                                  * Tx TC1 starts at: descriptor queue 64
3311                                  * Tx TC2 starts at: descriptor queue 96
3312                                  * Tx TC3 starts at: descriptor queue 112
3313                                  *
3314                                  * Rx TC0-TC3 are offset by 32 queues each
3315                                  */
3316                                 adapter->tx_ring[0].reg_idx = 0;
3317                                 adapter->tx_ring[1].reg_idx = 64;
3318                                 adapter->tx_ring[2].reg_idx = 96;
3319                                 adapter->tx_ring[3].reg_idx = 112;
3320                                 for (i = 0 ; i < dcb_i; i++)
3321                                         adapter->rx_ring[i].reg_idx = i << 5;
3322
3323                                 ret = true;
3324                         } else {
3325                                 ret = false;
3326                         }
3327                 } else {
3328                         ret = false;
3329                 }
3330         } else {
3331                 ret = false;
3332         }
3333
3334         return ret;
3335 }
3336 #endif
3337
3338 /**
3339  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3340  * @adapter: board private structure to initialize
3341  *
3342  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3343  *
3344  **/
3345 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3346 {
3347         int i;
3348         bool ret = false;
3349
3350         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3351             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3352              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3353                 for (i = 0; i < adapter->num_rx_queues; i++)
3354                         adapter->rx_ring[i].reg_idx = i;
3355                 for (i = 0; i < adapter->num_tx_queues; i++)
3356                         adapter->tx_ring[i].reg_idx = i;
3357                 ret = true;
3358         }
3359
3360         return ret;
3361 }
3362
3363 #ifdef IXGBE_FCOE
3364 /**
3365  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3366  * @adapter: board private structure to initialize
3367  *
3368  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3369  *
3370  */
3371 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3372 {
3373         int i, fcoe_i = 0;
3374         bool ret = false;
3375         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3376
3377         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3378 #ifdef CONFIG_IXGBE_DCB
3379                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3380                         ixgbe_cache_ring_dcb(adapter);
3381                         fcoe_i = adapter->rx_ring[0].reg_idx + 1;
3382                 }
3383 #endif /* CONFIG_IXGBE_DCB */
3384                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3385                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3386                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3387                                 ixgbe_cache_ring_fdir(adapter);
3388                         else
3389                                 ixgbe_cache_ring_rss(adapter);
3390
3391                         fcoe_i = f->mask;
3392                 }
3393                 for (i = 0; i < f->indices; i++, fcoe_i++)
3394                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_i;
3395                 ret = true;
3396         }
3397         return ret;
3398 }
3399
3400 #endif /* IXGBE_FCOE */
3401 /**
3402  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3403  * @adapter: board private structure to initialize
3404  *
3405  * Once we know the feature-set enabled for the device, we'll cache
3406  * the register offset the descriptor ring is assigned to.
3407  *
3408  * Note, the order the various feature calls is important.  It must start with
3409  * the "most" features enabled at the same time, then trickle down to the
3410  * least amount of features turned on at once.
3411  **/
3412 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3413 {
3414         /* start with default case */
3415         adapter->rx_ring[0].reg_idx = 0;
3416         adapter->tx_ring[0].reg_idx = 0;
3417
3418 #ifdef IXGBE_FCOE
3419         if (ixgbe_cache_ring_fcoe(adapter))
3420                 return;
3421
3422 #endif /* IXGBE_FCOE */
3423 #ifdef CONFIG_IXGBE_DCB
3424         if (ixgbe_cache_ring_dcb(adapter))
3425                 return;
3426
3427 #endif
3428         if (ixgbe_cache_ring_fdir(adapter))
3429                 return;
3430
3431         if (ixgbe_cache_ring_rss(adapter))
3432                 return;
3433 }
3434
3435 /**
3436  * ixgbe_alloc_queues - Allocate memory for all rings
3437  * @adapter: board private structure to initialize
3438  *
3439  * We allocate one ring per queue at run-time since we don't know the
3440  * number of queues at compile-time.  The polling_netdev array is
3441  * intended for Multiqueue, but should work fine with a single queue.
3442  **/
3443 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3444 {
3445         int i;
3446
3447         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3448                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3449         if (!adapter->tx_ring)
3450                 goto err_tx_ring_allocation;
3451
3452         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3453                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3454         if (!adapter->rx_ring)
3455                 goto err_rx_ring_allocation;
3456
3457         for (i = 0; i < adapter->num_tx_queues; i++) {
3458                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3459                 adapter->tx_ring[i].queue_index = i;
3460         }
3461
3462         for (i = 0; i < adapter->num_rx_queues; i++) {
3463                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3464                 adapter->rx_ring[i].queue_index = i;
3465         }
3466
3467         ixgbe_cache_ring_register(adapter);
3468
3469         return 0;
3470
3471 err_rx_ring_allocation:
3472         kfree(adapter->tx_ring);
3473 err_tx_ring_allocation:
3474         return -ENOMEM;
3475 }
3476
3477 /**
3478  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3479  * @adapter: board private structure to initialize
3480  *
3481  * Attempt to configure the interrupts using the best available
3482  * capabilities of the hardware and the kernel.
3483  **/
3484 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3485 {
3486         struct ixgbe_hw *hw = &adapter->hw;
3487         int err = 0;
3488         int vector, v_budget;
3489
3490         /*
3491          * It's easy to be greedy for MSI-X vectors, but it really
3492          * doesn't do us much good if we have a lot more vectors
3493          * than CPU's.  So let's be conservative and only ask for
3494          * (roughly) twice the number of vectors as there are CPU's.
3495          */
3496         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3497                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3498
3499         /*
3500          * At the same time, hardware can only support a maximum of
3501          * hw.mac->max_msix_vectors vectors.  With features
3502          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3503          * descriptor queues supported by our device.  Thus, we cap it off in
3504          * those rare cases where the cpu count also exceeds our vector limit.
3505          */
3506         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3507
3508         /* A failure in MSI-X entry allocation isn't fatal, but it does
3509          * mean we disable MSI-X capabilities of the adapter. */
3510         adapter->msix_entries = kcalloc(v_budget,
3511                                         sizeof(struct msix_entry), GFP_KERNEL);
3512         if (adapter->msix_entries) {
3513                 for (vector = 0; vector < v_budget; vector++)
3514                         adapter->msix_entries[vector].entry = vector;
3515
3516                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3517
3518                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3519                         goto out;
3520         }
3521
3522         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3523         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3524         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3525         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3526         adapter->atr_sample_rate = 0;
3527         ixgbe_set_num_queues(adapter);
3528
3529         err = pci_enable_msi(adapter->pdev);
3530         if (!err) {
3531                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3532         } else {
3533                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3534                         "falling back to legacy.  Error: %d\n", err);
3535                 /* reset err */
3536                 err = 0;
3537         }
3538
3539 out:
3540         return err;
3541 }
3542
3543 /**
3544  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3545  * @adapter: board private structure to initialize
3546  *
3547  * We allocate one q_vector per queue interrupt.  If allocation fails we
3548  * return -ENOMEM.
3549  **/
3550 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3551 {
3552         int q_idx, num_q_vectors;
3553         struct ixgbe_q_vector *q_vector;
3554         int napi_vectors;
3555         int (*poll)(struct napi_struct *, int);
3556
3557         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3558                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3559                 napi_vectors = adapter->num_rx_queues;
3560                 poll = &ixgbe_clean_rxtx_many;
3561         } else {
3562                 num_q_vectors = 1;
3563                 napi_vectors = 1;
3564                 poll = &ixgbe_poll;
3565         }
3566
3567         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3568                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3569                 if (!q_vector)
3570                         goto err_out;
3571                 q_vector->adapter = adapter;
3572                 q_vector->eitr = adapter->eitr_param;
3573                 q_vector->v_idx = q_idx;
3574                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3575                 adapter->q_vector[q_idx] = q_vector;
3576         }
3577
3578         return 0;
3579
3580 err_out:
3581         while (q_idx) {
3582                 q_idx--;
3583                 q_vector = adapter->q_vector[q_idx];
3584                 netif_napi_del(&q_vector->napi);
3585                 kfree(q_vector);
3586                 adapter->q_vector[q_idx] = NULL;
3587         }
3588         return -ENOMEM;
3589 }
3590
3591 /**
3592  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3593  * @adapter: board private structure to initialize
3594  *
3595  * This function frees the memory allocated to the q_vectors.  In addition if
3596  * NAPI is enabled it will delete any references to the NAPI struct prior
3597  * to freeing the q_vector.
3598  **/
3599 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3600 {
3601         int q_idx, num_q_vectors;
3602
3603         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3604                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3605         else
3606                 num_q_vectors = 1;
3607
3608         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3609                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3610                 adapter->q_vector[q_idx] = NULL;
3611                 netif_napi_del(&q_vector->napi);
3612                 kfree(q_vector);
3613         }
3614 }
3615
3616 void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3617 {
3618         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3619                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3620                 pci_disable_msix(adapter->pdev);
3621                 kfree(adapter->msix_entries);
3622                 adapter->msix_entries = NULL;
3623         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3624                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3625                 pci_disable_msi(adapter->pdev);
3626         }
3627         return;
3628 }
3629
3630 /**
3631  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3632  * @adapter: board private structure to initialize
3633  *
3634  * We determine which interrupt scheme to use based on...
3635  * - Kernel support (MSI, MSI-X)
3636  *   - which can be user-defined (via MODULE_PARAM)
3637  * - Hardware queue count (num_*_queues)
3638  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3639  **/
3640 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3641 {
3642         int err;
3643
3644         /* Number of supported queues */
3645         ixgbe_set_num_queues(adapter);
3646
3647         err = ixgbe_set_interrupt_capability(adapter);
3648         if (err) {
3649                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3650                 goto err_set_interrupt;
3651         }
3652
3653         err = ixgbe_alloc_q_vectors(adapter);
3654         if (err) {
3655                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3656                         "vectors\n");
3657                 goto err_alloc_q_vectors;
3658         }
3659
3660         err = ixgbe_alloc_queues(adapter);
3661         if (err) {
3662                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3663                 goto err_alloc_queues;
3664         }
3665
3666         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3667                 "Tx Queue count = %u\n",
3668                 (adapter->num_rx_queues > 1) ? "Enabled" :
3669                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3670
3671         set_bit(__IXGBE_DOWN, &adapter->state);
3672
3673         return 0;
3674
3675 err_alloc_queues:
3676         ixgbe_free_q_vectors(adapter);
3677 err_alloc_q_vectors:
3678         ixgbe_reset_interrupt_capability(adapter);
3679 err_set_interrupt:
3680         return err;
3681 }
3682
3683 /**
3684  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3685  * @adapter: board private structure to clear interrupt scheme on
3686  *
3687  * We go through and clear interrupt specific resources and reset the structure
3688  * to pre-load conditions
3689  **/
3690 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3691 {
3692         kfree(adapter->tx_ring);
3693         kfree(adapter->rx_ring);
3694         adapter->tx_ring = NULL;
3695         adapter->rx_ring = NULL;
3696
3697         ixgbe_free_q_vectors(adapter);
3698         ixgbe_reset_interrupt_capability(adapter);
3699 }
3700
3701 /**
3702  * ixgbe_sfp_timer - worker thread to find a missing module
3703  * @data: pointer to our adapter struct
3704  **/
3705 static void ixgbe_sfp_timer(unsigned long data)
3706 {
3707         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3708
3709         /*
3710          * Do the sfp_timer outside of interrupt context due to the
3711          * delays that sfp+ detection requires
3712          */
3713         schedule_work(&adapter->sfp_task);
3714 }
3715
3716 /**
3717  * ixgbe_sfp_task - worker thread to find a missing module
3718  * @work: pointer to work_struct containing our data
3719  **/
3720 static void ixgbe_sfp_task(struct work_struct *work)
3721 {
3722         struct ixgbe_adapter *adapter = container_of(work,
3723                                                      struct ixgbe_adapter,
3724                                                      sfp_task);
3725         struct ixgbe_hw *hw = &adapter->hw;
3726
3727         if ((hw->phy.type == ixgbe_phy_nl) &&
3728             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3729                 s32 ret = hw->phy.ops.identify_sfp(hw);
3730                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3731                         goto reschedule;
3732                 ret = hw->phy.ops.reset(hw);
3733                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3734                         dev_err(&adapter->pdev->dev, "failed to initialize "
3735                                 "because an unsupported SFP+ module type "
3736                                 "was detected.\n"
3737                                 "Reload the driver after installing a "
3738                                 "supported module.\n");
3739                         unregister_netdev(adapter->netdev);
3740                 } else {
3741                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3742                                 hw->phy.sfp_type);
3743                 }
3744                 /* don't need this routine any more */
3745                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3746         }
3747         return;
3748 reschedule:
3749         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3750                 mod_timer(&adapter->sfp_timer,
3751                           round_jiffies(jiffies + (2 * HZ)));
3752 }
3753
3754 /**
3755  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3756  * @adapter: board private structure to initialize
3757  *
3758  * ixgbe_sw_init initializes the Adapter private data structure.
3759  * Fields are initialized based on PCI device information and
3760  * OS network device settings (MTU size).
3761  **/
3762 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3763 {
3764         struct ixgbe_hw *hw = &adapter->hw;
3765         struct pci_dev *pdev = adapter->pdev;
3766         unsigned int rss;
3767 #ifdef CONFIG_IXGBE_DCB
3768         int j;
3769         struct tc_configuration *tc;
3770 #endif
3771
3772         /* PCI config space info */
3773
3774         hw->vendor_id = pdev->vendor;
3775         hw->device_id = pdev->device;
3776         hw->revision_id = pdev->revision;
3777         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3778         hw->subsystem_device_id = pdev->subsystem_device;
3779
3780         /* Set capability flags */
3781         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3782         adapter->ring_feature[RING_F_RSS].indices = rss;
3783         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3784         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3785         if (hw->mac.type == ixgbe_mac_82598EB) {
3786                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3787                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3788                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3789         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3790                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3791                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3792                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3793                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3794                 adapter->ring_feature[RING_F_FDIR].indices =
3795                                                          IXGBE_MAX_FDIR_INDICES;
3796                 adapter->atr_sample_rate = 20;
3797                 adapter->fdir_pballoc = 0;
3798 #ifdef IXGBE_FCOE
3799                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3800                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3801                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3802 #endif /* IXGBE_FCOE */
3803         }
3804
3805 #ifdef CONFIG_IXGBE_DCB
3806         /* Configure DCB traffic classes */
3807         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3808                 tc = &adapter->dcb_cfg.tc_config[j];
3809                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3810                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3811                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3812                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3813                 tc->dcb_pfc = pfc_disabled;
3814         }
3815         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3816         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3817         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3818         adapter->dcb_cfg.pfc_mode_enable = false;
3819         adapter->dcb_cfg.round_robin_enable = false;
3820         adapter->dcb_set_bitmap = 0x00;
3821         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3822                            adapter->ring_feature[RING_F_DCB].indices);
3823
3824 #endif
3825
3826         /* default flow control settings */
3827         hw->fc.requested_mode = ixgbe_fc_full;
3828         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3829 #ifdef CONFIG_DCB
3830         adapter->last_lfc_mode = hw->fc.current_mode;
3831 #endif
3832         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3833         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3834         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3835         hw->fc.send_xon = true;
3836         hw->fc.disable_fc_autoneg = false;
3837
3838         /* enable itr by default in dynamic mode */
3839         adapter->itr_setting = 1;
3840         adapter->eitr_param = 20000;
3841
3842         /* set defaults for eitr in MegaBytes */
3843         adapter->eitr_low = 10;
3844         adapter->eitr_high = 20;
3845
3846         /* set default ring sizes */
3847         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3848         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3849
3850         /* initialize eeprom parameters */
3851         if (ixgbe_init_eeprom_params_generic(hw)) {
3852                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3853                 return -EIO;
3854         }
3855
3856         /* enable rx csum by default */
3857         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3858
3859         set_bit(__IXGBE_DOWN, &adapter->state);
3860
3861         return 0;
3862 }
3863
3864 /**
3865  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3866  * @adapter: board private structure
3867  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3868  *
3869  * Return 0 on success, negative on failure
3870  **/
3871 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3872                              struct ixgbe_ring *tx_ring)
3873 {
3874         struct pci_dev *pdev = adapter->pdev;
3875         int size;
3876
3877         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3878         tx_ring->tx_buffer_info = vmalloc(size);
3879         if (!tx_ring->tx_buffer_info)
3880                 goto err;
3881         memset(tx_ring->tx_buffer_info, 0, size);
3882
3883         /* round up to nearest 4K */
3884         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3885         tx_ring->size = ALIGN(tx_ring->size, 4096);
3886
3887         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3888                                              &tx_ring->dma);
3889         if (!tx_ring->desc)
3890                 goto err;
3891
3892         tx_ring->next_to_use = 0;
3893         tx_ring->next_to_clean = 0;
3894         tx_ring->work_limit = tx_ring->count;
3895         return 0;
3896
3897 err:
3898         vfree(tx_ring->tx_buffer_info);
3899         tx_ring->tx_buffer_info = NULL;
3900         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3901                             "descriptor ring\n");
3902         return -ENOMEM;
3903 }
3904
3905 /**
3906  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3907  * @adapter: board private structure
3908  *
3909  * If this function returns with an error, then it's possible one or
3910  * more of the rings is populated (while the rest are not).  It is the
3911  * callers duty to clean those orphaned rings.
3912  *
3913  * Return 0 on success, negative on failure
3914  **/
3915 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3916 {
3917         int i, err = 0;
3918
3919         for (i = 0; i < adapter->num_tx_queues; i++) {
3920                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3921                 if (!err)
3922                         continue;
3923                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3924                 break;
3925         }
3926
3927         return err;
3928 }
3929
3930 /**
3931  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3932  * @adapter: board private structure
3933  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3934  *
3935  * Returns 0 on success, negative on failure
3936  **/
3937 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3938                              struct ixgbe_ring *rx_ring)
3939 {
3940         struct pci_dev *pdev = adapter->pdev;
3941         int size;
3942
3943         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3944         rx_ring->rx_buffer_info = vmalloc(size);
3945         if (!rx_ring->rx_buffer_info) {
3946                 DPRINTK(PROBE, ERR,
3947                         "vmalloc allocation failed for the rx desc ring\n");
3948                 goto alloc_failed;
3949         }
3950         memset(rx_ring->rx_buffer_info, 0, size);
3951
3952         /* Round up to nearest 4K */
3953         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3954         rx_ring->size = ALIGN(rx_ring->size, 4096);
3955
3956         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3957
3958         if (!rx_ring->desc) {
3959                 DPRINTK(PROBE, ERR,
3960                         "Memory allocation failed for the rx desc ring\n");
3961                 vfree(rx_ring->rx_buffer_info);
3962                 goto alloc_failed;
3963         }
3964
3965         rx_ring->next_to_clean = 0;
3966         rx_ring->next_to_use = 0;
3967
3968         return 0;
3969
3970 alloc_failed:
3971         return -ENOMEM;
3972 }
3973
3974 /**
3975  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
3976  * @adapter: board private structure
3977  *
3978  * If this function returns with an error, then it's possible one or
3979  * more of the rings is populated (while the rest are not).  It is the
3980  * callers duty to clean those orphaned rings.
3981  *
3982  * Return 0 on success, negative on failure
3983  **/
3984
3985 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
3986 {
3987         int i, err = 0;
3988
3989         for (i = 0; i < adapter->num_rx_queues; i++) {
3990                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
3991                 if (!err)
3992                         continue;
3993                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
3994                 break;
3995         }
3996
3997         return err;
3998 }
3999
4000 /**
4001  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4002  * @adapter: board private structure
4003  * @tx_ring: Tx descriptor ring for a specific queue
4004  *
4005  * Free all transmit software resources
4006  **/
4007 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4008                              struct ixgbe_ring *tx_ring)
4009 {
4010         struct pci_dev *pdev = adapter->pdev;
4011
4012         ixgbe_clean_tx_ring(adapter, tx_ring);
4013
4014         vfree(tx_ring->tx_buffer_info);
4015         tx_ring->tx_buffer_info = NULL;
4016
4017         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4018
4019         tx_ring->desc = NULL;
4020 }
4021
4022 /**
4023  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4024  * @adapter: board private structure
4025  *
4026  * Free all transmit software resources
4027  **/
4028 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4029 {
4030         int i;
4031
4032         for (i = 0; i < adapter->num_tx_queues; i++)
4033                 if (adapter->tx_ring[i].desc)
4034                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4035 }
4036
4037 /**
4038  * ixgbe_free_rx_resources - Free Rx Resources
4039  * @adapter: board private structure
4040  * @rx_ring: ring to clean the resources from
4041  *
4042  * Free all receive software resources
4043  **/
4044 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4045                              struct ixgbe_ring *rx_ring)
4046 {
4047         struct pci_dev *pdev = adapter->pdev;
4048
4049         ixgbe_clean_rx_ring(adapter, rx_ring);
4050
4051         vfree(rx_ring->rx_buffer_info);
4052         rx_ring->rx_buffer_info = NULL;
4053
4054         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4055
4056         rx_ring->desc = NULL;
4057 }
4058
4059 /**
4060  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4061  * @adapter: board private structure
4062  *
4063  * Free all receive software resources
4064  **/
4065 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4066 {
4067         int i;
4068
4069         for (i = 0; i < adapter->num_rx_queues; i++)
4070                 if (adapter->rx_ring[i].desc)
4071                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4072 }
4073
4074 /**
4075  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4076  * @netdev: network interface device structure
4077  * @new_mtu: new value for maximum frame size
4078  *
4079  * Returns 0 on success, negative on failure
4080  **/
4081 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4082 {
4083         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4084         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4085
4086         /* MTU < 68 is an error and causes problems on some kernels */
4087         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4088                 return -EINVAL;
4089
4090         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4091                 netdev->mtu, new_mtu);
4092         /* must set new MTU before calling down or up */
4093         netdev->mtu = new_mtu;
4094
4095         if (netif_running(netdev))
4096                 ixgbe_reinit_locked(adapter);
4097
4098         return 0;
4099 }
4100
4101 /**
4102  * ixgbe_open - Called when a network interface is made active
4103  * @netdev: network interface device structure
4104  *
4105  * Returns 0 on success, negative value on failure
4106  *
4107  * The open entry point is called when a network interface is made
4108  * active by the system (IFF_UP).  At this point all resources needed
4109  * for transmit and receive operations are allocated, the interrupt
4110  * handler is registered with the OS, the watchdog timer is started,
4111  * and the stack is notified that the interface is ready.
4112  **/
4113 static int ixgbe_open(struct net_device *netdev)
4114 {
4115         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4116         int err;
4117
4118         /* disallow open during test */
4119         if (test_bit(__IXGBE_TESTING, &adapter->state))
4120                 return -EBUSY;
4121
4122         netif_carrier_off(netdev);
4123
4124         /* allocate transmit descriptors */
4125         err = ixgbe_setup_all_tx_resources(adapter);
4126         if (err)
4127                 goto err_setup_tx;
4128
4129         /* allocate receive descriptors */
4130         err = ixgbe_setup_all_rx_resources(adapter);
4131         if (err)
4132                 goto err_setup_rx;
4133
4134         ixgbe_configure(adapter);
4135
4136         err = ixgbe_request_irq(adapter);
4137         if (err)
4138                 goto err_req_irq;
4139
4140         err = ixgbe_up_complete(adapter);
4141         if (err)
4142                 goto err_up;
4143
4144         netif_tx_start_all_queues(netdev);
4145
4146         return 0;
4147
4148 err_up:
4149         ixgbe_release_hw_control(adapter);
4150         ixgbe_free_irq(adapter);
4151 err_req_irq:
4152 err_setup_rx:
4153         ixgbe_free_all_rx_resources(adapter);
4154 err_setup_tx:
4155         ixgbe_free_all_tx_resources(adapter);
4156         ixgbe_reset(adapter);
4157
4158         return err;
4159 }
4160
4161 /**
4162  * ixgbe_close - Disables a network interface
4163  * @netdev: network interface device structure
4164  *
4165  * Returns 0, this is not allowed to fail
4166  *
4167  * The close entry point is called when an interface is de-activated
4168  * by the OS.  The hardware is still under the drivers control, but
4169  * needs to be disabled.  A global MAC reset is issued to stop the
4170  * hardware, and all transmit and receive resources are freed.
4171  **/
4172 static int ixgbe_close(struct net_device *netdev)
4173 {
4174         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4175
4176         ixgbe_down(adapter);
4177         ixgbe_free_irq(adapter);
4178
4179         ixgbe_free_all_tx_resources(adapter);
4180         ixgbe_free_all_rx_resources(adapter);
4181
4182         ixgbe_release_hw_control(adapter);
4183
4184         return 0;
4185 }
4186
4187 #ifdef CONFIG_PM
4188 static int ixgbe_resume(struct pci_dev *pdev)
4189 {
4190         struct net_device *netdev = pci_get_drvdata(pdev);
4191         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4192         u32 err;
4193
4194         pci_set_power_state(pdev, PCI_D0);
4195         pci_restore_state(pdev);
4196
4197         err = pci_enable_device_mem(pdev);
4198         if (err) {
4199                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4200                                 "suspend\n");
4201                 return err;
4202         }
4203         pci_set_master(pdev);
4204
4205         pci_wake_from_d3(pdev, false);
4206
4207         err = ixgbe_init_interrupt_scheme(adapter);
4208         if (err) {
4209                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4210                                 "device\n");
4211                 return err;
4212         }
4213
4214         ixgbe_reset(adapter);
4215
4216         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4217
4218         if (netif_running(netdev)) {
4219                 err = ixgbe_open(adapter->netdev);
4220                 if (err)
4221                         return err;
4222         }
4223
4224         netif_device_attach(netdev);
4225
4226         return 0;
4227 }
4228 #endif /* CONFIG_PM */
4229
4230 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4231 {
4232         struct net_device *netdev = pci_get_drvdata(pdev);
4233         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4234         struct ixgbe_hw *hw = &adapter->hw;
4235         u32 ctrl, fctrl;
4236         u32 wufc = adapter->wol;
4237 #ifdef CONFIG_PM
4238         int retval = 0;
4239 #endif
4240
4241         netif_device_detach(netdev);
4242
4243         if (netif_running(netdev)) {
4244                 ixgbe_down(adapter);
4245                 ixgbe_free_irq(adapter);
4246                 ixgbe_free_all_tx_resources(adapter);
4247                 ixgbe_free_all_rx_resources(adapter);
4248         }
4249         ixgbe_clear_interrupt_scheme(adapter);
4250
4251 #ifdef CONFIG_PM
4252         retval = pci_save_state(pdev);
4253         if (retval)
4254                 return retval;
4255
4256 #endif
4257         if (wufc) {
4258                 ixgbe_set_rx_mode(netdev);
4259
4260                 /* turn on all-multi mode if wake on multicast is enabled */
4261                 if (wufc & IXGBE_WUFC_MC) {
4262                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4263                         fctrl |= IXGBE_FCTRL_MPE;
4264                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4265                 }
4266
4267                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4268                 ctrl |= IXGBE_CTRL_GIO_DIS;
4269                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4270
4271                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4272         } else {
4273                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4274                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4275         }
4276
4277         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4278                 pci_wake_from_d3(pdev, true);
4279         else
4280                 pci_wake_from_d3(pdev, false);
4281
4282         *enable_wake = !!wufc;
4283
4284         ixgbe_release_hw_control(adapter);
4285
4286         pci_disable_device(pdev);
4287
4288         return 0;
4289 }
4290
4291 #ifdef CONFIG_PM
4292 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4293 {
4294         int retval;
4295         bool wake;
4296
4297         retval = __ixgbe_shutdown(pdev, &wake);
4298         if (retval)
4299                 return retval;
4300
4301         if (wake) {
4302                 pci_prepare_to_sleep(pdev);
4303         } else {
4304                 pci_wake_from_d3(pdev, false);
4305                 pci_set_power_state(pdev, PCI_D3hot);
4306         }
4307
4308         return 0;
4309 }
4310 #endif /* CONFIG_PM */
4311
4312 static void ixgbe_shutdown(struct pci_dev *pdev)
4313 {
4314         bool wake;
4315
4316         __ixgbe_shutdown(pdev, &wake);
4317
4318         if (system_state == SYSTEM_POWER_OFF) {
4319                 pci_wake_from_d3(pdev, wake);
4320                 pci_set_power_state(pdev, PCI_D3hot);
4321         }
4322 }
4323
4324 /**
4325  * ixgbe_update_stats - Update the board statistics counters.
4326  * @adapter: board private structure
4327  **/
4328 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4329 {
4330         struct ixgbe_hw *hw = &adapter->hw;
4331         u64 total_mpc = 0;
4332         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4333
4334         if (hw->mac.type == ixgbe_mac_82599EB) {
4335                 u64 rsc_count = 0;
4336                 for (i = 0; i < 16; i++)
4337                         adapter->hw_rx_no_dma_resources +=
4338                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4339                 for (i = 0; i < adapter->num_rx_queues; i++)
4340                         rsc_count += adapter->rx_ring[i].rsc_count;
4341                 adapter->rsc_count = rsc_count;
4342         }
4343
4344         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4345         for (i = 0; i < 8; i++) {
4346                 /* for packet buffers not used, the register should read 0 */
4347                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4348                 missed_rx += mpc;
4349                 adapter->stats.mpc[i] += mpc;
4350                 total_mpc += adapter->stats.mpc[i];
4351                 if (hw->mac.type == ixgbe_mac_82598EB)
4352                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4353                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4354                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4355                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4356                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4357                 if (hw->mac.type == ixgbe_mac_82599EB) {
4358                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4359                                                             IXGBE_PXONRXCNT(i));
4360                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4361                                                            IXGBE_PXOFFRXCNT(i));
4362                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4363                 } else {
4364                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4365                                                               IXGBE_PXONRXC(i));
4366                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4367                                                              IXGBE_PXOFFRXC(i));
4368                 }
4369                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4370                                                             IXGBE_PXONTXC(i));
4371                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4372                                                              IXGBE_PXOFFTXC(i));
4373         }
4374         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4375         /* work around hardware counting issue */
4376         adapter->stats.gprc -= missed_rx;
4377
4378         /* 82598 hardware only has a 32 bit counter in the high register */
4379         if (hw->mac.type == ixgbe_mac_82599EB) {
4380                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4381                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4382                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4383                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4384                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4385                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4386                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4387                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4388                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4389                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4390 #ifdef IXGBE_FCOE
4391                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4392                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4393                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4394                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4395                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4396                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4397 #endif /* IXGBE_FCOE */
4398         } else {
4399                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4400                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4401                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4402                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4403                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4404         }
4405         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4406         adapter->stats.bprc += bprc;
4407         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4408         if (hw->mac.type == ixgbe_mac_82598EB)
4409                 adapter->stats.mprc -= bprc;
4410         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4411         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4412         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4413         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4414         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4415         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4416         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4417         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4418         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4419         adapter->stats.lxontxc += lxon;
4420         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4421         adapter->stats.lxofftxc += lxoff;
4422         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4423         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4424         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4425         /*
4426          * 82598 errata - tx of flow control packets is included in tx counters
4427          */
4428         xon_off_tot = lxon + lxoff;
4429         adapter->stats.gptc -= xon_off_tot;
4430         adapter->stats.mptc -= xon_off_tot;
4431         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4432         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4433         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4434         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4435         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4436         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4437         adapter->stats.ptc64 -= xon_off_tot;
4438         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4439         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4440         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4441         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4442         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4443         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4444
4445         /* Fill out the OS statistics structure */
4446         adapter->net_stats.multicast = adapter->stats.mprc;
4447
4448         /* Rx Errors */
4449         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4450                                        adapter->stats.rlec;
4451         adapter->net_stats.rx_dropped = 0;
4452         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4453         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4454         adapter->net_stats.rx_missed_errors = total_mpc;
4455 }
4456
4457 /**
4458  * ixgbe_watchdog - Timer Call-back
4459  * @data: pointer to adapter cast into an unsigned long
4460  **/
4461 static void ixgbe_watchdog(unsigned long data)
4462 {
4463         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4464         struct ixgbe_hw *hw = &adapter->hw;
4465         u64 eics = 0;
4466         int i;
4467
4468         /*
4469          *  Do the watchdog outside of interrupt context due to the lovely
4470          * delays that some of the newer hardware requires
4471          */
4472
4473         if (test_bit(__IXGBE_DOWN, &adapter->state))
4474                 goto watchdog_short_circuit;
4475
4476         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4477                 /*
4478                  * for legacy and MSI interrupts don't set any bits
4479                  * that are enabled for EIAM, because this operation
4480                  * would set *both* EIMS and EICS for any bit in EIAM
4481                  */
4482                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4483                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4484                 goto watchdog_reschedule;
4485         }
4486
4487         /* get one bit for every active tx/rx interrupt vector */
4488         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4489                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4490                 if (qv->rxr_count || qv->txr_count)
4491                         eics |= ((u64)1 << i);
4492         }
4493
4494         /* Cause software interrupt to ensure rx rings are cleaned */
4495         ixgbe_irq_rearm_queues(adapter, eics);
4496
4497 watchdog_reschedule:
4498         /* Reset the timer */
4499         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4500
4501 watchdog_short_circuit:
4502         schedule_work(&adapter->watchdog_task);
4503 }
4504
4505 /**
4506  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4507  * @work: pointer to work_struct containing our data
4508  **/
4509 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4510 {
4511         struct ixgbe_adapter *adapter = container_of(work,
4512                                                      struct ixgbe_adapter,
4513                                                      multispeed_fiber_task);
4514         struct ixgbe_hw *hw = &adapter->hw;
4515         u32 autoneg;
4516
4517         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4518         autoneg = hw->phy.autoneg_advertised;
4519         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4520                 hw->mac.ops.get_link_capabilities(hw, &autoneg,
4521                                                   &hw->mac.autoneg);
4522         if (hw->mac.ops.setup_link_speed)
4523                 hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
4524         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4525         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4526 }
4527
4528 /**
4529  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4530  * @work: pointer to work_struct containing our data
4531  **/
4532 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4533 {
4534         struct ixgbe_adapter *adapter = container_of(work,
4535                                                      struct ixgbe_adapter,
4536                                                      sfp_config_module_task);
4537         struct ixgbe_hw *hw = &adapter->hw;
4538         u32 err;
4539
4540         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4541
4542         /* Time for electrical oscillations to settle down */
4543         msleep(100);
4544         err = hw->phy.ops.identify_sfp(hw);
4545
4546         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4547                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4548                         "an unsupported SFP+ module type was detected.\n"
4549                         "Reload the driver after installing a supported "
4550                         "module.\n");
4551                 unregister_netdev(adapter->netdev);
4552                 return;
4553         }
4554         hw->mac.ops.setup_sfp(hw);
4555
4556         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4557                 /* This will also work for DA Twinax connections */
4558                 schedule_work(&adapter->multispeed_fiber_task);
4559         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4560 }
4561
4562 /**
4563  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4564  * @work: pointer to work_struct containing our data
4565  **/
4566 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4567 {
4568         struct ixgbe_adapter *adapter = container_of(work,
4569                                                      struct ixgbe_adapter,
4570                                                      fdir_reinit_task);
4571         struct ixgbe_hw *hw = &adapter->hw;
4572         int i;
4573
4574         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4575                 for (i = 0; i < adapter->num_tx_queues; i++)
4576                         set_bit(__IXGBE_FDIR_INIT_DONE,
4577                                 &(adapter->tx_ring[i].reinit_state));
4578         } else {
4579                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4580                         "ignored adding FDIR ATR filters \n");
4581         }
4582         /* Done FDIR Re-initialization, enable transmits */
4583         netif_tx_start_all_queues(adapter->netdev);
4584 }
4585
4586 /**
4587  * ixgbe_watchdog_task - worker thread to bring link up
4588  * @work: pointer to work_struct containing our data
4589  **/
4590 static void ixgbe_watchdog_task(struct work_struct *work)
4591 {
4592         struct ixgbe_adapter *adapter = container_of(work,
4593                                                      struct ixgbe_adapter,
4594                                                      watchdog_task);
4595         struct net_device *netdev = adapter->netdev;
4596         struct ixgbe_hw *hw = &adapter->hw;
4597         u32 link_speed = adapter->link_speed;
4598         bool link_up = adapter->link_up;
4599         int i;
4600         struct ixgbe_ring *tx_ring;
4601         int some_tx_pending = 0;
4602
4603         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4604
4605         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4606                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4607                 if (link_up) {
4608 #ifdef CONFIG_DCB
4609                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4610                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4611                                         hw->mac.ops.fc_enable(hw, i);
4612                         } else {
4613                                 hw->mac.ops.fc_enable(hw, 0);
4614                         }
4615 #else
4616                         hw->mac.ops.fc_enable(hw, 0);
4617 #endif
4618                 }
4619
4620                 if (link_up ||
4621                     time_after(jiffies, (adapter->link_check_timeout +
4622                                          IXGBE_TRY_LINK_TIMEOUT))) {
4623                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4624                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4625                 }
4626                 adapter->link_up = link_up;
4627                 adapter->link_speed = link_speed;
4628         }
4629
4630         if (link_up) {
4631                 if (!netif_carrier_ok(netdev)) {
4632                         bool flow_rx, flow_tx;
4633
4634                         if (hw->mac.type == ixgbe_mac_82599EB) {
4635                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4636                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4637                                 flow_rx = (mflcn & IXGBE_MFLCN_RFCE);
4638                                 flow_tx = (fccfg & IXGBE_FCCFG_TFCE_802_3X);
4639                         } else {
4640                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4641                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4642                                 flow_rx = (frctl & IXGBE_FCTRL_RFCE);
4643                                 flow_tx = (rmcs & IXGBE_RMCS_TFCE_802_3X);
4644                         }
4645
4646                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4647                                "Flow Control: %s\n",
4648                                netdev->name,
4649                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4650                                 "10 Gbps" :
4651                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4652                                  "1 Gbps" : "unknown speed")),
4653                                ((flow_rx && flow_tx) ? "RX/TX" :
4654                                 (flow_rx ? "RX" :
4655                                 (flow_tx ? "TX" : "None"))));
4656
4657                         netif_carrier_on(netdev);
4658                 } else {
4659                         /* Force detection of hung controller */
4660                         adapter->detect_tx_hung = true;
4661                 }
4662         } else {
4663                 adapter->link_up = false;
4664                 adapter->link_speed = 0;
4665                 if (netif_carrier_ok(netdev)) {
4666                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4667                                netdev->name);
4668                         netif_carrier_off(netdev);
4669                 }
4670         }
4671
4672         if (!netif_carrier_ok(netdev)) {
4673                 for (i = 0; i < adapter->num_tx_queues; i++) {
4674                         tx_ring = &adapter->tx_ring[i];
4675                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4676                                 some_tx_pending = 1;
4677                                 break;
4678                         }
4679                 }
4680
4681                 if (some_tx_pending) {
4682                         /* We've lost link, so the controller stops DMA,
4683                          * but we've got queued Tx work that's never going
4684                          * to get done, so reset controller to flush Tx.
4685                          * (Do the reset outside of interrupt context).
4686                          */
4687                          schedule_work(&adapter->reset_task);
4688                 }
4689         }
4690
4691         ixgbe_update_stats(adapter);
4692         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4693 }
4694
4695 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4696                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4697                      u32 tx_flags, u8 *hdr_len)
4698 {
4699         struct ixgbe_adv_tx_context_desc *context_desc;
4700         unsigned int i;
4701         int err;
4702         struct ixgbe_tx_buffer *tx_buffer_info;
4703         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4704         u32 mss_l4len_idx, l4len;
4705
4706         if (skb_is_gso(skb)) {
4707                 if (skb_header_cloned(skb)) {
4708                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4709                         if (err)
4710                                 return err;
4711                 }
4712                 l4len = tcp_hdrlen(skb);
4713                 *hdr_len += l4len;
4714
4715                 if (skb->protocol == htons(ETH_P_IP)) {
4716                         struct iphdr *iph = ip_hdr(skb);
4717                         iph->tot_len = 0;
4718                         iph->check = 0;
4719                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4720                                                                  iph->daddr, 0,
4721                                                                  IPPROTO_TCP,
4722                                                                  0);
4723                         adapter->hw_tso_ctxt++;
4724                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4725                         ipv6_hdr(skb)->payload_len = 0;
4726                         tcp_hdr(skb)->check =
4727                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4728                                              &ipv6_hdr(skb)->daddr,
4729                                              0, IPPROTO_TCP, 0);
4730                         adapter->hw_tso6_ctxt++;
4731                 }
4732
4733                 i = tx_ring->next_to_use;
4734
4735                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4736                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4737
4738                 /* VLAN MACLEN IPLEN */
4739                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4740                         vlan_macip_lens |=
4741                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4742                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4743                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4744                 *hdr_len += skb_network_offset(skb);
4745                 vlan_macip_lens |=
4746                     (skb_transport_header(skb) - skb_network_header(skb));
4747                 *hdr_len +=
4748                     (skb_transport_header(skb) - skb_network_header(skb));
4749                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4750                 context_desc->seqnum_seed = 0;
4751
4752                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4753                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4754                                    IXGBE_ADVTXD_DTYP_CTXT);
4755
4756                 if (skb->protocol == htons(ETH_P_IP))
4757                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4758                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4759                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4760
4761                 /* MSS L4LEN IDX */
4762                 mss_l4len_idx =
4763                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4764                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4765                 /* use index 1 for TSO */
4766                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4767                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4768
4769                 tx_buffer_info->time_stamp = jiffies;
4770                 tx_buffer_info->next_to_watch = i;
4771
4772                 i++;
4773                 if (i == tx_ring->count)
4774                         i = 0;
4775                 tx_ring->next_to_use = i;
4776
4777                 return true;
4778         }
4779         return false;
4780 }
4781
4782 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4783                           struct ixgbe_ring *tx_ring,
4784                           struct sk_buff *skb, u32 tx_flags)
4785 {
4786         struct ixgbe_adv_tx_context_desc *context_desc;
4787         unsigned int i;
4788         struct ixgbe_tx_buffer *tx_buffer_info;
4789         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4790
4791         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4792             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4793                 i = tx_ring->next_to_use;
4794                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4795                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4796
4797                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4798                         vlan_macip_lens |=
4799                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4800                 vlan_macip_lens |= (skb_network_offset(skb) <<
4801                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4802                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4803                         vlan_macip_lens |= (skb_transport_header(skb) -
4804                                             skb_network_header(skb));
4805
4806                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4807                 context_desc->seqnum_seed = 0;
4808
4809                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4810                                     IXGBE_ADVTXD_DTYP_CTXT);
4811
4812                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4813                         switch (skb->protocol) {
4814                         case cpu_to_be16(ETH_P_IP):
4815                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4816                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4817                                         type_tucmd_mlhl |=
4818                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4819                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4820                                         type_tucmd_mlhl |=
4821                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4822                                 break;
4823                         case cpu_to_be16(ETH_P_IPV6):
4824                                 /* XXX what about other V6 headers?? */
4825                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4826                                         type_tucmd_mlhl |=
4827                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4828                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4829                                         type_tucmd_mlhl |=
4830                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4831                                 break;
4832                         default:
4833                                 if (unlikely(net_ratelimit())) {
4834                                         DPRINTK(PROBE, WARNING,
4835                                          "partial checksum but proto=%x!\n",
4836                                          skb->protocol);
4837                                 }
4838                                 break;
4839                         }
4840                 }
4841
4842                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4843                 /* use index zero for tx checksum offload */
4844                 context_desc->mss_l4len_idx = 0;
4845
4846                 tx_buffer_info->time_stamp = jiffies;
4847                 tx_buffer_info->next_to_watch = i;
4848
4849                 adapter->hw_csum_tx_good++;
4850                 i++;
4851                 if (i == tx_ring->count)
4852                         i = 0;
4853                 tx_ring->next_to_use = i;
4854
4855                 return true;
4856         }
4857
4858         return false;
4859 }
4860
4861 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4862                         struct ixgbe_ring *tx_ring,
4863                         struct sk_buff *skb, u32 tx_flags,
4864                         unsigned int first)
4865 {
4866         struct ixgbe_tx_buffer *tx_buffer_info;
4867         unsigned int len;
4868         unsigned int total = skb->len;
4869         unsigned int offset = 0, size, count = 0, i;
4870         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4871         unsigned int f;
4872         dma_addr_t *map;
4873
4874         i = tx_ring->next_to_use;
4875
4876         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4877                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4878                 return 0;
4879         }
4880
4881         map = skb_shinfo(skb)->dma_maps;
4882
4883         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4884                 /* excluding fcoe_crc_eof for FCoE */
4885                 total -= sizeof(struct fcoe_crc_eof);
4886
4887         len = min(skb_headlen(skb), total);
4888         while (len) {
4889                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4890                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4891
4892                 tx_buffer_info->length = size;
4893                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4894                 tx_buffer_info->time_stamp = jiffies;
4895                 tx_buffer_info->next_to_watch = i;
4896
4897                 len -= size;
4898                 total -= size;
4899                 offset += size;
4900                 count++;
4901
4902                 if (len) {
4903                         i++;
4904                         if (i == tx_ring->count)
4905                                 i = 0;
4906                 }
4907         }
4908
4909         for (f = 0; f < nr_frags; f++) {
4910                 struct skb_frag_struct *frag;
4911
4912                 frag = &skb_shinfo(skb)->frags[f];
4913                 len = min((unsigned int)frag->size, total);
4914                 offset = 0;
4915
4916                 while (len) {
4917                         i++;
4918                         if (i == tx_ring->count)
4919                                 i = 0;
4920
4921                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4922                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4923
4924                         tx_buffer_info->length = size;
4925                         tx_buffer_info->dma = map[f] + offset;
4926                         tx_buffer_info->time_stamp = jiffies;
4927                         tx_buffer_info->next_to_watch = i;
4928
4929                         len -= size;
4930                         total -= size;
4931                         offset += size;
4932                         count++;
4933                 }
4934                 if (total == 0)
4935                         break;
4936         }
4937
4938         tx_ring->tx_buffer_info[i].skb = skb;
4939         tx_ring->tx_buffer_info[first].next_to_watch = i;
4940
4941         return count;
4942 }
4943
4944 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4945                            struct ixgbe_ring *tx_ring,
4946                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4947 {
4948         union ixgbe_adv_tx_desc *tx_desc = NULL;
4949         struct ixgbe_tx_buffer *tx_buffer_info;
4950         u32 olinfo_status = 0, cmd_type_len = 0;
4951         unsigned int i;
4952         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4953
4954         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4955
4956         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4957
4958         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4959                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4960
4961         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4962                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4963
4964                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4965                                  IXGBE_ADVTXD_POPTS_SHIFT;
4966
4967                 /* use index 1 context for tso */
4968                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4969                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
4970                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
4971                                          IXGBE_ADVTXD_POPTS_SHIFT;
4972
4973         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
4974                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4975                                  IXGBE_ADVTXD_POPTS_SHIFT;
4976
4977         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
4978                 olinfo_status |= IXGBE_ADVTXD_CC;
4979                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4980                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
4981                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4982         }
4983
4984         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
4985
4986         i = tx_ring->next_to_use;
4987         while (count--) {
4988                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4989                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
4990                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
4991                 tx_desc->read.cmd_type_len =
4992                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
4993                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4994                 i++;
4995                 if (i == tx_ring->count)
4996                         i = 0;
4997         }
4998
4999         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5000
5001         /*
5002          * Force memory writes to complete before letting h/w
5003          * know there are new descriptors to fetch.  (Only
5004          * applicable for weak-ordered memory model archs,
5005          * such as IA-64).
5006          */
5007         wmb();
5008
5009         tx_ring->next_to_use = i;
5010         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5011 }
5012
5013 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5014                       int queue, u32 tx_flags)
5015 {
5016         /* Right now, we support IPv4 only */
5017         struct ixgbe_atr_input atr_input;
5018         struct tcphdr *th;
5019         struct udphdr *uh;
5020         struct iphdr *iph = ip_hdr(skb);
5021         struct ethhdr *eth = (struct ethhdr *)skb->data;
5022         u16 vlan_id, src_port, dst_port, flex_bytes;
5023         u32 src_ipv4_addr, dst_ipv4_addr;
5024         u8 l4type = 0;
5025
5026         /* check if we're UDP or TCP */
5027         if (iph->protocol == IPPROTO_TCP) {
5028                 th = tcp_hdr(skb);
5029                 src_port = th->source;
5030                 dst_port = th->dest;
5031                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5032                 /* l4type IPv4 type is 0, no need to assign */
5033         } else if(iph->protocol == IPPROTO_UDP) {
5034                 uh = udp_hdr(skb);
5035                 src_port = uh->source;
5036                 dst_port = uh->dest;
5037                 l4type |= IXGBE_ATR_L4TYPE_UDP;
5038                 /* l4type IPv4 type is 0, no need to assign */
5039         } else {
5040                 /* Unsupported L4 header, just bail here */
5041                 return;
5042         }
5043
5044         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5045
5046         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5047                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5048         src_ipv4_addr = iph->saddr;
5049         dst_ipv4_addr = iph->daddr;
5050         flex_bytes = eth->h_proto;
5051
5052         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5053         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5054         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5055         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5056         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5057         /* src and dst are inverted, think how the receiver sees them */
5058         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5059         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5060
5061         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5062         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5063 }
5064
5065 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5066                                  struct ixgbe_ring *tx_ring, int size)
5067 {
5068         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5069
5070         netif_stop_subqueue(netdev, tx_ring->queue_index);
5071         /* Herbert's original patch had:
5072          *  smp_mb__after_netif_stop_queue();
5073          * but since that doesn't exist yet, just open code it. */
5074         smp_mb();
5075
5076         /* We need to check again in a case another CPU has just
5077          * made room available. */
5078         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5079                 return -EBUSY;
5080
5081         /* A reprieve! - use start_queue because it doesn't call schedule */
5082         netif_start_subqueue(netdev, tx_ring->queue_index);
5083         ++adapter->restart_queue;
5084         return 0;
5085 }
5086
5087 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5088                               struct ixgbe_ring *tx_ring, int size)
5089 {
5090         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5091                 return 0;
5092         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5093 }
5094
5095 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5096 {
5097         struct ixgbe_adapter *adapter = netdev_priv(dev);
5098
5099         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5100                 return smp_processor_id();
5101
5102         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5103                 return 0;  /* All traffic should default to class 0 */
5104
5105         return skb_tx_hash(dev, skb);
5106 }
5107
5108 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
5109 {
5110         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5111         struct ixgbe_ring *tx_ring;
5112         unsigned int first;
5113         unsigned int tx_flags = 0;
5114         u8 hdr_len = 0;
5115         int r_idx = 0, tso;
5116         int count = 0;
5117         unsigned int f;
5118
5119         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5120                 tx_flags |= vlan_tx_tag_get(skb);
5121                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5122                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5123                         tx_flags |= (skb->queue_mapping << 13);
5124                 }
5125                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5126                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5127         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5128                 if (skb->priority != TC_PRIO_CONTROL) {
5129                         tx_flags |= (skb->queue_mapping << 13);
5130                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5131                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5132                 } else {
5133                         skb->queue_mapping =
5134                                 adapter->ring_feature[RING_F_DCB].indices-1;
5135                 }
5136         }
5137
5138         r_idx = skb->queue_mapping;
5139         tx_ring = &adapter->tx_ring[r_idx];
5140
5141         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5142             (skb->protocol == htons(ETH_P_FCOE)))
5143                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5144
5145         /* four things can cause us to need a context descriptor */
5146         if (skb_is_gso(skb) ||
5147             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5148             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5149             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5150                 count++;
5151
5152         count += TXD_USE_COUNT(skb_headlen(skb));
5153         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5154                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5155
5156         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5157                 adapter->tx_busy++;
5158                 return NETDEV_TX_BUSY;
5159         }
5160
5161         first = tx_ring->next_to_use;
5162         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5163 #ifdef IXGBE_FCOE
5164                 /* setup tx offload for FCoE */
5165                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5166                 if (tso < 0) {
5167                         dev_kfree_skb_any(skb);
5168                         return NETDEV_TX_OK;
5169                 }
5170                 if (tso)
5171                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5172 #endif /* IXGBE_FCOE */
5173         } else {
5174                 if (skb->protocol == htons(ETH_P_IP))
5175                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5176                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5177                 if (tso < 0) {
5178                         dev_kfree_skb_any(skb);
5179                         return NETDEV_TX_OK;
5180                 }
5181
5182                 if (tso)
5183                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5184                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5185                          (skb->ip_summed == CHECKSUM_PARTIAL))
5186                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5187         }
5188
5189         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5190         if (count) {
5191                 /* add the ATR filter if ATR is on */
5192                 if (tx_ring->atr_sample_rate) {
5193                         ++tx_ring->atr_count;
5194                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5195                              test_bit(__IXGBE_FDIR_INIT_DONE,
5196                                       &tx_ring->reinit_state)) {
5197                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5198                                           tx_flags);
5199                                 tx_ring->atr_count = 0;
5200                         }
5201                 }
5202                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5203                                hdr_len);
5204                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5205
5206         } else {
5207                 dev_kfree_skb_any(skb);
5208                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5209                 tx_ring->next_to_use = first;
5210         }
5211
5212         return NETDEV_TX_OK;
5213 }
5214
5215 /**
5216  * ixgbe_get_stats - Get System Network Statistics
5217  * @netdev: network interface device structure
5218  *
5219  * Returns the address of the device statistics structure.
5220  * The statistics are actually updated from the timer callback.
5221  **/
5222 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5223 {
5224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5225
5226         /* only return the current stats */
5227         return &adapter->net_stats;
5228 }
5229
5230 /**
5231  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5232  * @netdev: network interface device structure
5233  * @p: pointer to an address structure
5234  *
5235  * Returns 0 on success, negative on failure
5236  **/
5237 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5238 {
5239         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5240         struct ixgbe_hw *hw = &adapter->hw;
5241         struct sockaddr *addr = p;
5242
5243         if (!is_valid_ether_addr(addr->sa_data))
5244                 return -EADDRNOTAVAIL;
5245
5246         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5247         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5248
5249         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5250
5251         return 0;
5252 }
5253
5254 static int
5255 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5256 {
5257         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5258         struct ixgbe_hw *hw = &adapter->hw;
5259         u16 value;
5260         int rc;
5261
5262         if (prtad != hw->phy.mdio.prtad)
5263                 return -EINVAL;
5264         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5265         if (!rc)
5266                 rc = value;
5267         return rc;
5268 }
5269
5270 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5271                             u16 addr, u16 value)
5272 {
5273         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5274         struct ixgbe_hw *hw = &adapter->hw;
5275
5276         if (prtad != hw->phy.mdio.prtad)
5277                 return -EINVAL;
5278         return hw->phy.ops.write_reg(hw, addr, devad, value);
5279 }
5280
5281 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5282 {
5283         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5284
5285         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5286 }
5287
5288 /**
5289  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5290  * netdev->dev_addrs
5291  * @netdev: network interface device structure
5292  *
5293  * Returns non-zero on failure
5294  **/
5295 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5296 {
5297         int err = 0;
5298         struct ixgbe_adapter *adapter = netdev_priv(dev);
5299         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5300
5301         if (is_valid_ether_addr(mac->san_addr)) {
5302                 rtnl_lock();
5303                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5304                 rtnl_unlock();
5305         }
5306         return err;
5307 }
5308
5309 /**
5310  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5311  * netdev->dev_addrs
5312  * @netdev: network interface device structure
5313  *
5314  * Returns non-zero on failure
5315  **/
5316 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5317 {
5318         int err = 0;
5319         struct ixgbe_adapter *adapter = netdev_priv(dev);
5320         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5321
5322         if (is_valid_ether_addr(mac->san_addr)) {
5323                 rtnl_lock();
5324                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5325                 rtnl_unlock();
5326         }
5327         return err;
5328 }
5329
5330 #ifdef CONFIG_NET_POLL_CONTROLLER
5331 /*
5332  * Polling 'interrupt' - used by things like netconsole to send skbs
5333  * without having to re-enable interrupts. It's not called while
5334  * the interrupt routine is executing.
5335  */
5336 static void ixgbe_netpoll(struct net_device *netdev)
5337 {
5338         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5339         int i;
5340
5341         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5342         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5343                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5344                 for (i = 0; i < num_q_vectors; i++) {
5345                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5346                         ixgbe_msix_clean_many(0, q_vector);
5347                 }
5348         } else {
5349                 ixgbe_intr(adapter->pdev->irq, netdev);
5350         }
5351         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5352 }
5353 #endif
5354
5355 static const struct net_device_ops ixgbe_netdev_ops = {
5356         .ndo_open               = ixgbe_open,
5357         .ndo_stop               = ixgbe_close,
5358         .ndo_start_xmit         = ixgbe_xmit_frame,
5359         .ndo_select_queue       = ixgbe_select_queue,
5360         .ndo_get_stats          = ixgbe_get_stats,
5361         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5362         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5363         .ndo_validate_addr      = eth_validate_addr,
5364         .ndo_set_mac_address    = ixgbe_set_mac,
5365         .ndo_change_mtu         = ixgbe_change_mtu,
5366         .ndo_tx_timeout         = ixgbe_tx_timeout,
5367         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5368         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5369         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5370         .ndo_do_ioctl           = ixgbe_ioctl,
5371 #ifdef CONFIG_NET_POLL_CONTROLLER
5372         .ndo_poll_controller    = ixgbe_netpoll,
5373 #endif
5374 #ifdef IXGBE_FCOE
5375         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5376         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5377 #endif /* IXGBE_FCOE */
5378 };
5379
5380 /**
5381  * ixgbe_probe - Device Initialization Routine
5382  * @pdev: PCI device information struct
5383  * @ent: entry in ixgbe_pci_tbl
5384  *
5385  * Returns 0 on success, negative on failure
5386  *
5387  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5388  * The OS initialization, configuring of the adapter private structure,
5389  * and a hardware reset occur.
5390  **/
5391 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5392                                  const struct pci_device_id *ent)
5393 {
5394         struct net_device *netdev;
5395         struct ixgbe_adapter *adapter = NULL;
5396         struct ixgbe_hw *hw;
5397         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5398         static int cards_found;
5399         int i, err, pci_using_dac;
5400 #ifdef IXGBE_FCOE
5401         u16 device_caps;
5402 #endif
5403         u32 part_num, eec;
5404
5405         err = pci_enable_device_mem(pdev);
5406         if (err)
5407                 return err;
5408
5409         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5410             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5411                 pci_using_dac = 1;
5412         } else {
5413                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5414                 if (err) {
5415                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5416                         if (err) {
5417                                 dev_err(&pdev->dev, "No usable DMA "
5418                                         "configuration, aborting\n");
5419                                 goto err_dma;
5420                         }
5421                 }
5422                 pci_using_dac = 0;
5423         }
5424
5425         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5426                                            IORESOURCE_MEM), ixgbe_driver_name);
5427         if (err) {
5428                 dev_err(&pdev->dev,
5429                         "pci_request_selected_regions failed 0x%x\n", err);
5430                 goto err_pci_reg;
5431         }
5432
5433         err = pci_enable_pcie_error_reporting(pdev);
5434         if (err) {
5435                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5436                                     "0x%x\n", err);
5437                 /* non-fatal, continue */
5438         }
5439
5440         pci_set_master(pdev);
5441         pci_save_state(pdev);
5442
5443         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5444         if (!netdev) {
5445                 err = -ENOMEM;
5446                 goto err_alloc_etherdev;
5447         }
5448
5449         SET_NETDEV_DEV(netdev, &pdev->dev);
5450
5451         pci_set_drvdata(pdev, netdev);
5452         adapter = netdev_priv(netdev);
5453
5454         adapter->netdev = netdev;
5455         adapter->pdev = pdev;
5456         hw = &adapter->hw;
5457         hw->back = adapter;
5458         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5459
5460         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5461                               pci_resource_len(pdev, 0));
5462         if (!hw->hw_addr) {
5463                 err = -EIO;
5464                 goto err_ioremap;
5465         }
5466
5467         for (i = 1; i <= 5; i++) {
5468                 if (pci_resource_len(pdev, i) == 0)
5469                         continue;
5470         }
5471
5472         netdev->netdev_ops = &ixgbe_netdev_ops;
5473         ixgbe_set_ethtool_ops(netdev);
5474         netdev->watchdog_timeo = 5 * HZ;
5475         strcpy(netdev->name, pci_name(pdev));
5476
5477         adapter->bd_number = cards_found;
5478
5479         /* Setup hw api */
5480         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5481         hw->mac.type  = ii->mac;
5482
5483         /* EEPROM */
5484         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5485         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5486         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5487         if (!(eec & (1 << 8)))
5488                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5489
5490         /* PHY */
5491         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5492         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5493         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5494         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5495         hw->phy.mdio.mmds = 0;
5496         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5497         hw->phy.mdio.dev = netdev;
5498         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5499         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5500
5501         /* set up this timer and work struct before calling get_invariants
5502          * which might start the timer
5503          */
5504         init_timer(&adapter->sfp_timer);
5505         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5506         adapter->sfp_timer.data = (unsigned long) adapter;
5507
5508         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5509
5510         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5511         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5512
5513         /* a new SFP+ module arrival, called from GPI SDP2 context */
5514         INIT_WORK(&adapter->sfp_config_module_task,
5515                   ixgbe_sfp_config_module_task);
5516
5517         ii->get_invariants(hw);
5518
5519         /* setup the private structure */
5520         err = ixgbe_sw_init(adapter);
5521         if (err)
5522                 goto err_sw_init;
5523
5524         /*
5525          * If there is a fan on this device and it has failed log the
5526          * failure.
5527          */
5528         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5529                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5530                 if (esdp & IXGBE_ESDP_SDP1)
5531                         DPRINTK(PROBE, CRIT,
5532                                 "Fan has stopped, replace the adapter\n");
5533         }
5534
5535         /* reset_hw fills in the perm_addr as well */
5536         err = hw->mac.ops.reset_hw(hw);
5537         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5538             hw->mac.type == ixgbe_mac_82598EB) {
5539                 /*
5540                  * Start a kernel thread to watch for a module to arrive.
5541                  * Only do this for 82598, since 82599 will generate
5542                  * interrupts on module arrival.
5543                  */
5544                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5545                 mod_timer(&adapter->sfp_timer,
5546                           round_jiffies(jiffies + (2 * HZ)));
5547                 err = 0;
5548         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5549                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5550                         "an unsupported SFP+ module type was detected.\n"
5551                         "Reload the driver after installing a supported "
5552                         "module.\n");
5553                 goto err_sw_init;
5554         } else if (err) {
5555                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5556                 goto err_sw_init;
5557         }
5558
5559         netdev->features = NETIF_F_SG |
5560                            NETIF_F_IP_CSUM |
5561                            NETIF_F_HW_VLAN_TX |
5562                            NETIF_F_HW_VLAN_RX |
5563                            NETIF_F_HW_VLAN_FILTER;
5564
5565         netdev->features |= NETIF_F_IPV6_CSUM;
5566         netdev->features |= NETIF_F_TSO;
5567         netdev->features |= NETIF_F_TSO6;
5568         netdev->features |= NETIF_F_GRO;
5569
5570         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5571                 netdev->features |= NETIF_F_SCTP_CSUM;
5572
5573         netdev->vlan_features |= NETIF_F_TSO;
5574         netdev->vlan_features |= NETIF_F_TSO6;
5575         netdev->vlan_features |= NETIF_F_IP_CSUM;
5576         netdev->vlan_features |= NETIF_F_SG;
5577
5578         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5579                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5580
5581 #ifdef CONFIG_IXGBE_DCB
5582         netdev->dcbnl_ops = &dcbnl_ops;
5583 #endif
5584
5585 #ifdef IXGBE_FCOE
5586         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5587                 if (hw->mac.ops.get_device_caps) {
5588                         hw->mac.ops.get_device_caps(hw, &device_caps);
5589                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5590                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5591                 }
5592         }
5593 #endif /* IXGBE_FCOE */
5594         if (pci_using_dac)
5595                 netdev->features |= NETIF_F_HIGHDMA;
5596
5597         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5598                 netdev->features |= NETIF_F_LRO;
5599
5600         /* make sure the EEPROM is good */
5601         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5602                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5603                 err = -EIO;
5604                 goto err_eeprom;
5605         }
5606
5607         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5608         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5609
5610         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5611                 dev_err(&pdev->dev, "invalid MAC address\n");
5612                 err = -EIO;
5613                 goto err_eeprom;
5614         }
5615
5616         init_timer(&adapter->watchdog_timer);
5617         adapter->watchdog_timer.function = &ixgbe_watchdog;
5618         adapter->watchdog_timer.data = (unsigned long)adapter;
5619
5620         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5621         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5622
5623         err = ixgbe_init_interrupt_scheme(adapter);
5624         if (err)
5625                 goto err_sw_init;
5626
5627         switch (pdev->device) {
5628         case IXGBE_DEV_ID_82599_KX4:
5629                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5630                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5631                 /* Enable ACPI wakeup in GRC */
5632                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5633                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5634                 break;
5635         default:
5636                 adapter->wol = 0;
5637                 break;
5638         }
5639         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5640
5641         /* pick up the PCI bus settings for reporting later */
5642         hw->mac.ops.get_bus_info(hw);
5643
5644         /* print bus type/speed/width info */
5645         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5646                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5647                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5648                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5649                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5650                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5651                  "Unknown"),
5652                 netdev->dev_addr);
5653         ixgbe_read_pba_num_generic(hw, &part_num);
5654         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5655                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5656                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5657                          (part_num >> 8), (part_num & 0xff));
5658         else
5659                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5660                          hw->mac.type, hw->phy.type,
5661                          (part_num >> 8), (part_num & 0xff));
5662
5663         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5664                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5665                          "this card is not sufficient for optimal "
5666                          "performance.\n");
5667                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5668                          "PCI-Express slot is required.\n");
5669         }
5670
5671         /* save off EEPROM version number */
5672         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5673
5674         /* reset the hardware with the new settings */
5675         err = hw->mac.ops.start_hw(hw);
5676
5677         if (err == IXGBE_ERR_EEPROM_VERSION) {
5678                 /* We are running on a pre-production device, log a warning */
5679                 dev_warn(&pdev->dev, "This device is a pre-production "
5680                          "adapter/LOM.  Please be aware there may be issues "
5681                          "associated with your hardware.  If you are "
5682                          "experiencing problems please contact your Intel or "
5683                          "hardware representative who provided you with this "
5684                          "hardware.\n");
5685         }
5686         strcpy(netdev->name, "eth%d");
5687         err = register_netdev(netdev);
5688         if (err)
5689                 goto err_register;
5690
5691         /* carrier off reporting is important to ethtool even BEFORE open */
5692         netif_carrier_off(netdev);
5693
5694         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5695             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5696                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5697
5698 #ifdef CONFIG_IXGBE_DCA
5699         if (dca_add_requester(&pdev->dev) == 0) {
5700                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5701                 ixgbe_setup_dca(adapter);
5702         }
5703 #endif
5704         /* add san mac addr to netdev */
5705         ixgbe_add_sanmac_netdev(netdev);
5706
5707         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5708         cards_found++;
5709         return 0;
5710
5711 err_register:
5712         ixgbe_release_hw_control(adapter);
5713         ixgbe_clear_interrupt_scheme(adapter);
5714 err_sw_init:
5715 err_eeprom:
5716         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5717         del_timer_sync(&adapter->sfp_timer);
5718         cancel_work_sync(&adapter->sfp_task);
5719         cancel_work_sync(&adapter->multispeed_fiber_task);
5720         cancel_work_sync(&adapter->sfp_config_module_task);
5721         iounmap(hw->hw_addr);
5722 err_ioremap:
5723         free_netdev(netdev);
5724 err_alloc_etherdev:
5725         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5726                                      IORESOURCE_MEM));
5727 err_pci_reg:
5728 err_dma:
5729         pci_disable_device(pdev);
5730         return err;
5731 }
5732
5733 /**
5734  * ixgbe_remove - Device Removal Routine
5735  * @pdev: PCI device information struct
5736  *
5737  * ixgbe_remove is called by the PCI subsystem to alert the driver
5738  * that it should release a PCI device.  The could be caused by a
5739  * Hot-Plug event, or because the driver is going to be removed from
5740  * memory.
5741  **/
5742 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5743 {
5744         struct net_device *netdev = pci_get_drvdata(pdev);
5745         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5746         int err;
5747
5748         set_bit(__IXGBE_DOWN, &adapter->state);
5749         /* clear the module not found bit to make sure the worker won't
5750          * reschedule
5751          */
5752         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5753         del_timer_sync(&adapter->watchdog_timer);
5754
5755         del_timer_sync(&adapter->sfp_timer);
5756         cancel_work_sync(&adapter->watchdog_task);
5757         cancel_work_sync(&adapter->sfp_task);
5758         cancel_work_sync(&adapter->multispeed_fiber_task);
5759         cancel_work_sync(&adapter->sfp_config_module_task);
5760         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5761             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5762                 cancel_work_sync(&adapter->fdir_reinit_task);
5763         flush_scheduled_work();
5764
5765 #ifdef CONFIG_IXGBE_DCA
5766         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5767                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5768                 dca_remove_requester(&pdev->dev);
5769                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5770         }
5771
5772 #endif
5773 #ifdef IXGBE_FCOE
5774         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5775                 ixgbe_cleanup_fcoe(adapter);
5776
5777 #endif /* IXGBE_FCOE */
5778
5779         /* remove the added san mac */
5780         ixgbe_del_sanmac_netdev(netdev);
5781
5782         if (netdev->reg_state == NETREG_REGISTERED)
5783                 unregister_netdev(netdev);
5784
5785         ixgbe_clear_interrupt_scheme(adapter);
5786
5787         ixgbe_release_hw_control(adapter);
5788
5789         iounmap(adapter->hw.hw_addr);
5790         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5791                                      IORESOURCE_MEM));
5792
5793         DPRINTK(PROBE, INFO, "complete\n");
5794
5795         free_netdev(netdev);
5796
5797         err = pci_disable_pcie_error_reporting(pdev);
5798         if (err)
5799                 dev_err(&pdev->dev,
5800                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5801
5802         pci_disable_device(pdev);
5803 }
5804
5805 /**
5806  * ixgbe_io_error_detected - called when PCI error is detected
5807  * @pdev: Pointer to PCI device
5808  * @state: The current pci connection state
5809  *
5810  * This function is called after a PCI bus error affecting
5811  * this device has been detected.
5812  */
5813 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5814                                                 pci_channel_state_t state)
5815 {
5816         struct net_device *netdev = pci_get_drvdata(pdev);
5817         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5818
5819         netif_device_detach(netdev);
5820
5821         if (state == pci_channel_io_perm_failure)
5822                 return PCI_ERS_RESULT_DISCONNECT;
5823
5824         if (netif_running(netdev))
5825                 ixgbe_down(adapter);
5826         pci_disable_device(pdev);
5827
5828         /* Request a slot reset. */
5829         return PCI_ERS_RESULT_NEED_RESET;
5830 }
5831
5832 /**
5833  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5834  * @pdev: Pointer to PCI device
5835  *
5836  * Restart the card from scratch, as if from a cold-boot.
5837  */
5838 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5839 {
5840         struct net_device *netdev = pci_get_drvdata(pdev);
5841         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5842         pci_ers_result_t result;
5843         int err;
5844
5845         if (pci_enable_device_mem(pdev)) {
5846                 DPRINTK(PROBE, ERR,
5847                         "Cannot re-enable PCI device after reset.\n");
5848                 result = PCI_ERS_RESULT_DISCONNECT;
5849         } else {
5850                 pci_set_master(pdev);
5851                 pci_restore_state(pdev);
5852
5853                 pci_wake_from_d3(pdev, false);
5854
5855                 ixgbe_reset(adapter);
5856                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5857                 result = PCI_ERS_RESULT_RECOVERED;
5858         }
5859
5860         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5861         if (err) {
5862                 dev_err(&pdev->dev,
5863                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5864                 /* non-fatal, continue */
5865         }
5866
5867         return result;
5868 }
5869
5870 /**
5871  * ixgbe_io_resume - called when traffic can start flowing again.
5872  * @pdev: Pointer to PCI device
5873  *
5874  * This callback is called when the error recovery driver tells us that
5875  * its OK to resume normal operation.
5876  */
5877 static void ixgbe_io_resume(struct pci_dev *pdev)
5878 {
5879         struct net_device *netdev = pci_get_drvdata(pdev);
5880         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5881
5882         if (netif_running(netdev)) {
5883                 if (ixgbe_up(adapter)) {
5884                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5885                         return;
5886                 }
5887         }
5888
5889         netif_device_attach(netdev);
5890 }
5891
5892 static struct pci_error_handlers ixgbe_err_handler = {
5893         .error_detected = ixgbe_io_error_detected,
5894         .slot_reset = ixgbe_io_slot_reset,
5895         .resume = ixgbe_io_resume,
5896 };
5897
5898 static struct pci_driver ixgbe_driver = {
5899         .name     = ixgbe_driver_name,
5900         .id_table = ixgbe_pci_tbl,
5901         .probe    = ixgbe_probe,
5902         .remove   = __devexit_p(ixgbe_remove),
5903 #ifdef CONFIG_PM
5904         .suspend  = ixgbe_suspend,
5905         .resume   = ixgbe_resume,
5906 #endif
5907         .shutdown = ixgbe_shutdown,
5908         .err_handler = &ixgbe_err_handler
5909 };
5910
5911 /**
5912  * ixgbe_init_module - Driver Registration Routine
5913  *
5914  * ixgbe_init_module is the first routine called when the driver is
5915  * loaded. All it does is register with the PCI subsystem.
5916  **/
5917 static int __init ixgbe_init_module(void)
5918 {
5919         int ret;
5920         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5921                ixgbe_driver_string, ixgbe_driver_version);
5922
5923         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5924
5925 #ifdef CONFIG_IXGBE_DCA
5926         dca_register_notify(&dca_notifier);
5927 #endif
5928
5929         ret = pci_register_driver(&ixgbe_driver);
5930         return ret;
5931 }
5932
5933 module_init(ixgbe_init_module);
5934
5935 /**
5936  * ixgbe_exit_module - Driver Exit Cleanup Routine
5937  *
5938  * ixgbe_exit_module is called just before the driver is removed
5939  * from memory.
5940  **/
5941 static void __exit ixgbe_exit_module(void)
5942 {
5943 #ifdef CONFIG_IXGBE_DCA
5944         dca_unregister_notify(&dca_notifier);
5945 #endif
5946         pci_unregister_driver(&ixgbe_driver);
5947 }
5948
5949 #ifdef CONFIG_IXGBE_DCA
5950 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5951                             void *p)
5952 {
5953         int ret_val;
5954
5955         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5956                                          __ixgbe_notify_dca);
5957
5958         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5959 }
5960
5961 #endif /* CONFIG_IXGBE_DCA */
5962 #ifdef DEBUG
5963 /**
5964  * ixgbe_get_hw_dev_name - return device name string
5965  * used by hardware layer to print debugging information
5966  **/
5967 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
5968 {
5969         struct ixgbe_adapter *adapter = hw->back;
5970         return adapter->netdev->name;
5971 }
5972
5973 #endif
5974 module_exit(ixgbe_exit_module);
5975
5976 /* ixgbe_main.c */