drivers/net/irda/smsc-ircc2.c

   1 /*********************************************************************
   2  *
   3  * Description:   Driver for the SMC Infrared Communications Controller
   4  * Status:        Experimental.
   5  * Author:        Daniele Peri (peri@csai.unipa.it)
   6  * Created at:
   7  * Modified at:
   8  * Modified by:
   9  *
  10  *     Copyright (c) 2002      Daniele Peri
  11  *     All Rights Reserved.
  12  *     Copyright (c) 2002      Jean Tourrilhes
  13  *     Copyright (c) 2006      Linus Walleij
  14  *
  15  *
  16  * Based on smc-ircc.c:
  17  *
  18  *     Copyright (c) 2001      Stefani Seibold
  19  *     Copyright (c) 1999-2001 Dag Brattli
  20  *     Copyright (c) 1998-1999 Thomas Davis,
  21  *
  22  *      and irport.c:
  23  *
  24  *     Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
  25  *
  26  *
  27  *     This program is free software; you can redistribute it and/or
  28  *     modify it under the terms of the GNU General Public License as
  29  *     published by the Free Software Foundation; either version 2 of
  30  *     the License, or (at your option) any later version.
  31  *
  32  *     This program is distributed in the hope that it will be useful,
  33  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  34  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  35  *     GNU General Public License for more details.
  36  *
  37  *     You should have received a copy of the GNU General Public License
  38  *     along with this program; if not, write to the Free Software
  39  *     Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  40  *     MA 02111-1307 USA
  41  *
  42  ********************************************************************/
  43
  44 #include <linux/module.h>
  45 #include <linux/kernel.h>
  46 #include <linux/types.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/ioport.h>
  50 #include <linux/delay.h>
  51 #include <linux/init.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/rtnetlink.h>
  54 #include <linux/serial_reg.h>
  55 #include <linux/dma-mapping.h>
  56 #include <linux/pnp.h>
  57 #include <linux/platform_device.h>
  58 #include <linux/gfp.h>
  59
  60 #include <asm/io.h>
  61 #include <asm/dma.h>
  62 #include <asm/byteorder.h>
  63
  64 #include <linux/spinlock.h>
  65 #include <linux/pm.h>
  66 #ifdef CONFIG_PCI
  67 #include <linux/pci.h>
  68 #endif
  69
  70 #include <net/irda/wrapper.h>
  71 #include <net/irda/irda.h>
  72 #include <net/irda/irda_device.h>
  73
  74 #include "smsc-ircc2.h"
  75 #include "smsc-sio.h"
  76
  77
  78 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
  79 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
  80 MODULE_LICENSE("GPL");
  81
  82 static int smsc_nopnp = 1;
  83 module_param_named(nopnp, smsc_nopnp, bool, 0);
  84 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
  85
  86 #define DMA_INVAL 255
  87 static int ircc_dma = DMA_INVAL;
  88 module_param(ircc_dma, int, 0);
  89 MODULE_PARM_DESC(ircc_dma, "DMA channel");
  90
  91 #define IRQ_INVAL 255
  92 static int ircc_irq = IRQ_INVAL;
  93 module_param(ircc_irq, int, 0);
  94 MODULE_PARM_DESC(ircc_irq, "IRQ line");
  95
  96 static int ircc_fir;
  97 module_param(ircc_fir, int, 0);
  98 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
  99
 100 static int ircc_sir;
 101 module_param(ircc_sir, int, 0);
 102 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
 103
 104 static int ircc_cfg;
 105 module_param(ircc_cfg, int, 0);
 106 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
 107
 108 static int ircc_transceiver;
 109 module_param(ircc_transceiver, int, 0);
 110 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
 111
 112 /* Types */
 113
 114 #ifdef CONFIG_PCI
 115 struct smsc_ircc_subsystem_configuration {
 116         unsigned short vendor; /* PCI vendor ID */
 117         unsigned short device; /* PCI vendor ID */
 118         unsigned short subvendor; /* PCI subsystem vendor ID */
 119         unsigned short subdevice; /* PCI subsystem device ID */
 120         unsigned short sir_io; /* I/O port for SIR */
 121         unsigned short fir_io; /* I/O port for FIR */
 122         unsigned char  fir_irq; /* FIR IRQ */
 123         unsigned char  fir_dma; /* FIR DMA */
 124         unsigned short cfg_base; /* I/O port for chip configuration */
 125         int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
 126         const char *name;       /* name shown as info */
 127 };
 128 #endif
 129
 130 struct smsc_transceiver {
 131         char *name;
 132         void (*set_for_speed)(int fir_base, u32 speed);
 133         int  (*probe)(int fir_base);
 134 };
 135
 136 struct smsc_chip {
 137         char *name;
 138         #if 0
 139         u8      type;
 140         #endif
 141         u16 flags;
 142         u8 devid;
 143         u8 rev;
 144 };
 145
 146 struct smsc_chip_address {
 147         unsigned int cfg_base;
 148         unsigned int type;
 149 };
 150
 151 /* Private data for each instance */
 152 struct smsc_ircc_cb {
 153         struct net_device *netdev;     /* Yes! we are some kind of netdevice */
 154         struct irlap_cb    *irlap; /* The link layer we are binded to */
 155
 156         chipio_t io;               /* IrDA controller information */
 157         iobuff_t tx_buff;          /* Transmit buffer */
 158         iobuff_t rx_buff;          /* Receive buffer */
 159         dma_addr_t tx_buff_dma;
 160         dma_addr_t rx_buff_dma;
 161
 162         struct qos_info qos;       /* QoS capabilities for this device */
 163
 164         spinlock_t lock;           /* For serializing operations */
 165
 166         __u32 new_speed;
 167         __u32 flags;               /* Interface flags */
 168
 169         int tx_buff_offsets[10];   /* Offsets between frames in tx_buff */
 170         int tx_len;                /* Number of frames in tx_buff */
 171
 172         int transceiver;
 173         struct platform_device *pldev;
 174 };
 175
 176 /* Constants */
 177
 178 #define SMSC_IRCC2_DRIVER_NAME                  "smsc-ircc2"
 179
 180 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED        9600
 181 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER        1
 182 #define SMSC_IRCC2_C_NET_TIMEOUT                0
 183 #define SMSC_IRCC2_C_SIR_STOP                   0
 184
 185 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
 186
 187 /* Prototypes */
 188
 189 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
 190 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
 191 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
 192 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
 193 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
 194 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
 195 static int  smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
 196 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
 197 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
 198 static netdev_tx_t  smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
 199                                                   struct net_device *dev);
 200 static netdev_tx_t  smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
 201                                                   struct net_device *dev);
 202 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
 203 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
 204 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
 205 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
 206 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
 207 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
 208 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
 209 #if SMSC_IRCC2_C_SIR_STOP
 210 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
 211 #endif
 212 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
 213 static int  smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
 214 static int  smsc_ircc_net_open(struct net_device *dev);
 215 static int  smsc_ircc_net_close(struct net_device *dev);
 216 static int  smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 217 #if SMSC_IRCC2_C_NET_TIMEOUT
 218 static void smsc_ircc_timeout(struct net_device *dev);
 219 #endif
 220 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
 221 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
 222 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
 223 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
 224
 225 /* Probing */
 226 static int __init smsc_ircc_look_for_chips(void);
 227 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
 228 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
 229 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
 230 static int __init smsc_superio_fdc(unsigned short cfg_base);
 231 static int __init smsc_superio_lpc(unsigned short cfg_base);
 232 #ifdef CONFIG_PCI
 233 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
 234 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
 235 static void __init preconfigure_ali_port(struct pci_dev *dev,
 236                                          unsigned short port);
 237 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
 238 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
 239                                                     unsigned short ircc_fir,
 240                                                     unsigned short ircc_sir,
 241                                                     unsigned char ircc_dma,
 242                                                     unsigned char ircc_irq);
 243 #endif
 244
 245 /* Transceivers specific functions */
 246
 247 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
 248 static int  smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
 249 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
 250 static int  smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
 251 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
 252 static int  smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
 253
 254 /* Power Management */
 255
 256 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
 257 static int smsc_ircc_resume(struct platform_device *dev);
 258
 259 static struct platform_driver smsc_ircc_driver = {
 260         .suspend        = smsc_ircc_suspend,
 261         .resume         = smsc_ircc_resume,
 262         .driver         = {
 263                 .name   = SMSC_IRCC2_DRIVER_NAME,
 264         },
 265 };
 266
 267 /* Transceivers for SMSC-ircc */
 268
 269 static struct smsc_transceiver smsc_transceivers[] =
 270 {
 271         { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
 272         { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
 273         { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
 274         { NULL, NULL }
 275 };
 276 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
 277
 278 /*  SMC SuperIO chipsets definitions */
 279
 280 #define KEY55_1 0       /* SuperIO Configuration mode with Key <0x55> */
 281 #define KEY55_2 1       /* SuperIO Configuration mode with Key <0x55,0x55> */
 282 #define NoIRDA  2       /* SuperIO Chip has no IRDA Port */
 283 #define SIR     0       /* SuperIO Chip has only slow IRDA */
 284 #define FIR     4       /* SuperIO Chip has fast IRDA */
 285 #define SERx4   8       /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
 286
 287 static struct smsc_chip __initdata fdc_chips_flat[] =
 288 {
 289         /* Base address 0x3f0 or 0x370 */
 290         { "37C44",      KEY55_1|NoIRDA,         0x00, 0x00 }, /* This chip cannot be detected */
 291         { "37C665GT",   KEY55_2|NoIRDA,         0x65, 0x01 },
 292         { "37C665GT",   KEY55_2|NoIRDA,         0x66, 0x01 },
 293         { "37C669",     KEY55_2|SIR|SERx4,      0x03, 0x02 },
 294         { "37C669",     KEY55_2|SIR|SERx4,      0x04, 0x02 }, /* ID? */
 295         { "37C78",      KEY55_2|NoIRDA,         0x78, 0x00 },
 296         { "37N769",     KEY55_1|FIR|SERx4,      0x28, 0x00 },
 297         { "37N869",     KEY55_1|FIR|SERx4,      0x29, 0x00 },
 298         { NULL }
 299 };
 300
 301 static struct smsc_chip __initdata fdc_chips_paged[] =
 302 {
 303         /* Base address 0x3f0 or 0x370 */
 304         { "37B72X",     KEY55_1|SIR|SERx4,      0x4c, 0x00 },
 305         { "37B77X",     KEY55_1|SIR|SERx4,      0x43, 0x00 },
 306         { "37B78X",     KEY55_1|SIR|SERx4,      0x44, 0x00 },
 307         { "37B80X",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 308         { "37C67X",     KEY55_1|FIR|SERx4,      0x40, 0x00 },
 309         { "37C93X",     KEY55_2|SIR|SERx4,      0x02, 0x01 },
 310         { "37C93XAPM",  KEY55_1|SIR|SERx4,      0x30, 0x01 },
 311         { "37C93XFR",   KEY55_2|FIR|SERx4,      0x03, 0x01 },
 312         { "37M707",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 313         { "37M81X",     KEY55_1|SIR|SERx4,      0x4d, 0x00 },
 314         { "37N958FR",   KEY55_1|FIR|SERx4,      0x09, 0x04 },
 315         { "37N971",     KEY55_1|FIR|SERx4,      0x0a, 0x00 },
 316         { "37N972",     KEY55_1|FIR|SERx4,      0x0b, 0x00 },
 317         { NULL }
 318 };
 319
 320 static struct smsc_chip __initdata lpc_chips_flat[] =
 321 {
 322         /* Base address 0x2E or 0x4E */
 323         { "47N227",     KEY55_1|FIR|SERx4,      0x5a, 0x00 },
 324         { "47N227",     KEY55_1|FIR|SERx4,      0x7a, 0x00 },
 325         { "47N267",     KEY55_1|FIR|SERx4,      0x5e, 0x00 },
 326         { NULL }
 327 };
 328
 329 static struct smsc_chip __initdata lpc_chips_paged[] =
 330 {
 331         /* Base address 0x2E or 0x4E */
 332         { "47B27X",     KEY55_1|SIR|SERx4,      0x51, 0x00 },
 333         { "47B37X",     KEY55_1|SIR|SERx4,      0x52, 0x00 },
 334         { "47M10X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 335         { "47M120",     KEY55_1|NoIRDA|SERx4,   0x5c, 0x00 },
 336         { "47M13X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 337         { "47M14X",     KEY55_1|SIR|SERx4,      0x5f, 0x00 },
 338         { "47N252",     KEY55_1|FIR|SERx4,      0x0e, 0x00 },
 339         { "47S42X",     KEY55_1|SIR|SERx4,      0x57, 0x00 },
 340         { NULL }
 341 };
 342
 343 #define SMSCSIO_TYPE_FDC        1
 344 #define SMSCSIO_TYPE_LPC        2
 345 #define SMSCSIO_TYPE_FLAT       4
 346 #define SMSCSIO_TYPE_PAGED      8
 347
 348 static struct smsc_chip_address __initdata possible_addresses[] =
 349 {
 350         { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 351         { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 352         { 0xe0,  SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 353         { 0x2e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 354         { 0x4e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 355         { 0, 0 }
 356 };
 357
 358 /* Globals */
 359
 360 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
 361 static unsigned short dev_count;
 362
 363 static inline void register_bank(int iobase, int bank)
 364 {
 365         outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
 366                iobase + IRCC_MASTER);
 367 }
 368
 369 /* PNP hotplug support */
 370 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
 371         { .id = "SMCf010", .driver_data = 0 },
 372         /* and presumably others */
 373         { }
 374 };
 375 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
 376
 377 static int pnp_driver_registered;
 378
 379 #ifdef CONFIG_PNP
 380 static int __devinit smsc_ircc_pnp_probe(struct pnp_dev *dev,
 381                                       const struct pnp_device_id *dev_id)
 382 {
 383         unsigned int firbase, sirbase;
 384         u8 dma, irq;
 385
 386         if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
 387               pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
 388                 return -EINVAL;
 389
 390         sirbase = pnp_port_start(dev, 0);
 391         firbase = pnp_port_start(dev, 1);
 392         dma = pnp_dma(dev, 0);
 393         irq = pnp_irq(dev, 0);
 394
 395         if (smsc_ircc_open(firbase, sirbase, dma, irq))
 396                 return -ENODEV;
 397
 398         return 0;
 399 }
 400
 401 static struct pnp_driver smsc_ircc_pnp_driver = {
 402         .name           = "smsc-ircc2",
 403         .id_table       = smsc_ircc_pnp_table,
 404         .probe          = smsc_ircc_pnp_probe,
 405 };
 406 #else /* CONFIG_PNP */
 407 static struct pnp_driver smsc_ircc_pnp_driver;
 408 #endif
 409
 410 /*******************************************************************************
 411  *
 412  *
 413  * SMSC-ircc stuff
 414  *
 415  *
 416  *******************************************************************************/
 417
 418 static int __init smsc_ircc_legacy_probe(void)
 419 {
 420         int ret = 0;
 421
 422 #ifdef CONFIG_PCI
 423         if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
 424                 /* Ignore errors from preconfiguration */
 425                 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
 426         }
 427 #endif
 428
 429         if (ircc_fir > 0 && ircc_sir > 0) {
 430                 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
 431                 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
 432
 433                 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
 434                         ret = -ENODEV;
 435         } else {
 436                 ret = -ENODEV;
 437
 438                 /* try user provided configuration register base address */
 439                 if (ircc_cfg > 0) {
 440                         IRDA_MESSAGE(" Overriding configuration address "
 441                                      "0x%04x\n", ircc_cfg);
 442                         if (!smsc_superio_fdc(ircc_cfg))
 443                                 ret = 0;
 444                         if (!smsc_superio_lpc(ircc_cfg))
 445                                 ret = 0;
 446                 }
 447
 448                 if (smsc_ircc_look_for_chips() > 0)
 449                         ret = 0;
 450         }
 451         return ret;
 452 }
 453
 454 /*
 455  * Function smsc_ircc_init ()
 456  *
 457  *    Initialize chip. Just try to find out how many chips we are dealing with
 458  *    and where they are
 459  */
 460 static int __init smsc_ircc_init(void)
 461 {
 462         int ret;
 463
 464         IRDA_DEBUG(1, "%s\n", __func__);
 465
 466         ret = platform_driver_register(&smsc_ircc_driver);
 467         if (ret) {
 468                 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
 469                 return ret;
 470         }
 471
 472         dev_count = 0;
 473
 474         if (smsc_nopnp || !pnp_platform_devices ||
 475             ircc_cfg || ircc_fir || ircc_sir ||
 476             ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
 477                 ret = smsc_ircc_legacy_probe();
 478         } else {
 479                 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
 480                         pnp_driver_registered = 1;
 481         }
 482
 483         if (ret) {
 484                 if (pnp_driver_registered)
 485                         pnp_unregister_driver(&smsc_ircc_pnp_driver);
 486                 platform_driver_unregister(&smsc_ircc_driver);
 487         }
 488
 489         return ret;
 490 }
 491
 492 static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
 493                                             struct net_device *dev)
 494 {
 495         struct smsc_ircc_cb *self = netdev_priv(dev);
 496
 497         if (self->io.speed > 115200)
 498                 return  smsc_ircc_hard_xmit_fir(skb, dev);
 499         else
 500                 return  smsc_ircc_hard_xmit_sir(skb, dev);
 501 }
 502
 503 static const struct net_device_ops smsc_ircc_netdev_ops = {
 504         .ndo_open       = smsc_ircc_net_open,
 505         .ndo_stop       = smsc_ircc_net_close,
 506         .ndo_do_ioctl   = smsc_ircc_net_ioctl,
 507         .ndo_start_xmit = smsc_ircc_net_xmit,
 508 #if SMSC_IRCC2_C_NET_TIMEOUT
 509         .ndo_tx_timeout = smsc_ircc_timeout,
 510 #endif
 511 };
 512
 513 /*
 514  * Function smsc_ircc_open (firbase, sirbase, dma, irq)
 515  *
 516  *    Try to open driver instance
 517  *
 518  */
 519 static int __devinit smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
 520 {
 521         struct smsc_ircc_cb *self;
 522         struct net_device *dev;
 523         int err;
 524
 525         IRDA_DEBUG(1, "%s\n", __func__);
 526
 527         err = smsc_ircc_present(fir_base, sir_base);
 528         if (err)
 529                 goto err_out;
 530
 531         err = -ENOMEM;
 532         if (dev_count >= ARRAY_SIZE(dev_self)) {
 533                 IRDA_WARNING("%s(), too many devices!\n", __func__);
 534                 goto err_out1;
 535         }
 536
 537         /*
 538          *  Allocate new instance of the driver
 539          */
 540         dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
 541         if (!dev) {
 542                 IRDA_WARNING("%s() can't allocate net device\n", __func__);
 543                 goto err_out1;
 544         }
 545
 546 #if SMSC_IRCC2_C_NET_TIMEOUT
 547         dev->watchdog_timeo  = HZ * 2;  /* Allow enough time for speed change */
 548 #endif
 549         dev->netdev_ops = &smsc_ircc_netdev_ops;
 550
 551         self = netdev_priv(dev);
 552         self->netdev = dev;
 553
 554         /* Make ifconfig display some details */
 555         dev->base_addr = self->io.fir_base = fir_base;
 556         dev->irq = self->io.irq = irq;
 557
 558         /* Need to store self somewhere */
 559         dev_self[dev_count] = self;
 560         spin_lock_init(&self->lock);
 561
 562         self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
 563         self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
 564
 565         self->rx_buff.head =
 566                 dma_alloc_coherent(NULL, self->rx_buff.truesize,
 567                                    &self->rx_buff_dma, GFP_KERNEL);
 568         if (self->rx_buff.head == NULL) {
 569                 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
 570                            driver_name);
 571                 goto err_out2;
 572         }
 573
 574         self->tx_buff.head =
 575                 dma_alloc_coherent(NULL, self->tx_buff.truesize,
 576                                    &self->tx_buff_dma, GFP_KERNEL);
 577         if (self->tx_buff.head == NULL) {
 578                 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
 579                            driver_name);
 580                 goto err_out3;
 581         }
 582
 583         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 584         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 585
 586         self->rx_buff.in_frame = FALSE;
 587         self->rx_buff.state = OUTSIDE_FRAME;
 588         self->tx_buff.data = self->tx_buff.head;
 589         self->rx_buff.data = self->rx_buff.head;
 590
 591         smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
 592         smsc_ircc_setup_qos(self);
 593         smsc_ircc_init_chip(self);
 594
 595         if (ircc_transceiver > 0  &&
 596             ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
 597                 self->transceiver = ircc_transceiver;
 598         else
 599                 smsc_ircc_probe_transceiver(self);
 600
 601         err = register_netdev(self->netdev);
 602         if (err) {
 603                 IRDA_ERROR("%s, Network device registration failed!\n",
 604                            driver_name);
 605                 goto err_out4;
 606         }
 607
 608         self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
 609                                                       dev_count, NULL, 0);
 610         if (IS_ERR(self->pldev)) {
 611                 err = PTR_ERR(self->pldev);
 612                 goto err_out5;
 613         }
 614         platform_set_drvdata(self->pldev, self);
 615
 616         IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
 617         dev_count++;
 618
 619         return 0;
 620
 621  err_out5:
 622         unregister_netdev(self->netdev);
 623
 624  err_out4:
 625         dma_free_coherent(NULL, self->tx_buff.truesize,
 626                           self->tx_buff.head, self->tx_buff_dma);
 627  err_out3:
 628         dma_free_coherent(NULL, self->rx_buff.truesize,
 629                           self->rx_buff.head, self->rx_buff_dma);
 630  err_out2:
 631         free_netdev(self->netdev);
 632         dev_self[dev_count] = NULL;
 633  err_out1:
 634         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 635         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 636  err_out:
 637         return err;
 638 }
 639
 640 /*
 641  * Function smsc_ircc_present(fir_base, sir_base)
 642  *
 643  *    Check the smsc-ircc chip presence
 644  *
 645  */
 646 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
 647 {
 648         unsigned char low, high, chip, config, dma, irq, version;
 649
 650         if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
 651                             driver_name)) {
 652                 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
 653                              __func__, fir_base);
 654                 goto out1;
 655         }
 656
 657         if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
 658                             driver_name)) {
 659                 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
 660                              __func__, sir_base);
 661                 goto out2;
 662         }
 663
 664         register_bank(fir_base, 3);
 665
 666         high    = inb(fir_base + IRCC_ID_HIGH);
 667         low     = inb(fir_base + IRCC_ID_LOW);
 668         chip    = inb(fir_base + IRCC_CHIP_ID);
 669         version = inb(fir_base + IRCC_VERSION);
 670         config  = inb(fir_base + IRCC_INTERFACE);
 671         dma     = config & IRCC_INTERFACE_DMA_MASK;
 672         irq     = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 673
 674         if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
 675                 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
 676                              __func__, fir_base);
 677                 goto out3;
 678         }
 679         IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
 680                      "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
 681                      chip & 0x0f, version, fir_base, sir_base, dma, irq);
 682
 683         return 0;
 684
 685  out3:
 686         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 687  out2:
 688         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 689  out1:
 690         return -ENODEV;
 691 }
 692
 693 /*
 694  * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
 695  *
 696  *    Setup I/O
 697  *
 698  */
 699 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
 700                                unsigned int fir_base, unsigned int sir_base,
 701                                u8 dma, u8 irq)
 702 {
 703         unsigned char config, chip_dma, chip_irq;
 704
 705         register_bank(fir_base, 3);
 706         config = inb(fir_base + IRCC_INTERFACE);
 707         chip_dma = config & IRCC_INTERFACE_DMA_MASK;
 708         chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 709
 710         self->io.fir_base  = fir_base;
 711         self->io.sir_base  = sir_base;
 712         self->io.fir_ext   = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
 713         self->io.sir_ext   = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
 714         self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
 715         self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
 716
 717         if (irq != IRQ_INVAL) {
 718                 if (irq != chip_irq)
 719                         IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
 720                                      driver_name, chip_irq, irq);
 721                 self->io.irq = irq;
 722         } else
 723                 self->io.irq = chip_irq;
 724
 725         if (dma != DMA_INVAL) {
 726                 if (dma != chip_dma)
 727                         IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
 728                                      driver_name, chip_dma, dma);
 729                 self->io.dma = dma;
 730         } else
 731                 self->io.dma = chip_dma;
 732
 733 }
 734
 735 /*
 736  * Function smsc_ircc_setup_qos(self)
 737  *
 738  *    Setup qos
 739  *
 740  */
 741 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
 742 {
 743         /* Initialize QoS for this device */
 744         irda_init_max_qos_capabilies(&self->qos);
 745
 746         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 747                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
 748
 749         self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
 750         self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
 751         irda_qos_bits_to_value(&self->qos);
 752 }
 753
 754 /*
 755  * Function smsc_ircc_init_chip(self)
 756  *
 757  *    Init chip
 758  *
 759  */
 760 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
 761 {
 762         int iobase = self->io.fir_base;
 763
 764         register_bank(iobase, 0);
 765         outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
 766         outb(0x00, iobase + IRCC_MASTER);
 767
 768         register_bank(iobase, 1);
 769         outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
 770              iobase + IRCC_SCE_CFGA);
 771
 772 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
 773         outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
 774              iobase + IRCC_SCE_CFGB);
 775 #else
 776         outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
 777              iobase + IRCC_SCE_CFGB);
 778 #endif
 779         (void) inb(iobase + IRCC_FIFO_THRESHOLD);
 780         outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
 781
 782         register_bank(iobase, 4);
 783         outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
 784
 785         register_bank(iobase, 0);
 786         outb(0, iobase + IRCC_LCR_A);
 787
 788         smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
 789
 790         /* Power on device */
 791         outb(0x00, iobase + IRCC_MASTER);
 792 }
 793
 794 /*
 795  * Function smsc_ircc_net_ioctl (dev, rq, cmd)
 796  *
 797  *    Process IOCTL commands for this device
 798  *
 799  */
 800 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 801 {
 802         struct if_irda_req *irq = (struct if_irda_req *) rq;
 803         struct smsc_ircc_cb *self;
 804         unsigned long flags;
 805         int ret = 0;
 806
 807         IRDA_ASSERT(dev != NULL, return -1;);
 808
 809         self = netdev_priv(dev);
 810
 811         IRDA_ASSERT(self != NULL, return -1;);
 812
 813         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
 814
 815         switch (cmd) {
 816         case SIOCSBANDWIDTH: /* Set bandwidth */
 817                 if (!capable(CAP_NET_ADMIN))
 818                         ret = -EPERM;
 819                 else {
 820                         /* Make sure we are the only one touching
 821                          * self->io.speed and the hardware - Jean II */
 822                         spin_lock_irqsave(&self->lock, flags);
 823                         smsc_ircc_change_speed(self, irq->ifr_baudrate);
 824                         spin_unlock_irqrestore(&self->lock, flags);
 825                 }
 826                 break;
 827         case SIOCSMEDIABUSY: /* Set media busy */
 828                 if (!capable(CAP_NET_ADMIN)) {
 829                         ret = -EPERM;
 830                         break;
 831                 }
 832
 833                 irda_device_set_media_busy(self->netdev, TRUE);
 834                 break;
 835         case SIOCGRECEIVING: /* Check if we are receiving right now */
 836                 irq->ifr_receiving = smsc_ircc_is_receiving(self);
 837                 break;
 838         #if 0
 839         case SIOCSDTRRTS:
 840                 if (!capable(CAP_NET_ADMIN)) {
 841                         ret = -EPERM;
 842                         break;
 843                 }
 844                 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
 845                 break;
 846         #endif
 847         default:
 848                 ret = -EOPNOTSUPP;
 849         }
 850
 851         return ret;
 852 }
 853
 854 #if SMSC_IRCC2_C_NET_TIMEOUT
 855 /*
 856  * Function smsc_ircc_timeout (struct net_device *dev)
 857  *
 858  *    The networking timeout management.
 859  *
 860  */
 861
 862 static void smsc_ircc_timeout(struct net_device *dev)
 863 {
 864         struct smsc_ircc_cb *self = netdev_priv(dev);
 865         unsigned long flags;
 866
 867         IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
 868                      dev->name, self->io.speed);
 869         spin_lock_irqsave(&self->lock, flags);
 870         smsc_ircc_sir_start(self);
 871         smsc_ircc_change_speed(self, self->io.speed);
 872         dev->trans_start = jiffies; /* prevent tx timeout */
 873         netif_wake_queue(dev);
 874         spin_unlock_irqrestore(&self->lock, flags);
 875 }
 876 #endif
 877
 878 /*
 879  * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
 880  *
 881  *    Transmits the current frame until FIFO is full, then
 882  *    waits until the next transmit interrupt, and continues until the
 883  *    frame is transmitted.
 884  */
 885 static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
 886                                                  struct net_device *dev)
 887 {
 888         struct smsc_ircc_cb *self;
 889         unsigned long flags;
 890         s32 speed;
 891
 892         IRDA_DEBUG(1, "%s\n", __func__);
 893
 894         IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
 895
 896         self = netdev_priv(dev);
 897         IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
 898
 899         netif_stop_queue(dev);
 900
 901         /* Make sure test of self->io.speed & speed change are atomic */
 902         spin_lock_irqsave(&self->lock, flags);
 903
 904         /* Check if we need to change the speed */
 905         speed = irda_get_next_speed(skb);
 906         if (speed != self->io.speed && speed != -1) {
 907                 /* Check for empty frame */
 908                 if (!skb->len) {
 909                         /*
 910                          * We send frames one by one in SIR mode (no
 911                          * pipelining), so at this point, if we were sending
 912                          * a previous frame, we just received the interrupt
 913                          * telling us it is finished (UART_IIR_THRI).
 914                          * Therefore, waiting for the transmitter to really
 915                          * finish draining the fifo won't take too long.
 916                          * And the interrupt handler is not expected to run.
 917                          * - Jean II */
 918                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
 919                         smsc_ircc_change_speed(self, speed);
 920                         spin_unlock_irqrestore(&self->lock, flags);
 921                         dev_kfree_skb(skb);
 922                         return NETDEV_TX_OK;
 923                 }
 924                 self->new_speed = speed;
 925         }
 926
 927         /* Init tx buffer */
 928         self->tx_buff.data = self->tx_buff.head;
 929
 930         /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
 931         self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 932                                            self->tx_buff.truesize);
 933
 934         dev->stats.tx_bytes += self->tx_buff.len;
 935
 936         /* Turn on transmit finished interrupt. Will fire immediately!  */
 937         outb(UART_IER_THRI, self->io.sir_base + UART_IER);
 938
 939         spin_unlock_irqrestore(&self->lock, flags);
 940
 941         dev_kfree_skb(skb);
 942
 943         return NETDEV_TX_OK;
 944 }
 945
 946 /*
 947  * Function smsc_ircc_set_fir_speed (self, baud)
 948  *
 949  *    Change the speed of the device
 950  *
 951  */
 952 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
 953 {
 954         int fir_base, ir_mode, ctrl, fast;
 955
 956         IRDA_ASSERT(self != NULL, return;);
 957         fir_base = self->io.fir_base;
 958
 959         self->io.speed = speed;
 960
 961         switch (speed) {
 962         default:
 963         case 576000:
 964                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 965                 ctrl = IRCC_CRC;
 966                 fast = 0;
 967                 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
 968                 break;
 969         case 1152000:
 970                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 971                 ctrl = IRCC_1152 | IRCC_CRC;
 972                 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
 973                 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
 974                            __func__);
 975                 break;
 976         case 4000000:
 977                 ir_mode = IRCC_CFGA_IRDA_4PPM;
 978                 ctrl = IRCC_CRC;
 979                 fast = IRCC_LCR_A_FAST;
 980                 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
 981                            __func__);
 982                 break;
 983         }
 984         #if 0
 985         Now in tranceiver!
 986         /* This causes an interrupt */
 987         register_bank(fir_base, 0);
 988         outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast, fir_base + IRCC_LCR_A);
 989         #endif
 990
 991         register_bank(fir_base, 1);
 992         outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
 993
 994         register_bank(fir_base, 4);
 995         outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
 996 }
 997
 998 /*
 999  * Function smsc_ircc_fir_start(self)
1000  *
1001  *    Change the speed of the device
1002  *
1003  */
1004 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
1005 {
1006         struct net_device *dev;
1007         int fir_base;
1008
1009         IRDA_DEBUG(1, "%s\n", __func__);
1010
1011         IRDA_ASSERT(self != NULL, return;);
1012         dev = self->netdev;
1013         IRDA_ASSERT(dev != NULL, return;);
1014
1015         fir_base = self->io.fir_base;
1016
1017         /* Reset everything */
1018
1019         /* Clear FIFO */
1020         outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1021
1022         /* Enable interrupt */
1023         /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1024
1025         register_bank(fir_base, 1);
1026
1027         /* Select the TX/RX interface */
1028 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1029         outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1030              fir_base + IRCC_SCE_CFGB);
1031 #else
1032         outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1033              fir_base + IRCC_SCE_CFGB);
1034 #endif
1035         (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1036
1037         /* Enable SCE interrupts */
1038         outb(0, fir_base + IRCC_MASTER);
1039         register_bank(fir_base, 0);
1040         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1041         outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1042 }
1043
1044 /*
1045  * Function smsc_ircc_fir_stop(self, baud)
1046  *
1047  *    Change the speed of the device
1048  *
1049  */
1050 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1051 {
1052         int fir_base;
1053
1054         IRDA_DEBUG(1, "%s\n", __func__);
1055
1056         IRDA_ASSERT(self != NULL, return;);
1057
1058         fir_base = self->io.fir_base;
1059         register_bank(fir_base, 0);
1060         /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1061         outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1062 }
1063
1064
1065 /*
1066  * Function smsc_ircc_change_speed(self, baud)
1067  *
1068  *    Change the speed of the device
1069  *
1070  * This function *must* be called with spinlock held, because it may
1071  * be called from the irq handler. - Jean II
1072  */
1073 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1074 {
1075         struct net_device *dev;
1076         int last_speed_was_sir;
1077
1078         IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1079
1080         IRDA_ASSERT(self != NULL, return;);
1081         dev = self->netdev;
1082
1083         last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1084
1085         #if 0
1086         /* Temp Hack */
1087         speed= 1152000;
1088         self->io.speed = speed;
1089         last_speed_was_sir = 0;
1090         smsc_ircc_fir_start(self);
1091         #endif
1092
1093         if (self->io.speed == 0)
1094                 smsc_ircc_sir_start(self);
1095
1096         #if 0
1097         if (!last_speed_was_sir) speed = self->io.speed;
1098         #endif
1099
1100         if (self->io.speed != speed)
1101                 smsc_ircc_set_transceiver_for_speed(self, speed);
1102
1103         self->io.speed = speed;
1104
1105         if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1106                 if (!last_speed_was_sir) {
1107                         smsc_ircc_fir_stop(self);
1108                         smsc_ircc_sir_start(self);
1109                 }
1110                 smsc_ircc_set_sir_speed(self, speed);
1111         } else {
1112                 if (last_speed_was_sir) {
1113                         #if SMSC_IRCC2_C_SIR_STOP
1114                         smsc_ircc_sir_stop(self);
1115                         #endif
1116                         smsc_ircc_fir_start(self);
1117                 }
1118                 smsc_ircc_set_fir_speed(self, speed);
1119
1120                 #if 0
1121                 self->tx_buff.len = 10;
1122                 self->tx_buff.data = self->tx_buff.head;
1123
1124                 smsc_ircc_dma_xmit(self, 4000);
1125                 #endif
1126                 /* Be ready for incoming frames */
1127                 smsc_ircc_dma_receive(self);
1128         }
1129
1130         netif_wake_queue(dev);
1131 }
1132
1133 /*
1134  * Function smsc_ircc_set_sir_speed (self, speed)
1135  *
1136  *    Set speed of IrDA port to specified baudrate
1137  *
1138  */
1139 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1140 {
1141         int iobase;
1142         int fcr;    /* FIFO control reg */
1143         int lcr;    /* Line control reg */
1144         int divisor;
1145
1146         IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1147
1148         IRDA_ASSERT(self != NULL, return;);
1149         iobase = self->io.sir_base;
1150
1151         /* Update accounting for new speed */
1152         self->io.speed = speed;
1153
1154         /* Turn off interrupts */
1155         outb(0, iobase + UART_IER);
1156
1157         divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1158
1159         fcr = UART_FCR_ENABLE_FIFO;
1160
1161         /*
1162          * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1163          * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1164          * about this timeout since it will always be fast enough.
1165          */
1166         fcr |= self->io.speed < 38400 ?
1167                 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1168
1169         /* IrDA ports use 8N1 */
1170         lcr = UART_LCR_WLEN8;
1171
1172         outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1173         outb(divisor & 0xff,      iobase + UART_DLL); /* Set speed */
1174         outb(divisor >> 8,        iobase + UART_DLM);
1175         outb(lcr,                 iobase + UART_LCR); /* Set 8N1 */
1176         outb(fcr,                 iobase + UART_FCR); /* Enable FIFO's */
1177
1178         /* Turn on interrups */
1179         outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1180
1181         IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1182 }
1183
1184
1185 /*
1186  * Function smsc_ircc_hard_xmit_fir (skb, dev)
1187  *
1188  *    Transmit the frame!
1189  *
1190  */
1191 static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1192                                                  struct net_device *dev)
1193 {
1194         struct smsc_ircc_cb *self;
1195         unsigned long flags;
1196         s32 speed;
1197         int mtt;
1198
1199         IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
1200         self = netdev_priv(dev);
1201         IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1202
1203         netif_stop_queue(dev);
1204
1205         /* Make sure test of self->io.speed & speed change are atomic */
1206         spin_lock_irqsave(&self->lock, flags);
1207
1208         /* Check if we need to change the speed after this frame */
1209         speed = irda_get_next_speed(skb);
1210         if (speed != self->io.speed && speed != -1) {
1211                 /* Check for empty frame */
1212                 if (!skb->len) {
1213                         /* Note : you should make sure that speed changes
1214                          * are not going to corrupt any outgoing frame.
1215                          * Look at nsc-ircc for the gory details - Jean II */
1216                         smsc_ircc_change_speed(self, speed);
1217                         spin_unlock_irqrestore(&self->lock, flags);
1218                         dev_kfree_skb(skb);
1219                         return NETDEV_TX_OK;
1220                 }
1221
1222                 self->new_speed = speed;
1223         }
1224
1225         skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1226
1227         self->tx_buff.len = skb->len;
1228         self->tx_buff.data = self->tx_buff.head;
1229
1230         mtt = irda_get_mtt(skb);
1231         if (mtt) {
1232                 int bofs;
1233
1234                 /*
1235                  * Compute how many BOFs (STA or PA's) we need to waste the
1236                  * min turn time given the speed of the link.
1237                  */
1238                 bofs = mtt * (self->io.speed / 1000) / 8000;
1239                 if (bofs > 4095)
1240                         bofs = 4095;
1241
1242                 smsc_ircc_dma_xmit(self, bofs);
1243         } else {
1244                 /* Transmit frame */
1245                 smsc_ircc_dma_xmit(self, 0);
1246         }
1247
1248         spin_unlock_irqrestore(&self->lock, flags);
1249         dev_kfree_skb(skb);
1250
1251         return NETDEV_TX_OK;
1252 }
1253
1254 /*
1255  * Function smsc_ircc_dma_xmit (self, bofs)
1256  *
1257  *    Transmit data using DMA
1258  *
1259  */
1260 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1261 {
1262         int iobase = self->io.fir_base;
1263         u8 ctrl;
1264
1265         IRDA_DEBUG(3, "%s\n", __func__);
1266 #if 1
1267         /* Disable Rx */
1268         register_bank(iobase, 0);
1269         outb(0x00, iobase + IRCC_LCR_B);
1270 #endif
1271         register_bank(iobase, 1);
1272         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1273              iobase + IRCC_SCE_CFGB);
1274
1275         self->io.direction = IO_XMIT;
1276
1277         /* Set BOF additional count for generating the min turn time */
1278         register_bank(iobase, 4);
1279         outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1280         ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1281         outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1282
1283         /* Set max Tx frame size */
1284         outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1285         outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1286
1287         /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1288
1289         /* Enable burst mode chip Tx DMA */
1290         register_bank(iobase, 1);
1291         outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1292              IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1293
1294         /* Setup DMA controller (must be done after enabling chip DMA) */
1295         irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1296                        DMA_TX_MODE);
1297
1298         /* Enable interrupt */
1299
1300         register_bank(iobase, 0);
1301         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1302         outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1303
1304         /* Enable transmit */
1305         outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1306 }
1307
1308 /*
1309  * Function smsc_ircc_dma_xmit_complete (self)
1310  *
1311  *    The transfer of a frame in finished. This function will only be called
1312  *    by the interrupt handler
1313  *
1314  */
1315 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1316 {
1317         int iobase = self->io.fir_base;
1318
1319         IRDA_DEBUG(3, "%s\n", __func__);
1320 #if 0
1321         /* Disable Tx */
1322         register_bank(iobase, 0);
1323         outb(0x00, iobase + IRCC_LCR_B);
1324 #endif
1325         register_bank(iobase, 1);
1326         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1327              iobase + IRCC_SCE_CFGB);
1328
1329         /* Check for underrun! */
1330         register_bank(iobase, 0);
1331         if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1332                 self->netdev->stats.tx_errors++;
1333                 self->netdev->stats.tx_fifo_errors++;
1334
1335                 /* Reset error condition */
1336                 register_bank(iobase, 0);
1337                 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1338                 outb(0x00, iobase + IRCC_MASTER);
1339         } else {
1340                 self->netdev->stats.tx_packets++;
1341                 self->netdev->stats.tx_bytes += self->tx_buff.len;
1342         }
1343
1344         /* Check if it's time to change the speed */
1345         if (self->new_speed) {
1346                 smsc_ircc_change_speed(self, self->new_speed);
1347                 self->new_speed = 0;
1348         }
1349
1350         netif_wake_queue(self->netdev);
1351 }
1352
1353 /*
1354  * Function smsc_ircc_dma_receive(self)
1355  *
1356  *    Get ready for receiving a frame. The device will initiate a DMA
1357  *    if it starts to receive a frame.
1358  *
1359  */
1360 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1361 {
1362         int iobase = self->io.fir_base;
1363 #if 0
1364         /* Turn off chip DMA */
1365         register_bank(iobase, 1);
1366         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1367              iobase + IRCC_SCE_CFGB);
1368 #endif
1369
1370         /* Disable Tx */
1371         register_bank(iobase, 0);
1372         outb(0x00, iobase + IRCC_LCR_B);
1373
1374         /* Turn off chip DMA */
1375         register_bank(iobase, 1);
1376         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1377              iobase + IRCC_SCE_CFGB);
1378
1379         self->io.direction = IO_RECV;
1380         self->rx_buff.data = self->rx_buff.head;
1381
1382         /* Set max Rx frame size */
1383         register_bank(iobase, 4);
1384         outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1385         outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1386
1387         /* Setup DMA controller */
1388         irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1389                        DMA_RX_MODE);
1390
1391         /* Enable burst mode chip Rx DMA */
1392         register_bank(iobase, 1);
1393         outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1394              IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1395
1396         /* Enable interrupt */
1397         register_bank(iobase, 0);
1398         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1399         outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1400
1401         /* Enable receiver */
1402         register_bank(iobase, 0);
1403         outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1404              iobase + IRCC_LCR_B);
1405
1406         return 0;
1407 }
1408
1409 /*
1410  * Function smsc_ircc_dma_receive_complete(self)
1411  *
1412  *    Finished with receiving frames
1413  *
1414  */
1415 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1416 {
1417         struct sk_buff *skb;
1418         int len, msgcnt, lsr;
1419         int iobase = self->io.fir_base;
1420
1421         register_bank(iobase, 0);
1422
1423         IRDA_DEBUG(3, "%s\n", __func__);
1424 #if 0
1425         /* Disable Rx */
1426         register_bank(iobase, 0);
1427         outb(0x00, iobase + IRCC_LCR_B);
1428 #endif
1429         register_bank(iobase, 0);
1430         outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1431         lsr= inb(iobase + IRCC_LSR);
1432         msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1433
1434         IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1435                    get_dma_residue(self->io.dma));
1436
1437         len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1438
1439         /* Look for errors */
1440         if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1441                 self->netdev->stats.rx_errors++;
1442                 if (lsr & IRCC_LSR_FRAME_ERROR)
1443                         self->netdev->stats.rx_frame_errors++;
1444                 if (lsr & IRCC_LSR_CRC_ERROR)
1445                         self->netdev->stats.rx_crc_errors++;
1446                 if (lsr & IRCC_LSR_SIZE_ERROR)
1447                         self->netdev->stats.rx_length_errors++;
1448                 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1449                         self->netdev->stats.rx_length_errors++;
1450                 return;
1451         }
1452
1453         /* Remove CRC */
1454         len -= self->io.speed < 4000000 ? 2 : 4;
1455
1456         if (len < 2 || len > 2050) {
1457                 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1458                 return;
1459         }
1460         IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1461
1462         skb = dev_alloc_skb(len + 1);
1463         if (!skb) {
1464                 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1465                              __func__);
1466                 return;
1467         }
1468         /* Make sure IP header gets aligned */
1469         skb_reserve(skb, 1);
1470
1471         memcpy(skb_put(skb, len), self->rx_buff.data, len);
1472         self->netdev->stats.rx_packets++;
1473         self->netdev->stats.rx_bytes += len;
1474
1475         skb->dev = self->netdev;
1476         skb_reset_mac_header(skb);
1477         skb->protocol = htons(ETH_P_IRDA);
1478         netif_rx(skb);
1479 }
1480
1481 /*
1482  * Function smsc_ircc_sir_receive (self)
1483  *
1484  *    Receive one frame from the infrared port
1485  *
1486  */
1487 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1488 {
1489         int boguscount = 0;
1490         int iobase;
1491
1492         IRDA_ASSERT(self != NULL, return;);
1493
1494         iobase = self->io.sir_base;
1495
1496         /*
1497          * Receive all characters in Rx FIFO, unwrap and unstuff them.
1498          * async_unwrap_char will deliver all found frames
1499          */
1500         do {
1501                 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
1502                                   inb(iobase + UART_RX));
1503
1504                 /* Make sure we don't stay here to long */
1505                 if (boguscount++ > 32) {
1506                         IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1507                         break;
1508                 }
1509         } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1510 }
1511
1512
1513 /*
1514  * Function smsc_ircc_interrupt (irq, dev_id, regs)
1515  *
1516  *    An interrupt from the chip has arrived. Time to do some work
1517  *
1518  */
1519 static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1520 {
1521         struct net_device *dev = dev_id;
1522         struct smsc_ircc_cb *self = netdev_priv(dev);
1523         int iobase, iir, lcra, lsr;
1524         irqreturn_t ret = IRQ_NONE;
1525
1526         /* Serialise the interrupt handler in various CPUs, stop Tx path */
1527         spin_lock(&self->lock);
1528
1529         /* Check if we should use the SIR interrupt handler */
1530         if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1531                 ret = smsc_ircc_interrupt_sir(dev);
1532                 goto irq_ret_unlock;
1533         }
1534
1535         iobase = self->io.fir_base;
1536
1537         register_bank(iobase, 0);
1538         iir = inb(iobase + IRCC_IIR);
1539         if (iir == 0)
1540                 goto irq_ret_unlock;
1541         ret = IRQ_HANDLED;
1542
1543         /* Disable interrupts */
1544         outb(0, iobase + IRCC_IER);
1545         lcra = inb(iobase + IRCC_LCR_A);
1546         lsr = inb(iobase + IRCC_LSR);
1547
1548         IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1549
1550         if (iir & IRCC_IIR_EOM) {
1551                 if (self->io.direction == IO_RECV)
1552                         smsc_ircc_dma_receive_complete(self);
1553                 else
1554                         smsc_ircc_dma_xmit_complete(self);
1555
1556                 smsc_ircc_dma_receive(self);
1557         }
1558
1559         if (iir & IRCC_IIR_ACTIVE_FRAME) {
1560                 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1561         }
1562
1563         /* Enable interrupts again */
1564
1565         register_bank(iobase, 0);
1566         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1567
1568  irq_ret_unlock:
1569         spin_unlock(&self->lock);
1570
1571         return ret;
1572 }
1573
1574 /*
1575  * Function irport_interrupt_sir (irq, dev_id)
1576  *
1577  *    Interrupt handler for SIR modes
1578  */
1579 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1580 {
1581         struct smsc_ircc_cb *self = netdev_priv(dev);
1582         int boguscount = 0;
1583         int iobase;
1584         int iir, lsr;
1585
1586         /* Already locked coming here in smsc_ircc_interrupt() */
1587         /*spin_lock(&self->lock);*/
1588
1589         iobase = self->io.sir_base;
1590
1591         iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1592         if (iir == 0)
1593                 return IRQ_NONE;
1594         while (iir) {
1595                 /* Clear interrupt */
1596                 lsr = inb(iobase + UART_LSR);
1597
1598                 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1599                             __func__, iir, lsr, iobase);
1600
1601                 switch (iir) {
1602                 case UART_IIR_RLSI:
1603                         IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1604                         break;
1605                 case UART_IIR_RDI:
1606                         /* Receive interrupt */
1607                         smsc_ircc_sir_receive(self);
1608                         break;
1609                 case UART_IIR_THRI:
1610                         if (lsr & UART_LSR_THRE)
1611                                 /* Transmitter ready for data */
1612                                 smsc_ircc_sir_write_wakeup(self);
1613                         break;
1614                 default:
1615                         IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1616                                    __func__, iir);
1617                         break;
1618                 }
1619
1620                 /* Make sure we don't stay here to long */
1621                 if (boguscount++ > 100)
1622                         break;
1623
1624                 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1625         }
1626         /*spin_unlock(&self->lock);*/
1627         return IRQ_HANDLED;
1628 }
1629
1630
1631 #if 0 /* unused */
1632 /*
1633  * Function ircc_is_receiving (self)
1634  *
1635  *    Return TRUE is we are currently receiving a frame
1636  *
1637  */
1638 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1639 {
1640         int status = FALSE;
1641         /* int iobase; */
1642
1643         IRDA_DEBUG(1, "%s\n", __func__);
1644
1645         IRDA_ASSERT(self != NULL, return FALSE;);
1646
1647         IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1648                    get_dma_residue(self->io.dma));
1649
1650         status = (self->rx_buff.state != OUTSIDE_FRAME);
1651
1652         return status;
1653 }
1654 #endif /* unused */
1655
1656 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1657 {
1658         int error;
1659
1660         error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1661                             self->netdev->name, self->netdev);
1662         if (error)
1663                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1664                            __func__, self->io.irq, error);
1665
1666         return error;
1667 }
1668
1669 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1670 {
1671         unsigned long flags;
1672
1673         spin_lock_irqsave(&self->lock, flags);
1674
1675         self->io.speed = 0;
1676         smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1677
1678         spin_unlock_irqrestore(&self->lock, flags);
1679 }
1680
1681 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1682 {
1683         int iobase = self->io.fir_base;
1684         unsigned long flags;
1685
1686         spin_lock_irqsave(&self->lock, flags);
1687
1688         register_bank(iobase, 0);
1689         outb(0, iobase + IRCC_IER);
1690         outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1691         outb(0x00, iobase + IRCC_MASTER);
1692
1693         spin_unlock_irqrestore(&self->lock, flags);
1694 }
1695
1696
1697 /*
1698  * Function smsc_ircc_net_open (dev)
1699  *
1700  *    Start the device
1701  *
1702  */
1703 static int smsc_ircc_net_open(struct net_device *dev)
1704 {
1705         struct smsc_ircc_cb *self;
1706         char hwname[16];
1707
1708         IRDA_DEBUG(1, "%s\n", __func__);
1709
1710         IRDA_ASSERT(dev != NULL, return -1;);
1711         self = netdev_priv(dev);
1712         IRDA_ASSERT(self != NULL, return 0;);
1713
1714         if (self->io.suspended) {
1715                 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
1716                 return -EAGAIN;
1717         }
1718
1719         if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1720                         (void *) dev)) {
1721                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1722                            __func__, self->io.irq);
1723                 return -EAGAIN;
1724         }
1725
1726         smsc_ircc_start_interrupts(self);
1727
1728         /* Give self a hardware name */
1729         /* It would be cool to offer the chip revision here - Jean II */
1730         sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1731
1732         /*
1733          * Open new IrLAP layer instance, now that everything should be
1734          * initialized properly
1735          */
1736         self->irlap = irlap_open(dev, &self->qos, hwname);
1737
1738         /*
1739          * Always allocate the DMA channel after the IRQ,
1740          * and clean up on failure.
1741          */
1742         if (request_dma(self->io.dma, dev->name)) {
1743                 smsc_ircc_net_close(dev);
1744
1745                 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1746                              __func__, self->io.dma);
1747                 return -EAGAIN;
1748         }
1749
1750         netif_start_queue(dev);
1751
1752         return 0;
1753 }
1754
1755 /*
1756  * Function smsc_ircc_net_close (dev)
1757  *
1758  *    Stop the device
1759  *
1760  */
1761 static int smsc_ircc_net_close(struct net_device *dev)
1762 {
1763         struct smsc_ircc_cb *self;
1764
1765         IRDA_DEBUG(1, "%s\n", __func__);
1766
1767         IRDA_ASSERT(dev != NULL, return -1;);
1768         self = netdev_priv(dev);
1769         IRDA_ASSERT(self != NULL, return 0;);
1770
1771         /* Stop device */
1772         netif_stop_queue(dev);
1773
1774         /* Stop and remove instance of IrLAP */
1775         if (self->irlap)
1776                 irlap_close(self->irlap);
1777         self->irlap = NULL;
1778
1779         smsc_ircc_stop_interrupts(self);
1780
1781         /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1782         if (!self->io.suspended)
1783                 free_irq(self->io.irq, dev);
1784
1785         disable_dma(self->io.dma);
1786         free_dma(self->io.dma);
1787
1788         return 0;
1789 }
1790
1791 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1792 {
1793         struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1794
1795         if (!self->io.suspended) {
1796                 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1797
1798                 rtnl_lock();
1799                 if (netif_running(self->netdev)) {
1800                         netif_device_detach(self->netdev);
1801                         smsc_ircc_stop_interrupts(self);
1802                         free_irq(self->io.irq, self->netdev);
1803                         disable_dma(self->io.dma);
1804                 }
1805                 self->io.suspended = 1;
1806                 rtnl_unlock();
1807         }
1808
1809         return 0;
1810 }
1811
1812 static int smsc_ircc_resume(struct platform_device *dev)
1813 {
1814         struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1815
1816         if (self->io.suspended) {
1817                 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1818
1819                 rtnl_lock();
1820                 smsc_ircc_init_chip(self);
1821                 if (netif_running(self->netdev)) {
1822                         if (smsc_ircc_request_irq(self)) {
1823                                 /*
1824                                  * Don't fail resume process, just kill this
1825                                  * network interface
1826                                  */
1827                                 unregister_netdevice(self->netdev);
1828                         } else {
1829                                 enable_dma(self->io.dma);
1830                                 smsc_ircc_start_interrupts(self);
1831                                 netif_device_attach(self->netdev);
1832                         }
1833                 }
1834                 self->io.suspended = 0;
1835                 rtnl_unlock();
1836         }
1837         return 0;
1838 }
1839
1840 /*
1841  * Function smsc_ircc_close (self)
1842  *
1843  *    Close driver instance
1844  *
1845  */
1846 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1847 {
1848         IRDA_DEBUG(1, "%s\n", __func__);
1849
1850         IRDA_ASSERT(self != NULL, return -1;);
1851
1852         platform_device_unregister(self->pldev);
1853
1854         /* Remove netdevice */
1855         unregister_netdev(self->netdev);
1856
1857         smsc_ircc_stop_interrupts(self);
1858
1859         /* Release the PORTS that this driver is using */
1860         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n",  __func__,
1861                    self->io.fir_base);
1862
1863         release_region(self->io.fir_base, self->io.fir_ext);
1864
1865         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1866                    self->io.sir_base);
1867
1868         release_region(self->io.sir_base, self->io.sir_ext);
1869
1870         if (self->tx_buff.head)
1871                 dma_free_coherent(NULL, self->tx_buff.truesize,
1872                                   self->tx_buff.head, self->tx_buff_dma);
1873
1874         if (self->rx_buff.head)
1875                 dma_free_coherent(NULL, self->rx_buff.truesize,
1876                                   self->rx_buff.head, self->rx_buff_dma);
1877
1878         free_netdev(self->netdev);
1879
1880         return 0;
1881 }
1882
1883 static void __exit smsc_ircc_cleanup(void)
1884 {
1885         int i;
1886
1887         IRDA_DEBUG(1, "%s\n", __func__);
1888
1889         for (i = 0; i < 2; i++) {
1890                 if (dev_self[i])
1891                         smsc_ircc_close(dev_self[i]);
1892         }
1893
1894         if (pnp_driver_registered)
1895                 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1896
1897         platform_driver_unregister(&smsc_ircc_driver);
1898 }
1899
1900 /*
1901  *      Start SIR operations
1902  *
1903  * This function *must* be called with spinlock held, because it may
1904  * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1905  */
1906 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1907 {
1908         struct net_device *dev;
1909         int fir_base, sir_base;
1910
1911         IRDA_DEBUG(3, "%s\n", __func__);
1912
1913         IRDA_ASSERT(self != NULL, return;);
1914         dev = self->netdev;
1915         IRDA_ASSERT(dev != NULL, return;);
1916
1917         fir_base = self->io.fir_base;
1918         sir_base = self->io.sir_base;
1919
1920         /* Reset everything */
1921         outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1922
1923         #if SMSC_IRCC2_C_SIR_STOP
1924         /*smsc_ircc_sir_stop(self);*/
1925         #endif
1926
1927         register_bank(fir_base, 1);
1928         outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1929
1930         /* Initialize UART */
1931         outb(UART_LCR_WLEN8, sir_base + UART_LCR);  /* Reset DLAB */
1932         outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1933
1934         /* Turn on interrups */
1935         outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1936
1937         IRDA_DEBUG(3, "%s() - exit\n", __func__);
1938
1939         outb(0x00, fir_base + IRCC_MASTER);
1940 }
1941
1942 #if SMSC_IRCC2_C_SIR_STOP
1943 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1944 {
1945         int iobase;
1946
1947         IRDA_DEBUG(3, "%s\n", __func__);
1948         iobase = self->io.sir_base;
1949
1950         /* Reset UART */
1951         outb(0, iobase + UART_MCR);
1952
1953         /* Turn off interrupts */
1954         outb(0, iobase + UART_IER);
1955 }
1956 #endif
1957
1958 /*
1959  * Function smsc_sir_write_wakeup (self)
1960  *
1961  *    Called by the SIR interrupt handler when there's room for more data.
1962  *    If we have more packets to send, we send them here.
1963  *
1964  */
1965 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1966 {
1967         int actual = 0;
1968         int iobase;
1969         int fcr;
1970
1971         IRDA_ASSERT(self != NULL, return;);
1972
1973         IRDA_DEBUG(4, "%s\n", __func__);
1974
1975         iobase = self->io.sir_base;
1976
1977         /* Finished with frame?  */
1978         if (self->tx_buff.len > 0)  {
1979                 /* Write data left in transmit buffer */
1980                 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1981                                       self->tx_buff.data, self->tx_buff.len);
1982                 self->tx_buff.data += actual;
1983                 self->tx_buff.len  -= actual;
1984         } else {
1985
1986         /*if (self->tx_buff.len ==0)  {*/
1987
1988                 /*
1989                  *  Now serial buffer is almost free & we can start
1990                  *  transmission of another packet. But first we must check
1991                  *  if we need to change the speed of the hardware
1992                  */
1993                 if (self->new_speed) {
1994                         IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1995                                    __func__, self->new_speed);
1996                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
1997                         smsc_ircc_change_speed(self, self->new_speed);
1998                         self->new_speed = 0;
1999                 } else {
2000                         /* Tell network layer that we want more frames */
2001                         netif_wake_queue(self->netdev);
2002                 }
2003                 self->netdev->stats.tx_packets++;
2004
2005                 if (self->io.speed <= 115200) {
2006                         /*
2007                          * Reset Rx FIFO to make sure that all reflected transmit data
2008                          * is discarded. This is needed for half duplex operation
2009                          */
2010                         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2011                         fcr |= self->io.speed < 38400 ?
2012                                         UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2013
2014                         outb(fcr, iobase + UART_FCR);
2015
2016                         /* Turn on receive interrupts */
2017                         outb(UART_IER_RDI, iobase + UART_IER);
2018                 }
2019         }
2020 }
2021
2022 /*
2023  * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2024  *
2025  *    Fill Tx FIFO with transmit data
2026  *
2027  */
2028 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2029 {
2030         int actual = 0;
2031
2032         /* Tx FIFO should be empty! */
2033         if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2034                 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
2035                 return 0;
2036         }
2037
2038         /* Fill FIFO with current frame */
2039         while (fifo_size-- > 0 && actual < len) {
2040                 /* Transmit next byte */
2041                 outb(buf[actual], iobase + UART_TX);
2042                 actual++;
2043         }
2044         return actual;
2045 }
2046
2047 /*
2048  * Function smsc_ircc_is_receiving (self)
2049  *
2050  *    Returns true is we are currently receiving data
2051  *
2052  */
2053 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2054 {
2055         return self->rx_buff.state != OUTSIDE_FRAME;
2056 }
2057
2058
2059 /*
2060  * Function smsc_ircc_probe_transceiver(self)
2061  *
2062  *    Tries to find the used Transceiver
2063  *
2064  */
2065 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2066 {
2067         unsigned int    i;
2068
2069         IRDA_ASSERT(self != NULL, return;);
2070
2071         for (i = 0; smsc_transceivers[i].name != NULL; i++)
2072                 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2073                         IRDA_MESSAGE(" %s transceiver found\n",
2074                                      smsc_transceivers[i].name);
2075                         self->transceiver= i + 1;
2076                         return;
2077                 }
2078
2079         IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2080                      smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2081
2082         self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2083 }
2084
2085
2086 /*
2087  * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2088  *
2089  *    Set the transceiver according to the speed
2090  *
2091  */
2092 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2093 {
2094         unsigned int trx;
2095
2096         trx = self->transceiver;
2097         if (trx > 0)
2098                 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2099 }
2100
2101 /*
2102  * Function smsc_ircc_wait_hw_transmitter_finish ()
2103  *
2104  *    Wait for the real end of HW transmission
2105  *
2106  * The UART is a strict FIFO, and we get called only when we have finished
2107  * pushing data to the FIFO, so the maximum amount of time we must wait
2108  * is only for the FIFO to drain out.
2109  *
2110  * We use a simple calibrated loop. We may need to adjust the loop
2111  * delay (udelay) to balance I/O traffic and latency. And we also need to
2112  * adjust the maximum timeout.
2113  * It would probably be better to wait for the proper interrupt,
2114  * but it doesn't seem to be available.
2115  *
2116  * We can't use jiffies or kernel timers because :
2117  * 1) We are called from the interrupt handler, which disable softirqs,
2118  * so jiffies won't be increased
2119  * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2120  * want to wait that long to detect stuck hardware.
2121  * Jean II
2122  */
2123
2124 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2125 {
2126         int iobase = self->io.sir_base;
2127         int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2128
2129         /* Calibrated busy loop */
2130         while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2131                 udelay(1);
2132
2133         if (count < 0)
2134                 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
2135 }
2136
2137
2138 /* PROBING
2139  *
2140  * REVISIT we can be told about the device by PNP, and should use that info
2141  * instead of probing hardware and creating a platform_device ...
2142  */
2143
2144 static int __init smsc_ircc_look_for_chips(void)
2145 {
2146         struct smsc_chip_address *address;
2147         char *type;
2148         unsigned int cfg_base, found;
2149
2150         found = 0;
2151         address = possible_addresses;
2152
2153         while (address->cfg_base) {
2154                 cfg_base = address->cfg_base;
2155
2156                 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2157
2158                 if (address->type & SMSCSIO_TYPE_FDC) {
2159                         type = "FDC";
2160                         if (address->type & SMSCSIO_TYPE_FLAT)
2161                                 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2162                                         found++;
2163
2164                         if (address->type & SMSCSIO_TYPE_PAGED)
2165                                 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2166                                         found++;
2167                 }
2168                 if (address->type & SMSCSIO_TYPE_LPC) {
2169                         type = "LPC";
2170                         if (address->type & SMSCSIO_TYPE_FLAT)
2171                                 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2172                                         found++;
2173
2174                         if (address->type & SMSCSIO_TYPE_PAGED)
2175                                 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2176                                         found++;
2177                 }
2178                 address++;
2179         }
2180         return found;
2181 }
2182
2183 /*
2184  * Function smsc_superio_flat (chip, base, type)
2185  *
2186  *    Try to get configuration of a smc SuperIO chip with flat register model
2187  *
2188  */
2189 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2190 {
2191         unsigned short firbase, sirbase;
2192         u8 mode, dma, irq;
2193         int ret = -ENODEV;
2194
2195         IRDA_DEBUG(1, "%s\n", __func__);
2196
2197         if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2198                 return ret;
2199
2200         outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2201         mode = inb(cfgbase + 1);
2202
2203         /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2204
2205         if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2206                 IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
2207
2208         outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2209         sirbase = inb(cfgbase + 1) << 2;
2210
2211         /* FIR iobase */
2212         outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2213         firbase = inb(cfgbase + 1) << 3;
2214
2215         /* DMA */
2216         outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2217         dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2218
2219         /* IRQ */
2220         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2221         irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2222
2223         IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
2224
2225         if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2226                 ret = 0;
2227
2228         /* Exit configuration */
2229         outb(SMSCSIO_CFGEXITKEY, cfgbase);
2230
2231         return ret;
2232 }
2233
2234 /*
2235  * Function smsc_superio_paged (chip, base, type)
2236  *
2237  *    Try  to get configuration of a smc SuperIO chip with paged register model
2238  *
2239  */
2240 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2241 {
2242         unsigned short fir_io, sir_io;
2243         int ret = -ENODEV;
2244
2245         IRDA_DEBUG(1, "%s\n", __func__);
2246
2247         if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2248                 return ret;
2249
2250         /* Select logical device (UART2) */
2251         outb(0x07, cfg_base);
2252         outb(0x05, cfg_base + 1);
2253
2254         /* SIR iobase */
2255         outb(0x60, cfg_base);
2256         sir_io = inb(cfg_base + 1) << 8;
2257         outb(0x61, cfg_base);
2258         sir_io |= inb(cfg_base + 1);
2259
2260         /* Read FIR base */
2261         outb(0x62, cfg_base);
2262         fir_io = inb(cfg_base + 1) << 8;
2263         outb(0x63, cfg_base);
2264         fir_io |= inb(cfg_base + 1);
2265         outb(0x2b, cfg_base); /* ??? */
2266
2267         if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2268                 ret = 0;
2269
2270         /* Exit configuration */
2271         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2272
2273         return ret;
2274 }
2275
2276
2277 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2278 {
2279         IRDA_DEBUG(1, "%s\n", __func__);
2280
2281         outb(reg, cfg_base);
2282         return inb(cfg_base) != reg ? -1 : 0;
2283 }
2284
2285 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2286 {
2287         u8 devid, xdevid, rev;
2288
2289         IRDA_DEBUG(1, "%s\n", __func__);
2290
2291         /* Leave configuration */
2292
2293         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2294
2295         if (inb(cfg_base) == SMSCSIO_CFGEXITKEY)        /* not a smc superio chip */
2296                 return NULL;
2297
2298         outb(reg, cfg_base);
2299
2300         xdevid = inb(cfg_base + 1);
2301
2302         /* Enter configuration */
2303
2304         outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2305
2306         #if 0
2307         if (smsc_access(cfg_base,0x55)) /* send second key and check */
2308                 return NULL;
2309         #endif
2310
2311         /* probe device ID */
2312
2313         if (smsc_access(cfg_base, reg))
2314                 return NULL;
2315
2316         devid = inb(cfg_base + 1);
2317
2318         if (devid == 0 || devid == 0xff)        /* typical values for unused port */
2319                 return NULL;
2320
2321         /* probe revision ID */
2322
2323         if (smsc_access(cfg_base, reg + 1))
2324                 return NULL;
2325
2326         rev = inb(cfg_base + 1);
2327
2328         if (rev >= 128)                 /* i think this will make no sense */
2329                 return NULL;
2330
2331         if (devid == xdevid)            /* protection against false positives */
2332                 return NULL;
2333
2334         /* Check for expected device ID; are there others? */
2335
2336         while (chip->devid != devid) {
2337
2338                 chip++;
2339
2340                 if (chip->name == NULL)
2341                         return NULL;
2342         }
2343
2344         IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2345                      devid, rev, cfg_base, type, chip->name);
2346
2347         if (chip->rev > rev) {
2348                 IRDA_MESSAGE("Revision higher than expected\n");
2349                 return NULL;
2350         }
2351
2352         if (chip->flags & NoIRDA)
2353                 IRDA_MESSAGE("chipset does not support IRDA\n");
2354
2355         return chip;
2356 }
2357
2358 static int __init smsc_superio_fdc(unsigned short cfg_base)
2359 {
2360         int ret = -1;
2361
2362         if (!request_region(cfg_base, 2, driver_name)) {
2363                 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2364                              __func__, cfg_base);
2365         } else {
2366                 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2367                     !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2368                         ret =  0;
2369
2370                 release_region(cfg_base, 2);
2371         }
2372
2373         return ret;
2374 }
2375
2376 static int __init smsc_superio_lpc(unsigned short cfg_base)
2377 {
2378         int ret = -1;
2379
2380         if (!request_region(cfg_base, 2, driver_name)) {
2381                 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2382                              __func__, cfg_base);
2383         } else {
2384                 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2385                     !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2386                         ret = 0;
2387
2388                 release_region(cfg_base, 2);
2389         }
2390         return ret;
2391 }
2392
2393 /*
2394  * Look for some specific subsystem setups that need
2395  * pre-configuration not properly done by the BIOS (especially laptops)
2396  * This code is based in part on smcinit.c, tosh1800-smcinit.c
2397  * and tosh2450-smcinit.c. The table lists the device entries
2398  * for ISA bridges with an LPC (Low Pin Count) controller which
2399  * handles the communication with the SMSC device. After the LPC
2400  * controller is initialized through PCI, the SMSC device is initialized
2401  * through a dedicated port in the ISA port-mapped I/O area, this latter
2402  * area is used to configure the SMSC device with default
2403  * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2404  * used different sets of parameters and different control port
2405  * addresses making a subsystem device table necessary.
2406  */
2407 #ifdef CONFIG_PCI
2408 #define PCIID_VENDOR_INTEL 0x8086
2409 #define PCIID_VENDOR_ALI 0x10b9
2410 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2411         /*
2412          * Subsystems needing entries:
2413          * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2414          * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2415          * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2416          */
2417         {
2418                 /* Guessed entry */
2419                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2420                 .device = 0x24cc,
2421                 .subvendor = 0x103c,
2422                 .subdevice = 0x08bc,
2423                 .sir_io = 0x02f8,
2424                 .fir_io = 0x0130,
2425                 .fir_irq = 0x05,
2426                 .fir_dma = 0x03,
2427                 .cfg_base = 0x004e,
2428                 .preconfigure = preconfigure_through_82801,
2429                 .name = "HP nx5000 family",
2430         },
2431         {
2432                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2433                 .device = 0x24cc,
2434                 .subvendor = 0x103c,
2435                 .subdevice = 0x088c,
2436                 /* Quite certain these are the same for nc8000 as for nc6000 */
2437                 .sir_io = 0x02f8,
2438                 .fir_io = 0x0130,
2439                 .fir_irq = 0x05,
2440                 .fir_dma = 0x03,
2441                 .cfg_base = 0x004e,
2442                 .preconfigure = preconfigure_through_82801,
2443                 .name = "HP nc8000 family",
2444         },
2445         {
2446                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2447                 .device = 0x24cc,
2448                 .subvendor = 0x103c,
2449                 .subdevice = 0x0890,
2450                 .sir_io = 0x02f8,
2451                 .fir_io = 0x0130,
2452                 .fir_irq = 0x05,
2453                 .fir_dma = 0x03,
2454                 .cfg_base = 0x004e,
2455                 .preconfigure = preconfigure_through_82801,
2456                 .name = "HP nc6000 family",
2457         },
2458         {
2459                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2460                 .device = 0x24cc,
2461                 .subvendor = 0x0e11,
2462                 .subdevice = 0x0860,
2463                 /* I assume these are the same for x1000 as for the others */
2464                 .sir_io = 0x02e8,
2465                 .fir_io = 0x02f8,
2466                 .fir_irq = 0x07,
2467                 .fir_dma = 0x03,
2468                 .cfg_base = 0x002e,
2469                 .preconfigure = preconfigure_through_82801,
2470                 .name = "Compaq x1000 family",
2471         },
2472         {
2473                 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2474                 .vendor = PCIID_VENDOR_INTEL,
2475                 .device = 0x24c0,
2476                 .subvendor = 0x1179,
2477                 .subdevice = 0xffff, /* 0xffff is "any" */
2478                 .sir_io = 0x03f8,
2479                 .fir_io = 0x0130,
2480                 .fir_irq = 0x07,
2481                 .fir_dma = 0x01,
2482                 .cfg_base = 0x002e,
2483                 .preconfigure = preconfigure_through_82801,
2484                 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2485         },
2486         {
2487                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2488                 .device = 0x248c,
2489                 .subvendor = 0x1179,
2490                 .subdevice = 0xffff, /* 0xffff is "any" */
2491                 .sir_io = 0x03f8,
2492                 .fir_io = 0x0130,
2493                 .fir_irq = 0x03,
2494                 .fir_dma = 0x03,
2495                 .cfg_base = 0x002e,
2496                 .preconfigure = preconfigure_through_82801,
2497                 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2498         },
2499         {
2500                 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2501                 .vendor = PCIID_VENDOR_INTEL,
2502                 .device = 0x24cc,
2503                 .subvendor = 0x1179,
2504                 .subdevice = 0xffff, /* 0xffff is "any" */
2505                 .sir_io = 0x03f8,
2506                 .fir_io = 0x0130,
2507                 .fir_irq = 0x03,
2508                 .fir_dma = 0x03,
2509                 .cfg_base = 0x002e,
2510                 .preconfigure = preconfigure_through_82801,
2511                 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2512         },
2513         {
2514                 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2515                 .vendor = PCIID_VENDOR_ALI,
2516                 .device = 0x1533,
2517                 .subvendor = 0x1179,
2518                 .subdevice = 0xffff, /* 0xffff is "any" */
2519                 .sir_io = 0x02e8,
2520                 .fir_io = 0x02f8,
2521                 .fir_irq = 0x07,
2522                 .fir_dma = 0x03,
2523                 .cfg_base = 0x002e,
2524                 .preconfigure = preconfigure_through_ali,
2525                 .name = "Toshiba laptop with ALi ISA bridge",
2526         },
2527         { } // Terminator
2528 };
2529
2530
2531 /*
2532  * This sets up the basic SMSC parameters
2533  * (FIR port, SIR port, FIR DMA, FIR IRQ)
2534  * through the chip configuration port.
2535  */
2536 static int __init preconfigure_smsc_chip(struct
2537                                          smsc_ircc_subsystem_configuration
2538                                          *conf)
2539 {
2540         unsigned short iobase = conf->cfg_base;
2541         unsigned char tmpbyte;
2542
2543         outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2544         outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2545         tmpbyte = inb(iobase +1); // Read device ID
2546         IRDA_DEBUG(0,
2547                    "Detected Chip id: 0x%02x, setting up registers...\n",
2548                    tmpbyte);
2549
2550         /* Disable UART1 and set up SIR I/O port */
2551         outb(0x24, iobase);  // select CR24 - UART1 base addr
2552         outb(0x00, iobase + 1); // disable UART1
2553         outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase);  // select CR25 - UART2 base addr
2554         outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2555         tmpbyte = inb(iobase + 1);
2556         if (tmpbyte != (conf->sir_io >> 2) ) {
2557                 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2558                 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2559                 return -ENXIO;
2560         }
2561
2562         /* Set up FIR IRQ channel for UART2 */
2563         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2564         tmpbyte = inb(iobase + 1);
2565         tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2566         tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2567         outb(tmpbyte, iobase + 1);
2568         tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2569         if (tmpbyte != conf->fir_irq) {
2570                 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2571                 return -ENXIO;
2572         }
2573
2574         /* Set up FIR I/O port */
2575         outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase);  // CR2B - SCE (FIR) base addr
2576         outb((conf->fir_io >> 3), iobase + 1);
2577         tmpbyte = inb(iobase + 1);
2578         if (tmpbyte != (conf->fir_io >> 3) ) {
2579                 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2580                 return -ENXIO;
2581         }
2582
2583         /* Set up FIR DMA channel */
2584         outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase);  // CR2C - SCE (FIR) DMA select
2585         outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2586         tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2587         if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2588                 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2589                 return -ENXIO;
2590         }
2591
2592         outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase);  // CR0C - UART mode
2593         tmpbyte = inb(iobase + 1);
2594         tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2595                 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2596         outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2597
2598         outb(LPC47N227_APMBOOTDRIVE_REG, iobase);  // CR07 - Auto Pwr Mgt/boot drive sel
2599         tmpbyte = inb(iobase + 1);
2600         outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2601
2602         /* This one was not part of tosh1800 */
2603         outb(0x0a, iobase);  // CR0a - ecp fifo / ir mux
2604         tmpbyte = inb(iobase + 1);
2605         outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2606
2607         outb(LPC47N227_UART12POWER_REG, iobase);  // CR02 - UART 1,2 power
2608         tmpbyte = inb(iobase + 1);
2609         outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2610
2611         outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase);  // CR00 - FDC Power/valid config cycle
2612         tmpbyte = inb(iobase + 1);
2613         outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2614
2615         outb(LPC47N227_CFGEXITKEY, iobase);  // Exit configuration
2616
2617         return 0;
2618 }
2619
2620 /* 82801CAM generic registers */
2621 #define VID 0x00
2622 #define DID 0x02
2623 #define PIRQ_A_D_ROUT 0x60
2624 #define SIRQ_CNTL 0x64
2625 #define PIRQ_E_H_ROUT 0x68
2626 #define PCI_DMA_C 0x90
2627 /* LPC-specific registers */
2628 #define COM_DEC 0xe0
2629 #define GEN1_DEC 0xe4
2630 #define LPC_EN 0xe6
2631 #define GEN2_DEC 0xec
2632 /*
2633  * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2634  * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2635  * They all work the same way!
2636  */
2637 static int __init preconfigure_through_82801(struct pci_dev *dev,
2638                                              struct
2639                                              smsc_ircc_subsystem_configuration
2640                                              *conf)
2641 {
2642         unsigned short tmpword;
2643         unsigned char tmpbyte;
2644
2645         IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2646         /*
2647          * Select the range for the COMA COM port (SIR)
2648          * Register COM_DEC:
2649          * Bit 7: reserved
2650          * Bit 6-4, COMB decode range
2651          * Bit 3: reserved
2652          * Bit 2-0, COMA decode range
2653          *
2654          * Decode ranges:
2655          *   000 = 0x3f8-0x3ff (COM1)
2656          *   001 = 0x2f8-0x2ff (COM2)
2657          *   010 = 0x220-0x227
2658          *   011 = 0x228-0x22f
2659          *   100 = 0x238-0x23f
2660          *   101 = 0x2e8-0x2ef (COM4)
2661          *   110 = 0x338-0x33f
2662          *   111 = 0x3e8-0x3ef (COM3)
2663          */
2664         pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2665         tmpbyte &= 0xf8; /* mask COMA bits */
2666         switch(conf->sir_io) {
2667         case 0x3f8:
2668                 tmpbyte |= 0x00;
2669                 break;
2670         case 0x2f8:
2671                 tmpbyte |= 0x01;
2672                 break;
2673         case 0x220:
2674                 tmpbyte |= 0x02;
2675                 break;
2676         case 0x228:
2677                 tmpbyte |= 0x03;
2678                 break;
2679         case 0x238:
2680                 tmpbyte |= 0x04;
2681                 break;
2682         case 0x2e8:
2683                 tmpbyte |= 0x05;
2684                 break;
2685         case 0x338:
2686                 tmpbyte |= 0x06;
2687                 break;
2688         case 0x3e8:
2689                 tmpbyte |= 0x07;
2690                 break;
2691         default:
2692                 tmpbyte |= 0x01; /* COM2 default */
2693         }
2694         IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2695         pci_write_config_byte(dev, COM_DEC, tmpbyte);
2696
2697         /* Enable Low Pin Count interface */
2698         pci_read_config_word(dev, LPC_EN, &tmpword);
2699         /* These seem to be set up at all times,
2700          * just make sure it is properly set.
2701          */
2702         switch(conf->cfg_base) {
2703         case 0x04e:
2704                 tmpword |= 0x2000;
2705                 break;
2706         case 0x02e:
2707                 tmpword |= 0x1000;
2708                 break;
2709         case 0x062:
2710                 tmpword |= 0x0800;
2711                 break;
2712         case 0x060:
2713                 tmpword |= 0x0400;
2714                 break;
2715         default:
2716                 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2717                              conf->cfg_base);
2718                 break;
2719         }
2720         tmpword &= 0xfffd; /* disable LPC COMB */
2721         tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2722         IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2723         pci_write_config_word(dev, LPC_EN, tmpword);
2724
2725         /*
2726          * Configure LPC DMA channel
2727          * PCI_DMA_C bits:
2728          * Bit 15-14: DMA channel 7 select
2729          * Bit 13-12: DMA channel 6 select
2730          * Bit 11-10: DMA channel 5 select
2731          * Bit 9-8:   Reserved
2732          * Bit 7-6:   DMA channel 3 select
2733          * Bit 5-4:   DMA channel 2 select
2734          * Bit 3-2:   DMA channel 1 select
2735          * Bit 1-0:   DMA channel 0 select
2736          *  00 = Reserved value
2737          *  01 = PC/PCI DMA
2738          *  10 = Reserved value
2739          *  11 = LPC I/F DMA
2740          */
2741         pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2742         switch(conf->fir_dma) {
2743         case 0x07:
2744                 tmpword |= 0xc000;
2745                 break;
2746         case 0x06:
2747                 tmpword |= 0x3000;
2748                 break;
2749         case 0x05:
2750                 tmpword |= 0x0c00;
2751                 break;
2752         case 0x03:
2753                 tmpword |= 0x00c0;
2754                 break;
2755         case 0x02:
2756                 tmpword |= 0x0030;
2757                 break;
2758         case 0x01:
2759                 tmpword |= 0x000c;
2760                 break;
2761         case 0x00:
2762                 tmpword |= 0x0003;
2763                 break;
2764         default:
2765                 break; /* do not change settings */
2766         }
2767         IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2768         pci_write_config_word(dev, PCI_DMA_C, tmpword);
2769
2770         /*
2771          * GEN2_DEC bits:
2772          * Bit 15-4: Generic I/O range
2773          * Bit 3-1: reserved (read as 0)
2774          * Bit 0: enable GEN2 range on LPC I/F
2775          */
2776         tmpword = conf->fir_io & 0xfff8;
2777         tmpword |= 0x0001;
2778         IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2779         pci_write_config_word(dev, GEN2_DEC, tmpword);
2780
2781         /* Pre-configure chip */
2782         return preconfigure_smsc_chip(conf);
2783 }
2784
2785 /*
2786  * Pre-configure a certain port on the ALi 1533 bridge.
2787  * This is based on reverse-engineering since ALi does not
2788  * provide any data sheet for the 1533 chip.
2789  */
2790 static void __init preconfigure_ali_port(struct pci_dev *dev,
2791                                          unsigned short port)
2792 {
2793         unsigned char reg;
2794         /* These bits obviously control the different ports */
2795         unsigned char mask;
2796         unsigned char tmpbyte;
2797
2798         switch(port) {
2799         case 0x0130:
2800         case 0x0178:
2801                 reg = 0xb0;
2802                 mask = 0x80;
2803                 break;
2804         case 0x03f8:
2805                 reg = 0xb4;
2806                 mask = 0x80;
2807                 break;
2808         case 0x02f8:
2809                 reg = 0xb4;
2810                 mask = 0x30;
2811                 break;
2812         case 0x02e8:
2813                 reg = 0xb4;
2814                 mask = 0x08;
2815                 break;
2816         default:
2817                 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2818                 return;
2819         }
2820
2821         pci_read_config_byte(dev, reg, &tmpbyte);
2822         /* Turn on the right bits */
2823         tmpbyte |= mask;
2824         pci_write_config_byte(dev, reg, tmpbyte);
2825         IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2826 }
2827
2828 static int __init preconfigure_through_ali(struct pci_dev *dev,
2829                                            struct
2830                                            smsc_ircc_subsystem_configuration
2831                                            *conf)
2832 {
2833         /* Configure the two ports on the ALi 1533 */
2834         preconfigure_ali_port(dev, conf->sir_io);
2835         preconfigure_ali_port(dev, conf->fir_io);
2836
2837         /* Pre-configure chip */
2838         return preconfigure_smsc_chip(conf);
2839 }
2840
2841 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2842                                                     unsigned short ircc_fir,
2843                                                     unsigned short ircc_sir,
2844                                                     unsigned char ircc_dma,
2845                                                     unsigned char ircc_irq)
2846 {
2847         struct pci_dev *dev = NULL;
2848         unsigned short ss_vendor = 0x0000;
2849         unsigned short ss_device = 0x0000;
2850         int ret = 0;
2851
2852         for_each_pci_dev(dev) {
2853                 struct smsc_ircc_subsystem_configuration *conf;
2854
2855                 /*
2856                  * Cache the subsystem vendor/device:
2857                  * some manufacturers fail to set this for all components,
2858                  * so we save it in case there is just 0x0000 0x0000 on the
2859                  * device we want to check.
2860                  */
2861                 if (dev->subsystem_vendor != 0x0000U) {
2862                         ss_vendor = dev->subsystem_vendor;
2863                         ss_device = dev->subsystem_device;
2864                 }
2865                 conf = subsystem_configurations;
2866                 for( ; conf->subvendor; conf++) {
2867                         if(conf->vendor == dev->vendor &&
2868                            conf->device == dev->device &&
2869                            conf->subvendor == ss_vendor &&
2870                            /* Sometimes these are cached values */
2871                            (conf->subdevice == ss_device ||
2872                             conf->subdevice == 0xffff)) {
2873                                 struct smsc_ircc_subsystem_configuration
2874                                         tmpconf;
2875
2876                                 memcpy(&tmpconf, conf,
2877                                        sizeof(struct smsc_ircc_subsystem_configuration));
2878
2879                                 /*
2880                                  * Override the default values with anything
2881                                  * passed in as parameter
2882                                  */
2883                                 if (ircc_cfg != 0)
2884                                         tmpconf.cfg_base = ircc_cfg;
2885                                 if (ircc_fir != 0)
2886                                         tmpconf.fir_io = ircc_fir;
2887                                 if (ircc_sir != 0)
2888                                         tmpconf.sir_io = ircc_sir;
2889                                 if (ircc_dma != DMA_INVAL)
2890                                         tmpconf.fir_dma = ircc_dma;
2891                                 if (ircc_irq != IRQ_INVAL)
2892                                         tmpconf.fir_irq = ircc_irq;
2893
2894                                 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2895                                 if (conf->preconfigure)
2896                                         ret = conf->preconfigure(dev, &tmpconf);
2897                                 else
2898                                         ret = -ENODEV;
2899                         }
2900                 }
2901         }
2902
2903         return ret;
2904 }
2905 #endif // CONFIG_PCI
2906
2907 /************************************************
2908  *
2909  * Transceivers specific functions
2910  *
2911  ************************************************/
2912
2913
2914 /*
2915  * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2916  *
2917  *    Program transceiver through smsc-ircc ATC circuitry
2918  *
2919  */
2920
2921 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2922 {
2923         unsigned long jiffies_now, jiffies_timeout;
2924         u8 val;
2925
2926         jiffies_now = jiffies;
2927         jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2928
2929         /* ATC */
2930         register_bank(fir_base, 4);
2931         outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2932              fir_base + IRCC_ATC);
2933
2934         while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2935                 !time_after(jiffies, jiffies_timeout))
2936                 /* empty */;
2937
2938         if (val)
2939                 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
2940                              inb(fir_base + IRCC_ATC));
2941 }
2942
2943 /*
2944  * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2945  *
2946  *    Probe transceiver smsc-ircc ATC circuitry
2947  *
2948  */
2949
2950 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2951 {
2952         return 0;
2953 }
2954
2955 /*
2956  * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2957  *
2958  *    Set transceiver
2959  *
2960  */
2961
2962 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2963 {
2964         u8 fast_mode;
2965
2966         switch (speed) {
2967         default:
2968         case 576000 :
2969                 fast_mode = 0;
2970                 break;
2971         case 1152000 :
2972         case 4000000 :
2973                 fast_mode = IRCC_LCR_A_FAST;
2974                 break;
2975         }
2976         register_bank(fir_base, 0);
2977         outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2978 }
2979
2980 /*
2981  * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2982  *
2983  *    Probe transceiver
2984  *
2985  */
2986
2987 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2988 {
2989         return 0;
2990 }
2991
2992 /*
2993  * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2994  *
2995  *    Set transceiver
2996  *
2997  */
2998
2999 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
3000 {
3001         u8 fast_mode;
3002
3003         switch (speed) {
3004         default:
3005         case 576000 :
3006                 fast_mode = 0;
3007                 break;
3008         case 1152000 :
3009         case 4000000 :
3010                 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3011                 break;
3012
3013         }
3014         /* This causes an interrupt */
3015         register_bank(fir_base, 0);
3016         outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3017 }
3018
3019 /*
3020  * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3021  *
3022  *    Probe transceiver
3023  *
3024  */
3025
3026 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3027 {
3028         return 0;
3029 }
3030
3031
3032 module_init(smsc_ircc_init);
3033 module_exit(smsc_ircc_cleanup);