drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  72         /* required last entry */
  73         {0, }
  74 };
  75
  76 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  77
  78 void igb_reset(struct igb_adapter *);
  79 static int igb_setup_all_tx_resources(struct igb_adapter *);
  80 static int igb_setup_all_rx_resources(struct igb_adapter *);
  81 static void igb_free_all_tx_resources(struct igb_adapter *);
  82 static void igb_free_all_rx_resources(struct igb_adapter *);
  83 void igb_update_stats(struct igb_adapter *);
  84 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  85 static void __devexit igb_remove(struct pci_dev *pdev);
  86 static int igb_sw_init(struct igb_adapter *);
  87 static int igb_open(struct net_device *);
  88 static int igb_close(struct net_device *);
  89 static void igb_configure_tx(struct igb_adapter *);
  90 static void igb_configure_rx(struct igb_adapter *);
  91 static void igb_setup_rctl(struct igb_adapter *);
  92 static void igb_clean_all_tx_rings(struct igb_adapter *);
  93 static void igb_clean_all_rx_rings(struct igb_adapter *);
  94 static void igb_clean_tx_ring(struct igb_ring *);
  95 static void igb_clean_rx_ring(struct igb_ring *);
  96 static void igb_set_multi(struct net_device *);
  97 static void igb_update_phy_info(unsigned long);
  98 static void igb_watchdog(unsigned long);
  99 static void igb_watchdog_task(struct work_struct *);
 100 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
 101                                   struct igb_ring *);
 102 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
 103 static struct net_device_stats *igb_get_stats(struct net_device *);
 104 static int igb_change_mtu(struct net_device *, int);
 105 static int igb_set_mac(struct net_device *, void *);
 106 static irqreturn_t igb_intr(int irq, void *);
 107 static irqreturn_t igb_intr_msi(int irq, void *);
 108 static irqreturn_t igb_msix_other(int irq, void *);
 109 static irqreturn_t igb_msix_rx(int irq, void *);
 110 static irqreturn_t igb_msix_tx(int irq, void *);
 111 #ifdef CONFIG_IGB_DCA
 112 static void igb_update_rx_dca(struct igb_ring *);
 113 static void igb_update_tx_dca(struct igb_ring *);
 114 static void igb_setup_dca(struct igb_adapter *);
 115 #endif /* CONFIG_IGB_DCA */
 116 static bool igb_clean_tx_irq(struct igb_ring *);
 117 static int igb_poll(struct napi_struct *, int);
 118 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 119 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 120 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 121 static void igb_tx_timeout(struct net_device *);
 122 static void igb_reset_task(struct work_struct *);
 123 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 124 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 125 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 126 static void igb_restore_vlan(struct igb_adapter *);
 127 static void igb_ping_all_vfs(struct igb_adapter *);
 128 static void igb_msg_task(struct igb_adapter *);
 129 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 130 static void igb_set_mc_list_pools(struct igb_adapter *, int, u16);
 131 static void igb_vmm_control(struct igb_adapter *);
 132 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 133 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 134
 135 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
 136 {
 137         u32 reg_data;
 138
 139         reg_data = rd32(E1000_VMOLR(vfn));
 140         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
 141                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
 142                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
 143                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
 144                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
 145         wr32(E1000_VMOLR(vfn), reg_data);
 146 }
 147
 148 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
 149                                  int vfn)
 150 {
 151         struct e1000_hw *hw = &adapter->hw;
 152         u32 vmolr;
 153
 154         vmolr = rd32(E1000_VMOLR(vfn));
 155         vmolr &= ~E1000_VMOLR_RLPML_MASK;
 156         vmolr |= size | E1000_VMOLR_LPE;
 157         wr32(E1000_VMOLR(vfn), vmolr);
 158
 159         return 0;
 160 }
 161
 162 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
 163 {
 164         u32 reg_data;
 165
 166         reg_data = rd32(E1000_RAH(entry));
 167         reg_data &= ~E1000_RAH_POOL_MASK;
 168         reg_data |= E1000_RAH_POOL_1 << pool;;
 169         wr32(E1000_RAH(entry), reg_data);
 170 }
 171
 172 #ifdef CONFIG_PM
 173 static int igb_suspend(struct pci_dev *, pm_message_t);
 174 static int igb_resume(struct pci_dev *);
 175 #endif
 176 static void igb_shutdown(struct pci_dev *);
 177 #ifdef CONFIG_IGB_DCA
 178 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 179 static struct notifier_block dca_notifier = {
 180         .notifier_call  = igb_notify_dca,
 181         .next           = NULL,
 182         .priority       = 0
 183 };
 184 #endif
 185 #ifdef CONFIG_NET_POLL_CONTROLLER
 186 /* for netdump / net console */
 187 static void igb_netpoll(struct net_device *);
 188 #endif
 189 #ifdef CONFIG_PCI_IOV
 190 static unsigned int max_vfs = 0;
 191 module_param(max_vfs, uint, 0);
 192 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 193                  "per physical function");
 194 #endif /* CONFIG_PCI_IOV */
 195
 196 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 197                      pci_channel_state_t);
 198 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 199 static void igb_io_resume(struct pci_dev *);
 200
 201 static struct pci_error_handlers igb_err_handler = {
 202         .error_detected = igb_io_error_detected,
 203         .slot_reset = igb_io_slot_reset,
 204         .resume = igb_io_resume,
 205 };
 206
 207
 208 static struct pci_driver igb_driver = {
 209         .name     = igb_driver_name,
 210         .id_table = igb_pci_tbl,
 211         .probe    = igb_probe,
 212         .remove   = __devexit_p(igb_remove),
 213 #ifdef CONFIG_PM
 214         /* Power Managment Hooks */
 215         .suspend  = igb_suspend,
 216         .resume   = igb_resume,
 217 #endif
 218         .shutdown = igb_shutdown,
 219         .err_handler = &igb_err_handler
 220 };
 221
 222 static int global_quad_port_a; /* global quad port a indication */
 223
 224 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 225 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 226 MODULE_LICENSE("GPL");
 227 MODULE_VERSION(DRV_VERSION);
 228
 229 /**
 230  * Scale the NIC clock cycle by a large factor so that
 231  * relatively small clock corrections can be added or
 232  * substracted at each clock tick. The drawbacks of a
 233  * large factor are a) that the clock register overflows
 234  * more quickly (not such a big deal) and b) that the
 235  * increment per tick has to fit into 24 bits.
 236  *
 237  * Note that
 238  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 239  *             IGB_TSYNC_SCALE
 240  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 241  *
 242  * The base scale factor is intentionally a power of two
 243  * so that the division in %struct timecounter can be done with
 244  * a shift.
 245  */
 246 #define IGB_TSYNC_SHIFT (19)
 247 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 248
 249 /**
 250  * The duration of one clock cycle of the NIC.
 251  *
 252  * @todo This hard-coded value is part of the specification and might change
 253  * in future hardware revisions. Add revision check.
 254  */
 255 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 256
 257 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 258 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 259 #endif
 260
 261 /**
 262  * igb_read_clock - read raw cycle counter (to be used by time counter)
 263  */
 264 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 265 {
 266         struct igb_adapter *adapter =
 267                 container_of(tc, struct igb_adapter, cycles);
 268         struct e1000_hw *hw = &adapter->hw;
 269         u64 stamp;
 270
 271         stamp =  rd32(E1000_SYSTIML);
 272         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 273
 274         return stamp;
 275 }
 276
 277 #ifdef DEBUG
 278 /**
 279  * igb_get_hw_dev_name - return device name string
 280  * used by hardware layer to print debugging information
 281  **/
 282 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 283 {
 284         struct igb_adapter *adapter = hw->back;
 285         return adapter->netdev->name;
 286 }
 287
 288 /**
 289  * igb_get_time_str - format current NIC and system time as string
 290  */
 291 static char *igb_get_time_str(struct igb_adapter *adapter,
 292                               char buffer[160])
 293 {
 294         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 295         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 296         struct timespec sys;
 297         struct timespec delta;
 298         getnstimeofday(&sys);
 299
 300         delta = timespec_sub(nic, sys);
 301
 302         sprintf(buffer,
 303                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 304                 hw,
 305                 (long)nic.tv_sec, nic.tv_nsec,
 306                 (long)sys.tv_sec, sys.tv_nsec,
 307                 (long)delta.tv_sec, delta.tv_nsec);
 308
 309         return buffer;
 310 }
 311 #endif
 312
 313 /**
 314  * igb_desc_unused - calculate if we have unused descriptors
 315  **/
 316 static int igb_desc_unused(struct igb_ring *ring)
 317 {
 318         if (ring->next_to_clean > ring->next_to_use)
 319                 return ring->next_to_clean - ring->next_to_use - 1;
 320
 321         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 322 }
 323
 324 /**
 325  * igb_init_module - Driver Registration Routine
 326  *
 327  * igb_init_module is the first routine called when the driver is
 328  * loaded. All it does is register with the PCI subsystem.
 329  **/
 330 static int __init igb_init_module(void)
 331 {
 332         int ret;
 333         printk(KERN_INFO "%s - version %s\n",
 334                igb_driver_string, igb_driver_version);
 335
 336         printk(KERN_INFO "%s\n", igb_copyright);
 337
 338         global_quad_port_a = 0;
 339
 340 #ifdef CONFIG_IGB_DCA
 341         dca_register_notify(&dca_notifier);
 342 #endif
 343
 344         ret = pci_register_driver(&igb_driver);
 345         return ret;
 346 }
 347
 348 module_init(igb_init_module);
 349
 350 /**
 351  * igb_exit_module - Driver Exit Cleanup Routine
 352  *
 353  * igb_exit_module is called just before the driver is removed
 354  * from memory.
 355  **/
 356 static void __exit igb_exit_module(void)
 357 {
 358 #ifdef CONFIG_IGB_DCA
 359         dca_unregister_notify(&dca_notifier);
 360 #endif
 361         pci_unregister_driver(&igb_driver);
 362 }
 363
 364 module_exit(igb_exit_module);
 365
 366 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 367 /**
 368  * igb_cache_ring_register - Descriptor ring to register mapping
 369  * @adapter: board private structure to initialize
 370  *
 371  * Once we know the feature-set enabled for the device, we'll cache
 372  * the register offset the descriptor ring is assigned to.
 373  **/
 374 static void igb_cache_ring_register(struct igb_adapter *adapter)
 375 {
 376         int i;
 377         unsigned int rbase_offset = adapter->vfs_allocated_count;
 378
 379         switch (adapter->hw.mac.type) {
 380         case e1000_82576:
 381                 /* The queues are allocated for virtualization such that VF 0
 382                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 383                  * In order to avoid collision we start at the first free queue
 384                  * and continue consuming queues in the same sequence
 385                  */
 386                 for (i = 0; i < adapter->num_rx_queues; i++)
 387                         adapter->rx_ring[i].reg_idx = rbase_offset +
 388                                                       Q_IDX_82576(i);
 389                 for (i = 0; i < adapter->num_tx_queues; i++)
 390                         adapter->tx_ring[i].reg_idx = rbase_offset +
 391                                                       Q_IDX_82576(i);
 392                 break;
 393         case e1000_82575:
 394         default:
 395                 for (i = 0; i < adapter->num_rx_queues; i++)
 396                         adapter->rx_ring[i].reg_idx = i;
 397                 for (i = 0; i < adapter->num_tx_queues; i++)
 398                         adapter->tx_ring[i].reg_idx = i;
 399                 break;
 400         }
 401 }
 402
 403 /**
 404  * igb_alloc_queues - Allocate memory for all rings
 405  * @adapter: board private structure to initialize
 406  *
 407  * We allocate one ring per queue at run-time since we don't know the
 408  * number of queues at compile-time.
 409  **/
 410 static int igb_alloc_queues(struct igb_adapter *adapter)
 411 {
 412         int i;
 413
 414         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 415                                    sizeof(struct igb_ring), GFP_KERNEL);
 416         if (!adapter->tx_ring)
 417                 return -ENOMEM;
 418
 419         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 420                                    sizeof(struct igb_ring), GFP_KERNEL);
 421         if (!adapter->rx_ring) {
 422                 kfree(adapter->tx_ring);
 423                 return -ENOMEM;
 424         }
 425
 426         adapter->rx_ring->buddy = adapter->tx_ring;
 427
 428         for (i = 0; i < adapter->num_tx_queues; i++) {
 429                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 430                 ring->count = adapter->tx_ring_count;
 431                 ring->adapter = adapter;
 432                 ring->queue_index = i;
 433         }
 434         for (i = 0; i < adapter->num_rx_queues; i++) {
 435                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 436                 ring->count = adapter->rx_ring_count;
 437                 ring->adapter = adapter;
 438                 ring->queue_index = i;
 439                 ring->itr_register = E1000_ITR;
 440
 441                 /* set a default napi handler for each rx_ring */
 442                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 443         }
 444
 445         igb_cache_ring_register(adapter);
 446         return 0;
 447 }
 448
 449 static void igb_free_queues(struct igb_adapter *adapter)
 450 {
 451         int i;
 452
 453         for (i = 0; i < adapter->num_rx_queues; i++)
 454                 netif_napi_del(&adapter->rx_ring[i].napi);
 455
 456         adapter->num_rx_queues = 0;
 457         adapter->num_tx_queues = 0;
 458
 459         kfree(adapter->tx_ring);
 460         kfree(adapter->rx_ring);
 461 }
 462
 463 #define IGB_N0_QUEUE -1
 464 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 465                               int tx_queue, int msix_vector)
 466 {
 467         u32 msixbm = 0;
 468         struct e1000_hw *hw = &adapter->hw;
 469         u32 ivar, index;
 470
 471         switch (hw->mac.type) {
 472         case e1000_82575:
 473                 /* The 82575 assigns vectors using a bitmask, which matches the
 474                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 475                    or more queues to a vector, we write the appropriate bits
 476                    into the MSIXBM register for that vector. */
 477                 if (rx_queue > IGB_N0_QUEUE) {
 478                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 479                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 480                 }
 481                 if (tx_queue > IGB_N0_QUEUE) {
 482                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 483                         adapter->tx_ring[tx_queue].eims_value =
 484                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 485                 }
 486                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 487                 break;
 488         case e1000_82576:
 489                 /* 82576 uses a table-based method for assigning vectors.
 490                    Each queue has a single entry in the table to which we write
 491                    a vector number along with a "valid" bit.  Sadly, the layout
 492                    of the table is somewhat counterintuitive. */
 493                 if (rx_queue > IGB_N0_QUEUE) {
 494                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 495                         ivar = array_rd32(E1000_IVAR0, index);
 496                         if (rx_queue & 0x1) {
 497                                 /* vector goes into third byte of register */
 498                                 ivar = ivar & 0xFF00FFFF;
 499                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 500                         } else {
 501                                 /* vector goes into low byte of register */
 502                                 ivar = ivar & 0xFFFFFF00;
 503                                 ivar |= msix_vector | E1000_IVAR_VALID;
 504                         }
 505                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 506                         array_wr32(E1000_IVAR0, index, ivar);
 507                 }
 508                 if (tx_queue > IGB_N0_QUEUE) {
 509                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 510                         ivar = array_rd32(E1000_IVAR0, index);
 511                         if (tx_queue & 0x1) {
 512                                 /* vector goes into high byte of register */
 513                                 ivar = ivar & 0x00FFFFFF;
 514                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 515                         } else {
 516                                 /* vector goes into second byte of register */
 517                                 ivar = ivar & 0xFFFF00FF;
 518                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 519                         }
 520                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 521                         array_wr32(E1000_IVAR0, index, ivar);
 522                 }
 523                 break;
 524         default:
 525                 BUG();
 526                 break;
 527         }
 528 }
 529
 530 /**
 531  * igb_configure_msix - Configure MSI-X hardware
 532  *
 533  * igb_configure_msix sets up the hardware to properly
 534  * generate MSI-X interrupts.
 535  **/
 536 static void igb_configure_msix(struct igb_adapter *adapter)
 537 {
 538         u32 tmp;
 539         int i, vector = 0;
 540         struct e1000_hw *hw = &adapter->hw;
 541
 542         adapter->eims_enable_mask = 0;
 543         if (hw->mac.type == e1000_82576)
 544                 /* Turn on MSI-X capability first, or our settings
 545                  * won't stick.  And it will take days to debug. */
 546                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 547                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 548                                    E1000_GPIE_NSICR);
 549
 550         for (i = 0; i < adapter->num_tx_queues; i++) {
 551                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 552                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 553                 adapter->eims_enable_mask |= tx_ring->eims_value;
 554                 if (tx_ring->itr_val)
 555                         writel(tx_ring->itr_val,
 556                                hw->hw_addr + tx_ring->itr_register);
 557                 else
 558                         writel(1, hw->hw_addr + tx_ring->itr_register);
 559         }
 560
 561         for (i = 0; i < adapter->num_rx_queues; i++) {
 562                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 563                 rx_ring->buddy = NULL;
 564                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 565                 adapter->eims_enable_mask |= rx_ring->eims_value;
 566                 if (rx_ring->itr_val)
 567                         writel(rx_ring->itr_val,
 568                                hw->hw_addr + rx_ring->itr_register);
 569                 else
 570                         writel(1, hw->hw_addr + rx_ring->itr_register);
 571         }
 572
 573
 574         /* set vector for other causes, i.e. link changes */
 575         switch (hw->mac.type) {
 576         case e1000_82575:
 577                 array_wr32(E1000_MSIXBM(0), vector++,
 578                                       E1000_EIMS_OTHER);
 579
 580                 tmp = rd32(E1000_CTRL_EXT);
 581                 /* enable MSI-X PBA support*/
 582                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 583
 584                 /* Auto-Mask interrupts upon ICR read. */
 585                 tmp |= E1000_CTRL_EXT_EIAME;
 586                 tmp |= E1000_CTRL_EXT_IRCA;
 587
 588                 wr32(E1000_CTRL_EXT, tmp);
 589                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 590                 adapter->eims_other = E1000_EIMS_OTHER;
 591
 592                 break;
 593
 594         case e1000_82576:
 595                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 596                 wr32(E1000_IVAR_MISC, tmp);
 597
 598                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 599                 adapter->eims_other = 1 << (vector - 1);
 600                 break;
 601         default:
 602                 /* do nothing, since nothing else supports MSI-X */
 603                 break;
 604         } /* switch (hw->mac.type) */
 605         wrfl();
 606 }
 607
 608 /**
 609  * igb_request_msix - Initialize MSI-X interrupts
 610  *
 611  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 612  * kernel.
 613  **/
 614 static int igb_request_msix(struct igb_adapter *adapter)
 615 {
 616         struct net_device *netdev = adapter->netdev;
 617         int i, err = 0, vector = 0;
 618
 619         vector = 0;
 620
 621         for (i = 0; i < adapter->num_tx_queues; i++) {
 622                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 623                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 624                 err = request_irq(adapter->msix_entries[vector].vector,
 625                                   &igb_msix_tx, 0, ring->name,
 626                                   &(adapter->tx_ring[i]));
 627                 if (err)
 628                         goto out;
 629                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 630                 ring->itr_val = 976; /* ~4000 ints/sec */
 631                 vector++;
 632         }
 633         for (i = 0; i < adapter->num_rx_queues; i++) {
 634                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 635                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 636                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 637                 else
 638                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 639                 err = request_irq(adapter->msix_entries[vector].vector,
 640                                   &igb_msix_rx, 0, ring->name,
 641                                   &(adapter->rx_ring[i]));
 642                 if (err)
 643                         goto out;
 644                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 645                 ring->itr_val = adapter->itr;
 646                 vector++;
 647         }
 648
 649         err = request_irq(adapter->msix_entries[vector].vector,
 650                           &igb_msix_other, 0, netdev->name, netdev);
 651         if (err)
 652                 goto out;
 653
 654         igb_configure_msix(adapter);
 655         return 0;
 656 out:
 657         return err;
 658 }
 659
 660 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 661 {
 662         if (adapter->msix_entries) {
 663                 pci_disable_msix(adapter->pdev);
 664                 kfree(adapter->msix_entries);
 665                 adapter->msix_entries = NULL;
 666         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 667                 pci_disable_msi(adapter->pdev);
 668         return;
 669 }
 670
 671
 672 /**
 673  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 674  *
 675  * Attempt to configure interrupts using the best available
 676  * capabilities of the hardware and kernel.
 677  **/
 678 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 679 {
 680         int err;
 681         int numvecs, i;
 682
 683         /* Number of supported queues. */
 684         /* Having more queues than CPUs doesn't make sense. */
 685         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 686         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 687
 688         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 689         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 690                                         GFP_KERNEL);
 691         if (!adapter->msix_entries)
 692                 goto msi_only;
 693
 694         for (i = 0; i < numvecs; i++)
 695                 adapter->msix_entries[i].entry = i;
 696
 697         err = pci_enable_msix(adapter->pdev,
 698                               adapter->msix_entries,
 699                               numvecs);
 700         if (err == 0)
 701                 goto out;
 702
 703         igb_reset_interrupt_capability(adapter);
 704
 705         /* If we can't do MSI-X, try MSI */
 706 msi_only:
 707 #ifdef CONFIG_PCI_IOV
 708         /* disable SR-IOV for non MSI-X configurations */
 709         if (adapter->vf_data) {
 710                 struct e1000_hw *hw = &adapter->hw;
 711                 /* disable iov and allow time for transactions to clear */
 712                 pci_disable_sriov(adapter->pdev);
 713                 msleep(500);
 714
 715                 kfree(adapter->vf_data);
 716                 adapter->vf_data = NULL;
 717                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 718                 msleep(100);
 719                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 720         }
 721 #endif
 722         adapter->num_rx_queues = 1;
 723         adapter->num_tx_queues = 1;
 724         if (!pci_enable_msi(adapter->pdev))
 725                 adapter->flags |= IGB_FLAG_HAS_MSI;
 726 out:
 727         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 728         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 729         return;
 730 }
 731
 732 /**
 733  * igb_request_irq - initialize interrupts
 734  *
 735  * Attempts to configure interrupts using the best available
 736  * capabilities of the hardware and kernel.
 737  **/
 738 static int igb_request_irq(struct igb_adapter *adapter)
 739 {
 740         struct net_device *netdev = adapter->netdev;
 741         struct e1000_hw *hw = &adapter->hw;
 742         int err = 0;
 743
 744         if (adapter->msix_entries) {
 745                 err = igb_request_msix(adapter);
 746                 if (!err)
 747                         goto request_done;
 748                 /* fall back to MSI */
 749                 igb_reset_interrupt_capability(adapter);
 750                 if (!pci_enable_msi(adapter->pdev))
 751                         adapter->flags |= IGB_FLAG_HAS_MSI;
 752                 igb_free_all_tx_resources(adapter);
 753                 igb_free_all_rx_resources(adapter);
 754                 adapter->num_rx_queues = 1;
 755                 igb_alloc_queues(adapter);
 756         } else {
 757                 switch (hw->mac.type) {
 758                 case e1000_82575:
 759                         wr32(E1000_MSIXBM(0),
 760                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 761                         break;
 762                 case e1000_82576:
 763                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 764                         break;
 765                 default:
 766                         break;
 767                 }
 768         }
 769
 770         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 771                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 772                                   netdev->name, netdev);
 773                 if (!err)
 774                         goto request_done;
 775                 /* fall back to legacy interrupts */
 776                 igb_reset_interrupt_capability(adapter);
 777                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 778         }
 779
 780         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 781                           netdev->name, netdev);
 782
 783         if (err)
 784                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 785                         err);
 786
 787 request_done:
 788         return err;
 789 }
 790
 791 static void igb_free_irq(struct igb_adapter *adapter)
 792 {
 793         struct net_device *netdev = adapter->netdev;
 794
 795         if (adapter->msix_entries) {
 796                 int vector = 0, i;
 797
 798                 for (i = 0; i < adapter->num_tx_queues; i++)
 799                         free_irq(adapter->msix_entries[vector++].vector,
 800                                 &(adapter->tx_ring[i]));
 801                 for (i = 0; i < adapter->num_rx_queues; i++)
 802                         free_irq(adapter->msix_entries[vector++].vector,
 803                                 &(adapter->rx_ring[i]));
 804
 805                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 806                 return;
 807         }
 808
 809         free_irq(adapter->pdev->irq, netdev);
 810 }
 811
 812 /**
 813  * igb_irq_disable - Mask off interrupt generation on the NIC
 814  * @adapter: board private structure
 815  **/
 816 static void igb_irq_disable(struct igb_adapter *adapter)
 817 {
 818         struct e1000_hw *hw = &adapter->hw;
 819
 820         if (adapter->msix_entries) {
 821                 wr32(E1000_EIAM, 0);
 822                 wr32(E1000_EIMC, ~0);
 823                 wr32(E1000_EIAC, 0);
 824         }
 825
 826         wr32(E1000_IAM, 0);
 827         wr32(E1000_IMC, ~0);
 828         wrfl();
 829         synchronize_irq(adapter->pdev->irq);
 830 }
 831
 832 /**
 833  * igb_irq_enable - Enable default interrupt generation settings
 834  * @adapter: board private structure
 835  **/
 836 static void igb_irq_enable(struct igb_adapter *adapter)
 837 {
 838         struct e1000_hw *hw = &adapter->hw;
 839
 840         if (adapter->msix_entries) {
 841                 wr32(E1000_EIAC, adapter->eims_enable_mask);
 842                 wr32(E1000_EIAM, adapter->eims_enable_mask);
 843                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 844                 if (adapter->vfs_allocated_count)
 845                         wr32(E1000_MBVFIMR, 0xFF);
 846                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 847                                  E1000_IMS_DOUTSYNC));
 848         } else {
 849                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 850                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 851         }
 852 }
 853
 854 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 855 {
 856         struct net_device *netdev = adapter->netdev;
 857         u16 vid = adapter->hw.mng_cookie.vlan_id;
 858         u16 old_vid = adapter->mng_vlan_id;
 859         if (adapter->vlgrp) {
 860                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 861                         if (adapter->hw.mng_cookie.status &
 862                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 863                                 igb_vlan_rx_add_vid(netdev, vid);
 864                                 adapter->mng_vlan_id = vid;
 865                         } else
 866                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 867
 868                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 869                                         (vid != old_vid) &&
 870                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 871                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 872                 } else
 873                         adapter->mng_vlan_id = vid;
 874         }
 875 }
 876
 877 /**
 878  * igb_release_hw_control - release control of the h/w to f/w
 879  * @adapter: address of board private structure
 880  *
 881  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 882  * For ASF and Pass Through versions of f/w this means that the
 883  * driver is no longer loaded.
 884  *
 885  **/
 886 static void igb_release_hw_control(struct igb_adapter *adapter)
 887 {
 888         struct e1000_hw *hw = &adapter->hw;
 889         u32 ctrl_ext;
 890
 891         /* Let firmware take over control of h/w */
 892         ctrl_ext = rd32(E1000_CTRL_EXT);
 893         wr32(E1000_CTRL_EXT,
 894                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 895 }
 896
 897
 898 /**
 899  * igb_get_hw_control - get control of the h/w from f/w
 900  * @adapter: address of board private structure
 901  *
 902  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 903  * For ASF and Pass Through versions of f/w this means that
 904  * the driver is loaded.
 905  *
 906  **/
 907 static void igb_get_hw_control(struct igb_adapter *adapter)
 908 {
 909         struct e1000_hw *hw = &adapter->hw;
 910         u32 ctrl_ext;
 911
 912         /* Let firmware know the driver has taken over */
 913         ctrl_ext = rd32(E1000_CTRL_EXT);
 914         wr32(E1000_CTRL_EXT,
 915                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 916 }
 917
 918 /**
 919  * igb_configure - configure the hardware for RX and TX
 920  * @adapter: private board structure
 921  **/
 922 static void igb_configure(struct igb_adapter *adapter)
 923 {
 924         struct net_device *netdev = adapter->netdev;
 925         int i;
 926
 927         igb_get_hw_control(adapter);
 928         igb_set_multi(netdev);
 929
 930         igb_restore_vlan(adapter);
 931
 932         igb_configure_tx(adapter);
 933         igb_setup_rctl(adapter);
 934         igb_configure_rx(adapter);
 935
 936         igb_rx_fifo_flush_82575(&adapter->hw);
 937
 938         /* call igb_desc_unused which always leaves
 939          * at least 1 descriptor unused to make sure
 940          * next_to_use != next_to_clean */
 941         for (i = 0; i < adapter->num_rx_queues; i++) {
 942                 struct igb_ring *ring = &adapter->rx_ring[i];
 943                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 944         }
 945
 946
 947         adapter->tx_queue_len = netdev->tx_queue_len;
 948 }
 949
 950
 951 /**
 952  * igb_up - Open the interface and prepare it to handle traffic
 953  * @adapter: board private structure
 954  **/
 955
 956 int igb_up(struct igb_adapter *adapter)
 957 {
 958         struct e1000_hw *hw = &adapter->hw;
 959         int i;
 960
 961         /* hardware has been reset, we need to reload some things */
 962         igb_configure(adapter);
 963
 964         clear_bit(__IGB_DOWN, &adapter->state);
 965
 966         for (i = 0; i < adapter->num_rx_queues; i++)
 967                 napi_enable(&adapter->rx_ring[i].napi);
 968         if (adapter->msix_entries)
 969                 igb_configure_msix(adapter);
 970
 971         igb_vmm_control(adapter);
 972         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 973         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 974
 975         /* Clear any pending interrupts. */
 976         rd32(E1000_ICR);
 977         igb_irq_enable(adapter);
 978
 979         netif_tx_start_all_queues(adapter->netdev);
 980
 981         /* Fire a link change interrupt to start the watchdog. */
 982         wr32(E1000_ICS, E1000_ICS_LSC);
 983         return 0;
 984 }
 985
 986 void igb_down(struct igb_adapter *adapter)
 987 {
 988         struct e1000_hw *hw = &adapter->hw;
 989         struct net_device *netdev = adapter->netdev;
 990         u32 tctl, rctl;
 991         int i;
 992
 993         /* signal that we're down so the interrupt handler does not
 994          * reschedule our watchdog timer */
 995         set_bit(__IGB_DOWN, &adapter->state);
 996
 997         /* disable receives in the hardware */
 998         rctl = rd32(E1000_RCTL);
 999         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1000         /* flush and sleep below */
1001
1002         netif_tx_stop_all_queues(netdev);
1003
1004         /* disable transmits in the hardware */
1005         tctl = rd32(E1000_TCTL);
1006         tctl &= ~E1000_TCTL_EN;
1007         wr32(E1000_TCTL, tctl);
1008         /* flush both disables and wait for them to finish */
1009         wrfl();
1010         msleep(10);
1011
1012         for (i = 0; i < adapter->num_rx_queues; i++)
1013                 napi_disable(&adapter->rx_ring[i].napi);
1014
1015         igb_irq_disable(adapter);
1016
1017         del_timer_sync(&adapter->watchdog_timer);
1018         del_timer_sync(&adapter->phy_info_timer);
1019
1020         netdev->tx_queue_len = adapter->tx_queue_len;
1021         netif_carrier_off(netdev);
1022
1023         /* record the stats before reset*/
1024         igb_update_stats(adapter);
1025
1026         adapter->link_speed = 0;
1027         adapter->link_duplex = 0;
1028
1029         if (!pci_channel_offline(adapter->pdev))
1030                 igb_reset(adapter);
1031         igb_clean_all_tx_rings(adapter);
1032         igb_clean_all_rx_rings(adapter);
1033 #ifdef CONFIG_IGB_DCA
1034
1035         /* since we reset the hardware DCA settings were cleared */
1036         igb_setup_dca(adapter);
1037 #endif
1038 }
1039
1040 void igb_reinit_locked(struct igb_adapter *adapter)
1041 {
1042         WARN_ON(in_interrupt());
1043         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1044                 msleep(1);
1045         igb_down(adapter);
1046         igb_up(adapter);
1047         clear_bit(__IGB_RESETTING, &adapter->state);
1048 }
1049
1050 void igb_reset(struct igb_adapter *adapter)
1051 {
1052         struct e1000_hw *hw = &adapter->hw;
1053         struct e1000_mac_info *mac = &hw->mac;
1054         struct e1000_fc_info *fc = &hw->fc;
1055         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1056         u16 hwm;
1057
1058         /* Repartition Pba for greater than 9k mtu
1059          * To take effect CTRL.RST is required.
1060          */
1061         switch (mac->type) {
1062         case e1000_82576:
1063                 pba = E1000_PBA_64K;
1064                 break;
1065         case e1000_82575:
1066         default:
1067                 pba = E1000_PBA_34K;
1068                 break;
1069         }
1070
1071         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1072             (mac->type < e1000_82576)) {
1073                 /* adjust PBA for jumbo frames */
1074                 wr32(E1000_PBA, pba);
1075
1076                 /* To maintain wire speed transmits, the Tx FIFO should be
1077                  * large enough to accommodate two full transmit packets,
1078                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1079                  * the Rx FIFO should be large enough to accommodate at least
1080                  * one full receive packet and is similarly rounded up and
1081                  * expressed in KB. */
1082                 pba = rd32(E1000_PBA);
1083                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1084                 tx_space = pba >> 16;
1085                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1086                 pba &= 0xffff;
1087                 /* the tx fifo also stores 16 bytes of information about the tx
1088                  * but don't include ethernet FCS because hardware appends it */
1089                 min_tx_space = (adapter->max_frame_size +
1090                                 sizeof(union e1000_adv_tx_desc) -
1091                                 ETH_FCS_LEN) * 2;
1092                 min_tx_space = ALIGN(min_tx_space, 1024);
1093                 min_tx_space >>= 10;
1094                 /* software strips receive CRC, so leave room for it */
1095                 min_rx_space = adapter->max_frame_size;
1096                 min_rx_space = ALIGN(min_rx_space, 1024);
1097                 min_rx_space >>= 10;
1098
1099                 /* If current Tx allocation is less than the min Tx FIFO size,
1100                  * and the min Tx FIFO size is less than the current Rx FIFO
1101                  * allocation, take space away from current Rx allocation */
1102                 if (tx_space < min_tx_space &&
1103                     ((min_tx_space - tx_space) < pba)) {
1104                         pba = pba - (min_tx_space - tx_space);
1105
1106                         /* if short on rx space, rx wins and must trump tx
1107                          * adjustment */
1108                         if (pba < min_rx_space)
1109                                 pba = min_rx_space;
1110                 }
1111                 wr32(E1000_PBA, pba);
1112         }
1113
1114         /* flow control settings */
1115         /* The high water mark must be low enough to fit one full frame
1116          * (or the size used for early receive) above it in the Rx FIFO.
1117          * Set it to the lower of:
1118          * - 90% of the Rx FIFO size, or
1119          * - the full Rx FIFO size minus one full frame */
1120         hwm = min(((pba << 10) * 9 / 10),
1121                         ((pba << 10) - 2 * adapter->max_frame_size));
1122
1123         if (mac->type < e1000_82576) {
1124                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1125                 fc->low_water = fc->high_water - 8;
1126         } else {
1127                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1128                 fc->low_water = fc->high_water - 16;
1129         }
1130         fc->pause_time = 0xFFFF;
1131         fc->send_xon = 1;
1132         fc->type = fc->original_type;
1133
1134         /* disable receive for all VFs and wait one second */
1135         if (adapter->vfs_allocated_count) {
1136                 int i;
1137                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1138                         adapter->vf_data[i].clear_to_send = false;
1139
1140                 /* ping all the active vfs to let them know we are going down */
1141                         igb_ping_all_vfs(adapter);
1142
1143                 /* disable transmits and receives */
1144                 wr32(E1000_VFRE, 0);
1145                 wr32(E1000_VFTE, 0);
1146         }
1147
1148         /* Allow time for pending master requests to run */
1149         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1150         wr32(E1000_WUC, 0);
1151
1152         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1153                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1154
1155         igb_update_mng_vlan(adapter);
1156
1157         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1158         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1159
1160         igb_reset_adaptive(&adapter->hw);
1161         igb_get_phy_info(&adapter->hw);
1162 }
1163
1164 static const struct net_device_ops igb_netdev_ops = {
1165         .ndo_open               = igb_open,
1166         .ndo_stop               = igb_close,
1167         .ndo_start_xmit         = igb_xmit_frame_adv,
1168         .ndo_get_stats          = igb_get_stats,
1169         .ndo_set_multicast_list = igb_set_multi,
1170         .ndo_set_mac_address    = igb_set_mac,
1171         .ndo_change_mtu         = igb_change_mtu,
1172         .ndo_do_ioctl           = igb_ioctl,
1173         .ndo_tx_timeout         = igb_tx_timeout,
1174         .ndo_validate_addr      = eth_validate_addr,
1175         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1176         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1177         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1178 #ifdef CONFIG_NET_POLL_CONTROLLER
1179         .ndo_poll_controller    = igb_netpoll,
1180 #endif
1181 };
1182
1183 /**
1184  * igb_probe - Device Initialization Routine
1185  * @pdev: PCI device information struct
1186  * @ent: entry in igb_pci_tbl
1187  *
1188  * Returns 0 on success, negative on failure
1189  *
1190  * igb_probe initializes an adapter identified by a pci_dev structure.
1191  * The OS initialization, configuring of the adapter private structure,
1192  * and a hardware reset occur.
1193  **/
1194 static int __devinit igb_probe(struct pci_dev *pdev,
1195                                const struct pci_device_id *ent)
1196 {
1197         struct net_device *netdev;
1198         struct igb_adapter *adapter;
1199         struct e1000_hw *hw;
1200         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1201         unsigned long mmio_start, mmio_len;
1202         int err, pci_using_dac;
1203         u16 eeprom_data = 0;
1204         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1205         u32 part_num;
1206
1207         err = pci_enable_device_mem(pdev);
1208         if (err)
1209                 return err;
1210
1211         pci_using_dac = 0;
1212         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1213         if (!err) {
1214                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1215                 if (!err)
1216                         pci_using_dac = 1;
1217         } else {
1218                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1219                 if (err) {
1220                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1221                         if (err) {
1222                                 dev_err(&pdev->dev, "No usable DMA "
1223                                         "configuration, aborting\n");
1224                                 goto err_dma;
1225                         }
1226                 }
1227         }
1228
1229         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1230                                            IORESOURCE_MEM),
1231                                            igb_driver_name);
1232         if (err)
1233                 goto err_pci_reg;
1234
1235         err = pci_enable_pcie_error_reporting(pdev);
1236         if (err) {
1237                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1238                         "0x%x\n", err);
1239                 /* non-fatal, continue */
1240         }
1241
1242         pci_set_master(pdev);
1243         pci_save_state(pdev);
1244
1245         err = -ENOMEM;
1246         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1247                                    IGB_ABS_MAX_TX_QUEUES);
1248         if (!netdev)
1249                 goto err_alloc_etherdev;
1250
1251         SET_NETDEV_DEV(netdev, &pdev->dev);
1252
1253         pci_set_drvdata(pdev, netdev);
1254         adapter = netdev_priv(netdev);
1255         adapter->netdev = netdev;
1256         adapter->pdev = pdev;
1257         hw = &adapter->hw;
1258         hw->back = adapter;
1259         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1260
1261         mmio_start = pci_resource_start(pdev, 0);
1262         mmio_len = pci_resource_len(pdev, 0);
1263
1264         err = -EIO;
1265         hw->hw_addr = ioremap(mmio_start, mmio_len);
1266         if (!hw->hw_addr)
1267                 goto err_ioremap;
1268
1269         netdev->netdev_ops = &igb_netdev_ops;
1270         igb_set_ethtool_ops(netdev);
1271         netdev->watchdog_timeo = 5 * HZ;
1272
1273         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1274
1275         netdev->mem_start = mmio_start;
1276         netdev->mem_end = mmio_start + mmio_len;
1277
1278         /* PCI config space info */
1279         hw->vendor_id = pdev->vendor;
1280         hw->device_id = pdev->device;
1281         hw->revision_id = pdev->revision;
1282         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1283         hw->subsystem_device_id = pdev->subsystem_device;
1284
1285         /* setup the private structure */
1286         hw->back = adapter;
1287         /* Copy the default MAC, PHY and NVM function pointers */
1288         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1289         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1290         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1291         /* Initialize skew-specific constants */
1292         err = ei->get_invariants(hw);
1293         if (err)
1294                 goto err_sw_init;
1295
1296 #ifdef CONFIG_PCI_IOV
1297         /* since iov functionality isn't critical to base device function we
1298          * can accept failure.  If it fails we don't allow iov to be enabled */
1299         if (hw->mac.type == e1000_82576) {
1300                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1301                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1302                 int i;
1303                 unsigned char mac_addr[ETH_ALEN];
1304
1305                 if (num_vfs) {
1306                         adapter->vf_data = kcalloc(num_vfs,
1307                                                 sizeof(struct vf_data_storage),
1308                                                 GFP_KERNEL);
1309                         if (!adapter->vf_data) {
1310                                 dev_err(&pdev->dev,
1311                                         "Could not allocate VF private data - "
1312                                         "IOV enable failed\n");
1313                         } else {
1314                                 err = pci_enable_sriov(pdev, num_vfs);
1315                                 if (!err) {
1316                                         adapter->vfs_allocated_count = num_vfs;
1317                                         dev_info(&pdev->dev,
1318                                                  "%d vfs allocated\n",
1319                                                  num_vfs);
1320                                         for (i = 0;
1321                                              i < adapter->vfs_allocated_count;
1322                                              i++) {
1323                                                 random_ether_addr(mac_addr);
1324                                                 igb_set_vf_mac(adapter, i,
1325                                                                mac_addr);
1326                                         }
1327                                 } else {
1328                                         kfree(adapter->vf_data);
1329                                         adapter->vf_data = NULL;
1330                                 }
1331                         }
1332                 }
1333         }
1334
1335 #endif
1336         /* setup the private structure */
1337         err = igb_sw_init(adapter);
1338         if (err)
1339                 goto err_sw_init;
1340
1341         igb_get_bus_info_pcie(hw);
1342
1343         /* set flags */
1344         switch (hw->mac.type) {
1345         case e1000_82575:
1346                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1347                 break;
1348         case e1000_82576:
1349         default:
1350                 break;
1351         }
1352
1353         hw->phy.autoneg_wait_to_complete = false;
1354         hw->mac.adaptive_ifs = true;
1355
1356         /* Copper options */
1357         if (hw->phy.media_type == e1000_media_type_copper) {
1358                 hw->phy.mdix = AUTO_ALL_MODES;
1359                 hw->phy.disable_polarity_correction = false;
1360                 hw->phy.ms_type = e1000_ms_hw_default;
1361         }
1362
1363         if (igb_check_reset_block(hw))
1364                 dev_info(&pdev->dev,
1365                         "PHY reset is blocked due to SOL/IDER session.\n");
1366
1367         netdev->features = NETIF_F_SG |
1368                            NETIF_F_IP_CSUM |
1369                            NETIF_F_HW_VLAN_TX |
1370                            NETIF_F_HW_VLAN_RX |
1371                            NETIF_F_HW_VLAN_FILTER;
1372
1373         netdev->features |= NETIF_F_IPV6_CSUM;
1374         netdev->features |= NETIF_F_TSO;
1375         netdev->features |= NETIF_F_TSO6;
1376
1377         netdev->features |= NETIF_F_GRO;
1378
1379         netdev->vlan_features |= NETIF_F_TSO;
1380         netdev->vlan_features |= NETIF_F_TSO6;
1381         netdev->vlan_features |= NETIF_F_IP_CSUM;
1382         netdev->vlan_features |= NETIF_F_SG;
1383
1384         if (pci_using_dac)
1385                 netdev->features |= NETIF_F_HIGHDMA;
1386
1387         if (adapter->hw.mac.type == e1000_82576)
1388                 netdev->features |= NETIF_F_SCTP_CSUM;
1389
1390         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1391
1392         /* before reading the NVM, reset the controller to put the device in a
1393          * known good starting state */
1394         hw->mac.ops.reset_hw(hw);
1395
1396         /* make sure the NVM is good */
1397         if (igb_validate_nvm_checksum(hw) < 0) {
1398                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1399                 err = -EIO;
1400                 goto err_eeprom;
1401         }
1402
1403         /* copy the MAC address out of the NVM */
1404         if (hw->mac.ops.read_mac_addr(hw))
1405                 dev_err(&pdev->dev, "NVM Read Error\n");
1406
1407         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1408         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1409
1410         if (!is_valid_ether_addr(netdev->perm_addr)) {
1411                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1412                 err = -EIO;
1413                 goto err_eeprom;
1414         }
1415
1416         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1417                     (unsigned long) adapter);
1418         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1419                     (unsigned long) adapter);
1420
1421         INIT_WORK(&adapter->reset_task, igb_reset_task);
1422         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1423
1424         /* Initialize link properties that are user-changeable */
1425         adapter->fc_autoneg = true;
1426         hw->mac.autoneg = true;
1427         hw->phy.autoneg_advertised = 0x2f;
1428
1429         hw->fc.original_type = e1000_fc_default;
1430         hw->fc.type = e1000_fc_default;
1431
1432         adapter->itr_setting = IGB_DEFAULT_ITR;
1433         adapter->itr = IGB_START_ITR;
1434
1435         igb_validate_mdi_setting(hw);
1436
1437         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1438          * enable the ACPI Magic Packet filter
1439          */
1440
1441         if (hw->bus.func == 0)
1442                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1443         else if (hw->bus.func == 1)
1444                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1445
1446         if (eeprom_data & eeprom_apme_mask)
1447                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1448
1449         /* now that we have the eeprom settings, apply the special cases where
1450          * the eeprom may be wrong or the board simply won't support wake on
1451          * lan on a particular port */
1452         switch (pdev->device) {
1453         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1454                 adapter->eeprom_wol = 0;
1455                 break;
1456         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1457         case E1000_DEV_ID_82576_FIBER:
1458         case E1000_DEV_ID_82576_SERDES:
1459                 /* Wake events only supported on port A for dual fiber
1460                  * regardless of eeprom setting */
1461                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1462                         adapter->eeprom_wol = 0;
1463                 break;
1464         case E1000_DEV_ID_82576_QUAD_COPPER:
1465                 /* if quad port adapter, disable WoL on all but port A */
1466                 if (global_quad_port_a != 0)
1467                         adapter->eeprom_wol = 0;
1468                 else
1469                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1470                 /* Reset for multiple quad port adapters */
1471                 if (++global_quad_port_a == 4)
1472                         global_quad_port_a = 0;
1473                 break;
1474         }
1475
1476         /* initialize the wol settings based on the eeprom settings */
1477         adapter->wol = adapter->eeprom_wol;
1478         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1479
1480         /* reset the hardware with the new settings */
1481         igb_reset(adapter);
1482
1483         /* let the f/w know that the h/w is now under the control of the
1484          * driver. */
1485         igb_get_hw_control(adapter);
1486
1487         strcpy(netdev->name, "eth%d");
1488         err = register_netdev(netdev);
1489         if (err)
1490                 goto err_register;
1491
1492         /* carrier off reporting is important to ethtool even BEFORE open */
1493         netif_carrier_off(netdev);
1494
1495 #ifdef CONFIG_IGB_DCA
1496         if (dca_add_requester(&pdev->dev) == 0) {
1497                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1498                 dev_info(&pdev->dev, "DCA enabled\n");
1499                 igb_setup_dca(adapter);
1500         }
1501 #endif
1502
1503         /*
1504          * Initialize hardware timer: we keep it running just in case
1505          * that some program needs it later on.
1506          */
1507         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1508         adapter->cycles.read = igb_read_clock;
1509         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1510         adapter->cycles.mult = 1;
1511         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1512         wr32(E1000_TIMINCA,
1513              (1<<24) |
1514              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1515 #if 0
1516         /*
1517          * Avoid rollover while we initialize by resetting the time counter.
1518          */
1519         wr32(E1000_SYSTIML, 0x00000000);
1520         wr32(E1000_SYSTIMH, 0x00000000);
1521 #else
1522         /*
1523          * Set registers so that rollover occurs soon to test this.
1524          */
1525         wr32(E1000_SYSTIML, 0x00000000);
1526         wr32(E1000_SYSTIMH, 0xFF800000);
1527 #endif
1528         wrfl();
1529         timecounter_init(&adapter->clock,
1530                          &adapter->cycles,
1531                          ktime_to_ns(ktime_get_real()));
1532
1533         /*
1534          * Synchronize our NIC clock against system wall clock. NIC
1535          * time stamp reading requires ~3us per sample, each sample
1536          * was pretty stable even under load => only require 10
1537          * samples for each offset comparison.
1538          */
1539         memset(&adapter->compare, 0, sizeof(adapter->compare));
1540         adapter->compare.source = &adapter->clock;
1541         adapter->compare.target = ktime_get_real;
1542         adapter->compare.num_samples = 10;
1543         timecompare_update(&adapter->compare, 0);
1544
1545 #ifdef DEBUG
1546         {
1547                 char buffer[160];
1548                 printk(KERN_DEBUG
1549                         "igb: %s: hw %p initialized timer\n",
1550                         igb_get_time_str(adapter, buffer),
1551                         &adapter->hw);
1552         }
1553 #endif
1554
1555         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1556         /* print bus type/speed/width info */
1557         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1558                  netdev->name,
1559                  ((hw->bus.speed == e1000_bus_speed_2500)
1560                   ? "2.5Gb/s" : "unknown"),
1561                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1562                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1563                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1564                    "unknown"),
1565                  netdev->dev_addr);
1566
1567         igb_read_part_num(hw, &part_num);
1568         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1569                 (part_num >> 8), (part_num & 0xff));
1570
1571         dev_info(&pdev->dev,
1572                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1573                 adapter->msix_entries ? "MSI-X" :
1574                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1575                 adapter->num_rx_queues, adapter->num_tx_queues);
1576
1577         return 0;
1578
1579 err_register:
1580         igb_release_hw_control(adapter);
1581 err_eeprom:
1582         if (!igb_check_reset_block(hw))
1583                 igb_reset_phy(hw);
1584
1585         if (hw->flash_address)
1586                 iounmap(hw->flash_address);
1587
1588         igb_free_queues(adapter);
1589 err_sw_init:
1590         iounmap(hw->hw_addr);
1591 err_ioremap:
1592         free_netdev(netdev);
1593 err_alloc_etherdev:
1594         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1595                                      IORESOURCE_MEM));
1596 err_pci_reg:
1597 err_dma:
1598         pci_disable_device(pdev);
1599         return err;
1600 }
1601
1602 /**
1603  * igb_remove - Device Removal Routine
1604  * @pdev: PCI device information struct
1605  *
1606  * igb_remove is called by the PCI subsystem to alert the driver
1607  * that it should release a PCI device.  The could be caused by a
1608  * Hot-Plug event, or because the driver is going to be removed from
1609  * memory.
1610  **/
1611 static void __devexit igb_remove(struct pci_dev *pdev)
1612 {
1613         struct net_device *netdev = pci_get_drvdata(pdev);
1614         struct igb_adapter *adapter = netdev_priv(netdev);
1615         struct e1000_hw *hw = &adapter->hw;
1616         int err;
1617
1618         /* flush_scheduled work may reschedule our watchdog task, so
1619          * explicitly disable watchdog tasks from being rescheduled  */
1620         set_bit(__IGB_DOWN, &adapter->state);
1621         del_timer_sync(&adapter->watchdog_timer);
1622         del_timer_sync(&adapter->phy_info_timer);
1623
1624         flush_scheduled_work();
1625
1626 #ifdef CONFIG_IGB_DCA
1627         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1628                 dev_info(&pdev->dev, "DCA disabled\n");
1629                 dca_remove_requester(&pdev->dev);
1630                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1631                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1632         }
1633 #endif
1634
1635         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1636          * would have already happened in close and is redundant. */
1637         igb_release_hw_control(adapter);
1638
1639         unregister_netdev(netdev);
1640
1641         if (!igb_check_reset_block(&adapter->hw))
1642                 igb_reset_phy(&adapter->hw);
1643
1644         igb_reset_interrupt_capability(adapter);
1645
1646         igb_free_queues(adapter);
1647
1648 #ifdef CONFIG_PCI_IOV
1649         /* reclaim resources allocated to VFs */
1650         if (adapter->vf_data) {
1651                 /* disable iov and allow time for transactions to clear */
1652                 pci_disable_sriov(pdev);
1653                 msleep(500);
1654
1655                 kfree(adapter->vf_data);
1656                 adapter->vf_data = NULL;
1657                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1658                 msleep(100);
1659                 dev_info(&pdev->dev, "IOV Disabled\n");
1660         }
1661 #endif
1662         iounmap(hw->hw_addr);
1663         if (hw->flash_address)
1664                 iounmap(hw->flash_address);
1665         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1666                                      IORESOURCE_MEM));
1667
1668         free_netdev(netdev);
1669
1670         err = pci_disable_pcie_error_reporting(pdev);
1671         if (err)
1672                 dev_err(&pdev->dev,
1673                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1674
1675         pci_disable_device(pdev);
1676 }
1677
1678 /**
1679  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1680  * @adapter: board private structure to initialize
1681  *
1682  * igb_sw_init initializes the Adapter private data structure.
1683  * Fields are initialized based on PCI device information and
1684  * OS network device settings (MTU size).
1685  **/
1686 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1687 {
1688         struct e1000_hw *hw = &adapter->hw;
1689         struct net_device *netdev = adapter->netdev;
1690         struct pci_dev *pdev = adapter->pdev;
1691
1692         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1693
1694         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1695         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1696         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1697         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1698         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1699         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1700
1701         /* This call may decrease the number of queues depending on
1702          * interrupt mode. */
1703         igb_set_interrupt_capability(adapter);
1704
1705         if (igb_alloc_queues(adapter)) {
1706                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1707                 return -ENOMEM;
1708         }
1709
1710         /* Explicitly disable IRQ since the NIC can be in any state. */
1711         igb_irq_disable(adapter);
1712
1713         set_bit(__IGB_DOWN, &adapter->state);
1714         return 0;
1715 }
1716
1717 /**
1718  * igb_open - Called when a network interface is made active
1719  * @netdev: network interface device structure
1720  *
1721  * Returns 0 on success, negative value on failure
1722  *
1723  * The open entry point is called when a network interface is made
1724  * active by the system (IFF_UP).  At this point all resources needed
1725  * for transmit and receive operations are allocated, the interrupt
1726  * handler is registered with the OS, the watchdog timer is started,
1727  * and the stack is notified that the interface is ready.
1728  **/
1729 static int igb_open(struct net_device *netdev)
1730 {
1731         struct igb_adapter *adapter = netdev_priv(netdev);
1732         struct e1000_hw *hw = &adapter->hw;
1733         int err;
1734         int i;
1735
1736         /* disallow open during test */
1737         if (test_bit(__IGB_TESTING, &adapter->state))
1738                 return -EBUSY;
1739
1740         netif_carrier_off(netdev);
1741
1742         /* allocate transmit descriptors */
1743         err = igb_setup_all_tx_resources(adapter);
1744         if (err)
1745                 goto err_setup_tx;
1746
1747         /* allocate receive descriptors */
1748         err = igb_setup_all_rx_resources(adapter);
1749         if (err)
1750                 goto err_setup_rx;
1751
1752         /* e1000_power_up_phy(adapter); */
1753
1754         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1755         if ((adapter->hw.mng_cookie.status &
1756              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1757                 igb_update_mng_vlan(adapter);
1758
1759         /* before we allocate an interrupt, we must be ready to handle it.
1760          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1761          * as soon as we call pci_request_irq, so we have to setup our
1762          * clean_rx handler before we do so.  */
1763         igb_configure(adapter);
1764
1765         igb_vmm_control(adapter);
1766         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1767         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1768
1769         err = igb_request_irq(adapter);
1770         if (err)
1771                 goto err_req_irq;
1772
1773         /* From here on the code is the same as igb_up() */
1774         clear_bit(__IGB_DOWN, &adapter->state);
1775
1776         for (i = 0; i < adapter->num_rx_queues; i++)
1777                 napi_enable(&adapter->rx_ring[i].napi);
1778
1779         /* Clear any pending interrupts. */
1780         rd32(E1000_ICR);
1781
1782         igb_irq_enable(adapter);
1783
1784         netif_tx_start_all_queues(netdev);
1785
1786         /* Fire a link status change interrupt to start the watchdog. */
1787         wr32(E1000_ICS, E1000_ICS_LSC);
1788
1789         return 0;
1790
1791 err_req_irq:
1792         igb_release_hw_control(adapter);
1793         /* e1000_power_down_phy(adapter); */
1794         igb_free_all_rx_resources(adapter);
1795 err_setup_rx:
1796         igb_free_all_tx_resources(adapter);
1797 err_setup_tx:
1798         igb_reset(adapter);
1799
1800         return err;
1801 }
1802
1803 /**
1804  * igb_close - Disables a network interface
1805  * @netdev: network interface device structure
1806  *
1807  * Returns 0, this is not allowed to fail
1808  *
1809  * The close entry point is called when an interface is de-activated
1810  * by the OS.  The hardware is still under the driver's control, but
1811  * needs to be disabled.  A global MAC reset is issued to stop the
1812  * hardware, and all transmit and receive resources are freed.
1813  **/
1814 static int igb_close(struct net_device *netdev)
1815 {
1816         struct igb_adapter *adapter = netdev_priv(netdev);
1817
1818         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1819         igb_down(adapter);
1820
1821         igb_free_irq(adapter);
1822
1823         igb_free_all_tx_resources(adapter);
1824         igb_free_all_rx_resources(adapter);
1825
1826         /* kill manageability vlan ID if supported, but not if a vlan with
1827          * the same ID is registered on the host OS (let 8021q kill it) */
1828         if ((adapter->hw.mng_cookie.status &
1829                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1830              !(adapter->vlgrp &&
1831                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1832                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1833
1834         return 0;
1835 }
1836
1837 /**
1838  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1839  * @adapter: board private structure
1840  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1841  *
1842  * Return 0 on success, negative on failure
1843  **/
1844 int igb_setup_tx_resources(struct igb_adapter *adapter,
1845                            struct igb_ring *tx_ring)
1846 {
1847         struct pci_dev *pdev = adapter->pdev;
1848         int size;
1849
1850         size = sizeof(struct igb_buffer) * tx_ring->count;
1851         tx_ring->buffer_info = vmalloc(size);
1852         if (!tx_ring->buffer_info)
1853                 goto err;
1854         memset(tx_ring->buffer_info, 0, size);
1855
1856         /* round up to nearest 4K */
1857         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1858         tx_ring->size = ALIGN(tx_ring->size, 4096);
1859
1860         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1861                                              &tx_ring->dma);
1862
1863         if (!tx_ring->desc)
1864                 goto err;
1865
1866         tx_ring->adapter = adapter;
1867         tx_ring->next_to_use = 0;
1868         tx_ring->next_to_clean = 0;
1869         return 0;
1870
1871 err:
1872         vfree(tx_ring->buffer_info);
1873         dev_err(&adapter->pdev->dev,
1874                 "Unable to allocate memory for the transmit descriptor ring\n");
1875         return -ENOMEM;
1876 }
1877
1878 /**
1879  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1880  *                                (Descriptors) for all queues
1881  * @adapter: board private structure
1882  *
1883  * Return 0 on success, negative on failure
1884  **/
1885 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1886 {
1887         int i, err = 0;
1888         int r_idx;
1889
1890         for (i = 0; i < adapter->num_tx_queues; i++) {
1891                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1892                 if (err) {
1893                         dev_err(&adapter->pdev->dev,
1894                                 "Allocation for Tx Queue %u failed\n", i);
1895                         for (i--; i >= 0; i--)
1896                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1897                         break;
1898                 }
1899         }
1900
1901         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1902                 r_idx = i % adapter->num_tx_queues;
1903                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1904         }
1905         return err;
1906 }
1907
1908 /**
1909  * igb_configure_tx - Configure transmit Unit after Reset
1910  * @adapter: board private structure
1911  *
1912  * Configure the Tx unit of the MAC after a reset.
1913  **/
1914 static void igb_configure_tx(struct igb_adapter *adapter)
1915 {
1916         u64 tdba;
1917         struct e1000_hw *hw = &adapter->hw;
1918         u32 tctl;
1919         u32 txdctl, txctrl;
1920         int i, j;
1921
1922         for (i = 0; i < adapter->num_tx_queues; i++) {
1923                 struct igb_ring *ring = &adapter->tx_ring[i];
1924                 j = ring->reg_idx;
1925                 wr32(E1000_TDLEN(j),
1926                      ring->count * sizeof(union e1000_adv_tx_desc));
1927                 tdba = ring->dma;
1928                 wr32(E1000_TDBAL(j),
1929                      tdba & 0x00000000ffffffffULL);
1930                 wr32(E1000_TDBAH(j), tdba >> 32);
1931
1932                 ring->head = E1000_TDH(j);
1933                 ring->tail = E1000_TDT(j);
1934                 writel(0, hw->hw_addr + ring->tail);
1935                 writel(0, hw->hw_addr + ring->head);
1936                 txdctl = rd32(E1000_TXDCTL(j));
1937                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1938                 wr32(E1000_TXDCTL(j), txdctl);
1939
1940                 /* Turn off Relaxed Ordering on head write-backs.  The
1941                  * writebacks MUST be delivered in order or it will
1942                  * completely screw up our bookeeping.
1943                  */
1944                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1945                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1946                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1947         }
1948
1949         /* disable queue 0 to prevent tail bump w/o re-configuration */
1950         if (adapter->vfs_allocated_count)
1951                 wr32(E1000_TXDCTL(0), 0);
1952
1953         /* Program the Transmit Control Register */
1954         tctl = rd32(E1000_TCTL);
1955         tctl &= ~E1000_TCTL_CT;
1956         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1957                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1958
1959         igb_config_collision_dist(hw);
1960
1961         /* Setup Transmit Descriptor Settings for eop descriptor */
1962         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1963
1964         /* Enable transmits */
1965         tctl |= E1000_TCTL_EN;
1966
1967         wr32(E1000_TCTL, tctl);
1968 }
1969
1970 /**
1971  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1972  * @adapter: board private structure
1973  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1974  *
1975  * Returns 0 on success, negative on failure
1976  **/
1977 int igb_setup_rx_resources(struct igb_adapter *adapter,
1978                            struct igb_ring *rx_ring)
1979 {
1980         struct pci_dev *pdev = adapter->pdev;
1981         int size, desc_len;
1982
1983         size = sizeof(struct igb_buffer) * rx_ring->count;
1984         rx_ring->buffer_info = vmalloc(size);
1985         if (!rx_ring->buffer_info)
1986                 goto err;
1987         memset(rx_ring->buffer_info, 0, size);
1988
1989         desc_len = sizeof(union e1000_adv_rx_desc);
1990
1991         /* Round up to nearest 4K */
1992         rx_ring->size = rx_ring->count * desc_len;
1993         rx_ring->size = ALIGN(rx_ring->size, 4096);
1994
1995         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1996                                              &rx_ring->dma);
1997
1998         if (!rx_ring->desc)
1999                 goto err;
2000
2001         rx_ring->next_to_clean = 0;
2002         rx_ring->next_to_use = 0;
2003
2004         rx_ring->adapter = adapter;
2005
2006         return 0;
2007
2008 err:
2009         vfree(rx_ring->buffer_info);
2010         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2011                 "the receive descriptor ring\n");
2012         return -ENOMEM;
2013 }
2014
2015 /**
2016  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2017  *                                (Descriptors) for all queues
2018  * @adapter: board private structure
2019  *
2020  * Return 0 on success, negative on failure
2021  **/
2022 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2023 {
2024         int i, err = 0;
2025
2026         for (i = 0; i < adapter->num_rx_queues; i++) {
2027                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2028                 if (err) {
2029                         dev_err(&adapter->pdev->dev,
2030                                 "Allocation for Rx Queue %u failed\n", i);
2031                         for (i--; i >= 0; i--)
2032                                 igb_free_rx_resources(&adapter->rx_ring[i]);
2033                         break;
2034                 }
2035         }
2036
2037         return err;
2038 }
2039
2040 /**
2041  * igb_setup_rctl - configure the receive control registers
2042  * @adapter: Board private structure
2043  **/
2044 static void igb_setup_rctl(struct igb_adapter *adapter)
2045 {
2046         struct e1000_hw *hw = &adapter->hw;
2047         u32 rctl;
2048         u32 srrctl = 0;
2049         int i;
2050
2051         rctl = rd32(E1000_RCTL);
2052
2053         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2054         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2055
2056         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2057                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2058
2059         /*
2060          * enable stripping of CRC. It's unlikely this will break BMC
2061          * redirection as it did with e1000. Newer features require
2062          * that the HW strips the CRC.
2063          */
2064         rctl |= E1000_RCTL_SECRC;
2065
2066         /*
2067          * disable store bad packets and clear size bits.
2068          */
2069         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2070
2071         /* enable LPE when to prevent packets larger than max_frame_size */
2072                 rctl |= E1000_RCTL_LPE;
2073
2074         /* Setup buffer sizes */
2075         switch (adapter->rx_buffer_len) {
2076         case IGB_RXBUFFER_256:
2077                 rctl |= E1000_RCTL_SZ_256;
2078                 break;
2079         case IGB_RXBUFFER_512:
2080                 rctl |= E1000_RCTL_SZ_512;
2081                 break;
2082         default:
2083                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2084                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2085                 break;
2086         }
2087
2088         /* 82575 and greater support packet-split where the protocol
2089          * header is placed in skb->data and the packet data is
2090          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2091          * In the case of a non-split, skb->data is linearly filled,
2092          * followed by the page buffers.  Therefore, skb->data is
2093          * sized to hold the largest protocol header.
2094          */
2095         /* allocations using alloc_page take too long for regular MTU
2096          * so only enable packet split for jumbo frames */
2097         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2098                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2099                 srrctl |= adapter->rx_ps_hdr_size <<
2100                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2101                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2102         } else {
2103                 adapter->rx_ps_hdr_size = 0;
2104                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2105         }
2106
2107         /* Attention!!!  For SR-IOV PF driver operations you must enable
2108          * queue drop for all VF and PF queues to prevent head of line blocking
2109          * if an un-trusted VF does not provide descriptors to hardware.
2110          */
2111         if (adapter->vfs_allocated_count) {
2112                 u32 vmolr;
2113
2114                 /* set all queue drop enable bits */
2115                 wr32(E1000_QDE, ALL_QUEUES);
2116                 srrctl |= E1000_SRRCTL_DROP_EN;
2117
2118                 /* disable queue 0 to prevent tail write w/o re-config */
2119                 wr32(E1000_RXDCTL(0), 0);
2120
2121                 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2122                 if (rctl & E1000_RCTL_LPE)
2123                         vmolr |= E1000_VMOLR_LPE;
2124                 if (adapter->num_rx_queues > 1)
2125                         vmolr |= E1000_VMOLR_RSSE;
2126                 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2127         }
2128
2129         for (i = 0; i < adapter->num_rx_queues; i++) {
2130                 int j = adapter->rx_ring[i].reg_idx;
2131                 wr32(E1000_SRRCTL(j), srrctl);
2132         }
2133
2134         wr32(E1000_RCTL, rctl);
2135 }
2136
2137 /**
2138  * igb_rlpml_set - set maximum receive packet size
2139  * @adapter: board private structure
2140  *
2141  * Configure maximum receivable packet size.
2142  **/
2143 static void igb_rlpml_set(struct igb_adapter *adapter)
2144 {
2145         u32 max_frame_size = adapter->max_frame_size;
2146         struct e1000_hw *hw = &adapter->hw;
2147         u16 pf_id = adapter->vfs_allocated_count;
2148
2149         if (adapter->vlgrp)
2150                 max_frame_size += VLAN_TAG_SIZE;
2151
2152         /* if vfs are enabled we set RLPML to the largest possible request
2153          * size and set the VMOLR RLPML to the size we need */
2154         if (pf_id) {
2155                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2156                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2157         }
2158
2159         wr32(E1000_RLPML, max_frame_size);
2160 }
2161
2162 /**
2163  * igb_configure_vt_default_pool - Configure VT default pool
2164  * @adapter: board private structure
2165  *
2166  * Configure the default pool
2167  **/
2168 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2169 {
2170         struct e1000_hw *hw = &adapter->hw;
2171         u16 pf_id = adapter->vfs_allocated_count;
2172         u32 vtctl;
2173
2174         /* not in sr-iov mode - do nothing */
2175         if (!pf_id)
2176                 return;
2177
2178         vtctl = rd32(E1000_VT_CTL);
2179         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2180                    E1000_VT_CTL_DISABLE_DEF_POOL);
2181         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2182         wr32(E1000_VT_CTL, vtctl);
2183 }
2184
2185 /**
2186  * igb_configure_rx - Configure receive Unit after Reset
2187  * @adapter: board private structure
2188  *
2189  * Configure the Rx unit of the MAC after a reset.
2190  **/
2191 static void igb_configure_rx(struct igb_adapter *adapter)
2192 {
2193         u64 rdba;
2194         struct e1000_hw *hw = &adapter->hw;
2195         u32 rctl, rxcsum;
2196         u32 rxdctl;
2197         int i;
2198
2199         /* disable receives while setting up the descriptors */
2200         rctl = rd32(E1000_RCTL);
2201         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2202         wrfl();
2203         mdelay(10);
2204
2205         if (adapter->itr_setting > 3)
2206                 wr32(E1000_ITR, adapter->itr);
2207
2208         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2209          * the Base and Length of the Rx Descriptor Ring */
2210         for (i = 0; i < adapter->num_rx_queues; i++) {
2211                 struct igb_ring *ring = &adapter->rx_ring[i];
2212                 int j = ring->reg_idx;
2213                 rdba = ring->dma;
2214                 wr32(E1000_RDBAL(j),
2215                      rdba & 0x00000000ffffffffULL);
2216                 wr32(E1000_RDBAH(j), rdba >> 32);
2217                 wr32(E1000_RDLEN(j),
2218                      ring->count * sizeof(union e1000_adv_rx_desc));
2219
2220                 ring->head = E1000_RDH(j);
2221                 ring->tail = E1000_RDT(j);
2222                 writel(0, hw->hw_addr + ring->tail);
2223                 writel(0, hw->hw_addr + ring->head);
2224
2225                 rxdctl = rd32(E1000_RXDCTL(j));
2226                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2227                 rxdctl &= 0xFFF00000;
2228                 rxdctl |= IGB_RX_PTHRESH;
2229                 rxdctl |= IGB_RX_HTHRESH << 8;
2230                 rxdctl |= IGB_RX_WTHRESH << 16;
2231                 wr32(E1000_RXDCTL(j), rxdctl);
2232         }
2233
2234         if (adapter->num_rx_queues > 1) {
2235                 u32 random[10];
2236                 u32 mrqc;
2237                 u32 j, shift;
2238                 union e1000_reta {
2239                         u32 dword;
2240                         u8  bytes[4];
2241                 } reta;
2242
2243                 get_random_bytes(&random[0], 40);
2244
2245                 if (hw->mac.type >= e1000_82576)
2246                         shift = 0;
2247                 else
2248                         shift = 6;
2249                 for (j = 0; j < (32 * 4); j++) {
2250                         reta.bytes[j & 3] =
2251                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2252                         if ((j & 3) == 3)
2253                                 writel(reta.dword,
2254                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2255                 }
2256                 if (adapter->vfs_allocated_count)
2257                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2258                 else
2259                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2260
2261                 /* Fill out hash function seeds */
2262                 for (j = 0; j < 10; j++)
2263                         array_wr32(E1000_RSSRK(0), j, random[j]);
2264
2265                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2266                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2267                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2268                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2269                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2270                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2271                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2272                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2273
2274                 wr32(E1000_MRQC, mrqc);
2275         } else if (adapter->vfs_allocated_count) {
2276                 /* Enable multi-queue for sr-iov */
2277                 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2278         }
2279
2280         /* Enable Receive Checksum Offload for TCP and UDP */
2281         rxcsum = rd32(E1000_RXCSUM);
2282         /* Disable raw packet checksumming */
2283         rxcsum |= E1000_RXCSUM_PCSD;
2284
2285         if (adapter->hw.mac.type == e1000_82576)
2286                 /* Enable Receive Checksum Offload for SCTP */
2287                 rxcsum |= E1000_RXCSUM_CRCOFL;
2288
2289         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2290         wr32(E1000_RXCSUM, rxcsum);
2291
2292         /* Set the default pool for the PF's first queue */
2293         igb_configure_vt_default_pool(adapter);
2294
2295         igb_rlpml_set(adapter);
2296
2297         /* Enable Receives */
2298         wr32(E1000_RCTL, rctl);
2299 }
2300
2301 /**
2302  * igb_free_tx_resources - Free Tx Resources per Queue
2303  * @tx_ring: Tx descriptor ring for a specific queue
2304  *
2305  * Free all transmit software resources
2306  **/
2307 void igb_free_tx_resources(struct igb_ring *tx_ring)
2308 {
2309         struct pci_dev *pdev = tx_ring->adapter->pdev;
2310
2311         igb_clean_tx_ring(tx_ring);
2312
2313         vfree(tx_ring->buffer_info);
2314         tx_ring->buffer_info = NULL;
2315
2316         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2317
2318         tx_ring->desc = NULL;
2319 }
2320
2321 /**
2322  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2323  * @adapter: board private structure
2324  *
2325  * Free all transmit software resources
2326  **/
2327 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2328 {
2329         int i;
2330
2331         for (i = 0; i < adapter->num_tx_queues; i++)
2332                 igb_free_tx_resources(&adapter->tx_ring[i]);
2333 }
2334
2335 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2336                                            struct igb_buffer *buffer_info)
2337 {
2338         buffer_info->dma = 0;
2339         if (buffer_info->skb) {
2340                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2341                               DMA_TO_DEVICE);
2342                 dev_kfree_skb_any(buffer_info->skb);
2343                 buffer_info->skb = NULL;
2344         }
2345         buffer_info->time_stamp = 0;
2346         /* buffer_info must be completely set up in the transmit path */
2347 }
2348
2349 /**
2350  * igb_clean_tx_ring - Free Tx Buffers
2351  * @tx_ring: ring to be cleaned
2352  **/
2353 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2354 {
2355         struct igb_adapter *adapter = tx_ring->adapter;
2356         struct igb_buffer *buffer_info;
2357         unsigned long size;
2358         unsigned int i;
2359
2360         if (!tx_ring->buffer_info)
2361                 return;
2362         /* Free all the Tx ring sk_buffs */
2363
2364         for (i = 0; i < tx_ring->count; i++) {
2365                 buffer_info = &tx_ring->buffer_info[i];
2366                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2367         }
2368
2369         size = sizeof(struct igb_buffer) * tx_ring->count;
2370         memset(tx_ring->buffer_info, 0, size);
2371
2372         /* Zero out the descriptor ring */
2373
2374         memset(tx_ring->desc, 0, tx_ring->size);
2375
2376         tx_ring->next_to_use = 0;
2377         tx_ring->next_to_clean = 0;
2378
2379         writel(0, adapter->hw.hw_addr + tx_ring->head);
2380         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2381 }
2382
2383 /**
2384  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2385  * @adapter: board private structure
2386  **/
2387 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2388 {
2389         int i;
2390
2391         for (i = 0; i < adapter->num_tx_queues; i++)
2392                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2393 }
2394
2395 /**
2396  * igb_free_rx_resources - Free Rx Resources
2397  * @rx_ring: ring to clean the resources from
2398  *
2399  * Free all receive software resources
2400  **/
2401 void igb_free_rx_resources(struct igb_ring *rx_ring)
2402 {
2403         struct pci_dev *pdev = rx_ring->adapter->pdev;
2404
2405         igb_clean_rx_ring(rx_ring);
2406
2407         vfree(rx_ring->buffer_info);
2408         rx_ring->buffer_info = NULL;
2409
2410         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2411
2412         rx_ring->desc = NULL;
2413 }
2414
2415 /**
2416  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2417  * @adapter: board private structure
2418  *
2419  * Free all receive software resources
2420  **/
2421 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2422 {
2423         int i;
2424
2425         for (i = 0; i < adapter->num_rx_queues; i++)
2426                 igb_free_rx_resources(&adapter->rx_ring[i]);
2427 }
2428
2429 /**
2430  * igb_clean_rx_ring - Free Rx Buffers per Queue
2431  * @rx_ring: ring to free buffers from
2432  **/
2433 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2434 {
2435         struct igb_adapter *adapter = rx_ring->adapter;
2436         struct igb_buffer *buffer_info;
2437         struct pci_dev *pdev = adapter->pdev;
2438         unsigned long size;
2439         unsigned int i;
2440
2441         if (!rx_ring->buffer_info)
2442                 return;
2443         /* Free all the Rx ring sk_buffs */
2444         for (i = 0; i < rx_ring->count; i++) {
2445                 buffer_info = &rx_ring->buffer_info[i];
2446                 if (buffer_info->dma) {
2447                         if (adapter->rx_ps_hdr_size)
2448                                 pci_unmap_single(pdev, buffer_info->dma,
2449                                                  adapter->rx_ps_hdr_size,
2450                                                  PCI_DMA_FROMDEVICE);
2451                         else
2452                                 pci_unmap_single(pdev, buffer_info->dma,
2453                                                  adapter->rx_buffer_len,
2454                                                  PCI_DMA_FROMDEVICE);
2455                         buffer_info->dma = 0;
2456                 }
2457
2458                 if (buffer_info->skb) {
2459                         dev_kfree_skb(buffer_info->skb);
2460                         buffer_info->skb = NULL;
2461                 }
2462                 if (buffer_info->page) {
2463                         if (buffer_info->page_dma)
2464                                 pci_unmap_page(pdev, buffer_info->page_dma,
2465                                                PAGE_SIZE / 2,
2466                                                PCI_DMA_FROMDEVICE);
2467                         put_page(buffer_info->page);
2468                         buffer_info->page = NULL;
2469                         buffer_info->page_dma = 0;
2470                         buffer_info->page_offset = 0;
2471                 }
2472         }
2473
2474         size = sizeof(struct igb_buffer) * rx_ring->count;
2475         memset(rx_ring->buffer_info, 0, size);
2476
2477         /* Zero out the descriptor ring */
2478         memset(rx_ring->desc, 0, rx_ring->size);
2479
2480         rx_ring->next_to_clean = 0;
2481         rx_ring->next_to_use = 0;
2482
2483         writel(0, adapter->hw.hw_addr + rx_ring->head);
2484         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2485 }
2486
2487 /**
2488  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2489  * @adapter: board private structure
2490  **/
2491 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2492 {
2493         int i;
2494
2495         for (i = 0; i < adapter->num_rx_queues; i++)
2496                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2497 }
2498
2499 /**
2500  * igb_set_mac - Change the Ethernet Address of the NIC
2501  * @netdev: network interface device structure
2502  * @p: pointer to an address structure
2503  *
2504  * Returns 0 on success, negative on failure
2505  **/
2506 static int igb_set_mac(struct net_device *netdev, void *p)
2507 {
2508         struct igb_adapter *adapter = netdev_priv(netdev);
2509         struct e1000_hw *hw = &adapter->hw;
2510         struct sockaddr *addr = p;
2511
2512         if (!is_valid_ether_addr(addr->sa_data))
2513                 return -EADDRNOTAVAIL;
2514
2515         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2516         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2517
2518         hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
2519
2520         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2521
2522         return 0;
2523 }
2524
2525 /**
2526  * igb_set_multi - Multicast and Promiscuous mode set
2527  * @netdev: network interface device structure
2528  *
2529  * The set_multi entry point is called whenever the multicast address
2530  * list or the network interface flags are updated.  This routine is
2531  * responsible for configuring the hardware for proper multicast,
2532  * promiscuous mode, and all-multi behavior.
2533  **/
2534 static void igb_set_multi(struct net_device *netdev)
2535 {
2536         struct igb_adapter *adapter = netdev_priv(netdev);
2537         struct e1000_hw *hw = &adapter->hw;
2538         struct e1000_mac_info *mac = &hw->mac;
2539         struct dev_mc_list *mc_ptr;
2540         u8  *mta_list = NULL;
2541         u32 rctl;
2542         int i;
2543
2544         /* Check for Promiscuous and All Multicast modes */
2545
2546         rctl = rd32(E1000_RCTL);
2547
2548         if (netdev->flags & IFF_PROMISC) {
2549                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2550                 rctl &= ~E1000_RCTL_VFE;
2551         } else {
2552                 if (netdev->flags & IFF_ALLMULTI) {
2553                         rctl |= E1000_RCTL_MPE;
2554                         rctl &= ~E1000_RCTL_UPE;
2555                 } else
2556                         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2557                 rctl |= E1000_RCTL_VFE;
2558         }
2559         wr32(E1000_RCTL, rctl);
2560
2561         if (netdev->mc_count) {
2562                 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2563                 if (!mta_list) {
2564                         dev_err(&adapter->pdev->dev,
2565                                 "failed to allocate multicast filter list\n");
2566                         return;
2567                 }
2568         }
2569
2570         /* The shared function expects a packed array of only addresses. */
2571         mc_ptr = netdev->mc_list;
2572
2573         for (i = 0; i < netdev->mc_count; i++) {
2574                 if (!mc_ptr)
2575                         break;
2576                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2577                 mc_ptr = mc_ptr->next;
2578         }
2579         igb_update_mc_addr_list(hw, mta_list, i,
2580                                 adapter->vfs_allocated_count + 1,
2581                                 mac->rar_entry_count);
2582
2583         igb_set_mc_list_pools(adapter, i, mac->rar_entry_count);
2584         igb_restore_vf_multicasts(adapter);
2585
2586         kfree(mta_list);
2587 }
2588
2589 /* Need to wait a few seconds after link up to get diagnostic information from
2590  * the phy */
2591 static void igb_update_phy_info(unsigned long data)
2592 {
2593         struct igb_adapter *adapter = (struct igb_adapter *) data;
2594         igb_get_phy_info(&adapter->hw);
2595 }
2596
2597 /**
2598  * igb_has_link - check shared code for link and determine up/down
2599  * @adapter: pointer to driver private info
2600  **/
2601 static bool igb_has_link(struct igb_adapter *adapter)
2602 {
2603         struct e1000_hw *hw = &adapter->hw;
2604         bool link_active = false;
2605         s32 ret_val = 0;
2606
2607         /* get_link_status is set on LSC (link status) interrupt or
2608          * rx sequence error interrupt.  get_link_status will stay
2609          * false until the e1000_check_for_link establishes link
2610          * for copper adapters ONLY
2611          */
2612         switch (hw->phy.media_type) {
2613         case e1000_media_type_copper:
2614                 if (hw->mac.get_link_status) {
2615                         ret_val = hw->mac.ops.check_for_link(hw);
2616                         link_active = !hw->mac.get_link_status;
2617                 } else {
2618                         link_active = true;
2619                 }
2620                 break;
2621         case e1000_media_type_fiber:
2622                 ret_val = hw->mac.ops.check_for_link(hw);
2623                 link_active = !!(rd32(E1000_STATUS) & E1000_STATUS_LU);
2624                 break;
2625         case e1000_media_type_internal_serdes:
2626                 ret_val = hw->mac.ops.check_for_link(hw);
2627                 link_active = hw->mac.serdes_has_link;
2628                 break;
2629         default:
2630         case e1000_media_type_unknown:
2631                 break;
2632         }
2633
2634         return link_active;
2635 }
2636
2637 /**
2638  * igb_watchdog - Timer Call-back
2639  * @data: pointer to adapter cast into an unsigned long
2640  **/
2641 static void igb_watchdog(unsigned long data)
2642 {
2643         struct igb_adapter *adapter = (struct igb_adapter *)data;
2644         /* Do the rest outside of interrupt context */
2645         schedule_work(&adapter->watchdog_task);
2646 }
2647
2648 static void igb_watchdog_task(struct work_struct *work)
2649 {
2650         struct igb_adapter *adapter = container_of(work,
2651                                         struct igb_adapter, watchdog_task);
2652         struct e1000_hw *hw = &adapter->hw;
2653         struct net_device *netdev = adapter->netdev;
2654         struct igb_ring *tx_ring = adapter->tx_ring;
2655         u32 link;
2656         u32 eics = 0;
2657         int i;
2658
2659         link = igb_has_link(adapter);
2660         if ((netif_carrier_ok(netdev)) && link)
2661                 goto link_up;
2662
2663         if (link) {
2664                 if (!netif_carrier_ok(netdev)) {
2665                         u32 ctrl;
2666                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2667                                                    &adapter->link_speed,
2668                                                    &adapter->link_duplex);
2669
2670                         ctrl = rd32(E1000_CTRL);
2671                         /* Links status message must follow this format */
2672                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2673                                  "Flow Control: %s\n",
2674                                  netdev->name,
2675                                  adapter->link_speed,
2676                                  adapter->link_duplex == FULL_DUPLEX ?
2677                                  "Full Duplex" : "Half Duplex",
2678                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2679                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2680                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2681                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2682
2683                         /* tweak tx_queue_len according to speed/duplex and
2684                          * adjust the timeout factor */
2685                         netdev->tx_queue_len = adapter->tx_queue_len;
2686                         adapter->tx_timeout_factor = 1;
2687                         switch (adapter->link_speed) {
2688                         case SPEED_10:
2689                                 netdev->tx_queue_len = 10;
2690                                 adapter->tx_timeout_factor = 14;
2691                                 break;
2692                         case SPEED_100:
2693                                 netdev->tx_queue_len = 100;
2694                                 /* maybe add some timeout factor ? */
2695                                 break;
2696                         }
2697
2698                         netif_carrier_on(netdev);
2699
2700                         igb_ping_all_vfs(adapter);
2701
2702                         /* link state has changed, schedule phy info update */
2703                         if (!test_bit(__IGB_DOWN, &adapter->state))
2704                                 mod_timer(&adapter->phy_info_timer,
2705                                           round_jiffies(jiffies + 2 * HZ));
2706                 }
2707         } else {
2708                 if (netif_carrier_ok(netdev)) {
2709                         adapter->link_speed = 0;
2710                         adapter->link_duplex = 0;
2711                         /* Links status message must follow this format */
2712                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2713                                netdev->name);
2714                         netif_carrier_off(netdev);
2715
2716                         igb_ping_all_vfs(adapter);
2717
2718                         /* link state has changed, schedule phy info update */
2719                         if (!test_bit(__IGB_DOWN, &adapter->state))
2720                                 mod_timer(&adapter->phy_info_timer,
2721                                           round_jiffies(jiffies + 2 * HZ));
2722                 }
2723         }
2724
2725 link_up:
2726         igb_update_stats(adapter);
2727
2728         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2729         adapter->tpt_old = adapter->stats.tpt;
2730         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2731         adapter->colc_old = adapter->stats.colc;
2732
2733         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2734         adapter->gorc_old = adapter->stats.gorc;
2735         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2736         adapter->gotc_old = adapter->stats.gotc;
2737
2738         igb_update_adaptive(&adapter->hw);
2739
2740         if (!netif_carrier_ok(netdev)) {
2741                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2742                         /* We've lost link, so the controller stops DMA,
2743                          * but we've got queued Tx work that's never going
2744                          * to get done, so reset controller to flush Tx.
2745                          * (Do the reset outside of interrupt context). */
2746                         adapter->tx_timeout_count++;
2747                         schedule_work(&adapter->reset_task);
2748                         /* return immediately since reset is imminent */
2749                         return;
2750                 }
2751         }
2752
2753         /* Cause software interrupt to ensure rx ring is cleaned */
2754         if (adapter->msix_entries) {
2755                 for (i = 0; i < adapter->num_rx_queues; i++)
2756                         eics |= adapter->rx_ring[i].eims_value;
2757                 wr32(E1000_EICS, eics);
2758         } else {
2759                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2760         }
2761
2762         /* Force detection of hung controller every watchdog period */
2763         tx_ring->detect_tx_hung = true;
2764
2765         /* Reset the timer */
2766         if (!test_bit(__IGB_DOWN, &adapter->state))
2767                 mod_timer(&adapter->watchdog_timer,
2768                           round_jiffies(jiffies + 2 * HZ));
2769 }
2770
2771 enum latency_range {
2772         lowest_latency = 0,
2773         low_latency = 1,
2774         bulk_latency = 2,
2775         latency_invalid = 255
2776 };
2777
2778
2779 /**
2780  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2781  *
2782  *      Stores a new ITR value based on strictly on packet size.  This
2783  *      algorithm is less sophisticated than that used in igb_update_itr,
2784  *      due to the difficulty of synchronizing statistics across multiple
2785  *      receive rings.  The divisors and thresholds used by this fuction
2786  *      were determined based on theoretical maximum wire speed and testing
2787  *      data, in order to minimize response time while increasing bulk
2788  *      throughput.
2789  *      This functionality is controlled by the InterruptThrottleRate module
2790  *      parameter (see igb_param.c)
2791  *      NOTE:  This function is called only when operating in a multiqueue
2792  *             receive environment.
2793  * @rx_ring: pointer to ring
2794  **/
2795 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2796 {
2797         int new_val = rx_ring->itr_val;
2798         int avg_wire_size = 0;
2799         struct igb_adapter *adapter = rx_ring->adapter;
2800
2801         if (!rx_ring->total_packets)
2802                 goto clear_counts; /* no packets, so don't do anything */
2803
2804         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2805          * ints/sec - ITR timer value of 120 ticks.
2806          */
2807         if (adapter->link_speed != SPEED_1000) {
2808                 new_val = 120;
2809                 goto set_itr_val;
2810         }
2811         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2812
2813         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2814         avg_wire_size += 24;
2815
2816         /* Don't starve jumbo frames */
2817         avg_wire_size = min(avg_wire_size, 3000);
2818
2819         /* Give a little boost to mid-size frames */
2820         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2821                 new_val = avg_wire_size / 3;
2822         else
2823                 new_val = avg_wire_size / 2;
2824
2825 set_itr_val:
2826         if (new_val != rx_ring->itr_val) {
2827                 rx_ring->itr_val = new_val;
2828                 rx_ring->set_itr = 1;
2829         }
2830 clear_counts:
2831         rx_ring->total_bytes = 0;
2832         rx_ring->total_packets = 0;
2833 }
2834
2835 /**
2836  * igb_update_itr - update the dynamic ITR value based on statistics
2837  *      Stores a new ITR value based on packets and byte
2838  *      counts during the last interrupt.  The advantage of per interrupt
2839  *      computation is faster updates and more accurate ITR for the current
2840  *      traffic pattern.  Constants in this function were computed
2841  *      based on theoretical maximum wire speed and thresholds were set based
2842  *      on testing data as well as attempting to minimize response time
2843  *      while increasing bulk throughput.
2844  *      this functionality is controlled by the InterruptThrottleRate module
2845  *      parameter (see igb_param.c)
2846  *      NOTE:  These calculations are only valid when operating in a single-
2847  *             queue environment.
2848  * @adapter: pointer to adapter
2849  * @itr_setting: current adapter->itr
2850  * @packets: the number of packets during this measurement interval
2851  * @bytes: the number of bytes during this measurement interval
2852  **/
2853 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2854                                    int packets, int bytes)
2855 {
2856         unsigned int retval = itr_setting;
2857
2858         if (packets == 0)
2859                 goto update_itr_done;
2860
2861         switch (itr_setting) {
2862         case lowest_latency:
2863                 /* handle TSO and jumbo frames */
2864                 if (bytes/packets > 8000)
2865                         retval = bulk_latency;
2866                 else if ((packets < 5) && (bytes > 512))
2867                         retval = low_latency;
2868                 break;
2869         case low_latency:  /* 50 usec aka 20000 ints/s */
2870                 if (bytes > 10000) {
2871                         /* this if handles the TSO accounting */
2872                         if (bytes/packets > 8000) {
2873                                 retval = bulk_latency;
2874                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2875                                 retval = bulk_latency;
2876                         } else if ((packets > 35)) {
2877                                 retval = lowest_latency;
2878                         }
2879                 } else if (bytes/packets > 2000) {
2880                         retval = bulk_latency;
2881                 } else if (packets <= 2 && bytes < 512) {
2882                         retval = lowest_latency;
2883                 }
2884                 break;
2885         case bulk_latency: /* 250 usec aka 4000 ints/s */
2886                 if (bytes > 25000) {
2887                         if (packets > 35)
2888                                 retval = low_latency;
2889                 } else if (bytes < 1500) {
2890                         retval = low_latency;
2891                 }
2892                 break;
2893         }
2894
2895 update_itr_done:
2896         return retval;
2897 }
2898
2899 static void igb_set_itr(struct igb_adapter *adapter)
2900 {
2901         u16 current_itr;
2902         u32 new_itr = adapter->itr;
2903
2904         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2905         if (adapter->link_speed != SPEED_1000) {
2906                 current_itr = 0;
2907                 new_itr = 4000;
2908                 goto set_itr_now;
2909         }
2910
2911         adapter->rx_itr = igb_update_itr(adapter,
2912                                     adapter->rx_itr,
2913                                     adapter->rx_ring->total_packets,
2914                                     adapter->rx_ring->total_bytes);
2915
2916         if (adapter->rx_ring->buddy) {
2917                 adapter->tx_itr = igb_update_itr(adapter,
2918                                             adapter->tx_itr,
2919                                             adapter->tx_ring->total_packets,
2920                                             adapter->tx_ring->total_bytes);
2921                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2922         } else {
2923                 current_itr = adapter->rx_itr;
2924         }
2925
2926         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2927         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2928                 current_itr = low_latency;
2929
2930         switch (current_itr) {
2931         /* counts and packets in update_itr are dependent on these numbers */
2932         case lowest_latency:
2933                 new_itr = 56;  /* aka 70,000 ints/sec */
2934                 break;
2935         case low_latency:
2936                 new_itr = 196; /* aka 20,000 ints/sec */
2937                 break;
2938         case bulk_latency:
2939                 new_itr = 980; /* aka 4,000 ints/sec */
2940                 break;
2941         default:
2942                 break;
2943         }
2944
2945 set_itr_now:
2946         adapter->rx_ring->total_bytes = 0;
2947         adapter->rx_ring->total_packets = 0;
2948         if (adapter->rx_ring->buddy) {
2949                 adapter->rx_ring->buddy->total_bytes = 0;
2950                 adapter->rx_ring->buddy->total_packets = 0;
2951         }
2952
2953         if (new_itr != adapter->itr) {
2954                 /* this attempts to bias the interrupt rate towards Bulk
2955                  * by adding intermediate steps when interrupt rate is
2956                  * increasing */
2957                 new_itr = new_itr > adapter->itr ?
2958                              max((new_itr * adapter->itr) /
2959                                  (new_itr + (adapter->itr >> 2)), new_itr) :
2960                              new_itr;
2961                 /* Don't write the value here; it resets the adapter's
2962                  * internal timer, and causes us to delay far longer than
2963                  * we should between interrupts.  Instead, we write the ITR
2964                  * value at the beginning of the next interrupt so the timing
2965                  * ends up being correct.
2966                  */
2967                 adapter->itr = new_itr;
2968                 adapter->rx_ring->itr_val = new_itr;
2969                 adapter->rx_ring->set_itr = 1;
2970         }
2971
2972         return;
2973 }
2974
2975
2976 #define IGB_TX_FLAGS_CSUM               0x00000001
2977 #define IGB_TX_FLAGS_VLAN               0x00000002
2978 #define IGB_TX_FLAGS_TSO                0x00000004
2979 #define IGB_TX_FLAGS_IPV4               0x00000008
2980 #define IGB_TX_FLAGS_TSTAMP             0x00000010
2981 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
2982 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2983
2984 static inline int igb_tso_adv(struct igb_adapter *adapter,
2985                               struct igb_ring *tx_ring,
2986                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2987 {
2988         struct e1000_adv_tx_context_desc *context_desc;
2989         unsigned int i;
2990         int err;
2991         struct igb_buffer *buffer_info;
2992         u32 info = 0, tu_cmd = 0;
2993         u32 mss_l4len_idx, l4len;
2994         *hdr_len = 0;
2995
2996         if (skb_header_cloned(skb)) {
2997                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2998                 if (err)
2999                         return err;
3000         }
3001
3002         l4len = tcp_hdrlen(skb);
3003         *hdr_len += l4len;
3004
3005         if (skb->protocol == htons(ETH_P_IP)) {
3006                 struct iphdr *iph = ip_hdr(skb);
3007                 iph->tot_len = 0;
3008                 iph->check = 0;
3009                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3010                                                          iph->daddr, 0,
3011                                                          IPPROTO_TCP,
3012                                                          0);
3013         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3014                 ipv6_hdr(skb)->payload_len = 0;
3015                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3016                                                        &ipv6_hdr(skb)->daddr,
3017                                                        0, IPPROTO_TCP, 0);
3018         }
3019
3020         i = tx_ring->next_to_use;
3021
3022         buffer_info = &tx_ring->buffer_info[i];
3023         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3024         /* VLAN MACLEN IPLEN */
3025         if (tx_flags & IGB_TX_FLAGS_VLAN)
3026                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3027         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3028         *hdr_len += skb_network_offset(skb);
3029         info |= skb_network_header_len(skb);
3030         *hdr_len += skb_network_header_len(skb);
3031         context_desc->vlan_macip_lens = cpu_to_le32(info);
3032
3033         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3034         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3035
3036         if (skb->protocol == htons(ETH_P_IP))
3037                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3038         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3039
3040         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3041
3042         /* MSS L4LEN IDX */
3043         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3044         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3045
3046         /* For 82575, context index must be unique per ring. */
3047         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3048                 mss_l4len_idx |= tx_ring->queue_index << 4;
3049
3050         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3051         context_desc->seqnum_seed = 0;
3052
3053         buffer_info->time_stamp = jiffies;
3054         buffer_info->next_to_watch = i;
3055         buffer_info->dma = 0;
3056         i++;
3057         if (i == tx_ring->count)
3058                 i = 0;
3059
3060         tx_ring->next_to_use = i;
3061
3062         return true;
3063 }
3064
3065 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3066                                         struct igb_ring *tx_ring,
3067                                         struct sk_buff *skb, u32 tx_flags)
3068 {
3069         struct e1000_adv_tx_context_desc *context_desc;
3070         unsigned int i;
3071         struct igb_buffer *buffer_info;
3072         u32 info = 0, tu_cmd = 0;
3073
3074         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3075             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3076                 i = tx_ring->next_to_use;
3077                 buffer_info = &tx_ring->buffer_info[i];
3078                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3079
3080                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3081                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3082                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3083                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3084                         info |= skb_network_header_len(skb);
3085
3086                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3087
3088                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3089
3090                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3091                         __be16 protocol;
3092
3093                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3094                                 const struct vlan_ethhdr *vhdr =
3095                                           (const struct vlan_ethhdr*)skb->data;
3096
3097                                 protocol = vhdr->h_vlan_encapsulated_proto;
3098                         } else {
3099                                 protocol = skb->protocol;
3100                         }
3101
3102                         switch (protocol) {
3103                         case cpu_to_be16(ETH_P_IP):
3104                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3105                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3106                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3107                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3108                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3109                                 break;
3110                         case cpu_to_be16(ETH_P_IPV6):
3111                                 /* XXX what about other V6 headers?? */
3112                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3113                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3114                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3115                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3116                                 break;
3117                         default:
3118                                 if (unlikely(net_ratelimit()))
3119                                         dev_warn(&adapter->pdev->dev,
3120                                             "partial checksum but proto=%x!\n",
3121                                             skb->protocol);
3122                                 break;
3123                         }
3124                 }
3125
3126                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3127                 context_desc->seqnum_seed = 0;
3128                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3129                         context_desc->mss_l4len_idx =
3130                                 cpu_to_le32(tx_ring->queue_index << 4);
3131                 else
3132                         context_desc->mss_l4len_idx = 0;
3133
3134                 buffer_info->time_stamp = jiffies;
3135                 buffer_info->next_to_watch = i;
3136                 buffer_info->dma = 0;
3137
3138                 i++;
3139                 if (i == tx_ring->count)
3140                         i = 0;
3141                 tx_ring->next_to_use = i;
3142
3143                 return true;
3144         }
3145         return false;
3146 }
3147
3148 #define IGB_MAX_TXD_PWR 16
3149 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3150
3151 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3152                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3153                                  unsigned int first)
3154 {
3155         struct igb_buffer *buffer_info;
3156         unsigned int len = skb_headlen(skb);
3157         unsigned int count = 0, i;
3158         unsigned int f;
3159         dma_addr_t *map;
3160
3161         i = tx_ring->next_to_use;
3162
3163         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3164                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3165                 return 0;
3166         }
3167
3168         map = skb_shinfo(skb)->dma_maps;
3169
3170         buffer_info = &tx_ring->buffer_info[i];
3171         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3172         buffer_info->length = len;
3173         /* set time_stamp *before* dma to help avoid a possible race */
3174         buffer_info->time_stamp = jiffies;
3175         buffer_info->next_to_watch = i;
3176         buffer_info->dma = skb_shinfo(skb)->dma_head;
3177
3178         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3179                 struct skb_frag_struct *frag;
3180
3181                 i++;
3182                 if (i == tx_ring->count)
3183                         i = 0;
3184
3185                 frag = &skb_shinfo(skb)->frags[f];
3186                 len = frag->size;
3187
3188                 buffer_info = &tx_ring->buffer_info[i];
3189                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3190                 buffer_info->length = len;
3191                 buffer_info->time_stamp = jiffies;
3192                 buffer_info->next_to_watch = i;
3193                 buffer_info->dma = map[count];
3194                 count++;
3195         }
3196
3197         tx_ring->buffer_info[i].skb = skb;
3198         tx_ring->buffer_info[first].next_to_watch = i;
3199
3200         return count + 1;
3201 }
3202
3203 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3204                                     struct igb_ring *tx_ring,
3205                                     int tx_flags, int count, u32 paylen,
3206                                     u8 hdr_len)
3207 {
3208         union e1000_adv_tx_desc *tx_desc = NULL;
3209         struct igb_buffer *buffer_info;
3210         u32 olinfo_status = 0, cmd_type_len;
3211         unsigned int i;
3212
3213         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3214                         E1000_ADVTXD_DCMD_DEXT);
3215
3216         if (tx_flags & IGB_TX_FLAGS_VLAN)
3217                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3218
3219         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3220                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3221
3222         if (tx_flags & IGB_TX_FLAGS_TSO) {
3223                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3224
3225                 /* insert tcp checksum */
3226                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3227
3228                 /* insert ip checksum */
3229                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3230                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3231
3232         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3233                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3234         }
3235
3236         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3237             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3238                          IGB_TX_FLAGS_VLAN)))
3239                 olinfo_status |= tx_ring->queue_index << 4;
3240
3241         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3242
3243         i = tx_ring->next_to_use;
3244         while (count--) {
3245                 buffer_info = &tx_ring->buffer_info[i];
3246                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3247                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3248                 tx_desc->read.cmd_type_len =
3249                         cpu_to_le32(cmd_type_len | buffer_info->length);
3250                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3251                 i++;
3252                 if (i == tx_ring->count)
3253                         i = 0;
3254         }
3255
3256         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3257         /* Force memory writes to complete before letting h/w
3258          * know there are new descriptors to fetch.  (Only
3259          * applicable for weak-ordered memory model archs,
3260          * such as IA-64). */
3261         wmb();
3262
3263         tx_ring->next_to_use = i;
3264         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3265         /* we need this if more than one processor can write to our tail
3266          * at a time, it syncronizes IO on IA64/Altix systems */
3267         mmiowb();
3268 }
3269
3270 static int __igb_maybe_stop_tx(struct net_device *netdev,
3271                                struct igb_ring *tx_ring, int size)
3272 {
3273         struct igb_adapter *adapter = netdev_priv(netdev);
3274
3275         netif_stop_subqueue(netdev, tx_ring->queue_index);
3276
3277         /* Herbert's original patch had:
3278          *  smp_mb__after_netif_stop_queue();
3279          * but since that doesn't exist yet, just open code it. */
3280         smp_mb();
3281
3282         /* We need to check again in a case another CPU has just
3283          * made room available. */
3284         if (igb_desc_unused(tx_ring) < size)
3285                 return -EBUSY;
3286
3287         /* A reprieve! */
3288         netif_wake_subqueue(netdev, tx_ring->queue_index);
3289         ++adapter->restart_queue;
3290         return 0;
3291 }
3292
3293 static int igb_maybe_stop_tx(struct net_device *netdev,
3294                              struct igb_ring *tx_ring, int size)
3295 {
3296         if (igb_desc_unused(tx_ring) >= size)
3297                 return 0;
3298         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3299 }
3300
3301 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
3302                                    struct net_device *netdev,
3303                                    struct igb_ring *tx_ring)
3304 {
3305         struct igb_adapter *adapter = netdev_priv(netdev);
3306         unsigned int first;
3307         unsigned int tx_flags = 0;
3308         u8 hdr_len = 0;
3309         int count = 0;
3310         int tso = 0;
3311         union skb_shared_tx *shtx;
3312
3313         if (test_bit(__IGB_DOWN, &adapter->state)) {
3314                 dev_kfree_skb_any(skb);
3315                 return NETDEV_TX_OK;
3316         }
3317
3318         if (skb->len <= 0) {
3319                 dev_kfree_skb_any(skb);
3320                 return NETDEV_TX_OK;
3321         }
3322
3323         /* need: 1 descriptor per page,
3324          *       + 2 desc gap to keep tail from touching head,
3325          *       + 1 desc for skb->data,
3326          *       + 1 desc for context descriptor,
3327          * otherwise try next time */
3328         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3329                 /* this is a hard error */
3330                 return NETDEV_TX_BUSY;
3331         }
3332
3333         /*
3334          * TODO: check that there currently is no other packet with
3335          * time stamping in the queue
3336          *
3337          * When doing time stamping, keep the connection to the socket
3338          * a while longer: it is still needed by skb_hwtstamp_tx(),
3339          * called either in igb_tx_hwtstamp() or by our caller when
3340          * doing software time stamping.
3341          */
3342         shtx = skb_tx(skb);
3343         if (unlikely(shtx->hardware)) {
3344                 shtx->in_progress = 1;
3345                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3346         }
3347
3348         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3349                 tx_flags |= IGB_TX_FLAGS_VLAN;
3350                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3351         }
3352
3353         if (skb->protocol == htons(ETH_P_IP))
3354                 tx_flags |= IGB_TX_FLAGS_IPV4;
3355
3356         first = tx_ring->next_to_use;
3357         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3358                                               &hdr_len) : 0;
3359
3360         if (tso < 0) {
3361                 dev_kfree_skb_any(skb);
3362                 return NETDEV_TX_OK;
3363         }
3364
3365         if (tso)
3366                 tx_flags |= IGB_TX_FLAGS_TSO;
3367         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3368                  (skb->ip_summed == CHECKSUM_PARTIAL))
3369                 tx_flags |= IGB_TX_FLAGS_CSUM;
3370
3371         /*
3372          * count reflects descriptors mapped, if 0 then mapping error
3373          * has occured and we need to rewind the descriptor queue
3374          */
3375         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3376
3377         if (count) {
3378                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3379                                  skb->len, hdr_len);
3380                 /* Make sure there is space in the ring for the next send. */
3381                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3382         } else {
3383                 dev_kfree_skb_any(skb);
3384                 tx_ring->buffer_info[first].time_stamp = 0;
3385                 tx_ring->next_to_use = first;
3386         }
3387
3388         return NETDEV_TX_OK;
3389 }
3390
3391 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
3392 {
3393         struct igb_adapter *adapter = netdev_priv(netdev);
3394         struct igb_ring *tx_ring;
3395
3396         int r_idx = 0;
3397         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3398         tx_ring = adapter->multi_tx_table[r_idx];
3399
3400         /* This goes back to the question of how to logically map a tx queue
3401          * to a flow.  Right now, performance is impacted slightly negatively
3402          * if using multiple tx queues.  If the stack breaks away from a
3403          * single qdisc implementation, we can look at this again. */
3404         return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
3405 }
3406
3407 /**
3408  * igb_tx_timeout - Respond to a Tx Hang
3409  * @netdev: network interface device structure
3410  **/
3411 static void igb_tx_timeout(struct net_device *netdev)
3412 {
3413         struct igb_adapter *adapter = netdev_priv(netdev);
3414         struct e1000_hw *hw = &adapter->hw;
3415
3416         /* Do the reset outside of interrupt context */
3417         adapter->tx_timeout_count++;
3418         schedule_work(&adapter->reset_task);
3419         wr32(E1000_EICS,
3420              (adapter->eims_enable_mask & ~adapter->eims_other));
3421 }
3422
3423 static void igb_reset_task(struct work_struct *work)
3424 {
3425         struct igb_adapter *adapter;
3426         adapter = container_of(work, struct igb_adapter, reset_task);
3427
3428         igb_reinit_locked(adapter);
3429 }
3430
3431 /**
3432  * igb_get_stats - Get System Network Statistics
3433  * @netdev: network interface device structure
3434  *
3435  * Returns the address of the device statistics structure.
3436  * The statistics are actually updated from the timer callback.
3437  **/
3438 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3439 {
3440         struct igb_adapter *adapter = netdev_priv(netdev);
3441
3442         /* only return the current stats */
3443         return &adapter->net_stats;
3444 }
3445
3446 /**
3447  * igb_change_mtu - Change the Maximum Transfer Unit
3448  * @netdev: network interface device structure
3449  * @new_mtu: new value for maximum frame size
3450  *
3451  * Returns 0 on success, negative on failure
3452  **/
3453 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3454 {
3455         struct igb_adapter *adapter = netdev_priv(netdev);
3456         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3457
3458         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3459             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3460                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3461                 return -EINVAL;
3462         }
3463
3464         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3465                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3466                 return -EINVAL;
3467         }
3468
3469         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3470                 msleep(1);
3471
3472         /* igb_down has a dependency on max_frame_size */
3473         adapter->max_frame_size = max_frame;
3474         if (netif_running(netdev))
3475                 igb_down(adapter);
3476
3477         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3478          * means we reserve 2 more, this pushes us to allocate from the next
3479          * larger slab size.
3480          * i.e. RXBUFFER_2048 --> size-4096 slab
3481          */
3482
3483         if (max_frame <= IGB_RXBUFFER_256)
3484                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3485         else if (max_frame <= IGB_RXBUFFER_512)
3486                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3487         else if (max_frame <= IGB_RXBUFFER_1024)
3488                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3489         else if (max_frame <= IGB_RXBUFFER_2048)
3490                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3491         else
3492 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3493                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3494 #else
3495                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3496 #endif
3497
3498         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3499         if (adapter->vfs_allocated_count &&
3500             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3501                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3502
3503         /* adjust allocation if LPE protects us, and we aren't using SBP */
3504         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3505              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3506                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3507
3508         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3509                  netdev->mtu, new_mtu);
3510         netdev->mtu = new_mtu;
3511
3512         if (netif_running(netdev))
3513                 igb_up(adapter);
3514         else
3515                 igb_reset(adapter);
3516
3517         clear_bit(__IGB_RESETTING, &adapter->state);
3518
3519         return 0;
3520 }
3521
3522 /**
3523  * igb_update_stats - Update the board statistics counters
3524  * @adapter: board private structure
3525  **/
3526
3527 void igb_update_stats(struct igb_adapter *adapter)
3528 {
3529         struct e1000_hw *hw = &adapter->hw;
3530         struct pci_dev *pdev = adapter->pdev;
3531         u16 phy_tmp;
3532
3533 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3534
3535         /*
3536          * Prevent stats update while adapter is being reset, or if the pci
3537          * connection is down.
3538          */
3539         if (adapter->link_speed == 0)
3540                 return;
3541         if (pci_channel_offline(pdev))
3542                 return;
3543
3544         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3545         adapter->stats.gprc += rd32(E1000_GPRC);
3546         adapter->stats.gorc += rd32(E1000_GORCL);
3547         rd32(E1000_GORCH); /* clear GORCL */
3548         adapter->stats.bprc += rd32(E1000_BPRC);
3549         adapter->stats.mprc += rd32(E1000_MPRC);
3550         adapter->stats.roc += rd32(E1000_ROC);
3551
3552         adapter->stats.prc64 += rd32(E1000_PRC64);
3553         adapter->stats.prc127 += rd32(E1000_PRC127);
3554         adapter->stats.prc255 += rd32(E1000_PRC255);
3555         adapter->stats.prc511 += rd32(E1000_PRC511);
3556         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3557         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3558         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3559         adapter->stats.sec += rd32(E1000_SEC);
3560
3561         adapter->stats.mpc += rd32(E1000_MPC);
3562         adapter->stats.scc += rd32(E1000_SCC);
3563         adapter->stats.ecol += rd32(E1000_ECOL);
3564         adapter->stats.mcc += rd32(E1000_MCC);
3565         adapter->stats.latecol += rd32(E1000_LATECOL);
3566         adapter->stats.dc += rd32(E1000_DC);
3567         adapter->stats.rlec += rd32(E1000_RLEC);
3568         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3569         adapter->stats.xontxc += rd32(E1000_XONTXC);
3570         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3571         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3572         adapter->stats.fcruc += rd32(E1000_FCRUC);
3573         adapter->stats.gptc += rd32(E1000_GPTC);
3574         adapter->stats.gotc += rd32(E1000_GOTCL);
3575         rd32(E1000_GOTCH); /* clear GOTCL */
3576         adapter->stats.rnbc += rd32(E1000_RNBC);
3577         adapter->stats.ruc += rd32(E1000_RUC);
3578         adapter->stats.rfc += rd32(E1000_RFC);
3579         adapter->stats.rjc += rd32(E1000_RJC);
3580         adapter->stats.tor += rd32(E1000_TORH);
3581         adapter->stats.tot += rd32(E1000_TOTH);
3582         adapter->stats.tpr += rd32(E1000_TPR);
3583
3584         adapter->stats.ptc64 += rd32(E1000_PTC64);
3585         adapter->stats.ptc127 += rd32(E1000_PTC127);
3586         adapter->stats.ptc255 += rd32(E1000_PTC255);
3587         adapter->stats.ptc511 += rd32(E1000_PTC511);
3588         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3589         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3590
3591         adapter->stats.mptc += rd32(E1000_MPTC);
3592         adapter->stats.bptc += rd32(E1000_BPTC);
3593
3594         /* used for adaptive IFS */
3595
3596         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3597         adapter->stats.tpt += hw->mac.tx_packet_delta;
3598         hw->mac.collision_delta = rd32(E1000_COLC);
3599         adapter->stats.colc += hw->mac.collision_delta;
3600
3601         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3602         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3603         adapter->stats.tncrs += rd32(E1000_TNCRS);
3604         adapter->stats.tsctc += rd32(E1000_TSCTC);
3605         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3606
3607         adapter->stats.iac += rd32(E1000_IAC);
3608         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3609         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3610         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3611         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3612         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3613         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3614         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3615         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3616
3617         /* Fill out the OS statistics structure */
3618         adapter->net_stats.multicast = adapter->stats.mprc;
3619         adapter->net_stats.collisions = adapter->stats.colc;
3620
3621         /* Rx Errors */
3622
3623         if (hw->mac.type != e1000_82575) {
3624                 u32 rqdpc_tmp;
3625                 u64 rqdpc_total = 0;
3626                 int i;
3627                 /* Read out drops stats per RX queue.  Notice RQDPC (Receive
3628                  * Queue Drop Packet Count) stats only gets incremented, if
3629                  * the DROP_EN but it set (in the SRRCTL register for that
3630                  * queue).  If DROP_EN bit is NOT set, then the some what
3631                  * equivalent count is stored in RNBC (not per queue basis).
3632                  * Also note the drop count is due to lack of available
3633                  * descriptors.
3634                  */
3635                 for (i = 0; i < adapter->num_rx_queues; i++) {
3636                         rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3637                         adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3638                         rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
3639                 }
3640                 adapter->net_stats.rx_fifo_errors = rqdpc_total;
3641         }
3642
3643         /* Note RNBC (Receive No Buffers Count) is an not an exact
3644          * drop count as the hardware FIFO might save the day.  Thats
3645          * one of the reason for saving it in rx_fifo_errors, as its
3646          * potentially not a true drop.
3647          */
3648         adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3649
3650         /* RLEC on some newer hardware can be incorrect so build
3651          * our own version based on RUC and ROC */
3652         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3653                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3654                 adapter->stats.ruc + adapter->stats.roc +
3655                 adapter->stats.cexterr;
3656         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3657                                               adapter->stats.roc;
3658         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3659         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3660         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3661
3662         /* Tx Errors */
3663         adapter->net_stats.tx_errors = adapter->stats.ecol +
3664                                        adapter->stats.latecol;
3665         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3666         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3667         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3668
3669         /* Tx Dropped needs to be maintained elsewhere */
3670
3671         /* Phy Stats */
3672         if (hw->phy.media_type == e1000_media_type_copper) {
3673                 if ((adapter->link_speed == SPEED_1000) &&
3674                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3675                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3676                         adapter->phy_stats.idle_errors += phy_tmp;
3677                 }
3678         }
3679
3680         /* Management Stats */
3681         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3682         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3683         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3684 }
3685
3686 static irqreturn_t igb_msix_other(int irq, void *data)
3687 {
3688         struct net_device *netdev = data;
3689         struct igb_adapter *adapter = netdev_priv(netdev);
3690         struct e1000_hw *hw = &adapter->hw;
3691         u32 icr = rd32(E1000_ICR);
3692
3693         /* reading ICR causes bit 31 of EICR to be cleared */
3694
3695         if(icr & E1000_ICR_DOUTSYNC) {
3696                 /* HW is reporting DMA is out of sync */
3697                 adapter->stats.doosync++;
3698         }
3699
3700         /* Check for a mailbox event */
3701         if (icr & E1000_ICR_VMMB)
3702                 igb_msg_task(adapter);
3703
3704         if (icr & E1000_ICR_LSC) {
3705                 hw->mac.get_link_status = 1;
3706                 /* guard against interrupt when we're going down */
3707                 if (!test_bit(__IGB_DOWN, &adapter->state))
3708                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3709         }
3710
3711         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3712         wr32(E1000_EIMS, adapter->eims_other);
3713
3714         return IRQ_HANDLED;
3715 }
3716
3717 static irqreturn_t igb_msix_tx(int irq, void *data)
3718 {
3719         struct igb_ring *tx_ring = data;
3720         struct igb_adapter *adapter = tx_ring->adapter;
3721         struct e1000_hw *hw = &adapter->hw;
3722
3723 #ifdef CONFIG_IGB_DCA
3724         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3725                 igb_update_tx_dca(tx_ring);
3726 #endif
3727
3728         tx_ring->total_bytes = 0;
3729         tx_ring->total_packets = 0;
3730
3731         /* auto mask will automatically reenable the interrupt when we write
3732          * EICS */
3733         if (!igb_clean_tx_irq(tx_ring))
3734                 /* Ring was not completely cleaned, so fire another interrupt */
3735                 wr32(E1000_EICS, tx_ring->eims_value);
3736         else
3737                 wr32(E1000_EIMS, tx_ring->eims_value);
3738
3739         return IRQ_HANDLED;
3740 }
3741
3742 static void igb_write_itr(struct igb_ring *ring)
3743 {
3744         struct e1000_hw *hw = &ring->adapter->hw;
3745         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3746                 switch (hw->mac.type) {
3747                 case e1000_82576:
3748                         wr32(ring->itr_register, ring->itr_val |
3749                              0x80000000);
3750                         break;
3751                 default:
3752                         wr32(ring->itr_register, ring->itr_val |
3753                              (ring->itr_val << 16));
3754                         break;
3755                 }
3756                 ring->set_itr = 0;
3757         }
3758 }
3759
3760 static irqreturn_t igb_msix_rx(int irq, void *data)
3761 {
3762         struct igb_ring *rx_ring = data;
3763
3764         /* Write the ITR value calculated at the end of the
3765          * previous interrupt.
3766          */
3767
3768         igb_write_itr(rx_ring);
3769
3770         if (napi_schedule_prep(&rx_ring->napi))
3771                 __napi_schedule(&rx_ring->napi);
3772
3773 #ifdef CONFIG_IGB_DCA
3774         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3775                 igb_update_rx_dca(rx_ring);
3776 #endif
3777                 return IRQ_HANDLED;
3778 }
3779
3780 #ifdef CONFIG_IGB_DCA
3781 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3782 {
3783         u32 dca_rxctrl;
3784         struct igb_adapter *adapter = rx_ring->adapter;
3785         struct e1000_hw *hw = &adapter->hw;
3786         int cpu = get_cpu();
3787         int q = rx_ring->reg_idx;
3788
3789         if (rx_ring->cpu != cpu) {
3790                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3791                 if (hw->mac.type == e1000_82576) {
3792                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3793                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3794                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3795                 } else {
3796                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3797                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3798                 }
3799                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3800                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3801                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3802                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3803                 rx_ring->cpu = cpu;
3804         }
3805         put_cpu();
3806 }
3807
3808 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3809 {
3810         u32 dca_txctrl;
3811         struct igb_adapter *adapter = tx_ring->adapter;
3812         struct e1000_hw *hw = &adapter->hw;
3813         int cpu = get_cpu();
3814         int q = tx_ring->reg_idx;
3815
3816         if (tx_ring->cpu != cpu) {
3817                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3818                 if (hw->mac.type == e1000_82576) {
3819                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3820                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3821                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3822                 } else {
3823                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3824                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3825                 }
3826                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3827                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3828                 tx_ring->cpu = cpu;
3829         }
3830         put_cpu();
3831 }
3832
3833 static void igb_setup_dca(struct igb_adapter *adapter)
3834 {
3835         struct e1000_hw *hw = &adapter->hw;
3836         int i;
3837
3838         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3839                 return;
3840
3841         /* Always use CB2 mode, difference is masked in the CB driver. */
3842         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3843
3844         for (i = 0; i < adapter->num_tx_queues; i++) {
3845                 adapter->tx_ring[i].cpu = -1;
3846                 igb_update_tx_dca(&adapter->tx_ring[i]);
3847         }
3848         for (i = 0; i < adapter->num_rx_queues; i++) {
3849                 adapter->rx_ring[i].cpu = -1;
3850                 igb_update_rx_dca(&adapter->rx_ring[i]);
3851         }
3852 }
3853
3854 static int __igb_notify_dca(struct device *dev, void *data)
3855 {
3856         struct net_device *netdev = dev_get_drvdata(dev);
3857         struct igb_adapter *adapter = netdev_priv(netdev);
3858         struct e1000_hw *hw = &adapter->hw;
3859         unsigned long event = *(unsigned long *)data;
3860
3861         switch (event) {
3862         case DCA_PROVIDER_ADD:
3863                 /* if already enabled, don't do it again */
3864                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3865                         break;
3866                 /* Always use CB2 mode, difference is masked
3867                  * in the CB driver. */
3868                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3869                 if (dca_add_requester(dev) == 0) {
3870                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3871                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3872                         igb_setup_dca(adapter);
3873                         break;
3874                 }
3875                 /* Fall Through since DCA is disabled. */
3876         case DCA_PROVIDER_REMOVE:
3877                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3878                         /* without this a class_device is left
3879                          * hanging around in the sysfs model */
3880                         dca_remove_requester(dev);
3881                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3882                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3883                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3884                 }
3885                 break;
3886         }
3887
3888         return 0;
3889 }
3890
3891 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3892                           void *p)
3893 {
3894         int ret_val;
3895
3896         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3897                                          __igb_notify_dca);
3898
3899         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3900 }
3901 #endif /* CONFIG_IGB_DCA */
3902
3903 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3904 {
3905         struct e1000_hw *hw = &adapter->hw;
3906         u32 ping;
3907         int i;
3908
3909         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3910                 ping = E1000_PF_CONTROL_MSG;
3911                 if (adapter->vf_data[i].clear_to_send)
3912                         ping |= E1000_VT_MSGTYPE_CTS;
3913                 igb_write_mbx(hw, &ping, 1, i);
3914         }
3915 }
3916
3917 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3918                                   u32 *msgbuf, u32 vf)
3919 {
3920         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3921         u16 *hash_list = (u16 *)&msgbuf[1];
3922         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3923         int i;
3924
3925         /* only up to 30 hash values supported */
3926         if (n > 30)
3927                 n = 30;
3928
3929         /* salt away the number of multi cast addresses assigned
3930          * to this VF for later use to restore when the PF multi cast
3931          * list changes
3932          */
3933         vf_data->num_vf_mc_hashes = n;
3934
3935         /* VFs are limited to using the MTA hash table for their multicast
3936          * addresses */
3937         for (i = 0; i < n; i++)
3938                 vf_data->vf_mc_hashes[i] = hash_list[i];;
3939
3940         /* Flush and reset the mta with the new values */
3941         igb_set_multi(adapter->netdev);
3942
3943         return 0;
3944 }
3945
3946 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3947 {
3948         struct e1000_hw *hw = &adapter->hw;
3949         struct vf_data_storage *vf_data;
3950         int i, j;
3951
3952         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3953                 vf_data = &adapter->vf_data[i];
3954                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3955                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3956         }
3957 }
3958
3959 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3960 {
3961         struct e1000_hw *hw = &adapter->hw;
3962         u32 pool_mask, reg, vid;
3963         int i;
3964
3965         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3966
3967         /* Find the vlan filter for this id */
3968         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3969                 reg = rd32(E1000_VLVF(i));
3970
3971                 /* remove the vf from the pool */
3972                 reg &= ~pool_mask;
3973
3974                 /* if pool is empty then remove entry from vfta */
3975                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
3976                     (reg & E1000_VLVF_VLANID_ENABLE)) {
3977                         reg = 0;
3978                         vid = reg & E1000_VLVF_VLANID_MASK;
3979                         igb_vfta_set(hw, vid, false);
3980                 }
3981
3982                 wr32(E1000_VLVF(i), reg);
3983         }
3984 }
3985
3986 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
3987 {
3988         struct e1000_hw *hw = &adapter->hw;
3989         u32 reg, i;
3990
3991         /* It is an error to call this function when VFs are not enabled */
3992         if (!adapter->vfs_allocated_count)
3993                 return -1;
3994
3995         /* Find the vlan filter for this id */
3996         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
3997                 reg = rd32(E1000_VLVF(i));
3998                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
3999                     vid == (reg & E1000_VLVF_VLANID_MASK))
4000                         break;
4001         }
4002
4003         if (add) {
4004                 if (i == E1000_VLVF_ARRAY_SIZE) {
4005                         /* Did not find a matching VLAN ID entry that was
4006                          * enabled.  Search for a free filter entry, i.e.
4007                          * one without the enable bit set
4008                          */
4009                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4010                                 reg = rd32(E1000_VLVF(i));
4011                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4012                                         break;
4013                         }
4014                 }
4015                 if (i < E1000_VLVF_ARRAY_SIZE) {
4016                         /* Found an enabled/available entry */
4017                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4018
4019                         /* if !enabled we need to set this up in vfta */
4020                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
4021                                 /* add VID to filter table, if bit already set
4022                                  * PF must have added it outside of table */
4023                                 if (igb_vfta_set(hw, vid, true))
4024                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4025                                                 adapter->vfs_allocated_count);
4026                                 reg |= E1000_VLVF_VLANID_ENABLE;
4027                         }
4028                         reg &= ~E1000_VLVF_VLANID_MASK;
4029                         reg |= vid;
4030
4031                         wr32(E1000_VLVF(i), reg);
4032                         return 0;
4033                 }
4034         } else {
4035                 if (i < E1000_VLVF_ARRAY_SIZE) {
4036                         /* remove vf from the pool */
4037                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4038                         /* if pool is empty then remove entry from vfta */
4039                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4040                                 reg = 0;
4041                                 igb_vfta_set(hw, vid, false);
4042                         }
4043                         wr32(E1000_VLVF(i), reg);
4044                         return 0;
4045                 }
4046         }
4047         return -1;
4048 }
4049
4050 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4051 {
4052         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4053         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4054
4055         return igb_vlvf_set(adapter, vid, add, vf);
4056 }
4057
4058 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4059 {
4060         struct e1000_hw *hw = &adapter->hw;
4061
4062         /* disable mailbox functionality for vf */
4063         adapter->vf_data[vf].clear_to_send = false;
4064
4065         /* reset offloads to defaults */
4066         igb_set_vmolr(hw, vf);
4067
4068         /* reset vlans for device */
4069         igb_clear_vf_vfta(adapter, vf);
4070
4071         /* reset multicast table array for vf */
4072         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4073
4074         /* Flush and reset the mta with the new values */
4075         igb_set_multi(adapter->netdev);
4076 }
4077
4078 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4079 {
4080         struct e1000_hw *hw = &adapter->hw;
4081         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4082         u32 reg, msgbuf[3];
4083         u8 *addr = (u8 *)(&msgbuf[1]);
4084
4085         /* process all the same items cleared in a function level reset */
4086         igb_vf_reset_event(adapter, vf);
4087
4088         /* set vf mac address */
4089         igb_rar_set(hw, vf_mac, vf + 1);
4090         igb_set_rah_pool(hw, vf, vf + 1);
4091
4092         /* enable transmit and receive for vf */
4093         reg = rd32(E1000_VFTE);
4094         wr32(E1000_VFTE, reg | (1 << vf));
4095         reg = rd32(E1000_VFRE);
4096         wr32(E1000_VFRE, reg | (1 << vf));
4097
4098         /* enable mailbox functionality for vf */
4099         adapter->vf_data[vf].clear_to_send = true;
4100
4101         /* reply to reset with ack and vf mac address */
4102         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4103         memcpy(addr, vf_mac, 6);
4104         igb_write_mbx(hw, msgbuf, 3, vf);
4105 }
4106
4107 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4108 {
4109                 unsigned char *addr = (char *)&msg[1];
4110                 int err = -1;
4111
4112                 if (is_valid_ether_addr(addr))
4113                         err = igb_set_vf_mac(adapter, vf, addr);
4114
4115                 return err;
4116
4117 }
4118
4119 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4120 {
4121         struct e1000_hw *hw = &adapter->hw;
4122         u32 msg = E1000_VT_MSGTYPE_NACK;
4123
4124         /* if device isn't clear to send it shouldn't be reading either */
4125         if (!adapter->vf_data[vf].clear_to_send)
4126                 igb_write_mbx(hw, &msg, 1, vf);
4127 }
4128
4129
4130 static void igb_msg_task(struct igb_adapter *adapter)
4131 {
4132         struct e1000_hw *hw = &adapter->hw;
4133         u32 vf;
4134
4135         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4136                 /* process any reset requests */
4137                 if (!igb_check_for_rst(hw, vf)) {
4138                         adapter->vf_data[vf].clear_to_send = false;
4139                         igb_vf_reset_event(adapter, vf);
4140                 }
4141
4142                 /* process any messages pending */
4143                 if (!igb_check_for_msg(hw, vf))
4144                         igb_rcv_msg_from_vf(adapter, vf);
4145
4146                 /* process any acks */
4147                 if (!igb_check_for_ack(hw, vf))
4148                         igb_rcv_ack_from_vf(adapter, vf);
4149
4150         }
4151 }
4152
4153 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4154 {
4155         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4156         u32 msgbuf[mbx_size];
4157         struct e1000_hw *hw = &adapter->hw;
4158         s32 retval;
4159
4160         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4161
4162         if (retval)
4163                 dev_err(&adapter->pdev->dev,
4164                         "Error receiving message from VF\n");
4165
4166         /* this is a message we already processed, do nothing */
4167         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4168                 return retval;
4169
4170         /*
4171          * until the vf completes a reset it should not be
4172          * allowed to start any configuration.
4173          */
4174
4175         if (msgbuf[0] == E1000_VF_RESET) {
4176                 igb_vf_reset_msg(adapter, vf);
4177
4178                 return retval;
4179         }
4180
4181         if (!adapter->vf_data[vf].clear_to_send) {
4182                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4183                 igb_write_mbx(hw, msgbuf, 1, vf);
4184                 return retval;
4185         }
4186
4187         switch ((msgbuf[0] & 0xFFFF)) {
4188         case E1000_VF_SET_MAC_ADDR:
4189                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4190                 break;
4191         case E1000_VF_SET_MULTICAST:
4192                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4193                 break;
4194         case E1000_VF_SET_LPE:
4195                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4196                 break;
4197         case E1000_VF_SET_VLAN:
4198                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4199                 break;
4200         default:
4201                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4202                 retval = -1;
4203                 break;
4204         }
4205
4206         /* notify the VF of the results of what it sent us */
4207         if (retval)
4208                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4209         else
4210                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4211
4212         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4213
4214         igb_write_mbx(hw, msgbuf, 1, vf);
4215
4216         return retval;
4217 }
4218
4219 /**
4220  * igb_intr_msi - Interrupt Handler
4221  * @irq: interrupt number
4222  * @data: pointer to a network interface device structure
4223  **/
4224 static irqreturn_t igb_intr_msi(int irq, void *data)
4225 {
4226         struct net_device *netdev = data;
4227         struct igb_adapter *adapter = netdev_priv(netdev);
4228         struct e1000_hw *hw = &adapter->hw;
4229         /* read ICR disables interrupts using IAM */
4230         u32 icr = rd32(E1000_ICR);
4231
4232         igb_write_itr(adapter->rx_ring);
4233
4234         if(icr & E1000_ICR_DOUTSYNC) {
4235                 /* HW is reporting DMA is out of sync */
4236                 adapter->stats.doosync++;
4237         }
4238
4239         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4240                 hw->mac.get_link_status = 1;
4241                 if (!test_bit(__IGB_DOWN, &adapter->state))
4242                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4243         }
4244
4245         napi_schedule(&adapter->rx_ring[0].napi);
4246
4247         return IRQ_HANDLED;
4248 }
4249
4250 /**
4251  * igb_intr - Legacy Interrupt Handler
4252  * @irq: interrupt number
4253  * @data: pointer to a network interface device structure
4254  **/
4255 static irqreturn_t igb_intr(int irq, void *data)
4256 {
4257         struct net_device *netdev = data;
4258         struct igb_adapter *adapter = netdev_priv(netdev);
4259         struct e1000_hw *hw = &adapter->hw;
4260         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4261          * need for the IMC write */
4262         u32 icr = rd32(E1000_ICR);
4263         if (!icr)
4264                 return IRQ_NONE;  /* Not our interrupt */
4265
4266         igb_write_itr(adapter->rx_ring);
4267
4268         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4269          * not set, then the adapter didn't send an interrupt */
4270         if (!(icr & E1000_ICR_INT_ASSERTED))
4271                 return IRQ_NONE;
4272
4273         if(icr & E1000_ICR_DOUTSYNC) {
4274                 /* HW is reporting DMA is out of sync */
4275                 adapter->stats.doosync++;
4276         }
4277
4278         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4279                 hw->mac.get_link_status = 1;
4280                 /* guard against interrupt when we're going down */
4281                 if (!test_bit(__IGB_DOWN, &adapter->state))
4282                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4283         }
4284
4285         napi_schedule(&adapter->rx_ring[0].napi);
4286
4287         return IRQ_HANDLED;
4288 }
4289
4290 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4291 {
4292         struct igb_adapter *adapter = rx_ring->adapter;
4293         struct e1000_hw *hw = &adapter->hw;
4294
4295         if (adapter->itr_setting & 3) {
4296                 if (adapter->num_rx_queues == 1)
4297                         igb_set_itr(adapter);
4298                 else
4299                         igb_update_ring_itr(rx_ring);
4300         }
4301
4302         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4303                 if (adapter->msix_entries)
4304                         wr32(E1000_EIMS, rx_ring->eims_value);
4305                 else
4306                         igb_irq_enable(adapter);
4307         }
4308 }
4309
4310 /**
4311  * igb_poll - NAPI Rx polling callback
4312  * @napi: napi polling structure
4313  * @budget: count of how many packets we should handle
4314  **/
4315 static int igb_poll(struct napi_struct *napi, int budget)
4316 {
4317         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4318         int work_done = 0;
4319
4320 #ifdef CONFIG_IGB_DCA
4321         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4322                 igb_update_rx_dca(rx_ring);
4323 #endif
4324         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4325
4326         if (rx_ring->buddy) {
4327 #ifdef CONFIG_IGB_DCA
4328                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4329                         igb_update_tx_dca(rx_ring->buddy);
4330 #endif
4331                 if (!igb_clean_tx_irq(rx_ring->buddy))
4332                         work_done = budget;
4333         }
4334
4335         /* If not enough Rx work done, exit the polling mode */
4336         if (work_done < budget) {
4337                 napi_complete(napi);
4338                 igb_rx_irq_enable(rx_ring);
4339         }
4340
4341         return work_done;
4342 }
4343
4344 /**
4345  * igb_hwtstamp - utility function which checks for TX time stamp
4346  * @adapter: board private structure
4347  * @skb: packet that was just sent
4348  *
4349  * If we were asked to do hardware stamping and such a time stamp is
4350  * available, then it must have been for this skb here because we only
4351  * allow only one such packet into the queue.
4352  */
4353 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4354 {
4355         union skb_shared_tx *shtx = skb_tx(skb);
4356         struct e1000_hw *hw = &adapter->hw;
4357
4358         if (unlikely(shtx->hardware)) {
4359                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4360                 if (valid) {
4361                         u64 regval = rd32(E1000_TXSTMPL);
4362                         u64 ns;
4363                         struct skb_shared_hwtstamps shhwtstamps;
4364
4365                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4366                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4367                         ns = timecounter_cyc2time(&adapter->clock,
4368                                                   regval);
4369                         timecompare_update(&adapter->compare, ns);
4370                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4371                         shhwtstamps.syststamp =
4372                                 timecompare_transform(&adapter->compare, ns);
4373                         skb_tstamp_tx(skb, &shhwtstamps);
4374                 }
4375         }
4376 }
4377
4378 /**
4379  * igb_clean_tx_irq - Reclaim resources after transmit completes
4380  * @adapter: board private structure
4381  * returns true if ring is completely cleaned
4382  **/
4383 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4384 {
4385         struct igb_adapter *adapter = tx_ring->adapter;
4386         struct net_device *netdev = adapter->netdev;
4387         struct e1000_hw *hw = &adapter->hw;
4388         struct igb_buffer *buffer_info;
4389         struct sk_buff *skb;
4390         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4391         unsigned int total_bytes = 0, total_packets = 0;
4392         unsigned int i, eop, count = 0;
4393         bool cleaned = false;
4394
4395         i = tx_ring->next_to_clean;
4396         eop = tx_ring->buffer_info[i].next_to_watch;
4397         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4398
4399         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4400                (count < tx_ring->count)) {
4401                 for (cleaned = false; !cleaned; count++) {
4402                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4403                         buffer_info = &tx_ring->buffer_info[i];
4404                         cleaned = (i == eop);
4405                         skb = buffer_info->skb;
4406
4407                         if (skb) {
4408                                 unsigned int segs, bytecount;
4409                                 /* gso_segs is currently only valid for tcp */
4410                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4411                                 /* multiply data chunks by size of headers */
4412                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4413                                             skb->len;
4414                                 total_packets += segs;
4415                                 total_bytes += bytecount;
4416
4417                                 igb_tx_hwtstamp(adapter, skb);
4418                         }
4419
4420                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4421                         tx_desc->wb.status = 0;
4422
4423                         i++;
4424                         if (i == tx_ring->count)
4425                                 i = 0;
4426                 }
4427                 eop = tx_ring->buffer_info[i].next_to_watch;
4428                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4429         }
4430
4431         tx_ring->next_to_clean = i;
4432
4433         if (unlikely(count &&
4434                      netif_carrier_ok(netdev) &&
4435                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4436                 /* Make sure that anybody stopping the queue after this
4437                  * sees the new next_to_clean.
4438                  */
4439                 smp_mb();
4440                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4441                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4442                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4443                         ++adapter->restart_queue;
4444                 }
4445         }
4446
4447         if (tx_ring->detect_tx_hung) {
4448                 /* Detect a transmit hang in hardware, this serializes the
4449                  * check with the clearing of time_stamp and movement of i */
4450                 tx_ring->detect_tx_hung = false;
4451                 if (tx_ring->buffer_info[i].time_stamp &&
4452                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4453                                (adapter->tx_timeout_factor * HZ))
4454                     && !(rd32(E1000_STATUS) &
4455                          E1000_STATUS_TXOFF)) {
4456
4457                         /* detected Tx unit hang */
4458                         dev_err(&adapter->pdev->dev,
4459                                 "Detected Tx Unit Hang\n"
4460                                 "  Tx Queue             <%d>\n"
4461                                 "  TDH                  <%x>\n"
4462                                 "  TDT                  <%x>\n"
4463                                 "  next_to_use          <%x>\n"
4464                                 "  next_to_clean        <%x>\n"
4465                                 "buffer_info[next_to_clean]\n"
4466                                 "  time_stamp           <%lx>\n"
4467                                 "  next_to_watch        <%x>\n"
4468                                 "  jiffies              <%lx>\n"
4469                                 "  desc.status          <%x>\n",
4470                                 tx_ring->queue_index,
4471                                 readl(adapter->hw.hw_addr + tx_ring->head),
4472                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4473                                 tx_ring->next_to_use,
4474                                 tx_ring->next_to_clean,
4475                                 tx_ring->buffer_info[i].time_stamp,
4476                                 eop,
4477                                 jiffies,
4478                                 eop_desc->wb.status);
4479                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4480                 }
4481         }
4482         tx_ring->total_bytes += total_bytes;
4483         tx_ring->total_packets += total_packets;
4484         tx_ring->tx_stats.bytes += total_bytes;
4485         tx_ring->tx_stats.packets += total_packets;
4486         adapter->net_stats.tx_bytes += total_bytes;
4487         adapter->net_stats.tx_packets += total_packets;
4488         return (count < tx_ring->count);
4489 }
4490
4491 /**
4492  * igb_receive_skb - helper function to handle rx indications
4493  * @ring: pointer to receive ring receving this packet
4494  * @status: descriptor status field as written by hardware
4495  * @rx_desc: receive descriptor containing vlan and type information.
4496  * @skb: pointer to sk_buff to be indicated to stack
4497  **/
4498 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4499                             union e1000_adv_rx_desc * rx_desc,
4500                             struct sk_buff *skb)
4501 {
4502         struct igb_adapter * adapter = ring->adapter;
4503         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4504
4505         skb_record_rx_queue(skb, ring->queue_index);
4506         if (vlan_extracted)
4507                 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4508                                  le16_to_cpu(rx_desc->wb.upper.vlan),
4509                                  skb);
4510         else
4511                 napi_gro_receive(&ring->napi, skb);
4512 }
4513
4514 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4515                                        u32 status_err, struct sk_buff *skb)
4516 {
4517         skb->ip_summed = CHECKSUM_NONE;
4518
4519         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4520         if ((status_err & E1000_RXD_STAT_IXSM) ||
4521             (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4522                 return;
4523         /* TCP/UDP checksum error bit is set */
4524         if (status_err &
4525             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4526                 /*
4527                  * work around errata with sctp packets where the TCPE aka
4528                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4529                  * packets, (aka let the stack check the crc32c)
4530                  */
4531                 if (!((adapter->hw.mac.type == e1000_82576) &&
4532                       (skb->len == 60)))
4533                         adapter->hw_csum_err++;
4534                 /* let the stack verify checksum errors */
4535                 return;
4536         }
4537         /* It must be a TCP or UDP packet with a valid checksum */
4538         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4539                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4540
4541         dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4542         adapter->hw_csum_good++;
4543 }
4544
4545 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4546                                  int *work_done, int budget)
4547 {
4548         struct igb_adapter *adapter = rx_ring->adapter;
4549         struct net_device *netdev = adapter->netdev;
4550         struct e1000_hw *hw = &adapter->hw;
4551         struct pci_dev *pdev = adapter->pdev;
4552         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4553         struct igb_buffer *buffer_info , *next_buffer;
4554         struct sk_buff *skb;
4555         bool cleaned = false;
4556         int cleaned_count = 0;
4557         unsigned int total_bytes = 0, total_packets = 0;
4558         unsigned int i;
4559         u32 length, hlen, staterr;
4560
4561         i = rx_ring->next_to_clean;
4562         buffer_info = &rx_ring->buffer_info[i];
4563         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4564         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4565
4566         while (staterr & E1000_RXD_STAT_DD) {
4567                 if (*work_done >= budget)
4568                         break;
4569                 (*work_done)++;
4570
4571                 skb = buffer_info->skb;
4572                 prefetch(skb->data - NET_IP_ALIGN);
4573                 buffer_info->skb = NULL;
4574
4575                 i++;
4576                 if (i == rx_ring->count)
4577                         i = 0;
4578                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4579                 prefetch(next_rxd);
4580                 next_buffer = &rx_ring->buffer_info[i];
4581
4582                 length = le16_to_cpu(rx_desc->wb.upper.length);
4583                 cleaned = true;
4584                 cleaned_count++;
4585
4586                 /* this is the fast path for the non-packet split case */
4587                 if (!adapter->rx_ps_hdr_size) {
4588                         pci_unmap_single(pdev, buffer_info->dma,
4589                                          adapter->rx_buffer_len,
4590                                          PCI_DMA_FROMDEVICE);
4591                         buffer_info->dma = 0;
4592                         skb_put(skb, length);
4593                         goto send_up;
4594                 }
4595
4596                 /* HW will not DMA in data larger than the given buffer, even
4597                  * if it parses the (NFS, of course) header to be larger.  In
4598                  * that case, it fills the header buffer and spills the rest
4599                  * into the page.
4600                  */
4601                 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4602                   E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4603                 if (hlen > adapter->rx_ps_hdr_size)
4604                         hlen = adapter->rx_ps_hdr_size;
4605
4606                 if (!skb_shinfo(skb)->nr_frags) {
4607                         pci_unmap_single(pdev, buffer_info->dma,
4608                                          adapter->rx_ps_hdr_size,
4609                                          PCI_DMA_FROMDEVICE);
4610                         buffer_info->dma = 0;
4611                         skb_put(skb, hlen);
4612                 }
4613
4614                 if (length) {
4615                         pci_unmap_page(pdev, buffer_info->page_dma,
4616                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4617                         buffer_info->page_dma = 0;
4618
4619                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4620                                                 buffer_info->page,
4621                                                 buffer_info->page_offset,
4622                                                 length);
4623
4624                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4625                             (page_count(buffer_info->page) != 1))
4626                                 buffer_info->page = NULL;
4627                         else
4628                                 get_page(buffer_info->page);
4629
4630                         skb->len += length;
4631                         skb->data_len += length;
4632
4633                         skb->truesize += length;
4634                 }
4635
4636                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4637                         buffer_info->skb = next_buffer->skb;
4638                         buffer_info->dma = next_buffer->dma;
4639                         next_buffer->skb = skb;
4640                         next_buffer->dma = 0;
4641                         goto next_desc;
4642                 }
4643 send_up:
4644                 /*
4645                  * If this bit is set, then the RX registers contain
4646                  * the time stamp. No other packet will be time
4647                  * stamped until we read these registers, so read the
4648                  * registers to make them available again. Because
4649                  * only one packet can be time stamped at a time, we
4650                  * know that the register values must belong to this
4651                  * one here and therefore we don't need to compare
4652                  * any of the additional attributes stored for it.
4653                  *
4654                  * If nothing went wrong, then it should have a
4655                  * skb_shared_tx that we can turn into a
4656                  * skb_shared_hwtstamps.
4657                  *
4658                  * TODO: can time stamping be triggered (thus locking
4659                  * the registers) without the packet reaching this point
4660                  * here? In that case RX time stamping would get stuck.
4661                  *
4662                  * TODO: in "time stamp all packets" mode this bit is
4663                  * not set. Need a global flag for this mode and then
4664                  * always read the registers. Cannot be done without
4665                  * a race condition.
4666                  */
4667                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4668                         u64 regval;
4669                         u64 ns;
4670                         struct skb_shared_hwtstamps *shhwtstamps =
4671                                 skb_hwtstamps(skb);
4672
4673                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4674                              "igb: no RX time stamp available for time stamped packet");
4675                         regval = rd32(E1000_RXSTMPL);
4676                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4677                         ns = timecounter_cyc2time(&adapter->clock, regval);
4678                         timecompare_update(&adapter->compare, ns);
4679                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4680                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4681                         shhwtstamps->syststamp =
4682                                 timecompare_transform(&adapter->compare, ns);
4683                 }
4684
4685                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4686                         dev_kfree_skb_irq(skb);
4687                         goto next_desc;
4688                 }
4689
4690                 total_bytes += skb->len;
4691                 total_packets++;
4692
4693                 igb_rx_checksum_adv(adapter, staterr, skb);
4694
4695                 skb->protocol = eth_type_trans(skb, netdev);
4696
4697                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4698
4699 next_desc:
4700                 rx_desc->wb.upper.status_error = 0;
4701
4702                 /* return some buffers to hardware, one at a time is too slow */
4703                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4704                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4705                         cleaned_count = 0;
4706                 }
4707
4708                 /* use prefetched values */
4709                 rx_desc = next_rxd;
4710                 buffer_info = next_buffer;
4711                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4712         }
4713
4714         rx_ring->next_to_clean = i;
4715         cleaned_count = igb_desc_unused(rx_ring);
4716
4717         if (cleaned_count)
4718                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4719
4720         rx_ring->total_packets += total_packets;
4721         rx_ring->total_bytes += total_bytes;
4722         rx_ring->rx_stats.packets += total_packets;
4723         rx_ring->rx_stats.bytes += total_bytes;
4724         adapter->net_stats.rx_bytes += total_bytes;
4725         adapter->net_stats.rx_packets += total_packets;
4726         return cleaned;
4727 }
4728
4729 /**
4730  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4731  * @adapter: address of board private structure
4732  **/
4733 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4734                                      int cleaned_count)
4735 {
4736         struct igb_adapter *adapter = rx_ring->adapter;
4737         struct net_device *netdev = adapter->netdev;
4738         struct pci_dev *pdev = adapter->pdev;
4739         union e1000_adv_rx_desc *rx_desc;
4740         struct igb_buffer *buffer_info;
4741         struct sk_buff *skb;
4742         unsigned int i;
4743         int bufsz;
4744
4745         i = rx_ring->next_to_use;
4746         buffer_info = &rx_ring->buffer_info[i];
4747
4748         if (adapter->rx_ps_hdr_size)
4749                 bufsz = adapter->rx_ps_hdr_size;
4750         else
4751                 bufsz = adapter->rx_buffer_len;
4752
4753         while (cleaned_count--) {
4754                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4755
4756                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4757                         if (!buffer_info->page) {
4758                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4759                                 if (!buffer_info->page) {
4760                                         adapter->alloc_rx_buff_failed++;
4761                                         goto no_buffers;
4762                                 }
4763                                 buffer_info->page_offset = 0;
4764                         } else {
4765                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4766                         }
4767                         buffer_info->page_dma =
4768                                 pci_map_page(pdev, buffer_info->page,
4769                                              buffer_info->page_offset,
4770                                              PAGE_SIZE / 2,
4771                                              PCI_DMA_FROMDEVICE);
4772                 }
4773
4774                 if (!buffer_info->skb) {
4775                         skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
4776                         if (!skb) {
4777                                 adapter->alloc_rx_buff_failed++;
4778                                 goto no_buffers;
4779                         }
4780
4781                         /* Make buffer alignment 2 beyond a 16 byte boundary
4782                          * this will result in a 16 byte aligned IP header after
4783                          * the 14 byte MAC header is removed
4784                          */
4785                         skb_reserve(skb, NET_IP_ALIGN);
4786
4787                         buffer_info->skb = skb;
4788                         buffer_info->dma = pci_map_single(pdev, skb->data,
4789                                                           bufsz,
4790                                                           PCI_DMA_FROMDEVICE);
4791                 }
4792                 /* Refresh the desc even if buffer_addrs didn't change because
4793                  * each write-back erases this info. */
4794                 if (adapter->rx_ps_hdr_size) {
4795                         rx_desc->read.pkt_addr =
4796                              cpu_to_le64(buffer_info->page_dma);
4797                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4798                 } else {
4799                         rx_desc->read.pkt_addr =
4800                              cpu_to_le64(buffer_info->dma);
4801                         rx_desc->read.hdr_addr = 0;
4802                 }
4803
4804                 i++;
4805                 if (i == rx_ring->count)
4806                         i = 0;
4807                 buffer_info = &rx_ring->buffer_info[i];
4808         }
4809
4810 no_buffers:
4811         if (rx_ring->next_to_use != i) {
4812                 rx_ring->next_to_use = i;
4813                 if (i == 0)
4814                         i = (rx_ring->count - 1);
4815                 else
4816                         i--;
4817
4818                 /* Force memory writes to complete before letting h/w
4819                  * know there are new descriptors to fetch.  (Only
4820                  * applicable for weak-ordered memory model archs,
4821                  * such as IA-64). */
4822                 wmb();
4823                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4824         }
4825 }
4826
4827 /**
4828  * igb_mii_ioctl -
4829  * @netdev:
4830  * @ifreq:
4831  * @cmd:
4832  **/
4833 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4834 {
4835         struct igb_adapter *adapter = netdev_priv(netdev);
4836         struct mii_ioctl_data *data = if_mii(ifr);
4837
4838         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4839                 return -EOPNOTSUPP;
4840
4841         switch (cmd) {
4842         case SIOCGMIIPHY:
4843                 data->phy_id = adapter->hw.phy.addr;
4844                 break;
4845         case SIOCGMIIREG:
4846                 if (!capable(CAP_NET_ADMIN))
4847                         return -EPERM;
4848                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4849                                      &data->val_out))
4850                         return -EIO;
4851                 break;
4852         case SIOCSMIIREG:
4853         default:
4854                 return -EOPNOTSUPP;
4855         }
4856         return 0;
4857 }
4858
4859 /**
4860  * igb_hwtstamp_ioctl - control hardware time stamping
4861  * @netdev:
4862  * @ifreq:
4863  * @cmd:
4864  *
4865  * Outgoing time stamping can be enabled and disabled. Play nice and
4866  * disable it when requested, although it shouldn't case any overhead
4867  * when no packet needs it. At most one packet in the queue may be
4868  * marked for time stamping, otherwise it would be impossible to tell
4869  * for sure to which packet the hardware time stamp belongs.
4870  *
4871  * Incoming time stamping has to be configured via the hardware
4872  * filters. Not all combinations are supported, in particular event
4873  * type has to be specified. Matching the kind of event packet is
4874  * not supported, with the exception of "all V2 events regardless of
4875  * level 2 or 4".
4876  *
4877  **/
4878 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4879                               struct ifreq *ifr, int cmd)
4880 {
4881         struct igb_adapter *adapter = netdev_priv(netdev);
4882         struct e1000_hw *hw = &adapter->hw;
4883         struct hwtstamp_config config;
4884         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4885         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4886         u32 tsync_rx_ctl_type = 0;
4887         u32 tsync_rx_cfg = 0;
4888         int is_l4 = 0;
4889         int is_l2 = 0;
4890         short port = 319; /* PTP */
4891         u32 regval;
4892
4893         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4894                 return -EFAULT;
4895
4896         /* reserved for future extensions */
4897         if (config.flags)
4898                 return -EINVAL;
4899
4900         switch (config.tx_type) {
4901         case HWTSTAMP_TX_OFF:
4902                 tsync_tx_ctl_bit = 0;
4903                 break;
4904         case HWTSTAMP_TX_ON:
4905                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4906                 break;
4907         default:
4908                 return -ERANGE;
4909         }
4910
4911         switch (config.rx_filter) {
4912         case HWTSTAMP_FILTER_NONE:
4913                 tsync_rx_ctl_bit = 0;
4914                 break;
4915         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4916         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4917         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4918         case HWTSTAMP_FILTER_ALL:
4919                 /*
4920                  * register TSYNCRXCFG must be set, therefore it is not
4921                  * possible to time stamp both Sync and Delay_Req messages
4922                  * => fall back to time stamping all packets
4923                  */
4924                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4925                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4926                 break;
4927         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4928                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4929                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4930                 is_l4 = 1;
4931                 break;
4932         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
4933                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4934                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
4935                 is_l4 = 1;
4936                 break;
4937         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4938         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4939                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4940                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
4941                 is_l2 = 1;
4942                 is_l4 = 1;
4943                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4944                 break;
4945         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4946         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4947                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
4948                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
4949                 is_l2 = 1;
4950                 is_l4 = 1;
4951                 config.rx_filter = HWTSTAMP_FILTER_SOME;
4952                 break;
4953         case HWTSTAMP_FILTER_PTP_V2_EVENT:
4954         case HWTSTAMP_FILTER_PTP_V2_SYNC:
4955         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4956                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
4957                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
4958                 is_l2 = 1;
4959                 break;
4960         default:
4961                 return -ERANGE;
4962         }
4963
4964         /* enable/disable TX */
4965         regval = rd32(E1000_TSYNCTXCTL);
4966         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
4967         wr32(E1000_TSYNCTXCTL, regval);
4968
4969         /* enable/disable RX, define which PTP packets are time stamped */
4970         regval = rd32(E1000_TSYNCRXCTL);
4971         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
4972         regval = (regval & ~0xE) | tsync_rx_ctl_type;
4973         wr32(E1000_TSYNCRXCTL, regval);
4974         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
4975
4976         /*
4977          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
4978          *                                          (Ethertype to filter on)
4979          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
4980          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
4981          */
4982         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
4983
4984         /* L4 Queue Filter[0]: only filter by source and destination port */
4985         wr32(E1000_SPQF0, htons(port));
4986         wr32(E1000_IMIREXT(0), is_l4 ?
4987              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
4988         wr32(E1000_IMIR(0), is_l4 ?
4989              (htons(port)
4990               | (0<<16) /* immediate interrupt disabled */
4991               | 0 /* (1<<17) bit cleared: do not bypass
4992                      destination port check */)
4993                 : 0);
4994         wr32(E1000_FTQF0, is_l4 ?
4995              (0x11 /* UDP */
4996               | (1<<15) /* VF not compared */
4997               | (1<<27) /* Enable Timestamping */
4998               | (7<<28) /* only source port filter enabled,
4999                            source/target address and protocol
5000                            masked */)
5001              : ((1<<15) | (15<<28) /* all mask bits set = filter not
5002                                       enabled */));
5003
5004         wrfl();
5005
5006         adapter->hwtstamp_config = config;
5007
5008         /* clear TX/RX time stamp registers, just to be sure */
5009         regval = rd32(E1000_TXSTMPH);
5010         regval = rd32(E1000_RXSTMPH);
5011
5012         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5013                 -EFAULT : 0;
5014 }
5015
5016 /**
5017  * igb_ioctl -
5018  * @netdev:
5019  * @ifreq:
5020  * @cmd:
5021  **/
5022 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5023 {
5024         switch (cmd) {
5025         case SIOCGMIIPHY:
5026         case SIOCGMIIREG:
5027         case SIOCSMIIREG:
5028                 return igb_mii_ioctl(netdev, ifr, cmd);
5029         case SIOCSHWTSTAMP:
5030                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5031         default:
5032                 return -EOPNOTSUPP;
5033         }
5034 }
5035
5036 static void igb_vlan_rx_register(struct net_device *netdev,
5037                                  struct vlan_group *grp)
5038 {
5039         struct igb_adapter *adapter = netdev_priv(netdev);
5040         struct e1000_hw *hw = &adapter->hw;
5041         u32 ctrl, rctl;
5042
5043         igb_irq_disable(adapter);
5044         adapter->vlgrp = grp;
5045
5046         if (grp) {
5047                 /* enable VLAN tag insert/strip */
5048                 ctrl = rd32(E1000_CTRL);
5049                 ctrl |= E1000_CTRL_VME;
5050                 wr32(E1000_CTRL, ctrl);
5051
5052                 /* enable VLAN receive filtering */
5053                 rctl = rd32(E1000_RCTL);
5054                 rctl &= ~E1000_RCTL_CFIEN;
5055                 wr32(E1000_RCTL, rctl);
5056                 igb_update_mng_vlan(adapter);
5057         } else {
5058                 /* disable VLAN tag insert/strip */
5059                 ctrl = rd32(E1000_CTRL);
5060                 ctrl &= ~E1000_CTRL_VME;
5061                 wr32(E1000_CTRL, ctrl);
5062
5063                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5064                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5065                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5066                 }
5067         }
5068
5069         igb_rlpml_set(adapter);
5070
5071         if (!test_bit(__IGB_DOWN, &adapter->state))
5072                 igb_irq_enable(adapter);
5073 }
5074
5075 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5076 {
5077         struct igb_adapter *adapter = netdev_priv(netdev);
5078         struct e1000_hw *hw = &adapter->hw;
5079         int pf_id = adapter->vfs_allocated_count;
5080
5081         if ((hw->mng_cookie.status &
5082              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5083             (vid == adapter->mng_vlan_id))
5084                 return;
5085
5086         /* add vid to vlvf if sr-iov is enabled,
5087          * if that fails add directly to filter table */
5088         if (igb_vlvf_set(adapter, vid, true, pf_id))
5089                 igb_vfta_set(hw, vid, true);
5090
5091 }
5092
5093 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5094 {
5095         struct igb_adapter *adapter = netdev_priv(netdev);
5096         struct e1000_hw *hw = &adapter->hw;
5097         int pf_id = adapter->vfs_allocated_count;
5098
5099         igb_irq_disable(adapter);
5100         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5101
5102         if (!test_bit(__IGB_DOWN, &adapter->state))
5103                 igb_irq_enable(adapter);
5104
5105         if ((adapter->hw.mng_cookie.status &
5106              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5107             (vid == adapter->mng_vlan_id)) {
5108                 /* release control to f/w */
5109                 igb_release_hw_control(adapter);
5110                 return;
5111         }
5112
5113         /* remove vid from vlvf if sr-iov is enabled,
5114          * if not in vlvf remove from vfta */
5115         if (igb_vlvf_set(adapter, vid, false, pf_id))
5116                 igb_vfta_set(hw, vid, false);
5117 }
5118
5119 static void igb_restore_vlan(struct igb_adapter *adapter)
5120 {
5121         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5122
5123         if (adapter->vlgrp) {
5124                 u16 vid;
5125                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5126                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5127                                 continue;
5128                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5129                 }
5130         }
5131 }
5132
5133 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5134 {
5135         struct e1000_mac_info *mac = &adapter->hw.mac;
5136
5137         mac->autoneg = 0;
5138
5139         /* Fiber NICs only allow 1000 gbps Full duplex */
5140         if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
5141                 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5142                 dev_err(&adapter->pdev->dev,
5143                         "Unsupported Speed/Duplex configuration\n");
5144                 return -EINVAL;
5145         }
5146
5147         switch (spddplx) {
5148         case SPEED_10 + DUPLEX_HALF:
5149                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5150                 break;
5151         case SPEED_10 + DUPLEX_FULL:
5152                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5153                 break;
5154         case SPEED_100 + DUPLEX_HALF:
5155                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5156                 break;
5157         case SPEED_100 + DUPLEX_FULL:
5158                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5159                 break;
5160         case SPEED_1000 + DUPLEX_FULL:
5161                 mac->autoneg = 1;
5162                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5163                 break;
5164         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5165         default:
5166                 dev_err(&adapter->pdev->dev,
5167                         "Unsupported Speed/Duplex configuration\n");
5168                 return -EINVAL;
5169         }
5170         return 0;
5171 }
5172
5173 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5174 {
5175         struct net_device *netdev = pci_get_drvdata(pdev);
5176         struct igb_adapter *adapter = netdev_priv(netdev);
5177         struct e1000_hw *hw = &adapter->hw;
5178         u32 ctrl, rctl, status;
5179         u32 wufc = adapter->wol;
5180 #ifdef CONFIG_PM
5181         int retval = 0;
5182 #endif
5183
5184         netif_device_detach(netdev);
5185
5186         if (netif_running(netdev))
5187                 igb_close(netdev);
5188
5189         igb_reset_interrupt_capability(adapter);
5190
5191         igb_free_queues(adapter);
5192
5193 #ifdef CONFIG_PM
5194         retval = pci_save_state(pdev);
5195         if (retval)
5196                 return retval;
5197 #endif
5198
5199         status = rd32(E1000_STATUS);
5200         if (status & E1000_STATUS_LU)
5201                 wufc &= ~E1000_WUFC_LNKC;
5202
5203         if (wufc) {
5204                 igb_setup_rctl(adapter);
5205                 igb_set_multi(netdev);
5206
5207                 /* turn on all-multi mode if wake on multicast is enabled */
5208                 if (wufc & E1000_WUFC_MC) {
5209                         rctl = rd32(E1000_RCTL);
5210                         rctl |= E1000_RCTL_MPE;
5211                         wr32(E1000_RCTL, rctl);
5212                 }
5213
5214                 ctrl = rd32(E1000_CTRL);
5215                 /* advertise wake from D3Cold */
5216                 #define E1000_CTRL_ADVD3WUC 0x00100000
5217                 /* phy power management enable */
5218                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5219                 ctrl |= E1000_CTRL_ADVD3WUC;
5220                 wr32(E1000_CTRL, ctrl);
5221
5222                 /* Allow time for pending master requests to run */
5223                 igb_disable_pcie_master(&adapter->hw);
5224
5225                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5226                 wr32(E1000_WUFC, wufc);
5227         } else {
5228                 wr32(E1000_WUC, 0);
5229                 wr32(E1000_WUFC, 0);
5230         }
5231
5232         *enable_wake = wufc || adapter->en_mng_pt;
5233         if (!*enable_wake)
5234                 igb_shutdown_fiber_serdes_link_82575(hw);
5235
5236         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5237          * would have already happened in close and is redundant. */
5238         igb_release_hw_control(adapter);
5239
5240         pci_disable_device(pdev);
5241
5242         return 0;
5243 }
5244
5245 #ifdef CONFIG_PM
5246 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5247 {
5248         int retval;
5249         bool wake;
5250
5251         retval = __igb_shutdown(pdev, &wake);
5252         if (retval)
5253                 return retval;
5254
5255         if (wake) {
5256                 pci_prepare_to_sleep(pdev);
5257         } else {
5258                 pci_wake_from_d3(pdev, false);
5259                 pci_set_power_state(pdev, PCI_D3hot);
5260         }
5261
5262         return 0;
5263 }
5264
5265 static int igb_resume(struct pci_dev *pdev)
5266 {
5267         struct net_device *netdev = pci_get_drvdata(pdev);
5268         struct igb_adapter *adapter = netdev_priv(netdev);
5269         struct e1000_hw *hw = &adapter->hw;
5270         u32 err;
5271
5272         pci_set_power_state(pdev, PCI_D0);
5273         pci_restore_state(pdev);
5274
5275         err = pci_enable_device_mem(pdev);
5276         if (err) {
5277                 dev_err(&pdev->dev,
5278                         "igb: Cannot enable PCI device from suspend\n");
5279                 return err;
5280         }
5281         pci_set_master(pdev);
5282
5283         pci_enable_wake(pdev, PCI_D3hot, 0);
5284         pci_enable_wake(pdev, PCI_D3cold, 0);
5285
5286         igb_set_interrupt_capability(adapter);
5287
5288         if (igb_alloc_queues(adapter)) {
5289                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5290                 return -ENOMEM;
5291         }
5292
5293         /* e1000_power_up_phy(adapter); */
5294
5295         igb_reset(adapter);
5296
5297         /* let the f/w know that the h/w is now under the control of the
5298          * driver. */
5299         igb_get_hw_control(adapter);
5300
5301         wr32(E1000_WUS, ~0);
5302
5303         if (netif_running(netdev)) {
5304                 err = igb_open(netdev);
5305                 if (err)
5306                         return err;
5307         }
5308
5309         netif_device_attach(netdev);
5310
5311         return 0;
5312 }
5313 #endif
5314
5315 static void igb_shutdown(struct pci_dev *pdev)
5316 {
5317         bool wake;
5318
5319         __igb_shutdown(pdev, &wake);
5320
5321         if (system_state == SYSTEM_POWER_OFF) {
5322                 pci_wake_from_d3(pdev, wake);
5323                 pci_set_power_state(pdev, PCI_D3hot);
5324         }
5325 }
5326
5327 #ifdef CONFIG_NET_POLL_CONTROLLER
5328 /*
5329  * Polling 'interrupt' - used by things like netconsole to send skbs
5330  * without having to re-enable interrupts. It's not called while
5331  * the interrupt routine is executing.
5332  */
5333 static void igb_netpoll(struct net_device *netdev)
5334 {
5335         struct igb_adapter *adapter = netdev_priv(netdev);
5336         struct e1000_hw *hw = &adapter->hw;
5337         int i;
5338
5339         if (!adapter->msix_entries) {
5340                 igb_irq_disable(adapter);
5341                 napi_schedule(&adapter->rx_ring[0].napi);
5342                 return;
5343         }
5344
5345         for (i = 0; i < adapter->num_tx_queues; i++) {
5346                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5347                 wr32(E1000_EIMC, tx_ring->eims_value);
5348                 igb_clean_tx_irq(tx_ring);
5349                 wr32(E1000_EIMS, tx_ring->eims_value);
5350         }
5351
5352         for (i = 0; i < adapter->num_rx_queues; i++) {
5353                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5354                 wr32(E1000_EIMC, rx_ring->eims_value);
5355                 napi_schedule(&rx_ring->napi);
5356         }
5357 }
5358 #endif /* CONFIG_NET_POLL_CONTROLLER */
5359
5360 /**
5361  * igb_io_error_detected - called when PCI error is detected
5362  * @pdev: Pointer to PCI device
5363  * @state: The current pci connection state
5364  *
5365  * This function is called after a PCI bus error affecting
5366  * this device has been detected.
5367  */
5368 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5369                                               pci_channel_state_t state)
5370 {
5371         struct net_device *netdev = pci_get_drvdata(pdev);
5372         struct igb_adapter *adapter = netdev_priv(netdev);
5373
5374         netif_device_detach(netdev);
5375
5376         if (state == pci_channel_io_perm_failure)
5377                 return PCI_ERS_RESULT_DISCONNECT;
5378
5379         if (netif_running(netdev))
5380                 igb_down(adapter);
5381         pci_disable_device(pdev);
5382
5383         /* Request a slot slot reset. */
5384         return PCI_ERS_RESULT_NEED_RESET;
5385 }
5386
5387 /**
5388  * igb_io_slot_reset - called after the pci bus has been reset.
5389  * @pdev: Pointer to PCI device
5390  *
5391  * Restart the card from scratch, as if from a cold-boot. Implementation
5392  * resembles the first-half of the igb_resume routine.
5393  */
5394 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5395 {
5396         struct net_device *netdev = pci_get_drvdata(pdev);
5397         struct igb_adapter *adapter = netdev_priv(netdev);
5398         struct e1000_hw *hw = &adapter->hw;
5399         pci_ers_result_t result;
5400         int err;
5401
5402         if (pci_enable_device_mem(pdev)) {
5403                 dev_err(&pdev->dev,
5404                         "Cannot re-enable PCI device after reset.\n");
5405                 result = PCI_ERS_RESULT_DISCONNECT;
5406         } else {
5407                 pci_set_master(pdev);
5408                 pci_restore_state(pdev);
5409
5410                 pci_enable_wake(pdev, PCI_D3hot, 0);
5411                 pci_enable_wake(pdev, PCI_D3cold, 0);
5412
5413                 igb_reset(adapter);
5414                 wr32(E1000_WUS, ~0);
5415                 result = PCI_ERS_RESULT_RECOVERED;
5416         }
5417
5418         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5419         if (err) {
5420                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5421                         "failed 0x%0x\n", err);
5422                 /* non-fatal, continue */
5423         }
5424
5425         return result;
5426 }
5427
5428 /**
5429  * igb_io_resume - called when traffic can start flowing again.
5430  * @pdev: Pointer to PCI device
5431  *
5432  * This callback is called when the error recovery driver tells us that
5433  * its OK to resume normal operation. Implementation resembles the
5434  * second-half of the igb_resume routine.
5435  */
5436 static void igb_io_resume(struct pci_dev *pdev)
5437 {
5438         struct net_device *netdev = pci_get_drvdata(pdev);
5439         struct igb_adapter *adapter = netdev_priv(netdev);
5440
5441         if (netif_running(netdev)) {
5442                 if (igb_up(adapter)) {
5443                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5444                         return;
5445                 }
5446         }
5447
5448         netif_device_attach(netdev);
5449
5450         /* let the f/w know that the h/w is now under the control of the
5451          * driver. */
5452         igb_get_hw_control(adapter);
5453 }
5454
5455 static void igb_set_mc_list_pools(struct igb_adapter *adapter,
5456                                   int entry_count, u16 total_rar_filters)
5457 {
5458         struct e1000_hw *hw = &adapter->hw;
5459         int i = adapter->vfs_allocated_count + 1;
5460
5461         if ((i + entry_count) < total_rar_filters)
5462                 total_rar_filters = i + entry_count;
5463
5464         for (; i < total_rar_filters; i++)
5465                 igb_set_rah_pool(hw, adapter->vfs_allocated_count, i);
5466 }
5467
5468 static int igb_set_vf_mac(struct igb_adapter *adapter,
5469                           int vf, unsigned char *mac_addr)
5470 {
5471         struct e1000_hw *hw = &adapter->hw;
5472         int rar_entry = vf + 1; /* VF MAC addresses start at entry 1 */
5473
5474         igb_rar_set(hw, mac_addr, rar_entry);
5475
5476         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5477
5478         igb_set_rah_pool(hw, vf, rar_entry);
5479
5480         return 0;
5481 }
5482
5483 static void igb_vmm_control(struct igb_adapter *adapter)
5484 {
5485         struct e1000_hw *hw = &adapter->hw;
5486         u32 reg_data;
5487
5488         if (!adapter->vfs_allocated_count)
5489                 return;
5490
5491         /* VF's need PF reset indication before they
5492          * can send/receive mail */
5493         reg_data = rd32(E1000_CTRL_EXT);
5494         reg_data |= E1000_CTRL_EXT_PFRSTD;
5495         wr32(E1000_CTRL_EXT, reg_data);
5496
5497         igb_vmdq_set_loopback_pf(hw, true);
5498         igb_vmdq_set_replication_pf(hw, true);
5499 }
5500
5501 /* igb_main.c */