drivers/net/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/module.h>
  29 #include <linux/types.h>
  30 #include <linux/init.h>
  31 #include <linux/vmalloc.h>
  32 #include <linux/pagemap.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ipv6.h>
  35 #include <net/checksum.h>
  36 #include <net/ip6_checksum.h>
  37 #include <linux/net_tstamp.h>
  38 #include <linux/mii.h>
  39 #include <linux/ethtool.h>
  40 #include <linux/if_vlan.h>
  41 #include <linux/pci.h>
  42 #include <linux/pci-aspm.h>
  43 #include <linux/delay.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/if_ether.h>
  46 #include <linux/aer.h>
  47 #ifdef CONFIG_IGB_DCA
  48 #include <linux/dca.h>
  49 #endif
  50 #include "igb.h"
  51
  52 #define DRV_VERSION "1.3.16-k2"
  53 char igb_driver_name[] = "igb";
  54 char igb_driver_version[] = DRV_VERSION;
  55 static const char igb_driver_string[] =
  56                                 "Intel(R) Gigabit Ethernet Network Driver";
  57 static const char igb_copyright[] = "Copyright (c) 2007-2009 Intel Corporation.";
  58
  59 static const struct e1000_info *igb_info_tbl[] = {
  60         [board_82575] = &e1000_82575_info,
  61 };
  62
  63 static struct pci_device_id igb_pci_tbl[] = {
  64         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  65         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  66         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  67         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  68         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
  72         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
  73         /* required last entry */
  74         {0, }
  75 };
  76
  77 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
  78
  79 void igb_reset(struct igb_adapter *);
  80 static int igb_setup_all_tx_resources(struct igb_adapter *);
  81 static int igb_setup_all_rx_resources(struct igb_adapter *);
  82 static void igb_free_all_tx_resources(struct igb_adapter *);
  83 static void igb_free_all_rx_resources(struct igb_adapter *);
  84 void igb_update_stats(struct igb_adapter *);
  85 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
  86 static void __devexit igb_remove(struct pci_dev *pdev);
  87 static int igb_sw_init(struct igb_adapter *);
  88 static int igb_open(struct net_device *);
  89 static int igb_close(struct net_device *);
  90 static void igb_configure_tx(struct igb_adapter *);
  91 static void igb_configure_rx(struct igb_adapter *);
  92 static void igb_setup_rctl(struct igb_adapter *);
  93 static void igb_clean_all_tx_rings(struct igb_adapter *);
  94 static void igb_clean_all_rx_rings(struct igb_adapter *);
  95 static void igb_clean_tx_ring(struct igb_ring *);
  96 static void igb_clean_rx_ring(struct igb_ring *);
  97 static void igb_set_rx_mode(struct net_device *);
  98 static void igb_update_phy_info(unsigned long);
  99 static void igb_watchdog(unsigned long);
 100 static void igb_watchdog_task(struct work_struct *);
 101 static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *,
 102                                            struct net_device *,
 103                                            struct igb_ring *);
 104 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
 105                                       struct net_device *);
 106 static struct net_device_stats *igb_get_stats(struct net_device *);
 107 static int igb_change_mtu(struct net_device *, int);
 108 static int igb_set_mac(struct net_device *, void *);
 109 static irqreturn_t igb_intr(int irq, void *);
 110 static irqreturn_t igb_intr_msi(int irq, void *);
 111 static irqreturn_t igb_msix_other(int irq, void *);
 112 static irqreturn_t igb_msix_rx(int irq, void *);
 113 static irqreturn_t igb_msix_tx(int irq, void *);
 114 #ifdef CONFIG_IGB_DCA
 115 static void igb_update_rx_dca(struct igb_ring *);
 116 static void igb_update_tx_dca(struct igb_ring *);
 117 static void igb_setup_dca(struct igb_adapter *);
 118 #endif /* CONFIG_IGB_DCA */
 119 static bool igb_clean_tx_irq(struct igb_ring *);
 120 static int igb_poll(struct napi_struct *, int);
 121 static bool igb_clean_rx_irq_adv(struct igb_ring *, int *, int);
 122 static void igb_alloc_rx_buffers_adv(struct igb_ring *, int);
 123 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 124 static void igb_tx_timeout(struct net_device *);
 125 static void igb_reset_task(struct work_struct *);
 126 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
 127 static void igb_vlan_rx_add_vid(struct net_device *, u16);
 128 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
 129 static void igb_restore_vlan(struct igb_adapter *);
 130 static void igb_ping_all_vfs(struct igb_adapter *);
 131 static void igb_msg_task(struct igb_adapter *);
 132 static int igb_rcv_msg_from_vf(struct igb_adapter *, u32);
 133 static inline void igb_set_rah_pool(struct e1000_hw *, int , int);
 134 static void igb_vmm_control(struct igb_adapter *);
 135 static int igb_set_vf_mac(struct igb_adapter *adapter, int, unsigned char *);
 136 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 137
 138 static inline void igb_set_vmolr(struct e1000_hw *hw, int vfn)
 139 {
 140         u32 reg_data;
 141
 142         reg_data = rd32(E1000_VMOLR(vfn));
 143         reg_data |= E1000_VMOLR_BAM |    /* Accept broadcast */
 144                     E1000_VMOLR_ROPE |   /* Accept packets matched in UTA */
 145                     E1000_VMOLR_ROMPE |  /* Accept packets matched in MTA */
 146                     E1000_VMOLR_AUPE |   /* Accept untagged packets */
 147                     E1000_VMOLR_STRVLAN; /* Strip vlan tags */
 148         wr32(E1000_VMOLR(vfn), reg_data);
 149 }
 150
 151 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
 152                                  int vfn)
 153 {
 154         struct e1000_hw *hw = &adapter->hw;
 155         u32 vmolr;
 156
 157         /* if it isn't the PF check to see if VFs are enabled and
 158          * increase the size to support vlan tags */
 159         if (vfn < adapter->vfs_allocated_count &&
 160             adapter->vf_data[vfn].vlans_enabled)
 161                 size += VLAN_TAG_SIZE;
 162
 163         vmolr = rd32(E1000_VMOLR(vfn));
 164         vmolr &= ~E1000_VMOLR_RLPML_MASK;
 165         vmolr |= size | E1000_VMOLR_LPE;
 166         wr32(E1000_VMOLR(vfn), vmolr);
 167
 168         return 0;
 169 }
 170
 171 static inline void igb_set_rah_pool(struct e1000_hw *hw, int pool, int entry)
 172 {
 173         u32 reg_data;
 174
 175         reg_data = rd32(E1000_RAH(entry));
 176         reg_data &= ~E1000_RAH_POOL_MASK;
 177         reg_data |= E1000_RAH_POOL_1 << pool;;
 178         wr32(E1000_RAH(entry), reg_data);
 179 }
 180
 181 #ifdef CONFIG_PM
 182 static int igb_suspend(struct pci_dev *, pm_message_t);
 183 static int igb_resume(struct pci_dev *);
 184 #endif
 185 static void igb_shutdown(struct pci_dev *);
 186 #ifdef CONFIG_IGB_DCA
 187 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 188 static struct notifier_block dca_notifier = {
 189         .notifier_call  = igb_notify_dca,
 190         .next           = NULL,
 191         .priority       = 0
 192 };
 193 #endif
 194 #ifdef CONFIG_NET_POLL_CONTROLLER
 195 /* for netdump / net console */
 196 static void igb_netpoll(struct net_device *);
 197 #endif
 198 #ifdef CONFIG_PCI_IOV
 199 static unsigned int max_vfs = 0;
 200 module_param(max_vfs, uint, 0);
 201 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 202                  "per physical function");
 203 #endif /* CONFIG_PCI_IOV */
 204
 205 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 206                      pci_channel_state_t);
 207 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 208 static void igb_io_resume(struct pci_dev *);
 209
 210 static struct pci_error_handlers igb_err_handler = {
 211         .error_detected = igb_io_error_detected,
 212         .slot_reset = igb_io_slot_reset,
 213         .resume = igb_io_resume,
 214 };
 215
 216
 217 static struct pci_driver igb_driver = {
 218         .name     = igb_driver_name,
 219         .id_table = igb_pci_tbl,
 220         .probe    = igb_probe,
 221         .remove   = __devexit_p(igb_remove),
 222 #ifdef CONFIG_PM
 223         /* Power Managment Hooks */
 224         .suspend  = igb_suspend,
 225         .resume   = igb_resume,
 226 #endif
 227         .shutdown = igb_shutdown,
 228         .err_handler = &igb_err_handler
 229 };
 230
 231 static int global_quad_port_a; /* global quad port a indication */
 232
 233 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 234 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 235 MODULE_LICENSE("GPL");
 236 MODULE_VERSION(DRV_VERSION);
 237
 238 /**
 239  * Scale the NIC clock cycle by a large factor so that
 240  * relatively small clock corrections can be added or
 241  * substracted at each clock tick. The drawbacks of a
 242  * large factor are a) that the clock register overflows
 243  * more quickly (not such a big deal) and b) that the
 244  * increment per tick has to fit into 24 bits.
 245  *
 246  * Note that
 247  *   TIMINCA = IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS *
 248  *             IGB_TSYNC_SCALE
 249  *   TIMINCA += TIMINCA * adjustment [ppm] / 1e9
 250  *
 251  * The base scale factor is intentionally a power of two
 252  * so that the division in %struct timecounter can be done with
 253  * a shift.
 254  */
 255 #define IGB_TSYNC_SHIFT (19)
 256 #define IGB_TSYNC_SCALE (1<<IGB_TSYNC_SHIFT)
 257
 258 /**
 259  * The duration of one clock cycle of the NIC.
 260  *
 261  * @todo This hard-coded value is part of the specification and might change
 262  * in future hardware revisions. Add revision check.
 263  */
 264 #define IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS 16
 265
 266 #if (IGB_TSYNC_SCALE * IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS) >= (1<<24)
 267 # error IGB_TSYNC_SCALE and/or IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS are too large to fit into TIMINCA
 268 #endif
 269
 270 /**
 271  * igb_read_clock - read raw cycle counter (to be used by time counter)
 272  */
 273 static cycle_t igb_read_clock(const struct cyclecounter *tc)
 274 {
 275         struct igb_adapter *adapter =
 276                 container_of(tc, struct igb_adapter, cycles);
 277         struct e1000_hw *hw = &adapter->hw;
 278         u64 stamp;
 279
 280         stamp =  rd32(E1000_SYSTIML);
 281         stamp |= (u64)rd32(E1000_SYSTIMH) << 32ULL;
 282
 283         return stamp;
 284 }
 285
 286 #ifdef DEBUG
 287 /**
 288  * igb_get_hw_dev_name - return device name string
 289  * used by hardware layer to print debugging information
 290  **/
 291 char *igb_get_hw_dev_name(struct e1000_hw *hw)
 292 {
 293         struct igb_adapter *adapter = hw->back;
 294         return adapter->netdev->name;
 295 }
 296
 297 /**
 298  * igb_get_time_str - format current NIC and system time as string
 299  */
 300 static char *igb_get_time_str(struct igb_adapter *adapter,
 301                               char buffer[160])
 302 {
 303         cycle_t hw = adapter->cycles.read(&adapter->cycles);
 304         struct timespec nic = ns_to_timespec(timecounter_read(&adapter->clock));
 305         struct timespec sys;
 306         struct timespec delta;
 307         getnstimeofday(&sys);
 308
 309         delta = timespec_sub(nic, sys);
 310
 311         sprintf(buffer,
 312                 "HW %llu, NIC %ld.%09lus, SYS %ld.%09lus, NIC-SYS %lds + %09luns",
 313                 hw,
 314                 (long)nic.tv_sec, nic.tv_nsec,
 315                 (long)sys.tv_sec, sys.tv_nsec,
 316                 (long)delta.tv_sec, delta.tv_nsec);
 317
 318         return buffer;
 319 }
 320 #endif
 321
 322 /**
 323  * igb_desc_unused - calculate if we have unused descriptors
 324  **/
 325 static int igb_desc_unused(struct igb_ring *ring)
 326 {
 327         if (ring->next_to_clean > ring->next_to_use)
 328                 return ring->next_to_clean - ring->next_to_use - 1;
 329
 330         return ring->count + ring->next_to_clean - ring->next_to_use - 1;
 331 }
 332
 333 /**
 334  * igb_init_module - Driver Registration Routine
 335  *
 336  * igb_init_module is the first routine called when the driver is
 337  * loaded. All it does is register with the PCI subsystem.
 338  **/
 339 static int __init igb_init_module(void)
 340 {
 341         int ret;
 342         printk(KERN_INFO "%s - version %s\n",
 343                igb_driver_string, igb_driver_version);
 344
 345         printk(KERN_INFO "%s\n", igb_copyright);
 346
 347         global_quad_port_a = 0;
 348
 349 #ifdef CONFIG_IGB_DCA
 350         dca_register_notify(&dca_notifier);
 351 #endif
 352
 353         ret = pci_register_driver(&igb_driver);
 354         return ret;
 355 }
 356
 357 module_init(igb_init_module);
 358
 359 /**
 360  * igb_exit_module - Driver Exit Cleanup Routine
 361  *
 362  * igb_exit_module is called just before the driver is removed
 363  * from memory.
 364  **/
 365 static void __exit igb_exit_module(void)
 366 {
 367 #ifdef CONFIG_IGB_DCA
 368         dca_unregister_notify(&dca_notifier);
 369 #endif
 370         pci_unregister_driver(&igb_driver);
 371 }
 372
 373 module_exit(igb_exit_module);
 374
 375 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 376 /**
 377  * igb_cache_ring_register - Descriptor ring to register mapping
 378  * @adapter: board private structure to initialize
 379  *
 380  * Once we know the feature-set enabled for the device, we'll cache
 381  * the register offset the descriptor ring is assigned to.
 382  **/
 383 static void igb_cache_ring_register(struct igb_adapter *adapter)
 384 {
 385         int i;
 386         unsigned int rbase_offset = adapter->vfs_allocated_count;
 387
 388         switch (adapter->hw.mac.type) {
 389         case e1000_82576:
 390                 /* The queues are allocated for virtualization such that VF 0
 391                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 392                  * In order to avoid collision we start at the first free queue
 393                  * and continue consuming queues in the same sequence
 394                  */
 395                 for (i = 0; i < adapter->num_rx_queues; i++)
 396                         adapter->rx_ring[i].reg_idx = rbase_offset +
 397                                                       Q_IDX_82576(i);
 398                 for (i = 0; i < adapter->num_tx_queues; i++)
 399                         adapter->tx_ring[i].reg_idx = rbase_offset +
 400                                                       Q_IDX_82576(i);
 401                 break;
 402         case e1000_82575:
 403         default:
 404                 for (i = 0; i < adapter->num_rx_queues; i++)
 405                         adapter->rx_ring[i].reg_idx = i;
 406                 for (i = 0; i < adapter->num_tx_queues; i++)
 407                         adapter->tx_ring[i].reg_idx = i;
 408                 break;
 409         }
 410 }
 411
 412 /**
 413  * igb_alloc_queues - Allocate memory for all rings
 414  * @adapter: board private structure to initialize
 415  *
 416  * We allocate one ring per queue at run-time since we don't know the
 417  * number of queues at compile-time.
 418  **/
 419 static int igb_alloc_queues(struct igb_adapter *adapter)
 420 {
 421         int i;
 422
 423         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
 424                                    sizeof(struct igb_ring), GFP_KERNEL);
 425         if (!adapter->tx_ring)
 426                 return -ENOMEM;
 427
 428         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
 429                                    sizeof(struct igb_ring), GFP_KERNEL);
 430         if (!adapter->rx_ring) {
 431                 kfree(adapter->tx_ring);
 432                 return -ENOMEM;
 433         }
 434
 435         adapter->rx_ring->buddy = adapter->tx_ring;
 436
 437         for (i = 0; i < adapter->num_tx_queues; i++) {
 438                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 439                 ring->count = adapter->tx_ring_count;
 440                 ring->adapter = adapter;
 441                 ring->queue_index = i;
 442         }
 443         for (i = 0; i < adapter->num_rx_queues; i++) {
 444                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 445                 ring->count = adapter->rx_ring_count;
 446                 ring->adapter = adapter;
 447                 ring->queue_index = i;
 448                 ring->itr_register = E1000_ITR;
 449
 450                 /* set a default napi handler for each rx_ring */
 451                 netif_napi_add(adapter->netdev, &ring->napi, igb_poll, 64);
 452         }
 453
 454         igb_cache_ring_register(adapter);
 455         return 0;
 456 }
 457
 458 static void igb_free_queues(struct igb_adapter *adapter)
 459 {
 460         int i;
 461
 462         for (i = 0; i < adapter->num_rx_queues; i++)
 463                 netif_napi_del(&adapter->rx_ring[i].napi);
 464
 465         adapter->num_rx_queues = 0;
 466         adapter->num_tx_queues = 0;
 467
 468         kfree(adapter->tx_ring);
 469         kfree(adapter->rx_ring);
 470 }
 471
 472 #define IGB_N0_QUEUE -1
 473 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
 474                               int tx_queue, int msix_vector)
 475 {
 476         u32 msixbm = 0;
 477         struct e1000_hw *hw = &adapter->hw;
 478         u32 ivar, index;
 479
 480         switch (hw->mac.type) {
 481         case e1000_82575:
 482                 /* The 82575 assigns vectors using a bitmask, which matches the
 483                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 484                    or more queues to a vector, we write the appropriate bits
 485                    into the MSIXBM register for that vector. */
 486                 if (rx_queue > IGB_N0_QUEUE) {
 487                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 488                         adapter->rx_ring[rx_queue].eims_value = msixbm;
 489                 }
 490                 if (tx_queue > IGB_N0_QUEUE) {
 491                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 492                         adapter->tx_ring[tx_queue].eims_value =
 493                                   E1000_EICR_TX_QUEUE0 << tx_queue;
 494                 }
 495                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 496                 break;
 497         case e1000_82576:
 498                 /* 82576 uses a table-based method for assigning vectors.
 499                    Each queue has a single entry in the table to which we write
 500                    a vector number along with a "valid" bit.  Sadly, the layout
 501                    of the table is somewhat counterintuitive. */
 502                 if (rx_queue > IGB_N0_QUEUE) {
 503                         index = (rx_queue >> 1) + adapter->vfs_allocated_count;
 504                         ivar = array_rd32(E1000_IVAR0, index);
 505                         if (rx_queue & 0x1) {
 506                                 /* vector goes into third byte of register */
 507                                 ivar = ivar & 0xFF00FFFF;
 508                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 16;
 509                         } else {
 510                                 /* vector goes into low byte of register */
 511                                 ivar = ivar & 0xFFFFFF00;
 512                                 ivar |= msix_vector | E1000_IVAR_VALID;
 513                         }
 514                         adapter->rx_ring[rx_queue].eims_value= 1 << msix_vector;
 515                         array_wr32(E1000_IVAR0, index, ivar);
 516                 }
 517                 if (tx_queue > IGB_N0_QUEUE) {
 518                         index = (tx_queue >> 1) + adapter->vfs_allocated_count;
 519                         ivar = array_rd32(E1000_IVAR0, index);
 520                         if (tx_queue & 0x1) {
 521                                 /* vector goes into high byte of register */
 522                                 ivar = ivar & 0x00FFFFFF;
 523                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 24;
 524                         } else {
 525                                 /* vector goes into second byte of register */
 526                                 ivar = ivar & 0xFFFF00FF;
 527                                 ivar |= (msix_vector | E1000_IVAR_VALID) << 8;
 528                         }
 529                         adapter->tx_ring[tx_queue].eims_value= 1 << msix_vector;
 530                         array_wr32(E1000_IVAR0, index, ivar);
 531                 }
 532                 break;
 533         default:
 534                 BUG();
 535                 break;
 536         }
 537 }
 538
 539 /**
 540  * igb_configure_msix - Configure MSI-X hardware
 541  *
 542  * igb_configure_msix sets up the hardware to properly
 543  * generate MSI-X interrupts.
 544  **/
 545 static void igb_configure_msix(struct igb_adapter *adapter)
 546 {
 547         u32 tmp;
 548         int i, vector = 0;
 549         struct e1000_hw *hw = &adapter->hw;
 550
 551         adapter->eims_enable_mask = 0;
 552         if (hw->mac.type == e1000_82576)
 553                 /* Turn on MSI-X capability first, or our settings
 554                  * won't stick.  And it will take days to debug. */
 555                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 556                                    E1000_GPIE_PBA | E1000_GPIE_EIAME |
 557                                    E1000_GPIE_NSICR);
 558
 559         for (i = 0; i < adapter->num_tx_queues; i++) {
 560                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
 561                 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
 562                 adapter->eims_enable_mask |= tx_ring->eims_value;
 563                 if (tx_ring->itr_val)
 564                         writel(tx_ring->itr_val,
 565                                hw->hw_addr + tx_ring->itr_register);
 566                 else
 567                         writel(1, hw->hw_addr + tx_ring->itr_register);
 568         }
 569
 570         for (i = 0; i < adapter->num_rx_queues; i++) {
 571                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
 572                 rx_ring->buddy = NULL;
 573                 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
 574                 adapter->eims_enable_mask |= rx_ring->eims_value;
 575                 if (rx_ring->itr_val)
 576                         writel(rx_ring->itr_val,
 577                                hw->hw_addr + rx_ring->itr_register);
 578                 else
 579                         writel(1, hw->hw_addr + rx_ring->itr_register);
 580         }
 581
 582
 583         /* set vector for other causes, i.e. link changes */
 584         switch (hw->mac.type) {
 585         case e1000_82575:
 586                 array_wr32(E1000_MSIXBM(0), vector++,
 587                                       E1000_EIMS_OTHER);
 588
 589                 tmp = rd32(E1000_CTRL_EXT);
 590                 /* enable MSI-X PBA support*/
 591                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 592
 593                 /* Auto-Mask interrupts upon ICR read. */
 594                 tmp |= E1000_CTRL_EXT_EIAME;
 595                 tmp |= E1000_CTRL_EXT_IRCA;
 596
 597                 wr32(E1000_CTRL_EXT, tmp);
 598                 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
 599                 adapter->eims_other = E1000_EIMS_OTHER;
 600
 601                 break;
 602
 603         case e1000_82576:
 604                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 605                 wr32(E1000_IVAR_MISC, tmp);
 606
 607                 adapter->eims_enable_mask = (1 << (vector)) - 1;
 608                 adapter->eims_other = 1 << (vector - 1);
 609                 break;
 610         default:
 611                 /* do nothing, since nothing else supports MSI-X */
 612                 break;
 613         } /* switch (hw->mac.type) */
 614         wrfl();
 615 }
 616
 617 /**
 618  * igb_request_msix - Initialize MSI-X interrupts
 619  *
 620  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 621  * kernel.
 622  **/
 623 static int igb_request_msix(struct igb_adapter *adapter)
 624 {
 625         struct net_device *netdev = adapter->netdev;
 626         int i, err = 0, vector = 0;
 627
 628         vector = 0;
 629
 630         for (i = 0; i < adapter->num_tx_queues; i++) {
 631                 struct igb_ring *ring = &(adapter->tx_ring[i]);
 632                 sprintf(ring->name, "%s-tx-%d", netdev->name, i);
 633                 err = request_irq(adapter->msix_entries[vector].vector,
 634                                   &igb_msix_tx, 0, ring->name,
 635                                   &(adapter->tx_ring[i]));
 636                 if (err)
 637                         goto out;
 638                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 639                 ring->itr_val = 976; /* ~4000 ints/sec */
 640                 vector++;
 641         }
 642         for (i = 0; i < adapter->num_rx_queues; i++) {
 643                 struct igb_ring *ring = &(adapter->rx_ring[i]);
 644                 if (strlen(netdev->name) < (IFNAMSIZ - 5))
 645                         sprintf(ring->name, "%s-rx-%d", netdev->name, i);
 646                 else
 647                         memcpy(ring->name, netdev->name, IFNAMSIZ);
 648                 err = request_irq(adapter->msix_entries[vector].vector,
 649                                   &igb_msix_rx, 0, ring->name,
 650                                   &(adapter->rx_ring[i]));
 651                 if (err)
 652                         goto out;
 653                 ring->itr_register = E1000_EITR(0) + (vector << 2);
 654                 ring->itr_val = adapter->itr;
 655                 vector++;
 656         }
 657
 658         err = request_irq(adapter->msix_entries[vector].vector,
 659                           &igb_msix_other, 0, netdev->name, netdev);
 660         if (err)
 661                 goto out;
 662
 663         igb_configure_msix(adapter);
 664         return 0;
 665 out:
 666         return err;
 667 }
 668
 669 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 670 {
 671         if (adapter->msix_entries) {
 672                 pci_disable_msix(adapter->pdev);
 673                 kfree(adapter->msix_entries);
 674                 adapter->msix_entries = NULL;
 675         } else if (adapter->flags & IGB_FLAG_HAS_MSI)
 676                 pci_disable_msi(adapter->pdev);
 677         return;
 678 }
 679
 680
 681 /**
 682  * igb_set_interrupt_capability - set MSI or MSI-X if supported
 683  *
 684  * Attempt to configure interrupts using the best available
 685  * capabilities of the hardware and kernel.
 686  **/
 687 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
 688 {
 689         int err;
 690         int numvecs, i;
 691
 692         /* Number of supported queues. */
 693         /* Having more queues than CPUs doesn't make sense. */
 694         adapter->num_rx_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
 695         adapter->num_tx_queues = min_t(u32, IGB_MAX_TX_QUEUES, num_online_cpus());
 696
 697         numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
 698         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
 699                                         GFP_KERNEL);
 700         if (!adapter->msix_entries)
 701                 goto msi_only;
 702
 703         for (i = 0; i < numvecs; i++)
 704                 adapter->msix_entries[i].entry = i;
 705
 706         err = pci_enable_msix(adapter->pdev,
 707                               adapter->msix_entries,
 708                               numvecs);
 709         if (err == 0)
 710                 goto out;
 711
 712         igb_reset_interrupt_capability(adapter);
 713
 714         /* If we can't do MSI-X, try MSI */
 715 msi_only:
 716 #ifdef CONFIG_PCI_IOV
 717         /* disable SR-IOV for non MSI-X configurations */
 718         if (adapter->vf_data) {
 719                 struct e1000_hw *hw = &adapter->hw;
 720                 /* disable iov and allow time for transactions to clear */
 721                 pci_disable_sriov(adapter->pdev);
 722                 msleep(500);
 723
 724                 kfree(adapter->vf_data);
 725                 adapter->vf_data = NULL;
 726                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
 727                 msleep(100);
 728                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
 729         }
 730 #endif
 731         adapter->num_rx_queues = 1;
 732         adapter->num_tx_queues = 1;
 733         if (!pci_enable_msi(adapter->pdev))
 734                 adapter->flags |= IGB_FLAG_HAS_MSI;
 735 out:
 736         /* Notify the stack of the (possibly) reduced Tx Queue count. */
 737         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
 738         return;
 739 }
 740
 741 /**
 742  * igb_request_irq - initialize interrupts
 743  *
 744  * Attempts to configure interrupts using the best available
 745  * capabilities of the hardware and kernel.
 746  **/
 747 static int igb_request_irq(struct igb_adapter *adapter)
 748 {
 749         struct net_device *netdev = adapter->netdev;
 750         struct e1000_hw *hw = &adapter->hw;
 751         int err = 0;
 752
 753         if (adapter->msix_entries) {
 754                 err = igb_request_msix(adapter);
 755                 if (!err)
 756                         goto request_done;
 757                 /* fall back to MSI */
 758                 igb_reset_interrupt_capability(adapter);
 759                 if (!pci_enable_msi(adapter->pdev))
 760                         adapter->flags |= IGB_FLAG_HAS_MSI;
 761                 igb_free_all_tx_resources(adapter);
 762                 igb_free_all_rx_resources(adapter);
 763                 adapter->num_rx_queues = 1;
 764                 igb_alloc_queues(adapter);
 765         } else {
 766                 switch (hw->mac.type) {
 767                 case e1000_82575:
 768                         wr32(E1000_MSIXBM(0),
 769                              (E1000_EICR_RX_QUEUE0 | E1000_EIMS_OTHER));
 770                         break;
 771                 case e1000_82576:
 772                         wr32(E1000_IVAR0, E1000_IVAR_VALID);
 773                         break;
 774                 default:
 775                         break;
 776                 }
 777         }
 778
 779         if (adapter->flags & IGB_FLAG_HAS_MSI) {
 780                 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
 781                                   netdev->name, netdev);
 782                 if (!err)
 783                         goto request_done;
 784                 /* fall back to legacy interrupts */
 785                 igb_reset_interrupt_capability(adapter);
 786                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
 787         }
 788
 789         err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
 790                           netdev->name, netdev);
 791
 792         if (err)
 793                 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
 794                         err);
 795
 796 request_done:
 797         return err;
 798 }
 799
 800 static void igb_free_irq(struct igb_adapter *adapter)
 801 {
 802         struct net_device *netdev = adapter->netdev;
 803
 804         if (adapter->msix_entries) {
 805                 int vector = 0, i;
 806
 807                 for (i = 0; i < adapter->num_tx_queues; i++)
 808                         free_irq(adapter->msix_entries[vector++].vector,
 809                                 &(adapter->tx_ring[i]));
 810                 for (i = 0; i < adapter->num_rx_queues; i++)
 811                         free_irq(adapter->msix_entries[vector++].vector,
 812                                 &(adapter->rx_ring[i]));
 813
 814                 free_irq(adapter->msix_entries[vector++].vector, netdev);
 815                 return;
 816         }
 817
 818         free_irq(adapter->pdev->irq, netdev);
 819 }
 820
 821 /**
 822  * igb_irq_disable - Mask off interrupt generation on the NIC
 823  * @adapter: board private structure
 824  **/
 825 static void igb_irq_disable(struct igb_adapter *adapter)
 826 {
 827         struct e1000_hw *hw = &adapter->hw;
 828
 829         if (adapter->msix_entries) {
 830                 u32 regval = rd32(E1000_EIAM);
 831                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
 832                 wr32(E1000_EIMC, adapter->eims_enable_mask);
 833                 regval = rd32(E1000_EIAC);
 834                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
 835         }
 836
 837         wr32(E1000_IAM, 0);
 838         wr32(E1000_IMC, ~0);
 839         wrfl();
 840         synchronize_irq(adapter->pdev->irq);
 841 }
 842
 843 /**
 844  * igb_irq_enable - Enable default interrupt generation settings
 845  * @adapter: board private structure
 846  **/
 847 static void igb_irq_enable(struct igb_adapter *adapter)
 848 {
 849         struct e1000_hw *hw = &adapter->hw;
 850
 851         if (adapter->msix_entries) {
 852                 u32 regval = rd32(E1000_EIAC);
 853                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
 854                 regval = rd32(E1000_EIAM);
 855                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
 856                 wr32(E1000_EIMS, adapter->eims_enable_mask);
 857                 if (adapter->vfs_allocated_count)
 858                         wr32(E1000_MBVFIMR, 0xFF);
 859                 wr32(E1000_IMS, (E1000_IMS_LSC | E1000_IMS_VMMB |
 860                                  E1000_IMS_DOUTSYNC));
 861         } else {
 862                 wr32(E1000_IMS, IMS_ENABLE_MASK);
 863                 wr32(E1000_IAM, IMS_ENABLE_MASK);
 864         }
 865 }
 866
 867 static void igb_update_mng_vlan(struct igb_adapter *adapter)
 868 {
 869         struct net_device *netdev = adapter->netdev;
 870         u16 vid = adapter->hw.mng_cookie.vlan_id;
 871         u16 old_vid = adapter->mng_vlan_id;
 872         if (adapter->vlgrp) {
 873                 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
 874                         if (adapter->hw.mng_cookie.status &
 875                                 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
 876                                 igb_vlan_rx_add_vid(netdev, vid);
 877                                 adapter->mng_vlan_id = vid;
 878                         } else
 879                                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
 880
 881                         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
 882                                         (vid != old_vid) &&
 883                             !vlan_group_get_device(adapter->vlgrp, old_vid))
 884                                 igb_vlan_rx_kill_vid(netdev, old_vid);
 885                 } else
 886                         adapter->mng_vlan_id = vid;
 887         }
 888 }
 889
 890 /**
 891  * igb_release_hw_control - release control of the h/w to f/w
 892  * @adapter: address of board private structure
 893  *
 894  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 895  * For ASF and Pass Through versions of f/w this means that the
 896  * driver is no longer loaded.
 897  *
 898  **/
 899 static void igb_release_hw_control(struct igb_adapter *adapter)
 900 {
 901         struct e1000_hw *hw = &adapter->hw;
 902         u32 ctrl_ext;
 903
 904         /* Let firmware take over control of h/w */
 905         ctrl_ext = rd32(E1000_CTRL_EXT);
 906         wr32(E1000_CTRL_EXT,
 907                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
 908 }
 909
 910
 911 /**
 912  * igb_get_hw_control - get control of the h/w from f/w
 913  * @adapter: address of board private structure
 914  *
 915  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 916  * For ASF and Pass Through versions of f/w this means that
 917  * the driver is loaded.
 918  *
 919  **/
 920 static void igb_get_hw_control(struct igb_adapter *adapter)
 921 {
 922         struct e1000_hw *hw = &adapter->hw;
 923         u32 ctrl_ext;
 924
 925         /* Let firmware know the driver has taken over */
 926         ctrl_ext = rd32(E1000_CTRL_EXT);
 927         wr32(E1000_CTRL_EXT,
 928                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
 929 }
 930
 931 /**
 932  * igb_configure - configure the hardware for RX and TX
 933  * @adapter: private board structure
 934  **/
 935 static void igb_configure(struct igb_adapter *adapter)
 936 {
 937         struct net_device *netdev = adapter->netdev;
 938         int i;
 939
 940         igb_get_hw_control(adapter);
 941         igb_set_rx_mode(netdev);
 942
 943         igb_restore_vlan(adapter);
 944
 945         igb_configure_tx(adapter);
 946         igb_setup_rctl(adapter);
 947         igb_configure_rx(adapter);
 948
 949         igb_rx_fifo_flush_82575(&adapter->hw);
 950
 951         /* call igb_desc_unused which always leaves
 952          * at least 1 descriptor unused to make sure
 953          * next_to_use != next_to_clean */
 954         for (i = 0; i < adapter->num_rx_queues; i++) {
 955                 struct igb_ring *ring = &adapter->rx_ring[i];
 956                 igb_alloc_rx_buffers_adv(ring, igb_desc_unused(ring));
 957         }
 958
 959
 960         adapter->tx_queue_len = netdev->tx_queue_len;
 961 }
 962
 963
 964 /**
 965  * igb_up - Open the interface and prepare it to handle traffic
 966  * @adapter: board private structure
 967  **/
 968
 969 int igb_up(struct igb_adapter *adapter)
 970 {
 971         struct e1000_hw *hw = &adapter->hw;
 972         int i;
 973
 974         /* hardware has been reset, we need to reload some things */
 975         igb_configure(adapter);
 976
 977         clear_bit(__IGB_DOWN, &adapter->state);
 978
 979         for (i = 0; i < adapter->num_rx_queues; i++)
 980                 napi_enable(&adapter->rx_ring[i].napi);
 981         if (adapter->msix_entries)
 982                 igb_configure_msix(adapter);
 983
 984         igb_vmm_control(adapter);
 985         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
 986         igb_set_vmolr(hw, adapter->vfs_allocated_count);
 987
 988         /* Clear any pending interrupts. */
 989         rd32(E1000_ICR);
 990         igb_irq_enable(adapter);
 991
 992         netif_tx_start_all_queues(adapter->netdev);
 993
 994         /* Fire a link change interrupt to start the watchdog. */
 995         wr32(E1000_ICS, E1000_ICS_LSC);
 996         return 0;
 997 }
 998
 999 void igb_down(struct igb_adapter *adapter)
1000 {
1001         struct e1000_hw *hw = &adapter->hw;
1002         struct net_device *netdev = adapter->netdev;
1003         u32 tctl, rctl;
1004         int i;
1005
1006         /* signal that we're down so the interrupt handler does not
1007          * reschedule our watchdog timer */
1008         set_bit(__IGB_DOWN, &adapter->state);
1009
1010         /* disable receives in the hardware */
1011         rctl = rd32(E1000_RCTL);
1012         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1013         /* flush and sleep below */
1014
1015         netif_tx_stop_all_queues(netdev);
1016
1017         /* disable transmits in the hardware */
1018         tctl = rd32(E1000_TCTL);
1019         tctl &= ~E1000_TCTL_EN;
1020         wr32(E1000_TCTL, tctl);
1021         /* flush both disables and wait for them to finish */
1022         wrfl();
1023         msleep(10);
1024
1025         for (i = 0; i < adapter->num_rx_queues; i++)
1026                 napi_disable(&adapter->rx_ring[i].napi);
1027
1028         igb_irq_disable(adapter);
1029
1030         del_timer_sync(&adapter->watchdog_timer);
1031         del_timer_sync(&adapter->phy_info_timer);
1032
1033         netdev->tx_queue_len = adapter->tx_queue_len;
1034         netif_carrier_off(netdev);
1035
1036         /* record the stats before reset*/
1037         igb_update_stats(adapter);
1038
1039         adapter->link_speed = 0;
1040         adapter->link_duplex = 0;
1041
1042         if (!pci_channel_offline(adapter->pdev))
1043                 igb_reset(adapter);
1044         igb_clean_all_tx_rings(adapter);
1045         igb_clean_all_rx_rings(adapter);
1046 #ifdef CONFIG_IGB_DCA
1047
1048         /* since we reset the hardware DCA settings were cleared */
1049         igb_setup_dca(adapter);
1050 #endif
1051 }
1052
1053 void igb_reinit_locked(struct igb_adapter *adapter)
1054 {
1055         WARN_ON(in_interrupt());
1056         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1057                 msleep(1);
1058         igb_down(adapter);
1059         igb_up(adapter);
1060         clear_bit(__IGB_RESETTING, &adapter->state);
1061 }
1062
1063 void igb_reset(struct igb_adapter *adapter)
1064 {
1065         struct e1000_hw *hw = &adapter->hw;
1066         struct e1000_mac_info *mac = &hw->mac;
1067         struct e1000_fc_info *fc = &hw->fc;
1068         u32 pba = 0, tx_space, min_tx_space, min_rx_space;
1069         u16 hwm;
1070
1071         /* Repartition Pba for greater than 9k mtu
1072          * To take effect CTRL.RST is required.
1073          */
1074         switch (mac->type) {
1075         case e1000_82576:
1076                 pba = E1000_PBA_64K;
1077                 break;
1078         case e1000_82575:
1079         default:
1080                 pba = E1000_PBA_34K;
1081                 break;
1082         }
1083
1084         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1085             (mac->type < e1000_82576)) {
1086                 /* adjust PBA for jumbo frames */
1087                 wr32(E1000_PBA, pba);
1088
1089                 /* To maintain wire speed transmits, the Tx FIFO should be
1090                  * large enough to accommodate two full transmit packets,
1091                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1092                  * the Rx FIFO should be large enough to accommodate at least
1093                  * one full receive packet and is similarly rounded up and
1094                  * expressed in KB. */
1095                 pba = rd32(E1000_PBA);
1096                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1097                 tx_space = pba >> 16;
1098                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1099                 pba &= 0xffff;
1100                 /* the tx fifo also stores 16 bytes of information about the tx
1101                  * but don't include ethernet FCS because hardware appends it */
1102                 min_tx_space = (adapter->max_frame_size +
1103                                 sizeof(union e1000_adv_tx_desc) -
1104                                 ETH_FCS_LEN) * 2;
1105                 min_tx_space = ALIGN(min_tx_space, 1024);
1106                 min_tx_space >>= 10;
1107                 /* software strips receive CRC, so leave room for it */
1108                 min_rx_space = adapter->max_frame_size;
1109                 min_rx_space = ALIGN(min_rx_space, 1024);
1110                 min_rx_space >>= 10;
1111
1112                 /* If current Tx allocation is less than the min Tx FIFO size,
1113                  * and the min Tx FIFO size is less than the current Rx FIFO
1114                  * allocation, take space away from current Rx allocation */
1115                 if (tx_space < min_tx_space &&
1116                     ((min_tx_space - tx_space) < pba)) {
1117                         pba = pba - (min_tx_space - tx_space);
1118
1119                         /* if short on rx space, rx wins and must trump tx
1120                          * adjustment */
1121                         if (pba < min_rx_space)
1122                                 pba = min_rx_space;
1123                 }
1124                 wr32(E1000_PBA, pba);
1125         }
1126
1127         /* flow control settings */
1128         /* The high water mark must be low enough to fit one full frame
1129          * (or the size used for early receive) above it in the Rx FIFO.
1130          * Set it to the lower of:
1131          * - 90% of the Rx FIFO size, or
1132          * - the full Rx FIFO size minus one full frame */
1133         hwm = min(((pba << 10) * 9 / 10),
1134                         ((pba << 10) - 2 * adapter->max_frame_size));
1135
1136         if (mac->type < e1000_82576) {
1137                 fc->high_water = hwm & 0xFFF8;  /* 8-byte granularity */
1138                 fc->low_water = fc->high_water - 8;
1139         } else {
1140                 fc->high_water = hwm & 0xFFF0;  /* 16-byte granularity */
1141                 fc->low_water = fc->high_water - 16;
1142         }
1143         fc->pause_time = 0xFFFF;
1144         fc->send_xon = 1;
1145         fc->current_mode = fc->requested_mode;
1146
1147         /* disable receive for all VFs and wait one second */
1148         if (adapter->vfs_allocated_count) {
1149                 int i;
1150                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1151                         adapter->vf_data[i].clear_to_send = false;
1152
1153                 /* ping all the active vfs to let them know we are going down */
1154                         igb_ping_all_vfs(adapter);
1155
1156                 /* disable transmits and receives */
1157                 wr32(E1000_VFRE, 0);
1158                 wr32(E1000_VFTE, 0);
1159         }
1160
1161         /* Allow time for pending master requests to run */
1162         adapter->hw.mac.ops.reset_hw(&adapter->hw);
1163         wr32(E1000_WUC, 0);
1164
1165         if (adapter->hw.mac.ops.init_hw(&adapter->hw))
1166                 dev_err(&adapter->pdev->dev, "Hardware Error\n");
1167
1168         igb_update_mng_vlan(adapter);
1169
1170         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1171         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1172
1173         igb_reset_adaptive(&adapter->hw);
1174         igb_get_phy_info(&adapter->hw);
1175 }
1176
1177 static const struct net_device_ops igb_netdev_ops = {
1178         .ndo_open               = igb_open,
1179         .ndo_stop               = igb_close,
1180         .ndo_start_xmit         = igb_xmit_frame_adv,
1181         .ndo_get_stats          = igb_get_stats,
1182         .ndo_set_rx_mode        = igb_set_rx_mode,
1183         .ndo_set_multicast_list = igb_set_rx_mode,
1184         .ndo_set_mac_address    = igb_set_mac,
1185         .ndo_change_mtu         = igb_change_mtu,
1186         .ndo_do_ioctl           = igb_ioctl,
1187         .ndo_tx_timeout         = igb_tx_timeout,
1188         .ndo_validate_addr      = eth_validate_addr,
1189         .ndo_vlan_rx_register   = igb_vlan_rx_register,
1190         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1191         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1192 #ifdef CONFIG_NET_POLL_CONTROLLER
1193         .ndo_poll_controller    = igb_netpoll,
1194 #endif
1195 };
1196
1197 /**
1198  * igb_probe - Device Initialization Routine
1199  * @pdev: PCI device information struct
1200  * @ent: entry in igb_pci_tbl
1201  *
1202  * Returns 0 on success, negative on failure
1203  *
1204  * igb_probe initializes an adapter identified by a pci_dev structure.
1205  * The OS initialization, configuring of the adapter private structure,
1206  * and a hardware reset occur.
1207  **/
1208 static int __devinit igb_probe(struct pci_dev *pdev,
1209                                const struct pci_device_id *ent)
1210 {
1211         struct net_device *netdev;
1212         struct igb_adapter *adapter;
1213         struct e1000_hw *hw;
1214         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1215         unsigned long mmio_start, mmio_len;
1216         int err, pci_using_dac;
1217         u16 eeprom_data = 0;
1218         u16 eeprom_apme_mask = IGB_EEPROM_APME;
1219         u32 part_num;
1220
1221         err = pci_enable_device_mem(pdev);
1222         if (err)
1223                 return err;
1224
1225         pci_using_dac = 0;
1226         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1227         if (!err) {
1228                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1229                 if (!err)
1230                         pci_using_dac = 1;
1231         } else {
1232                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1233                 if (err) {
1234                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1235                         if (err) {
1236                                 dev_err(&pdev->dev, "No usable DMA "
1237                                         "configuration, aborting\n");
1238                                 goto err_dma;
1239                         }
1240                 }
1241         }
1242
1243         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
1244                                            IORESOURCE_MEM),
1245                                            igb_driver_name);
1246         if (err)
1247                 goto err_pci_reg;
1248
1249         err = pci_enable_pcie_error_reporting(pdev);
1250         if (err) {
1251                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
1252                         "0x%x\n", err);
1253                 /* non-fatal, continue */
1254         }
1255
1256         pci_set_master(pdev);
1257         pci_save_state(pdev);
1258
1259         err = -ENOMEM;
1260         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1261                                    IGB_ABS_MAX_TX_QUEUES);
1262         if (!netdev)
1263                 goto err_alloc_etherdev;
1264
1265         SET_NETDEV_DEV(netdev, &pdev->dev);
1266
1267         pci_set_drvdata(pdev, netdev);
1268         adapter = netdev_priv(netdev);
1269         adapter->netdev = netdev;
1270         adapter->pdev = pdev;
1271         hw = &adapter->hw;
1272         hw->back = adapter;
1273         adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
1274
1275         mmio_start = pci_resource_start(pdev, 0);
1276         mmio_len = pci_resource_len(pdev, 0);
1277
1278         err = -EIO;
1279         hw->hw_addr = ioremap(mmio_start, mmio_len);
1280         if (!hw->hw_addr)
1281                 goto err_ioremap;
1282
1283         netdev->netdev_ops = &igb_netdev_ops;
1284         igb_set_ethtool_ops(netdev);
1285         netdev->watchdog_timeo = 5 * HZ;
1286
1287         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1288
1289         netdev->mem_start = mmio_start;
1290         netdev->mem_end = mmio_start + mmio_len;
1291
1292         /* PCI config space info */
1293         hw->vendor_id = pdev->vendor;
1294         hw->device_id = pdev->device;
1295         hw->revision_id = pdev->revision;
1296         hw->subsystem_vendor_id = pdev->subsystem_vendor;
1297         hw->subsystem_device_id = pdev->subsystem_device;
1298
1299         /* setup the private structure */
1300         hw->back = adapter;
1301         /* Copy the default MAC, PHY and NVM function pointers */
1302         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
1303         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
1304         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
1305         /* Initialize skew-specific constants */
1306         err = ei->get_invariants(hw);
1307         if (err)
1308                 goto err_sw_init;
1309
1310 #ifdef CONFIG_PCI_IOV
1311         /* since iov functionality isn't critical to base device function we
1312          * can accept failure.  If it fails we don't allow iov to be enabled */
1313         if (hw->mac.type == e1000_82576) {
1314                 /* 82576 supports a maximum of 7 VFs in addition to the PF */
1315                 unsigned int num_vfs = (max_vfs > 7) ? 7 : max_vfs;
1316                 int i;
1317                 unsigned char mac_addr[ETH_ALEN];
1318
1319                 if (num_vfs) {
1320                         adapter->vf_data = kcalloc(num_vfs,
1321                                                 sizeof(struct vf_data_storage),
1322                                                 GFP_KERNEL);
1323                         if (!adapter->vf_data) {
1324                                 dev_err(&pdev->dev,
1325                                         "Could not allocate VF private data - "
1326                                         "IOV enable failed\n");
1327                         } else {
1328                                 err = pci_enable_sriov(pdev, num_vfs);
1329                                 if (!err) {
1330                                         adapter->vfs_allocated_count = num_vfs;
1331                                         dev_info(&pdev->dev,
1332                                                  "%d vfs allocated\n",
1333                                                  num_vfs);
1334                                         for (i = 0;
1335                                              i < adapter->vfs_allocated_count;
1336                                              i++) {
1337                                                 random_ether_addr(mac_addr);
1338                                                 igb_set_vf_mac(adapter, i,
1339                                                                mac_addr);
1340                                         }
1341                                 } else {
1342                                         kfree(adapter->vf_data);
1343                                         adapter->vf_data = NULL;
1344                                 }
1345                         }
1346                 }
1347         }
1348
1349 #endif
1350         /* setup the private structure */
1351         err = igb_sw_init(adapter);
1352         if (err)
1353                 goto err_sw_init;
1354
1355         igb_get_bus_info_pcie(hw);
1356
1357         /* set flags */
1358         switch (hw->mac.type) {
1359         case e1000_82575:
1360                 adapter->flags |= IGB_FLAG_NEED_CTX_IDX;
1361                 break;
1362         case e1000_82576:
1363         default:
1364                 break;
1365         }
1366
1367         hw->phy.autoneg_wait_to_complete = false;
1368         hw->mac.adaptive_ifs = true;
1369
1370         /* Copper options */
1371         if (hw->phy.media_type == e1000_media_type_copper) {
1372                 hw->phy.mdix = AUTO_ALL_MODES;
1373                 hw->phy.disable_polarity_correction = false;
1374                 hw->phy.ms_type = e1000_ms_hw_default;
1375         }
1376
1377         if (igb_check_reset_block(hw))
1378                 dev_info(&pdev->dev,
1379                         "PHY reset is blocked due to SOL/IDER session.\n");
1380
1381         netdev->features = NETIF_F_SG |
1382                            NETIF_F_IP_CSUM |
1383                            NETIF_F_HW_VLAN_TX |
1384                            NETIF_F_HW_VLAN_RX |
1385                            NETIF_F_HW_VLAN_FILTER;
1386
1387         netdev->features |= NETIF_F_IPV6_CSUM;
1388         netdev->features |= NETIF_F_TSO;
1389         netdev->features |= NETIF_F_TSO6;
1390
1391         netdev->features |= NETIF_F_GRO;
1392
1393         netdev->vlan_features |= NETIF_F_TSO;
1394         netdev->vlan_features |= NETIF_F_TSO6;
1395         netdev->vlan_features |= NETIF_F_IP_CSUM;
1396         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1397         netdev->vlan_features |= NETIF_F_SG;
1398
1399         if (pci_using_dac)
1400                 netdev->features |= NETIF_F_HIGHDMA;
1401
1402         if (adapter->hw.mac.type == e1000_82576)
1403                 netdev->features |= NETIF_F_SCTP_CSUM;
1404
1405         adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1406
1407         /* before reading the NVM, reset the controller to put the device in a
1408          * known good starting state */
1409         hw->mac.ops.reset_hw(hw);
1410
1411         /* make sure the NVM is good */
1412         if (igb_validate_nvm_checksum(hw) < 0) {
1413                 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1414                 err = -EIO;
1415                 goto err_eeprom;
1416         }
1417
1418         /* copy the MAC address out of the NVM */
1419         if (hw->mac.ops.read_mac_addr(hw))
1420                 dev_err(&pdev->dev, "NVM Read Error\n");
1421
1422         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1423         memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1424
1425         if (!is_valid_ether_addr(netdev->perm_addr)) {
1426                 dev_err(&pdev->dev, "Invalid MAC Address\n");
1427                 err = -EIO;
1428                 goto err_eeprom;
1429         }
1430
1431         setup_timer(&adapter->watchdog_timer, &igb_watchdog,
1432                     (unsigned long) adapter);
1433         setup_timer(&adapter->phy_info_timer, &igb_update_phy_info,
1434                     (unsigned long) adapter);
1435
1436         INIT_WORK(&adapter->reset_task, igb_reset_task);
1437         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1438
1439         /* Initialize link properties that are user-changeable */
1440         adapter->fc_autoneg = true;
1441         hw->mac.autoneg = true;
1442         hw->phy.autoneg_advertised = 0x2f;
1443
1444         hw->fc.requested_mode = e1000_fc_default;
1445         hw->fc.current_mode = e1000_fc_default;
1446
1447         adapter->itr_setting = IGB_DEFAULT_ITR;
1448         adapter->itr = IGB_START_ITR;
1449
1450         igb_validate_mdi_setting(hw);
1451
1452         /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1453          * enable the ACPI Magic Packet filter
1454          */
1455
1456         if (hw->bus.func == 0)
1457                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1458         else if (hw->bus.func == 1)
1459                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1460
1461         if (eeprom_data & eeprom_apme_mask)
1462                 adapter->eeprom_wol |= E1000_WUFC_MAG;
1463
1464         /* now that we have the eeprom settings, apply the special cases where
1465          * the eeprom may be wrong or the board simply won't support wake on
1466          * lan on a particular port */
1467         switch (pdev->device) {
1468         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1469                 adapter->eeprom_wol = 0;
1470                 break;
1471         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1472         case E1000_DEV_ID_82576_FIBER:
1473         case E1000_DEV_ID_82576_SERDES:
1474                 /* Wake events only supported on port A for dual fiber
1475                  * regardless of eeprom setting */
1476                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1477                         adapter->eeprom_wol = 0;
1478                 break;
1479         case E1000_DEV_ID_82576_QUAD_COPPER:
1480                 /* if quad port adapter, disable WoL on all but port A */
1481                 if (global_quad_port_a != 0)
1482                         adapter->eeprom_wol = 0;
1483                 else
1484                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
1485                 /* Reset for multiple quad port adapters */
1486                 if (++global_quad_port_a == 4)
1487                         global_quad_port_a = 0;
1488                 break;
1489         }
1490
1491         /* initialize the wol settings based on the eeprom settings */
1492         adapter->wol = adapter->eeprom_wol;
1493         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1494
1495         /* reset the hardware with the new settings */
1496         igb_reset(adapter);
1497
1498         /* let the f/w know that the h/w is now under the control of the
1499          * driver. */
1500         igb_get_hw_control(adapter);
1501
1502         strcpy(netdev->name, "eth%d");
1503         err = register_netdev(netdev);
1504         if (err)
1505                 goto err_register;
1506
1507         /* carrier off reporting is important to ethtool even BEFORE open */
1508         netif_carrier_off(netdev);
1509
1510 #ifdef CONFIG_IGB_DCA
1511         if (dca_add_requester(&pdev->dev) == 0) {
1512                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
1513                 dev_info(&pdev->dev, "DCA enabled\n");
1514                 igb_setup_dca(adapter);
1515         }
1516 #endif
1517
1518         /*
1519          * Initialize hardware timer: we keep it running just in case
1520          * that some program needs it later on.
1521          */
1522         memset(&adapter->cycles, 0, sizeof(adapter->cycles));
1523         adapter->cycles.read = igb_read_clock;
1524         adapter->cycles.mask = CLOCKSOURCE_MASK(64);
1525         adapter->cycles.mult = 1;
1526         adapter->cycles.shift = IGB_TSYNC_SHIFT;
1527         wr32(E1000_TIMINCA,
1528              (1<<24) |
1529              IGB_TSYNC_CYCLE_TIME_IN_NANOSECONDS * IGB_TSYNC_SCALE);
1530 #if 0
1531         /*
1532          * Avoid rollover while we initialize by resetting the time counter.
1533          */
1534         wr32(E1000_SYSTIML, 0x00000000);
1535         wr32(E1000_SYSTIMH, 0x00000000);
1536 #else
1537         /*
1538          * Set registers so that rollover occurs soon to test this.
1539          */
1540         wr32(E1000_SYSTIML, 0x00000000);
1541         wr32(E1000_SYSTIMH, 0xFF800000);
1542 #endif
1543         wrfl();
1544         timecounter_init(&adapter->clock,
1545                          &adapter->cycles,
1546                          ktime_to_ns(ktime_get_real()));
1547
1548         /*
1549          * Synchronize our NIC clock against system wall clock. NIC
1550          * time stamp reading requires ~3us per sample, each sample
1551          * was pretty stable even under load => only require 10
1552          * samples for each offset comparison.
1553          */
1554         memset(&adapter->compare, 0, sizeof(adapter->compare));
1555         adapter->compare.source = &adapter->clock;
1556         adapter->compare.target = ktime_get_real;
1557         adapter->compare.num_samples = 10;
1558         timecompare_update(&adapter->compare, 0);
1559
1560 #ifdef DEBUG
1561         {
1562                 char buffer[160];
1563                 printk(KERN_DEBUG
1564                         "igb: %s: hw %p initialized timer\n",
1565                         igb_get_time_str(adapter, buffer),
1566                         &adapter->hw);
1567         }
1568 #endif
1569
1570         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1571         /* print bus type/speed/width info */
1572         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
1573                  netdev->name,
1574                  ((hw->bus.speed == e1000_bus_speed_2500)
1575                   ? "2.5Gb/s" : "unknown"),
1576                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
1577                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
1578                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
1579                    "unknown"),
1580                  netdev->dev_addr);
1581
1582         igb_read_part_num(hw, &part_num);
1583         dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1584                 (part_num >> 8), (part_num & 0xff));
1585
1586         dev_info(&pdev->dev,
1587                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1588                 adapter->msix_entries ? "MSI-X" :
1589                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
1590                 adapter->num_rx_queues, adapter->num_tx_queues);
1591
1592         return 0;
1593
1594 err_register:
1595         igb_release_hw_control(adapter);
1596 err_eeprom:
1597         if (!igb_check_reset_block(hw))
1598                 igb_reset_phy(hw);
1599
1600         if (hw->flash_address)
1601                 iounmap(hw->flash_address);
1602
1603         igb_free_queues(adapter);
1604 err_sw_init:
1605         iounmap(hw->hw_addr);
1606 err_ioremap:
1607         free_netdev(netdev);
1608 err_alloc_etherdev:
1609         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1610                                      IORESOURCE_MEM));
1611 err_pci_reg:
1612 err_dma:
1613         pci_disable_device(pdev);
1614         return err;
1615 }
1616
1617 /**
1618  * igb_remove - Device Removal Routine
1619  * @pdev: PCI device information struct
1620  *
1621  * igb_remove is called by the PCI subsystem to alert the driver
1622  * that it should release a PCI device.  The could be caused by a
1623  * Hot-Plug event, or because the driver is going to be removed from
1624  * memory.
1625  **/
1626 static void __devexit igb_remove(struct pci_dev *pdev)
1627 {
1628         struct net_device *netdev = pci_get_drvdata(pdev);
1629         struct igb_adapter *adapter = netdev_priv(netdev);
1630         struct e1000_hw *hw = &adapter->hw;
1631         int err;
1632
1633         /* flush_scheduled work may reschedule our watchdog task, so
1634          * explicitly disable watchdog tasks from being rescheduled  */
1635         set_bit(__IGB_DOWN, &adapter->state);
1636         del_timer_sync(&adapter->watchdog_timer);
1637         del_timer_sync(&adapter->phy_info_timer);
1638
1639         flush_scheduled_work();
1640
1641 #ifdef CONFIG_IGB_DCA
1642         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
1643                 dev_info(&pdev->dev, "DCA disabled\n");
1644                 dca_remove_requester(&pdev->dev);
1645                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
1646                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
1647         }
1648 #endif
1649
1650         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
1651          * would have already happened in close and is redundant. */
1652         igb_release_hw_control(adapter);
1653
1654         unregister_netdev(netdev);
1655
1656         if (!igb_check_reset_block(&adapter->hw))
1657                 igb_reset_phy(&adapter->hw);
1658
1659         igb_reset_interrupt_capability(adapter);
1660
1661         igb_free_queues(adapter);
1662
1663 #ifdef CONFIG_PCI_IOV
1664         /* reclaim resources allocated to VFs */
1665         if (adapter->vf_data) {
1666                 /* disable iov and allow time for transactions to clear */
1667                 pci_disable_sriov(pdev);
1668                 msleep(500);
1669
1670                 kfree(adapter->vf_data);
1671                 adapter->vf_data = NULL;
1672                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1673                 msleep(100);
1674                 dev_info(&pdev->dev, "IOV Disabled\n");
1675         }
1676 #endif
1677         iounmap(hw->hw_addr);
1678         if (hw->flash_address)
1679                 iounmap(hw->flash_address);
1680         pci_release_selected_regions(pdev, pci_select_bars(pdev,
1681                                      IORESOURCE_MEM));
1682
1683         free_netdev(netdev);
1684
1685         err = pci_disable_pcie_error_reporting(pdev);
1686         if (err)
1687                 dev_err(&pdev->dev,
1688                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
1689
1690         pci_disable_device(pdev);
1691 }
1692
1693 /**
1694  * igb_sw_init - Initialize general software structures (struct igb_adapter)
1695  * @adapter: board private structure to initialize
1696  *
1697  * igb_sw_init initializes the Adapter private data structure.
1698  * Fields are initialized based on PCI device information and
1699  * OS network device settings (MTU size).
1700  **/
1701 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1702 {
1703         struct e1000_hw *hw = &adapter->hw;
1704         struct net_device *netdev = adapter->netdev;
1705         struct pci_dev *pdev = adapter->pdev;
1706
1707         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1708
1709         adapter->tx_ring_count = IGB_DEFAULT_TXD;
1710         adapter->rx_ring_count = IGB_DEFAULT_RXD;
1711         adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1712         adapter->rx_ps_hdr_size = 0; /* disable packet split */
1713         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1714         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1715
1716         /* This call may decrease the number of queues depending on
1717          * interrupt mode. */
1718         igb_set_interrupt_capability(adapter);
1719
1720         if (igb_alloc_queues(adapter)) {
1721                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1722                 return -ENOMEM;
1723         }
1724
1725         /* Explicitly disable IRQ since the NIC can be in any state. */
1726         igb_irq_disable(adapter);
1727
1728         set_bit(__IGB_DOWN, &adapter->state);
1729         return 0;
1730 }
1731
1732 /**
1733  * igb_open - Called when a network interface is made active
1734  * @netdev: network interface device structure
1735  *
1736  * Returns 0 on success, negative value on failure
1737  *
1738  * The open entry point is called when a network interface is made
1739  * active by the system (IFF_UP).  At this point all resources needed
1740  * for transmit and receive operations are allocated, the interrupt
1741  * handler is registered with the OS, the watchdog timer is started,
1742  * and the stack is notified that the interface is ready.
1743  **/
1744 static int igb_open(struct net_device *netdev)
1745 {
1746         struct igb_adapter *adapter = netdev_priv(netdev);
1747         struct e1000_hw *hw = &adapter->hw;
1748         int err;
1749         int i;
1750
1751         /* disallow open during test */
1752         if (test_bit(__IGB_TESTING, &adapter->state))
1753                 return -EBUSY;
1754
1755         netif_carrier_off(netdev);
1756
1757         /* allocate transmit descriptors */
1758         err = igb_setup_all_tx_resources(adapter);
1759         if (err)
1760                 goto err_setup_tx;
1761
1762         /* allocate receive descriptors */
1763         err = igb_setup_all_rx_resources(adapter);
1764         if (err)
1765                 goto err_setup_rx;
1766
1767         /* e1000_power_up_phy(adapter); */
1768
1769         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1770         if ((adapter->hw.mng_cookie.status &
1771              E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1772                 igb_update_mng_vlan(adapter);
1773
1774         /* before we allocate an interrupt, we must be ready to handle it.
1775          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1776          * as soon as we call pci_request_irq, so we have to setup our
1777          * clean_rx handler before we do so.  */
1778         igb_configure(adapter);
1779
1780         igb_vmm_control(adapter);
1781         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
1782         igb_set_vmolr(hw, adapter->vfs_allocated_count);
1783
1784         err = igb_request_irq(adapter);
1785         if (err)
1786                 goto err_req_irq;
1787
1788         /* From here on the code is the same as igb_up() */
1789         clear_bit(__IGB_DOWN, &adapter->state);
1790
1791         for (i = 0; i < adapter->num_rx_queues; i++)
1792                 napi_enable(&adapter->rx_ring[i].napi);
1793
1794         /* Clear any pending interrupts. */
1795         rd32(E1000_ICR);
1796
1797         igb_irq_enable(adapter);
1798
1799         netif_tx_start_all_queues(netdev);
1800
1801         /* Fire a link status change interrupt to start the watchdog. */
1802         wr32(E1000_ICS, E1000_ICS_LSC);
1803
1804         return 0;
1805
1806 err_req_irq:
1807         igb_release_hw_control(adapter);
1808         /* e1000_power_down_phy(adapter); */
1809         igb_free_all_rx_resources(adapter);
1810 err_setup_rx:
1811         igb_free_all_tx_resources(adapter);
1812 err_setup_tx:
1813         igb_reset(adapter);
1814
1815         return err;
1816 }
1817
1818 /**
1819  * igb_close - Disables a network interface
1820  * @netdev: network interface device structure
1821  *
1822  * Returns 0, this is not allowed to fail
1823  *
1824  * The close entry point is called when an interface is de-activated
1825  * by the OS.  The hardware is still under the driver's control, but
1826  * needs to be disabled.  A global MAC reset is issued to stop the
1827  * hardware, and all transmit and receive resources are freed.
1828  **/
1829 static int igb_close(struct net_device *netdev)
1830 {
1831         struct igb_adapter *adapter = netdev_priv(netdev);
1832
1833         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1834         igb_down(adapter);
1835
1836         igb_free_irq(adapter);
1837
1838         igb_free_all_tx_resources(adapter);
1839         igb_free_all_rx_resources(adapter);
1840
1841         /* kill manageability vlan ID if supported, but not if a vlan with
1842          * the same ID is registered on the host OS (let 8021q kill it) */
1843         if ((adapter->hw.mng_cookie.status &
1844                           E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1845              !(adapter->vlgrp &&
1846                vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1847                 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1848
1849         return 0;
1850 }
1851
1852 /**
1853  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1854  * @adapter: board private structure
1855  * @tx_ring: tx descriptor ring (for a specific queue) to setup
1856  *
1857  * Return 0 on success, negative on failure
1858  **/
1859 int igb_setup_tx_resources(struct igb_adapter *adapter,
1860                            struct igb_ring *tx_ring)
1861 {
1862         struct pci_dev *pdev = adapter->pdev;
1863         int size;
1864
1865         size = sizeof(struct igb_buffer) * tx_ring->count;
1866         tx_ring->buffer_info = vmalloc(size);
1867         if (!tx_ring->buffer_info)
1868                 goto err;
1869         memset(tx_ring->buffer_info, 0, size);
1870
1871         /* round up to nearest 4K */
1872         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1873         tx_ring->size = ALIGN(tx_ring->size, 4096);
1874
1875         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1876                                              &tx_ring->dma);
1877
1878         if (!tx_ring->desc)
1879                 goto err;
1880
1881         tx_ring->adapter = adapter;
1882         tx_ring->next_to_use = 0;
1883         tx_ring->next_to_clean = 0;
1884         return 0;
1885
1886 err:
1887         vfree(tx_ring->buffer_info);
1888         dev_err(&adapter->pdev->dev,
1889                 "Unable to allocate memory for the transmit descriptor ring\n");
1890         return -ENOMEM;
1891 }
1892
1893 /**
1894  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1895  *                                (Descriptors) for all queues
1896  * @adapter: board private structure
1897  *
1898  * Return 0 on success, negative on failure
1899  **/
1900 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1901 {
1902         int i, err = 0;
1903         int r_idx;
1904
1905         for (i = 0; i < adapter->num_tx_queues; i++) {
1906                 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1907                 if (err) {
1908                         dev_err(&adapter->pdev->dev,
1909                                 "Allocation for Tx Queue %u failed\n", i);
1910                         for (i--; i >= 0; i--)
1911                                 igb_free_tx_resources(&adapter->tx_ring[i]);
1912                         break;
1913                 }
1914         }
1915
1916         for (i = 0; i < IGB_MAX_TX_QUEUES; i++) {
1917                 r_idx = i % adapter->num_tx_queues;
1918                 adapter->multi_tx_table[i] = &adapter->tx_ring[r_idx];
1919         }
1920         return err;
1921 }
1922
1923 /**
1924  * igb_configure_tx - Configure transmit Unit after Reset
1925  * @adapter: board private structure
1926  *
1927  * Configure the Tx unit of the MAC after a reset.
1928  **/
1929 static void igb_configure_tx(struct igb_adapter *adapter)
1930 {
1931         u64 tdba;
1932         struct e1000_hw *hw = &adapter->hw;
1933         u32 tctl;
1934         u32 txdctl, txctrl;
1935         int i, j;
1936
1937         for (i = 0; i < adapter->num_tx_queues; i++) {
1938                 struct igb_ring *ring = &adapter->tx_ring[i];
1939                 j = ring->reg_idx;
1940                 wr32(E1000_TDLEN(j),
1941                      ring->count * sizeof(union e1000_adv_tx_desc));
1942                 tdba = ring->dma;
1943                 wr32(E1000_TDBAL(j),
1944                      tdba & 0x00000000ffffffffULL);
1945                 wr32(E1000_TDBAH(j), tdba >> 32);
1946
1947                 ring->head = E1000_TDH(j);
1948                 ring->tail = E1000_TDT(j);
1949                 writel(0, hw->hw_addr + ring->tail);
1950                 writel(0, hw->hw_addr + ring->head);
1951                 txdctl = rd32(E1000_TXDCTL(j));
1952                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1953                 wr32(E1000_TXDCTL(j), txdctl);
1954
1955                 /* Turn off Relaxed Ordering on head write-backs.  The
1956                  * writebacks MUST be delivered in order or it will
1957                  * completely screw up our bookeeping.
1958                  */
1959                 txctrl = rd32(E1000_DCA_TXCTRL(j));
1960                 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1961                 wr32(E1000_DCA_TXCTRL(j), txctrl);
1962         }
1963
1964         /* disable queue 0 to prevent tail bump w/o re-configuration */
1965         if (adapter->vfs_allocated_count)
1966                 wr32(E1000_TXDCTL(0), 0);
1967
1968         /* Program the Transmit Control Register */
1969         tctl = rd32(E1000_TCTL);
1970         tctl &= ~E1000_TCTL_CT;
1971         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1972                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1973
1974         igb_config_collision_dist(hw);
1975
1976         /* Setup Transmit Descriptor Settings for eop descriptor */
1977         adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1978
1979         /* Enable transmits */
1980         tctl |= E1000_TCTL_EN;
1981
1982         wr32(E1000_TCTL, tctl);
1983 }
1984
1985 /**
1986  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1987  * @adapter: board private structure
1988  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
1989  *
1990  * Returns 0 on success, negative on failure
1991  **/
1992 int igb_setup_rx_resources(struct igb_adapter *adapter,
1993                            struct igb_ring *rx_ring)
1994 {
1995         struct pci_dev *pdev = adapter->pdev;
1996         int size, desc_len;
1997
1998         size = sizeof(struct igb_buffer) * rx_ring->count;
1999         rx_ring->buffer_info = vmalloc(size);
2000         if (!rx_ring->buffer_info)
2001                 goto err;
2002         memset(rx_ring->buffer_info, 0, size);
2003
2004         desc_len = sizeof(union e1000_adv_rx_desc);
2005
2006         /* Round up to nearest 4K */
2007         rx_ring->size = rx_ring->count * desc_len;
2008         rx_ring->size = ALIGN(rx_ring->size, 4096);
2009
2010         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
2011                                              &rx_ring->dma);
2012
2013         if (!rx_ring->desc)
2014                 goto err;
2015
2016         rx_ring->next_to_clean = 0;
2017         rx_ring->next_to_use = 0;
2018
2019         rx_ring->adapter = adapter;
2020
2021         return 0;
2022
2023 err:
2024         vfree(rx_ring->buffer_info);
2025         dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
2026                 "the receive descriptor ring\n");
2027         return -ENOMEM;
2028 }
2029
2030 /**
2031  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
2032  *                                (Descriptors) for all queues
2033  * @adapter: board private structure
2034  *
2035  * Return 0 on success, negative on failure
2036  **/
2037 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
2038 {
2039         int i, err = 0;
2040
2041         for (i = 0; i < adapter->num_rx_queues; i++) {
2042                 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2043                 if (err) {
2044                         dev_err(&adapter->pdev->dev,
2045                                 "Allocation for Rx Queue %u failed\n", i);
2046                         for (i--; i >= 0; i--)
2047                                 igb_free_rx_resources(&adapter->rx_ring[i]);
2048                         break;
2049                 }
2050         }
2051
2052         return err;
2053 }
2054
2055 /**
2056  * igb_setup_rctl - configure the receive control registers
2057  * @adapter: Board private structure
2058  **/
2059 static void igb_setup_rctl(struct igb_adapter *adapter)
2060 {
2061         struct e1000_hw *hw = &adapter->hw;
2062         u32 rctl;
2063         u32 srrctl = 0;
2064         int i;
2065
2066         rctl = rd32(E1000_RCTL);
2067
2068         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2069         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2070
2071         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2072                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2073
2074         /*
2075          * enable stripping of CRC. It's unlikely this will break BMC
2076          * redirection as it did with e1000. Newer features require
2077          * that the HW strips the CRC.
2078          */
2079         rctl |= E1000_RCTL_SECRC;
2080
2081         /*
2082          * disable store bad packets and clear size bits.
2083          */
2084         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2085
2086         /* enable LPE when to prevent packets larger than max_frame_size */
2087                 rctl |= E1000_RCTL_LPE;
2088
2089         /* Setup buffer sizes */
2090         switch (adapter->rx_buffer_len) {
2091         case IGB_RXBUFFER_256:
2092                 rctl |= E1000_RCTL_SZ_256;
2093                 break;
2094         case IGB_RXBUFFER_512:
2095                 rctl |= E1000_RCTL_SZ_512;
2096                 break;
2097         default:
2098                 srrctl = ALIGN(adapter->rx_buffer_len, 1024)
2099                          >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2100                 break;
2101         }
2102
2103         /* 82575 and greater support packet-split where the protocol
2104          * header is placed in skb->data and the packet data is
2105          * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2106          * In the case of a non-split, skb->data is linearly filled,
2107          * followed by the page buffers.  Therefore, skb->data is
2108          * sized to hold the largest protocol header.
2109          */
2110         /* allocations using alloc_page take too long for regular MTU
2111          * so only enable packet split for jumbo frames */
2112         if (adapter->netdev->mtu > ETH_DATA_LEN) {
2113                 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
2114                 srrctl |= adapter->rx_ps_hdr_size <<
2115                          E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2116                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2117         } else {
2118                 adapter->rx_ps_hdr_size = 0;
2119                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2120         }
2121
2122         /* Attention!!!  For SR-IOV PF driver operations you must enable
2123          * queue drop for all VF and PF queues to prevent head of line blocking
2124          * if an un-trusted VF does not provide descriptors to hardware.
2125          */
2126         if (adapter->vfs_allocated_count) {
2127                 u32 vmolr;
2128
2129                 /* set all queue drop enable bits */
2130                 wr32(E1000_QDE, ALL_QUEUES);
2131                 srrctl |= E1000_SRRCTL_DROP_EN;
2132
2133                 /* disable queue 0 to prevent tail write w/o re-config */
2134                 wr32(E1000_RXDCTL(0), 0);
2135
2136                 vmolr = rd32(E1000_VMOLR(adapter->vfs_allocated_count));
2137                 if (rctl & E1000_RCTL_LPE)
2138                         vmolr |= E1000_VMOLR_LPE;
2139                 if (adapter->num_rx_queues > 1)
2140                         vmolr |= E1000_VMOLR_RSSE;
2141                 wr32(E1000_VMOLR(adapter->vfs_allocated_count), vmolr);
2142         }
2143
2144         for (i = 0; i < adapter->num_rx_queues; i++) {
2145                 int j = adapter->rx_ring[i].reg_idx;
2146                 wr32(E1000_SRRCTL(j), srrctl);
2147         }
2148
2149         wr32(E1000_RCTL, rctl);
2150 }
2151
2152 /**
2153  * igb_rlpml_set - set maximum receive packet size
2154  * @adapter: board private structure
2155  *
2156  * Configure maximum receivable packet size.
2157  **/
2158 static void igb_rlpml_set(struct igb_adapter *adapter)
2159 {
2160         u32 max_frame_size = adapter->max_frame_size;
2161         struct e1000_hw *hw = &adapter->hw;
2162         u16 pf_id = adapter->vfs_allocated_count;
2163
2164         if (adapter->vlgrp)
2165                 max_frame_size += VLAN_TAG_SIZE;
2166
2167         /* if vfs are enabled we set RLPML to the largest possible request
2168          * size and set the VMOLR RLPML to the size we need */
2169         if (pf_id) {
2170                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
2171                 max_frame_size = MAX_STD_JUMBO_FRAME_SIZE + VLAN_TAG_SIZE;
2172         }
2173
2174         wr32(E1000_RLPML, max_frame_size);
2175 }
2176
2177 /**
2178  * igb_configure_vt_default_pool - Configure VT default pool
2179  * @adapter: board private structure
2180  *
2181  * Configure the default pool
2182  **/
2183 static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
2184 {
2185         struct e1000_hw *hw = &adapter->hw;
2186         u16 pf_id = adapter->vfs_allocated_count;
2187         u32 vtctl;
2188
2189         /* not in sr-iov mode - do nothing */
2190         if (!pf_id)
2191                 return;
2192
2193         vtctl = rd32(E1000_VT_CTL);
2194         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
2195                    E1000_VT_CTL_DISABLE_DEF_POOL);
2196         vtctl |= pf_id << E1000_VT_CTL_DEFAULT_POOL_SHIFT;
2197         wr32(E1000_VT_CTL, vtctl);
2198 }
2199
2200 /**
2201  * igb_configure_rx - Configure receive Unit after Reset
2202  * @adapter: board private structure
2203  *
2204  * Configure the Rx unit of the MAC after a reset.
2205  **/
2206 static void igb_configure_rx(struct igb_adapter *adapter)
2207 {
2208         u64 rdba;
2209         struct e1000_hw *hw = &adapter->hw;
2210         u32 rctl, rxcsum;
2211         u32 rxdctl;
2212         int i;
2213
2214         /* disable receives while setting up the descriptors */
2215         rctl = rd32(E1000_RCTL);
2216         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2217         wrfl();
2218         mdelay(10);
2219
2220         if (adapter->itr_setting > 3)
2221                 wr32(E1000_ITR, adapter->itr);
2222
2223         /* Setup the HW Rx Head and Tail Descriptor Pointers and
2224          * the Base and Length of the Rx Descriptor Ring */
2225         for (i = 0; i < adapter->num_rx_queues; i++) {
2226                 struct igb_ring *ring = &adapter->rx_ring[i];
2227                 int j = ring->reg_idx;
2228                 rdba = ring->dma;
2229                 wr32(E1000_RDBAL(j),
2230                      rdba & 0x00000000ffffffffULL);
2231                 wr32(E1000_RDBAH(j), rdba >> 32);
2232                 wr32(E1000_RDLEN(j),
2233                      ring->count * sizeof(union e1000_adv_rx_desc));
2234
2235                 ring->head = E1000_RDH(j);
2236                 ring->tail = E1000_RDT(j);
2237                 writel(0, hw->hw_addr + ring->tail);
2238                 writel(0, hw->hw_addr + ring->head);
2239
2240                 rxdctl = rd32(E1000_RXDCTL(j));
2241                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2242                 rxdctl &= 0xFFF00000;
2243                 rxdctl |= IGB_RX_PTHRESH;
2244                 rxdctl |= IGB_RX_HTHRESH << 8;
2245                 rxdctl |= IGB_RX_WTHRESH << 16;
2246                 wr32(E1000_RXDCTL(j), rxdctl);
2247         }
2248
2249         if (adapter->num_rx_queues > 1) {
2250                 u32 random[10];
2251                 u32 mrqc;
2252                 u32 j, shift;
2253                 union e1000_reta {
2254                         u32 dword;
2255                         u8  bytes[4];
2256                 } reta;
2257
2258                 get_random_bytes(&random[0], 40);
2259
2260                 if (hw->mac.type >= e1000_82576)
2261                         shift = 0;
2262                 else
2263                         shift = 6;
2264                 for (j = 0; j < (32 * 4); j++) {
2265                         reta.bytes[j & 3] =
2266                                 adapter->rx_ring[(j % adapter->num_rx_queues)].reg_idx << shift;
2267                         if ((j & 3) == 3)
2268                                 writel(reta.dword,
2269                                        hw->hw_addr + E1000_RETA(0) + (j & ~3));
2270                 }
2271                 if (adapter->vfs_allocated_count)
2272                         mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
2273                 else
2274                         mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2275
2276                 /* Fill out hash function seeds */
2277                 for (j = 0; j < 10; j++)
2278                         array_wr32(E1000_RSSRK(0), j, random[j]);
2279
2280                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2281                          E1000_MRQC_RSS_FIELD_IPV4_TCP);
2282                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2283                          E1000_MRQC_RSS_FIELD_IPV6_TCP);
2284                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
2285                          E1000_MRQC_RSS_FIELD_IPV6_UDP);
2286                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2287                          E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2288
2289                 wr32(E1000_MRQC, mrqc);
2290         } else if (adapter->vfs_allocated_count) {
2291                 /* Enable multi-queue for sr-iov */
2292                 wr32(E1000_MRQC, E1000_MRQC_ENABLE_VMDQ);
2293         }
2294
2295         /* Enable Receive Checksum Offload for TCP and UDP */
2296         rxcsum = rd32(E1000_RXCSUM);
2297         /* Disable raw packet checksumming */
2298         rxcsum |= E1000_RXCSUM_PCSD;
2299
2300         if (adapter->hw.mac.type == e1000_82576)
2301                 /* Enable Receive Checksum Offload for SCTP */
2302                 rxcsum |= E1000_RXCSUM_CRCOFL;
2303
2304         /* Don't need to set TUOFL or IPOFL, they default to 1 */
2305         wr32(E1000_RXCSUM, rxcsum);
2306
2307         /* Set the default pool for the PF's first queue */
2308         igb_configure_vt_default_pool(adapter);
2309
2310         igb_rlpml_set(adapter);
2311
2312         /* Enable Receives */
2313         wr32(E1000_RCTL, rctl);
2314 }
2315
2316 /**
2317  * igb_free_tx_resources - Free Tx Resources per Queue
2318  * @tx_ring: Tx descriptor ring for a specific queue
2319  *
2320  * Free all transmit software resources
2321  **/
2322 void igb_free_tx_resources(struct igb_ring *tx_ring)
2323 {
2324         struct pci_dev *pdev = tx_ring->adapter->pdev;
2325
2326         igb_clean_tx_ring(tx_ring);
2327
2328         vfree(tx_ring->buffer_info);
2329         tx_ring->buffer_info = NULL;
2330
2331         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2332
2333         tx_ring->desc = NULL;
2334 }
2335
2336 /**
2337  * igb_free_all_tx_resources - Free Tx Resources for All Queues
2338  * @adapter: board private structure
2339  *
2340  * Free all transmit software resources
2341  **/
2342 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
2343 {
2344         int i;
2345
2346         for (i = 0; i < adapter->num_tx_queues; i++)
2347                 igb_free_tx_resources(&adapter->tx_ring[i]);
2348 }
2349
2350 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
2351                                            struct igb_buffer *buffer_info)
2352 {
2353         buffer_info->dma = 0;
2354         if (buffer_info->skb) {
2355                 skb_dma_unmap(&adapter->pdev->dev, buffer_info->skb,
2356                               DMA_TO_DEVICE);
2357                 dev_kfree_skb_any(buffer_info->skb);
2358                 buffer_info->skb = NULL;
2359         }
2360         buffer_info->time_stamp = 0;
2361         /* buffer_info must be completely set up in the transmit path */
2362 }
2363
2364 /**
2365  * igb_clean_tx_ring - Free Tx Buffers
2366  * @tx_ring: ring to be cleaned
2367  **/
2368 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
2369 {
2370         struct igb_adapter *adapter = tx_ring->adapter;
2371         struct igb_buffer *buffer_info;
2372         unsigned long size;
2373         unsigned int i;
2374
2375         if (!tx_ring->buffer_info)
2376                 return;
2377         /* Free all the Tx ring sk_buffs */
2378
2379         for (i = 0; i < tx_ring->count; i++) {
2380                 buffer_info = &tx_ring->buffer_info[i];
2381                 igb_unmap_and_free_tx_resource(adapter, buffer_info);
2382         }
2383
2384         size = sizeof(struct igb_buffer) * tx_ring->count;
2385         memset(tx_ring->buffer_info, 0, size);
2386
2387         /* Zero out the descriptor ring */
2388
2389         memset(tx_ring->desc, 0, tx_ring->size);
2390
2391         tx_ring->next_to_use = 0;
2392         tx_ring->next_to_clean = 0;
2393
2394         writel(0, adapter->hw.hw_addr + tx_ring->head);
2395         writel(0, adapter->hw.hw_addr + tx_ring->tail);
2396 }
2397
2398 /**
2399  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
2400  * @adapter: board private structure
2401  **/
2402 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
2403 {
2404         int i;
2405
2406         for (i = 0; i < adapter->num_tx_queues; i++)
2407                 igb_clean_tx_ring(&adapter->tx_ring[i]);
2408 }
2409
2410 /**
2411  * igb_free_rx_resources - Free Rx Resources
2412  * @rx_ring: ring to clean the resources from
2413  *
2414  * Free all receive software resources
2415  **/
2416 void igb_free_rx_resources(struct igb_ring *rx_ring)
2417 {
2418         struct pci_dev *pdev = rx_ring->adapter->pdev;
2419
2420         igb_clean_rx_ring(rx_ring);
2421
2422         vfree(rx_ring->buffer_info);
2423         rx_ring->buffer_info = NULL;
2424
2425         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2426
2427         rx_ring->desc = NULL;
2428 }
2429
2430 /**
2431  * igb_free_all_rx_resources - Free Rx Resources for All Queues
2432  * @adapter: board private structure
2433  *
2434  * Free all receive software resources
2435  **/
2436 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
2437 {
2438         int i;
2439
2440         for (i = 0; i < adapter->num_rx_queues; i++)
2441                 igb_free_rx_resources(&adapter->rx_ring[i]);
2442 }
2443
2444 /**
2445  * igb_clean_rx_ring - Free Rx Buffers per Queue
2446  * @rx_ring: ring to free buffers from
2447  **/
2448 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
2449 {
2450         struct igb_adapter *adapter = rx_ring->adapter;
2451         struct igb_buffer *buffer_info;
2452         struct pci_dev *pdev = adapter->pdev;
2453         unsigned long size;
2454         unsigned int i;
2455
2456         if (!rx_ring->buffer_info)
2457                 return;
2458         /* Free all the Rx ring sk_buffs */
2459         for (i = 0; i < rx_ring->count; i++) {
2460                 buffer_info = &rx_ring->buffer_info[i];
2461                 if (buffer_info->dma) {
2462                         if (adapter->rx_ps_hdr_size)
2463                                 pci_unmap_single(pdev, buffer_info->dma,
2464                                                  adapter->rx_ps_hdr_size,
2465                                                  PCI_DMA_FROMDEVICE);
2466                         else
2467                                 pci_unmap_single(pdev, buffer_info->dma,
2468                                                  adapter->rx_buffer_len,
2469                                                  PCI_DMA_FROMDEVICE);
2470                         buffer_info->dma = 0;
2471                 }
2472
2473                 if (buffer_info->skb) {
2474                         dev_kfree_skb(buffer_info->skb);
2475                         buffer_info->skb = NULL;
2476                 }
2477                 if (buffer_info->page) {
2478                         if (buffer_info->page_dma)
2479                                 pci_unmap_page(pdev, buffer_info->page_dma,
2480                                                PAGE_SIZE / 2,
2481                                                PCI_DMA_FROMDEVICE);
2482                         put_page(buffer_info->page);
2483                         buffer_info->page = NULL;
2484                         buffer_info->page_dma = 0;
2485                         buffer_info->page_offset = 0;
2486                 }
2487         }
2488
2489         size = sizeof(struct igb_buffer) * rx_ring->count;
2490         memset(rx_ring->buffer_info, 0, size);
2491
2492         /* Zero out the descriptor ring */
2493         memset(rx_ring->desc, 0, rx_ring->size);
2494
2495         rx_ring->next_to_clean = 0;
2496         rx_ring->next_to_use = 0;
2497
2498         writel(0, adapter->hw.hw_addr + rx_ring->head);
2499         writel(0, adapter->hw.hw_addr + rx_ring->tail);
2500 }
2501
2502 /**
2503  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
2504  * @adapter: board private structure
2505  **/
2506 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
2507 {
2508         int i;
2509
2510         for (i = 0; i < adapter->num_rx_queues; i++)
2511                 igb_clean_rx_ring(&adapter->rx_ring[i]);
2512 }
2513
2514 /**
2515  * igb_set_mac - Change the Ethernet Address of the NIC
2516  * @netdev: network interface device structure
2517  * @p: pointer to an address structure
2518  *
2519  * Returns 0 on success, negative on failure
2520  **/
2521 static int igb_set_mac(struct net_device *netdev, void *p)
2522 {
2523         struct igb_adapter *adapter = netdev_priv(netdev);
2524         struct e1000_hw *hw = &adapter->hw;
2525         struct sockaddr *addr = p;
2526
2527         if (!is_valid_ether_addr(addr->sa_data))
2528                 return -EADDRNOTAVAIL;
2529
2530         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2531         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
2532
2533         igb_rar_set(hw, hw->mac.addr, 0);
2534         igb_set_rah_pool(hw, adapter->vfs_allocated_count, 0);
2535
2536         return 0;
2537 }
2538
2539 /**
2540  * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
2541  * @netdev: network interface device structure
2542  *
2543  * The set_rx_mode entry point is called whenever the unicast or multicast
2544  * address lists or the network interface flags are updated.  This routine is
2545  * responsible for configuring the hardware for proper unicast, multicast,
2546  * promiscuous mode, and all-multi behavior.
2547  **/
2548 static void igb_set_rx_mode(struct net_device *netdev)
2549 {
2550         struct igb_adapter *adapter = netdev_priv(netdev);
2551         struct e1000_hw *hw = &adapter->hw;
2552         unsigned int rar_entries = hw->mac.rar_entry_count -
2553                                    (adapter->vfs_allocated_count + 1);
2554         struct dev_mc_list *mc_ptr = netdev->mc_list;
2555         u8  *mta_list = NULL;
2556         u32 rctl;
2557         int i;
2558
2559         /* Check for Promiscuous and All Multicast modes */
2560         rctl = rd32(E1000_RCTL);
2561
2562         if (netdev->flags & IFF_PROMISC) {
2563                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2564                 rctl &= ~E1000_RCTL_VFE;
2565         } else {
2566                 if (netdev->flags & IFF_ALLMULTI)
2567                         rctl |= E1000_RCTL_MPE;
2568                 else
2569                         rctl &= ~E1000_RCTL_MPE;
2570
2571                 if (netdev->uc.count > rar_entries)
2572                         rctl |= E1000_RCTL_UPE;
2573                 else
2574                         rctl &= ~E1000_RCTL_UPE;
2575                 rctl |= E1000_RCTL_VFE;
2576         }
2577         wr32(E1000_RCTL, rctl);
2578
2579         if (netdev->uc.count && rar_entries) {
2580                 struct netdev_hw_addr *ha;
2581                 list_for_each_entry(ha, &netdev->uc.list, list) {
2582                         if (!rar_entries)
2583                                 break;
2584                         igb_rar_set(hw, ha->addr, rar_entries);
2585                         igb_set_rah_pool(hw, adapter->vfs_allocated_count,
2586                                          rar_entries);
2587                         rar_entries--;
2588                 }
2589         }
2590         /* write the addresses in reverse order to avoid write combining */
2591         for (; rar_entries > 0 ; rar_entries--) {
2592                 wr32(E1000_RAH(rar_entries), 0);
2593                 wr32(E1000_RAL(rar_entries), 0);
2594         }
2595         wrfl();
2596
2597         if (!netdev->mc_count) {
2598                 /* nothing to program, so clear mc list */
2599                 igb_update_mc_addr_list(hw, NULL, 0);
2600                 igb_restore_vf_multicasts(adapter);
2601                 return;
2602         }
2603
2604         mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2605         if (!mta_list) {
2606                 dev_err(&adapter->pdev->dev,
2607                         "failed to allocate multicast filter list\n");
2608                 return;
2609         }
2610
2611         /* The shared function expects a packed array of only addresses. */
2612         for (i = 0; i < netdev->mc_count; i++) {
2613                 if (!mc_ptr)
2614                         break;
2615                 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2616                 mc_ptr = mc_ptr->next;
2617         }
2618         igb_update_mc_addr_list(hw, mta_list, i);
2619         kfree(mta_list);
2620         igb_restore_vf_multicasts(adapter);
2621 }
2622
2623 /* Need to wait a few seconds after link up to get diagnostic information from
2624  * the phy */
2625 static void igb_update_phy_info(unsigned long data)
2626 {
2627         struct igb_adapter *adapter = (struct igb_adapter *) data;
2628         igb_get_phy_info(&adapter->hw);
2629 }
2630
2631 /**
2632  * igb_has_link - check shared code for link and determine up/down
2633  * @adapter: pointer to driver private info
2634  **/
2635 static bool igb_has_link(struct igb_adapter *adapter)
2636 {
2637         struct e1000_hw *hw = &adapter->hw;
2638         bool link_active = false;
2639         s32 ret_val = 0;
2640
2641         /* get_link_status is set on LSC (link status) interrupt or
2642          * rx sequence error interrupt.  get_link_status will stay
2643          * false until the e1000_check_for_link establishes link
2644          * for copper adapters ONLY
2645          */
2646         switch (hw->phy.media_type) {
2647         case e1000_media_type_copper:
2648                 if (hw->mac.get_link_status) {
2649                         ret_val = hw->mac.ops.check_for_link(hw);
2650                         link_active = !hw->mac.get_link_status;
2651                 } else {
2652                         link_active = true;
2653                 }
2654                 break;
2655         case e1000_media_type_internal_serdes:
2656                 ret_val = hw->mac.ops.check_for_link(hw);
2657                 link_active = hw->mac.serdes_has_link;
2658                 break;
2659         default:
2660         case e1000_media_type_unknown:
2661                 break;
2662         }
2663
2664         return link_active;
2665 }
2666
2667 /**
2668  * igb_watchdog - Timer Call-back
2669  * @data: pointer to adapter cast into an unsigned long
2670  **/
2671 static void igb_watchdog(unsigned long data)
2672 {
2673         struct igb_adapter *adapter = (struct igb_adapter *)data;
2674         /* Do the rest outside of interrupt context */
2675         schedule_work(&adapter->watchdog_task);
2676 }
2677
2678 static void igb_watchdog_task(struct work_struct *work)
2679 {
2680         struct igb_adapter *adapter = container_of(work,
2681                                         struct igb_adapter, watchdog_task);
2682         struct e1000_hw *hw = &adapter->hw;
2683         struct net_device *netdev = adapter->netdev;
2684         struct igb_ring *tx_ring = adapter->tx_ring;
2685         u32 link;
2686         u32 eics = 0;
2687         int i;
2688
2689         link = igb_has_link(adapter);
2690         if ((netif_carrier_ok(netdev)) && link)
2691                 goto link_up;
2692
2693         if (link) {
2694                 if (!netif_carrier_ok(netdev)) {
2695                         u32 ctrl;
2696                         hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2697                                                    &adapter->link_speed,
2698                                                    &adapter->link_duplex);
2699
2700                         ctrl = rd32(E1000_CTRL);
2701                         /* Links status message must follow this format */
2702                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
2703                                  "Flow Control: %s\n",
2704                                  netdev->name,
2705                                  adapter->link_speed,
2706                                  adapter->link_duplex == FULL_DUPLEX ?
2707                                  "Full Duplex" : "Half Duplex",
2708                                  ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2709                                  E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2710                                  E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2711                                  E1000_CTRL_TFCE) ? "TX" : "None")));
2712
2713                         /* tweak tx_queue_len according to speed/duplex and
2714                          * adjust the timeout factor */
2715                         netdev->tx_queue_len = adapter->tx_queue_len;
2716                         adapter->tx_timeout_factor = 1;
2717                         switch (adapter->link_speed) {
2718                         case SPEED_10:
2719                                 netdev->tx_queue_len = 10;
2720                                 adapter->tx_timeout_factor = 14;
2721                                 break;
2722                         case SPEED_100:
2723                                 netdev->tx_queue_len = 100;
2724                                 /* maybe add some timeout factor ? */
2725                                 break;
2726                         }
2727
2728                         netif_carrier_on(netdev);
2729
2730                         igb_ping_all_vfs(adapter);
2731
2732                         /* link state has changed, schedule phy info update */
2733                         if (!test_bit(__IGB_DOWN, &adapter->state))
2734                                 mod_timer(&adapter->phy_info_timer,
2735                                           round_jiffies(jiffies + 2 * HZ));
2736                 }
2737         } else {
2738                 if (netif_carrier_ok(netdev)) {
2739                         adapter->link_speed = 0;
2740                         adapter->link_duplex = 0;
2741                         /* Links status message must follow this format */
2742                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
2743                                netdev->name);
2744                         netif_carrier_off(netdev);
2745
2746                         igb_ping_all_vfs(adapter);
2747
2748                         /* link state has changed, schedule phy info update */
2749                         if (!test_bit(__IGB_DOWN, &adapter->state))
2750                                 mod_timer(&adapter->phy_info_timer,
2751                                           round_jiffies(jiffies + 2 * HZ));
2752                 }
2753         }
2754
2755 link_up:
2756         igb_update_stats(adapter);
2757
2758         hw->mac.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2759         adapter->tpt_old = adapter->stats.tpt;
2760         hw->mac.collision_delta = adapter->stats.colc - adapter->colc_old;
2761         adapter->colc_old = adapter->stats.colc;
2762
2763         adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2764         adapter->gorc_old = adapter->stats.gorc;
2765         adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2766         adapter->gotc_old = adapter->stats.gotc;
2767
2768         igb_update_adaptive(&adapter->hw);
2769
2770         if (!netif_carrier_ok(netdev)) {
2771                 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
2772                         /* We've lost link, so the controller stops DMA,
2773                          * but we've got queued Tx work that's never going
2774                          * to get done, so reset controller to flush Tx.
2775                          * (Do the reset outside of interrupt context). */
2776                         adapter->tx_timeout_count++;
2777                         schedule_work(&adapter->reset_task);
2778                         /* return immediately since reset is imminent */
2779                         return;
2780                 }
2781         }
2782
2783         /* Cause software interrupt to ensure rx ring is cleaned */
2784         if (adapter->msix_entries) {
2785                 for (i = 0; i < adapter->num_rx_queues; i++)
2786                         eics |= adapter->rx_ring[i].eims_value;
2787                 wr32(E1000_EICS, eics);
2788         } else {
2789                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2790         }
2791
2792         /* Force detection of hung controller every watchdog period */
2793         tx_ring->detect_tx_hung = true;
2794
2795         /* Reset the timer */
2796         if (!test_bit(__IGB_DOWN, &adapter->state))
2797                 mod_timer(&adapter->watchdog_timer,
2798                           round_jiffies(jiffies + 2 * HZ));
2799 }
2800
2801 enum latency_range {
2802         lowest_latency = 0,
2803         low_latency = 1,
2804         bulk_latency = 2,
2805         latency_invalid = 255
2806 };
2807
2808
2809 /**
2810  * igb_update_ring_itr - update the dynamic ITR value based on packet size
2811  *
2812  *      Stores a new ITR value based on strictly on packet size.  This
2813  *      algorithm is less sophisticated than that used in igb_update_itr,
2814  *      due to the difficulty of synchronizing statistics across multiple
2815  *      receive rings.  The divisors and thresholds used by this fuction
2816  *      were determined based on theoretical maximum wire speed and testing
2817  *      data, in order to minimize response time while increasing bulk
2818  *      throughput.
2819  *      This functionality is controlled by the InterruptThrottleRate module
2820  *      parameter (see igb_param.c)
2821  *      NOTE:  This function is called only when operating in a multiqueue
2822  *             receive environment.
2823  * @rx_ring: pointer to ring
2824  **/
2825 static void igb_update_ring_itr(struct igb_ring *rx_ring)
2826 {
2827         int new_val = rx_ring->itr_val;
2828         int avg_wire_size = 0;
2829         struct igb_adapter *adapter = rx_ring->adapter;
2830
2831         if (!rx_ring->total_packets)
2832                 goto clear_counts; /* no packets, so don't do anything */
2833
2834         /* For non-gigabit speeds, just fix the interrupt rate at 4000
2835          * ints/sec - ITR timer value of 120 ticks.
2836          */
2837         if (adapter->link_speed != SPEED_1000) {
2838                 new_val = 120;
2839                 goto set_itr_val;
2840         }
2841         avg_wire_size = rx_ring->total_bytes / rx_ring->total_packets;
2842
2843         /* Add 24 bytes to size to account for CRC, preamble, and gap */
2844         avg_wire_size += 24;
2845
2846         /* Don't starve jumbo frames */
2847         avg_wire_size = min(avg_wire_size, 3000);
2848
2849         /* Give a little boost to mid-size frames */
2850         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
2851                 new_val = avg_wire_size / 3;
2852         else
2853                 new_val = avg_wire_size / 2;
2854
2855 set_itr_val:
2856         if (new_val != rx_ring->itr_val) {
2857                 rx_ring->itr_val = new_val;
2858                 rx_ring->set_itr = 1;
2859         }
2860 clear_counts:
2861         rx_ring->total_bytes = 0;
2862         rx_ring->total_packets = 0;
2863 }
2864
2865 /**
2866  * igb_update_itr - update the dynamic ITR value based on statistics
2867  *      Stores a new ITR value based on packets and byte
2868  *      counts during the last interrupt.  The advantage of per interrupt
2869  *      computation is faster updates and more accurate ITR for the current
2870  *      traffic pattern.  Constants in this function were computed
2871  *      based on theoretical maximum wire speed and thresholds were set based
2872  *      on testing data as well as attempting to minimize response time
2873  *      while increasing bulk throughput.
2874  *      this functionality is controlled by the InterruptThrottleRate module
2875  *      parameter (see igb_param.c)
2876  *      NOTE:  These calculations are only valid when operating in a single-
2877  *             queue environment.
2878  * @adapter: pointer to adapter
2879  * @itr_setting: current adapter->itr
2880  * @packets: the number of packets during this measurement interval
2881  * @bytes: the number of bytes during this measurement interval
2882  **/
2883 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2884                                    int packets, int bytes)
2885 {
2886         unsigned int retval = itr_setting;
2887
2888         if (packets == 0)
2889                 goto update_itr_done;
2890
2891         switch (itr_setting) {
2892         case lowest_latency:
2893                 /* handle TSO and jumbo frames */
2894                 if (bytes/packets > 8000)
2895                         retval = bulk_latency;
2896                 else if ((packets < 5) && (bytes > 512))
2897                         retval = low_latency;
2898                 break;
2899         case low_latency:  /* 50 usec aka 20000 ints/s */
2900                 if (bytes > 10000) {
2901                         /* this if handles the TSO accounting */
2902                         if (bytes/packets > 8000) {
2903                                 retval = bulk_latency;
2904                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2905                                 retval = bulk_latency;
2906                         } else if ((packets > 35)) {
2907                                 retval = lowest_latency;
2908                         }
2909                 } else if (bytes/packets > 2000) {
2910                         retval = bulk_latency;
2911                 } else if (packets <= 2 && bytes < 512) {
2912                         retval = lowest_latency;
2913                 }
2914                 break;
2915         case bulk_latency: /* 250 usec aka 4000 ints/s */
2916                 if (bytes > 25000) {
2917                         if (packets > 35)
2918                                 retval = low_latency;
2919                 } else if (bytes < 1500) {
2920                         retval = low_latency;
2921                 }
2922                 break;
2923         }
2924
2925 update_itr_done:
2926         return retval;
2927 }
2928
2929 static void igb_set_itr(struct igb_adapter *adapter)
2930 {
2931         u16 current_itr;
2932         u32 new_itr = adapter->itr;
2933
2934         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2935         if (adapter->link_speed != SPEED_1000) {
2936                 current_itr = 0;
2937                 new_itr = 4000;
2938                 goto set_itr_now;
2939         }
2940
2941         adapter->rx_itr = igb_update_itr(adapter,
2942                                     adapter->rx_itr,
2943                                     adapter->rx_ring->total_packets,
2944                                     adapter->rx_ring->total_bytes);
2945
2946         if (adapter->rx_ring->buddy) {
2947                 adapter->tx_itr = igb_update_itr(adapter,
2948                                             adapter->tx_itr,
2949                                             adapter->tx_ring->total_packets,
2950                                             adapter->tx_ring->total_bytes);
2951                 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2952         } else {
2953                 current_itr = adapter->rx_itr;
2954         }
2955
2956         /* conservative mode (itr 3) eliminates the lowest_latency setting */
2957         if (adapter->itr_setting == 3 && current_itr == lowest_latency)
2958                 current_itr = low_latency;
2959
2960         switch (current_itr) {
2961         /* counts and packets in update_itr are dependent on these numbers */
2962         case lowest_latency:
2963                 new_itr = 56;  /* aka 70,000 ints/sec */
2964                 break;
2965         case low_latency:
2966                 new_itr = 196; /* aka 20,000 ints/sec */
2967                 break;
2968         case bulk_latency:
2969                 new_itr = 980; /* aka 4,000 ints/sec */
2970                 break;
2971         default:
2972                 break;
2973         }
2974
2975 set_itr_now:
2976         adapter->rx_ring->total_bytes = 0;
2977         adapter->rx_ring->total_packets = 0;
2978         if (adapter->rx_ring->buddy) {
2979                 adapter->rx_ring->buddy->total_bytes = 0;
2980                 adapter->rx_ring->buddy->total_packets = 0;
2981         }
2982
2983         if (new_itr != adapter->itr) {
2984                 /* this attempts to bias the interrupt rate towards Bulk
2985                  * by adding intermediate steps when interrupt rate is
2986                  * increasing */
2987                 new_itr = new_itr > adapter->itr ?
2988                              max((new_itr * adapter->itr) /
2989                                  (new_itr + (adapter->itr >> 2)), new_itr) :
2990                              new_itr;
2991                 /* Don't write the value here; it resets the adapter's
2992                  * internal timer, and causes us to delay far longer than
2993                  * we should between interrupts.  Instead, we write the ITR
2994                  * value at the beginning of the next interrupt so the timing
2995                  * ends up being correct.
2996                  */
2997                 adapter->itr = new_itr;
2998                 adapter->rx_ring->itr_val = new_itr;
2999                 adapter->rx_ring->set_itr = 1;
3000         }
3001
3002         return;
3003 }
3004
3005
3006 #define IGB_TX_FLAGS_CSUM               0x00000001
3007 #define IGB_TX_FLAGS_VLAN               0x00000002
3008 #define IGB_TX_FLAGS_TSO                0x00000004
3009 #define IGB_TX_FLAGS_IPV4               0x00000008
3010 #define IGB_TX_FLAGS_TSTAMP             0x00000010
3011 #define IGB_TX_FLAGS_VLAN_MASK  0xffff0000
3012 #define IGB_TX_FLAGS_VLAN_SHIFT 16
3013
3014 static inline int igb_tso_adv(struct igb_adapter *adapter,
3015                               struct igb_ring *tx_ring,
3016                               struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
3017 {
3018         struct e1000_adv_tx_context_desc *context_desc;
3019         unsigned int i;
3020         int err;
3021         struct igb_buffer *buffer_info;
3022         u32 info = 0, tu_cmd = 0;
3023         u32 mss_l4len_idx, l4len;
3024         *hdr_len = 0;
3025
3026         if (skb_header_cloned(skb)) {
3027                 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3028                 if (err)
3029                         return err;
3030         }
3031
3032         l4len = tcp_hdrlen(skb);
3033         *hdr_len += l4len;
3034
3035         if (skb->protocol == htons(ETH_P_IP)) {
3036                 struct iphdr *iph = ip_hdr(skb);
3037                 iph->tot_len = 0;
3038                 iph->check = 0;
3039                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3040                                                          iph->daddr, 0,
3041                                                          IPPROTO_TCP,
3042                                                          0);
3043         } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3044                 ipv6_hdr(skb)->payload_len = 0;
3045                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3046                                                        &ipv6_hdr(skb)->daddr,
3047                                                        0, IPPROTO_TCP, 0);
3048         }
3049
3050         i = tx_ring->next_to_use;
3051
3052         buffer_info = &tx_ring->buffer_info[i];
3053         context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3054         /* VLAN MACLEN IPLEN */
3055         if (tx_flags & IGB_TX_FLAGS_VLAN)
3056                 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3057         info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3058         *hdr_len += skb_network_offset(skb);
3059         info |= skb_network_header_len(skb);
3060         *hdr_len += skb_network_header_len(skb);
3061         context_desc->vlan_macip_lens = cpu_to_le32(info);
3062
3063         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3064         tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3065
3066         if (skb->protocol == htons(ETH_P_IP))
3067                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3068         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3069
3070         context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3071
3072         /* MSS L4LEN IDX */
3073         mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
3074         mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
3075
3076         /* For 82575, context index must be unique per ring. */
3077         if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3078                 mss_l4len_idx |= tx_ring->queue_index << 4;
3079
3080         context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3081         context_desc->seqnum_seed = 0;
3082
3083         buffer_info->time_stamp = jiffies;
3084         buffer_info->next_to_watch = i;
3085         buffer_info->dma = 0;
3086         i++;
3087         if (i == tx_ring->count)
3088                 i = 0;
3089
3090         tx_ring->next_to_use = i;
3091
3092         return true;
3093 }
3094
3095 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
3096                                         struct igb_ring *tx_ring,
3097                                         struct sk_buff *skb, u32 tx_flags)
3098 {
3099         struct e1000_adv_tx_context_desc *context_desc;
3100         unsigned int i;
3101         struct igb_buffer *buffer_info;
3102         u32 info = 0, tu_cmd = 0;
3103
3104         if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
3105             (tx_flags & IGB_TX_FLAGS_VLAN)) {
3106                 i = tx_ring->next_to_use;
3107                 buffer_info = &tx_ring->buffer_info[i];
3108                 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
3109
3110                 if (tx_flags & IGB_TX_FLAGS_VLAN)
3111                         info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
3112                 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
3113                 if (skb->ip_summed == CHECKSUM_PARTIAL)
3114                         info |= skb_network_header_len(skb);
3115
3116                 context_desc->vlan_macip_lens = cpu_to_le32(info);
3117
3118                 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
3119
3120                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3121                         __be16 protocol;
3122
3123                         if (skb->protocol == cpu_to_be16(ETH_P_8021Q)) {
3124                                 const struct vlan_ethhdr *vhdr =
3125                                           (const struct vlan_ethhdr*)skb->data;
3126
3127                                 protocol = vhdr->h_vlan_encapsulated_proto;
3128                         } else {
3129                                 protocol = skb->protocol;
3130                         }
3131
3132                         switch (protocol) {
3133                         case cpu_to_be16(ETH_P_IP):
3134                                 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
3135                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3136                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3137                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
3138                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3139                                 break;
3140                         case cpu_to_be16(ETH_P_IPV6):
3141                                 /* XXX what about other V6 headers?? */
3142                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3143                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
3144                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
3145                                         tu_cmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
3146                                 break;
3147                         default:
3148                                 if (unlikely(net_ratelimit()))
3149                                         dev_warn(&adapter->pdev->dev,
3150                                             "partial checksum but proto=%x!\n",
3151                                             skb->protocol);
3152                                 break;
3153                         }
3154                 }
3155
3156                 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
3157                 context_desc->seqnum_seed = 0;
3158                 if (adapter->flags & IGB_FLAG_NEED_CTX_IDX)
3159                         context_desc->mss_l4len_idx =
3160                                 cpu_to_le32(tx_ring->queue_index << 4);
3161                 else
3162                         context_desc->mss_l4len_idx = 0;
3163
3164                 buffer_info->time_stamp = jiffies;
3165                 buffer_info->next_to_watch = i;
3166                 buffer_info->dma = 0;
3167
3168                 i++;
3169                 if (i == tx_ring->count)
3170                         i = 0;
3171                 tx_ring->next_to_use = i;
3172
3173                 return true;
3174         }
3175         return false;
3176 }
3177
3178 #define IGB_MAX_TXD_PWR 16
3179 #define IGB_MAX_DATA_PER_TXD    (1<<IGB_MAX_TXD_PWR)
3180
3181 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
3182                                  struct igb_ring *tx_ring, struct sk_buff *skb,
3183                                  unsigned int first)
3184 {
3185         struct igb_buffer *buffer_info;
3186         unsigned int len = skb_headlen(skb);
3187         unsigned int count = 0, i;
3188         unsigned int f;
3189         dma_addr_t *map;
3190
3191         i = tx_ring->next_to_use;
3192
3193         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
3194                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
3195                 return 0;
3196         }
3197
3198         map = skb_shinfo(skb)->dma_maps;
3199
3200         buffer_info = &tx_ring->buffer_info[i];
3201         BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3202         buffer_info->length = len;
3203         /* set time_stamp *before* dma to help avoid a possible race */
3204         buffer_info->time_stamp = jiffies;
3205         buffer_info->next_to_watch = i;
3206         buffer_info->dma = skb_shinfo(skb)->dma_head;
3207
3208         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
3209                 struct skb_frag_struct *frag;
3210
3211                 i++;
3212                 if (i == tx_ring->count)
3213                         i = 0;
3214
3215                 frag = &skb_shinfo(skb)->frags[f];
3216                 len = frag->size;
3217
3218                 buffer_info = &tx_ring->buffer_info[i];
3219                 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
3220                 buffer_info->length = len;
3221                 buffer_info->time_stamp = jiffies;
3222                 buffer_info->next_to_watch = i;
3223                 buffer_info->dma = map[count];
3224                 count++;
3225         }
3226
3227         tx_ring->buffer_info[i].skb = skb;
3228         tx_ring->buffer_info[first].next_to_watch = i;
3229
3230         return count + 1;
3231 }
3232
3233 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
3234                                     struct igb_ring *tx_ring,
3235                                     int tx_flags, int count, u32 paylen,
3236                                     u8 hdr_len)
3237 {
3238         union e1000_adv_tx_desc *tx_desc = NULL;
3239         struct igb_buffer *buffer_info;
3240         u32 olinfo_status = 0, cmd_type_len;
3241         unsigned int i;
3242
3243         cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
3244                         E1000_ADVTXD_DCMD_DEXT);
3245
3246         if (tx_flags & IGB_TX_FLAGS_VLAN)
3247                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3248
3249         if (tx_flags & IGB_TX_FLAGS_TSTAMP)
3250                 cmd_type_len |= E1000_ADVTXD_MAC_TSTAMP;
3251
3252         if (tx_flags & IGB_TX_FLAGS_TSO) {
3253                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3254
3255                 /* insert tcp checksum */
3256                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3257
3258                 /* insert ip checksum */
3259                 if (tx_flags & IGB_TX_FLAGS_IPV4)
3260                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3261
3262         } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
3263                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3264         }
3265
3266         if ((adapter->flags & IGB_FLAG_NEED_CTX_IDX) &&
3267             (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
3268                          IGB_TX_FLAGS_VLAN)))
3269                 olinfo_status |= tx_ring->queue_index << 4;
3270
3271         olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
3272
3273         i = tx_ring->next_to_use;
3274         while (count--) {
3275                 buffer_info = &tx_ring->buffer_info[i];
3276                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
3277                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
3278                 tx_desc->read.cmd_type_len =
3279                         cpu_to_le32(cmd_type_len | buffer_info->length);
3280                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3281                 i++;
3282                 if (i == tx_ring->count)
3283                         i = 0;
3284         }
3285
3286         tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
3287         /* Force memory writes to complete before letting h/w
3288          * know there are new descriptors to fetch.  (Only
3289          * applicable for weak-ordered memory model archs,
3290          * such as IA-64). */
3291         wmb();
3292
3293         tx_ring->next_to_use = i;
3294         writel(i, adapter->hw.hw_addr + tx_ring->tail);
3295         /* we need this if more than one processor can write to our tail
3296          * at a time, it syncronizes IO on IA64/Altix systems */
3297         mmiowb();
3298 }
3299
3300 static int __igb_maybe_stop_tx(struct net_device *netdev,
3301                                struct igb_ring *tx_ring, int size)
3302 {
3303         struct igb_adapter *adapter = netdev_priv(netdev);
3304
3305         netif_stop_subqueue(netdev, tx_ring->queue_index);
3306
3307         /* Herbert's original patch had:
3308          *  smp_mb__after_netif_stop_queue();
3309          * but since that doesn't exist yet, just open code it. */
3310         smp_mb();
3311
3312         /* We need to check again in a case another CPU has just
3313          * made room available. */
3314         if (igb_desc_unused(tx_ring) < size)
3315                 return -EBUSY;
3316
3317         /* A reprieve! */
3318         netif_wake_subqueue(netdev, tx_ring->queue_index);
3319         ++adapter->restart_queue;
3320         return 0;
3321 }
3322
3323 static int igb_maybe_stop_tx(struct net_device *netdev,
3324                              struct igb_ring *tx_ring, int size)
3325 {
3326         if (igb_desc_unused(tx_ring) >= size)
3327                 return 0;
3328         return __igb_maybe_stop_tx(netdev, tx_ring, size);
3329 }
3330
3331 static netdev_tx_t igb_xmit_frame_ring_adv(struct sk_buff *skb,
3332                                            struct net_device *netdev,
3333                                            struct igb_ring *tx_ring)
3334 {
3335         struct igb_adapter *adapter = netdev_priv(netdev);
3336         unsigned int first;
3337         unsigned int tx_flags = 0;
3338         u8 hdr_len = 0;
3339         int count = 0;
3340         int tso = 0;
3341         union skb_shared_tx *shtx;
3342
3343         if (test_bit(__IGB_DOWN, &adapter->state)) {
3344                 dev_kfree_skb_any(skb);
3345                 return NETDEV_TX_OK;
3346         }
3347
3348         if (skb->len <= 0) {
3349                 dev_kfree_skb_any(skb);
3350                 return NETDEV_TX_OK;
3351         }
3352
3353         /* need: 1 descriptor per page,
3354          *       + 2 desc gap to keep tail from touching head,
3355          *       + 1 desc for skb->data,
3356          *       + 1 desc for context descriptor,
3357          * otherwise try next time */
3358         if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
3359                 /* this is a hard error */
3360                 return NETDEV_TX_BUSY;
3361         }
3362
3363         /*
3364          * TODO: check that there currently is no other packet with
3365          * time stamping in the queue
3366          *
3367          * When doing time stamping, keep the connection to the socket
3368          * a while longer: it is still needed by skb_hwtstamp_tx(),
3369          * called either in igb_tx_hwtstamp() or by our caller when
3370          * doing software time stamping.
3371          */
3372         shtx = skb_tx(skb);
3373         if (unlikely(shtx->hardware)) {
3374                 shtx->in_progress = 1;
3375                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
3376         }
3377
3378         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3379                 tx_flags |= IGB_TX_FLAGS_VLAN;
3380                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
3381         }
3382
3383         if (skb->protocol == htons(ETH_P_IP))
3384                 tx_flags |= IGB_TX_FLAGS_IPV4;
3385
3386         first = tx_ring->next_to_use;
3387         tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
3388                                               &hdr_len) : 0;
3389
3390         if (tso < 0) {
3391                 dev_kfree_skb_any(skb);
3392                 return NETDEV_TX_OK;
3393         }
3394
3395         if (tso)
3396                 tx_flags |= IGB_TX_FLAGS_TSO;
3397         else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags) &&
3398                  (skb->ip_summed == CHECKSUM_PARTIAL))
3399                 tx_flags |= IGB_TX_FLAGS_CSUM;
3400
3401         /*
3402          * count reflects descriptors mapped, if 0 then mapping error
3403          * has occured and we need to rewind the descriptor queue
3404          */
3405         count = igb_tx_map_adv(adapter, tx_ring, skb, first);
3406
3407         if (count) {
3408                 igb_tx_queue_adv(adapter, tx_ring, tx_flags, count,
3409                                  skb->len, hdr_len);
3410                 /* Make sure there is space in the ring for the next send. */
3411                 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
3412         } else {
3413                 dev_kfree_skb_any(skb);
3414                 tx_ring->buffer_info[first].time_stamp = 0;
3415                 tx_ring->next_to_use = first;
3416         }
3417
3418         return NETDEV_TX_OK;
3419 }
3420
3421 static netdev_tx_t igb_xmit_frame_adv(struct sk_buff *skb,
3422                                       struct net_device *netdev)
3423 {
3424         struct igb_adapter *adapter = netdev_priv(netdev);
3425         struct igb_ring *tx_ring;
3426
3427         int r_idx = 0;
3428         r_idx = skb->queue_mapping & (IGB_ABS_MAX_TX_QUEUES - 1);
3429         tx_ring = adapter->multi_tx_table[r_idx];
3430
3431         /* This goes back to the question of how to logically map a tx queue
3432          * to a flow.  Right now, performance is impacted slightly negatively
3433          * if using multiple tx queues.  If the stack breaks away from a
3434          * single qdisc implementation, we can look at this again. */
3435         return igb_xmit_frame_ring_adv(skb, netdev, tx_ring);
3436 }
3437
3438 /**
3439  * igb_tx_timeout - Respond to a Tx Hang
3440  * @netdev: network interface device structure
3441  **/
3442 static void igb_tx_timeout(struct net_device *netdev)
3443 {
3444         struct igb_adapter *adapter = netdev_priv(netdev);
3445         struct e1000_hw *hw = &adapter->hw;
3446
3447         /* Do the reset outside of interrupt context */
3448         adapter->tx_timeout_count++;
3449         schedule_work(&adapter->reset_task);
3450         wr32(E1000_EICS,
3451              (adapter->eims_enable_mask & ~adapter->eims_other));
3452 }
3453
3454 static void igb_reset_task(struct work_struct *work)
3455 {
3456         struct igb_adapter *adapter;
3457         adapter = container_of(work, struct igb_adapter, reset_task);
3458
3459         igb_reinit_locked(adapter);
3460 }
3461
3462 /**
3463  * igb_get_stats - Get System Network Statistics
3464  * @netdev: network interface device structure
3465  *
3466  * Returns the address of the device statistics structure.
3467  * The statistics are actually updated from the timer callback.
3468  **/
3469 static struct net_device_stats *igb_get_stats(struct net_device *netdev)
3470 {
3471         struct igb_adapter *adapter = netdev_priv(netdev);
3472
3473         /* only return the current stats */
3474         return &adapter->net_stats;
3475 }
3476
3477 /**
3478  * igb_change_mtu - Change the Maximum Transfer Unit
3479  * @netdev: network interface device structure
3480  * @new_mtu: new value for maximum frame size
3481  *
3482  * Returns 0 on success, negative on failure
3483  **/
3484 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
3485 {
3486         struct igb_adapter *adapter = netdev_priv(netdev);
3487         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
3488
3489         if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
3490             (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3491                 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
3492                 return -EINVAL;
3493         }
3494
3495         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3496                 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
3497                 return -EINVAL;
3498         }
3499
3500         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
3501                 msleep(1);
3502
3503         /* igb_down has a dependency on max_frame_size */
3504         adapter->max_frame_size = max_frame;
3505         if (netif_running(netdev))
3506                 igb_down(adapter);
3507
3508         /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
3509          * means we reserve 2 more, this pushes us to allocate from the next
3510          * larger slab size.
3511          * i.e. RXBUFFER_2048 --> size-4096 slab
3512          */
3513
3514         if (max_frame <= IGB_RXBUFFER_256)
3515                 adapter->rx_buffer_len = IGB_RXBUFFER_256;
3516         else if (max_frame <= IGB_RXBUFFER_512)
3517                 adapter->rx_buffer_len = IGB_RXBUFFER_512;
3518         else if (max_frame <= IGB_RXBUFFER_1024)
3519                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3520         else if (max_frame <= IGB_RXBUFFER_2048)
3521                 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
3522         else
3523 #if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3524                 adapter->rx_buffer_len = IGB_RXBUFFER_16384;
3525 #else
3526                 adapter->rx_buffer_len = PAGE_SIZE / 2;
3527 #endif
3528
3529         /* if sr-iov is enabled we need to force buffer size to 1K or larger */
3530         if (adapter->vfs_allocated_count &&
3531             (adapter->rx_buffer_len < IGB_RXBUFFER_1024))
3532                 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
3533
3534         /* adjust allocation if LPE protects us, and we aren't using SBP */
3535         if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
3536              (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
3537                 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3538
3539         dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
3540                  netdev->mtu, new_mtu);
3541         netdev->mtu = new_mtu;
3542
3543         if (netif_running(netdev))
3544                 igb_up(adapter);
3545         else
3546                 igb_reset(adapter);
3547
3548         clear_bit(__IGB_RESETTING, &adapter->state);
3549
3550         return 0;
3551 }
3552
3553 /**
3554  * igb_update_stats - Update the board statistics counters
3555  * @adapter: board private structure
3556  **/
3557
3558 void igb_update_stats(struct igb_adapter *adapter)
3559 {
3560         struct e1000_hw *hw = &adapter->hw;
3561         struct pci_dev *pdev = adapter->pdev;
3562         u16 phy_tmp;
3563
3564 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3565
3566         /*
3567          * Prevent stats update while adapter is being reset, or if the pci
3568          * connection is down.
3569          */
3570         if (adapter->link_speed == 0)
3571                 return;
3572         if (pci_channel_offline(pdev))
3573                 return;
3574
3575         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
3576         adapter->stats.gprc += rd32(E1000_GPRC);
3577         adapter->stats.gorc += rd32(E1000_GORCL);
3578         rd32(E1000_GORCH); /* clear GORCL */
3579         adapter->stats.bprc += rd32(E1000_BPRC);
3580         adapter->stats.mprc += rd32(E1000_MPRC);
3581         adapter->stats.roc += rd32(E1000_ROC);
3582
3583         adapter->stats.prc64 += rd32(E1000_PRC64);
3584         adapter->stats.prc127 += rd32(E1000_PRC127);
3585         adapter->stats.prc255 += rd32(E1000_PRC255);
3586         adapter->stats.prc511 += rd32(E1000_PRC511);
3587         adapter->stats.prc1023 += rd32(E1000_PRC1023);
3588         adapter->stats.prc1522 += rd32(E1000_PRC1522);
3589         adapter->stats.symerrs += rd32(E1000_SYMERRS);
3590         adapter->stats.sec += rd32(E1000_SEC);
3591
3592         adapter->stats.mpc += rd32(E1000_MPC);
3593         adapter->stats.scc += rd32(E1000_SCC);
3594         adapter->stats.ecol += rd32(E1000_ECOL);
3595         adapter->stats.mcc += rd32(E1000_MCC);
3596         adapter->stats.latecol += rd32(E1000_LATECOL);
3597         adapter->stats.dc += rd32(E1000_DC);
3598         adapter->stats.rlec += rd32(E1000_RLEC);
3599         adapter->stats.xonrxc += rd32(E1000_XONRXC);
3600         adapter->stats.xontxc += rd32(E1000_XONTXC);
3601         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
3602         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
3603         adapter->stats.fcruc += rd32(E1000_FCRUC);
3604         adapter->stats.gptc += rd32(E1000_GPTC);
3605         adapter->stats.gotc += rd32(E1000_GOTCL);
3606         rd32(E1000_GOTCH); /* clear GOTCL */
3607         adapter->stats.rnbc += rd32(E1000_RNBC);
3608         adapter->stats.ruc += rd32(E1000_RUC);
3609         adapter->stats.rfc += rd32(E1000_RFC);
3610         adapter->stats.rjc += rd32(E1000_RJC);
3611         adapter->stats.tor += rd32(E1000_TORH);
3612         adapter->stats.tot += rd32(E1000_TOTH);
3613         adapter->stats.tpr += rd32(E1000_TPR);
3614
3615         adapter->stats.ptc64 += rd32(E1000_PTC64);
3616         adapter->stats.ptc127 += rd32(E1000_PTC127);
3617         adapter->stats.ptc255 += rd32(E1000_PTC255);
3618         adapter->stats.ptc511 += rd32(E1000_PTC511);
3619         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
3620         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
3621
3622         adapter->stats.mptc += rd32(E1000_MPTC);
3623         adapter->stats.bptc += rd32(E1000_BPTC);
3624
3625         /* used for adaptive IFS */
3626
3627         hw->mac.tx_packet_delta = rd32(E1000_TPT);
3628         adapter->stats.tpt += hw->mac.tx_packet_delta;
3629         hw->mac.collision_delta = rd32(E1000_COLC);
3630         adapter->stats.colc += hw->mac.collision_delta;
3631
3632         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
3633         adapter->stats.rxerrc += rd32(E1000_RXERRC);
3634         adapter->stats.tncrs += rd32(E1000_TNCRS);
3635         adapter->stats.tsctc += rd32(E1000_TSCTC);
3636         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
3637
3638         adapter->stats.iac += rd32(E1000_IAC);
3639         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
3640         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
3641         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
3642         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
3643         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
3644         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
3645         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
3646         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
3647
3648         /* Fill out the OS statistics structure */
3649         adapter->net_stats.multicast = adapter->stats.mprc;
3650         adapter->net_stats.collisions = adapter->stats.colc;
3651
3652         /* Rx Errors */
3653
3654         if (hw->mac.type != e1000_82575) {
3655                 u32 rqdpc_tmp;
3656                 u64 rqdpc_total = 0;
3657                 int i;
3658                 /* Read out drops stats per RX queue.  Notice RQDPC (Receive
3659                  * Queue Drop Packet Count) stats only gets incremented, if
3660                  * the DROP_EN but it set (in the SRRCTL register for that
3661                  * queue).  If DROP_EN bit is NOT set, then the some what
3662                  * equivalent count is stored in RNBC (not per queue basis).
3663                  * Also note the drop count is due to lack of available
3664                  * descriptors.
3665                  */
3666                 for (i = 0; i < adapter->num_rx_queues; i++) {
3667                         rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0xFFF;
3668                         adapter->rx_ring[i].rx_stats.drops += rqdpc_tmp;
3669                         rqdpc_total += adapter->rx_ring[i].rx_stats.drops;
3670                 }
3671                 adapter->net_stats.rx_fifo_errors = rqdpc_total;
3672         }
3673
3674         /* Note RNBC (Receive No Buffers Count) is an not an exact
3675          * drop count as the hardware FIFO might save the day.  Thats
3676          * one of the reason for saving it in rx_fifo_errors, as its
3677          * potentially not a true drop.
3678          */
3679         adapter->net_stats.rx_fifo_errors += adapter->stats.rnbc;
3680
3681         /* RLEC on some newer hardware can be incorrect so build
3682          * our own version based on RUC and ROC */
3683         adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3684                 adapter->stats.crcerrs + adapter->stats.algnerrc +
3685                 adapter->stats.ruc + adapter->stats.roc +
3686                 adapter->stats.cexterr;
3687         adapter->net_stats.rx_length_errors = adapter->stats.ruc +
3688                                               adapter->stats.roc;
3689         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3690         adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3691         adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3692
3693         /* Tx Errors */
3694         adapter->net_stats.tx_errors = adapter->stats.ecol +
3695                                        adapter->stats.latecol;
3696         adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3697         adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3698         adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3699
3700         /* Tx Dropped needs to be maintained elsewhere */
3701
3702         /* Phy Stats */
3703         if (hw->phy.media_type == e1000_media_type_copper) {
3704                 if ((adapter->link_speed == SPEED_1000) &&
3705                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3706                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3707                         adapter->phy_stats.idle_errors += phy_tmp;
3708                 }
3709         }
3710
3711         /* Management Stats */
3712         adapter->stats.mgptc += rd32(E1000_MGTPTC);
3713         adapter->stats.mgprc += rd32(E1000_MGTPRC);
3714         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3715 }
3716
3717 static irqreturn_t igb_msix_other(int irq, void *data)
3718 {
3719         struct net_device *netdev = data;
3720         struct igb_adapter *adapter = netdev_priv(netdev);
3721         struct e1000_hw *hw = &adapter->hw;
3722         u32 icr = rd32(E1000_ICR);
3723
3724         /* reading ICR causes bit 31 of EICR to be cleared */
3725
3726         if(icr & E1000_ICR_DOUTSYNC) {
3727                 /* HW is reporting DMA is out of sync */
3728                 adapter->stats.doosync++;
3729         }
3730
3731         /* Check for a mailbox event */
3732         if (icr & E1000_ICR_VMMB)
3733                 igb_msg_task(adapter);
3734
3735         if (icr & E1000_ICR_LSC) {
3736                 hw->mac.get_link_status = 1;
3737                 /* guard against interrupt when we're going down */
3738                 if (!test_bit(__IGB_DOWN, &adapter->state))
3739                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
3740         }
3741
3742         wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_VMMB);
3743         wr32(E1000_EIMS, adapter->eims_other);
3744
3745         return IRQ_HANDLED;
3746 }
3747
3748 static irqreturn_t igb_msix_tx(int irq, void *data)
3749 {
3750         struct igb_ring *tx_ring = data;
3751         struct igb_adapter *adapter = tx_ring->adapter;
3752         struct e1000_hw *hw = &adapter->hw;
3753
3754 #ifdef CONFIG_IGB_DCA
3755         if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3756                 igb_update_tx_dca(tx_ring);
3757 #endif
3758
3759         tx_ring->total_bytes = 0;
3760         tx_ring->total_packets = 0;
3761
3762         /* auto mask will automatically reenable the interrupt when we write
3763          * EICS */
3764         if (!igb_clean_tx_irq(tx_ring))
3765                 /* Ring was not completely cleaned, so fire another interrupt */
3766                 wr32(E1000_EICS, tx_ring->eims_value);
3767         else
3768                 wr32(E1000_EIMS, tx_ring->eims_value);
3769
3770         return IRQ_HANDLED;
3771 }
3772
3773 static void igb_write_itr(struct igb_ring *ring)
3774 {
3775         struct e1000_hw *hw = &ring->adapter->hw;
3776         if ((ring->adapter->itr_setting & 3) && ring->set_itr) {
3777                 switch (hw->mac.type) {
3778                 case e1000_82576:
3779                         wr32(ring->itr_register, ring->itr_val |
3780                              0x80000000);
3781                         break;
3782                 default:
3783                         wr32(ring->itr_register, ring->itr_val |
3784                              (ring->itr_val << 16));
3785                         break;
3786                 }
3787                 ring->set_itr = 0;
3788         }
3789 }
3790
3791 static irqreturn_t igb_msix_rx(int irq, void *data)
3792 {
3793         struct igb_ring *rx_ring = data;
3794
3795         /* Write the ITR value calculated at the end of the
3796          * previous interrupt.
3797          */
3798
3799         igb_write_itr(rx_ring);
3800
3801         if (napi_schedule_prep(&rx_ring->napi))
3802                 __napi_schedule(&rx_ring->napi);
3803
3804 #ifdef CONFIG_IGB_DCA
3805         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
3806                 igb_update_rx_dca(rx_ring);
3807 #endif
3808                 return IRQ_HANDLED;
3809 }
3810
3811 #ifdef CONFIG_IGB_DCA
3812 static void igb_update_rx_dca(struct igb_ring *rx_ring)
3813 {
3814         u32 dca_rxctrl;
3815         struct igb_adapter *adapter = rx_ring->adapter;
3816         struct e1000_hw *hw = &adapter->hw;
3817         int cpu = get_cpu();
3818         int q = rx_ring->reg_idx;
3819
3820         if (rx_ring->cpu != cpu) {
3821                 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
3822                 if (hw->mac.type == e1000_82576) {
3823                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
3824                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3825                                       E1000_DCA_RXCTRL_CPUID_SHIFT;
3826                 } else {
3827                         dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
3828                         dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3829                 }
3830                 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
3831                 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
3832                 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
3833                 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
3834                 rx_ring->cpu = cpu;
3835         }
3836         put_cpu();
3837 }
3838
3839 static void igb_update_tx_dca(struct igb_ring *tx_ring)
3840 {
3841         u32 dca_txctrl;
3842         struct igb_adapter *adapter = tx_ring->adapter;
3843         struct e1000_hw *hw = &adapter->hw;
3844         int cpu = get_cpu();
3845         int q = tx_ring->reg_idx;
3846
3847         if (tx_ring->cpu != cpu) {
3848                 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
3849                 if (hw->mac.type == e1000_82576) {
3850                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
3851                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
3852                                       E1000_DCA_TXCTRL_CPUID_SHIFT;
3853                 } else {
3854                         dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
3855                         dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
3856                 }
3857                 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
3858                 wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
3859                 tx_ring->cpu = cpu;
3860         }
3861         put_cpu();
3862 }
3863
3864 static void igb_setup_dca(struct igb_adapter *adapter)
3865 {
3866         struct e1000_hw *hw = &adapter->hw;
3867         int i;
3868
3869         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
3870                 return;
3871
3872         /* Always use CB2 mode, difference is masked in the CB driver. */
3873         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3874
3875         for (i = 0; i < adapter->num_tx_queues; i++) {
3876                 adapter->tx_ring[i].cpu = -1;
3877                 igb_update_tx_dca(&adapter->tx_ring[i]);
3878         }
3879         for (i = 0; i < adapter->num_rx_queues; i++) {
3880                 adapter->rx_ring[i].cpu = -1;
3881                 igb_update_rx_dca(&adapter->rx_ring[i]);
3882         }
3883 }
3884
3885 static int __igb_notify_dca(struct device *dev, void *data)
3886 {
3887         struct net_device *netdev = dev_get_drvdata(dev);
3888         struct igb_adapter *adapter = netdev_priv(netdev);
3889         struct e1000_hw *hw = &adapter->hw;
3890         unsigned long event = *(unsigned long *)data;
3891
3892         switch (event) {
3893         case DCA_PROVIDER_ADD:
3894                 /* if already enabled, don't do it again */
3895                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
3896                         break;
3897                 /* Always use CB2 mode, difference is masked
3898                  * in the CB driver. */
3899                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
3900                 if (dca_add_requester(dev) == 0) {
3901                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
3902                         dev_info(&adapter->pdev->dev, "DCA enabled\n");
3903                         igb_setup_dca(adapter);
3904                         break;
3905                 }
3906                 /* Fall Through since DCA is disabled. */
3907         case DCA_PROVIDER_REMOVE:
3908                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3909                         /* without this a class_device is left
3910                          * hanging around in the sysfs model */
3911                         dca_remove_requester(dev);
3912                         dev_info(&adapter->pdev->dev, "DCA disabled\n");
3913                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3914                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3915                 }
3916                 break;
3917         }
3918
3919         return 0;
3920 }
3921
3922 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
3923                           void *p)
3924 {
3925         int ret_val;
3926
3927         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
3928                                          __igb_notify_dca);
3929
3930         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
3931 }
3932 #endif /* CONFIG_IGB_DCA */
3933
3934 static void igb_ping_all_vfs(struct igb_adapter *adapter)
3935 {
3936         struct e1000_hw *hw = &adapter->hw;
3937         u32 ping;
3938         int i;
3939
3940         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
3941                 ping = E1000_PF_CONTROL_MSG;
3942                 if (adapter->vf_data[i].clear_to_send)
3943                         ping |= E1000_VT_MSGTYPE_CTS;
3944                 igb_write_mbx(hw, &ping, 1, i);
3945         }
3946 }
3947
3948 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
3949                                   u32 *msgbuf, u32 vf)
3950 {
3951         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
3952         u16 *hash_list = (u16 *)&msgbuf[1];
3953         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
3954         int i;
3955
3956         /* only up to 30 hash values supported */
3957         if (n > 30)
3958                 n = 30;
3959
3960         /* salt away the number of multi cast addresses assigned
3961          * to this VF for later use to restore when the PF multi cast
3962          * list changes
3963          */
3964         vf_data->num_vf_mc_hashes = n;
3965
3966         /* VFs are limited to using the MTA hash table for their multicast
3967          * addresses */
3968         for (i = 0; i < n; i++)
3969                 vf_data->vf_mc_hashes[i] = hash_list[i];
3970
3971         /* Flush and reset the mta with the new values */
3972         igb_set_rx_mode(adapter->netdev);
3973
3974         return 0;
3975 }
3976
3977 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
3978 {
3979         struct e1000_hw *hw = &adapter->hw;
3980         struct vf_data_storage *vf_data;
3981         int i, j;
3982
3983         for (i = 0; i < adapter->vfs_allocated_count; i++) {
3984                 vf_data = &adapter->vf_data[i];
3985                 for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
3986                         igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
3987         }
3988 }
3989
3990 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
3991 {
3992         struct e1000_hw *hw = &adapter->hw;
3993         u32 pool_mask, reg, vid;
3994         int i;
3995
3996         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
3997
3998         /* Find the vlan filter for this id */
3999         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4000                 reg = rd32(E1000_VLVF(i));
4001
4002                 /* remove the vf from the pool */
4003                 reg &= ~pool_mask;
4004
4005                 /* if pool is empty then remove entry from vfta */
4006                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
4007                     (reg & E1000_VLVF_VLANID_ENABLE)) {
4008                         reg = 0;
4009                         vid = reg & E1000_VLVF_VLANID_MASK;
4010                         igb_vfta_set(hw, vid, false);
4011                 }
4012
4013                 wr32(E1000_VLVF(i), reg);
4014         }
4015
4016         adapter->vf_data[vf].vlans_enabled = 0;
4017 }
4018
4019 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
4020 {
4021         struct e1000_hw *hw = &adapter->hw;
4022         u32 reg, i;
4023
4024         /* It is an error to call this function when VFs are not enabled */
4025         if (!adapter->vfs_allocated_count)
4026                 return -1;
4027
4028         /* Find the vlan filter for this id */
4029         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4030                 reg = rd32(E1000_VLVF(i));
4031                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
4032                     vid == (reg & E1000_VLVF_VLANID_MASK))
4033                         break;
4034         }
4035
4036         if (add) {
4037                 if (i == E1000_VLVF_ARRAY_SIZE) {
4038                         /* Did not find a matching VLAN ID entry that was
4039                          * enabled.  Search for a free filter entry, i.e.
4040                          * one without the enable bit set
4041                          */
4042                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
4043                                 reg = rd32(E1000_VLVF(i));
4044                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
4045                                         break;
4046                         }
4047                 }
4048                 if (i < E1000_VLVF_ARRAY_SIZE) {
4049                         /* Found an enabled/available entry */
4050                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
4051
4052                         /* if !enabled we need to set this up in vfta */
4053                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
4054                                 /* add VID to filter table, if bit already set
4055                                  * PF must have added it outside of table */
4056                                 if (igb_vfta_set(hw, vid, true))
4057                                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT +
4058                                                 adapter->vfs_allocated_count);
4059                                 reg |= E1000_VLVF_VLANID_ENABLE;
4060                         }
4061                         reg &= ~E1000_VLVF_VLANID_MASK;
4062                         reg |= vid;
4063
4064                         wr32(E1000_VLVF(i), reg);
4065
4066                         /* do not modify RLPML for PF devices */
4067                         if (vf >= adapter->vfs_allocated_count)
4068                                 return 0;
4069
4070                         if (!adapter->vf_data[vf].vlans_enabled) {
4071                                 u32 size;
4072                                 reg = rd32(E1000_VMOLR(vf));
4073                                 size = reg & E1000_VMOLR_RLPML_MASK;
4074                                 size += 4;
4075                                 reg &= ~E1000_VMOLR_RLPML_MASK;
4076                                 reg |= size;
4077                                 wr32(E1000_VMOLR(vf), reg);
4078                         }
4079                         adapter->vf_data[vf].vlans_enabled++;
4080
4081                         return 0;
4082                 }
4083         } else {
4084                 if (i < E1000_VLVF_ARRAY_SIZE) {
4085                         /* remove vf from the pool */
4086                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
4087                         /* if pool is empty then remove entry from vfta */
4088                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
4089                                 reg = 0;
4090                                 igb_vfta_set(hw, vid, false);
4091                         }
4092                         wr32(E1000_VLVF(i), reg);
4093
4094                         /* do not modify RLPML for PF devices */
4095                         if (vf >= adapter->vfs_allocated_count)
4096                                 return 0;
4097
4098                         adapter->vf_data[vf].vlans_enabled--;
4099                         if (!adapter->vf_data[vf].vlans_enabled) {
4100                                 u32 size;
4101                                 reg = rd32(E1000_VMOLR(vf));
4102                                 size = reg & E1000_VMOLR_RLPML_MASK;
4103                                 size -= 4;
4104                                 reg &= ~E1000_VMOLR_RLPML_MASK;
4105                                 reg |= size;
4106                                 wr32(E1000_VMOLR(vf), reg);
4107                         }
4108                         return 0;
4109                 }
4110         }
4111         return -1;
4112 }
4113
4114 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
4115 {
4116         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
4117         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
4118
4119         return igb_vlvf_set(adapter, vid, add, vf);
4120 }
4121
4122 static inline void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
4123 {
4124         struct e1000_hw *hw = &adapter->hw;
4125
4126         /* disable mailbox functionality for vf */
4127         adapter->vf_data[vf].clear_to_send = false;
4128
4129         /* reset offloads to defaults */
4130         igb_set_vmolr(hw, vf);
4131
4132         /* reset vlans for device */
4133         igb_clear_vf_vfta(adapter, vf);
4134
4135         /* reset multicast table array for vf */
4136         adapter->vf_data[vf].num_vf_mc_hashes = 0;
4137
4138         /* Flush and reset the mta with the new values */
4139         igb_set_rx_mode(adapter->netdev);
4140 }
4141
4142 static inline void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
4143 {
4144         struct e1000_hw *hw = &adapter->hw;
4145         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
4146         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
4147         u32 reg, msgbuf[3];
4148         u8 *addr = (u8 *)(&msgbuf[1]);
4149
4150         /* process all the same items cleared in a function level reset */
4151         igb_vf_reset_event(adapter, vf);
4152
4153         /* set vf mac address */
4154         igb_rar_set(hw, vf_mac, rar_entry);
4155         igb_set_rah_pool(hw, vf, rar_entry);
4156
4157         /* enable transmit and receive for vf */
4158         reg = rd32(E1000_VFTE);
4159         wr32(E1000_VFTE, reg | (1 << vf));
4160         reg = rd32(E1000_VFRE);
4161         wr32(E1000_VFRE, reg | (1 << vf));
4162
4163         /* enable mailbox functionality for vf */
4164         adapter->vf_data[vf].clear_to_send = true;
4165
4166         /* reply to reset with ack and vf mac address */
4167         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
4168         memcpy(addr, vf_mac, 6);
4169         igb_write_mbx(hw, msgbuf, 3, vf);
4170 }
4171
4172 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
4173 {
4174                 unsigned char *addr = (char *)&msg[1];
4175                 int err = -1;
4176
4177                 if (is_valid_ether_addr(addr))
4178                         err = igb_set_vf_mac(adapter, vf, addr);
4179
4180                 return err;
4181
4182 }
4183
4184 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
4185 {
4186         struct e1000_hw *hw = &adapter->hw;
4187         u32 msg = E1000_VT_MSGTYPE_NACK;
4188
4189         /* if device isn't clear to send it shouldn't be reading either */
4190         if (!adapter->vf_data[vf].clear_to_send)
4191                 igb_write_mbx(hw, &msg, 1, vf);
4192 }
4193
4194
4195 static void igb_msg_task(struct igb_adapter *adapter)
4196 {
4197         struct e1000_hw *hw = &adapter->hw;
4198         u32 vf;
4199
4200         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
4201                 /* process any reset requests */
4202                 if (!igb_check_for_rst(hw, vf)) {
4203                         adapter->vf_data[vf].clear_to_send = false;
4204                         igb_vf_reset_event(adapter, vf);
4205                 }
4206
4207                 /* process any messages pending */
4208                 if (!igb_check_for_msg(hw, vf))
4209                         igb_rcv_msg_from_vf(adapter, vf);
4210
4211                 /* process any acks */
4212                 if (!igb_check_for_ack(hw, vf))
4213                         igb_rcv_ack_from_vf(adapter, vf);
4214
4215         }
4216 }
4217
4218 static int igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
4219 {
4220         u32 mbx_size = E1000_VFMAILBOX_SIZE;
4221         u32 msgbuf[mbx_size];
4222         struct e1000_hw *hw = &adapter->hw;
4223         s32 retval;
4224
4225         retval = igb_read_mbx(hw, msgbuf, mbx_size, vf);
4226
4227         if (retval)
4228                 dev_err(&adapter->pdev->dev,
4229                         "Error receiving message from VF\n");
4230
4231         /* this is a message we already processed, do nothing */
4232         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
4233                 return retval;
4234
4235         /*
4236          * until the vf completes a reset it should not be
4237          * allowed to start any configuration.
4238          */
4239
4240         if (msgbuf[0] == E1000_VF_RESET) {
4241                 igb_vf_reset_msg(adapter, vf);
4242
4243                 return retval;
4244         }
4245
4246         if (!adapter->vf_data[vf].clear_to_send) {
4247                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4248                 igb_write_mbx(hw, msgbuf, 1, vf);
4249                 return retval;
4250         }
4251
4252         switch ((msgbuf[0] & 0xFFFF)) {
4253         case E1000_VF_SET_MAC_ADDR:
4254                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
4255                 break;
4256         case E1000_VF_SET_MULTICAST:
4257                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
4258                 break;
4259         case E1000_VF_SET_LPE:
4260                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
4261                 break;
4262         case E1000_VF_SET_VLAN:
4263                 retval = igb_set_vf_vlan(adapter, msgbuf, vf);
4264                 break;
4265         default:
4266                 dev_err(&adapter->pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
4267                 retval = -1;
4268                 break;
4269         }
4270
4271         /* notify the VF of the results of what it sent us */
4272         if (retval)
4273                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
4274         else
4275                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
4276
4277         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
4278
4279         igb_write_mbx(hw, msgbuf, 1, vf);
4280
4281         return retval;
4282 }
4283
4284 /**
4285  * igb_intr_msi - Interrupt Handler
4286  * @irq: interrupt number
4287  * @data: pointer to a network interface device structure
4288  **/
4289 static irqreturn_t igb_intr_msi(int irq, void *data)
4290 {
4291         struct net_device *netdev = data;
4292         struct igb_adapter *adapter = netdev_priv(netdev);
4293         struct e1000_hw *hw = &adapter->hw;
4294         /* read ICR disables interrupts using IAM */
4295         u32 icr = rd32(E1000_ICR);
4296
4297         igb_write_itr(adapter->rx_ring);
4298
4299         if(icr & E1000_ICR_DOUTSYNC) {
4300                 /* HW is reporting DMA is out of sync */
4301                 adapter->stats.doosync++;
4302         }
4303
4304         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4305                 hw->mac.get_link_status = 1;
4306                 if (!test_bit(__IGB_DOWN, &adapter->state))
4307                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4308         }
4309
4310         napi_schedule(&adapter->rx_ring[0].napi);
4311
4312         return IRQ_HANDLED;
4313 }
4314
4315 /**
4316  * igb_intr - Legacy Interrupt Handler
4317  * @irq: interrupt number
4318  * @data: pointer to a network interface device structure
4319  **/
4320 static irqreturn_t igb_intr(int irq, void *data)
4321 {
4322         struct net_device *netdev = data;
4323         struct igb_adapter *adapter = netdev_priv(netdev);
4324         struct e1000_hw *hw = &adapter->hw;
4325         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
4326          * need for the IMC write */
4327         u32 icr = rd32(E1000_ICR);
4328         if (!icr)
4329                 return IRQ_NONE;  /* Not our interrupt */
4330
4331         igb_write_itr(adapter->rx_ring);
4332
4333         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
4334          * not set, then the adapter didn't send an interrupt */
4335         if (!(icr & E1000_ICR_INT_ASSERTED))
4336                 return IRQ_NONE;
4337
4338         if(icr & E1000_ICR_DOUTSYNC) {
4339                 /* HW is reporting DMA is out of sync */
4340                 adapter->stats.doosync++;
4341         }
4342
4343         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4344                 hw->mac.get_link_status = 1;
4345                 /* guard against interrupt when we're going down */
4346                 if (!test_bit(__IGB_DOWN, &adapter->state))
4347                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
4348         }
4349
4350         napi_schedule(&adapter->rx_ring[0].napi);
4351
4352         return IRQ_HANDLED;
4353 }
4354
4355 static inline void igb_rx_irq_enable(struct igb_ring *rx_ring)
4356 {
4357         struct igb_adapter *adapter = rx_ring->adapter;
4358         struct e1000_hw *hw = &adapter->hw;
4359
4360         if (adapter->itr_setting & 3) {
4361                 if (adapter->num_rx_queues == 1)
4362                         igb_set_itr(adapter);
4363                 else
4364                         igb_update_ring_itr(rx_ring);
4365         }
4366
4367         if (!test_bit(__IGB_DOWN, &adapter->state)) {
4368                 if (adapter->msix_entries)
4369                         wr32(E1000_EIMS, rx_ring->eims_value);
4370                 else
4371                         igb_irq_enable(adapter);
4372         }
4373 }
4374
4375 /**
4376  * igb_poll - NAPI Rx polling callback
4377  * @napi: napi polling structure
4378  * @budget: count of how many packets we should handle
4379  **/
4380 static int igb_poll(struct napi_struct *napi, int budget)
4381 {
4382         struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
4383         int work_done = 0;
4384
4385 #ifdef CONFIG_IGB_DCA
4386         if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4387                 igb_update_rx_dca(rx_ring);
4388 #endif
4389         igb_clean_rx_irq_adv(rx_ring, &work_done, budget);
4390
4391         if (rx_ring->buddy) {
4392 #ifdef CONFIG_IGB_DCA
4393                 if (rx_ring->adapter->flags & IGB_FLAG_DCA_ENABLED)
4394                         igb_update_tx_dca(rx_ring->buddy);
4395 #endif
4396                 if (!igb_clean_tx_irq(rx_ring->buddy))
4397                         work_done = budget;
4398         }
4399
4400         /* If not enough Rx work done, exit the polling mode */
4401         if (work_done < budget) {
4402                 napi_complete(napi);
4403                 igb_rx_irq_enable(rx_ring);
4404         }
4405
4406         return work_done;
4407 }
4408
4409 /**
4410  * igb_hwtstamp - utility function which checks for TX time stamp
4411  * @adapter: board private structure
4412  * @skb: packet that was just sent
4413  *
4414  * If we were asked to do hardware stamping and such a time stamp is
4415  * available, then it must have been for this skb here because we only
4416  * allow only one such packet into the queue.
4417  */
4418 static void igb_tx_hwtstamp(struct igb_adapter *adapter, struct sk_buff *skb)
4419 {
4420         union skb_shared_tx *shtx = skb_tx(skb);
4421         struct e1000_hw *hw = &adapter->hw;
4422
4423         if (unlikely(shtx->hardware)) {
4424                 u32 valid = rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID;
4425                 if (valid) {
4426                         u64 regval = rd32(E1000_TXSTMPL);
4427                         u64 ns;
4428                         struct skb_shared_hwtstamps shhwtstamps;
4429
4430                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
4431                         regval |= (u64)rd32(E1000_TXSTMPH) << 32;
4432                         ns = timecounter_cyc2time(&adapter->clock,
4433                                                   regval);
4434                         timecompare_update(&adapter->compare, ns);
4435                         shhwtstamps.hwtstamp = ns_to_ktime(ns);
4436                         shhwtstamps.syststamp =
4437                                 timecompare_transform(&adapter->compare, ns);
4438                         skb_tstamp_tx(skb, &shhwtstamps);
4439                 }
4440         }
4441 }
4442
4443 /**
4444  * igb_clean_tx_irq - Reclaim resources after transmit completes
4445  * @adapter: board private structure
4446  * returns true if ring is completely cleaned
4447  **/
4448 static bool igb_clean_tx_irq(struct igb_ring *tx_ring)
4449 {
4450         struct igb_adapter *adapter = tx_ring->adapter;
4451         struct net_device *netdev = adapter->netdev;
4452         struct e1000_hw *hw = &adapter->hw;
4453         struct igb_buffer *buffer_info;
4454         struct sk_buff *skb;
4455         union e1000_adv_tx_desc *tx_desc, *eop_desc;
4456         unsigned int total_bytes = 0, total_packets = 0;
4457         unsigned int i, eop, count = 0;
4458         bool cleaned = false;
4459
4460         i = tx_ring->next_to_clean;
4461         eop = tx_ring->buffer_info[i].next_to_watch;
4462         eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4463
4464         while ((eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)) &&
4465                (count < tx_ring->count)) {
4466                 for (cleaned = false; !cleaned; count++) {
4467                         tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
4468                         buffer_info = &tx_ring->buffer_info[i];
4469                         cleaned = (i == eop);
4470                         skb = buffer_info->skb;
4471
4472                         if (skb) {
4473                                 unsigned int segs, bytecount;
4474                                 /* gso_segs is currently only valid for tcp */
4475                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
4476                                 /* multiply data chunks by size of headers */
4477                                 bytecount = ((segs - 1) * skb_headlen(skb)) +
4478                                             skb->len;
4479                                 total_packets += segs;
4480                                 total_bytes += bytecount;
4481
4482                                 igb_tx_hwtstamp(adapter, skb);
4483                         }
4484
4485                         igb_unmap_and_free_tx_resource(adapter, buffer_info);
4486                         tx_desc->wb.status = 0;
4487
4488                         i++;
4489                         if (i == tx_ring->count)
4490                                 i = 0;
4491                 }
4492                 eop = tx_ring->buffer_info[i].next_to_watch;
4493                 eop_desc = E1000_TX_DESC_ADV(*tx_ring, eop);
4494         }
4495
4496         tx_ring->next_to_clean = i;
4497
4498         if (unlikely(count &&
4499                      netif_carrier_ok(netdev) &&
4500                      igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
4501                 /* Make sure that anybody stopping the queue after this
4502                  * sees the new next_to_clean.
4503                  */
4504                 smp_mb();
4505                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
4506                     !(test_bit(__IGB_DOWN, &adapter->state))) {
4507                         netif_wake_subqueue(netdev, tx_ring->queue_index);
4508                         ++adapter->restart_queue;
4509                 }
4510         }
4511
4512         if (tx_ring->detect_tx_hung) {
4513                 /* Detect a transmit hang in hardware, this serializes the
4514                  * check with the clearing of time_stamp and movement of i */
4515                 tx_ring->detect_tx_hung = false;
4516                 if (tx_ring->buffer_info[i].time_stamp &&
4517                     time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
4518                                (adapter->tx_timeout_factor * HZ))
4519                     && !(rd32(E1000_STATUS) &
4520                          E1000_STATUS_TXOFF)) {
4521
4522                         /* detected Tx unit hang */
4523                         dev_err(&adapter->pdev->dev,
4524                                 "Detected Tx Unit Hang\n"
4525                                 "  Tx Queue             <%d>\n"
4526                                 "  TDH                  <%x>\n"
4527                                 "  TDT                  <%x>\n"
4528                                 "  next_to_use          <%x>\n"
4529                                 "  next_to_clean        <%x>\n"
4530                                 "buffer_info[next_to_clean]\n"
4531                                 "  time_stamp           <%lx>\n"
4532                                 "  next_to_watch        <%x>\n"
4533                                 "  jiffies              <%lx>\n"
4534                                 "  desc.status          <%x>\n",
4535                                 tx_ring->queue_index,
4536                                 readl(adapter->hw.hw_addr + tx_ring->head),
4537                                 readl(adapter->hw.hw_addr + tx_ring->tail),
4538                                 tx_ring->next_to_use,
4539                                 tx_ring->next_to_clean,
4540                                 tx_ring->buffer_info[i].time_stamp,
4541                                 eop,
4542                                 jiffies,
4543                                 eop_desc->wb.status);
4544                         netif_stop_subqueue(netdev, tx_ring->queue_index);
4545                 }
4546         }
4547         tx_ring->total_bytes += total_bytes;
4548         tx_ring->total_packets += total_packets;
4549         tx_ring->tx_stats.bytes += total_bytes;
4550         tx_ring->tx_stats.packets += total_packets;
4551         adapter->net_stats.tx_bytes += total_bytes;
4552         adapter->net_stats.tx_packets += total_packets;
4553         return (count < tx_ring->count);
4554 }
4555
4556 /**
4557  * igb_receive_skb - helper function to handle rx indications
4558  * @ring: pointer to receive ring receving this packet
4559  * @status: descriptor status field as written by hardware
4560  * @rx_desc: receive descriptor containing vlan and type information.
4561  * @skb: pointer to sk_buff to be indicated to stack
4562  **/
4563 static void igb_receive_skb(struct igb_ring *ring, u8 status,
4564                             union e1000_adv_rx_desc * rx_desc,
4565                             struct sk_buff *skb)
4566 {
4567         struct igb_adapter * adapter = ring->adapter;
4568         bool vlan_extracted = (adapter->vlgrp && (status & E1000_RXD_STAT_VP));
4569
4570         skb_record_rx_queue(skb, ring->queue_index);
4571         if (vlan_extracted)
4572                 vlan_gro_receive(&ring->napi, adapter->vlgrp,
4573                                  le16_to_cpu(rx_desc->wb.upper.vlan),
4574                                  skb);
4575         else
4576                 napi_gro_receive(&ring->napi, skb);
4577 }
4578
4579 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
4580                                        u32 status_err, struct sk_buff *skb)
4581 {
4582         skb->ip_summed = CHECKSUM_NONE;
4583
4584         /* Ignore Checksum bit is set or checksum is disabled through ethtool */
4585         if ((status_err & E1000_RXD_STAT_IXSM) ||
4586             (adapter->flags & IGB_FLAG_RX_CSUM_DISABLED))
4587                 return;
4588         /* TCP/UDP checksum error bit is set */
4589         if (status_err &
4590             (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
4591                 /*
4592                  * work around errata with sctp packets where the TCPE aka
4593                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
4594                  * packets, (aka let the stack check the crc32c)
4595                  */
4596                 if (!((adapter->hw.mac.type == e1000_82576) &&
4597                       (skb->len == 60)))
4598                         adapter->hw_csum_err++;
4599                 /* let the stack verify checksum errors */
4600                 return;
4601         }
4602         /* It must be a TCP or UDP packet with a valid checksum */
4603         if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
4604                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4605
4606         dev_dbg(&adapter->pdev->dev, "cksum success: bits %08X\n", status_err);
4607         adapter->hw_csum_good++;
4608 }
4609
4610 static inline u16 igb_get_hlen(struct igb_adapter *adapter,
4611                                union e1000_adv_rx_desc *rx_desc)
4612 {
4613         /* HW will not DMA in data larger than the given buffer, even if it
4614          * parses the (NFS, of course) header to be larger.  In that case, it
4615          * fills the header buffer and spills the rest into the page.
4616          */
4617         u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
4618                    E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
4619         if (hlen > adapter->rx_ps_hdr_size)
4620                 hlen = adapter->rx_ps_hdr_size;
4621         return hlen;
4622 }
4623
4624 static bool igb_clean_rx_irq_adv(struct igb_ring *rx_ring,
4625                                  int *work_done, int budget)
4626 {
4627         struct igb_adapter *adapter = rx_ring->adapter;
4628         struct net_device *netdev = adapter->netdev;
4629         struct e1000_hw *hw = &adapter->hw;
4630         struct pci_dev *pdev = adapter->pdev;
4631         union e1000_adv_rx_desc *rx_desc , *next_rxd;
4632         struct igb_buffer *buffer_info , *next_buffer;
4633         struct sk_buff *skb;
4634         bool cleaned = false;
4635         int cleaned_count = 0;
4636         unsigned int total_bytes = 0, total_packets = 0;
4637         unsigned int i;
4638         u32 staterr;
4639         u16 length;
4640
4641         i = rx_ring->next_to_clean;
4642         buffer_info = &rx_ring->buffer_info[i];
4643         rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4644         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4645
4646         while (staterr & E1000_RXD_STAT_DD) {
4647                 if (*work_done >= budget)
4648                         break;
4649                 (*work_done)++;
4650
4651                 skb = buffer_info->skb;
4652                 prefetch(skb->data - NET_IP_ALIGN);
4653                 buffer_info->skb = NULL;
4654
4655                 i++;
4656                 if (i == rx_ring->count)
4657                         i = 0;
4658                 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
4659                 prefetch(next_rxd);
4660                 next_buffer = &rx_ring->buffer_info[i];
4661
4662                 length = le16_to_cpu(rx_desc->wb.upper.length);
4663                 cleaned = true;
4664                 cleaned_count++;
4665
4666                 /* this is the fast path for the non-packet split case */
4667                 if (!adapter->rx_ps_hdr_size) {
4668                         pci_unmap_single(pdev, buffer_info->dma,
4669                                          adapter->rx_buffer_len,
4670                                          PCI_DMA_FROMDEVICE);
4671                         buffer_info->dma = 0;
4672                         skb_put(skb, length);
4673                         goto send_up;
4674                 }
4675
4676                 if (buffer_info->dma) {
4677                         u16 hlen = igb_get_hlen(adapter, rx_desc);
4678                         pci_unmap_single(pdev, buffer_info->dma,
4679                                          adapter->rx_ps_hdr_size,
4680                                          PCI_DMA_FROMDEVICE);
4681                         buffer_info->dma = 0;
4682                         skb_put(skb, hlen);
4683                 }
4684
4685                 if (length) {
4686                         pci_unmap_page(pdev, buffer_info->page_dma,
4687                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
4688                         buffer_info->page_dma = 0;
4689
4690                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags++,
4691                                                 buffer_info->page,
4692                                                 buffer_info->page_offset,
4693                                                 length);
4694
4695                         if ((adapter->rx_buffer_len > (PAGE_SIZE / 2)) ||
4696                             (page_count(buffer_info->page) != 1))
4697                                 buffer_info->page = NULL;
4698                         else
4699                                 get_page(buffer_info->page);
4700
4701                         skb->len += length;
4702                         skb->data_len += length;
4703
4704                         skb->truesize += length;
4705                 }
4706
4707                 if (!(staterr & E1000_RXD_STAT_EOP)) {
4708                         buffer_info->skb = next_buffer->skb;
4709                         buffer_info->dma = next_buffer->dma;
4710                         next_buffer->skb = skb;
4711                         next_buffer->dma = 0;
4712                         goto next_desc;
4713                 }
4714 send_up:
4715                 /*
4716                  * If this bit is set, then the RX registers contain
4717                  * the time stamp. No other packet will be time
4718                  * stamped until we read these registers, so read the
4719                  * registers to make them available again. Because
4720                  * only one packet can be time stamped at a time, we
4721                  * know that the register values must belong to this
4722                  * one here and therefore we don't need to compare
4723                  * any of the additional attributes stored for it.
4724                  *
4725                  * If nothing went wrong, then it should have a
4726                  * skb_shared_tx that we can turn into a
4727                  * skb_shared_hwtstamps.
4728                  *
4729                  * TODO: can time stamping be triggered (thus locking
4730                  * the registers) without the packet reaching this point
4731                  * here? In that case RX time stamping would get stuck.
4732                  *
4733                  * TODO: in "time stamp all packets" mode this bit is
4734                  * not set. Need a global flag for this mode and then
4735                  * always read the registers. Cannot be done without
4736                  * a race condition.
4737                  */
4738                 if (unlikely(staterr & E1000_RXD_STAT_TS)) {
4739                         u64 regval;
4740                         u64 ns;
4741                         struct skb_shared_hwtstamps *shhwtstamps =
4742                                 skb_hwtstamps(skb);
4743
4744                         WARN(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID),
4745                              "igb: no RX time stamp available for time stamped packet");
4746                         regval = rd32(E1000_RXSTMPL);
4747                         regval |= (u64)rd32(E1000_RXSTMPH) << 32;
4748                         ns = timecounter_cyc2time(&adapter->clock, regval);
4749                         timecompare_update(&adapter->compare, ns);
4750                         memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4751                         shhwtstamps->hwtstamp = ns_to_ktime(ns);
4752                         shhwtstamps->syststamp =
4753                                 timecompare_transform(&adapter->compare, ns);
4754                 }
4755
4756                 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
4757                         dev_kfree_skb_irq(skb);
4758                         goto next_desc;
4759                 }
4760
4761                 total_bytes += skb->len;
4762                 total_packets++;
4763
4764                 igb_rx_checksum_adv(adapter, staterr, skb);
4765
4766                 skb->protocol = eth_type_trans(skb, netdev);
4767
4768                 igb_receive_skb(rx_ring, staterr, rx_desc, skb);
4769
4770 next_desc:
4771                 rx_desc->wb.upper.status_error = 0;
4772
4773                 /* return some buffers to hardware, one at a time is too slow */
4774                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
4775                         igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4776                         cleaned_count = 0;
4777                 }
4778
4779                 /* use prefetched values */
4780                 rx_desc = next_rxd;
4781                 buffer_info = next_buffer;
4782                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
4783         }
4784
4785         rx_ring->next_to_clean = i;
4786         cleaned_count = igb_desc_unused(rx_ring);
4787
4788         if (cleaned_count)
4789                 igb_alloc_rx_buffers_adv(rx_ring, cleaned_count);
4790
4791         rx_ring->total_packets += total_packets;
4792         rx_ring->total_bytes += total_bytes;
4793         rx_ring->rx_stats.packets += total_packets;
4794         rx_ring->rx_stats.bytes += total_bytes;
4795         adapter->net_stats.rx_bytes += total_bytes;
4796         adapter->net_stats.rx_packets += total_packets;
4797         return cleaned;
4798 }
4799
4800 /**
4801  * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
4802  * @adapter: address of board private structure
4803  **/
4804 static void igb_alloc_rx_buffers_adv(struct igb_ring *rx_ring,
4805                                      int cleaned_count)
4806 {
4807         struct igb_adapter *adapter = rx_ring->adapter;
4808         struct net_device *netdev = adapter->netdev;
4809         struct pci_dev *pdev = adapter->pdev;
4810         union e1000_adv_rx_desc *rx_desc;
4811         struct igb_buffer *buffer_info;
4812         struct sk_buff *skb;
4813         unsigned int i;
4814         int bufsz;
4815
4816         i = rx_ring->next_to_use;
4817         buffer_info = &rx_ring->buffer_info[i];
4818
4819         if (adapter->rx_ps_hdr_size)
4820                 bufsz = adapter->rx_ps_hdr_size;
4821         else
4822                 bufsz = adapter->rx_buffer_len;
4823
4824         while (cleaned_count--) {
4825                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
4826
4827                 if (adapter->rx_ps_hdr_size && !buffer_info->page_dma) {
4828                         if (!buffer_info->page) {
4829                                 buffer_info->page = alloc_page(GFP_ATOMIC);
4830                                 if (!buffer_info->page) {
4831                                         adapter->alloc_rx_buff_failed++;
4832                                         goto no_buffers;
4833                                 }
4834                                 buffer_info->page_offset = 0;
4835                         } else {
4836                                 buffer_info->page_offset ^= PAGE_SIZE / 2;
4837                         }
4838                         buffer_info->page_dma =
4839                                 pci_map_page(pdev, buffer_info->page,
4840                                              buffer_info->page_offset,
4841                                              PAGE_SIZE / 2,
4842                                              PCI_DMA_FROMDEVICE);
4843                 }
4844
4845                 if (!buffer_info->skb) {
4846                         skb = netdev_alloc_skb(netdev, bufsz + NET_IP_ALIGN);
4847                         if (!skb) {
4848                                 adapter->alloc_rx_buff_failed++;
4849                                 goto no_buffers;
4850                         }
4851
4852                         /* Make buffer alignment 2 beyond a 16 byte boundary
4853                          * this will result in a 16 byte aligned IP header after
4854                          * the 14 byte MAC header is removed
4855                          */
4856                         skb_reserve(skb, NET_IP_ALIGN);
4857
4858                         buffer_info->skb = skb;
4859                         buffer_info->dma = pci_map_single(pdev, skb->data,
4860                                                           bufsz,
4861                                                           PCI_DMA_FROMDEVICE);
4862                 }
4863                 /* Refresh the desc even if buffer_addrs didn't change because
4864                  * each write-back erases this info. */
4865                 if (adapter->rx_ps_hdr_size) {
4866                         rx_desc->read.pkt_addr =
4867                              cpu_to_le64(buffer_info->page_dma);
4868                         rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
4869                 } else {
4870                         rx_desc->read.pkt_addr =
4871                              cpu_to_le64(buffer_info->dma);
4872                         rx_desc->read.hdr_addr = 0;
4873                 }
4874
4875                 i++;
4876                 if (i == rx_ring->count)
4877                         i = 0;
4878                 buffer_info = &rx_ring->buffer_info[i];
4879         }
4880
4881 no_buffers:
4882         if (rx_ring->next_to_use != i) {
4883                 rx_ring->next_to_use = i;
4884                 if (i == 0)
4885                         i = (rx_ring->count - 1);
4886                 else
4887                         i--;
4888
4889                 /* Force memory writes to complete before letting h/w
4890                  * know there are new descriptors to fetch.  (Only
4891                  * applicable for weak-ordered memory model archs,
4892                  * such as IA-64). */
4893                 wmb();
4894                 writel(i, adapter->hw.hw_addr + rx_ring->tail);
4895         }
4896 }
4897
4898 /**
4899  * igb_mii_ioctl -
4900  * @netdev:
4901  * @ifreq:
4902  * @cmd:
4903  **/
4904 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4905 {
4906         struct igb_adapter *adapter = netdev_priv(netdev);
4907         struct mii_ioctl_data *data = if_mii(ifr);
4908
4909         if (adapter->hw.phy.media_type != e1000_media_type_copper)
4910                 return -EOPNOTSUPP;
4911
4912         switch (cmd) {
4913         case SIOCGMIIPHY:
4914                 data->phy_id = adapter->hw.phy.addr;
4915                 break;
4916         case SIOCGMIIREG:
4917                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
4918                                      &data->val_out))
4919                         return -EIO;
4920                 break;
4921         case SIOCSMIIREG:
4922         default:
4923                 return -EOPNOTSUPP;
4924         }
4925         return 0;
4926 }
4927
4928 /**
4929  * igb_hwtstamp_ioctl - control hardware time stamping
4930  * @netdev:
4931  * @ifreq:
4932  * @cmd:
4933  *
4934  * Outgoing time stamping can be enabled and disabled. Play nice and
4935  * disable it when requested, although it shouldn't case any overhead
4936  * when no packet needs it. At most one packet in the queue may be
4937  * marked for time stamping, otherwise it would be impossible to tell
4938  * for sure to which packet the hardware time stamp belongs.
4939  *
4940  * Incoming time stamping has to be configured via the hardware
4941  * filters. Not all combinations are supported, in particular event
4942  * type has to be specified. Matching the kind of event packet is
4943  * not supported, with the exception of "all V2 events regardless of
4944  * level 2 or 4".
4945  *
4946  **/
4947 static int igb_hwtstamp_ioctl(struct net_device *netdev,
4948                               struct ifreq *ifr, int cmd)
4949 {
4950         struct igb_adapter *adapter = netdev_priv(netdev);
4951         struct e1000_hw *hw = &adapter->hw;
4952         struct hwtstamp_config config;
4953         u32 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4954         u32 tsync_rx_ctl_bit = E1000_TSYNCRXCTL_ENABLED;
4955         u32 tsync_rx_ctl_type = 0;
4956         u32 tsync_rx_cfg = 0;
4957         int is_l4 = 0;
4958         int is_l2 = 0;
4959         short port = 319; /* PTP */
4960         u32 regval;
4961
4962         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
4963                 return -EFAULT;
4964
4965         /* reserved for future extensions */
4966         if (config.flags)
4967                 return -EINVAL;
4968
4969         switch (config.tx_type) {
4970         case HWTSTAMP_TX_OFF:
4971                 tsync_tx_ctl_bit = 0;
4972                 break;
4973         case HWTSTAMP_TX_ON:
4974                 tsync_tx_ctl_bit = E1000_TSYNCTXCTL_ENABLED;
4975                 break;
4976         default:
4977                 return -ERANGE;
4978         }
4979
4980         switch (config.rx_filter) {
4981         case HWTSTAMP_FILTER_NONE:
4982                 tsync_rx_ctl_bit = 0;
4983                 break;
4984         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
4985         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4986         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4987         case HWTSTAMP_FILTER_ALL:
4988                 /*
4989                  * register TSYNCRXCFG must be set, therefore it is not
4990                  * possible to time stamp both Sync and Delay_Req messages
4991                  * => fall back to time stamping all packets
4992                  */
4993                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_ALL;
4994                 config.rx_filter = HWTSTAMP_FILTER_ALL;
4995                 break;
4996         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
4997                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
4998                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
4999                 is_l4 = 1;
5000                 break;
5001         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
5002                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L4_V1;
5003                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
5004                 is_l4 = 1;
5005                 break;
5006         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5007         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5008                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5009                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
5010                 is_l2 = 1;
5011                 is_l4 = 1;
5012                 config.rx_filter = HWTSTAMP_FILTER_SOME;
5013                 break;
5014         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5015         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5016                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
5017                 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
5018                 is_l2 = 1;
5019                 is_l4 = 1;
5020                 config.rx_filter = HWTSTAMP_FILTER_SOME;
5021                 break;
5022         case HWTSTAMP_FILTER_PTP_V2_EVENT:
5023         case HWTSTAMP_FILTER_PTP_V2_SYNC:
5024         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5025                 tsync_rx_ctl_type = E1000_TSYNCRXCTL_TYPE_EVENT_V2;
5026                 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
5027                 is_l2 = 1;
5028                 break;
5029         default:
5030                 return -ERANGE;
5031         }
5032
5033         /* enable/disable TX */
5034         regval = rd32(E1000_TSYNCTXCTL);
5035         regval = (regval & ~E1000_TSYNCTXCTL_ENABLED) | tsync_tx_ctl_bit;
5036         wr32(E1000_TSYNCTXCTL, regval);
5037
5038         /* enable/disable RX, define which PTP packets are time stamped */
5039         regval = rd32(E1000_TSYNCRXCTL);
5040         regval = (regval & ~E1000_TSYNCRXCTL_ENABLED) | tsync_rx_ctl_bit;
5041         regval = (regval & ~0xE) | tsync_rx_ctl_type;
5042         wr32(E1000_TSYNCRXCTL, regval);
5043         wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
5044
5045         /*
5046          * Ethertype Filter Queue Filter[0][15:0] = 0x88F7
5047          *                                          (Ethertype to filter on)
5048          * Ethertype Filter Queue Filter[0][26] = 0x1 (Enable filter)
5049          * Ethertype Filter Queue Filter[0][30] = 0x1 (Enable Timestamping)
5050          */
5051         wr32(E1000_ETQF0, is_l2 ? 0x440088f7 : 0);
5052
5053         /* L4 Queue Filter[0]: only filter by source and destination port */
5054         wr32(E1000_SPQF0, htons(port));
5055         wr32(E1000_IMIREXT(0), is_l4 ?
5056              ((1<<12) | (1<<19) /* bypass size and control flags */) : 0);
5057         wr32(E1000_IMIR(0), is_l4 ?
5058              (htons(port)
5059               | (0<<16) /* immediate interrupt disabled */
5060               | 0 /* (1<<17) bit cleared: do not bypass
5061                      destination port check */)
5062                 : 0);
5063         wr32(E1000_FTQF0, is_l4 ?
5064              (0x11 /* UDP */
5065               | (1<<15) /* VF not compared */
5066               | (1<<27) /* Enable Timestamping */
5067               | (7<<28) /* only source port filter enabled,
5068                            source/target address and protocol
5069                            masked */)
5070              : ((1<<15) | (15<<28) /* all mask bits set = filter not
5071                                       enabled */));
5072
5073         wrfl();
5074
5075         adapter->hwtstamp_config = config;
5076
5077         /* clear TX/RX time stamp registers, just to be sure */
5078         regval = rd32(E1000_TXSTMPH);
5079         regval = rd32(E1000_RXSTMPH);
5080
5081         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
5082                 -EFAULT : 0;
5083 }
5084
5085 /**
5086  * igb_ioctl -
5087  * @netdev:
5088  * @ifreq:
5089  * @cmd:
5090  **/
5091 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5092 {
5093         switch (cmd) {
5094         case SIOCGMIIPHY:
5095         case SIOCGMIIREG:
5096         case SIOCSMIIREG:
5097                 return igb_mii_ioctl(netdev, ifr, cmd);
5098         case SIOCSHWTSTAMP:
5099                 return igb_hwtstamp_ioctl(netdev, ifr, cmd);
5100         default:
5101                 return -EOPNOTSUPP;
5102         }
5103 }
5104
5105 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5106 {
5107         struct igb_adapter *adapter = hw->back;
5108         u16 cap_offset;
5109
5110         cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5111         if (!cap_offset)
5112                 return -E1000_ERR_CONFIG;
5113
5114         pci_read_config_word(adapter->pdev, cap_offset + reg, value);
5115
5116         return 0;
5117 }
5118
5119 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
5120 {
5121         struct igb_adapter *adapter = hw->back;
5122         u16 cap_offset;
5123
5124         cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
5125         if (!cap_offset)
5126                 return -E1000_ERR_CONFIG;
5127
5128         pci_write_config_word(adapter->pdev, cap_offset + reg, *value);
5129
5130         return 0;
5131 }
5132
5133 static void igb_vlan_rx_register(struct net_device *netdev,
5134                                  struct vlan_group *grp)
5135 {
5136         struct igb_adapter *adapter = netdev_priv(netdev);
5137         struct e1000_hw *hw = &adapter->hw;
5138         u32 ctrl, rctl;
5139
5140         igb_irq_disable(adapter);
5141         adapter->vlgrp = grp;
5142
5143         if (grp) {
5144                 /* enable VLAN tag insert/strip */
5145                 ctrl = rd32(E1000_CTRL);
5146                 ctrl |= E1000_CTRL_VME;
5147                 wr32(E1000_CTRL, ctrl);
5148
5149                 /* enable VLAN receive filtering */
5150                 rctl = rd32(E1000_RCTL);
5151                 rctl &= ~E1000_RCTL_CFIEN;
5152                 wr32(E1000_RCTL, rctl);
5153                 igb_update_mng_vlan(adapter);
5154         } else {
5155                 /* disable VLAN tag insert/strip */
5156                 ctrl = rd32(E1000_CTRL);
5157                 ctrl &= ~E1000_CTRL_VME;
5158                 wr32(E1000_CTRL, ctrl);
5159
5160                 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
5161                         igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
5162                         adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
5163                 }
5164         }
5165
5166         igb_rlpml_set(adapter);
5167
5168         if (!test_bit(__IGB_DOWN, &adapter->state))
5169                 igb_irq_enable(adapter);
5170 }
5171
5172 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
5173 {
5174         struct igb_adapter *adapter = netdev_priv(netdev);
5175         struct e1000_hw *hw = &adapter->hw;
5176         int pf_id = adapter->vfs_allocated_count;
5177
5178         if ((hw->mng_cookie.status &
5179              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5180             (vid == adapter->mng_vlan_id))
5181                 return;
5182
5183         /* add vid to vlvf if sr-iov is enabled,
5184          * if that fails add directly to filter table */
5185         if (igb_vlvf_set(adapter, vid, true, pf_id))
5186                 igb_vfta_set(hw, vid, true);
5187
5188 }
5189
5190 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
5191 {
5192         struct igb_adapter *adapter = netdev_priv(netdev);
5193         struct e1000_hw *hw = &adapter->hw;
5194         int pf_id = adapter->vfs_allocated_count;
5195
5196         igb_irq_disable(adapter);
5197         vlan_group_set_device(adapter->vlgrp, vid, NULL);
5198
5199         if (!test_bit(__IGB_DOWN, &adapter->state))
5200                 igb_irq_enable(adapter);
5201
5202         if ((adapter->hw.mng_cookie.status &
5203              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
5204             (vid == adapter->mng_vlan_id)) {
5205                 /* release control to f/w */
5206                 igb_release_hw_control(adapter);
5207                 return;
5208         }
5209
5210         /* remove vid from vlvf if sr-iov is enabled,
5211          * if not in vlvf remove from vfta */
5212         if (igb_vlvf_set(adapter, vid, false, pf_id))
5213                 igb_vfta_set(hw, vid, false);
5214 }
5215
5216 static void igb_restore_vlan(struct igb_adapter *adapter)
5217 {
5218         igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5219
5220         if (adapter->vlgrp) {
5221                 u16 vid;
5222                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5223                         if (!vlan_group_get_device(adapter->vlgrp, vid))
5224                                 continue;
5225                         igb_vlan_rx_add_vid(adapter->netdev, vid);
5226                 }
5227         }
5228 }
5229
5230 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
5231 {
5232         struct e1000_mac_info *mac = &adapter->hw.mac;
5233
5234         mac->autoneg = 0;
5235
5236         switch (spddplx) {
5237         case SPEED_10 + DUPLEX_HALF:
5238                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
5239                 break;
5240         case SPEED_10 + DUPLEX_FULL:
5241                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
5242                 break;
5243         case SPEED_100 + DUPLEX_HALF:
5244                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
5245                 break;
5246         case SPEED_100 + DUPLEX_FULL:
5247                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
5248                 break;
5249         case SPEED_1000 + DUPLEX_FULL:
5250                 mac->autoneg = 1;
5251                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
5252                 break;
5253         case SPEED_1000 + DUPLEX_HALF: /* not supported */
5254         default:
5255                 dev_err(&adapter->pdev->dev,
5256                         "Unsupported Speed/Duplex configuration\n");
5257                 return -EINVAL;
5258         }
5259         return 0;
5260 }
5261
5262 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
5263 {
5264         struct net_device *netdev = pci_get_drvdata(pdev);
5265         struct igb_adapter *adapter = netdev_priv(netdev);
5266         struct e1000_hw *hw = &adapter->hw;
5267         u32 ctrl, rctl, status;
5268         u32 wufc = adapter->wol;
5269 #ifdef CONFIG_PM
5270         int retval = 0;
5271 #endif
5272
5273         netif_device_detach(netdev);
5274
5275         if (netif_running(netdev))
5276                 igb_close(netdev);
5277
5278         igb_reset_interrupt_capability(adapter);
5279
5280         igb_free_queues(adapter);
5281
5282 #ifdef CONFIG_PM
5283         retval = pci_save_state(pdev);
5284         if (retval)
5285                 return retval;
5286 #endif
5287
5288         status = rd32(E1000_STATUS);
5289         if (status & E1000_STATUS_LU)
5290                 wufc &= ~E1000_WUFC_LNKC;
5291
5292         if (wufc) {
5293                 igb_setup_rctl(adapter);
5294                 igb_set_rx_mode(netdev);
5295
5296                 /* turn on all-multi mode if wake on multicast is enabled */
5297                 if (wufc & E1000_WUFC_MC) {
5298                         rctl = rd32(E1000_RCTL);
5299                         rctl |= E1000_RCTL_MPE;
5300                         wr32(E1000_RCTL, rctl);
5301                 }
5302
5303                 ctrl = rd32(E1000_CTRL);
5304                 /* advertise wake from D3Cold */
5305                 #define E1000_CTRL_ADVD3WUC 0x00100000
5306                 /* phy power management enable */
5307                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5308                 ctrl |= E1000_CTRL_ADVD3WUC;
5309                 wr32(E1000_CTRL, ctrl);
5310
5311                 /* Allow time for pending master requests to run */
5312                 igb_disable_pcie_master(&adapter->hw);
5313
5314                 wr32(E1000_WUC, E1000_WUC_PME_EN);
5315                 wr32(E1000_WUFC, wufc);
5316         } else {
5317                 wr32(E1000_WUC, 0);
5318                 wr32(E1000_WUFC, 0);
5319         }
5320
5321         *enable_wake = wufc || adapter->en_mng_pt;
5322         if (!*enable_wake)
5323                 igb_shutdown_serdes_link_82575(hw);
5324
5325         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
5326          * would have already happened in close and is redundant. */
5327         igb_release_hw_control(adapter);
5328
5329         pci_disable_device(pdev);
5330
5331         return 0;
5332 }
5333
5334 #ifdef CONFIG_PM
5335 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
5336 {
5337         int retval;
5338         bool wake;
5339
5340         retval = __igb_shutdown(pdev, &wake);
5341         if (retval)
5342                 return retval;
5343
5344         if (wake) {
5345                 pci_prepare_to_sleep(pdev);
5346         } else {
5347                 pci_wake_from_d3(pdev, false);
5348                 pci_set_power_state(pdev, PCI_D3hot);
5349         }
5350
5351         return 0;
5352 }
5353
5354 static int igb_resume(struct pci_dev *pdev)
5355 {
5356         struct net_device *netdev = pci_get_drvdata(pdev);
5357         struct igb_adapter *adapter = netdev_priv(netdev);
5358         struct e1000_hw *hw = &adapter->hw;
5359         u32 err;
5360
5361         pci_set_power_state(pdev, PCI_D0);
5362         pci_restore_state(pdev);
5363
5364         err = pci_enable_device_mem(pdev);
5365         if (err) {
5366                 dev_err(&pdev->dev,
5367                         "igb: Cannot enable PCI device from suspend\n");
5368                 return err;
5369         }
5370         pci_set_master(pdev);
5371
5372         pci_enable_wake(pdev, PCI_D3hot, 0);
5373         pci_enable_wake(pdev, PCI_D3cold, 0);
5374
5375         igb_set_interrupt_capability(adapter);
5376
5377         if (igb_alloc_queues(adapter)) {
5378                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
5379                 return -ENOMEM;
5380         }
5381
5382         /* e1000_power_up_phy(adapter); */
5383
5384         igb_reset(adapter);
5385
5386         /* let the f/w know that the h/w is now under the control of the
5387          * driver. */
5388         igb_get_hw_control(adapter);
5389
5390         wr32(E1000_WUS, ~0);
5391
5392         if (netif_running(netdev)) {
5393                 err = igb_open(netdev);
5394                 if (err)
5395                         return err;
5396         }
5397
5398         netif_device_attach(netdev);
5399
5400         return 0;
5401 }
5402 #endif
5403
5404 static void igb_shutdown(struct pci_dev *pdev)
5405 {
5406         bool wake;
5407
5408         __igb_shutdown(pdev, &wake);
5409
5410         if (system_state == SYSTEM_POWER_OFF) {
5411                 pci_wake_from_d3(pdev, wake);
5412                 pci_set_power_state(pdev, PCI_D3hot);
5413         }
5414 }
5415
5416 #ifdef CONFIG_NET_POLL_CONTROLLER
5417 /*
5418  * Polling 'interrupt' - used by things like netconsole to send skbs
5419  * without having to re-enable interrupts. It's not called while
5420  * the interrupt routine is executing.
5421  */
5422 static void igb_netpoll(struct net_device *netdev)
5423 {
5424         struct igb_adapter *adapter = netdev_priv(netdev);
5425         struct e1000_hw *hw = &adapter->hw;
5426         int i;
5427
5428         if (!adapter->msix_entries) {
5429                 igb_irq_disable(adapter);
5430                 napi_schedule(&adapter->rx_ring[0].napi);
5431                 return;
5432         }
5433
5434         for (i = 0; i < adapter->num_tx_queues; i++) {
5435                 struct igb_ring *tx_ring = &adapter->tx_ring[i];
5436                 wr32(E1000_EIMC, tx_ring->eims_value);
5437                 igb_clean_tx_irq(tx_ring);
5438                 wr32(E1000_EIMS, tx_ring->eims_value);
5439         }
5440
5441         for (i = 0; i < adapter->num_rx_queues; i++) {
5442                 struct igb_ring *rx_ring = &adapter->rx_ring[i];
5443                 wr32(E1000_EIMC, rx_ring->eims_value);
5444                 napi_schedule(&rx_ring->napi);
5445         }
5446 }
5447 #endif /* CONFIG_NET_POLL_CONTROLLER */
5448
5449 /**
5450  * igb_io_error_detected - called when PCI error is detected
5451  * @pdev: Pointer to PCI device
5452  * @state: The current pci connection state
5453  *
5454  * This function is called after a PCI bus error affecting
5455  * this device has been detected.
5456  */
5457 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
5458                                               pci_channel_state_t state)
5459 {
5460         struct net_device *netdev = pci_get_drvdata(pdev);
5461         struct igb_adapter *adapter = netdev_priv(netdev);
5462
5463         netif_device_detach(netdev);
5464
5465         if (state == pci_channel_io_perm_failure)
5466                 return PCI_ERS_RESULT_DISCONNECT;
5467
5468         if (netif_running(netdev))
5469                 igb_down(adapter);
5470         pci_disable_device(pdev);
5471
5472         /* Request a slot slot reset. */
5473         return PCI_ERS_RESULT_NEED_RESET;
5474 }
5475
5476 /**
5477  * igb_io_slot_reset - called after the pci bus has been reset.
5478  * @pdev: Pointer to PCI device
5479  *
5480  * Restart the card from scratch, as if from a cold-boot. Implementation
5481  * resembles the first-half of the igb_resume routine.
5482  */
5483 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
5484 {
5485         struct net_device *netdev = pci_get_drvdata(pdev);
5486         struct igb_adapter *adapter = netdev_priv(netdev);
5487         struct e1000_hw *hw = &adapter->hw;
5488         pci_ers_result_t result;
5489         int err;
5490
5491         if (pci_enable_device_mem(pdev)) {
5492                 dev_err(&pdev->dev,
5493                         "Cannot re-enable PCI device after reset.\n");
5494                 result = PCI_ERS_RESULT_DISCONNECT;
5495         } else {
5496                 pci_set_master(pdev);
5497                 pci_restore_state(pdev);
5498
5499                 pci_enable_wake(pdev, PCI_D3hot, 0);
5500                 pci_enable_wake(pdev, PCI_D3cold, 0);
5501
5502                 igb_reset(adapter);
5503                 wr32(E1000_WUS, ~0);
5504                 result = PCI_ERS_RESULT_RECOVERED;
5505         }
5506
5507         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5508         if (err) {
5509                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
5510                         "failed 0x%0x\n", err);
5511                 /* non-fatal, continue */
5512         }
5513
5514         return result;
5515 }
5516
5517 /**
5518  * igb_io_resume - called when traffic can start flowing again.
5519  * @pdev: Pointer to PCI device
5520  *
5521  * This callback is called when the error recovery driver tells us that
5522  * its OK to resume normal operation. Implementation resembles the
5523  * second-half of the igb_resume routine.
5524  */
5525 static void igb_io_resume(struct pci_dev *pdev)
5526 {
5527         struct net_device *netdev = pci_get_drvdata(pdev);
5528         struct igb_adapter *adapter = netdev_priv(netdev);
5529
5530         if (netif_running(netdev)) {
5531                 if (igb_up(adapter)) {
5532                         dev_err(&pdev->dev, "igb_up failed after reset\n");
5533                         return;
5534                 }
5535         }
5536
5537         netif_device_attach(netdev);
5538
5539         /* let the f/w know that the h/w is now under the control of the
5540          * driver. */
5541         igb_get_hw_control(adapter);
5542 }
5543
5544 static int igb_set_vf_mac(struct igb_adapter *adapter,
5545                           int vf, unsigned char *mac_addr)
5546 {
5547         struct e1000_hw *hw = &adapter->hw;
5548         /* VF MAC addresses start at end of receive addresses and moves
5549          * torwards the first, as a result a collision should not be possible */
5550         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5551
5552         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
5553
5554         igb_rar_set(hw, mac_addr, rar_entry);
5555         igb_set_rah_pool(hw, vf, rar_entry);
5556
5557         return 0;
5558 }
5559
5560 static void igb_vmm_control(struct igb_adapter *adapter)
5561 {
5562         struct e1000_hw *hw = &adapter->hw;
5563         u32 reg_data;
5564
5565         if (!adapter->vfs_allocated_count)
5566                 return;
5567
5568         /* VF's need PF reset indication before they
5569          * can send/receive mail */
5570         reg_data = rd32(E1000_CTRL_EXT);
5571         reg_data |= E1000_CTRL_EXT_PFRSTD;
5572         wr32(E1000_CTRL_EXT, reg_data);
5573
5574         igb_vmdq_set_loopback_pf(hw, true);
5575         igb_vmdq_set_replication_pf(hw, true);
5576 }
5577
5578 /* igb_main.c */