drivers/net/igb/e1000_hw.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #ifndef _E1000_HW_H_
  29 #define _E1000_HW_H_
  30
  31 #include <linux/types.h>
  32 #include <linux/delay.h>
  33 #include <linux/io.h>
  34
  35 #include "e1000_mac.h"
  36 #include "e1000_regs.h"
  37 #include "e1000_defines.h"
  38
  39 struct e1000_hw;
  40
  41 #define E1000_DEV_ID_82576                    0x10C9
  42 #define E1000_DEV_ID_82576_FIBER              0x10E6
  43 #define E1000_DEV_ID_82576_SERDES             0x10E7
  44 #define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
  45 #define E1000_DEV_ID_82575EB_COPPER           0x10A7
  46 #define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
  47 #define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
  48
  49 #define E1000_REVISION_2 2
  50 #define E1000_REVISION_4 4
  51
  52 #define E1000_FUNC_1     1
  53
  54 enum e1000_mac_type {
  55         e1000_undefined = 0,
  56         e1000_82575,
  57         e1000_82576,
  58         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  59 };
  60
  61 enum e1000_media_type {
  62         e1000_media_type_unknown = 0,
  63         e1000_media_type_copper = 1,
  64         e1000_media_type_fiber = 2,
  65         e1000_media_type_internal_serdes = 3,
  66         e1000_num_media_types
  67 };
  68
  69 enum e1000_nvm_type {
  70         e1000_nvm_unknown = 0,
  71         e1000_nvm_none,
  72         e1000_nvm_eeprom_spi,
  73         e1000_nvm_eeprom_microwire,
  74         e1000_nvm_flash_hw,
  75         e1000_nvm_flash_sw
  76 };
  77
  78 enum e1000_nvm_override {
  79         e1000_nvm_override_none = 0,
  80         e1000_nvm_override_spi_small,
  81         e1000_nvm_override_spi_large,
  82         e1000_nvm_override_microwire_small,
  83         e1000_nvm_override_microwire_large
  84 };
  85
  86 enum e1000_phy_type {
  87         e1000_phy_unknown = 0,
  88         e1000_phy_none,
  89         e1000_phy_m88,
  90         e1000_phy_igp,
  91         e1000_phy_igp_2,
  92         e1000_phy_gg82563,
  93         e1000_phy_igp_3,
  94         e1000_phy_ife,
  95 };
  96
  97 enum e1000_bus_type {
  98         e1000_bus_type_unknown = 0,
  99         e1000_bus_type_pci,
 100         e1000_bus_type_pcix,
 101         e1000_bus_type_pci_express,
 102         e1000_bus_type_reserved
 103 };
 104
 105 enum e1000_bus_speed {
 106         e1000_bus_speed_unknown = 0,
 107         e1000_bus_speed_33,
 108         e1000_bus_speed_66,
 109         e1000_bus_speed_100,
 110         e1000_bus_speed_120,
 111         e1000_bus_speed_133,
 112         e1000_bus_speed_2500,
 113         e1000_bus_speed_5000,
 114         e1000_bus_speed_reserved
 115 };
 116
 117 enum e1000_bus_width {
 118         e1000_bus_width_unknown = 0,
 119         e1000_bus_width_pcie_x1,
 120         e1000_bus_width_pcie_x2,
 121         e1000_bus_width_pcie_x4 = 4,
 122         e1000_bus_width_pcie_x8 = 8,
 123         e1000_bus_width_32,
 124         e1000_bus_width_64,
 125         e1000_bus_width_reserved
 126 };
 127
 128 enum e1000_1000t_rx_status {
 129         e1000_1000t_rx_status_not_ok = 0,
 130         e1000_1000t_rx_status_ok,
 131         e1000_1000t_rx_status_undefined = 0xFF
 132 };
 133
 134 enum e1000_rev_polarity {
 135         e1000_rev_polarity_normal = 0,
 136         e1000_rev_polarity_reversed,
 137         e1000_rev_polarity_undefined = 0xFF
 138 };
 139
 140 enum e1000_fc_type {
 141         e1000_fc_none = 0,
 142         e1000_fc_rx_pause,
 143         e1000_fc_tx_pause,
 144         e1000_fc_full,
 145         e1000_fc_default = 0xFF
 146 };
 147
 148
 149 /* Receive Descriptor */
 150 struct e1000_rx_desc {
 151         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 152         __le16 length;      /* Length of data DMAed into data buffer */
 153         __le16 csum;        /* Packet checksum */
 154         u8  status;      /* Descriptor status */
 155         u8  errors;      /* Descriptor Errors */
 156         __le16 special;
 157 };
 158
 159 /* Receive Descriptor - Extended */
 160 union e1000_rx_desc_extended {
 161         struct {
 162                 __le64 buffer_addr;
 163                 __le64 reserved;
 164         } read;
 165         struct {
 166                 struct {
 167                         __le32 mrq;              /* Multiple Rx Queues */
 168                         union {
 169                                 __le32 rss;            /* RSS Hash */
 170                                 struct {
 171                                         __le16 ip_id;  /* IP id */
 172                                         __le16 csum;   /* Packet Checksum */
 173                                 } csum_ip;
 174                         } hi_dword;
 175                 } lower;
 176                 struct {
 177                         __le32 status_error;     /* ext status/error */
 178                         __le16 length;
 179                         __le16 vlan;             /* VLAN tag */
 180                 } upper;
 181         } wb;  /* writeback */
 182 };
 183
 184 #define MAX_PS_BUFFERS 4
 185 /* Receive Descriptor - Packet Split */
 186 union e1000_rx_desc_packet_split {
 187         struct {
 188                 /* one buffer for protocol header(s), three data buffers */
 189                 __le64 buffer_addr[MAX_PS_BUFFERS];
 190         } read;
 191         struct {
 192                 struct {
 193                         __le32 mrq;              /* Multiple Rx Queues */
 194                         union {
 195                                 __le32 rss;              /* RSS Hash */
 196                                 struct {
 197                                         __le16 ip_id;    /* IP id */
 198                                         __le16 csum;     /* Packet Checksum */
 199                                 } csum_ip;
 200                         } hi_dword;
 201                 } lower;
 202                 struct {
 203                         __le32 status_error;     /* ext status/error */
 204                         __le16 length0;          /* length of buffer 0 */
 205                         __le16 vlan;             /* VLAN tag */
 206                 } middle;
 207                 struct {
 208                         __le16 header_status;
 209                         __le16 length[3];        /* length of buffers 1-3 */
 210                 } upper;
 211                 __le64 reserved;
 212         } wb; /* writeback */
 213 };
 214
 215 /* Transmit Descriptor */
 216 struct e1000_tx_desc {
 217         __le64 buffer_addr;      /* Address of the descriptor's data buffer */
 218         union {
 219                 __le32 data;
 220                 struct {
 221                         __le16 length;    /* Data buffer length */
 222                         u8 cso;        /* Checksum offset */
 223                         u8 cmd;        /* Descriptor control */
 224                 } flags;
 225         } lower;
 226         union {
 227                 __le32 data;
 228                 struct {
 229                         u8 status;     /* Descriptor status */
 230                         u8 css;        /* Checksum start */
 231                         __le16 special;
 232                 } fields;
 233         } upper;
 234 };
 235
 236 /* Offload Context Descriptor */
 237 struct e1000_context_desc {
 238         union {
 239                 __le32 ip_config;
 240                 struct {
 241                         u8 ipcss;      /* IP checksum start */
 242                         u8 ipcso;      /* IP checksum offset */
 243                         __le16 ipcse;     /* IP checksum end */
 244                 } ip_fields;
 245         } lower_setup;
 246         union {
 247                 __le32 tcp_config;
 248                 struct {
 249                         u8 tucss;      /* TCP checksum start */
 250                         u8 tucso;      /* TCP checksum offset */
 251                         __le16 tucse;     /* TCP checksum end */
 252                 } tcp_fields;
 253         } upper_setup;
 254         __le32 cmd_and_length;
 255         union {
 256                 __le32 data;
 257                 struct {
 258                         u8 status;     /* Descriptor status */
 259                         u8 hdr_len;    /* Header length */
 260                         __le16 mss;       /* Maximum segment size */
 261                 } fields;
 262         } tcp_seg_setup;
 263 };
 264
 265 /* Offload data descriptor */
 266 struct e1000_data_desc {
 267         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 268         union {
 269                 __le32 data;
 270                 struct {
 271                         __le16 length;    /* Data buffer length */
 272                         u8 typ_len_ext;
 273                         u8 cmd;
 274                 } flags;
 275         } lower;
 276         union {
 277                 __le32 data;
 278                 struct {
 279                         u8 status;     /* Descriptor status */
 280                         u8 popts;      /* Packet Options */
 281                         __le16 special;
 282                 } fields;
 283         } upper;
 284 };
 285
 286 /* Statistics counters collected by the MAC */
 287 struct e1000_hw_stats {
 288         u64 crcerrs;
 289         u64 algnerrc;
 290         u64 symerrs;
 291         u64 rxerrc;
 292         u64 mpc;
 293         u64 scc;
 294         u64 ecol;
 295         u64 mcc;
 296         u64 latecol;
 297         u64 colc;
 298         u64 dc;
 299         u64 tncrs;
 300         u64 sec;
 301         u64 cexterr;
 302         u64 rlec;
 303         u64 xonrxc;
 304         u64 xontxc;
 305         u64 xoffrxc;
 306         u64 xofftxc;
 307         u64 fcruc;
 308         u64 prc64;
 309         u64 prc127;
 310         u64 prc255;
 311         u64 prc511;
 312         u64 prc1023;
 313         u64 prc1522;
 314         u64 gprc;
 315         u64 bprc;
 316         u64 mprc;
 317         u64 gptc;
 318         u64 gorc;
 319         u64 gotc;
 320         u64 rnbc;
 321         u64 ruc;
 322         u64 rfc;
 323         u64 roc;
 324         u64 rjc;
 325         u64 mgprc;
 326         u64 mgpdc;
 327         u64 mgptc;
 328         u64 tor;
 329         u64 tot;
 330         u64 tpr;
 331         u64 tpt;
 332         u64 ptc64;
 333         u64 ptc127;
 334         u64 ptc255;
 335         u64 ptc511;
 336         u64 ptc1023;
 337         u64 ptc1522;
 338         u64 mptc;
 339         u64 bptc;
 340         u64 tsctc;
 341         u64 tsctfc;
 342         u64 iac;
 343         u64 icrxptc;
 344         u64 icrxatc;
 345         u64 ictxptc;
 346         u64 ictxatc;
 347         u64 ictxqec;
 348         u64 ictxqmtc;
 349         u64 icrxdmtc;
 350         u64 icrxoc;
 351         u64 cbtmpc;
 352         u64 htdpmc;
 353         u64 cbrdpc;
 354         u64 cbrmpc;
 355         u64 rpthc;
 356         u64 hgptc;
 357         u64 htcbdpc;
 358         u64 hgorc;
 359         u64 hgotc;
 360         u64 lenerrs;
 361         u64 scvpc;
 362         u64 hrmpc;
 363 };
 364
 365 struct e1000_phy_stats {
 366         u32 idle_errors;
 367         u32 receive_errors;
 368 };
 369
 370 struct e1000_host_mng_dhcp_cookie {
 371         u32 signature;
 372         u8  status;
 373         u8  reserved0;
 374         u16 vlan_id;
 375         u32 reserved1;
 376         u16 reserved2;
 377         u8  reserved3;
 378         u8  checksum;
 379 };
 380
 381 /* Host Interface "Rev 1" */
 382 struct e1000_host_command_header {
 383         u8 command_id;
 384         u8 command_length;
 385         u8 command_options;
 386         u8 checksum;
 387 };
 388
 389 #define E1000_HI_MAX_DATA_LENGTH     252
 390 struct e1000_host_command_info {
 391         struct e1000_host_command_header command_header;
 392         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 393 };
 394
 395 /* Host Interface "Rev 2" */
 396 struct e1000_host_mng_command_header {
 397         u8  command_id;
 398         u8  checksum;
 399         u16 reserved1;
 400         u16 reserved2;
 401         u16 command_length;
 402 };
 403
 404 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 405 struct e1000_host_mng_command_info {
 406         struct e1000_host_mng_command_header command_header;
 407         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 408 };
 409
 410 #include "e1000_mac.h"
 411 #include "e1000_phy.h"
 412 #include "e1000_nvm.h"
 413
 414 struct e1000_mac_operations {
 415         s32  (*check_for_link)(struct e1000_hw *);
 416         s32  (*reset_hw)(struct e1000_hw *);
 417         s32  (*init_hw)(struct e1000_hw *);
 418         bool (*check_mng_mode)(struct e1000_hw *);
 419         s32  (*setup_physical_interface)(struct e1000_hw *);
 420         void (*rar_set)(struct e1000_hw *, u8 *, u32);
 421         s32  (*read_mac_addr)(struct e1000_hw *);
 422         s32  (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
 423         void (*mta_set)(struct e1000_hw *, u32);
 424 };
 425
 426 struct e1000_phy_operations {
 427         s32  (*acquire_phy)(struct e1000_hw *);
 428         s32  (*check_reset_block)(struct e1000_hw *);
 429         s32  (*force_speed_duplex)(struct e1000_hw *);
 430         s32  (*get_cfg_done)(struct e1000_hw *hw);
 431         s32  (*get_cable_length)(struct e1000_hw *);
 432         s32  (*get_phy_info)(struct e1000_hw *);
 433         s32  (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
 434         void (*release_phy)(struct e1000_hw *);
 435         s32  (*reset_phy)(struct e1000_hw *);
 436         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 437         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 438         s32  (*write_phy_reg)(struct e1000_hw *, u32, u16);
 439 };
 440
 441 struct e1000_nvm_operations {
 442         s32  (*acquire_nvm)(struct e1000_hw *);
 443         s32  (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
 444         void (*release_nvm)(struct e1000_hw *);
 445         s32  (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
 446 };
 447
 448 struct e1000_info {
 449         s32 (*get_invariants)(struct e1000_hw *);
 450         struct e1000_mac_operations *mac_ops;
 451         struct e1000_phy_operations *phy_ops;
 452         struct e1000_nvm_operations *nvm_ops;
 453 };
 454
 455 extern const struct e1000_info e1000_82575_info;
 456
 457 struct e1000_mac_info {
 458         struct e1000_mac_operations ops;
 459
 460         u8 addr[6];
 461         u8 perm_addr[6];
 462
 463         enum e1000_mac_type type;
 464
 465         u32 collision_delta;
 466         u32 ledctl_default;
 467         u32 ledctl_mode1;
 468         u32 ledctl_mode2;
 469         u32 mc_filter_type;
 470         u32 tx_packet_delta;
 471         u32 txcw;
 472
 473         u16 current_ifs_val;
 474         u16 ifs_max_val;
 475         u16 ifs_min_val;
 476         u16 ifs_ratio;
 477         u16 ifs_step_size;
 478         u16 mta_reg_count;
 479         u16 rar_entry_count;
 480
 481         u8  forced_speed_duplex;
 482
 483         bool adaptive_ifs;
 484         bool arc_subsystem_valid;
 485         bool asf_firmware_present;
 486         bool autoneg;
 487         bool autoneg_failed;
 488         bool disable_av;
 489         bool disable_hw_init_bits;
 490         bool get_link_status;
 491         bool ifs_params_forced;
 492         bool in_ifs_mode;
 493         bool report_tx_early;
 494         bool serdes_has_link;
 495         bool tx_pkt_filtering;
 496 };
 497
 498 struct e1000_phy_info {
 499         struct e1000_phy_operations ops;
 500
 501         enum e1000_phy_type type;
 502
 503         enum e1000_1000t_rx_status local_rx;
 504         enum e1000_1000t_rx_status remote_rx;
 505         enum e1000_ms_type ms_type;
 506         enum e1000_ms_type original_ms_type;
 507         enum e1000_rev_polarity cable_polarity;
 508         enum e1000_smart_speed smart_speed;
 509
 510         u32 addr;
 511         u32 id;
 512         u32 reset_delay_us; /* in usec */
 513         u32 revision;
 514
 515         enum e1000_media_type media_type;
 516
 517         u16 autoneg_advertised;
 518         u16 autoneg_mask;
 519         u16 cable_length;
 520         u16 max_cable_length;
 521         u16 min_cable_length;
 522
 523         u8 mdix;
 524
 525         bool disable_polarity_correction;
 526         bool is_mdix;
 527         bool polarity_correction;
 528         bool reset_disable;
 529         bool speed_downgraded;
 530         bool autoneg_wait_to_complete;
 531 };
 532
 533 struct e1000_nvm_info {
 534         struct e1000_nvm_operations ops;
 535
 536         enum e1000_nvm_type type;
 537         enum e1000_nvm_override override;
 538
 539         u32 flash_bank_size;
 540         u32 flash_base_addr;
 541
 542         u16 word_size;
 543         u16 delay_usec;
 544         u16 address_bits;
 545         u16 opcode_bits;
 546         u16 page_size;
 547 };
 548
 549 struct e1000_bus_info {
 550         enum e1000_bus_type type;
 551         enum e1000_bus_speed speed;
 552         enum e1000_bus_width width;
 553
 554         u32 snoop;
 555
 556         u16 func;
 557         u16 pci_cmd_word;
 558 };
 559
 560 struct e1000_fc_info {
 561         u32 high_water;     /* Flow control high-water mark */
 562         u32 low_water;      /* Flow control low-water mark */
 563         u16 pause_time;     /* Flow control pause timer */
 564         bool send_xon;      /* Flow control send XON */
 565         bool strict_ieee;   /* Strict IEEE mode */
 566         enum e1000_fc_type type; /* Type of flow control */
 567         enum e1000_fc_type original_type;
 568 };
 569
 570 struct e1000_hw {
 571         void *back;
 572         void *dev_spec;
 573
 574         u8 __iomem *hw_addr;
 575         u8 __iomem *flash_address;
 576         unsigned long io_base;
 577
 578         struct e1000_mac_info  mac;
 579         struct e1000_fc_info   fc;
 580         struct e1000_phy_info  phy;
 581         struct e1000_nvm_info  nvm;
 582         struct e1000_bus_info  bus;
 583         struct e1000_host_mng_dhcp_cookie mng_cookie;
 584
 585         u32 dev_spec_size;
 586
 587         u16 device_id;
 588         u16 subsystem_vendor_id;
 589         u16 subsystem_device_id;
 590         u16 vendor_id;
 591
 592         u8  revision_id;
 593 };
 594
 595 #ifdef DEBUG
 596 extern char *igb_get_hw_dev_name(struct e1000_hw *hw);
 597 #define hw_dbg(format, arg...) \
 598         printk(KERN_DEBUG "%s: " format, igb_get_hw_dev_name(hw), ##arg)
 599 #else
 600 #define hw_dbg(format, arg...)
 601 #endif
 602
 603 #endif