drivers/net/hamradio/dmascc.c

   1 /*
   2  * Driver for high-speed SCC boards (those with DMA support)
   3  * Copyright (C) 1997-2000 Klaus Kudielka
   4  *
   5  * S5SCC/DMA support by Janko Koleznik S52HI
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22
  23 #include <linux/module.h>
  24 #include <linux/delay.h>
  25 #include <linux/errno.h>
  26 #include <linux/if_arp.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/rtnetlink.h>
  35 #include <linux/sockios.h>
  36 #include <linux/workqueue.h>
  37 #include <asm/atomic.h>
  38 #include <asm/bitops.h>
  39 #include <asm/dma.h>
  40 #include <asm/io.h>
  41 #include <asm/irq.h>
  42 #include <asm/uaccess.h>
  43 #include <net/ax25.h>
  44 #include "z8530.h"
  45
  46
  47 /* Number of buffers per channel */
  48
  49 #define NUM_TX_BUF      2       /* NUM_TX_BUF >= 1 (min. 2 recommended) */
  50 #define NUM_RX_BUF      6       /* NUM_RX_BUF >= 1 (min. 2 recommended) */
  51 #define BUF_SIZE        1576    /* BUF_SIZE >= mtu + hard_header_len */
  52
  53
  54 /* Cards supported */
  55
  56 #define HW_PI           { "Ottawa PI", 0x300, 0x20, 0x10, 8, \
  57                             0, 8, 1843200, 3686400 }
  58 #define HW_PI2          { "Ottawa PI2", 0x300, 0x20, 0x10, 8, \
  59                             0, 8, 3686400, 7372800 }
  60 #define HW_TWIN         { "Gracilis PackeTwin", 0x200, 0x10, 0x10, 32, \
  61                             0, 4, 6144000, 6144000 }
  62 #define HW_S5           { "S5SCC/DMA", 0x200, 0x10, 0x10, 32, \
  63                           0, 8, 4915200, 9830400 }
  64
  65 #define HARDWARE        { HW_PI, HW_PI2, HW_TWIN, HW_S5 }
  66
  67 #define TMR_0_HZ        25600   /* Frequency of timer 0 */
  68
  69 #define TYPE_PI         0
  70 #define TYPE_PI2        1
  71 #define TYPE_TWIN       2
  72 #define TYPE_S5         3
  73 #define NUM_TYPES       4
  74
  75 #define MAX_NUM_DEVS    32
  76
  77
  78 /* SCC chips supported */
  79
  80 #define Z8530           0
  81 #define Z85C30          1
  82 #define Z85230          2
  83
  84 #define CHIPNAMES       { "Z8530", "Z85C30", "Z85230" }
  85
  86
  87 /* I/O registers */
  88
  89 /* 8530 registers relative to card base */
  90 #define SCCB_CMD        0x00
  91 #define SCCB_DATA       0x01
  92 #define SCCA_CMD        0x02
  93 #define SCCA_DATA       0x03
  94
  95 /* 8253/8254 registers relative to card base */
  96 #define TMR_CNT0        0x00
  97 #define TMR_CNT1        0x01
  98 #define TMR_CNT2        0x02
  99 #define TMR_CTRL        0x03
 100
 101 /* Additional PI/PI2 registers relative to card base */
 102 #define PI_DREQ_MASK    0x04
 103
 104 /* Additional PackeTwin registers relative to card base */
 105 #define TWIN_INT_REG    0x08
 106 #define TWIN_CLR_TMR1   0x09
 107 #define TWIN_CLR_TMR2   0x0a
 108 #define TWIN_SPARE_1    0x0b
 109 #define TWIN_DMA_CFG    0x08
 110 #define TWIN_SERIAL_CFG 0x09
 111 #define TWIN_DMA_CLR_FF 0x0a
 112 #define TWIN_SPARE_2    0x0b
 113
 114
 115 /* PackeTwin I/O register values */
 116
 117 /* INT_REG */
 118 #define TWIN_SCC_MSK       0x01
 119 #define TWIN_TMR1_MSK      0x02
 120 #define TWIN_TMR2_MSK      0x04
 121 #define TWIN_INT_MSK       0x07
 122
 123 /* SERIAL_CFG */
 124 #define TWIN_DTRA_ON       0x01
 125 #define TWIN_DTRB_ON       0x02
 126 #define TWIN_EXTCLKA       0x04
 127 #define TWIN_EXTCLKB       0x08
 128 #define TWIN_LOOPA_ON      0x10
 129 #define TWIN_LOOPB_ON      0x20
 130 #define TWIN_EI            0x80
 131
 132 /* DMA_CFG */
 133 #define TWIN_DMA_HDX_T1    0x08
 134 #define TWIN_DMA_HDX_R1    0x0a
 135 #define TWIN_DMA_HDX_T3    0x14
 136 #define TWIN_DMA_HDX_R3    0x16
 137 #define TWIN_DMA_FDX_T3R1  0x1b
 138 #define TWIN_DMA_FDX_T1R3  0x1d
 139
 140
 141 /* Status values */
 142
 143 #define IDLE      0
 144 #define TX_HEAD   1
 145 #define TX_DATA   2
 146 #define TX_PAUSE  3
 147 #define TX_TAIL   4
 148 #define RTS_OFF   5
 149 #define WAIT      6
 150 #define DCD_ON    7
 151 #define RX_ON     8
 152 #define DCD_OFF   9
 153
 154
 155 /* Ioctls */
 156
 157 #define SIOCGSCCPARAM SIOCDEVPRIVATE
 158 #define SIOCSSCCPARAM (SIOCDEVPRIVATE+1)
 159
 160
 161 /* Data types */
 162
 163 struct scc_param {
 164         int pclk_hz;            /* frequency of BRG input (don't change) */
 165         int brg_tc;             /* BRG terminal count; BRG disabled if < 0 */
 166         int nrzi;               /* 0 (nrz), 1 (nrzi) */
 167         int clocks;             /* see dmascc_cfg documentation */
 168         int txdelay;            /* [1/TMR_0_HZ] */
 169         int txtimeout;          /* [1/HZ] */
 170         int txtail;             /* [1/TMR_0_HZ] */
 171         int waittime;           /* [1/TMR_0_HZ] */
 172         int slottime;           /* [1/TMR_0_HZ] */
 173         int persist;            /* 1 ... 256 */
 174         int dma;                /* -1 (disable), 0, 1, 3 */
 175         int txpause;            /* [1/TMR_0_HZ] */
 176         int rtsoff;             /* [1/TMR_0_HZ] */
 177         int dcdon;              /* [1/TMR_0_HZ] */
 178         int dcdoff;             /* [1/TMR_0_HZ] */
 179 };
 180
 181 struct scc_hardware {
 182         char *name;
 183         int io_region;
 184         int io_delta;
 185         int io_size;
 186         int num_devs;
 187         int scc_offset;
 188         int tmr_offset;
 189         int tmr_hz;
 190         int pclk_hz;
 191 };
 192
 193 struct scc_priv {
 194         int type;
 195         int chip;
 196         struct net_device *dev;
 197         struct scc_info *info;
 198         struct net_device_stats stats;
 199         int channel;
 200         int card_base, scc_cmd, scc_data;
 201         int tmr_cnt, tmr_ctrl, tmr_mode;
 202         struct scc_param param;
 203         char rx_buf[NUM_RX_BUF][BUF_SIZE];
 204         int rx_len[NUM_RX_BUF];
 205         int rx_ptr;
 206         struct work_struct rx_work;
 207         int rx_head, rx_tail, rx_count;
 208         int rx_over;
 209         char tx_buf[NUM_TX_BUF][BUF_SIZE];
 210         int tx_len[NUM_TX_BUF];
 211         int tx_ptr;
 212         int tx_head, tx_tail, tx_count;
 213         int state;
 214         unsigned long tx_start;
 215         int rr0;
 216         spinlock_t *register_lock;      /* Per scc_info */
 217         spinlock_t ring_lock;
 218 };
 219
 220 struct scc_info {
 221         int irq_used;
 222         int twin_serial_cfg;
 223         struct net_device *dev[2];
 224         struct scc_priv priv[2];
 225         struct scc_info *next;
 226         spinlock_t register_lock;       /* Per device register lock */
 227 };
 228
 229
 230 /* Function declarations */
 231 static int setup_adapter(int card_base, int type, int n) __init;
 232
 233 static void write_scc(struct scc_priv *priv, int reg, int val);
 234 static void write_scc_data(struct scc_priv *priv, int val, int fast);
 235 static int read_scc(struct scc_priv *priv, int reg);
 236 static int read_scc_data(struct scc_priv *priv);
 237
 238 static int scc_open(struct net_device *dev);
 239 static int scc_close(struct net_device *dev);
 240 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
 241 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev);
 242 static struct net_device_stats *scc_get_stats(struct net_device *dev);
 243 static int scc_set_mac_address(struct net_device *dev, void *sa);
 244
 245 static inline void tx_on(struct scc_priv *priv);
 246 static inline void rx_on(struct scc_priv *priv);
 247 static inline void rx_off(struct scc_priv *priv);
 248 static void start_timer(struct scc_priv *priv, int t, int r15);
 249 static inline unsigned char random(void);
 250
 251 static inline void z8530_isr(struct scc_info *info);
 252 static irqreturn_t scc_isr(int irq, void *dev_id);
 253 static void rx_isr(struct scc_priv *priv);
 254 static void special_condition(struct scc_priv *priv, int rc);
 255 static void rx_bh(struct work_struct *);
 256 static void tx_isr(struct scc_priv *priv);
 257 static void es_isr(struct scc_priv *priv);
 258 static void tm_isr(struct scc_priv *priv);
 259
 260
 261 /* Initialization variables */
 262
 263 static int io[MAX_NUM_DEVS] __initdata = { 0, };
 264
 265 /* Beware! hw[] is also used in cleanup_module(). */
 266 static struct scc_hardware hw[NUM_TYPES] __initdata_or_module = HARDWARE;
 267
 268
 269 /* Global variables */
 270
 271 static struct scc_info *first;
 272 static unsigned long rand;
 273
 274
 275 MODULE_AUTHOR("Klaus Kudielka");
 276 MODULE_DESCRIPTION("Driver for high-speed SCC boards");
 277 module_param_array(io, int, NULL, 0);
 278 MODULE_LICENSE("GPL");
 279
 280 static void __exit dmascc_exit(void)
 281 {
 282         int i;
 283         struct scc_info *info;
 284
 285         while (first) {
 286                 info = first;
 287
 288                 /* Unregister devices */
 289                 for (i = 0; i < 2; i++)
 290                         unregister_netdev(info->dev[i]);
 291
 292                 /* Reset board */
 293                 if (info->priv[0].type == TYPE_TWIN)
 294                         outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
 295                 write_scc(&info->priv[0], R9, FHWRES);
 296                 release_region(info->dev[0]->base_addr,
 297                                hw[info->priv[0].type].io_size);
 298
 299                 for (i = 0; i < 2; i++)
 300                         free_netdev(info->dev[i]);
 301
 302                 /* Free memory */
 303                 first = info->next;
 304                 kfree(info);
 305         }
 306 }
 307
 308 static int __init dmascc_init(void)
 309 {
 310         int h, i, j, n;
 311         int base[MAX_NUM_DEVS], tcmd[MAX_NUM_DEVS], t0[MAX_NUM_DEVS],
 312             t1[MAX_NUM_DEVS];
 313         unsigned t_val;
 314         unsigned long time, start[MAX_NUM_DEVS], delay[MAX_NUM_DEVS],
 315             counting[MAX_NUM_DEVS];
 316
 317         /* Initialize random number generator */
 318         rand = jiffies;
 319         /* Cards found = 0 */
 320         n = 0;
 321         /* Warning message */
 322         if (!io[0])
 323                 printk(KERN_INFO "dmascc: autoprobing (dangerous)\n");
 324
 325         /* Run autodetection for each card type */
 326         for (h = 0; h < NUM_TYPES; h++) {
 327
 328                 if (io[0]) {
 329                         /* User-specified I/O address regions */
 330                         for (i = 0; i < hw[h].num_devs; i++)
 331                                 base[i] = 0;
 332                         for (i = 0; i < MAX_NUM_DEVS && io[i]; i++) {
 333                                 j = (io[i] -
 334                                      hw[h].io_region) / hw[h].io_delta;
 335                                 if (j >= 0 && j < hw[h].num_devs
 336                                     && hw[h].io_region +
 337                                     j * hw[h].io_delta == io[i]) {
 338                                         base[j] = io[i];
 339                                 }
 340                         }
 341                 } else {
 342                         /* Default I/O address regions */
 343                         for (i = 0; i < hw[h].num_devs; i++) {
 344                                 base[i] =
 345                                     hw[h].io_region + i * hw[h].io_delta;
 346                         }
 347                 }
 348
 349                 /* Check valid I/O address regions */
 350                 for (i = 0; i < hw[h].num_devs; i++)
 351                         if (base[i]) {
 352                                 if (!request_region
 353                                     (base[i], hw[h].io_size, "dmascc"))
 354                                         base[i] = 0;
 355                                 else {
 356                                         tcmd[i] =
 357                                             base[i] + hw[h].tmr_offset +
 358                                             TMR_CTRL;
 359                                         t0[i] =
 360                                             base[i] + hw[h].tmr_offset +
 361                                             TMR_CNT0;
 362                                         t1[i] =
 363                                             base[i] + hw[h].tmr_offset +
 364                                             TMR_CNT1;
 365                                 }
 366                         }
 367
 368                 /* Start timers */
 369                 for (i = 0; i < hw[h].num_devs; i++)
 370                         if (base[i]) {
 371                                 /* Timer 0: LSB+MSB, Mode 3, TMR_0_HZ */
 372                                 outb(0x36, tcmd[i]);
 373                                 outb((hw[h].tmr_hz / TMR_0_HZ) & 0xFF,
 374                                      t0[i]);
 375                                 outb((hw[h].tmr_hz / TMR_0_HZ) >> 8,
 376                                      t0[i]);
 377                                 /* Timer 1: LSB+MSB, Mode 0, HZ/10 */
 378                                 outb(0x70, tcmd[i]);
 379                                 outb((TMR_0_HZ / HZ * 10) & 0xFF, t1[i]);
 380                                 outb((TMR_0_HZ / HZ * 10) >> 8, t1[i]);
 381                                 start[i] = jiffies;
 382                                 delay[i] = 0;
 383                                 counting[i] = 1;
 384                                 /* Timer 2: LSB+MSB, Mode 0 */
 385                                 outb(0xb0, tcmd[i]);
 386                         }
 387                 time = jiffies;
 388                 /* Wait until counter registers are loaded */
 389                 udelay(2000000 / TMR_0_HZ);
 390
 391                 /* Timing loop */
 392                 while (jiffies - time < 13) {
 393                         for (i = 0; i < hw[h].num_devs; i++)
 394                                 if (base[i] && counting[i]) {
 395                                         /* Read back Timer 1: latch; read LSB; read MSB */
 396                                         outb(0x40, tcmd[i]);
 397                                         t_val =
 398                                             inb(t1[i]) + (inb(t1[i]) << 8);
 399                                         /* Also check whether counter did wrap */
 400                                         if (t_val == 0
 401                                             || t_val > TMR_0_HZ / HZ * 10)
 402                                                 counting[i] = 0;
 403                                         delay[i] = jiffies - start[i];
 404                                 }
 405                 }
 406
 407                 /* Evaluate measurements */
 408                 for (i = 0; i < hw[h].num_devs; i++)
 409                         if (base[i]) {
 410                                 if ((delay[i] >= 9 && delay[i] <= 11) &&
 411                                     /* Ok, we have found an adapter */
 412                                     (setup_adapter(base[i], h, n) == 0))
 413                                         n++;
 414                                 else
 415                                         release_region(base[i],
 416                                                        hw[h].io_size);
 417                         }
 418
 419         }                       /* NUM_TYPES */
 420
 421         /* If any adapter was successfully initialized, return ok */
 422         if (n)
 423                 return 0;
 424
 425         /* If no adapter found, return error */
 426         printk(KERN_INFO "dmascc: no adapters found\n");
 427         return -EIO;
 428 }
 429
 430 module_init(dmascc_init);
 431 module_exit(dmascc_exit);
 432
 433 static void __init dev_setup(struct net_device *dev)
 434 {
 435         dev->type = ARPHRD_AX25;
 436         dev->hard_header_len = AX25_MAX_HEADER_LEN;
 437         dev->mtu = 1500;
 438         dev->addr_len = AX25_ADDR_LEN;
 439         dev->tx_queue_len = 64;
 440         memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
 441         memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN);
 442 }
 443
 444 static int __init setup_adapter(int card_base, int type, int n)
 445 {
 446         int i, irq, chip;
 447         struct scc_info *info;
 448         struct net_device *dev;
 449         struct scc_priv *priv;
 450         unsigned long time;
 451         unsigned int irqs;
 452         int tmr_base = card_base + hw[type].tmr_offset;
 453         int scc_base = card_base + hw[type].scc_offset;
 454         char *chipnames[] = CHIPNAMES;
 455
 456         /* Allocate memory */
 457         info = kmalloc(sizeof(struct scc_info), GFP_KERNEL | GFP_DMA);
 458         if (!info) {
 459                 printk(KERN_ERR "dmascc: "
 460                        "could not allocate memory for %s at %#3x\n",
 461                        hw[type].name, card_base);
 462                 goto out;
 463         }
 464
 465         /* Initialize what is necessary for write_scc and write_scc_data */
 466         memset(info, 0, sizeof(struct scc_info));
 467
 468         info->dev[0] = alloc_netdev(0, "", dev_setup);
 469         if (!info->dev[0]) {
 470                 printk(KERN_ERR "dmascc: "
 471                        "could not allocate memory for %s at %#3x\n",
 472                        hw[type].name, card_base);
 473                 goto out1;
 474         }
 475
 476         info->dev[1] = alloc_netdev(0, "", dev_setup);
 477         if (!info->dev[1]) {
 478                 printk(KERN_ERR "dmascc: "
 479                        "could not allocate memory for %s at %#3x\n",
 480                        hw[type].name, card_base);
 481                 goto out2;
 482         }
 483         spin_lock_init(&info->register_lock);
 484
 485         priv = &info->priv[0];
 486         priv->type = type;
 487         priv->card_base = card_base;
 488         priv->scc_cmd = scc_base + SCCA_CMD;
 489         priv->scc_data = scc_base + SCCA_DATA;
 490         priv->register_lock = &info->register_lock;
 491
 492         /* Reset SCC */
 493         write_scc(priv, R9, FHWRES | MIE | NV);
 494
 495         /* Determine type of chip by enabling SDLC/HDLC enhancements */
 496         write_scc(priv, R15, SHDLCE);
 497         if (!read_scc(priv, R15)) {
 498                 /* WR7' not present. This is an ordinary Z8530 SCC. */
 499                 chip = Z8530;
 500         } else {
 501                 /* Put one character in TX FIFO */
 502                 write_scc_data(priv, 0, 0);
 503                 if (read_scc(priv, R0) & Tx_BUF_EMP) {
 504                         /* TX FIFO not full. This is a Z85230 ESCC with a 4-byte FIFO. */
 505                         chip = Z85230;
 506                 } else {
 507                         /* TX FIFO full. This is a Z85C30 SCC with a 1-byte FIFO. */
 508                         chip = Z85C30;
 509                 }
 510         }
 511         write_scc(priv, R15, 0);
 512
 513         /* Start IRQ auto-detection */
 514         irqs = probe_irq_on();
 515
 516         /* Enable interrupts */
 517         if (type == TYPE_TWIN) {
 518                 outb(0, card_base + TWIN_DMA_CFG);
 519                 inb(card_base + TWIN_CLR_TMR1);
 520                 inb(card_base + TWIN_CLR_TMR2);
 521                 info->twin_serial_cfg = TWIN_EI;
 522                 outb(info->twin_serial_cfg, card_base + TWIN_SERIAL_CFG);
 523         } else {
 524                 write_scc(priv, R15, CTSIE);
 525                 write_scc(priv, R0, RES_EXT_INT);
 526                 write_scc(priv, R1, EXT_INT_ENAB);
 527         }
 528
 529         /* Start timer */
 530         outb(1, tmr_base + TMR_CNT1);
 531         outb(0, tmr_base + TMR_CNT1);
 532
 533         /* Wait and detect IRQ */
 534         time = jiffies;
 535         while (jiffies - time < 2 + HZ / TMR_0_HZ);
 536         irq = probe_irq_off(irqs);
 537
 538         /* Clear pending interrupt, disable interrupts */
 539         if (type == TYPE_TWIN) {
 540                 inb(card_base + TWIN_CLR_TMR1);
 541         } else {
 542                 write_scc(priv, R1, 0);
 543                 write_scc(priv, R15, 0);
 544                 write_scc(priv, R0, RES_EXT_INT);
 545         }
 546
 547         if (irq <= 0) {
 548                 printk(KERN_ERR
 549                        "dmascc: could not find irq of %s at %#3x (irq=%d)\n",
 550                        hw[type].name, card_base, irq);
 551                 goto out3;
 552         }
 553
 554         /* Set up data structures */
 555         for (i = 0; i < 2; i++) {
 556                 dev = info->dev[i];
 557                 priv = &info->priv[i];
 558                 priv->type = type;
 559                 priv->chip = chip;
 560                 priv->dev = dev;
 561                 priv->info = info;
 562                 priv->channel = i;
 563                 spin_lock_init(&priv->ring_lock);
 564                 priv->register_lock = &info->register_lock;
 565                 priv->card_base = card_base;
 566                 priv->scc_cmd = scc_base + (i ? SCCB_CMD : SCCA_CMD);
 567                 priv->scc_data = scc_base + (i ? SCCB_DATA : SCCA_DATA);
 568                 priv->tmr_cnt = tmr_base + (i ? TMR_CNT2 : TMR_CNT1);
 569                 priv->tmr_ctrl = tmr_base + TMR_CTRL;
 570                 priv->tmr_mode = i ? 0xb0 : 0x70;
 571                 priv->param.pclk_hz = hw[type].pclk_hz;
 572                 priv->param.brg_tc = -1;
 573                 priv->param.clocks = TCTRxCP | RCRTxCP;
 574                 priv->param.persist = 256;
 575                 priv->param.dma = -1;
 576                 INIT_WORK(&priv->rx_work, rx_bh);
 577                 dev->priv = priv;
 578                 sprintf(dev->name, "dmascc%i", 2 * n + i);
 579                 dev->base_addr = card_base;
 580                 dev->irq = irq;
 581                 dev->open = scc_open;
 582                 dev->stop = scc_close;
 583                 dev->do_ioctl = scc_ioctl;
 584                 dev->hard_start_xmit = scc_send_packet;
 585                 dev->get_stats = scc_get_stats;
 586                 dev->hard_header = ax25_hard_header;
 587                 dev->rebuild_header = ax25_rebuild_header;
 588                 dev->set_mac_address = scc_set_mac_address;
 589         }
 590         if (register_netdev(info->dev[0])) {
 591                 printk(KERN_ERR "dmascc: could not register %s\n",
 592                        info->dev[0]->name);
 593                 goto out3;
 594         }
 595         if (register_netdev(info->dev[1])) {
 596                 printk(KERN_ERR "dmascc: could not register %s\n",
 597                        info->dev[1]->name);
 598                 goto out4;
 599         }
 600
 601
 602         info->next = first;
 603         first = info;
 604         printk(KERN_INFO "dmascc: found %s (%s) at %#3x, irq %d\n",
 605                hw[type].name, chipnames[chip], card_base, irq);
 606         return 0;
 607
 608       out4:
 609         unregister_netdev(info->dev[0]);
 610       out3:
 611         if (info->priv[0].type == TYPE_TWIN)
 612                 outb(0, info->dev[0]->base_addr + TWIN_SERIAL_CFG);
 613         write_scc(&info->priv[0], R9, FHWRES);
 614         free_netdev(info->dev[1]);
 615       out2:
 616         free_netdev(info->dev[0]);
 617       out1:
 618         kfree(info);
 619       out:
 620         return -1;
 621 }
 622
 623
 624 /* Driver functions */
 625
 626 static void write_scc(struct scc_priv *priv, int reg, int val)
 627 {
 628         unsigned long flags;
 629         switch (priv->type) {
 630         case TYPE_S5:
 631                 if (reg)
 632                         outb(reg, priv->scc_cmd);
 633                 outb(val, priv->scc_cmd);
 634                 return;
 635         case TYPE_TWIN:
 636                 if (reg)
 637                         outb_p(reg, priv->scc_cmd);
 638                 outb_p(val, priv->scc_cmd);
 639                 return;
 640         default:
 641                 spin_lock_irqsave(priv->register_lock, flags);
 642                 outb_p(0, priv->card_base + PI_DREQ_MASK);
 643                 if (reg)
 644                         outb_p(reg, priv->scc_cmd);
 645                 outb_p(val, priv->scc_cmd);
 646                 outb(1, priv->card_base + PI_DREQ_MASK);
 647                 spin_unlock_irqrestore(priv->register_lock, flags);
 648                 return;
 649         }
 650 }
 651
 652
 653 static void write_scc_data(struct scc_priv *priv, int val, int fast)
 654 {
 655         unsigned long flags;
 656         switch (priv->type) {
 657         case TYPE_S5:
 658                 outb(val, priv->scc_data);
 659                 return;
 660         case TYPE_TWIN:
 661                 outb_p(val, priv->scc_data);
 662                 return;
 663         default:
 664                 if (fast)
 665                         outb_p(val, priv->scc_data);
 666                 else {
 667                         spin_lock_irqsave(priv->register_lock, flags);
 668                         outb_p(0, priv->card_base + PI_DREQ_MASK);
 669                         outb_p(val, priv->scc_data);
 670                         outb(1, priv->card_base + PI_DREQ_MASK);
 671                         spin_unlock_irqrestore(priv->register_lock, flags);
 672                 }
 673                 return;
 674         }
 675 }
 676
 677
 678 static int read_scc(struct scc_priv *priv, int reg)
 679 {
 680         int rc;
 681         unsigned long flags;
 682         switch (priv->type) {
 683         case TYPE_S5:
 684                 if (reg)
 685                         outb(reg, priv->scc_cmd);
 686                 return inb(priv->scc_cmd);
 687         case TYPE_TWIN:
 688                 if (reg)
 689                         outb_p(reg, priv->scc_cmd);
 690                 return inb_p(priv->scc_cmd);
 691         default:
 692                 spin_lock_irqsave(priv->register_lock, flags);
 693                 outb_p(0, priv->card_base + PI_DREQ_MASK);
 694                 if (reg)
 695                         outb_p(reg, priv->scc_cmd);
 696                 rc = inb_p(priv->scc_cmd);
 697                 outb(1, priv->card_base + PI_DREQ_MASK);
 698                 spin_unlock_irqrestore(priv->register_lock, flags);
 699                 return rc;
 700         }
 701 }
 702
 703
 704 static int read_scc_data(struct scc_priv *priv)
 705 {
 706         int rc;
 707         unsigned long flags;
 708         switch (priv->type) {
 709         case TYPE_S5:
 710                 return inb(priv->scc_data);
 711         case TYPE_TWIN:
 712                 return inb_p(priv->scc_data);
 713         default:
 714                 spin_lock_irqsave(priv->register_lock, flags);
 715                 outb_p(0, priv->card_base + PI_DREQ_MASK);
 716                 rc = inb_p(priv->scc_data);
 717                 outb(1, priv->card_base + PI_DREQ_MASK);
 718                 spin_unlock_irqrestore(priv->register_lock, flags);
 719                 return rc;
 720         }
 721 }
 722
 723
 724 static int scc_open(struct net_device *dev)
 725 {
 726         struct scc_priv *priv = dev->priv;
 727         struct scc_info *info = priv->info;
 728         int card_base = priv->card_base;
 729
 730         /* Request IRQ if not already used by other channel */
 731         if (!info->irq_used) {
 732                 if (request_irq(dev->irq, scc_isr, 0, "dmascc", info)) {
 733                         return -EAGAIN;
 734                 }
 735         }
 736         info->irq_used++;
 737
 738         /* Request DMA if required */
 739         if (priv->param.dma >= 0) {
 740                 if (request_dma(priv->param.dma, "dmascc")) {
 741                         if (--info->irq_used == 0)
 742                                 free_irq(dev->irq, info);
 743                         return -EAGAIN;
 744                 } else {
 745                         unsigned long flags = claim_dma_lock();
 746                         clear_dma_ff(priv->param.dma);
 747                         release_dma_lock(flags);
 748                 }
 749         }
 750
 751         /* Initialize local variables */
 752         priv->rx_ptr = 0;
 753         priv->rx_over = 0;
 754         priv->rx_head = priv->rx_tail = priv->rx_count = 0;
 755         priv->state = IDLE;
 756         priv->tx_head = priv->tx_tail = priv->tx_count = 0;
 757         priv->tx_ptr = 0;
 758
 759         /* Reset channel */
 760         write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
 761         /* X1 clock, SDLC mode */
 762         write_scc(priv, R4, SDLC | X1CLK);
 763         /* DMA */
 764         write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
 765         /* 8 bit RX char, RX disable */
 766         write_scc(priv, R3, Rx8);
 767         /* 8 bit TX char, TX disable */
 768         write_scc(priv, R5, Tx8);
 769         /* SDLC address field */
 770         write_scc(priv, R6, 0);
 771         /* SDLC flag */
 772         write_scc(priv, R7, FLAG);
 773         switch (priv->chip) {
 774         case Z85C30:
 775                 /* Select WR7' */
 776                 write_scc(priv, R15, SHDLCE);
 777                 /* Auto EOM reset */
 778                 write_scc(priv, R7, AUTOEOM);
 779                 write_scc(priv, R15, 0);
 780                 break;
 781         case Z85230:
 782                 /* Select WR7' */
 783                 write_scc(priv, R15, SHDLCE);
 784                 /* The following bits are set (see 2.5.2.1):
 785                    - Automatic EOM reset
 786                    - Interrupt request if RX FIFO is half full
 787                    This bit should be ignored in DMA mode (according to the
 788                    documentation), but actually isn't. The receiver doesn't work if
 789                    it is set. Thus, we have to clear it in DMA mode.
 790                    - Interrupt/DMA request if TX FIFO is completely empty
 791                    a) If set, the ESCC behaves as if it had no TX FIFO (Z85C30
 792                    compatibility).
 793                    b) If cleared, DMA requests may follow each other very quickly,
 794                    filling up the TX FIFO.
 795                    Advantage: TX works even in case of high bus latency.
 796                    Disadvantage: Edge-triggered DMA request circuitry may miss
 797                    a request. No more data is delivered, resulting
 798                    in a TX FIFO underrun.
 799                    Both PI2 and S5SCC/DMA seem to work fine with TXFIFOE cleared.
 800                    The PackeTwin doesn't. I don't know about the PI, but let's
 801                    assume it behaves like the PI2.
 802                  */
 803                 if (priv->param.dma >= 0) {
 804                         if (priv->type == TYPE_TWIN)
 805                                 write_scc(priv, R7, AUTOEOM | TXFIFOE);
 806                         else
 807                                 write_scc(priv, R7, AUTOEOM);
 808                 } else {
 809                         write_scc(priv, R7, AUTOEOM | RXFIFOH);
 810                 }
 811                 write_scc(priv, R15, 0);
 812                 break;
 813         }
 814         /* Preset CRC, NRZ(I) encoding */
 815         write_scc(priv, R10, CRCPS | (priv->param.nrzi ? NRZI : NRZ));
 816
 817         /* Configure baud rate generator */
 818         if (priv->param.brg_tc >= 0) {
 819                 /* Program BR generator */
 820                 write_scc(priv, R12, priv->param.brg_tc & 0xFF);
 821                 write_scc(priv, R13, (priv->param.brg_tc >> 8) & 0xFF);
 822                 /* BRG source = SYS CLK; enable BRG; DTR REQ function (required by
 823                    PackeTwin, not connected on the PI2); set DPLL source to BRG */
 824                 write_scc(priv, R14, SSBR | DTRREQ | BRSRC | BRENABL);
 825                 /* Enable DPLL */
 826                 write_scc(priv, R14, SEARCH | DTRREQ | BRSRC | BRENABL);
 827         } else {
 828                 /* Disable BR generator */
 829                 write_scc(priv, R14, DTRREQ | BRSRC);
 830         }
 831
 832         /* Configure clocks */
 833         if (priv->type == TYPE_TWIN) {
 834                 /* Disable external TX clock receiver */
 835                 outb((info->twin_serial_cfg &=
 836                       ~(priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
 837                      card_base + TWIN_SERIAL_CFG);
 838         }
 839         write_scc(priv, R11, priv->param.clocks);
 840         if ((priv->type == TYPE_TWIN) && !(priv->param.clocks & TRxCOI)) {
 841                 /* Enable external TX clock receiver */
 842                 outb((info->twin_serial_cfg |=
 843                       (priv->channel ? TWIN_EXTCLKB : TWIN_EXTCLKA)),
 844                      card_base + TWIN_SERIAL_CFG);
 845         }
 846
 847         /* Configure PackeTwin */
 848         if (priv->type == TYPE_TWIN) {
 849                 /* Assert DTR, enable interrupts */
 850                 outb((info->twin_serial_cfg |= TWIN_EI |
 851                       (priv->channel ? TWIN_DTRB_ON : TWIN_DTRA_ON)),
 852                      card_base + TWIN_SERIAL_CFG);
 853         }
 854
 855         /* Read current status */
 856         priv->rr0 = read_scc(priv, R0);
 857         /* Enable DCD interrupt */
 858         write_scc(priv, R15, DCDIE);
 859
 860         netif_start_queue(dev);
 861
 862         return 0;
 863 }
 864
 865
 866 static int scc_close(struct net_device *dev)
 867 {
 868         struct scc_priv *priv = dev->priv;
 869         struct scc_info *info = priv->info;
 870         int card_base = priv->card_base;
 871
 872         netif_stop_queue(dev);
 873
 874         if (priv->type == TYPE_TWIN) {
 875                 /* Drop DTR */
 876                 outb((info->twin_serial_cfg &=
 877                       (priv->channel ? ~TWIN_DTRB_ON : ~TWIN_DTRA_ON)),
 878                      card_base + TWIN_SERIAL_CFG);
 879         }
 880
 881         /* Reset channel, free DMA and IRQ */
 882         write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV);
 883         if (priv->param.dma >= 0) {
 884                 if (priv->type == TYPE_TWIN)
 885                         outb(0, card_base + TWIN_DMA_CFG);
 886                 free_dma(priv->param.dma);
 887         }
 888         if (--info->irq_used == 0)
 889                 free_irq(dev->irq, info);
 890
 891         return 0;
 892 }
 893
 894
 895 static int scc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 896 {
 897         struct scc_priv *priv = dev->priv;
 898
 899         switch (cmd) {
 900         case SIOCGSCCPARAM:
 901                 if (copy_to_user
 902                     (ifr->ifr_data, &priv->param,
 903                      sizeof(struct scc_param)))
 904                         return -EFAULT;
 905                 return 0;
 906         case SIOCSSCCPARAM:
 907                 if (!capable(CAP_NET_ADMIN))
 908                         return -EPERM;
 909                 if (netif_running(dev))
 910                         return -EAGAIN;
 911                 if (copy_from_user
 912                     (&priv->param, ifr->ifr_data,
 913                      sizeof(struct scc_param)))
 914                         return -EFAULT;
 915                 return 0;
 916         default:
 917                 return -EINVAL;
 918         }
 919 }
 920
 921
 922 static int scc_send_packet(struct sk_buff *skb, struct net_device *dev)
 923 {
 924         struct scc_priv *priv = dev->priv;
 925         unsigned long flags;
 926         int i;
 927
 928         /* Temporarily stop the scheduler feeding us packets */
 929         netif_stop_queue(dev);
 930
 931         /* Transfer data to DMA buffer */
 932         i = priv->tx_head;
 933         skb_copy_from_linear_data_offset(skb, 1, priv->tx_buf[i], skb->len - 1);
 934         priv->tx_len[i] = skb->len - 1;
 935
 936         /* Clear interrupts while we touch our circular buffers */
 937
 938         spin_lock_irqsave(&priv->ring_lock, flags);
 939         /* Move the ring buffer's head */
 940         priv->tx_head = (i + 1) % NUM_TX_BUF;
 941         priv->tx_count++;
 942
 943         /* If we just filled up the last buffer, leave queue stopped.
 944            The higher layers must wait until we have a DMA buffer
 945            to accept the data. */
 946         if (priv->tx_count < NUM_TX_BUF)
 947                 netif_wake_queue(dev);
 948
 949         /* Set new TX state */
 950         if (priv->state == IDLE) {
 951                 /* Assert RTS, start timer */
 952                 priv->state = TX_HEAD;
 953                 priv->tx_start = jiffies;
 954                 write_scc(priv, R5, TxCRC_ENAB | RTS | TxENAB | Tx8);
 955                 write_scc(priv, R15, 0);
 956                 start_timer(priv, priv->param.txdelay, 0);
 957         }
 958
 959         /* Turn interrupts back on and free buffer */
 960         spin_unlock_irqrestore(&priv->ring_lock, flags);
 961         dev_kfree_skb(skb);
 962
 963         return 0;
 964 }
 965
 966
 967 static struct net_device_stats *scc_get_stats(struct net_device *dev)
 968 {
 969         struct scc_priv *priv = dev->priv;
 970
 971         return &priv->stats;
 972 }
 973
 974
 975 static int scc_set_mac_address(struct net_device *dev, void *sa)
 976 {
 977         memcpy(dev->dev_addr, ((struct sockaddr *) sa)->sa_data,
 978                dev->addr_len);
 979         return 0;
 980 }
 981
 982
 983 static inline void tx_on(struct scc_priv *priv)
 984 {
 985         int i, n;
 986         unsigned long flags;
 987
 988         if (priv->param.dma >= 0) {
 989                 n = (priv->chip == Z85230) ? 3 : 1;
 990                 /* Program DMA controller */
 991                 flags = claim_dma_lock();
 992                 set_dma_mode(priv->param.dma, DMA_MODE_WRITE);
 993                 set_dma_addr(priv->param.dma,
 994                              (int) priv->tx_buf[priv->tx_tail] + n);
 995                 set_dma_count(priv->param.dma,
 996                               priv->tx_len[priv->tx_tail] - n);
 997                 release_dma_lock(flags);
 998                 /* Enable TX underrun interrupt */
 999                 write_scc(priv, R15, TxUIE);
1000                 /* Configure DREQ */
1001                 if (priv->type == TYPE_TWIN)
1002                         outb((priv->param.dma ==
1003                               1) ? TWIN_DMA_HDX_T1 : TWIN_DMA_HDX_T3,
1004                              priv->card_base + TWIN_DMA_CFG);
1005                 else
1006                         write_scc(priv, R1,
1007                                   EXT_INT_ENAB | WT_FN_RDYFN |
1008                                   WT_RDY_ENAB);
1009                 /* Write first byte(s) */
1010                 spin_lock_irqsave(priv->register_lock, flags);
1011                 for (i = 0; i < n; i++)
1012                         write_scc_data(priv,
1013                                        priv->tx_buf[priv->tx_tail][i], 1);
1014                 enable_dma(priv->param.dma);
1015                 spin_unlock_irqrestore(priv->register_lock, flags);
1016         } else {
1017                 write_scc(priv, R15, TxUIE);
1018                 write_scc(priv, R1,
1019                           EXT_INT_ENAB | WT_FN_RDYFN | TxINT_ENAB);
1020                 tx_isr(priv);
1021         }
1022         /* Reset EOM latch if we do not have the AUTOEOM feature */
1023         if (priv->chip == Z8530)
1024                 write_scc(priv, R0, RES_EOM_L);
1025 }
1026
1027
1028 static inline void rx_on(struct scc_priv *priv)
1029 {
1030         unsigned long flags;
1031
1032         /* Clear RX FIFO */
1033         while (read_scc(priv, R0) & Rx_CH_AV)
1034                 read_scc_data(priv);
1035         priv->rx_over = 0;
1036         if (priv->param.dma >= 0) {
1037                 /* Program DMA controller */
1038                 flags = claim_dma_lock();
1039                 set_dma_mode(priv->param.dma, DMA_MODE_READ);
1040                 set_dma_addr(priv->param.dma,
1041                              (int) priv->rx_buf[priv->rx_head]);
1042                 set_dma_count(priv->param.dma, BUF_SIZE);
1043                 release_dma_lock(flags);
1044                 enable_dma(priv->param.dma);
1045                 /* Configure PackeTwin DMA */
1046                 if (priv->type == TYPE_TWIN) {
1047                         outb((priv->param.dma ==
1048                               1) ? TWIN_DMA_HDX_R1 : TWIN_DMA_HDX_R3,
1049                              priv->card_base + TWIN_DMA_CFG);
1050                 }
1051                 /* Sp. cond. intr. only, ext int enable, RX DMA enable */
1052                 write_scc(priv, R1, EXT_INT_ENAB | INT_ERR_Rx |
1053                           WT_RDY_RT | WT_FN_RDYFN | WT_RDY_ENAB);
1054         } else {
1055                 /* Reset current frame */
1056                 priv->rx_ptr = 0;
1057                 /* Intr. on all Rx characters and Sp. cond., ext int enable */
1058                 write_scc(priv, R1, EXT_INT_ENAB | INT_ALL_Rx | WT_RDY_RT |
1059                           WT_FN_RDYFN);
1060         }
1061         write_scc(priv, R0, ERR_RES);
1062         write_scc(priv, R3, RxENABLE | Rx8 | RxCRC_ENAB);
1063 }
1064
1065
1066 static inline void rx_off(struct scc_priv *priv)
1067 {
1068         /* Disable receiver */
1069         write_scc(priv, R3, Rx8);
1070         /* Disable DREQ / RX interrupt */
1071         if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1072                 outb(0, priv->card_base + TWIN_DMA_CFG);
1073         else
1074                 write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1075         /* Disable DMA */
1076         if (priv->param.dma >= 0)
1077                 disable_dma(priv->param.dma);
1078 }
1079
1080
1081 static void start_timer(struct scc_priv *priv, int t, int r15)
1082 {
1083         unsigned long flags;
1084
1085         outb(priv->tmr_mode, priv->tmr_ctrl);
1086         if (t == 0) {
1087                 tm_isr(priv);
1088         } else if (t > 0) {
1089                 save_flags(flags);
1090                 cli();
1091                 outb(t & 0xFF, priv->tmr_cnt);
1092                 outb((t >> 8) & 0xFF, priv->tmr_cnt);
1093                 if (priv->type != TYPE_TWIN) {
1094                         write_scc(priv, R15, r15 | CTSIE);
1095                         priv->rr0 |= CTS;
1096                 }
1097                 restore_flags(flags);
1098         }
1099 }
1100
1101
1102 static inline unsigned char random(void)
1103 {
1104         /* See "Numerical Recipes in C", second edition, p. 284 */
1105         rand = rand * 1664525L + 1013904223L;
1106         return (unsigned char) (rand >> 24);
1107 }
1108
1109 static inline void z8530_isr(struct scc_info *info)
1110 {
1111         int is, i = 100;
1112
1113         while ((is = read_scc(&info->priv[0], R3)) && i--) {
1114                 if (is & CHARxIP) {
1115                         rx_isr(&info->priv[0]);
1116                 } else if (is & CHATxIP) {
1117                         tx_isr(&info->priv[0]);
1118                 } else if (is & CHAEXT) {
1119                         es_isr(&info->priv[0]);
1120                 } else if (is & CHBRxIP) {
1121                         rx_isr(&info->priv[1]);
1122                 } else if (is & CHBTxIP) {
1123                         tx_isr(&info->priv[1]);
1124                 } else {
1125                         es_isr(&info->priv[1]);
1126                 }
1127                 write_scc(&info->priv[0], R0, RES_H_IUS);
1128                 i++;
1129         }
1130         if (i < 0) {
1131                 printk(KERN_ERR "dmascc: stuck in ISR with RR3=0x%02x.\n",
1132                        is);
1133         }
1134         /* Ok, no interrupts pending from this 8530. The INT line should
1135            be inactive now. */
1136 }
1137
1138
1139 static irqreturn_t scc_isr(int irq, void *dev_id)
1140 {
1141         struct scc_info *info = dev_id;
1142
1143         spin_lock(info->priv[0].register_lock);
1144         /* At this point interrupts are enabled, and the interrupt under service
1145            is already acknowledged, but masked off.
1146
1147            Interrupt processing: We loop until we know that the IRQ line is
1148            low. If another positive edge occurs afterwards during the ISR,
1149            another interrupt will be triggered by the interrupt controller
1150            as soon as the IRQ level is enabled again (see asm/irq.h).
1151
1152            Bottom-half handlers will be processed after scc_isr(). This is
1153            important, since we only have small ringbuffers and want new data
1154            to be fetched/delivered immediately. */
1155
1156         if (info->priv[0].type == TYPE_TWIN) {
1157                 int is, card_base = info->priv[0].card_base;
1158                 while ((is = ~inb(card_base + TWIN_INT_REG)) &
1159                        TWIN_INT_MSK) {
1160                         if (is & TWIN_SCC_MSK) {
1161                                 z8530_isr(info);
1162                         } else if (is & TWIN_TMR1_MSK) {
1163                                 inb(card_base + TWIN_CLR_TMR1);
1164                                 tm_isr(&info->priv[0]);
1165                         } else {
1166                                 inb(card_base + TWIN_CLR_TMR2);
1167                                 tm_isr(&info->priv[1]);
1168                         }
1169                 }
1170         } else
1171                 z8530_isr(info);
1172         spin_unlock(info->priv[0].register_lock);
1173         return IRQ_HANDLED;
1174 }
1175
1176
1177 static void rx_isr(struct scc_priv *priv)
1178 {
1179         if (priv->param.dma >= 0) {
1180                 /* Check special condition and perform error reset. See 2.4.7.5. */
1181                 special_condition(priv, read_scc(priv, R1));
1182                 write_scc(priv, R0, ERR_RES);
1183         } else {
1184                 /* Check special condition for each character. Error reset not necessary.
1185                    Same algorithm for SCC and ESCC. See 2.4.7.1 and 2.4.7.4. */
1186                 int rc;
1187                 while (read_scc(priv, R0) & Rx_CH_AV) {
1188                         rc = read_scc(priv, R1);
1189                         if (priv->rx_ptr < BUF_SIZE)
1190                                 priv->rx_buf[priv->rx_head][priv->
1191                                                             rx_ptr++] =
1192                                     read_scc_data(priv);
1193                         else {
1194                                 priv->rx_over = 2;
1195                                 read_scc_data(priv);
1196                         }
1197                         special_condition(priv, rc);
1198                 }
1199         }
1200 }
1201
1202
1203 static void special_condition(struct scc_priv *priv, int rc)
1204 {
1205         int cb;
1206         unsigned long flags;
1207
1208         /* See Figure 2-15. Only overrun and EOF need to be checked. */
1209
1210         if (rc & Rx_OVR) {
1211                 /* Receiver overrun */
1212                 priv->rx_over = 1;
1213                 if (priv->param.dma < 0)
1214                         write_scc(priv, R0, ERR_RES);
1215         } else if (rc & END_FR) {
1216                 /* End of frame. Get byte count */
1217                 if (priv->param.dma >= 0) {
1218                         flags = claim_dma_lock();
1219                         cb = BUF_SIZE - get_dma_residue(priv->param.dma) -
1220                             2;
1221                         release_dma_lock(flags);
1222                 } else {
1223                         cb = priv->rx_ptr - 2;
1224                 }
1225                 if (priv->rx_over) {
1226                         /* We had an overrun */
1227                         priv->stats.rx_errors++;
1228                         if (priv->rx_over == 2)
1229                                 priv->stats.rx_length_errors++;
1230                         else
1231                                 priv->stats.rx_fifo_errors++;
1232                         priv->rx_over = 0;
1233                 } else if (rc & CRC_ERR) {
1234                         /* Count invalid CRC only if packet length >= minimum */
1235                         if (cb >= 15) {
1236                                 priv->stats.rx_errors++;
1237                                 priv->stats.rx_crc_errors++;
1238                         }
1239                 } else {
1240                         if (cb >= 15) {
1241                                 if (priv->rx_count < NUM_RX_BUF - 1) {
1242                                         /* Put good frame in FIFO */
1243                                         priv->rx_len[priv->rx_head] = cb;
1244                                         priv->rx_head =
1245                                             (priv->rx_head +
1246                                              1) % NUM_RX_BUF;
1247                                         priv->rx_count++;
1248                                         schedule_work(&priv->rx_work);
1249                                 } else {
1250                                         priv->stats.rx_errors++;
1251                                         priv->stats.rx_over_errors++;
1252                                 }
1253                         }
1254                 }
1255                 /* Get ready for new frame */
1256                 if (priv->param.dma >= 0) {
1257                         flags = claim_dma_lock();
1258                         set_dma_addr(priv->param.dma,
1259                                      (int) priv->rx_buf[priv->rx_head]);
1260                         set_dma_count(priv->param.dma, BUF_SIZE);
1261                         release_dma_lock(flags);
1262                 } else {
1263                         priv->rx_ptr = 0;
1264                 }
1265         }
1266 }
1267
1268
1269 static void rx_bh(struct work_struct *ugli_api)
1270 {
1271         struct scc_priv *priv = container_of(ugli_api, struct scc_priv, rx_work);
1272         int i = priv->rx_tail;
1273         int cb;
1274         unsigned long flags;
1275         struct sk_buff *skb;
1276         unsigned char *data;
1277
1278         spin_lock_irqsave(&priv->ring_lock, flags);
1279         while (priv->rx_count) {
1280                 spin_unlock_irqrestore(&priv->ring_lock, flags);
1281                 cb = priv->rx_len[i];
1282                 /* Allocate buffer */
1283                 skb = dev_alloc_skb(cb + 1);
1284                 if (skb == NULL) {
1285                         /* Drop packet */
1286                         priv->stats.rx_dropped++;
1287                 } else {
1288                         /* Fill buffer */
1289                         data = skb_put(skb, cb + 1);
1290                         data[0] = 0;
1291                         memcpy(&data[1], priv->rx_buf[i], cb);
1292                         skb->protocol = ax25_type_trans(skb, priv->dev);
1293                         netif_rx(skb);
1294                         priv->dev->last_rx = jiffies;
1295                         priv->stats.rx_packets++;
1296                         priv->stats.rx_bytes += cb;
1297                 }
1298                 spin_lock_irqsave(&priv->ring_lock, flags);
1299                 /* Move tail */
1300                 priv->rx_tail = i = (i + 1) % NUM_RX_BUF;
1301                 priv->rx_count--;
1302         }
1303         spin_unlock_irqrestore(&priv->ring_lock, flags);
1304 }
1305
1306
1307 static void tx_isr(struct scc_priv *priv)
1308 {
1309         int i = priv->tx_tail, p = priv->tx_ptr;
1310
1311         /* Suspend TX interrupts if we don't want to send anything.
1312            See Figure 2-22. */
1313         if (p == priv->tx_len[i]) {
1314                 write_scc(priv, R0, RES_Tx_P);
1315                 return;
1316         }
1317
1318         /* Write characters */
1319         while ((read_scc(priv, R0) & Tx_BUF_EMP) && p < priv->tx_len[i]) {
1320                 write_scc_data(priv, priv->tx_buf[i][p++], 0);
1321         }
1322
1323         /* Reset EOM latch of Z8530 */
1324         if (!priv->tx_ptr && p && priv->chip == Z8530)
1325                 write_scc(priv, R0, RES_EOM_L);
1326
1327         priv->tx_ptr = p;
1328 }
1329
1330
1331 static void es_isr(struct scc_priv *priv)
1332 {
1333         int i, rr0, drr0, res;
1334         unsigned long flags;
1335
1336         /* Read status, reset interrupt bit (open latches) */
1337         rr0 = read_scc(priv, R0);
1338         write_scc(priv, R0, RES_EXT_INT);
1339         drr0 = priv->rr0 ^ rr0;
1340         priv->rr0 = rr0;
1341
1342         /* Transmit underrun (2.4.9.6). We can't check the TxEOM flag, since
1343            it might have already been cleared again by AUTOEOM. */
1344         if (priv->state == TX_DATA) {
1345                 /* Get remaining bytes */
1346                 i = priv->tx_tail;
1347                 if (priv->param.dma >= 0) {
1348                         disable_dma(priv->param.dma);
1349                         flags = claim_dma_lock();
1350                         res = get_dma_residue(priv->param.dma);
1351                         release_dma_lock(flags);
1352                 } else {
1353                         res = priv->tx_len[i] - priv->tx_ptr;
1354                         priv->tx_ptr = 0;
1355                 }
1356                 /* Disable DREQ / TX interrupt */
1357                 if (priv->param.dma >= 0 && priv->type == TYPE_TWIN)
1358                         outb(0, priv->card_base + TWIN_DMA_CFG);
1359                 else
1360                         write_scc(priv, R1, EXT_INT_ENAB | WT_FN_RDYFN);
1361                 if (res) {
1362                         /* Update packet statistics */
1363                         priv->stats.tx_errors++;
1364                         priv->stats.tx_fifo_errors++;
1365                         /* Other underrun interrupts may already be waiting */
1366                         write_scc(priv, R0, RES_EXT_INT);
1367                         write_scc(priv, R0, RES_EXT_INT);
1368                 } else {
1369                         /* Update packet statistics */
1370                         priv->stats.tx_packets++;
1371                         priv->stats.tx_bytes += priv->tx_len[i];
1372                         /* Remove frame from FIFO */
1373                         priv->tx_tail = (i + 1) % NUM_TX_BUF;
1374                         priv->tx_count--;
1375                         /* Inform upper layers */
1376                         netif_wake_queue(priv->dev);
1377                 }
1378                 /* Switch state */
1379                 write_scc(priv, R15, 0);
1380                 if (priv->tx_count &&
1381                     (jiffies - priv->tx_start) < priv->param.txtimeout) {
1382                         priv->state = TX_PAUSE;
1383                         start_timer(priv, priv->param.txpause, 0);
1384                 } else {
1385                         priv->state = TX_TAIL;
1386                         start_timer(priv, priv->param.txtail, 0);
1387                 }
1388         }
1389
1390         /* DCD transition */
1391         if (drr0 & DCD) {
1392                 if (rr0 & DCD) {
1393                         switch (priv->state) {
1394                         case IDLE:
1395                         case WAIT:
1396                                 priv->state = DCD_ON;
1397                                 write_scc(priv, R15, 0);
1398                                 start_timer(priv, priv->param.dcdon, 0);
1399                         }
1400                 } else {
1401                         switch (priv->state) {
1402                         case RX_ON:
1403                                 rx_off(priv);
1404                                 priv->state = DCD_OFF;
1405                                 write_scc(priv, R15, 0);
1406                                 start_timer(priv, priv->param.dcdoff, 0);
1407                         }
1408                 }
1409         }
1410
1411         /* CTS transition */
1412         if ((drr0 & CTS) && (~rr0 & CTS) && priv->type != TYPE_TWIN)
1413                 tm_isr(priv);
1414
1415 }
1416
1417
1418 static void tm_isr(struct scc_priv *priv)
1419 {
1420         switch (priv->state) {
1421         case TX_HEAD:
1422         case TX_PAUSE:
1423                 tx_on(priv);
1424                 priv->state = TX_DATA;
1425                 break;
1426         case TX_TAIL:
1427                 write_scc(priv, R5, TxCRC_ENAB | Tx8);
1428                 priv->state = RTS_OFF;
1429                 if (priv->type != TYPE_TWIN)
1430                         write_scc(priv, R15, 0);
1431                 start_timer(priv, priv->param.rtsoff, 0);
1432                 break;
1433         case RTS_OFF:
1434                 write_scc(priv, R15, DCDIE);
1435                 priv->rr0 = read_scc(priv, R0);
1436                 if (priv->rr0 & DCD) {
1437                         priv->stats.collisions++;
1438                         rx_on(priv);
1439                         priv->state = RX_ON;
1440                 } else {
1441                         priv->state = WAIT;
1442                         start_timer(priv, priv->param.waittime, DCDIE);
1443                 }
1444                 break;
1445         case WAIT:
1446                 if (priv->tx_count) {
1447                         priv->state = TX_HEAD;
1448                         priv->tx_start = jiffies;
1449                         write_scc(priv, R5,
1450                                   TxCRC_ENAB | RTS | TxENAB | Tx8);
1451                         write_scc(priv, R15, 0);
1452                         start_timer(priv, priv->param.txdelay, 0);
1453                 } else {
1454                         priv->state = IDLE;
1455                         if (priv->type != TYPE_TWIN)
1456                                 write_scc(priv, R15, DCDIE);
1457                 }
1458                 break;
1459         case DCD_ON:
1460         case DCD_OFF:
1461                 write_scc(priv, R15, DCDIE);
1462                 priv->rr0 = read_scc(priv, R0);
1463                 if (priv->rr0 & DCD) {
1464                         rx_on(priv);
1465                         priv->state = RX_ON;
1466                 } else {
1467                         priv->state = WAIT;
1468                         start_timer(priv,
1469                                     random() / priv->param.persist *
1470                                     priv->param.slottime, DCDIE);
1471                 }
1472                 break;
1473         }
1474 }