drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  * This program is free software; you can redistribute  it and/or modify it
  17  * under  the terms of  the GNU General  Public License as published by the
  18  * Free Software Foundation;  either version 2 of the  License, or (at your
  19  * option) any later version.
  20  *
  21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  22  *  RA 11 31 24.2
  23  *  Dec +69 19 52
  24  *  V 3.84
  25  *  B-V +1.62
  26  *
  27  *  Theory of operation
  28  *
  29  *  The driver is initialized through of_device. Configuration information
  30  *  is therefore conveyed through an OF-style device tree.
  31  *
  32  *  The Gianfar Ethernet Controller uses a ring of buffer
  33  *  descriptors.  The beginning is indicated by a register
  34  *  pointing to the physical address of the start of the ring.
  35  *  The end is determined by a "wrap" bit being set in the
  36  *  last descriptor of the ring.
  37  *
  38  *  When a packet is received, the RXF bit in the
  39  *  IEVENT register is set, triggering an interrupt when the
  40  *  corresponding bit in the IMASK register is also set (if
  41  *  interrupt coalescing is active, then the interrupt may not
  42  *  happen immediately, but will wait until either a set number
  43  *  of frames or amount of time have passed).  In NAPI, the
  44  *  interrupt handler will signal there is work to be done, and
  45  *  exit. This method will start at the last known empty
  46  *  descriptor, and process every subsequent descriptor until there
  47  *  are none left with data (NAPI will stop after a set number of
  48  *  packets to give time to other tasks, but will eventually
  49  *  process all the packets).  The data arrives inside a
  50  *  pre-allocated skb, and so after the skb is passed up to the
  51  *  stack, a new skb must be allocated, and the address field in
  52  *  the buffer descriptor must be updated to indicate this new
  53  *  skb.
  54  *
  55  *  When the kernel requests that a packet be transmitted, the
  56  *  driver starts where it left off last time, and points the
  57  *  descriptor at the buffer which was passed in.  The driver
  58  *  then informs the DMA engine that there are packets ready to
  59  *  be transmitted.  Once the controller is finished transmitting
  60  *  the packet, an interrupt may be triggered (under the same
  61  *  conditions as for reception, but depending on the TXF bit).
  62  *  The driver then cleans up the buffer.
  63  */
  64
  65 #include <linux/kernel.h>
  66 #include <linux/string.h>
  67 #include <linux/errno.h>
  68 #include <linux/unistd.h>
  69 #include <linux/slab.h>
  70 #include <linux/interrupt.h>
  71 #include <linux/init.h>
  72 #include <linux/delay.h>
  73 #include <linux/netdevice.h>
  74 #include <linux/etherdevice.h>
  75 #include <linux/skbuff.h>
  76 #include <linux/if_vlan.h>
  77 #include <linux/spinlock.h>
  78 #include <linux/mm.h>
  79 #include <linux/of_mdio.h>
  80 #include <linux/of_platform.h>
  81 #include <linux/ip.h>
  82 #include <linux/tcp.h>
  83 #include <linux/udp.h>
  84 #include <linux/in.h>
  85 #include <linux/net_tstamp.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/reg.h>
  89 #include <asm/irq.h>
  90 #include <asm/uaccess.h>
  91 #include <linux/module.h>
  92 #include <linux/dma-mapping.h>
  93 #include <linux/crc32.h>
  94 #include <linux/mii.h>
  95 #include <linux/phy.h>
  96 #include <linux/phy_fixed.h>
  97 #include <linux/of.h>
  98 #include <linux/of_net.h>
  99
 100 #include "gianfar.h"
 101 #include "fsl_pq_mdio.h"
 102
 103 #define TX_TIMEOUT      (1*HZ)
 104 #undef BRIEF_GFAR_ERRORS
 105 #undef VERBOSE_GFAR_ERRORS
 106
 107 const char gfar_driver_name[] = "Gianfar Ethernet";
 108 const char gfar_driver_version[] = "1.3";
 109
 110 static int gfar_enet_open(struct net_device *dev);
 111 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 112 static void gfar_reset_task(struct work_struct *work);
 113 static void gfar_timeout(struct net_device *dev);
 114 static int gfar_close(struct net_device *dev);
 115 struct sk_buff *gfar_new_skb(struct net_device *dev);
 116 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 117                 struct sk_buff *skb);
 118 static int gfar_set_mac_address(struct net_device *dev);
 119 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 120 static irqreturn_t gfar_error(int irq, void *dev_id);
 121 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 122 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 123 static void adjust_link(struct net_device *dev);
 124 static void init_registers(struct net_device *dev);
 125 static int init_phy(struct net_device *dev);
 126 static int gfar_probe(struct platform_device *ofdev);
 127 static int gfar_remove(struct platform_device *ofdev);
 128 static void free_skb_resources(struct gfar_private *priv);
 129 static void gfar_set_multi(struct net_device *dev);
 130 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 131 static void gfar_configure_serdes(struct net_device *dev);
 132 static int gfar_poll(struct napi_struct *napi, int budget);
 133 #ifdef CONFIG_NET_POLL_CONTROLLER
 134 static void gfar_netpoll(struct net_device *dev);
 135 #endif
 136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 137 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 139                               int amount_pull);
 140 static void gfar_vlan_rx_register(struct net_device *netdev,
 141                                 struct vlan_group *grp);
 142 void gfar_halt(struct net_device *dev);
 143 static void gfar_halt_nodisable(struct net_device *dev);
 144 void gfar_start(struct net_device *dev);
 145 static void gfar_clear_exact_match(struct net_device *dev);
 146 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 147                                   const u8 *addr);
 148 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 149
 150 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 151 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 152 MODULE_LICENSE("GPL");
 153
 154 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 155                             dma_addr_t buf)
 156 {
 157         u32 lstatus;
 158
 159         bdp->bufPtr = buf;
 160
 161         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 162         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 163                 lstatus |= BD_LFLAG(RXBD_WRAP);
 164
 165         eieio();
 166
 167         bdp->lstatus = lstatus;
 168 }
 169
 170 static int gfar_init_bds(struct net_device *ndev)
 171 {
 172         struct gfar_private *priv = netdev_priv(ndev);
 173         struct gfar_priv_tx_q *tx_queue = NULL;
 174         struct gfar_priv_rx_q *rx_queue = NULL;
 175         struct txbd8 *txbdp;
 176         struct rxbd8 *rxbdp;
 177         int i, j;
 178
 179         for (i = 0; i < priv->num_tx_queues; i++) {
 180                 tx_queue = priv->tx_queue[i];
 181                 /* Initialize some variables in our dev structure */
 182                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 183                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 184                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 185                 tx_queue->skb_curtx = 0;
 186                 tx_queue->skb_dirtytx = 0;
 187
 188                 /* Initialize Transmit Descriptor Ring */
 189                 txbdp = tx_queue->tx_bd_base;
 190                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 191                         txbdp->lstatus = 0;
 192                         txbdp->bufPtr = 0;
 193                         txbdp++;
 194                 }
 195
 196                 /* Set the last descriptor in the ring to indicate wrap */
 197                 txbdp--;
 198                 txbdp->status |= TXBD_WRAP;
 199         }
 200
 201         for (i = 0; i < priv->num_rx_queues; i++) {
 202                 rx_queue = priv->rx_queue[i];
 203                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 204                 rx_queue->skb_currx = 0;
 205                 rxbdp = rx_queue->rx_bd_base;
 206
 207                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 208                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 209
 210                         if (skb) {
 211                                 gfar_init_rxbdp(rx_queue, rxbdp,
 212                                                 rxbdp->bufPtr);
 213                         } else {
 214                                 skb = gfar_new_skb(ndev);
 215                                 if (!skb) {
 216                                         pr_err("%s: Can't allocate RX buffers\n",
 217                                                         ndev->name);
 218                                         goto err_rxalloc_fail;
 219                                 }
 220                                 rx_queue->rx_skbuff[j] = skb;
 221
 222                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 223                         }
 224
 225                         rxbdp++;
 226                 }
 227
 228         }
 229
 230         return 0;
 231
 232 err_rxalloc_fail:
 233         free_skb_resources(priv);
 234         return -ENOMEM;
 235 }
 236
 237 static int gfar_alloc_skb_resources(struct net_device *ndev)
 238 {
 239         void *vaddr;
 240         dma_addr_t addr;
 241         int i, j, k;
 242         struct gfar_private *priv = netdev_priv(ndev);
 243         struct device *dev = &priv->ofdev->dev;
 244         struct gfar_priv_tx_q *tx_queue = NULL;
 245         struct gfar_priv_rx_q *rx_queue = NULL;
 246
 247         priv->total_tx_ring_size = 0;
 248         for (i = 0; i < priv->num_tx_queues; i++)
 249                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 250
 251         priv->total_rx_ring_size = 0;
 252         for (i = 0; i < priv->num_rx_queues; i++)
 253                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 254
 255         /* Allocate memory for the buffer descriptors */
 256         vaddr = dma_alloc_coherent(dev,
 257                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 258                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 259                         &addr, GFP_KERNEL);
 260         if (!vaddr) {
 261                 if (netif_msg_ifup(priv))
 262                         pr_err("%s: Could not allocate buffer descriptors!\n",
 263                                ndev->name);
 264                 return -ENOMEM;
 265         }
 266
 267         for (i = 0; i < priv->num_tx_queues; i++) {
 268                 tx_queue = priv->tx_queue[i];
 269                 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
 270                 tx_queue->tx_bd_dma_base = addr;
 271                 tx_queue->dev = ndev;
 272                 /* enet DMA only understands physical addresses */
 273                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 274                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 275         }
 276
 277         /* Start the rx descriptor ring where the tx ring leaves off */
 278         for (i = 0; i < priv->num_rx_queues; i++) {
 279                 rx_queue = priv->rx_queue[i];
 280                 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
 281                 rx_queue->rx_bd_dma_base = addr;
 282                 rx_queue->dev = ndev;
 283                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 284                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 285         }
 286
 287         /* Setup the skbuff rings */
 288         for (i = 0; i < priv->num_tx_queues; i++) {
 289                 tx_queue = priv->tx_queue[i];
 290                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 291                                   tx_queue->tx_ring_size, GFP_KERNEL);
 292                 if (!tx_queue->tx_skbuff) {
 293                         if (netif_msg_ifup(priv))
 294                                 pr_err("%s: Could not allocate tx_skbuff\n",
 295                                                 ndev->name);
 296                         goto cleanup;
 297                 }
 298
 299                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 300                         tx_queue->tx_skbuff[k] = NULL;
 301         }
 302
 303         for (i = 0; i < priv->num_rx_queues; i++) {
 304                 rx_queue = priv->rx_queue[i];
 305                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 306                                   rx_queue->rx_ring_size, GFP_KERNEL);
 307
 308                 if (!rx_queue->rx_skbuff) {
 309                         if (netif_msg_ifup(priv))
 310                                 pr_err("%s: Could not allocate rx_skbuff\n",
 311                                        ndev->name);
 312                         goto cleanup;
 313                 }
 314
 315                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 316                         rx_queue->rx_skbuff[j] = NULL;
 317         }
 318
 319         if (gfar_init_bds(ndev))
 320                 goto cleanup;
 321
 322         return 0;
 323
 324 cleanup:
 325         free_skb_resources(priv);
 326         return -ENOMEM;
 327 }
 328
 329 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 330 {
 331         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 332         u32 __iomem *baddr;
 333         int i;
 334
 335         baddr = &regs->tbase0;
 336         for(i = 0; i < priv->num_tx_queues; i++) {
 337                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 338                 baddr   += 2;
 339         }
 340
 341         baddr = &regs->rbase0;
 342         for(i = 0; i < priv->num_rx_queues; i++) {
 343                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 344                 baddr   += 2;
 345         }
 346 }
 347
 348 static void gfar_init_mac(struct net_device *ndev)
 349 {
 350         struct gfar_private *priv = netdev_priv(ndev);
 351         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 352         u32 rctrl = 0;
 353         u32 tctrl = 0;
 354         u32 attrs = 0;
 355
 356         /* write the tx/rx base registers */
 357         gfar_init_tx_rx_base(priv);
 358
 359         /* Configure the coalescing support */
 360         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 361
 362         if (priv->rx_filer_enable) {
 363                 rctrl |= RCTRL_FILREN;
 364                 /* Program the RIR0 reg with the required distribution */
 365                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 366         }
 367
 368         if (ndev->features & NETIF_F_RXCSUM)
 369                 rctrl |= RCTRL_CHECKSUMMING;
 370
 371         if (priv->extended_hash) {
 372                 rctrl |= RCTRL_EXTHASH;
 373
 374                 gfar_clear_exact_match(ndev);
 375                 rctrl |= RCTRL_EMEN;
 376         }
 377
 378         if (priv->padding) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(priv->padding);
 381         }
 382
 383         /* Insert receive time stamps into padding alignment bytes */
 384         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 385                 rctrl &= ~RCTRL_PAL_MASK;
 386                 rctrl |= RCTRL_PADDING(8);
 387                 priv->padding = 8;
 388         }
 389
 390         /* Enable HW time stamping if requested from user space */
 391         if (priv->hwts_rx_en)
 392                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 393
 394         /* keep vlan related bits if it's enabled */
 395         if (priv->vlgrp) {
 396                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 397                 tctrl |= TCTRL_VLINS;
 398         }
 399
 400         /* Init rctrl based on our settings */
 401         gfar_write(&regs->rctrl, rctrl);
 402
 403         if (ndev->features & NETIF_F_IP_CSUM)
 404                 tctrl |= TCTRL_INIT_CSUM;
 405
 406         tctrl |= TCTRL_TXSCHED_PRIO;
 407
 408         gfar_write(&regs->tctrl, tctrl);
 409
 410         /* Set the extraction length and index */
 411         attrs = ATTRELI_EL(priv->rx_stash_size) |
 412                 ATTRELI_EI(priv->rx_stash_index);
 413
 414         gfar_write(&regs->attreli, attrs);
 415
 416         /* Start with defaults, and add stashing or locking
 417          * depending on the approprate variables */
 418         attrs = ATTR_INIT_SETTINGS;
 419
 420         if (priv->bd_stash_en)
 421                 attrs |= ATTR_BDSTASH;
 422
 423         if (priv->rx_stash_size != 0)
 424                 attrs |= ATTR_BUFSTASH;
 425
 426         gfar_write(&regs->attr, attrs);
 427
 428         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 429         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 430         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 431 }
 432
 433 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 434 {
 435         struct gfar_private *priv = netdev_priv(dev);
 436         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 437         unsigned long tx_packets = 0, tx_bytes = 0;
 438         int i = 0;
 439
 440         for (i = 0; i < priv->num_rx_queues; i++) {
 441                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 442                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
 443                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 444         }
 445
 446         dev->stats.rx_packets = rx_packets;
 447         dev->stats.rx_bytes = rx_bytes;
 448         dev->stats.rx_dropped = rx_dropped;
 449
 450         for (i = 0; i < priv->num_tx_queues; i++) {
 451                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 452                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 453         }
 454
 455         dev->stats.tx_bytes = tx_bytes;
 456         dev->stats.tx_packets = tx_packets;
 457
 458         return &dev->stats;
 459 }
 460
 461 static const struct net_device_ops gfar_netdev_ops = {
 462         .ndo_open = gfar_enet_open,
 463         .ndo_start_xmit = gfar_start_xmit,
 464         .ndo_stop = gfar_close,
 465         .ndo_change_mtu = gfar_change_mtu,
 466         .ndo_set_features = gfar_set_features,
 467         .ndo_set_multicast_list = gfar_set_multi,
 468         .ndo_tx_timeout = gfar_timeout,
 469         .ndo_do_ioctl = gfar_ioctl,
 470         .ndo_get_stats = gfar_get_stats,
 471         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 472         .ndo_set_mac_address = eth_mac_addr,
 473         .ndo_validate_addr = eth_validate_addr,
 474 #ifdef CONFIG_NET_POLL_CONTROLLER
 475         .ndo_poll_controller = gfar_netpoll,
 476 #endif
 477 };
 478
 479 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
 480 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
 481
 482 void lock_rx_qs(struct gfar_private *priv)
 483 {
 484         int i = 0x0;
 485
 486         for (i = 0; i < priv->num_rx_queues; i++)
 487                 spin_lock(&priv->rx_queue[i]->rxlock);
 488 }
 489
 490 void lock_tx_qs(struct gfar_private *priv)
 491 {
 492         int i = 0x0;
 493
 494         for (i = 0; i < priv->num_tx_queues; i++)
 495                 spin_lock(&priv->tx_queue[i]->txlock);
 496 }
 497
 498 void unlock_rx_qs(struct gfar_private *priv)
 499 {
 500         int i = 0x0;
 501
 502         for (i = 0; i < priv->num_rx_queues; i++)
 503                 spin_unlock(&priv->rx_queue[i]->rxlock);
 504 }
 505
 506 void unlock_tx_qs(struct gfar_private *priv)
 507 {
 508         int i = 0x0;
 509
 510         for (i = 0; i < priv->num_tx_queues; i++)
 511                 spin_unlock(&priv->tx_queue[i]->txlock);
 512 }
 513
 514 /* Returns 1 if incoming frames use an FCB */
 515 static inline int gfar_uses_fcb(struct gfar_private *priv)
 516 {
 517         return priv->vlgrp || (priv->ndev->features & NETIF_F_RXCSUM) ||
 518                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 519 }
 520
 521 static void free_tx_pointers(struct gfar_private *priv)
 522 {
 523         int i = 0;
 524
 525         for (i = 0; i < priv->num_tx_queues; i++)
 526                 kfree(priv->tx_queue[i]);
 527 }
 528
 529 static void free_rx_pointers(struct gfar_private *priv)
 530 {
 531         int i = 0;
 532
 533         for (i = 0; i < priv->num_rx_queues; i++)
 534                 kfree(priv->rx_queue[i]);
 535 }
 536
 537 static void unmap_group_regs(struct gfar_private *priv)
 538 {
 539         int i = 0;
 540
 541         for (i = 0; i < MAXGROUPS; i++)
 542                 if (priv->gfargrp[i].regs)
 543                         iounmap(priv->gfargrp[i].regs);
 544 }
 545
 546 static void disable_napi(struct gfar_private *priv)
 547 {
 548         int i = 0;
 549
 550         for (i = 0; i < priv->num_grps; i++)
 551                 napi_disable(&priv->gfargrp[i].napi);
 552 }
 553
 554 static void enable_napi(struct gfar_private *priv)
 555 {
 556         int i = 0;
 557
 558         for (i = 0; i < priv->num_grps; i++)
 559                 napi_enable(&priv->gfargrp[i].napi);
 560 }
 561
 562 static int gfar_parse_group(struct device_node *np,
 563                 struct gfar_private *priv, const char *model)
 564 {
 565         u32 *queue_mask;
 566
 567         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 568         if (!priv->gfargrp[priv->num_grps].regs)
 569                 return -ENOMEM;
 570
 571         priv->gfargrp[priv->num_grps].interruptTransmit =
 572                         irq_of_parse_and_map(np, 0);
 573
 574         /* If we aren't the FEC we have multiple interrupts */
 575         if (model && strcasecmp(model, "FEC")) {
 576                 priv->gfargrp[priv->num_grps].interruptReceive =
 577                         irq_of_parse_and_map(np, 1);
 578                 priv->gfargrp[priv->num_grps].interruptError =
 579                         irq_of_parse_and_map(np,2);
 580                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
 581                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
 582                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
 583                         return -EINVAL;
 584         }
 585
 586         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 587         priv->gfargrp[priv->num_grps].priv = priv;
 588         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 589         if(priv->mode == MQ_MG_MODE) {
 590                 queue_mask = (u32 *)of_get_property(np,
 591                                         "fsl,rx-bit-map", NULL);
 592                 priv->gfargrp[priv->num_grps].rx_bit_map =
 593                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 594                 queue_mask = (u32 *)of_get_property(np,
 595                                         "fsl,tx-bit-map", NULL);
 596                 priv->gfargrp[priv->num_grps].tx_bit_map =
 597                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 598         } else {
 599                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 600                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 601         }
 602         priv->num_grps++;
 603
 604         return 0;
 605 }
 606
 607 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 608 {
 609         const char *model;
 610         const char *ctype;
 611         const void *mac_addr;
 612         int err = 0, i;
 613         struct net_device *dev = NULL;
 614         struct gfar_private *priv = NULL;
 615         struct device_node *np = ofdev->dev.of_node;
 616         struct device_node *child = NULL;
 617         const u32 *stash;
 618         const u32 *stash_len;
 619         const u32 *stash_idx;
 620         unsigned int num_tx_qs, num_rx_qs;
 621         u32 *tx_queues, *rx_queues;
 622
 623         if (!np || !of_device_is_available(np))
 624                 return -ENODEV;
 625
 626         /* parse the num of tx and rx queues */
 627         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 628         num_tx_qs = tx_queues ? *tx_queues : 1;
 629
 630         if (num_tx_qs > MAX_TX_QS) {
 631                 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 632                                 num_tx_qs, MAX_TX_QS);
 633                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 634                 return -EINVAL;
 635         }
 636
 637         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 638         num_rx_qs = rx_queues ? *rx_queues : 1;
 639
 640         if (num_rx_qs > MAX_RX_QS) {
 641                 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 642                                 num_tx_qs, MAX_TX_QS);
 643                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 644                 return -EINVAL;
 645         }
 646
 647         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 648         dev = *pdev;
 649         if (NULL == dev)
 650                 return -ENOMEM;
 651
 652         priv = netdev_priv(dev);
 653         priv->node = ofdev->dev.of_node;
 654         priv->ndev = dev;
 655
 656         priv->num_tx_queues = num_tx_qs;
 657         netif_set_real_num_rx_queues(dev, num_rx_qs);
 658         priv->num_rx_queues = num_rx_qs;
 659         priv->num_grps = 0x0;
 660
 661         model = of_get_property(np, "model", NULL);
 662
 663         for (i = 0; i < MAXGROUPS; i++)
 664                 priv->gfargrp[i].regs = NULL;
 665
 666         /* Parse and initialize group specific information */
 667         if (of_device_is_compatible(np, "fsl,etsec2")) {
 668                 priv->mode = MQ_MG_MODE;
 669                 for_each_child_of_node(np, child) {
 670                         err = gfar_parse_group(child, priv, model);
 671                         if (err)
 672                                 goto err_grp_init;
 673                 }
 674         } else {
 675                 priv->mode = SQ_SG_MODE;
 676                 err = gfar_parse_group(np, priv, model);
 677                 if(err)
 678                         goto err_grp_init;
 679         }
 680
 681         for (i = 0; i < priv->num_tx_queues; i++)
 682                priv->tx_queue[i] = NULL;
 683         for (i = 0; i < priv->num_rx_queues; i++)
 684                 priv->rx_queue[i] = NULL;
 685
 686         for (i = 0; i < priv->num_tx_queues; i++) {
 687                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 688                                             GFP_KERNEL);
 689                 if (!priv->tx_queue[i]) {
 690                         err = -ENOMEM;
 691                         goto tx_alloc_failed;
 692                 }
 693                 priv->tx_queue[i]->tx_skbuff = NULL;
 694                 priv->tx_queue[i]->qindex = i;
 695                 priv->tx_queue[i]->dev = dev;
 696                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 697         }
 698
 699         for (i = 0; i < priv->num_rx_queues; i++) {
 700                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 701                                             GFP_KERNEL);
 702                 if (!priv->rx_queue[i]) {
 703                         err = -ENOMEM;
 704                         goto rx_alloc_failed;
 705                 }
 706                 priv->rx_queue[i]->rx_skbuff = NULL;
 707                 priv->rx_queue[i]->qindex = i;
 708                 priv->rx_queue[i]->dev = dev;
 709                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 710         }
 711
 712
 713         stash = of_get_property(np, "bd-stash", NULL);
 714
 715         if (stash) {
 716                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 717                 priv->bd_stash_en = 1;
 718         }
 719
 720         stash_len = of_get_property(np, "rx-stash-len", NULL);
 721
 722         if (stash_len)
 723                 priv->rx_stash_size = *stash_len;
 724
 725         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 726
 727         if (stash_idx)
 728                 priv->rx_stash_index = *stash_idx;
 729
 730         if (stash_len || stash_idx)
 731                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 732
 733         mac_addr = of_get_mac_address(np);
 734         if (mac_addr)
 735                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 736
 737         if (model && !strcasecmp(model, "TSEC"))
 738                 priv->device_flags =
 739                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 740                         FSL_GIANFAR_DEV_HAS_COALESCE |
 741                         FSL_GIANFAR_DEV_HAS_RMON |
 742                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 743         if (model && !strcasecmp(model, "eTSEC"))
 744                 priv->device_flags =
 745                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 746                         FSL_GIANFAR_DEV_HAS_COALESCE |
 747                         FSL_GIANFAR_DEV_HAS_RMON |
 748                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 749                         FSL_GIANFAR_DEV_HAS_PADDING |
 750                         FSL_GIANFAR_DEV_HAS_CSUM |
 751                         FSL_GIANFAR_DEV_HAS_VLAN |
 752                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 753                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 754                         FSL_GIANFAR_DEV_HAS_TIMER;
 755
 756         ctype = of_get_property(np, "phy-connection-type", NULL);
 757
 758         /* We only care about rgmii-id.  The rest are autodetected */
 759         if (ctype && !strcmp(ctype, "rgmii-id"))
 760                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 761         else
 762                 priv->interface = PHY_INTERFACE_MODE_MII;
 763
 764         if (of_get_property(np, "fsl,magic-packet", NULL))
 765                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 766
 767         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 768
 769         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 770         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 771
 772         return 0;
 773
 774 rx_alloc_failed:
 775         free_rx_pointers(priv);
 776 tx_alloc_failed:
 777         free_tx_pointers(priv);
 778 err_grp_init:
 779         unmap_group_regs(priv);
 780         free_netdev(dev);
 781         return err;
 782 }
 783
 784 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 785                         struct ifreq *ifr, int cmd)
 786 {
 787         struct hwtstamp_config config;
 788         struct gfar_private *priv = netdev_priv(netdev);
 789
 790         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 791                 return -EFAULT;
 792
 793         /* reserved for future extensions */
 794         if (config.flags)
 795                 return -EINVAL;
 796
 797         switch (config.tx_type) {
 798         case HWTSTAMP_TX_OFF:
 799                 priv->hwts_tx_en = 0;
 800                 break;
 801         case HWTSTAMP_TX_ON:
 802                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 803                         return -ERANGE;
 804                 priv->hwts_tx_en = 1;
 805                 break;
 806         default:
 807                 return -ERANGE;
 808         }
 809
 810         switch (config.rx_filter) {
 811         case HWTSTAMP_FILTER_NONE:
 812                 if (priv->hwts_rx_en) {
 813                         stop_gfar(netdev);
 814                         priv->hwts_rx_en = 0;
 815                         startup_gfar(netdev);
 816                 }
 817                 break;
 818         default:
 819                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 820                         return -ERANGE;
 821                 if (!priv->hwts_rx_en) {
 822                         stop_gfar(netdev);
 823                         priv->hwts_rx_en = 1;
 824                         startup_gfar(netdev);
 825                 }
 826                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 827                 break;
 828         }
 829
 830         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 831                 -EFAULT : 0;
 832 }
 833
 834 /* Ioctl MII Interface */
 835 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 836 {
 837         struct gfar_private *priv = netdev_priv(dev);
 838
 839         if (!netif_running(dev))
 840                 return -EINVAL;
 841
 842         if (cmd == SIOCSHWTSTAMP)
 843                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 844
 845         if (!priv->phydev)
 846                 return -ENODEV;
 847
 848         return phy_mii_ioctl(priv->phydev, rq, cmd);
 849 }
 850
 851 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 852 {
 853         unsigned int new_bit_map = 0x0;
 854         int mask = 0x1 << (max_qs - 1), i;
 855         for (i = 0; i < max_qs; i++) {
 856                 if (bit_map & mask)
 857                         new_bit_map = new_bit_map + (1 << i);
 858                 mask = mask >> 0x1;
 859         }
 860         return new_bit_map;
 861 }
 862
 863 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 864                                    u32 class)
 865 {
 866         u32 rqfpr = FPR_FILER_MASK;
 867         u32 rqfcr = 0x0;
 868
 869         rqfar--;
 870         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 871         ftp_rqfpr[rqfar] = rqfpr;
 872         ftp_rqfcr[rqfar] = rqfcr;
 873         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 874
 875         rqfar--;
 876         rqfcr = RQFCR_CMP_NOMATCH;
 877         ftp_rqfpr[rqfar] = rqfpr;
 878         ftp_rqfcr[rqfar] = rqfcr;
 879         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 880
 881         rqfar--;
 882         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 883         rqfpr = class;
 884         ftp_rqfcr[rqfar] = rqfcr;
 885         ftp_rqfpr[rqfar] = rqfpr;
 886         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 887
 888         rqfar--;
 889         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 890         rqfpr = class;
 891         ftp_rqfcr[rqfar] = rqfcr;
 892         ftp_rqfpr[rqfar] = rqfpr;
 893         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 894
 895         return rqfar;
 896 }
 897
 898 static void gfar_init_filer_table(struct gfar_private *priv)
 899 {
 900         int i = 0x0;
 901         u32 rqfar = MAX_FILER_IDX;
 902         u32 rqfcr = 0x0;
 903         u32 rqfpr = FPR_FILER_MASK;
 904
 905         /* Default rule */
 906         rqfcr = RQFCR_CMP_MATCH;
 907         ftp_rqfcr[rqfar] = rqfcr;
 908         ftp_rqfpr[rqfar] = rqfpr;
 909         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 910
 911         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 912         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 913         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 914         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 915         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 916         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 917
 918         /* cur_filer_idx indicated the first non-masked rule */
 919         priv->cur_filer_idx = rqfar;
 920
 921         /* Rest are masked rules */
 922         rqfcr = RQFCR_CMP_NOMATCH;
 923         for (i = 0; i < rqfar; i++) {
 924                 ftp_rqfcr[i] = rqfcr;
 925                 ftp_rqfpr[i] = rqfpr;
 926                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 927         }
 928 }
 929
 930 static void gfar_detect_errata(struct gfar_private *priv)
 931 {
 932         struct device *dev = &priv->ofdev->dev;
 933         unsigned int pvr = mfspr(SPRN_PVR);
 934         unsigned int svr = mfspr(SPRN_SVR);
 935         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 936         unsigned int rev = svr & 0xffff;
 937
 938         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 939         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 940                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 941                 priv->errata |= GFAR_ERRATA_74;
 942
 943         /* MPC8313 and MPC837x all rev */
 944         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 945                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 946                 priv->errata |= GFAR_ERRATA_76;
 947
 948         /* MPC8313 and MPC837x all rev */
 949         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 950                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 951                 priv->errata |= GFAR_ERRATA_A002;
 952
 953         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 954         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 955                         (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 956                 priv->errata |= GFAR_ERRATA_12;
 957
 958         if (priv->errata)
 959                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 960                          priv->errata);
 961 }
 962
 963 /* Set up the ethernet device structure, private data,
 964  * and anything else we need before we start */
 965 static int gfar_probe(struct platform_device *ofdev)
 966 {
 967         u32 tempval;
 968         struct net_device *dev = NULL;
 969         struct gfar_private *priv = NULL;
 970         struct gfar __iomem *regs = NULL;
 971         int err = 0, i, grp_idx = 0;
 972         int len_devname;
 973         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 974         u32 isrg = 0;
 975         u32 __iomem *baddr;
 976
 977         err = gfar_of_init(ofdev, &dev);
 978
 979         if (err)
 980                 return err;
 981
 982         priv = netdev_priv(dev);
 983         priv->ndev = dev;
 984         priv->ofdev = ofdev;
 985         priv->node = ofdev->dev.of_node;
 986         SET_NETDEV_DEV(dev, &ofdev->dev);
 987
 988         spin_lock_init(&priv->bflock);
 989         INIT_WORK(&priv->reset_task, gfar_reset_task);
 990
 991         dev_set_drvdata(&ofdev->dev, priv);
 992         regs = priv->gfargrp[0].regs;
 993
 994         gfar_detect_errata(priv);
 995
 996         /* Stop the DMA engine now, in case it was running before */
 997         /* (The firmware could have used it, and left it running). */
 998         gfar_halt(dev);
 999
1000         /* Reset MAC layer */
1001         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1002
1003         /* We need to delay at least 3 TX clocks */
1004         udelay(2);
1005
1006         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1007         gfar_write(&regs->maccfg1, tempval);
1008
1009         /* Initialize MACCFG2. */
1010         tempval = MACCFG2_INIT_SETTINGS;
1011         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1012                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1013         gfar_write(&regs->maccfg2, tempval);
1014
1015         /* Initialize ECNTRL */
1016         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1017
1018         /* Set the dev->base_addr to the gfar reg region */
1019         dev->base_addr = (unsigned long) regs;
1020
1021         SET_NETDEV_DEV(dev, &ofdev->dev);
1022
1023         /* Fill in the dev structure */
1024         dev->watchdog_timeo = TX_TIMEOUT;
1025         dev->mtu = 1500;
1026         dev->netdev_ops = &gfar_netdev_ops;
1027         dev->ethtool_ops = &gfar_ethtool_ops;
1028
1029         /* Register for napi ...We are registering NAPI for each grp */
1030         for (i = 0; i < priv->num_grps; i++)
1031                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1032
1033         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1034                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1035                         NETIF_F_RXCSUM;
1036                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1037                         NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1038         }
1039
1040         priv->vlgrp = NULL;
1041
1042         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
1043                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1044
1045         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1046                 priv->extended_hash = 1;
1047                 priv->hash_width = 9;
1048
1049                 priv->hash_regs[0] = &regs->igaddr0;
1050                 priv->hash_regs[1] = &regs->igaddr1;
1051                 priv->hash_regs[2] = &regs->igaddr2;
1052                 priv->hash_regs[3] = &regs->igaddr3;
1053                 priv->hash_regs[4] = &regs->igaddr4;
1054                 priv->hash_regs[5] = &regs->igaddr5;
1055                 priv->hash_regs[6] = &regs->igaddr6;
1056                 priv->hash_regs[7] = &regs->igaddr7;
1057                 priv->hash_regs[8] = &regs->gaddr0;
1058                 priv->hash_regs[9] = &regs->gaddr1;
1059                 priv->hash_regs[10] = &regs->gaddr2;
1060                 priv->hash_regs[11] = &regs->gaddr3;
1061                 priv->hash_regs[12] = &regs->gaddr4;
1062                 priv->hash_regs[13] = &regs->gaddr5;
1063                 priv->hash_regs[14] = &regs->gaddr6;
1064                 priv->hash_regs[15] = &regs->gaddr7;
1065
1066         } else {
1067                 priv->extended_hash = 0;
1068                 priv->hash_width = 8;
1069
1070                 priv->hash_regs[0] = &regs->gaddr0;
1071                 priv->hash_regs[1] = &regs->gaddr1;
1072                 priv->hash_regs[2] = &regs->gaddr2;
1073                 priv->hash_regs[3] = &regs->gaddr3;
1074                 priv->hash_regs[4] = &regs->gaddr4;
1075                 priv->hash_regs[5] = &regs->gaddr5;
1076                 priv->hash_regs[6] = &regs->gaddr6;
1077                 priv->hash_regs[7] = &regs->gaddr7;
1078         }
1079
1080         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1081                 priv->padding = DEFAULT_PADDING;
1082         else
1083                 priv->padding = 0;
1084
1085         if (dev->features & NETIF_F_IP_CSUM ||
1086                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1087                 dev->hard_header_len += GMAC_FCB_LEN;
1088
1089         /* Program the isrg regs only if number of grps > 1 */
1090         if (priv->num_grps > 1) {
1091                 baddr = &regs->isrg0;
1092                 for (i = 0; i < priv->num_grps; i++) {
1093                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1094                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1095                         gfar_write(baddr, isrg);
1096                         baddr++;
1097                         isrg = 0x0;
1098                 }
1099         }
1100
1101         /* Need to reverse the bit maps as  bit_map's MSB is q0
1102          * but, for_each_set_bit parses from right to left, which
1103          * basically reverses the queue numbers */
1104         for (i = 0; i< priv->num_grps; i++) {
1105                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1106                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1107                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1108                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1109         }
1110
1111         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1112          * also assign queues to groups */
1113         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1114                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1115                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1116                                 priv->num_rx_queues) {
1117                         priv->gfargrp[grp_idx].num_rx_queues++;
1118                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1119                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1120                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1121                 }
1122                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1123                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1124                                 priv->num_tx_queues) {
1125                         priv->gfargrp[grp_idx].num_tx_queues++;
1126                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1127                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1128                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1129                 }
1130                 priv->gfargrp[grp_idx].rstat = rstat;
1131                 priv->gfargrp[grp_idx].tstat = tstat;
1132                 rstat = tstat =0;
1133         }
1134
1135         gfar_write(&regs->rqueue, rqueue);
1136         gfar_write(&regs->tqueue, tqueue);
1137
1138         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1139
1140         /* Initializing some of the rx/tx queue level parameters */
1141         for (i = 0; i < priv->num_tx_queues; i++) {
1142                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1143                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1144                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1145                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1146         }
1147
1148         for (i = 0; i < priv->num_rx_queues; i++) {
1149                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1150                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1151                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1152         }
1153
1154         /* enable filer if using multiple RX queues*/
1155         if(priv->num_rx_queues > 1)
1156                 priv->rx_filer_enable = 1;
1157         /* Enable most messages by default */
1158         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1159
1160         /* Carrier starts down, phylib will bring it up */
1161         netif_carrier_off(dev);
1162
1163         err = register_netdev(dev);
1164
1165         if (err) {
1166                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1167                                 dev->name);
1168                 goto register_fail;
1169         }
1170
1171         device_init_wakeup(&dev->dev,
1172                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1173
1174         /* fill out IRQ number and name fields */
1175         len_devname = strlen(dev->name);
1176         for (i = 0; i < priv->num_grps; i++) {
1177                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1178                                 len_devname);
1179                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1180                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1181                                 "_g", sizeof("_g"));
1182                         priv->gfargrp[i].int_name_tx[
1183                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1184                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1185                                 priv->gfargrp[i].int_name_tx)],
1186                                 "_tx", sizeof("_tx") + 1);
1187
1188                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1189                                         len_devname);
1190                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1191                                         "_g", sizeof("_g"));
1192                         priv->gfargrp[i].int_name_rx[
1193                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1194                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1195                                 priv->gfargrp[i].int_name_rx)],
1196                                 "_rx", sizeof("_rx") + 1);
1197
1198                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1199                                         len_devname);
1200                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1201                                 "_g", sizeof("_g"));
1202                         priv->gfargrp[i].int_name_er[strlen(
1203                                         priv->gfargrp[i].int_name_er)] = i+48;
1204                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1205                                 priv->gfargrp[i].int_name_er)],
1206                                 "_er", sizeof("_er") + 1);
1207                 } else
1208                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1209         }
1210
1211         /* Initialize the filer table */
1212         gfar_init_filer_table(priv);
1213
1214         /* Create all the sysfs files */
1215         gfar_init_sysfs(dev);
1216
1217         /* Print out the device info */
1218         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1219
1220         /* Even more device info helps when determining which kernel */
1221         /* provided which set of benchmarks. */
1222         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1223         for (i = 0; i < priv->num_rx_queues; i++)
1224                 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
1225                         dev->name, i, priv->rx_queue[i]->rx_ring_size);
1226         for(i = 0; i < priv->num_tx_queues; i++)
1227                  printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
1228                         dev->name, i, priv->tx_queue[i]->tx_ring_size);
1229
1230         return 0;
1231
1232 register_fail:
1233         unmap_group_regs(priv);
1234         free_tx_pointers(priv);
1235         free_rx_pointers(priv);
1236         if (priv->phy_node)
1237                 of_node_put(priv->phy_node);
1238         if (priv->tbi_node)
1239                 of_node_put(priv->tbi_node);
1240         free_netdev(dev);
1241         return err;
1242 }
1243
1244 static int gfar_remove(struct platform_device *ofdev)
1245 {
1246         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1247
1248         if (priv->phy_node)
1249                 of_node_put(priv->phy_node);
1250         if (priv->tbi_node)
1251                 of_node_put(priv->tbi_node);
1252
1253         dev_set_drvdata(&ofdev->dev, NULL);
1254
1255         unregister_netdev(priv->ndev);
1256         unmap_group_regs(priv);
1257         free_netdev(priv->ndev);
1258
1259         return 0;
1260 }
1261
1262 #ifdef CONFIG_PM
1263
1264 static int gfar_suspend(struct device *dev)
1265 {
1266         struct gfar_private *priv = dev_get_drvdata(dev);
1267         struct net_device *ndev = priv->ndev;
1268         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1269         unsigned long flags;
1270         u32 tempval;
1271
1272         int magic_packet = priv->wol_en &&
1273                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1274
1275         netif_device_detach(ndev);
1276
1277         if (netif_running(ndev)) {
1278
1279                 local_irq_save(flags);
1280                 lock_tx_qs(priv);
1281                 lock_rx_qs(priv);
1282
1283                 gfar_halt_nodisable(ndev);
1284
1285                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1286                 tempval = gfar_read(&regs->maccfg1);
1287
1288                 tempval &= ~MACCFG1_TX_EN;
1289
1290                 if (!magic_packet)
1291                         tempval &= ~MACCFG1_RX_EN;
1292
1293                 gfar_write(&regs->maccfg1, tempval);
1294
1295                 unlock_rx_qs(priv);
1296                 unlock_tx_qs(priv);
1297                 local_irq_restore(flags);
1298
1299                 disable_napi(priv);
1300
1301                 if (magic_packet) {
1302                         /* Enable interrupt on Magic Packet */
1303                         gfar_write(&regs->imask, IMASK_MAG);
1304
1305                         /* Enable Magic Packet mode */
1306                         tempval = gfar_read(&regs->maccfg2);
1307                         tempval |= MACCFG2_MPEN;
1308                         gfar_write(&regs->maccfg2, tempval);
1309                 } else {
1310                         phy_stop(priv->phydev);
1311                 }
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int gfar_resume(struct device *dev)
1318 {
1319         struct gfar_private *priv = dev_get_drvdata(dev);
1320         struct net_device *ndev = priv->ndev;
1321         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1322         unsigned long flags;
1323         u32 tempval;
1324         int magic_packet = priv->wol_en &&
1325                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1326
1327         if (!netif_running(ndev)) {
1328                 netif_device_attach(ndev);
1329                 return 0;
1330         }
1331
1332         if (!magic_packet && priv->phydev)
1333                 phy_start(priv->phydev);
1334
1335         /* Disable Magic Packet mode, in case something
1336          * else woke us up.
1337          */
1338         local_irq_save(flags);
1339         lock_tx_qs(priv);
1340         lock_rx_qs(priv);
1341
1342         tempval = gfar_read(&regs->maccfg2);
1343         tempval &= ~MACCFG2_MPEN;
1344         gfar_write(&regs->maccfg2, tempval);
1345
1346         gfar_start(ndev);
1347
1348         unlock_rx_qs(priv);
1349         unlock_tx_qs(priv);
1350         local_irq_restore(flags);
1351
1352         netif_device_attach(ndev);
1353
1354         enable_napi(priv);
1355
1356         return 0;
1357 }
1358
1359 static int gfar_restore(struct device *dev)
1360 {
1361         struct gfar_private *priv = dev_get_drvdata(dev);
1362         struct net_device *ndev = priv->ndev;
1363
1364         if (!netif_running(ndev))
1365                 return 0;
1366
1367         gfar_init_bds(ndev);
1368         init_registers(ndev);
1369         gfar_set_mac_address(ndev);
1370         gfar_init_mac(ndev);
1371         gfar_start(ndev);
1372
1373         priv->oldlink = 0;
1374         priv->oldspeed = 0;
1375         priv->oldduplex = -1;
1376
1377         if (priv->phydev)
1378                 phy_start(priv->phydev);
1379
1380         netif_device_attach(ndev);
1381         enable_napi(priv);
1382
1383         return 0;
1384 }
1385
1386 static struct dev_pm_ops gfar_pm_ops = {
1387         .suspend = gfar_suspend,
1388         .resume = gfar_resume,
1389         .freeze = gfar_suspend,
1390         .thaw = gfar_resume,
1391         .restore = gfar_restore,
1392 };
1393
1394 #define GFAR_PM_OPS (&gfar_pm_ops)
1395
1396 #else
1397
1398 #define GFAR_PM_OPS NULL
1399
1400 #endif
1401
1402 /* Reads the controller's registers to determine what interface
1403  * connects it to the PHY.
1404  */
1405 static phy_interface_t gfar_get_interface(struct net_device *dev)
1406 {
1407         struct gfar_private *priv = netdev_priv(dev);
1408         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1409         u32 ecntrl;
1410
1411         ecntrl = gfar_read(&regs->ecntrl);
1412
1413         if (ecntrl & ECNTRL_SGMII_MODE)
1414                 return PHY_INTERFACE_MODE_SGMII;
1415
1416         if (ecntrl & ECNTRL_TBI_MODE) {
1417                 if (ecntrl & ECNTRL_REDUCED_MODE)
1418                         return PHY_INTERFACE_MODE_RTBI;
1419                 else
1420                         return PHY_INTERFACE_MODE_TBI;
1421         }
1422
1423         if (ecntrl & ECNTRL_REDUCED_MODE) {
1424                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1425                         return PHY_INTERFACE_MODE_RMII;
1426                 else {
1427                         phy_interface_t interface = priv->interface;
1428
1429                         /*
1430                          * This isn't autodetected right now, so it must
1431                          * be set by the device tree or platform code.
1432                          */
1433                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1434                                 return PHY_INTERFACE_MODE_RGMII_ID;
1435
1436                         return PHY_INTERFACE_MODE_RGMII;
1437                 }
1438         }
1439
1440         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1441                 return PHY_INTERFACE_MODE_GMII;
1442
1443         return PHY_INTERFACE_MODE_MII;
1444 }
1445
1446
1447 /* Initializes driver's PHY state, and attaches to the PHY.
1448  * Returns 0 on success.
1449  */
1450 static int init_phy(struct net_device *dev)
1451 {
1452         struct gfar_private *priv = netdev_priv(dev);
1453         uint gigabit_support =
1454                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1455                 SUPPORTED_1000baseT_Full : 0;
1456         phy_interface_t interface;
1457
1458         priv->oldlink = 0;
1459         priv->oldspeed = 0;
1460         priv->oldduplex = -1;
1461
1462         interface = gfar_get_interface(dev);
1463
1464         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1465                                       interface);
1466         if (!priv->phydev)
1467                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1468                                                          interface);
1469         if (!priv->phydev) {
1470                 dev_err(&dev->dev, "could not attach to PHY\n");
1471                 return -ENODEV;
1472         }
1473
1474         if (interface == PHY_INTERFACE_MODE_SGMII)
1475                 gfar_configure_serdes(dev);
1476
1477         /* Remove any features not supported by the controller */
1478         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1479         priv->phydev->advertising = priv->phydev->supported;
1480
1481         return 0;
1482 }
1483
1484 /*
1485  * Initialize TBI PHY interface for communicating with the
1486  * SERDES lynx PHY on the chip.  We communicate with this PHY
1487  * through the MDIO bus on each controller, treating it as a
1488  * "normal" PHY at the address found in the TBIPA register.  We assume
1489  * that the TBIPA register is valid.  Either the MDIO bus code will set
1490  * it to a value that doesn't conflict with other PHYs on the bus, or the
1491  * value doesn't matter, as there are no other PHYs on the bus.
1492  */
1493 static void gfar_configure_serdes(struct net_device *dev)
1494 {
1495         struct gfar_private *priv = netdev_priv(dev);
1496         struct phy_device *tbiphy;
1497
1498         if (!priv->tbi_node) {
1499                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1500                                     "device tree specify a tbi-handle\n");
1501                 return;
1502         }
1503
1504         tbiphy = of_phy_find_device(priv->tbi_node);
1505         if (!tbiphy) {
1506                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1507                 return;
1508         }
1509
1510         /*
1511          * If the link is already up, we must already be ok, and don't need to
1512          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1513          * everything for us?  Resetting it takes the link down and requires
1514          * several seconds for it to come back.
1515          */
1516         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1517                 return;
1518
1519         /* Single clk mode, mii mode off(for serdes communication) */
1520         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1521
1522         phy_write(tbiphy, MII_ADVERTISE,
1523                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1524                         ADVERTISE_1000XPSE_ASYM);
1525
1526         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1527                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1528 }
1529
1530 static void init_registers(struct net_device *dev)
1531 {
1532         struct gfar_private *priv = netdev_priv(dev);
1533         struct gfar __iomem *regs = NULL;
1534         int i = 0;
1535
1536         for (i = 0; i < priv->num_grps; i++) {
1537                 regs = priv->gfargrp[i].regs;
1538                 /* Clear IEVENT */
1539                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1540
1541                 /* Initialize IMASK */
1542                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1543         }
1544
1545         regs = priv->gfargrp[0].regs;
1546         /* Init hash registers to zero */
1547         gfar_write(&regs->igaddr0, 0);
1548         gfar_write(&regs->igaddr1, 0);
1549         gfar_write(&regs->igaddr2, 0);
1550         gfar_write(&regs->igaddr3, 0);
1551         gfar_write(&regs->igaddr4, 0);
1552         gfar_write(&regs->igaddr5, 0);
1553         gfar_write(&regs->igaddr6, 0);
1554         gfar_write(&regs->igaddr7, 0);
1555
1556         gfar_write(&regs->gaddr0, 0);
1557         gfar_write(&regs->gaddr1, 0);
1558         gfar_write(&regs->gaddr2, 0);
1559         gfar_write(&regs->gaddr3, 0);
1560         gfar_write(&regs->gaddr4, 0);
1561         gfar_write(&regs->gaddr5, 0);
1562         gfar_write(&regs->gaddr6, 0);
1563         gfar_write(&regs->gaddr7, 0);
1564
1565         /* Zero out the rmon mib registers if it has them */
1566         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1567                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1568
1569                 /* Mask off the CAM interrupts */
1570                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1571                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1572         }
1573
1574         /* Initialize the max receive buffer length */
1575         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1576
1577         /* Initialize the Minimum Frame Length Register */
1578         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1579 }
1580
1581 static int __gfar_is_rx_idle(struct gfar_private *priv)
1582 {
1583         u32 res;
1584
1585         /*
1586          * Normaly TSEC should not hang on GRS commands, so we should
1587          * actually wait for IEVENT_GRSC flag.
1588          */
1589         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1590                 return 0;
1591
1592         /*
1593          * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1594          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1595          * and the Rx can be safely reset.
1596          */
1597         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1598         res &= 0x7f807f80;
1599         if ((res & 0xffff) == (res >> 16))
1600                 return 1;
1601
1602         return 0;
1603 }
1604
1605 /* Halt the receive and transmit queues */
1606 static void gfar_halt_nodisable(struct net_device *dev)
1607 {
1608         struct gfar_private *priv = netdev_priv(dev);
1609         struct gfar __iomem *regs = NULL;
1610         u32 tempval;
1611         int i = 0;
1612
1613         for (i = 0; i < priv->num_grps; i++) {
1614                 regs = priv->gfargrp[i].regs;
1615                 /* Mask all interrupts */
1616                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1617
1618                 /* Clear all interrupts */
1619                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1620         }
1621
1622         regs = priv->gfargrp[0].regs;
1623         /* Stop the DMA, and wait for it to stop */
1624         tempval = gfar_read(&regs->dmactrl);
1625         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1626             != (DMACTRL_GRS | DMACTRL_GTS)) {
1627                 int ret;
1628
1629                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1630                 gfar_write(&regs->dmactrl, tempval);
1631
1632                 do {
1633                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1634                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1635                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1636                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1637                                 ret = __gfar_is_rx_idle(priv);
1638                 } while (!ret);
1639         }
1640 }
1641
1642 /* Halt the receive and transmit queues */
1643 void gfar_halt(struct net_device *dev)
1644 {
1645         struct gfar_private *priv = netdev_priv(dev);
1646         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1647         u32 tempval;
1648
1649         gfar_halt_nodisable(dev);
1650
1651         /* Disable Rx and Tx */
1652         tempval = gfar_read(&regs->maccfg1);
1653         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1654         gfar_write(&regs->maccfg1, tempval);
1655 }
1656
1657 static void free_grp_irqs(struct gfar_priv_grp *grp)
1658 {
1659         free_irq(grp->interruptError, grp);
1660         free_irq(grp->interruptTransmit, grp);
1661         free_irq(grp->interruptReceive, grp);
1662 }
1663
1664 void stop_gfar(struct net_device *dev)
1665 {
1666         struct gfar_private *priv = netdev_priv(dev);
1667         unsigned long flags;
1668         int i;
1669
1670         phy_stop(priv->phydev);
1671
1672
1673         /* Lock it down */
1674         local_irq_save(flags);
1675         lock_tx_qs(priv);
1676         lock_rx_qs(priv);
1677
1678         gfar_halt(dev);
1679
1680         unlock_rx_qs(priv);
1681         unlock_tx_qs(priv);
1682         local_irq_restore(flags);
1683
1684         /* Free the IRQs */
1685         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1686                 for (i = 0; i < priv->num_grps; i++)
1687                         free_grp_irqs(&priv->gfargrp[i]);
1688         } else {
1689                 for (i = 0; i < priv->num_grps; i++)
1690                         free_irq(priv->gfargrp[i].interruptTransmit,
1691                                         &priv->gfargrp[i]);
1692         }
1693
1694         free_skb_resources(priv);
1695 }
1696
1697 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1698 {
1699         struct txbd8 *txbdp;
1700         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1701         int i, j;
1702
1703         txbdp = tx_queue->tx_bd_base;
1704
1705         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1706                 if (!tx_queue->tx_skbuff[i])
1707                         continue;
1708
1709                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1710                                 txbdp->length, DMA_TO_DEVICE);
1711                 txbdp->lstatus = 0;
1712                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1713                                 j++) {
1714                         txbdp++;
1715                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1716                                         txbdp->length, DMA_TO_DEVICE);
1717                 }
1718                 txbdp++;
1719                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1720                 tx_queue->tx_skbuff[i] = NULL;
1721         }
1722         kfree(tx_queue->tx_skbuff);
1723 }
1724
1725 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1726 {
1727         struct rxbd8 *rxbdp;
1728         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1729         int i;
1730
1731         rxbdp = rx_queue->rx_bd_base;
1732
1733         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1734                 if (rx_queue->rx_skbuff[i]) {
1735                         dma_unmap_single(&priv->ofdev->dev,
1736                                         rxbdp->bufPtr, priv->rx_buffer_size,
1737                                         DMA_FROM_DEVICE);
1738                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1739                         rx_queue->rx_skbuff[i] = NULL;
1740                 }
1741                 rxbdp->lstatus = 0;
1742                 rxbdp->bufPtr = 0;
1743                 rxbdp++;
1744         }
1745         kfree(rx_queue->rx_skbuff);
1746 }
1747
1748 /* If there are any tx skbs or rx skbs still around, free them.
1749  * Then free tx_skbuff and rx_skbuff */
1750 static void free_skb_resources(struct gfar_private *priv)
1751 {
1752         struct gfar_priv_tx_q *tx_queue = NULL;
1753         struct gfar_priv_rx_q *rx_queue = NULL;
1754         int i;
1755
1756         /* Go through all the buffer descriptors and free their data buffers */
1757         for (i = 0; i < priv->num_tx_queues; i++) {
1758                 tx_queue = priv->tx_queue[i];
1759                 if(tx_queue->tx_skbuff)
1760                         free_skb_tx_queue(tx_queue);
1761         }
1762
1763         for (i = 0; i < priv->num_rx_queues; i++) {
1764                 rx_queue = priv->rx_queue[i];
1765                 if(rx_queue->rx_skbuff)
1766                         free_skb_rx_queue(rx_queue);
1767         }
1768
1769         dma_free_coherent(&priv->ofdev->dev,
1770                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1771                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1772                         priv->tx_queue[0]->tx_bd_base,
1773                         priv->tx_queue[0]->tx_bd_dma_base);
1774         skb_queue_purge(&priv->rx_recycle);
1775 }
1776
1777 void gfar_start(struct net_device *dev)
1778 {
1779         struct gfar_private *priv = netdev_priv(dev);
1780         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1781         u32 tempval;
1782         int i = 0;
1783
1784         /* Enable Rx and Tx in MACCFG1 */
1785         tempval = gfar_read(&regs->maccfg1);
1786         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1787         gfar_write(&regs->maccfg1, tempval);
1788
1789         /* Initialize DMACTRL to have WWR and WOP */
1790         tempval = gfar_read(&regs->dmactrl);
1791         tempval |= DMACTRL_INIT_SETTINGS;
1792         gfar_write(&regs->dmactrl, tempval);
1793
1794         /* Make sure we aren't stopped */
1795         tempval = gfar_read(&regs->dmactrl);
1796         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1797         gfar_write(&regs->dmactrl, tempval);
1798
1799         for (i = 0; i < priv->num_grps; i++) {
1800                 regs = priv->gfargrp[i].regs;
1801                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1802                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1803                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1804                 /* Unmask the interrupts we look for */
1805                 gfar_write(&regs->imask, IMASK_DEFAULT);
1806         }
1807
1808         dev->trans_start = jiffies; /* prevent tx timeout */
1809 }
1810
1811 void gfar_configure_coalescing(struct gfar_private *priv,
1812         unsigned long tx_mask, unsigned long rx_mask)
1813 {
1814         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1815         u32 __iomem *baddr;
1816         int i = 0;
1817
1818         /* Backward compatible case ---- even if we enable
1819          * multiple queues, there's only single reg to program
1820          */
1821         gfar_write(&regs->txic, 0);
1822         if(likely(priv->tx_queue[0]->txcoalescing))
1823                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1824
1825         gfar_write(&regs->rxic, 0);
1826         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1827                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1828
1829         if (priv->mode == MQ_MG_MODE) {
1830                 baddr = &regs->txic0;
1831                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1832                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1833                                 gfar_write(baddr + i, 0);
1834                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1835                         }
1836                 }
1837
1838                 baddr = &regs->rxic0;
1839                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1840                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1841                                 gfar_write(baddr + i, 0);
1842                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1843                         }
1844                 }
1845         }
1846 }
1847
1848 static int register_grp_irqs(struct gfar_priv_grp *grp)
1849 {
1850         struct gfar_private *priv = grp->priv;
1851         struct net_device *dev = priv->ndev;
1852         int err;
1853
1854         /* If the device has multiple interrupts, register for
1855          * them.  Otherwise, only register for the one */
1856         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1857                 /* Install our interrupt handlers for Error,
1858                  * Transmit, and Receive */
1859                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1860                                 grp->int_name_er,grp)) < 0) {
1861                         if (netif_msg_intr(priv))
1862                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1863                                         dev->name, grp->interruptError);
1864
1865                         goto err_irq_fail;
1866                 }
1867
1868                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1869                                 0, grp->int_name_tx, grp)) < 0) {
1870                         if (netif_msg_intr(priv))
1871                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1872                                         dev->name, grp->interruptTransmit);
1873                         goto tx_irq_fail;
1874                 }
1875
1876                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1877                                 grp->int_name_rx, grp)) < 0) {
1878                         if (netif_msg_intr(priv))
1879                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1880                                         dev->name, grp->interruptReceive);
1881                         goto rx_irq_fail;
1882                 }
1883         } else {
1884                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1885                                 grp->int_name_tx, grp)) < 0) {
1886                         if (netif_msg_intr(priv))
1887                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1888                                         dev->name, grp->interruptTransmit);
1889                         goto err_irq_fail;
1890                 }
1891         }
1892
1893         return 0;
1894
1895 rx_irq_fail:
1896         free_irq(grp->interruptTransmit, grp);
1897 tx_irq_fail:
1898         free_irq(grp->interruptError, grp);
1899 err_irq_fail:
1900         return err;
1901
1902 }
1903
1904 /* Bring the controller up and running */
1905 int startup_gfar(struct net_device *ndev)
1906 {
1907         struct gfar_private *priv = netdev_priv(ndev);
1908         struct gfar __iomem *regs = NULL;
1909         int err, i, j;
1910
1911         for (i = 0; i < priv->num_grps; i++) {
1912                 regs= priv->gfargrp[i].regs;
1913                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1914         }
1915
1916         regs= priv->gfargrp[0].regs;
1917         err = gfar_alloc_skb_resources(ndev);
1918         if (err)
1919                 return err;
1920
1921         gfar_init_mac(ndev);
1922
1923         for (i = 0; i < priv->num_grps; i++) {
1924                 err = register_grp_irqs(&priv->gfargrp[i]);
1925                 if (err) {
1926                         for (j = 0; j < i; j++)
1927                                 free_grp_irqs(&priv->gfargrp[j]);
1928                         goto irq_fail;
1929                 }
1930         }
1931
1932         /* Start the controller */
1933         gfar_start(ndev);
1934
1935         phy_start(priv->phydev);
1936
1937         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1938
1939         return 0;
1940
1941 irq_fail:
1942         free_skb_resources(priv);
1943         return err;
1944 }
1945
1946 /* Called when something needs to use the ethernet device */
1947 /* Returns 0 for success. */
1948 static int gfar_enet_open(struct net_device *dev)
1949 {
1950         struct gfar_private *priv = netdev_priv(dev);
1951         int err;
1952
1953         enable_napi(priv);
1954
1955         skb_queue_head_init(&priv->rx_recycle);
1956
1957         /* Initialize a bunch of registers */
1958         init_registers(dev);
1959
1960         gfar_set_mac_address(dev);
1961
1962         err = init_phy(dev);
1963
1964         if (err) {
1965                 disable_napi(priv);
1966                 return err;
1967         }
1968
1969         err = startup_gfar(dev);
1970         if (err) {
1971                 disable_napi(priv);
1972                 return err;
1973         }
1974
1975         netif_tx_start_all_queues(dev);
1976
1977         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1978
1979         return err;
1980 }
1981
1982 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1983 {
1984         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1985
1986         memset(fcb, 0, GMAC_FCB_LEN);
1987
1988         return fcb;
1989 }
1990
1991 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1992 {
1993         u8 flags = 0;
1994
1995         /* If we're here, it's a IP packet with a TCP or UDP
1996          * payload.  We set it to checksum, using a pseudo-header
1997          * we provide
1998          */
1999         flags = TXFCB_DEFAULT;
2000
2001         /* Tell the controller what the protocol is */
2002         /* And provide the already calculated phcs */
2003         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2004                 flags |= TXFCB_UDP;
2005                 fcb->phcs = udp_hdr(skb)->check;
2006         } else
2007                 fcb->phcs = tcp_hdr(skb)->check;
2008
2009         /* l3os is the distance between the start of the
2010          * frame (skb->data) and the start of the IP hdr.
2011          * l4os is the distance between the start of the
2012          * l3 hdr and the l4 hdr */
2013         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2014         fcb->l4os = skb_network_header_len(skb);
2015
2016         fcb->flags = flags;
2017 }
2018
2019 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2020 {
2021         fcb->flags |= TXFCB_VLN;
2022         fcb->vlctl = vlan_tx_tag_get(skb);
2023 }
2024
2025 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2026                                struct txbd8 *base, int ring_size)
2027 {
2028         struct txbd8 *new_bd = bdp + stride;
2029
2030         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2031 }
2032
2033 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2034                 int ring_size)
2035 {
2036         return skip_txbd(bdp, 1, base, ring_size);
2037 }
2038
2039 /* This is called by the kernel when a frame is ready for transmission. */
2040 /* It is pointed to by the dev->hard_start_xmit function pointer */
2041 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2042 {
2043         struct gfar_private *priv = netdev_priv(dev);
2044         struct gfar_priv_tx_q *tx_queue = NULL;
2045         struct netdev_queue *txq;
2046         struct gfar __iomem *regs = NULL;
2047         struct txfcb *fcb = NULL;
2048         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2049         u32 lstatus;
2050         int i, rq = 0, do_tstamp = 0;
2051         u32 bufaddr;
2052         unsigned long flags;
2053         unsigned int nr_frags, nr_txbds, length;
2054
2055         /*
2056          * TOE=1 frames larger than 2500 bytes may see excess delays
2057          * before start of transmission.
2058          */
2059         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2060                         skb->ip_summed == CHECKSUM_PARTIAL &&
2061                         skb->len > 2500)) {
2062                 int ret;
2063
2064                 ret = skb_checksum_help(skb);
2065                 if (ret)
2066                         return ret;
2067         }
2068
2069         rq = skb->queue_mapping;
2070         tx_queue = priv->tx_queue[rq];
2071         txq = netdev_get_tx_queue(dev, rq);
2072         base = tx_queue->tx_bd_base;
2073         regs = tx_queue->grp->regs;
2074
2075         /* check if time stamp should be generated */
2076         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2077                      priv->hwts_tx_en))
2078                 do_tstamp = 1;
2079
2080         /* make space for additional header when fcb is needed */
2081         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2082                         vlan_tx_tag_present(skb) ||
2083                         unlikely(do_tstamp)) &&
2084                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
2085                 struct sk_buff *skb_new;
2086
2087                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2088                 if (!skb_new) {
2089                         dev->stats.tx_errors++;
2090                         kfree_skb(skb);
2091                         return NETDEV_TX_OK;
2092                 }
2093                 kfree_skb(skb);
2094                 skb = skb_new;
2095         }
2096
2097         /* total number of fragments in the SKB */
2098         nr_frags = skb_shinfo(skb)->nr_frags;
2099
2100         /* calculate the required number of TxBDs for this skb */
2101         if (unlikely(do_tstamp))
2102                 nr_txbds = nr_frags + 2;
2103         else
2104                 nr_txbds = nr_frags + 1;
2105
2106         /* check if there is space to queue this packet */
2107         if (nr_txbds > tx_queue->num_txbdfree) {
2108                 /* no space, stop the queue */
2109                 netif_tx_stop_queue(txq);
2110                 dev->stats.tx_fifo_errors++;
2111                 return NETDEV_TX_BUSY;
2112         }
2113
2114         /* Update transmit stats */
2115         tx_queue->stats.tx_bytes += skb->len;
2116         tx_queue->stats.tx_packets++;
2117
2118         txbdp = txbdp_start = tx_queue->cur_tx;
2119         lstatus = txbdp->lstatus;
2120
2121         /* Time stamp insertion requires one additional TxBD */
2122         if (unlikely(do_tstamp))
2123                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2124                                 tx_queue->tx_ring_size);
2125
2126         if (nr_frags == 0) {
2127                 if (unlikely(do_tstamp))
2128                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2129                                         TXBD_INTERRUPT);
2130                 else
2131                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2132         } else {
2133                 /* Place the fragment addresses and lengths into the TxBDs */
2134                 for (i = 0; i < nr_frags; i++) {
2135                         /* Point at the next BD, wrapping as needed */
2136                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2137
2138                         length = skb_shinfo(skb)->frags[i].size;
2139
2140                         lstatus = txbdp->lstatus | length |
2141                                 BD_LFLAG(TXBD_READY);
2142
2143                         /* Handle the last BD specially */
2144                         if (i == nr_frags - 1)
2145                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2146
2147                         bufaddr = dma_map_page(&priv->ofdev->dev,
2148                                         skb_shinfo(skb)->frags[i].page,
2149                                         skb_shinfo(skb)->frags[i].page_offset,
2150                                         length,
2151                                         DMA_TO_DEVICE);
2152
2153                         /* set the TxBD length and buffer pointer */
2154                         txbdp->bufPtr = bufaddr;
2155                         txbdp->lstatus = lstatus;
2156                 }
2157
2158                 lstatus = txbdp_start->lstatus;
2159         }
2160
2161         /* Set up checksumming */
2162         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2163                 fcb = gfar_add_fcb(skb);
2164                 /* as specified by errata */
2165                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2166                              && ((unsigned long)fcb % 0x20) > 0x18)) {
2167                         __skb_pull(skb, GMAC_FCB_LEN);
2168                         skb_checksum_help(skb);
2169                 } else {
2170                         lstatus |= BD_LFLAG(TXBD_TOE);
2171                         gfar_tx_checksum(skb, fcb);
2172                 }
2173         }
2174
2175         if (vlan_tx_tag_present(skb)) {
2176                 if (unlikely(NULL == fcb)) {
2177                         fcb = gfar_add_fcb(skb);
2178                         lstatus |= BD_LFLAG(TXBD_TOE);
2179                 }
2180
2181                 gfar_tx_vlan(skb, fcb);
2182         }
2183
2184         /* Setup tx hardware time stamping if requested */
2185         if (unlikely(do_tstamp)) {
2186                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2187                 if (fcb == NULL)
2188                         fcb = gfar_add_fcb(skb);
2189                 fcb->ptp = 1;
2190                 lstatus |= BD_LFLAG(TXBD_TOE);
2191         }
2192
2193         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2194                         skb_headlen(skb), DMA_TO_DEVICE);
2195
2196         /*
2197          * If time stamping is requested one additional TxBD must be set up. The
2198          * first TxBD points to the FCB and must have a data length of
2199          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2200          * the full frame length.
2201          */
2202         if (unlikely(do_tstamp)) {
2203                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2204                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2205                                 (skb_headlen(skb) - GMAC_FCB_LEN);
2206                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2207         } else {
2208                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2209         }
2210
2211         /*
2212          * We can work in parallel with gfar_clean_tx_ring(), except
2213          * when modifying num_txbdfree. Note that we didn't grab the lock
2214          * when we were reading the num_txbdfree and checking for available
2215          * space, that's because outside of this function it can only grow,
2216          * and once we've got needed space, it cannot suddenly disappear.
2217          *
2218          * The lock also protects us from gfar_error(), which can modify
2219          * regs->tstat and thus retrigger the transfers, which is why we
2220          * also must grab the lock before setting ready bit for the first
2221          * to be transmitted BD.
2222          */
2223         spin_lock_irqsave(&tx_queue->txlock, flags);
2224
2225         /*
2226          * The powerpc-specific eieio() is used, as wmb() has too strong
2227          * semantics (it requires synchronization between cacheable and
2228          * uncacheable mappings, which eieio doesn't provide and which we
2229          * don't need), thus requiring a more expensive sync instruction.  At
2230          * some point, the set of architecture-independent barrier functions
2231          * should be expanded to include weaker barriers.
2232          */
2233         eieio();
2234
2235         txbdp_start->lstatus = lstatus;
2236
2237         eieio(); /* force lstatus write before tx_skbuff */
2238
2239         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2240
2241         /* Update the current skb pointer to the next entry we will use
2242          * (wrapping if necessary) */
2243         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2244                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2245
2246         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2247
2248         /* reduce TxBD free count */
2249         tx_queue->num_txbdfree -= (nr_txbds);
2250
2251         /* If the next BD still needs to be cleaned up, then the bds
2252            are full.  We need to tell the kernel to stop sending us stuff. */
2253         if (!tx_queue->num_txbdfree) {
2254                 netif_tx_stop_queue(txq);
2255
2256                 dev->stats.tx_fifo_errors++;
2257         }
2258
2259         /* Tell the DMA to go go go */
2260         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2261
2262         /* Unlock priv */
2263         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2264
2265         return NETDEV_TX_OK;
2266 }
2267
2268 /* Stops the kernel queue, and halts the controller */
2269 static int gfar_close(struct net_device *dev)
2270 {
2271         struct gfar_private *priv = netdev_priv(dev);
2272
2273         disable_napi(priv);
2274
2275         cancel_work_sync(&priv->reset_task);
2276         stop_gfar(dev);
2277
2278         /* Disconnect from the PHY */
2279         phy_disconnect(priv->phydev);
2280         priv->phydev = NULL;
2281
2282         netif_tx_stop_all_queues(dev);
2283
2284         return 0;
2285 }
2286
2287 /* Changes the mac address if the controller is not running. */
2288 static int gfar_set_mac_address(struct net_device *dev)
2289 {
2290         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2291
2292         return 0;
2293 }
2294
2295
2296 /* Enables and disables VLAN insertion/extraction */
2297 static void gfar_vlan_rx_register(struct net_device *dev,
2298                 struct vlan_group *grp)
2299 {
2300         struct gfar_private *priv = netdev_priv(dev);
2301         struct gfar __iomem *regs = NULL;
2302         unsigned long flags;
2303         u32 tempval;
2304
2305         regs = priv->gfargrp[0].regs;
2306         local_irq_save(flags);
2307         lock_rx_qs(priv);
2308
2309         priv->vlgrp = grp;
2310
2311         if (grp) {
2312                 /* Enable VLAN tag insertion */
2313                 tempval = gfar_read(&regs->tctrl);
2314                 tempval |= TCTRL_VLINS;
2315
2316                 gfar_write(&regs->tctrl, tempval);
2317
2318                 /* Enable VLAN tag extraction */
2319                 tempval = gfar_read(&regs->rctrl);
2320                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2321                 gfar_write(&regs->rctrl, tempval);
2322         } else {
2323                 /* Disable VLAN tag insertion */
2324                 tempval = gfar_read(&regs->tctrl);
2325                 tempval &= ~TCTRL_VLINS;
2326                 gfar_write(&regs->tctrl, tempval);
2327
2328                 /* Disable VLAN tag extraction */
2329                 tempval = gfar_read(&regs->rctrl);
2330                 tempval &= ~RCTRL_VLEX;
2331                 /* If parse is no longer required, then disable parser */
2332                 if (tempval & RCTRL_REQ_PARSER)
2333                         tempval |= RCTRL_PRSDEP_INIT;
2334                 else
2335                         tempval &= ~RCTRL_PRSDEP_INIT;
2336                 gfar_write(&regs->rctrl, tempval);
2337         }
2338
2339         gfar_change_mtu(dev, dev->mtu);
2340
2341         unlock_rx_qs(priv);
2342         local_irq_restore(flags);
2343 }
2344
2345 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2346 {
2347         int tempsize, tempval;
2348         struct gfar_private *priv = netdev_priv(dev);
2349         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2350         int oldsize = priv->rx_buffer_size;
2351         int frame_size = new_mtu + ETH_HLEN;
2352
2353         if (priv->vlgrp)
2354                 frame_size += VLAN_HLEN;
2355
2356         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2357                 if (netif_msg_drv(priv))
2358                         printk(KERN_ERR "%s: Invalid MTU setting\n",
2359                                         dev->name);
2360                 return -EINVAL;
2361         }
2362
2363         if (gfar_uses_fcb(priv))
2364                 frame_size += GMAC_FCB_LEN;
2365
2366         frame_size += priv->padding;
2367
2368         tempsize =
2369             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2370             INCREMENTAL_BUFFER_SIZE;
2371
2372         /* Only stop and start the controller if it isn't already
2373          * stopped, and we changed something */
2374         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2375                 stop_gfar(dev);
2376
2377         priv->rx_buffer_size = tempsize;
2378
2379         dev->mtu = new_mtu;
2380
2381         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2382         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2383
2384         /* If the mtu is larger than the max size for standard
2385          * ethernet frames (ie, a jumbo frame), then set maccfg2
2386          * to allow huge frames, and to check the length */
2387         tempval = gfar_read(&regs->maccfg2);
2388
2389         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2390                         gfar_has_errata(priv, GFAR_ERRATA_74))
2391                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2392         else
2393                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2394
2395         gfar_write(&regs->maccfg2, tempval);
2396
2397         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2398                 startup_gfar(dev);
2399
2400         return 0;
2401 }
2402
2403 /* gfar_reset_task gets scheduled when a packet has not been
2404  * transmitted after a set amount of time.
2405  * For now, assume that clearing out all the structures, and
2406  * starting over will fix the problem.
2407  */
2408 static void gfar_reset_task(struct work_struct *work)
2409 {
2410         struct gfar_private *priv = container_of(work, struct gfar_private,
2411                         reset_task);
2412         struct net_device *dev = priv->ndev;
2413
2414         if (dev->flags & IFF_UP) {
2415                 netif_tx_stop_all_queues(dev);
2416                 stop_gfar(dev);
2417                 startup_gfar(dev);
2418                 netif_tx_start_all_queues(dev);
2419         }
2420
2421         netif_tx_schedule_all(dev);
2422 }
2423
2424 static void gfar_timeout(struct net_device *dev)
2425 {
2426         struct gfar_private *priv = netdev_priv(dev);
2427
2428         dev->stats.tx_errors++;
2429         schedule_work(&priv->reset_task);
2430 }
2431
2432 static void gfar_align_skb(struct sk_buff *skb)
2433 {
2434         /* We need the data buffer to be aligned properly.  We will reserve
2435          * as many bytes as needed to align the data properly
2436          */
2437         skb_reserve(skb, RXBUF_ALIGNMENT -
2438                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2439 }
2440
2441 /* Interrupt Handler for Transmit complete */
2442 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2443 {
2444         struct net_device *dev = tx_queue->dev;
2445         struct gfar_private *priv = netdev_priv(dev);
2446         struct gfar_priv_rx_q *rx_queue = NULL;
2447         struct txbd8 *bdp, *next = NULL;
2448         struct txbd8 *lbdp = NULL;
2449         struct txbd8 *base = tx_queue->tx_bd_base;
2450         struct sk_buff *skb;
2451         int skb_dirtytx;
2452         int tx_ring_size = tx_queue->tx_ring_size;
2453         int frags = 0, nr_txbds = 0;
2454         int i;
2455         int howmany = 0;
2456         u32 lstatus;
2457         size_t buflen;
2458
2459         rx_queue = priv->rx_queue[tx_queue->qindex];
2460         bdp = tx_queue->dirty_tx;
2461         skb_dirtytx = tx_queue->skb_dirtytx;
2462
2463         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2464                 unsigned long flags;
2465
2466                 frags = skb_shinfo(skb)->nr_frags;
2467
2468                 /*
2469                  * When time stamping, one additional TxBD must be freed.
2470                  * Also, we need to dma_unmap_single() the TxPAL.
2471                  */
2472                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2473                         nr_txbds = frags + 2;
2474                 else
2475                         nr_txbds = frags + 1;
2476
2477                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2478
2479                 lstatus = lbdp->lstatus;
2480
2481                 /* Only clean completed frames */
2482                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2483                                 (lstatus & BD_LENGTH_MASK))
2484                         break;
2485
2486                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2487                         next = next_txbd(bdp, base, tx_ring_size);
2488                         buflen = next->length + GMAC_FCB_LEN;
2489                 } else
2490                         buflen = bdp->length;
2491
2492                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2493                                 buflen, DMA_TO_DEVICE);
2494
2495                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2496                         struct skb_shared_hwtstamps shhwtstamps;
2497                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2498                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2499                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2500                         skb_tstamp_tx(skb, &shhwtstamps);
2501                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2502                         bdp = next;
2503                 }
2504
2505                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2506                 bdp = next_txbd(bdp, base, tx_ring_size);
2507
2508                 for (i = 0; i < frags; i++) {
2509                         dma_unmap_page(&priv->ofdev->dev,
2510                                         bdp->bufPtr,
2511                                         bdp->length,
2512                                         DMA_TO_DEVICE);
2513                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2514                         bdp = next_txbd(bdp, base, tx_ring_size);
2515                 }
2516
2517                 /*
2518                  * If there's room in the queue (limit it to rx_buffer_size)
2519                  * we add this skb back into the pool, if it's the right size
2520                  */
2521                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2522                                 skb_recycle_check(skb, priv->rx_buffer_size +
2523                                         RXBUF_ALIGNMENT)) {
2524                         gfar_align_skb(skb);
2525                         skb_queue_head(&priv->rx_recycle, skb);
2526                 } else
2527                         dev_kfree_skb_any(skb);
2528
2529                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2530
2531                 skb_dirtytx = (skb_dirtytx + 1) &
2532                         TX_RING_MOD_MASK(tx_ring_size);
2533
2534                 howmany++;
2535                 spin_lock_irqsave(&tx_queue->txlock, flags);
2536                 tx_queue->num_txbdfree += nr_txbds;
2537                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2538         }
2539
2540         /* If we freed a buffer, we can restart transmission, if necessary */
2541         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2542                 netif_wake_subqueue(dev, tx_queue->qindex);
2543
2544         /* Update dirty indicators */
2545         tx_queue->skb_dirtytx = skb_dirtytx;
2546         tx_queue->dirty_tx = bdp;
2547
2548         return howmany;
2549 }
2550
2551 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2552 {
2553         unsigned long flags;
2554
2555         spin_lock_irqsave(&gfargrp->grplock, flags);
2556         if (napi_schedule_prep(&gfargrp->napi)) {
2557                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2558                 __napi_schedule(&gfargrp->napi);
2559         } else {
2560                 /*
2561                  * Clear IEVENT, so interrupts aren't called again
2562                  * because of the packets that have already arrived.
2563                  */
2564                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2565         }
2566         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2567
2568 }
2569
2570 /* Interrupt Handler for Transmit complete */
2571 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2572 {
2573         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2574         return IRQ_HANDLED;
2575 }
2576
2577 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2578                 struct sk_buff *skb)
2579 {
2580         struct net_device *dev = rx_queue->dev;
2581         struct gfar_private *priv = netdev_priv(dev);
2582         dma_addr_t buf;
2583
2584         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2585                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2586         gfar_init_rxbdp(rx_queue, bdp, buf);
2587 }
2588
2589 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2590 {
2591         struct gfar_private *priv = netdev_priv(dev);
2592         struct sk_buff *skb = NULL;
2593
2594         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2595         if (!skb)
2596                 return NULL;
2597
2598         gfar_align_skb(skb);
2599
2600         return skb;
2601 }
2602
2603 struct sk_buff * gfar_new_skb(struct net_device *dev)
2604 {
2605         struct gfar_private *priv = netdev_priv(dev);
2606         struct sk_buff *skb = NULL;
2607
2608         skb = skb_dequeue(&priv->rx_recycle);
2609         if (!skb)
2610                 skb = gfar_alloc_skb(dev);
2611
2612         return skb;
2613 }
2614
2615 static inline void count_errors(unsigned short status, struct net_device *dev)
2616 {
2617         struct gfar_private *priv = netdev_priv(dev);
2618         struct net_device_stats *stats = &dev->stats;
2619         struct gfar_extra_stats *estats = &priv->extra_stats;
2620
2621         /* If the packet was truncated, none of the other errors
2622          * matter */
2623         if (status & RXBD_TRUNCATED) {
2624                 stats->rx_length_errors++;
2625
2626                 estats->rx_trunc++;
2627
2628                 return;
2629         }
2630         /* Count the errors, if there were any */
2631         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2632                 stats->rx_length_errors++;
2633
2634                 if (status & RXBD_LARGE)
2635                         estats->rx_large++;
2636                 else
2637                         estats->rx_short++;
2638         }
2639         if (status & RXBD_NONOCTET) {
2640                 stats->rx_frame_errors++;
2641                 estats->rx_nonoctet++;
2642         }
2643         if (status & RXBD_CRCERR) {
2644                 estats->rx_crcerr++;
2645                 stats->rx_crc_errors++;
2646         }
2647         if (status & RXBD_OVERRUN) {
2648                 estats->rx_overrun++;
2649                 stats->rx_crc_errors++;
2650         }
2651 }
2652
2653 irqreturn_t gfar_receive(int irq, void *grp_id)
2654 {
2655         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2656         return IRQ_HANDLED;
2657 }
2658
2659 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2660 {
2661         /* If valid headers were found, and valid sums
2662          * were verified, then we tell the kernel that no
2663          * checksumming is necessary.  Otherwise, it is */
2664         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2665                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2666         else
2667                 skb_checksum_none_assert(skb);
2668 }
2669
2670
2671 /* gfar_process_frame() -- handle one incoming packet if skb
2672  * isn't NULL.  */
2673 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2674                               int amount_pull)
2675 {
2676         struct gfar_private *priv = netdev_priv(dev);
2677         struct rxfcb *fcb = NULL;
2678
2679         int ret;
2680
2681         /* fcb is at the beginning if exists */
2682         fcb = (struct rxfcb *)skb->data;
2683
2684         /* Remove the FCB from the skb */
2685         /* Remove the padded bytes, if there are any */
2686         if (amount_pull) {
2687                 skb_record_rx_queue(skb, fcb->rq);
2688                 skb_pull(skb, amount_pull);
2689         }
2690
2691         /* Get receive timestamp from the skb */
2692         if (priv->hwts_rx_en) {
2693                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2694                 u64 *ns = (u64 *) skb->data;
2695                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2696                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2697         }
2698
2699         if (priv->padding)
2700                 skb_pull(skb, priv->padding);
2701
2702         if (dev->features & NETIF_F_RXCSUM)
2703                 gfar_rx_checksum(skb, fcb);
2704
2705         /* Tell the skb what kind of packet this is */
2706         skb->protocol = eth_type_trans(skb, dev);
2707
2708         /* Send the packet up the stack */
2709         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2710                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2711         else
2712                 ret = netif_receive_skb(skb);
2713
2714         if (NET_RX_DROP == ret)
2715                 priv->extra_stats.kernel_dropped++;
2716
2717         return 0;
2718 }
2719
2720 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2721  *   until the budget/quota has been reached. Returns the number
2722  *   of frames handled
2723  */
2724 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2725 {
2726         struct net_device *dev = rx_queue->dev;
2727         struct rxbd8 *bdp, *base;
2728         struct sk_buff *skb;
2729         int pkt_len;
2730         int amount_pull;
2731         int howmany = 0;
2732         struct gfar_private *priv = netdev_priv(dev);
2733
2734         /* Get the first full descriptor */
2735         bdp = rx_queue->cur_rx;
2736         base = rx_queue->rx_bd_base;
2737
2738         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2739
2740         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2741                 struct sk_buff *newskb;
2742                 rmb();
2743
2744                 /* Add another skb for the future */
2745                 newskb = gfar_new_skb(dev);
2746
2747                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2748
2749                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2750                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2751
2752                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2753                                 bdp->length > priv->rx_buffer_size))
2754                         bdp->status = RXBD_LARGE;
2755
2756                 /* We drop the frame if we failed to allocate a new buffer */
2757                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2758                                  bdp->status & RXBD_ERR)) {
2759                         count_errors(bdp->status, dev);
2760
2761                         if (unlikely(!newskb))
2762                                 newskb = skb;
2763                         else if (skb)
2764                                 skb_queue_head(&priv->rx_recycle, skb);
2765                 } else {
2766                         /* Increment the number of packets */
2767                         rx_queue->stats.rx_packets++;
2768                         howmany++;
2769
2770                         if (likely(skb)) {
2771                                 pkt_len = bdp->length - ETH_FCS_LEN;
2772                                 /* Remove the FCS from the packet length */
2773                                 skb_put(skb, pkt_len);
2774                                 rx_queue->stats.rx_bytes += pkt_len;
2775                                 skb_record_rx_queue(skb, rx_queue->qindex);
2776                                 gfar_process_frame(dev, skb, amount_pull);
2777
2778                         } else {
2779                                 if (netif_msg_rx_err(priv))
2780                                         printk(KERN_WARNING
2781                                                "%s: Missing skb!\n", dev->name);
2782                                 rx_queue->stats.rx_dropped++;
2783                                 priv->extra_stats.rx_skbmissing++;
2784                         }
2785
2786                 }
2787
2788                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2789
2790                 /* Setup the new bdp */
2791                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2792
2793                 /* Update to the next pointer */
2794                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2795
2796                 /* update to point at the next skb */
2797                 rx_queue->skb_currx =
2798                     (rx_queue->skb_currx + 1) &
2799                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2800         }
2801
2802         /* Update the current rxbd pointer to be the next one */
2803         rx_queue->cur_rx = bdp;
2804
2805         return howmany;
2806 }
2807
2808 static int gfar_poll(struct napi_struct *napi, int budget)
2809 {
2810         struct gfar_priv_grp *gfargrp = container_of(napi,
2811                         struct gfar_priv_grp, napi);
2812         struct gfar_private *priv = gfargrp->priv;
2813         struct gfar __iomem *regs = gfargrp->regs;
2814         struct gfar_priv_tx_q *tx_queue = NULL;
2815         struct gfar_priv_rx_q *rx_queue = NULL;
2816         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2817         int tx_cleaned = 0, i, left_over_budget = budget;
2818         unsigned long serviced_queues = 0;
2819         int num_queues = 0;
2820
2821         num_queues = gfargrp->num_rx_queues;
2822         budget_per_queue = budget/num_queues;
2823
2824         /* Clear IEVENT, so interrupts aren't called again
2825          * because of the packets that have already arrived */
2826         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2827
2828         while (num_queues && left_over_budget) {
2829
2830                 budget_per_queue = left_over_budget/num_queues;
2831                 left_over_budget = 0;
2832
2833                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2834                         if (test_bit(i, &serviced_queues))
2835                                 continue;
2836                         rx_queue = priv->rx_queue[i];
2837                         tx_queue = priv->tx_queue[rx_queue->qindex];
2838
2839                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2840                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2841                                                         budget_per_queue);
2842                         rx_cleaned += rx_cleaned_per_queue;
2843                         if(rx_cleaned_per_queue < budget_per_queue) {
2844                                 left_over_budget = left_over_budget +
2845                                         (budget_per_queue - rx_cleaned_per_queue);
2846                                 set_bit(i, &serviced_queues);
2847                                 num_queues--;
2848                         }
2849                 }
2850         }
2851
2852         if (tx_cleaned)
2853                 return budget;
2854
2855         if (rx_cleaned < budget) {
2856                 napi_complete(napi);
2857
2858                 /* Clear the halt bit in RSTAT */
2859                 gfar_write(&regs->rstat, gfargrp->rstat);
2860
2861                 gfar_write(&regs->imask, IMASK_DEFAULT);
2862
2863                 /* If we are coalescing interrupts, update the timer */
2864                 /* Otherwise, clear it */
2865                 gfar_configure_coalescing(priv,
2866                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2867         }
2868
2869         return rx_cleaned;
2870 }
2871
2872 #ifdef CONFIG_NET_POLL_CONTROLLER
2873 /*
2874  * Polling 'interrupt' - used by things like netconsole to send skbs
2875  * without having to re-enable interrupts. It's not called while
2876  * the interrupt routine is executing.
2877  */
2878 static void gfar_netpoll(struct net_device *dev)
2879 {
2880         struct gfar_private *priv = netdev_priv(dev);
2881         int i = 0;
2882
2883         /* If the device has multiple interrupts, run tx/rx */
2884         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2885                 for (i = 0; i < priv->num_grps; i++) {
2886                         disable_irq(priv->gfargrp[i].interruptTransmit);
2887                         disable_irq(priv->gfargrp[i].interruptReceive);
2888                         disable_irq(priv->gfargrp[i].interruptError);
2889                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2890                                                 &priv->gfargrp[i]);
2891                         enable_irq(priv->gfargrp[i].interruptError);
2892                         enable_irq(priv->gfargrp[i].interruptReceive);
2893                         enable_irq(priv->gfargrp[i].interruptTransmit);
2894                 }
2895         } else {
2896                 for (i = 0; i < priv->num_grps; i++) {
2897                         disable_irq(priv->gfargrp[i].interruptTransmit);
2898                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2899                                                 &priv->gfargrp[i]);
2900                         enable_irq(priv->gfargrp[i].interruptTransmit);
2901                 }
2902         }
2903 }
2904 #endif
2905
2906 /* The interrupt handler for devices with one interrupt */
2907 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2908 {
2909         struct gfar_priv_grp *gfargrp = grp_id;
2910
2911         /* Save ievent for future reference */
2912         u32 events = gfar_read(&gfargrp->regs->ievent);
2913
2914         /* Check for reception */
2915         if (events & IEVENT_RX_MASK)
2916                 gfar_receive(irq, grp_id);
2917
2918         /* Check for transmit completion */
2919         if (events & IEVENT_TX_MASK)
2920                 gfar_transmit(irq, grp_id);
2921
2922         /* Check for errors */
2923         if (events & IEVENT_ERR_MASK)
2924                 gfar_error(irq, grp_id);
2925
2926         return IRQ_HANDLED;
2927 }
2928
2929 /* Called every time the controller might need to be made
2930  * aware of new link state.  The PHY code conveys this
2931  * information through variables in the phydev structure, and this
2932  * function converts those variables into the appropriate
2933  * register values, and can bring down the device if needed.
2934  */
2935 static void adjust_link(struct net_device *dev)
2936 {
2937         struct gfar_private *priv = netdev_priv(dev);
2938         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2939         unsigned long flags;
2940         struct phy_device *phydev = priv->phydev;
2941         int new_state = 0;
2942
2943         local_irq_save(flags);
2944         lock_tx_qs(priv);
2945
2946         if (phydev->link) {
2947                 u32 tempval = gfar_read(&regs->maccfg2);
2948                 u32 ecntrl = gfar_read(&regs->ecntrl);
2949
2950                 /* Now we make sure that we can be in full duplex mode.
2951                  * If not, we operate in half-duplex mode. */
2952                 if (phydev->duplex != priv->oldduplex) {
2953                         new_state = 1;
2954                         if (!(phydev->duplex))
2955                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2956                         else
2957                                 tempval |= MACCFG2_FULL_DUPLEX;
2958
2959                         priv->oldduplex = phydev->duplex;
2960                 }
2961
2962                 if (phydev->speed != priv->oldspeed) {
2963                         new_state = 1;
2964                         switch (phydev->speed) {
2965                         case 1000:
2966                                 tempval =
2967                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2968
2969                                 ecntrl &= ~(ECNTRL_R100);
2970                                 break;
2971                         case 100:
2972                         case 10:
2973                                 tempval =
2974                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2975
2976                                 /* Reduced mode distinguishes
2977                                  * between 10 and 100 */
2978                                 if (phydev->speed == SPEED_100)
2979                                         ecntrl |= ECNTRL_R100;
2980                                 else
2981                                         ecntrl &= ~(ECNTRL_R100);
2982                                 break;
2983                         default:
2984                                 if (netif_msg_link(priv))
2985                                         printk(KERN_WARNING
2986                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2987                                                 dev->name, phydev->speed);
2988                                 break;
2989                         }
2990
2991                         priv->oldspeed = phydev->speed;
2992                 }
2993
2994                 gfar_write(&regs->maccfg2, tempval);
2995                 gfar_write(&regs->ecntrl, ecntrl);
2996
2997                 if (!priv->oldlink) {
2998                         new_state = 1;
2999                         priv->oldlink = 1;
3000                 }
3001         } else if (priv->oldlink) {
3002                 new_state = 1;
3003                 priv->oldlink = 0;
3004                 priv->oldspeed = 0;
3005                 priv->oldduplex = -1;
3006         }
3007
3008         if (new_state && netif_msg_link(priv))
3009                 phy_print_status(phydev);
3010         unlock_tx_qs(priv);
3011         local_irq_restore(flags);
3012 }
3013
3014 /* Update the hash table based on the current list of multicast
3015  * addresses we subscribe to.  Also, change the promiscuity of
3016  * the device based on the flags (this function is called
3017  * whenever dev->flags is changed */
3018 static void gfar_set_multi(struct net_device *dev)
3019 {
3020         struct netdev_hw_addr *ha;
3021         struct gfar_private *priv = netdev_priv(dev);
3022         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3023         u32 tempval;
3024
3025         if (dev->flags & IFF_PROMISC) {
3026                 /* Set RCTRL to PROM */
3027                 tempval = gfar_read(&regs->rctrl);
3028                 tempval |= RCTRL_PROM;
3029                 gfar_write(&regs->rctrl, tempval);
3030         } else {
3031                 /* Set RCTRL to not PROM */
3032                 tempval = gfar_read(&regs->rctrl);
3033                 tempval &= ~(RCTRL_PROM);
3034                 gfar_write(&regs->rctrl, tempval);
3035         }
3036
3037         if (dev->flags & IFF_ALLMULTI) {
3038                 /* Set the hash to rx all multicast frames */
3039                 gfar_write(&regs->igaddr0, 0xffffffff);
3040                 gfar_write(&regs->igaddr1, 0xffffffff);
3041                 gfar_write(&regs->igaddr2, 0xffffffff);
3042                 gfar_write(&regs->igaddr3, 0xffffffff);
3043                 gfar_write(&regs->igaddr4, 0xffffffff);
3044                 gfar_write(&regs->igaddr5, 0xffffffff);
3045                 gfar_write(&regs->igaddr6, 0xffffffff);
3046                 gfar_write(&regs->igaddr7, 0xffffffff);
3047                 gfar_write(&regs->gaddr0, 0xffffffff);
3048                 gfar_write(&regs->gaddr1, 0xffffffff);
3049                 gfar_write(&regs->gaddr2, 0xffffffff);
3050                 gfar_write(&regs->gaddr3, 0xffffffff);
3051                 gfar_write(&regs->gaddr4, 0xffffffff);
3052                 gfar_write(&regs->gaddr5, 0xffffffff);
3053                 gfar_write(&regs->gaddr6, 0xffffffff);
3054                 gfar_write(&regs->gaddr7, 0xffffffff);
3055         } else {
3056                 int em_num;
3057                 int idx;
3058
3059                 /* zero out the hash */
3060                 gfar_write(&regs->igaddr0, 0x0);
3061                 gfar_write(&regs->igaddr1, 0x0);
3062                 gfar_write(&regs->igaddr2, 0x0);
3063                 gfar_write(&regs->igaddr3, 0x0);
3064                 gfar_write(&regs->igaddr4, 0x0);
3065                 gfar_write(&regs->igaddr5, 0x0);
3066                 gfar_write(&regs->igaddr6, 0x0);
3067                 gfar_write(&regs->igaddr7, 0x0);
3068                 gfar_write(&regs->gaddr0, 0x0);
3069                 gfar_write(&regs->gaddr1, 0x0);
3070                 gfar_write(&regs->gaddr2, 0x0);
3071                 gfar_write(&regs->gaddr3, 0x0);
3072                 gfar_write(&regs->gaddr4, 0x0);
3073                 gfar_write(&regs->gaddr5, 0x0);
3074                 gfar_write(&regs->gaddr6, 0x0);
3075                 gfar_write(&regs->gaddr7, 0x0);
3076
3077                 /* If we have extended hash tables, we need to
3078                  * clear the exact match registers to prepare for
3079                  * setting them */
3080                 if (priv->extended_hash) {
3081                         em_num = GFAR_EM_NUM + 1;
3082                         gfar_clear_exact_match(dev);
3083                         idx = 1;
3084                 } else {
3085                         idx = 0;
3086                         em_num = 0;
3087                 }
3088
3089                 if (netdev_mc_empty(dev))
3090                         return;
3091
3092                 /* Parse the list, and set the appropriate bits */
3093                 netdev_for_each_mc_addr(ha, dev) {
3094                         if (idx < em_num) {
3095                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3096                                 idx++;
3097                         } else
3098                                 gfar_set_hash_for_addr(dev, ha->addr);
3099                 }
3100         }
3101 }
3102
3103
3104 /* Clears each of the exact match registers to zero, so they
3105  * don't interfere with normal reception */
3106 static void gfar_clear_exact_match(struct net_device *dev)
3107 {
3108         int idx;
3109         static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
3110
3111         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3112                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3113 }
3114
3115 /* Set the appropriate hash bit for the given addr */
3116 /* The algorithm works like so:
3117  * 1) Take the Destination Address (ie the multicast address), and
3118  * do a CRC on it (little endian), and reverse the bits of the
3119  * result.
3120  * 2) Use the 8 most significant bits as a hash into a 256-entry
3121  * table.  The table is controlled through 8 32-bit registers:
3122  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3123  * gaddr7.  This means that the 3 most significant bits in the
3124  * hash index which gaddr register to use, and the 5 other bits
3125  * indicate which bit (assuming an IBM numbering scheme, which
3126  * for PowerPC (tm) is usually the case) in the register holds
3127  * the entry. */
3128 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3129 {
3130         u32 tempval;
3131         struct gfar_private *priv = netdev_priv(dev);
3132         u32 result = ether_crc(MAC_ADDR_LEN, addr);
3133         int width = priv->hash_width;
3134         u8 whichbit = (result >> (32 - width)) & 0x1f;
3135         u8 whichreg = result >> (32 - width + 5);
3136         u32 value = (1 << (31-whichbit));
3137
3138         tempval = gfar_read(priv->hash_regs[whichreg]);
3139         tempval |= value;
3140         gfar_write(priv->hash_regs[whichreg], tempval);
3141 }
3142
3143
3144 /* There are multiple MAC Address register pairs on some controllers
3145  * This function sets the numth pair to a given address
3146  */
3147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3148                                   const u8 *addr)
3149 {
3150         struct gfar_private *priv = netdev_priv(dev);
3151         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3152         int idx;
3153         char tmpbuf[MAC_ADDR_LEN];
3154         u32 tempval;
3155         u32 __iomem *macptr = &regs->macstnaddr1;
3156
3157         macptr += num*2;
3158
3159         /* Now copy it into the mac registers backwards, cuz */
3160         /* little endian is silly */
3161         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3162                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3163
3164         gfar_write(macptr, *((u32 *) (tmpbuf)));
3165
3166         tempval = *((u32 *) (tmpbuf + 4));
3167
3168         gfar_write(macptr+1, tempval);
3169 }
3170
3171 /* GFAR error interrupt handler */
3172 static irqreturn_t gfar_error(int irq, void *grp_id)
3173 {
3174         struct gfar_priv_grp *gfargrp = grp_id;
3175         struct gfar __iomem *regs = gfargrp->regs;
3176         struct gfar_private *priv= gfargrp->priv;
3177         struct net_device *dev = priv->ndev;
3178
3179         /* Save ievent for future reference */
3180         u32 events = gfar_read(&regs->ievent);
3181
3182         /* Clear IEVENT */
3183         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3184
3185         /* Magic Packet is not an error. */
3186         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3187             (events & IEVENT_MAG))
3188                 events &= ~IEVENT_MAG;
3189
3190         /* Hmm... */
3191         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3192                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3193                        dev->name, events, gfar_read(&regs->imask));
3194
3195         /* Update the error counters */
3196         if (events & IEVENT_TXE) {
3197                 dev->stats.tx_errors++;
3198
3199                 if (events & IEVENT_LC)
3200                         dev->stats.tx_window_errors++;
3201                 if (events & IEVENT_CRL)
3202                         dev->stats.tx_aborted_errors++;
3203                 if (events & IEVENT_XFUN) {
3204                         unsigned long flags;
3205
3206                         if (netif_msg_tx_err(priv))
3207                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3208                                        "packet dropped.\n", dev->name);
3209                         dev->stats.tx_dropped++;
3210                         priv->extra_stats.tx_underrun++;
3211
3212                         local_irq_save(flags);
3213                         lock_tx_qs(priv);
3214
3215                         /* Reactivate the Tx Queues */
3216                         gfar_write(&regs->tstat, gfargrp->tstat);
3217
3218                         unlock_tx_qs(priv);
3219                         local_irq_restore(flags);
3220                 }
3221                 if (netif_msg_tx_err(priv))
3222                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
3223         }
3224         if (events & IEVENT_BSY) {
3225                 dev->stats.rx_errors++;
3226                 priv->extra_stats.rx_bsy++;
3227
3228                 gfar_receive(irq, grp_id);
3229
3230                 if (netif_msg_rx_err(priv))
3231                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
3232                                dev->name, gfar_read(&regs->rstat));
3233         }
3234         if (events & IEVENT_BABR) {
3235                 dev->stats.rx_errors++;
3236                 priv->extra_stats.rx_babr++;
3237
3238                 if (netif_msg_rx_err(priv))
3239                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
3240         }
3241         if (events & IEVENT_EBERR) {
3242                 priv->extra_stats.eberr++;
3243                 if (netif_msg_rx_err(priv))
3244                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
3245         }
3246         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
3247                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
3248
3249         if (events & IEVENT_BABT) {
3250                 priv->extra_stats.tx_babt++;
3251                 if (netif_msg_tx_err(priv))
3252                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
3253         }
3254         return IRQ_HANDLED;
3255 }
3256
3257 static struct of_device_id gfar_match[] =
3258 {
3259         {
3260                 .type = "network",
3261                 .compatible = "gianfar",
3262         },
3263         {
3264                 .compatible = "fsl,etsec2",
3265         },
3266         {},
3267 };
3268 MODULE_DEVICE_TABLE(of, gfar_match);
3269
3270 /* Structure for a device driver */
3271 static struct platform_driver gfar_driver = {
3272         .driver = {
3273                 .name = "fsl-gianfar",
3274                 .owner = THIS_MODULE,
3275                 .pm = GFAR_PM_OPS,
3276                 .of_match_table = gfar_match,
3277         },
3278         .probe = gfar_probe,
3279         .remove = gfar_remove,
3280 };
3281
3282 static int __init gfar_init(void)
3283 {
3284         return platform_driver_register(&gfar_driver);
3285 }
3286
3287 static void __exit gfar_exit(void)
3288 {
3289         platform_driver_unregister(&gfar_driver);
3290 }
3291
3292 module_init(gfar_init);
3293 module_exit(gfar_exit);
3294