drivers/net/gianfar.c

   1 /*
   2  * drivers/net/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  * This program is free software; you can redistribute  it and/or modify it
  17  * under  the terms of  the GNU General  Public License as published by the
  18  * Free Software Foundation;  either version 2 of the  License, or (at your
  19  * option) any later version.
  20  *
  21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  22  *  RA 11 31 24.2
  23  *  Dec +69 19 52
  24  *  V 3.84
  25  *  B-V +1.62
  26  *
  27  *  Theory of operation
  28  *
  29  *  The driver is initialized through of_device. Configuration information
  30  *  is therefore conveyed through an OF-style device tree.
  31  *
  32  *  The Gianfar Ethernet Controller uses a ring of buffer
  33  *  descriptors.  The beginning is indicated by a register
  34  *  pointing to the physical address of the start of the ring.
  35  *  The end is determined by a "wrap" bit being set in the
  36  *  last descriptor of the ring.
  37  *
  38  *  When a packet is received, the RXF bit in the
  39  *  IEVENT register is set, triggering an interrupt when the
  40  *  corresponding bit in the IMASK register is also set (if
  41  *  interrupt coalescing is active, then the interrupt may not
  42  *  happen immediately, but will wait until either a set number
  43  *  of frames or amount of time have passed).  In NAPI, the
  44  *  interrupt handler will signal there is work to be done, and
  45  *  exit. This method will start at the last known empty
  46  *  descriptor, and process every subsequent descriptor until there
  47  *  are none left with data (NAPI will stop after a set number of
  48  *  packets to give time to other tasks, but will eventually
  49  *  process all the packets).  The data arrives inside a
  50  *  pre-allocated skb, and so after the skb is passed up to the
  51  *  stack, a new skb must be allocated, and the address field in
  52  *  the buffer descriptor must be updated to indicate this new
  53  *  skb.
  54  *
  55  *  When the kernel requests that a packet be transmitted, the
  56  *  driver starts where it left off last time, and points the
  57  *  descriptor at the buffer which was passed in.  The driver
  58  *  then informs the DMA engine that there are packets ready to
  59  *  be transmitted.  Once the controller is finished transmitting
  60  *  the packet, an interrupt may be triggered (under the same
  61  *  conditions as for reception, but depending on the TXF bit).
  62  *  The driver then cleans up the buffer.
  63  */
  64
  65 #include <linux/kernel.h>
  66 #include <linux/string.h>
  67 #include <linux/errno.h>
  68 #include <linux/unistd.h>
  69 #include <linux/slab.h>
  70 #include <linux/interrupt.h>
  71 #include <linux/init.h>
  72 #include <linux/delay.h>
  73 #include <linux/netdevice.h>
  74 #include <linux/etherdevice.h>
  75 #include <linux/skbuff.h>
  76 #include <linux/if_vlan.h>
  77 #include <linux/spinlock.h>
  78 #include <linux/mm.h>
  79 #include <linux/of_mdio.h>
  80 #include <linux/of_platform.h>
  81 #include <linux/ip.h>
  82 #include <linux/tcp.h>
  83 #include <linux/udp.h>
  84 #include <linux/in.h>
  85 #include <linux/net_tstamp.h>
  86
  87 #include <asm/io.h>
  88 #include <asm/irq.h>
  89 #include <asm/uaccess.h>
  90 #include <linux/module.h>
  91 #include <linux/dma-mapping.h>
  92 #include <linux/crc32.h>
  93 #include <linux/mii.h>
  94 #include <linux/phy.h>
  95 #include <linux/phy_fixed.h>
  96 #include <linux/of.h>
  97
  98 #include "gianfar.h"
  99 #include "fsl_pq_mdio.h"
 100
 101 #define TX_TIMEOUT      (1*HZ)
 102 #undef BRIEF_GFAR_ERRORS
 103 #undef VERBOSE_GFAR_ERRORS
 104
 105 const char gfar_driver_name[] = "Gianfar Ethernet";
 106 const char gfar_driver_version[] = "1.3";
 107
 108 static int gfar_enet_open(struct net_device *dev);
 109 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 110 static void gfar_reset_task(struct work_struct *work);
 111 static void gfar_timeout(struct net_device *dev);
 112 static int gfar_close(struct net_device *dev);
 113 struct sk_buff *gfar_new_skb(struct net_device *dev);
 114 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 115                 struct sk_buff *skb);
 116 static int gfar_set_mac_address(struct net_device *dev);
 117 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 118 static irqreturn_t gfar_error(int irq, void *dev_id);
 119 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 120 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 121 static void adjust_link(struct net_device *dev);
 122 static void init_registers(struct net_device *dev);
 123 static int init_phy(struct net_device *dev);
 124 static int gfar_probe(struct of_device *ofdev,
 125                 const struct of_device_id *match);
 126 static int gfar_remove(struct of_device *ofdev);
 127 static void free_skb_resources(struct gfar_private *priv);
 128 static void gfar_set_multi(struct net_device *dev);
 129 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 130 static void gfar_configure_serdes(struct net_device *dev);
 131 static int gfar_poll(struct napi_struct *napi, int budget);
 132 #ifdef CONFIG_NET_POLL_CONTROLLER
 133 static void gfar_netpoll(struct net_device *dev);
 134 #endif
 135 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 136 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 137 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 138                               int amount_pull);
 139 static void gfar_vlan_rx_register(struct net_device *netdev,
 140                                 struct vlan_group *grp);
 141 void gfar_halt(struct net_device *dev);
 142 static void gfar_halt_nodisable(struct net_device *dev);
 143 void gfar_start(struct net_device *dev);
 144 static void gfar_clear_exact_match(struct net_device *dev);
 145 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
 146 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 147
 148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 150 MODULE_LICENSE("GPL");
 151
 152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 153                             dma_addr_t buf)
 154 {
 155         u32 lstatus;
 156
 157         bdp->bufPtr = buf;
 158
 159         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 160         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 161                 lstatus |= BD_LFLAG(RXBD_WRAP);
 162
 163         eieio();
 164
 165         bdp->lstatus = lstatus;
 166 }
 167
 168 static int gfar_init_bds(struct net_device *ndev)
 169 {
 170         struct gfar_private *priv = netdev_priv(ndev);
 171         struct gfar_priv_tx_q *tx_queue = NULL;
 172         struct gfar_priv_rx_q *rx_queue = NULL;
 173         struct txbd8 *txbdp;
 174         struct rxbd8 *rxbdp;
 175         int i, j;
 176
 177         for (i = 0; i < priv->num_tx_queues; i++) {
 178                 tx_queue = priv->tx_queue[i];
 179                 /* Initialize some variables in our dev structure */
 180                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 181                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 182                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 183                 tx_queue->skb_curtx = 0;
 184                 tx_queue->skb_dirtytx = 0;
 185
 186                 /* Initialize Transmit Descriptor Ring */
 187                 txbdp = tx_queue->tx_bd_base;
 188                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 189                         txbdp->lstatus = 0;
 190                         txbdp->bufPtr = 0;
 191                         txbdp++;
 192                 }
 193
 194                 /* Set the last descriptor in the ring to indicate wrap */
 195                 txbdp--;
 196                 txbdp->status |= TXBD_WRAP;
 197         }
 198
 199         for (i = 0; i < priv->num_rx_queues; i++) {
 200                 rx_queue = priv->rx_queue[i];
 201                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 202                 rx_queue->skb_currx = 0;
 203                 rxbdp = rx_queue->rx_bd_base;
 204
 205                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 206                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 207
 208                         if (skb) {
 209                                 gfar_init_rxbdp(rx_queue, rxbdp,
 210                                                 rxbdp->bufPtr);
 211                         } else {
 212                                 skb = gfar_new_skb(ndev);
 213                                 if (!skb) {
 214                                         pr_err("%s: Can't allocate RX buffers\n",
 215                                                         ndev->name);
 216                                         goto err_rxalloc_fail;
 217                                 }
 218                                 rx_queue->rx_skbuff[j] = skb;
 219
 220                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 221                         }
 222
 223                         rxbdp++;
 224                 }
 225
 226         }
 227
 228         return 0;
 229
 230 err_rxalloc_fail:
 231         free_skb_resources(priv);
 232         return -ENOMEM;
 233 }
 234
 235 static int gfar_alloc_skb_resources(struct net_device *ndev)
 236 {
 237         void *vaddr;
 238         dma_addr_t addr;
 239         int i, j, k;
 240         struct gfar_private *priv = netdev_priv(ndev);
 241         struct device *dev = &priv->ofdev->dev;
 242         struct gfar_priv_tx_q *tx_queue = NULL;
 243         struct gfar_priv_rx_q *rx_queue = NULL;
 244
 245         priv->total_tx_ring_size = 0;
 246         for (i = 0; i < priv->num_tx_queues; i++)
 247                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 248
 249         priv->total_rx_ring_size = 0;
 250         for (i = 0; i < priv->num_rx_queues; i++)
 251                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 252
 253         /* Allocate memory for the buffer descriptors */
 254         vaddr = dma_alloc_coherent(dev,
 255                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 256                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 257                         &addr, GFP_KERNEL);
 258         if (!vaddr) {
 259                 if (netif_msg_ifup(priv))
 260                         pr_err("%s: Could not allocate buffer descriptors!\n",
 261                                ndev->name);
 262                 return -ENOMEM;
 263         }
 264
 265         for (i = 0; i < priv->num_tx_queues; i++) {
 266                 tx_queue = priv->tx_queue[i];
 267                 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
 268                 tx_queue->tx_bd_dma_base = addr;
 269                 tx_queue->dev = ndev;
 270                 /* enet DMA only understands physical addresses */
 271                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 272                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 273         }
 274
 275         /* Start the rx descriptor ring where the tx ring leaves off */
 276         for (i = 0; i < priv->num_rx_queues; i++) {
 277                 rx_queue = priv->rx_queue[i];
 278                 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
 279                 rx_queue->rx_bd_dma_base = addr;
 280                 rx_queue->dev = ndev;
 281                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 282                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 283         }
 284
 285         /* Setup the skbuff rings */
 286         for (i = 0; i < priv->num_tx_queues; i++) {
 287                 tx_queue = priv->tx_queue[i];
 288                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 289                                   tx_queue->tx_ring_size, GFP_KERNEL);
 290                 if (!tx_queue->tx_skbuff) {
 291                         if (netif_msg_ifup(priv))
 292                                 pr_err("%s: Could not allocate tx_skbuff\n",
 293                                                 ndev->name);
 294                         goto cleanup;
 295                 }
 296
 297                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 298                         tx_queue->tx_skbuff[k] = NULL;
 299         }
 300
 301         for (i = 0; i < priv->num_rx_queues; i++) {
 302                 rx_queue = priv->rx_queue[i];
 303                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 304                                   rx_queue->rx_ring_size, GFP_KERNEL);
 305
 306                 if (!rx_queue->rx_skbuff) {
 307                         if (netif_msg_ifup(priv))
 308                                 pr_err("%s: Could not allocate rx_skbuff\n",
 309                                        ndev->name);
 310                         goto cleanup;
 311                 }
 312
 313                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 314                         rx_queue->rx_skbuff[j] = NULL;
 315         }
 316
 317         if (gfar_init_bds(ndev))
 318                 goto cleanup;
 319
 320         return 0;
 321
 322 cleanup:
 323         free_skb_resources(priv);
 324         return -ENOMEM;
 325 }
 326
 327 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 328 {
 329         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 330         u32 __iomem *baddr;
 331         int i;
 332
 333         baddr = &regs->tbase0;
 334         for(i = 0; i < priv->num_tx_queues; i++) {
 335                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 336                 baddr   += 2;
 337         }
 338
 339         baddr = &regs->rbase0;
 340         for(i = 0; i < priv->num_rx_queues; i++) {
 341                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 342                 baddr   += 2;
 343         }
 344 }
 345
 346 static void gfar_init_mac(struct net_device *ndev)
 347 {
 348         struct gfar_private *priv = netdev_priv(ndev);
 349         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 350         u32 rctrl = 0;
 351         u32 tctrl = 0;
 352         u32 attrs = 0;
 353
 354         /* write the tx/rx base registers */
 355         gfar_init_tx_rx_base(priv);
 356
 357         /* Configure the coalescing support */
 358         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 359
 360         if (priv->rx_filer_enable) {
 361                 rctrl |= RCTRL_FILREN;
 362                 /* Program the RIR0 reg with the required distribution */
 363                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 364         }
 365
 366         if (priv->rx_csum_enable)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash) {
 370                 rctrl |= RCTRL_EXTHASH;
 371
 372                 gfar_clear_exact_match(ndev);
 373                 rctrl |= RCTRL_EMEN;
 374         }
 375
 376         if (priv->padding) {
 377                 rctrl &= ~RCTRL_PAL_MASK;
 378                 rctrl |= RCTRL_PADDING(priv->padding);
 379         }
 380
 381         /* Insert receive time stamps into padding alignment bytes */
 382         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 383                 rctrl &= ~RCTRL_PAL_MASK;
 384                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE | RCTRL_PADDING(8);
 385                 priv->padding = 8;
 386         }
 387
 388         /* keep vlan related bits if it's enabled */
 389         if (priv->vlgrp) {
 390                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 391                 tctrl |= TCTRL_VLINS;
 392         }
 393
 394         /* Init rctrl based on our settings */
 395         gfar_write(&regs->rctrl, rctrl);
 396
 397         if (ndev->features & NETIF_F_IP_CSUM)
 398                 tctrl |= TCTRL_INIT_CSUM;
 399
 400         tctrl |= TCTRL_TXSCHED_PRIO;
 401
 402         gfar_write(&regs->tctrl, tctrl);
 403
 404         /* Set the extraction length and index */
 405         attrs = ATTRELI_EL(priv->rx_stash_size) |
 406                 ATTRELI_EI(priv->rx_stash_index);
 407
 408         gfar_write(&regs->attreli, attrs);
 409
 410         /* Start with defaults, and add stashing or locking
 411          * depending on the approprate variables */
 412         attrs = ATTR_INIT_SETTINGS;
 413
 414         if (priv->bd_stash_en)
 415                 attrs |= ATTR_BDSTASH;
 416
 417         if (priv->rx_stash_size != 0)
 418                 attrs |= ATTR_BUFSTASH;
 419
 420         gfar_write(&regs->attr, attrs);
 421
 422         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 423         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 424         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 425 }
 426
 427 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 428 {
 429         struct gfar_private *priv = netdev_priv(dev);
 430         struct netdev_queue *txq;
 431         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 432         unsigned long tx_packets = 0, tx_bytes = 0;
 433         int i = 0;
 434
 435         for (i = 0; i < priv->num_rx_queues; i++) {
 436                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 437                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
 438                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 439         }
 440
 441         dev->stats.rx_packets = rx_packets;
 442         dev->stats.rx_bytes = rx_bytes;
 443         dev->stats.rx_dropped = rx_dropped;
 444
 445         for (i = 0; i < priv->num_tx_queues; i++) {
 446                 txq = netdev_get_tx_queue(dev, i);
 447                 tx_bytes += txq->tx_bytes;
 448                 tx_packets += txq->tx_packets;
 449         }
 450
 451         dev->stats.tx_bytes = tx_bytes;
 452         dev->stats.tx_packets = tx_packets;
 453
 454         return &dev->stats;
 455 }
 456
 457 static const struct net_device_ops gfar_netdev_ops = {
 458         .ndo_open = gfar_enet_open,
 459         .ndo_start_xmit = gfar_start_xmit,
 460         .ndo_stop = gfar_close,
 461         .ndo_change_mtu = gfar_change_mtu,
 462         .ndo_set_multicast_list = gfar_set_multi,
 463         .ndo_tx_timeout = gfar_timeout,
 464         .ndo_do_ioctl = gfar_ioctl,
 465         .ndo_get_stats = gfar_get_stats,
 466         .ndo_vlan_rx_register = gfar_vlan_rx_register,
 467         .ndo_set_mac_address = eth_mac_addr,
 468         .ndo_validate_addr = eth_validate_addr,
 469 #ifdef CONFIG_NET_POLL_CONTROLLER
 470         .ndo_poll_controller = gfar_netpoll,
 471 #endif
 472 };
 473
 474 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
 475 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
 476
 477 void lock_rx_qs(struct gfar_private *priv)
 478 {
 479         int i = 0x0;
 480
 481         for (i = 0; i < priv->num_rx_queues; i++)
 482                 spin_lock(&priv->rx_queue[i]->rxlock);
 483 }
 484
 485 void lock_tx_qs(struct gfar_private *priv)
 486 {
 487         int i = 0x0;
 488
 489         for (i = 0; i < priv->num_tx_queues; i++)
 490                 spin_lock(&priv->tx_queue[i]->txlock);
 491 }
 492
 493 void unlock_rx_qs(struct gfar_private *priv)
 494 {
 495         int i = 0x0;
 496
 497         for (i = 0; i < priv->num_rx_queues; i++)
 498                 spin_unlock(&priv->rx_queue[i]->rxlock);
 499 }
 500
 501 void unlock_tx_qs(struct gfar_private *priv)
 502 {
 503         int i = 0x0;
 504
 505         for (i = 0; i < priv->num_tx_queues; i++)
 506                 spin_unlock(&priv->tx_queue[i]->txlock);
 507 }
 508
 509 /* Returns 1 if incoming frames use an FCB */
 510 static inline int gfar_uses_fcb(struct gfar_private *priv)
 511 {
 512         return priv->vlgrp || priv->rx_csum_enable ||
 513                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 514 }
 515
 516 static void free_tx_pointers(struct gfar_private *priv)
 517 {
 518         int i = 0;
 519
 520         for (i = 0; i < priv->num_tx_queues; i++)
 521                 kfree(priv->tx_queue[i]);
 522 }
 523
 524 static void free_rx_pointers(struct gfar_private *priv)
 525 {
 526         int i = 0;
 527
 528         for (i = 0; i < priv->num_rx_queues; i++)
 529                 kfree(priv->rx_queue[i]);
 530 }
 531
 532 static void unmap_group_regs(struct gfar_private *priv)
 533 {
 534         int i = 0;
 535
 536         for (i = 0; i < MAXGROUPS; i++)
 537                 if (priv->gfargrp[i].regs)
 538                         iounmap(priv->gfargrp[i].regs);
 539 }
 540
 541 static void disable_napi(struct gfar_private *priv)
 542 {
 543         int i = 0;
 544
 545         for (i = 0; i < priv->num_grps; i++)
 546                 napi_disable(&priv->gfargrp[i].napi);
 547 }
 548
 549 static void enable_napi(struct gfar_private *priv)
 550 {
 551         int i = 0;
 552
 553         for (i = 0; i < priv->num_grps; i++)
 554                 napi_enable(&priv->gfargrp[i].napi);
 555 }
 556
 557 static int gfar_parse_group(struct device_node *np,
 558                 struct gfar_private *priv, const char *model)
 559 {
 560         u32 *queue_mask;
 561
 562         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 563         if (!priv->gfargrp[priv->num_grps].regs)
 564                 return -ENOMEM;
 565
 566         priv->gfargrp[priv->num_grps].interruptTransmit =
 567                         irq_of_parse_and_map(np, 0);
 568
 569         /* If we aren't the FEC we have multiple interrupts */
 570         if (model && strcasecmp(model, "FEC")) {
 571                 priv->gfargrp[priv->num_grps].interruptReceive =
 572                         irq_of_parse_and_map(np, 1);
 573                 priv->gfargrp[priv->num_grps].interruptError =
 574                         irq_of_parse_and_map(np,2);
 575                 if (priv->gfargrp[priv->num_grps].interruptTransmit < 0 ||
 576                         priv->gfargrp[priv->num_grps].interruptReceive < 0 ||
 577                         priv->gfargrp[priv->num_grps].interruptError < 0) {
 578                         return -EINVAL;
 579                 }
 580         }
 581
 582         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 583         priv->gfargrp[priv->num_grps].priv = priv;
 584         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 585         if(priv->mode == MQ_MG_MODE) {
 586                 queue_mask = (u32 *)of_get_property(np,
 587                                         "fsl,rx-bit-map", NULL);
 588                 priv->gfargrp[priv->num_grps].rx_bit_map =
 589                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 590                 queue_mask = (u32 *)of_get_property(np,
 591                                         "fsl,tx-bit-map", NULL);
 592                 priv->gfargrp[priv->num_grps].tx_bit_map =
 593                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 594         } else {
 595                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 596                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 597         }
 598         priv->num_grps++;
 599
 600         return 0;
 601 }
 602
 603 static int gfar_of_init(struct of_device *ofdev, struct net_device **pdev)
 604 {
 605         const char *model;
 606         const char *ctype;
 607         const void *mac_addr;
 608         int err = 0, i;
 609         struct net_device *dev = NULL;
 610         struct gfar_private *priv = NULL;
 611         struct device_node *np = ofdev->dev.of_node;
 612         struct device_node *child = NULL;
 613         const u32 *stash;
 614         const u32 *stash_len;
 615         const u32 *stash_idx;
 616         unsigned int num_tx_qs, num_rx_qs;
 617         u32 *tx_queues, *rx_queues;
 618
 619         if (!np || !of_device_is_available(np))
 620                 return -ENODEV;
 621
 622         /* parse the num of tx and rx queues */
 623         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 624         num_tx_qs = tx_queues ? *tx_queues : 1;
 625
 626         if (num_tx_qs > MAX_TX_QS) {
 627                 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 628                                 num_tx_qs, MAX_TX_QS);
 629                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 630                 return -EINVAL;
 631         }
 632
 633         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 634         num_rx_qs = rx_queues ? *rx_queues : 1;
 635
 636         if (num_rx_qs > MAX_RX_QS) {
 637                 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 638                                 num_tx_qs, MAX_TX_QS);
 639                 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
 640                 return -EINVAL;
 641         }
 642
 643         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 644         dev = *pdev;
 645         if (NULL == dev)
 646                 return -ENOMEM;
 647
 648         priv = netdev_priv(dev);
 649         priv->node = ofdev->dev.of_node;
 650         priv->ndev = dev;
 651
 652         dev->num_tx_queues = num_tx_qs;
 653         dev->real_num_tx_queues = num_tx_qs;
 654         priv->num_tx_queues = num_tx_qs;
 655         priv->num_rx_queues = num_rx_qs;
 656         priv->num_grps = 0x0;
 657
 658         model = of_get_property(np, "model", NULL);
 659
 660         for (i = 0; i < MAXGROUPS; i++)
 661                 priv->gfargrp[i].regs = NULL;
 662
 663         /* Parse and initialize group specific information */
 664         if (of_device_is_compatible(np, "fsl,etsec2")) {
 665                 priv->mode = MQ_MG_MODE;
 666                 for_each_child_of_node(np, child) {
 667                         err = gfar_parse_group(child, priv, model);
 668                         if (err)
 669                                 goto err_grp_init;
 670                 }
 671         } else {
 672                 priv->mode = SQ_SG_MODE;
 673                 err = gfar_parse_group(np, priv, model);
 674                 if(err)
 675                         goto err_grp_init;
 676         }
 677
 678         for (i = 0; i < priv->num_tx_queues; i++)
 679                priv->tx_queue[i] = NULL;
 680         for (i = 0; i < priv->num_rx_queues; i++)
 681                 priv->rx_queue[i] = NULL;
 682
 683         for (i = 0; i < priv->num_tx_queues; i++) {
 684                 priv->tx_queue[i] =  (struct gfar_priv_tx_q *)kzalloc(
 685                                 sizeof (struct gfar_priv_tx_q), GFP_KERNEL);
 686                 if (!priv->tx_queue[i]) {
 687                         err = -ENOMEM;
 688                         goto tx_alloc_failed;
 689                 }
 690                 priv->tx_queue[i]->tx_skbuff = NULL;
 691                 priv->tx_queue[i]->qindex = i;
 692                 priv->tx_queue[i]->dev = dev;
 693                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 694         }
 695
 696         for (i = 0; i < priv->num_rx_queues; i++) {
 697                 priv->rx_queue[i] = (struct gfar_priv_rx_q *)kzalloc(
 698                                         sizeof (struct gfar_priv_rx_q), GFP_KERNEL);
 699                 if (!priv->rx_queue[i]) {
 700                         err = -ENOMEM;
 701                         goto rx_alloc_failed;
 702                 }
 703                 priv->rx_queue[i]->rx_skbuff = NULL;
 704                 priv->rx_queue[i]->qindex = i;
 705                 priv->rx_queue[i]->dev = dev;
 706                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 707         }
 708
 709
 710         stash = of_get_property(np, "bd-stash", NULL);
 711
 712         if (stash) {
 713                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 714                 priv->bd_stash_en = 1;
 715         }
 716
 717         stash_len = of_get_property(np, "rx-stash-len", NULL);
 718
 719         if (stash_len)
 720                 priv->rx_stash_size = *stash_len;
 721
 722         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 723
 724         if (stash_idx)
 725                 priv->rx_stash_index = *stash_idx;
 726
 727         if (stash_len || stash_idx)
 728                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 729
 730         mac_addr = of_get_mac_address(np);
 731         if (mac_addr)
 732                 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
 733
 734         if (model && !strcasecmp(model, "TSEC"))
 735                 priv->device_flags =
 736                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 737                         FSL_GIANFAR_DEV_HAS_COALESCE |
 738                         FSL_GIANFAR_DEV_HAS_RMON |
 739                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 740         if (model && !strcasecmp(model, "eTSEC"))
 741                 priv->device_flags =
 742                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 743                         FSL_GIANFAR_DEV_HAS_COALESCE |
 744                         FSL_GIANFAR_DEV_HAS_RMON |
 745                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 746                         FSL_GIANFAR_DEV_HAS_PADDING |
 747                         FSL_GIANFAR_DEV_HAS_CSUM |
 748                         FSL_GIANFAR_DEV_HAS_VLAN |
 749                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 750                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 751                         FSL_GIANFAR_DEV_HAS_TIMER;
 752
 753         ctype = of_get_property(np, "phy-connection-type", NULL);
 754
 755         /* We only care about rgmii-id.  The rest are autodetected */
 756         if (ctype && !strcmp(ctype, "rgmii-id"))
 757                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 758         else
 759                 priv->interface = PHY_INTERFACE_MODE_MII;
 760
 761         if (of_get_property(np, "fsl,magic-packet", NULL))
 762                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 763
 764         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 765
 766         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 767         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 768
 769         return 0;
 770
 771 rx_alloc_failed:
 772         free_rx_pointers(priv);
 773 tx_alloc_failed:
 774         free_tx_pointers(priv);
 775 err_grp_init:
 776         unmap_group_regs(priv);
 777         free_netdev(dev);
 778         return err;
 779 }
 780
 781 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 782                         struct ifreq *ifr, int cmd)
 783 {
 784         struct hwtstamp_config config;
 785         struct gfar_private *priv = netdev_priv(netdev);
 786
 787         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 788                 return -EFAULT;
 789
 790         /* reserved for future extensions */
 791         if (config.flags)
 792                 return -EINVAL;
 793
 794         switch (config.tx_type) {
 795         case HWTSTAMP_TX_OFF:
 796                 priv->hwts_tx_en = 0;
 797                 break;
 798         case HWTSTAMP_TX_ON:
 799                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 800                         return -ERANGE;
 801                 priv->hwts_tx_en = 1;
 802                 break;
 803         default:
 804                 return -ERANGE;
 805         }
 806
 807         switch (config.rx_filter) {
 808         case HWTSTAMP_FILTER_NONE:
 809                 priv->hwts_rx_en = 0;
 810                 break;
 811         default:
 812                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 813                         return -ERANGE;
 814                 priv->hwts_rx_en = 1;
 815                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 816                 break;
 817         }
 818
 819         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 820                 -EFAULT : 0;
 821 }
 822
 823 /* Ioctl MII Interface */
 824 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 825 {
 826         struct gfar_private *priv = netdev_priv(dev);
 827
 828         if (!netif_running(dev))
 829                 return -EINVAL;
 830
 831         if (cmd == SIOCSHWTSTAMP)
 832                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 833
 834         if (!priv->phydev)
 835                 return -ENODEV;
 836
 837         return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
 838 }
 839
 840 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 841 {
 842         unsigned int new_bit_map = 0x0;
 843         int mask = 0x1 << (max_qs - 1), i;
 844         for (i = 0; i < max_qs; i++) {
 845                 if (bit_map & mask)
 846                         new_bit_map = new_bit_map + (1 << i);
 847                 mask = mask >> 0x1;
 848         }
 849         return new_bit_map;
 850 }
 851
 852 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 853                                    u32 class)
 854 {
 855         u32 rqfpr = FPR_FILER_MASK;
 856         u32 rqfcr = 0x0;
 857
 858         rqfar--;
 859         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 860         ftp_rqfpr[rqfar] = rqfpr;
 861         ftp_rqfcr[rqfar] = rqfcr;
 862         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 863
 864         rqfar--;
 865         rqfcr = RQFCR_CMP_NOMATCH;
 866         ftp_rqfpr[rqfar] = rqfpr;
 867         ftp_rqfcr[rqfar] = rqfcr;
 868         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 869
 870         rqfar--;
 871         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 872         rqfpr = class;
 873         ftp_rqfcr[rqfar] = rqfcr;
 874         ftp_rqfpr[rqfar] = rqfpr;
 875         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 876
 877         rqfar--;
 878         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 879         rqfpr = class;
 880         ftp_rqfcr[rqfar] = rqfcr;
 881         ftp_rqfpr[rqfar] = rqfpr;
 882         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 883
 884         return rqfar;
 885 }
 886
 887 static void gfar_init_filer_table(struct gfar_private *priv)
 888 {
 889         int i = 0x0;
 890         u32 rqfar = MAX_FILER_IDX;
 891         u32 rqfcr = 0x0;
 892         u32 rqfpr = FPR_FILER_MASK;
 893
 894         /* Default rule */
 895         rqfcr = RQFCR_CMP_MATCH;
 896         ftp_rqfcr[rqfar] = rqfcr;
 897         ftp_rqfpr[rqfar] = rqfpr;
 898         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 899
 900         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 901         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 902         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 903         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 904         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 905         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 906
 907         /* cur_filer_idx indicated the fisrt non-masked rule */
 908         priv->cur_filer_idx = rqfar;
 909
 910         /* Rest are masked rules */
 911         rqfcr = RQFCR_CMP_NOMATCH;
 912         for (i = 0; i < rqfar; i++) {
 913                 ftp_rqfcr[i] = rqfcr;
 914                 ftp_rqfpr[i] = rqfpr;
 915                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 916         }
 917 }
 918
 919 /* Set up the ethernet device structure, private data,
 920  * and anything else we need before we start */
 921 static int gfar_probe(struct of_device *ofdev,
 922                 const struct of_device_id *match)
 923 {
 924         u32 tempval;
 925         struct net_device *dev = NULL;
 926         struct gfar_private *priv = NULL;
 927         struct gfar __iomem *regs = NULL;
 928         int err = 0, i, grp_idx = 0;
 929         int len_devname;
 930         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 931         u32 isrg = 0;
 932         u32 __iomem *baddr;
 933
 934         err = gfar_of_init(ofdev, &dev);
 935
 936         if (err)
 937                 return err;
 938
 939         priv = netdev_priv(dev);
 940         priv->ndev = dev;
 941         priv->ofdev = ofdev;
 942         priv->node = ofdev->dev.of_node;
 943         SET_NETDEV_DEV(dev, &ofdev->dev);
 944
 945         spin_lock_init(&priv->bflock);
 946         INIT_WORK(&priv->reset_task, gfar_reset_task);
 947
 948         dev_set_drvdata(&ofdev->dev, priv);
 949         regs = priv->gfargrp[0].regs;
 950
 951         /* Stop the DMA engine now, in case it was running before */
 952         /* (The firmware could have used it, and left it running). */
 953         gfar_halt(dev);
 954
 955         /* Reset MAC layer */
 956         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
 957
 958         /* We need to delay at least 3 TX clocks */
 959         udelay(2);
 960
 961         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
 962         gfar_write(&regs->maccfg1, tempval);
 963
 964         /* Initialize MACCFG2. */
 965         gfar_write(&regs->maccfg2, MACCFG2_INIT_SETTINGS);
 966
 967         /* Initialize ECNTRL */
 968         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
 969
 970         /* Set the dev->base_addr to the gfar reg region */
 971         dev->base_addr = (unsigned long) regs;
 972
 973         SET_NETDEV_DEV(dev, &ofdev->dev);
 974
 975         /* Fill in the dev structure */
 976         dev->watchdog_timeo = TX_TIMEOUT;
 977         dev->mtu = 1500;
 978         dev->netdev_ops = &gfar_netdev_ops;
 979         dev->ethtool_ops = &gfar_ethtool_ops;
 980
 981         /* Register for napi ...We are registering NAPI for each grp */
 982         for (i = 0; i < priv->num_grps; i++)
 983                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
 984
 985         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
 986                 priv->rx_csum_enable = 1;
 987                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
 988         } else
 989                 priv->rx_csum_enable = 0;
 990
 991         priv->vlgrp = NULL;
 992
 993         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
 994                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
 995
 996         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
 997                 priv->extended_hash = 1;
 998                 priv->hash_width = 9;
 999
1000                 priv->hash_regs[0] = &regs->igaddr0;
1001                 priv->hash_regs[1] = &regs->igaddr1;
1002                 priv->hash_regs[2] = &regs->igaddr2;
1003                 priv->hash_regs[3] = &regs->igaddr3;
1004                 priv->hash_regs[4] = &regs->igaddr4;
1005                 priv->hash_regs[5] = &regs->igaddr5;
1006                 priv->hash_regs[6] = &regs->igaddr6;
1007                 priv->hash_regs[7] = &regs->igaddr7;
1008                 priv->hash_regs[8] = &regs->gaddr0;
1009                 priv->hash_regs[9] = &regs->gaddr1;
1010                 priv->hash_regs[10] = &regs->gaddr2;
1011                 priv->hash_regs[11] = &regs->gaddr3;
1012                 priv->hash_regs[12] = &regs->gaddr4;
1013                 priv->hash_regs[13] = &regs->gaddr5;
1014                 priv->hash_regs[14] = &regs->gaddr6;
1015                 priv->hash_regs[15] = &regs->gaddr7;
1016
1017         } else {
1018                 priv->extended_hash = 0;
1019                 priv->hash_width = 8;
1020
1021                 priv->hash_regs[0] = &regs->gaddr0;
1022                 priv->hash_regs[1] = &regs->gaddr1;
1023                 priv->hash_regs[2] = &regs->gaddr2;
1024                 priv->hash_regs[3] = &regs->gaddr3;
1025                 priv->hash_regs[4] = &regs->gaddr4;
1026                 priv->hash_regs[5] = &regs->gaddr5;
1027                 priv->hash_regs[6] = &regs->gaddr6;
1028                 priv->hash_regs[7] = &regs->gaddr7;
1029         }
1030
1031         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1032                 priv->padding = DEFAULT_PADDING;
1033         else
1034                 priv->padding = 0;
1035
1036         if (dev->features & NETIF_F_IP_CSUM ||
1037                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1038                 dev->hard_header_len += GMAC_FCB_LEN;
1039
1040         /* Program the isrg regs only if number of grps > 1 */
1041         if (priv->num_grps > 1) {
1042                 baddr = &regs->isrg0;
1043                 for (i = 0; i < priv->num_grps; i++) {
1044                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1045                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1046                         gfar_write(baddr, isrg);
1047                         baddr++;
1048                         isrg = 0x0;
1049                 }
1050         }
1051
1052         /* Need to reverse the bit maps as  bit_map's MSB is q0
1053          * but, for_each_set_bit parses from right to left, which
1054          * basically reverses the queue numbers */
1055         for (i = 0; i< priv->num_grps; i++) {
1056                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1057                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1058                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1059                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1060         }
1061
1062         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1063          * also assign queues to groups */
1064         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1065                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1066                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1067                                 priv->num_rx_queues) {
1068                         priv->gfargrp[grp_idx].num_rx_queues++;
1069                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1070                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1071                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1072                 }
1073                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1074                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1075                                 priv->num_tx_queues) {
1076                         priv->gfargrp[grp_idx].num_tx_queues++;
1077                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1078                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1079                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1080                 }
1081                 priv->gfargrp[grp_idx].rstat = rstat;
1082                 priv->gfargrp[grp_idx].tstat = tstat;
1083                 rstat = tstat =0;
1084         }
1085
1086         gfar_write(&regs->rqueue, rqueue);
1087         gfar_write(&regs->tqueue, tqueue);
1088
1089         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1090
1091         /* Initializing some of the rx/tx queue level parameters */
1092         for (i = 0; i < priv->num_tx_queues; i++) {
1093                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1094                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1095                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1096                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1097         }
1098
1099         for (i = 0; i < priv->num_rx_queues; i++) {
1100                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1101                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1102                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1103         }
1104
1105         /* enable filer if using multiple RX queues*/
1106         if(priv->num_rx_queues > 1)
1107                 priv->rx_filer_enable = 1;
1108         /* Enable most messages by default */
1109         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1110
1111         /* Carrier starts down, phylib will bring it up */
1112         netif_carrier_off(dev);
1113
1114         err = register_netdev(dev);
1115
1116         if (err) {
1117                 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1118                                 dev->name);
1119                 goto register_fail;
1120         }
1121
1122         device_init_wakeup(&dev->dev,
1123                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1124
1125         /* fill out IRQ number and name fields */
1126         len_devname = strlen(dev->name);
1127         for (i = 0; i < priv->num_grps; i++) {
1128                 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1129                                 len_devname);
1130                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1131                         strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1132                                 "_g", sizeof("_g"));
1133                         priv->gfargrp[i].int_name_tx[
1134                                 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1135                         strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1136                                 priv->gfargrp[i].int_name_tx)],
1137                                 "_tx", sizeof("_tx") + 1);
1138
1139                         strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1140                                         len_devname);
1141                         strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1142                                         "_g", sizeof("_g"));
1143                         priv->gfargrp[i].int_name_rx[
1144                                 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1145                         strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1146                                 priv->gfargrp[i].int_name_rx)],
1147                                 "_rx", sizeof("_rx") + 1);
1148
1149                         strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1150                                         len_devname);
1151                         strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1152                                 "_g", sizeof("_g"));
1153                         priv->gfargrp[i].int_name_er[strlen(
1154                                         priv->gfargrp[i].int_name_er)] = i+48;
1155                         strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1156                                 priv->gfargrp[i].int_name_er)],
1157                                 "_er", sizeof("_er") + 1);
1158                 } else
1159                         priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1160         }
1161
1162         /* Initialize the filer table */
1163         gfar_init_filer_table(priv);
1164
1165         /* Create all the sysfs files */
1166         gfar_init_sysfs(dev);
1167
1168         /* Print out the device info */
1169         printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1170
1171         /* Even more device info helps when determining which kernel */
1172         /* provided which set of benchmarks. */
1173         printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1174         for (i = 0; i < priv->num_rx_queues; i++)
1175                 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
1176                         dev->name, i, priv->rx_queue[i]->rx_ring_size);
1177         for(i = 0; i < priv->num_tx_queues; i++)
1178                  printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
1179                         dev->name, i, priv->tx_queue[i]->tx_ring_size);
1180
1181         return 0;
1182
1183 register_fail:
1184         unmap_group_regs(priv);
1185         free_tx_pointers(priv);
1186         free_rx_pointers(priv);
1187         if (priv->phy_node)
1188                 of_node_put(priv->phy_node);
1189         if (priv->tbi_node)
1190                 of_node_put(priv->tbi_node);
1191         free_netdev(dev);
1192         return err;
1193 }
1194
1195 static int gfar_remove(struct of_device *ofdev)
1196 {
1197         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1198
1199         if (priv->phy_node)
1200                 of_node_put(priv->phy_node);
1201         if (priv->tbi_node)
1202                 of_node_put(priv->tbi_node);
1203
1204         dev_set_drvdata(&ofdev->dev, NULL);
1205
1206         unregister_netdev(priv->ndev);
1207         unmap_group_regs(priv);
1208         free_netdev(priv->ndev);
1209
1210         return 0;
1211 }
1212
1213 #ifdef CONFIG_PM
1214
1215 static int gfar_suspend(struct device *dev)
1216 {
1217         struct gfar_private *priv = dev_get_drvdata(dev);
1218         struct net_device *ndev = priv->ndev;
1219         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1220         unsigned long flags;
1221         u32 tempval;
1222
1223         int magic_packet = priv->wol_en &&
1224                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1225
1226         netif_device_detach(ndev);
1227
1228         if (netif_running(ndev)) {
1229
1230                 local_irq_save(flags);
1231                 lock_tx_qs(priv);
1232                 lock_rx_qs(priv);
1233
1234                 gfar_halt_nodisable(ndev);
1235
1236                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1237                 tempval = gfar_read(&regs->maccfg1);
1238
1239                 tempval &= ~MACCFG1_TX_EN;
1240
1241                 if (!magic_packet)
1242                         tempval &= ~MACCFG1_RX_EN;
1243
1244                 gfar_write(&regs->maccfg1, tempval);
1245
1246                 unlock_rx_qs(priv);
1247                 unlock_tx_qs(priv);
1248                 local_irq_restore(flags);
1249
1250                 disable_napi(priv);
1251
1252                 if (magic_packet) {
1253                         /* Enable interrupt on Magic Packet */
1254                         gfar_write(&regs->imask, IMASK_MAG);
1255
1256                         /* Enable Magic Packet mode */
1257                         tempval = gfar_read(&regs->maccfg2);
1258                         tempval |= MACCFG2_MPEN;
1259                         gfar_write(&regs->maccfg2, tempval);
1260                 } else {
1261                         phy_stop(priv->phydev);
1262                 }
1263         }
1264
1265         return 0;
1266 }
1267
1268 static int gfar_resume(struct device *dev)
1269 {
1270         struct gfar_private *priv = dev_get_drvdata(dev);
1271         struct net_device *ndev = priv->ndev;
1272         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273         unsigned long flags;
1274         u32 tempval;
1275         int magic_packet = priv->wol_en &&
1276                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1277
1278         if (!netif_running(ndev)) {
1279                 netif_device_attach(ndev);
1280                 return 0;
1281         }
1282
1283         if (!magic_packet && priv->phydev)
1284                 phy_start(priv->phydev);
1285
1286         /* Disable Magic Packet mode, in case something
1287          * else woke us up.
1288          */
1289         local_irq_save(flags);
1290         lock_tx_qs(priv);
1291         lock_rx_qs(priv);
1292
1293         tempval = gfar_read(&regs->maccfg2);
1294         tempval &= ~MACCFG2_MPEN;
1295         gfar_write(&regs->maccfg2, tempval);
1296
1297         gfar_start(ndev);
1298
1299         unlock_rx_qs(priv);
1300         unlock_tx_qs(priv);
1301         local_irq_restore(flags);
1302
1303         netif_device_attach(ndev);
1304
1305         enable_napi(priv);
1306
1307         return 0;
1308 }
1309
1310 static int gfar_restore(struct device *dev)
1311 {
1312         struct gfar_private *priv = dev_get_drvdata(dev);
1313         struct net_device *ndev = priv->ndev;
1314
1315         if (!netif_running(ndev))
1316                 return 0;
1317
1318         gfar_init_bds(ndev);
1319         init_registers(ndev);
1320         gfar_set_mac_address(ndev);
1321         gfar_init_mac(ndev);
1322         gfar_start(ndev);
1323
1324         priv->oldlink = 0;
1325         priv->oldspeed = 0;
1326         priv->oldduplex = -1;
1327
1328         if (priv->phydev)
1329                 phy_start(priv->phydev);
1330
1331         netif_device_attach(ndev);
1332         enable_napi(priv);
1333
1334         return 0;
1335 }
1336
1337 static struct dev_pm_ops gfar_pm_ops = {
1338         .suspend = gfar_suspend,
1339         .resume = gfar_resume,
1340         .freeze = gfar_suspend,
1341         .thaw = gfar_resume,
1342         .restore = gfar_restore,
1343 };
1344
1345 #define GFAR_PM_OPS (&gfar_pm_ops)
1346
1347 #else
1348
1349 #define GFAR_PM_OPS NULL
1350
1351 #endif
1352
1353 /* Reads the controller's registers to determine what interface
1354  * connects it to the PHY.
1355  */
1356 static phy_interface_t gfar_get_interface(struct net_device *dev)
1357 {
1358         struct gfar_private *priv = netdev_priv(dev);
1359         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1360         u32 ecntrl;
1361
1362         ecntrl = gfar_read(&regs->ecntrl);
1363
1364         if (ecntrl & ECNTRL_SGMII_MODE)
1365                 return PHY_INTERFACE_MODE_SGMII;
1366
1367         if (ecntrl & ECNTRL_TBI_MODE) {
1368                 if (ecntrl & ECNTRL_REDUCED_MODE)
1369                         return PHY_INTERFACE_MODE_RTBI;
1370                 else
1371                         return PHY_INTERFACE_MODE_TBI;
1372         }
1373
1374         if (ecntrl & ECNTRL_REDUCED_MODE) {
1375                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1376                         return PHY_INTERFACE_MODE_RMII;
1377                 else {
1378                         phy_interface_t interface = priv->interface;
1379
1380                         /*
1381                          * This isn't autodetected right now, so it must
1382                          * be set by the device tree or platform code.
1383                          */
1384                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1385                                 return PHY_INTERFACE_MODE_RGMII_ID;
1386
1387                         return PHY_INTERFACE_MODE_RGMII;
1388                 }
1389         }
1390
1391         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1392                 return PHY_INTERFACE_MODE_GMII;
1393
1394         return PHY_INTERFACE_MODE_MII;
1395 }
1396
1397
1398 /* Initializes driver's PHY state, and attaches to the PHY.
1399  * Returns 0 on success.
1400  */
1401 static int init_phy(struct net_device *dev)
1402 {
1403         struct gfar_private *priv = netdev_priv(dev);
1404         uint gigabit_support =
1405                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1406                 SUPPORTED_1000baseT_Full : 0;
1407         phy_interface_t interface;
1408
1409         priv->oldlink = 0;
1410         priv->oldspeed = 0;
1411         priv->oldduplex = -1;
1412
1413         interface = gfar_get_interface(dev);
1414
1415         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1416                                       interface);
1417         if (!priv->phydev)
1418                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1419                                                          interface);
1420         if (!priv->phydev) {
1421                 dev_err(&dev->dev, "could not attach to PHY\n");
1422                 return -ENODEV;
1423         }
1424
1425         if (interface == PHY_INTERFACE_MODE_SGMII)
1426                 gfar_configure_serdes(dev);
1427
1428         /* Remove any features not supported by the controller */
1429         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1430         priv->phydev->advertising = priv->phydev->supported;
1431
1432         return 0;
1433 }
1434
1435 /*
1436  * Initialize TBI PHY interface for communicating with the
1437  * SERDES lynx PHY on the chip.  We communicate with this PHY
1438  * through the MDIO bus on each controller, treating it as a
1439  * "normal" PHY at the address found in the TBIPA register.  We assume
1440  * that the TBIPA register is valid.  Either the MDIO bus code will set
1441  * it to a value that doesn't conflict with other PHYs on the bus, or the
1442  * value doesn't matter, as there are no other PHYs on the bus.
1443  */
1444 static void gfar_configure_serdes(struct net_device *dev)
1445 {
1446         struct gfar_private *priv = netdev_priv(dev);
1447         struct phy_device *tbiphy;
1448
1449         if (!priv->tbi_node) {
1450                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1451                                     "device tree specify a tbi-handle\n");
1452                 return;
1453         }
1454
1455         tbiphy = of_phy_find_device(priv->tbi_node);
1456         if (!tbiphy) {
1457                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1458                 return;
1459         }
1460
1461         /*
1462          * If the link is already up, we must already be ok, and don't need to
1463          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1464          * everything for us?  Resetting it takes the link down and requires
1465          * several seconds for it to come back.
1466          */
1467         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1468                 return;
1469
1470         /* Single clk mode, mii mode off(for serdes communication) */
1471         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1472
1473         phy_write(tbiphy, MII_ADVERTISE,
1474                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1475                         ADVERTISE_1000XPSE_ASYM);
1476
1477         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1478                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1479 }
1480
1481 static void init_registers(struct net_device *dev)
1482 {
1483         struct gfar_private *priv = netdev_priv(dev);
1484         struct gfar __iomem *regs = NULL;
1485         int i = 0;
1486
1487         for (i = 0; i < priv->num_grps; i++) {
1488                 regs = priv->gfargrp[i].regs;
1489                 /* Clear IEVENT */
1490                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1491
1492                 /* Initialize IMASK */
1493                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1494         }
1495
1496         regs = priv->gfargrp[0].regs;
1497         /* Init hash registers to zero */
1498         gfar_write(&regs->igaddr0, 0);
1499         gfar_write(&regs->igaddr1, 0);
1500         gfar_write(&regs->igaddr2, 0);
1501         gfar_write(&regs->igaddr3, 0);
1502         gfar_write(&regs->igaddr4, 0);
1503         gfar_write(&regs->igaddr5, 0);
1504         gfar_write(&regs->igaddr6, 0);
1505         gfar_write(&regs->igaddr7, 0);
1506
1507         gfar_write(&regs->gaddr0, 0);
1508         gfar_write(&regs->gaddr1, 0);
1509         gfar_write(&regs->gaddr2, 0);
1510         gfar_write(&regs->gaddr3, 0);
1511         gfar_write(&regs->gaddr4, 0);
1512         gfar_write(&regs->gaddr5, 0);
1513         gfar_write(&regs->gaddr6, 0);
1514         gfar_write(&regs->gaddr7, 0);
1515
1516         /* Zero out the rmon mib registers if it has them */
1517         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1518                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1519
1520                 /* Mask off the CAM interrupts */
1521                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1522                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1523         }
1524
1525         /* Initialize the max receive buffer length */
1526         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1527
1528         /* Initialize the Minimum Frame Length Register */
1529         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1530 }
1531
1532
1533 /* Halt the receive and transmit queues */
1534 static void gfar_halt_nodisable(struct net_device *dev)
1535 {
1536         struct gfar_private *priv = netdev_priv(dev);
1537         struct gfar __iomem *regs = NULL;
1538         u32 tempval;
1539         int i = 0;
1540
1541         for (i = 0; i < priv->num_grps; i++) {
1542                 regs = priv->gfargrp[i].regs;
1543                 /* Mask all interrupts */
1544                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1545
1546                 /* Clear all interrupts */
1547                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1548         }
1549
1550         regs = priv->gfargrp[0].regs;
1551         /* Stop the DMA, and wait for it to stop */
1552         tempval = gfar_read(&regs->dmactrl);
1553         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1554             != (DMACTRL_GRS | DMACTRL_GTS)) {
1555                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1556                 gfar_write(&regs->dmactrl, tempval);
1557
1558                 spin_event_timeout(((gfar_read(&regs->ievent) &
1559                          (IEVENT_GRSC | IEVENT_GTSC)) ==
1560                          (IEVENT_GRSC | IEVENT_GTSC)), -1, 0);
1561         }
1562 }
1563
1564 /* Halt the receive and transmit queues */
1565 void gfar_halt(struct net_device *dev)
1566 {
1567         struct gfar_private *priv = netdev_priv(dev);
1568         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1569         u32 tempval;
1570
1571         gfar_halt_nodisable(dev);
1572
1573         /* Disable Rx and Tx */
1574         tempval = gfar_read(&regs->maccfg1);
1575         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1576         gfar_write(&regs->maccfg1, tempval);
1577 }
1578
1579 static void free_grp_irqs(struct gfar_priv_grp *grp)
1580 {
1581         free_irq(grp->interruptError, grp);
1582         free_irq(grp->interruptTransmit, grp);
1583         free_irq(grp->interruptReceive, grp);
1584 }
1585
1586 void stop_gfar(struct net_device *dev)
1587 {
1588         struct gfar_private *priv = netdev_priv(dev);
1589         unsigned long flags;
1590         int i;
1591
1592         phy_stop(priv->phydev);
1593
1594
1595         /* Lock it down */
1596         local_irq_save(flags);
1597         lock_tx_qs(priv);
1598         lock_rx_qs(priv);
1599
1600         gfar_halt(dev);
1601
1602         unlock_rx_qs(priv);
1603         unlock_tx_qs(priv);
1604         local_irq_restore(flags);
1605
1606         /* Free the IRQs */
1607         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1608                 for (i = 0; i < priv->num_grps; i++)
1609                         free_grp_irqs(&priv->gfargrp[i]);
1610         } else {
1611                 for (i = 0; i < priv->num_grps; i++)
1612                         free_irq(priv->gfargrp[i].interruptTransmit,
1613                                         &priv->gfargrp[i]);
1614         }
1615
1616         free_skb_resources(priv);
1617 }
1618
1619 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1620 {
1621         struct txbd8 *txbdp;
1622         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1623         int i, j;
1624
1625         txbdp = tx_queue->tx_bd_base;
1626
1627         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1628                 if (!tx_queue->tx_skbuff[i])
1629                         continue;
1630
1631                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1632                                 txbdp->length, DMA_TO_DEVICE);
1633                 txbdp->lstatus = 0;
1634                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1635                                 j++) {
1636                         txbdp++;
1637                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1638                                         txbdp->length, DMA_TO_DEVICE);
1639                 }
1640                 txbdp++;
1641                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1642                 tx_queue->tx_skbuff[i] = NULL;
1643         }
1644         kfree(tx_queue->tx_skbuff);
1645 }
1646
1647 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1648 {
1649         struct rxbd8 *rxbdp;
1650         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1651         int i;
1652
1653         rxbdp = rx_queue->rx_bd_base;
1654
1655         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1656                 if (rx_queue->rx_skbuff[i]) {
1657                         dma_unmap_single(&priv->ofdev->dev,
1658                                         rxbdp->bufPtr, priv->rx_buffer_size,
1659                                         DMA_FROM_DEVICE);
1660                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1661                         rx_queue->rx_skbuff[i] = NULL;
1662                 }
1663                 rxbdp->lstatus = 0;
1664                 rxbdp->bufPtr = 0;
1665                 rxbdp++;
1666         }
1667         kfree(rx_queue->rx_skbuff);
1668 }
1669
1670 /* If there are any tx skbs or rx skbs still around, free them.
1671  * Then free tx_skbuff and rx_skbuff */
1672 static void free_skb_resources(struct gfar_private *priv)
1673 {
1674         struct gfar_priv_tx_q *tx_queue = NULL;
1675         struct gfar_priv_rx_q *rx_queue = NULL;
1676         int i;
1677
1678         /* Go through all the buffer descriptors and free their data buffers */
1679         for (i = 0; i < priv->num_tx_queues; i++) {
1680                 tx_queue = priv->tx_queue[i];
1681                 if(tx_queue->tx_skbuff)
1682                         free_skb_tx_queue(tx_queue);
1683         }
1684
1685         for (i = 0; i < priv->num_rx_queues; i++) {
1686                 rx_queue = priv->rx_queue[i];
1687                 if(rx_queue->rx_skbuff)
1688                         free_skb_rx_queue(rx_queue);
1689         }
1690
1691         dma_free_coherent(&priv->ofdev->dev,
1692                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1693                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1694                         priv->tx_queue[0]->tx_bd_base,
1695                         priv->tx_queue[0]->tx_bd_dma_base);
1696         skb_queue_purge(&priv->rx_recycle);
1697 }
1698
1699 void gfar_start(struct net_device *dev)
1700 {
1701         struct gfar_private *priv = netdev_priv(dev);
1702         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1703         u32 tempval;
1704         int i = 0;
1705
1706         /* Enable Rx and Tx in MACCFG1 */
1707         tempval = gfar_read(&regs->maccfg1);
1708         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1709         gfar_write(&regs->maccfg1, tempval);
1710
1711         /* Initialize DMACTRL to have WWR and WOP */
1712         tempval = gfar_read(&regs->dmactrl);
1713         tempval |= DMACTRL_INIT_SETTINGS;
1714         gfar_write(&regs->dmactrl, tempval);
1715
1716         /* Make sure we aren't stopped */
1717         tempval = gfar_read(&regs->dmactrl);
1718         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1719         gfar_write(&regs->dmactrl, tempval);
1720
1721         for (i = 0; i < priv->num_grps; i++) {
1722                 regs = priv->gfargrp[i].regs;
1723                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1724                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1725                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1726                 /* Unmask the interrupts we look for */
1727                 gfar_write(&regs->imask, IMASK_DEFAULT);
1728         }
1729
1730         dev->trans_start = jiffies; /* prevent tx timeout */
1731 }
1732
1733 void gfar_configure_coalescing(struct gfar_private *priv,
1734         unsigned long tx_mask, unsigned long rx_mask)
1735 {
1736         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1737         u32 __iomem *baddr;
1738         int i = 0;
1739
1740         /* Backward compatible case ---- even if we enable
1741          * multiple queues, there's only single reg to program
1742          */
1743         gfar_write(&regs->txic, 0);
1744         if(likely(priv->tx_queue[0]->txcoalescing))
1745                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1746
1747         gfar_write(&regs->rxic, 0);
1748         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1749                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1750
1751         if (priv->mode == MQ_MG_MODE) {
1752                 baddr = &regs->txic0;
1753                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1754                         if (likely(priv->tx_queue[i]->txcoalescing)) {
1755                                 gfar_write(baddr + i, 0);
1756                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1757                         }
1758                 }
1759
1760                 baddr = &regs->rxic0;
1761                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1762                         if (likely(priv->rx_queue[i]->rxcoalescing)) {
1763                                 gfar_write(baddr + i, 0);
1764                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1765                         }
1766                 }
1767         }
1768 }
1769
1770 static int register_grp_irqs(struct gfar_priv_grp *grp)
1771 {
1772         struct gfar_private *priv = grp->priv;
1773         struct net_device *dev = priv->ndev;
1774         int err;
1775
1776         /* If the device has multiple interrupts, register for
1777          * them.  Otherwise, only register for the one */
1778         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1779                 /* Install our interrupt handlers for Error,
1780                  * Transmit, and Receive */
1781                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1782                                 grp->int_name_er,grp)) < 0) {
1783                         if (netif_msg_intr(priv))
1784                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1785                                         dev->name, grp->interruptError);
1786
1787                                 goto err_irq_fail;
1788                 }
1789
1790                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1791                                 0, grp->int_name_tx, grp)) < 0) {
1792                         if (netif_msg_intr(priv))
1793                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1794                                         dev->name, grp->interruptTransmit);
1795                         goto tx_irq_fail;
1796                 }
1797
1798                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1799                                 grp->int_name_rx, grp)) < 0) {
1800                         if (netif_msg_intr(priv))
1801                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1802                                         dev->name, grp->interruptReceive);
1803                         goto rx_irq_fail;
1804                 }
1805         } else {
1806                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1807                                 grp->int_name_tx, grp)) < 0) {
1808                         if (netif_msg_intr(priv))
1809                                 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1810                                         dev->name, grp->interruptTransmit);
1811                         goto err_irq_fail;
1812                 }
1813         }
1814
1815         return 0;
1816
1817 rx_irq_fail:
1818         free_irq(grp->interruptTransmit, grp);
1819 tx_irq_fail:
1820         free_irq(grp->interruptError, grp);
1821 err_irq_fail:
1822         return err;
1823
1824 }
1825
1826 /* Bring the controller up and running */
1827 int startup_gfar(struct net_device *ndev)
1828 {
1829         struct gfar_private *priv = netdev_priv(ndev);
1830         struct gfar __iomem *regs = NULL;
1831         int err, i, j;
1832
1833         for (i = 0; i < priv->num_grps; i++) {
1834                 regs= priv->gfargrp[i].regs;
1835                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1836         }
1837
1838         regs= priv->gfargrp[0].regs;
1839         err = gfar_alloc_skb_resources(ndev);
1840         if (err)
1841                 return err;
1842
1843         gfar_init_mac(ndev);
1844
1845         for (i = 0; i < priv->num_grps; i++) {
1846                 err = register_grp_irqs(&priv->gfargrp[i]);
1847                 if (err) {
1848                         for (j = 0; j < i; j++)
1849                                 free_grp_irqs(&priv->gfargrp[j]);
1850                                 goto irq_fail;
1851                 }
1852         }
1853
1854         /* Start the controller */
1855         gfar_start(ndev);
1856
1857         phy_start(priv->phydev);
1858
1859         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1860
1861         return 0;
1862
1863 irq_fail:
1864         free_skb_resources(priv);
1865         return err;
1866 }
1867
1868 /* Called when something needs to use the ethernet device */
1869 /* Returns 0 for success. */
1870 static int gfar_enet_open(struct net_device *dev)
1871 {
1872         struct gfar_private *priv = netdev_priv(dev);
1873         int err;
1874
1875         enable_napi(priv);
1876
1877         skb_queue_head_init(&priv->rx_recycle);
1878
1879         /* Initialize a bunch of registers */
1880         init_registers(dev);
1881
1882         gfar_set_mac_address(dev);
1883
1884         err = init_phy(dev);
1885
1886         if (err) {
1887                 disable_napi(priv);
1888                 return err;
1889         }
1890
1891         err = startup_gfar(dev);
1892         if (err) {
1893                 disable_napi(priv);
1894                 return err;
1895         }
1896
1897         netif_tx_start_all_queues(dev);
1898
1899         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1900
1901         return err;
1902 }
1903
1904 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1905 {
1906         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1907
1908         memset(fcb, 0, GMAC_FCB_LEN);
1909
1910         return fcb;
1911 }
1912
1913 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1914 {
1915         u8 flags = 0;
1916
1917         /* If we're here, it's a IP packet with a TCP or UDP
1918          * payload.  We set it to checksum, using a pseudo-header
1919          * we provide
1920          */
1921         flags = TXFCB_DEFAULT;
1922
1923         /* Tell the controller what the protocol is */
1924         /* And provide the already calculated phcs */
1925         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1926                 flags |= TXFCB_UDP;
1927                 fcb->phcs = udp_hdr(skb)->check;
1928         } else
1929                 fcb->phcs = tcp_hdr(skb)->check;
1930
1931         /* l3os is the distance between the start of the
1932          * frame (skb->data) and the start of the IP hdr.
1933          * l4os is the distance between the start of the
1934          * l3 hdr and the l4 hdr */
1935         fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1936         fcb->l4os = skb_network_header_len(skb);
1937
1938         fcb->flags = flags;
1939 }
1940
1941 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1942 {
1943         fcb->flags |= TXFCB_VLN;
1944         fcb->vlctl = vlan_tx_tag_get(skb);
1945 }
1946
1947 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1948                                struct txbd8 *base, int ring_size)
1949 {
1950         struct txbd8 *new_bd = bdp + stride;
1951
1952         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
1953 }
1954
1955 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
1956                 int ring_size)
1957 {
1958         return skip_txbd(bdp, 1, base, ring_size);
1959 }
1960
1961 /* This is called by the kernel when a frame is ready for transmission. */
1962 /* It is pointed to by the dev->hard_start_xmit function pointer */
1963 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1964 {
1965         struct gfar_private *priv = netdev_priv(dev);
1966         struct gfar_priv_tx_q *tx_queue = NULL;
1967         struct netdev_queue *txq;
1968         struct gfar __iomem *regs = NULL;
1969         struct txfcb *fcb = NULL;
1970         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
1971         u32 lstatus;
1972         int i, rq = 0, do_tstamp = 0;
1973         u32 bufaddr;
1974         unsigned long flags;
1975         unsigned int nr_frags, nr_txbds, length;
1976         union skb_shared_tx *shtx;
1977
1978         rq = skb->queue_mapping;
1979         tx_queue = priv->tx_queue[rq];
1980         txq = netdev_get_tx_queue(dev, rq);
1981         base = tx_queue->tx_bd_base;
1982         regs = tx_queue->grp->regs;
1983         shtx = skb_tx(skb);
1984
1985         /* check if time stamp should be generated */
1986         if (unlikely(shtx->hardware && priv->hwts_tx_en))
1987                 do_tstamp = 1;
1988
1989         /* make space for additional header when fcb is needed */
1990         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
1991                         (priv->vlgrp && vlan_tx_tag_present(skb)) ||
1992                         unlikely(do_tstamp)) &&
1993                         (skb_headroom(skb) < GMAC_FCB_LEN)) {
1994                 struct sk_buff *skb_new;
1995
1996                 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
1997                 if (!skb_new) {
1998                         dev->stats.tx_errors++;
1999                         kfree_skb(skb);
2000                         return NETDEV_TX_OK;
2001                 }
2002                 kfree_skb(skb);
2003                 skb = skb_new;
2004         }
2005
2006         /* total number of fragments in the SKB */
2007         nr_frags = skb_shinfo(skb)->nr_frags;
2008
2009         /* calculate the required number of TxBDs for this skb */
2010         if (unlikely(do_tstamp))
2011                 nr_txbds = nr_frags + 2;
2012         else
2013                 nr_txbds = nr_frags + 1;
2014
2015         /* check if there is space to queue this packet */
2016         if (nr_txbds > tx_queue->num_txbdfree) {
2017                 /* no space, stop the queue */
2018                 netif_tx_stop_queue(txq);
2019                 dev->stats.tx_fifo_errors++;
2020                 return NETDEV_TX_BUSY;
2021         }
2022
2023         /* Update transmit stats */
2024         txq->tx_bytes += skb->len;
2025         txq->tx_packets ++;
2026
2027         txbdp = txbdp_start = tx_queue->cur_tx;
2028         lstatus = txbdp->lstatus;
2029
2030         /* Time stamp insertion requires one additional TxBD */
2031         if (unlikely(do_tstamp))
2032                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2033                                 tx_queue->tx_ring_size);
2034
2035         if (nr_frags == 0) {
2036                 if (unlikely(do_tstamp))
2037                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2038                                         TXBD_INTERRUPT);
2039                 else
2040                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2041         } else {
2042                 /* Place the fragment addresses and lengths into the TxBDs */
2043                 for (i = 0; i < nr_frags; i++) {
2044                         /* Point at the next BD, wrapping as needed */
2045                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2046
2047                         length = skb_shinfo(skb)->frags[i].size;
2048
2049                         lstatus = txbdp->lstatus | length |
2050                                 BD_LFLAG(TXBD_READY);
2051
2052                         /* Handle the last BD specially */
2053                         if (i == nr_frags - 1)
2054                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2055
2056                         bufaddr = dma_map_page(&priv->ofdev->dev,
2057                                         skb_shinfo(skb)->frags[i].page,
2058                                         skb_shinfo(skb)->frags[i].page_offset,
2059                                         length,
2060                                         DMA_TO_DEVICE);
2061
2062                         /* set the TxBD length and buffer pointer */
2063                         txbdp->bufPtr = bufaddr;
2064                         txbdp->lstatus = lstatus;
2065                 }
2066
2067                 lstatus = txbdp_start->lstatus;
2068         }
2069
2070         /* Set up checksumming */
2071         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2072                 fcb = gfar_add_fcb(skb);
2073                 lstatus |= BD_LFLAG(TXBD_TOE);
2074                 gfar_tx_checksum(skb, fcb);
2075         }
2076
2077         if (priv->vlgrp && vlan_tx_tag_present(skb)) {
2078                 if (unlikely(NULL == fcb)) {
2079                         fcb = gfar_add_fcb(skb);
2080                         lstatus |= BD_LFLAG(TXBD_TOE);
2081                 }
2082
2083                 gfar_tx_vlan(skb, fcb);
2084         }
2085
2086         /* Setup tx hardware time stamping if requested */
2087         if (unlikely(do_tstamp)) {
2088                 shtx->in_progress = 1;
2089                 if (fcb == NULL)
2090                         fcb = gfar_add_fcb(skb);
2091                 fcb->ptp = 1;
2092                 lstatus |= BD_LFLAG(TXBD_TOE);
2093         }
2094
2095         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2096                         skb_headlen(skb), DMA_TO_DEVICE);
2097
2098         /*
2099          * If time stamping is requested one additional TxBD must be set up. The
2100          * first TxBD points to the FCB and must have a data length of
2101          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2102          * the full frame length.
2103          */
2104         if (unlikely(do_tstamp)) {
2105                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2106                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2107                                 (skb_headlen(skb) - GMAC_FCB_LEN);
2108                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2109         } else {
2110                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2111         }
2112
2113         /*
2114          * We can work in parallel with gfar_clean_tx_ring(), except
2115          * when modifying num_txbdfree. Note that we didn't grab the lock
2116          * when we were reading the num_txbdfree and checking for available
2117          * space, that's because outside of this function it can only grow,
2118          * and once we've got needed space, it cannot suddenly disappear.
2119          *
2120          * The lock also protects us from gfar_error(), which can modify
2121          * regs->tstat and thus retrigger the transfers, which is why we
2122          * also must grab the lock before setting ready bit for the first
2123          * to be transmitted BD.
2124          */
2125         spin_lock_irqsave(&tx_queue->txlock, flags);
2126
2127         /*
2128          * The powerpc-specific eieio() is used, as wmb() has too strong
2129          * semantics (it requires synchronization between cacheable and
2130          * uncacheable mappings, which eieio doesn't provide and which we
2131          * don't need), thus requiring a more expensive sync instruction.  At
2132          * some point, the set of architecture-independent barrier functions
2133          * should be expanded to include weaker barriers.
2134          */
2135         eieio();
2136
2137         txbdp_start->lstatus = lstatus;
2138
2139         eieio(); /* force lstatus write before tx_skbuff */
2140
2141         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2142
2143         /* Update the current skb pointer to the next entry we will use
2144          * (wrapping if necessary) */
2145         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2146                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2147
2148         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2149
2150         /* reduce TxBD free count */
2151         tx_queue->num_txbdfree -= (nr_txbds);
2152
2153         /* If the next BD still needs to be cleaned up, then the bds
2154            are full.  We need to tell the kernel to stop sending us stuff. */
2155         if (!tx_queue->num_txbdfree) {
2156                 netif_tx_stop_queue(txq);
2157
2158                 dev->stats.tx_fifo_errors++;
2159         }
2160
2161         /* Tell the DMA to go go go */
2162         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2163
2164         /* Unlock priv */
2165         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2166
2167         return NETDEV_TX_OK;
2168 }
2169
2170 /* Stops the kernel queue, and halts the controller */
2171 static int gfar_close(struct net_device *dev)
2172 {
2173         struct gfar_private *priv = netdev_priv(dev);
2174
2175         disable_napi(priv);
2176
2177         cancel_work_sync(&priv->reset_task);
2178         stop_gfar(dev);
2179
2180         /* Disconnect from the PHY */
2181         phy_disconnect(priv->phydev);
2182         priv->phydev = NULL;
2183
2184         netif_tx_stop_all_queues(dev);
2185
2186         return 0;
2187 }
2188
2189 /* Changes the mac address if the controller is not running. */
2190 static int gfar_set_mac_address(struct net_device *dev)
2191 {
2192         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2193
2194         return 0;
2195 }
2196
2197
2198 /* Enables and disables VLAN insertion/extraction */
2199 static void gfar_vlan_rx_register(struct net_device *dev,
2200                 struct vlan_group *grp)
2201 {
2202         struct gfar_private *priv = netdev_priv(dev);
2203         struct gfar __iomem *regs = NULL;
2204         unsigned long flags;
2205         u32 tempval;
2206
2207         regs = priv->gfargrp[0].regs;
2208         local_irq_save(flags);
2209         lock_rx_qs(priv);
2210
2211         priv->vlgrp = grp;
2212
2213         if (grp) {
2214                 /* Enable VLAN tag insertion */
2215                 tempval = gfar_read(&regs->tctrl);
2216                 tempval |= TCTRL_VLINS;
2217
2218                 gfar_write(&regs->tctrl, tempval);
2219
2220                 /* Enable VLAN tag extraction */
2221                 tempval = gfar_read(&regs->rctrl);
2222                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2223                 gfar_write(&regs->rctrl, tempval);
2224         } else {
2225                 /* Disable VLAN tag insertion */
2226                 tempval = gfar_read(&regs->tctrl);
2227                 tempval &= ~TCTRL_VLINS;
2228                 gfar_write(&regs->tctrl, tempval);
2229
2230                 /* Disable VLAN tag extraction */
2231                 tempval = gfar_read(&regs->rctrl);
2232                 tempval &= ~RCTRL_VLEX;
2233                 /* If parse is no longer required, then disable parser */
2234                 if (tempval & RCTRL_REQ_PARSER)
2235                         tempval |= RCTRL_PRSDEP_INIT;
2236                 else
2237                         tempval &= ~RCTRL_PRSDEP_INIT;
2238                 gfar_write(&regs->rctrl, tempval);
2239         }
2240
2241         gfar_change_mtu(dev, dev->mtu);
2242
2243         unlock_rx_qs(priv);
2244         local_irq_restore(flags);
2245 }
2246
2247 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2248 {
2249         int tempsize, tempval;
2250         struct gfar_private *priv = netdev_priv(dev);
2251         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2252         int oldsize = priv->rx_buffer_size;
2253         int frame_size = new_mtu + ETH_HLEN;
2254
2255         if (priv->vlgrp)
2256                 frame_size += VLAN_HLEN;
2257
2258         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2259                 if (netif_msg_drv(priv))
2260                         printk(KERN_ERR "%s: Invalid MTU setting\n",
2261                                         dev->name);
2262                 return -EINVAL;
2263         }
2264
2265         if (gfar_uses_fcb(priv))
2266                 frame_size += GMAC_FCB_LEN;
2267
2268         frame_size += priv->padding;
2269
2270         tempsize =
2271             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2272             INCREMENTAL_BUFFER_SIZE;
2273
2274         /* Only stop and start the controller if it isn't already
2275          * stopped, and we changed something */
2276         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2277                 stop_gfar(dev);
2278
2279         priv->rx_buffer_size = tempsize;
2280
2281         dev->mtu = new_mtu;
2282
2283         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2284         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2285
2286         /* If the mtu is larger than the max size for standard
2287          * ethernet frames (ie, a jumbo frame), then set maccfg2
2288          * to allow huge frames, and to check the length */
2289         tempval = gfar_read(&regs->maccfg2);
2290
2291         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
2292                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2293         else
2294                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2295
2296         gfar_write(&regs->maccfg2, tempval);
2297
2298         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2299                 startup_gfar(dev);
2300
2301         return 0;
2302 }
2303
2304 /* gfar_reset_task gets scheduled when a packet has not been
2305  * transmitted after a set amount of time.
2306  * For now, assume that clearing out all the structures, and
2307  * starting over will fix the problem.
2308  */
2309 static void gfar_reset_task(struct work_struct *work)
2310 {
2311         struct gfar_private *priv = container_of(work, struct gfar_private,
2312                         reset_task);
2313         struct net_device *dev = priv->ndev;
2314
2315         if (dev->flags & IFF_UP) {
2316                 netif_tx_stop_all_queues(dev);
2317                 stop_gfar(dev);
2318                 startup_gfar(dev);
2319                 netif_tx_start_all_queues(dev);
2320         }
2321
2322         netif_tx_schedule_all(dev);
2323 }
2324
2325 static void gfar_timeout(struct net_device *dev)
2326 {
2327         struct gfar_private *priv = netdev_priv(dev);
2328
2329         dev->stats.tx_errors++;
2330         schedule_work(&priv->reset_task);
2331 }
2332
2333 /* Interrupt Handler for Transmit complete */
2334 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2335 {
2336         struct net_device *dev = tx_queue->dev;
2337         struct gfar_private *priv = netdev_priv(dev);
2338         struct gfar_priv_rx_q *rx_queue = NULL;
2339         struct txbd8 *bdp, *next = NULL;
2340         struct txbd8 *lbdp = NULL;
2341         struct txbd8 *base = tx_queue->tx_bd_base;
2342         struct sk_buff *skb;
2343         int skb_dirtytx;
2344         int tx_ring_size = tx_queue->tx_ring_size;
2345         int frags = 0, nr_txbds = 0;
2346         int i;
2347         int howmany = 0;
2348         u32 lstatus;
2349         size_t buflen;
2350         union skb_shared_tx *shtx;
2351
2352         rx_queue = priv->rx_queue[tx_queue->qindex];
2353         bdp = tx_queue->dirty_tx;
2354         skb_dirtytx = tx_queue->skb_dirtytx;
2355
2356         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2357                 unsigned long flags;
2358
2359                 frags = skb_shinfo(skb)->nr_frags;
2360
2361                 /*
2362                  * When time stamping, one additional TxBD must be freed.
2363                  * Also, we need to dma_unmap_single() the TxPAL.
2364                  */
2365                 shtx = skb_tx(skb);
2366                 if (unlikely(shtx->in_progress))
2367                         nr_txbds = frags + 2;
2368                 else
2369                         nr_txbds = frags + 1;
2370
2371                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2372
2373                 lstatus = lbdp->lstatus;
2374
2375                 /* Only clean completed frames */
2376                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2377                                 (lstatus & BD_LENGTH_MASK))
2378                         break;
2379
2380                 if (unlikely(shtx->in_progress)) {
2381                         next = next_txbd(bdp, base, tx_ring_size);
2382                         buflen = next->length + GMAC_FCB_LEN;
2383                 } else
2384                         buflen = bdp->length;
2385
2386                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2387                                 buflen, DMA_TO_DEVICE);
2388
2389                 if (unlikely(shtx->in_progress)) {
2390                         struct skb_shared_hwtstamps shhwtstamps;
2391                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2392                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2393                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2394                         skb_tstamp_tx(skb, &shhwtstamps);
2395                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2396                         bdp = next;
2397                 }
2398
2399                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2400                 bdp = next_txbd(bdp, base, tx_ring_size);
2401
2402                 for (i = 0; i < frags; i++) {
2403                         dma_unmap_page(&priv->ofdev->dev,
2404                                         bdp->bufPtr,
2405                                         bdp->length,
2406                                         DMA_TO_DEVICE);
2407                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2408                         bdp = next_txbd(bdp, base, tx_ring_size);
2409                 }
2410
2411                 /*
2412                  * If there's room in the queue (limit it to rx_buffer_size)
2413                  * we add this skb back into the pool, if it's the right size
2414                  */
2415                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2416                                 skb_recycle_check(skb, priv->rx_buffer_size +
2417                                         RXBUF_ALIGNMENT))
2418                         __skb_queue_head(&priv->rx_recycle, skb);
2419                 else
2420                         dev_kfree_skb_any(skb);
2421
2422                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2423
2424                 skb_dirtytx = (skb_dirtytx + 1) &
2425                         TX_RING_MOD_MASK(tx_ring_size);
2426
2427                 howmany++;
2428                 spin_lock_irqsave(&tx_queue->txlock, flags);
2429                 tx_queue->num_txbdfree += nr_txbds;
2430                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2431         }
2432
2433         /* If we freed a buffer, we can restart transmission, if necessary */
2434         if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2435                 netif_wake_subqueue(dev, tx_queue->qindex);
2436
2437         /* Update dirty indicators */
2438         tx_queue->skb_dirtytx = skb_dirtytx;
2439         tx_queue->dirty_tx = bdp;
2440
2441         return howmany;
2442 }
2443
2444 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2445 {
2446         unsigned long flags;
2447
2448         spin_lock_irqsave(&gfargrp->grplock, flags);
2449         if (napi_schedule_prep(&gfargrp->napi)) {
2450                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2451                 __napi_schedule(&gfargrp->napi);
2452         } else {
2453                 /*
2454                  * Clear IEVENT, so interrupts aren't called again
2455                  * because of the packets that have already arrived.
2456                  */
2457                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2458         }
2459         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2460
2461 }
2462
2463 /* Interrupt Handler for Transmit complete */
2464 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2465 {
2466         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2467         return IRQ_HANDLED;
2468 }
2469
2470 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2471                 struct sk_buff *skb)
2472 {
2473         struct net_device *dev = rx_queue->dev;
2474         struct gfar_private *priv = netdev_priv(dev);
2475         dma_addr_t buf;
2476
2477         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2478                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2479         gfar_init_rxbdp(rx_queue, bdp, buf);
2480 }
2481
2482
2483 struct sk_buff * gfar_new_skb(struct net_device *dev)
2484 {
2485         unsigned int alignamount;
2486         struct gfar_private *priv = netdev_priv(dev);
2487         struct sk_buff *skb = NULL;
2488
2489         skb = __skb_dequeue(&priv->rx_recycle);
2490         if (!skb)
2491                 skb = netdev_alloc_skb(dev,
2492                                 priv->rx_buffer_size + RXBUF_ALIGNMENT);
2493
2494         if (!skb)
2495                 return NULL;
2496
2497         alignamount = RXBUF_ALIGNMENT -
2498                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
2499
2500         /* We need the data buffer to be aligned properly.  We will reserve
2501          * as many bytes as needed to align the data properly
2502          */
2503         skb_reserve(skb, alignamount);
2504         GFAR_CB(skb)->alignamount = alignamount;
2505
2506         return skb;
2507 }
2508
2509 static inline void count_errors(unsigned short status, struct net_device *dev)
2510 {
2511         struct gfar_private *priv = netdev_priv(dev);
2512         struct net_device_stats *stats = &dev->stats;
2513         struct gfar_extra_stats *estats = &priv->extra_stats;
2514
2515         /* If the packet was truncated, none of the other errors
2516          * matter */
2517         if (status & RXBD_TRUNCATED) {
2518                 stats->rx_length_errors++;
2519
2520                 estats->rx_trunc++;
2521
2522                 return;
2523         }
2524         /* Count the errors, if there were any */
2525         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2526                 stats->rx_length_errors++;
2527
2528                 if (status & RXBD_LARGE)
2529                         estats->rx_large++;
2530                 else
2531                         estats->rx_short++;
2532         }
2533         if (status & RXBD_NONOCTET) {
2534                 stats->rx_frame_errors++;
2535                 estats->rx_nonoctet++;
2536         }
2537         if (status & RXBD_CRCERR) {
2538                 estats->rx_crcerr++;
2539                 stats->rx_crc_errors++;
2540         }
2541         if (status & RXBD_OVERRUN) {
2542                 estats->rx_overrun++;
2543                 stats->rx_crc_errors++;
2544         }
2545 }
2546
2547 irqreturn_t gfar_receive(int irq, void *grp_id)
2548 {
2549         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2550         return IRQ_HANDLED;
2551 }
2552
2553 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2554 {
2555         /* If valid headers were found, and valid sums
2556          * were verified, then we tell the kernel that no
2557          * checksumming is necessary.  Otherwise, it is */
2558         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2559                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2560         else
2561                 skb->ip_summed = CHECKSUM_NONE;
2562 }
2563
2564
2565 /* gfar_process_frame() -- handle one incoming packet if skb
2566  * isn't NULL.  */
2567 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2568                               int amount_pull)
2569 {
2570         struct gfar_private *priv = netdev_priv(dev);
2571         struct rxfcb *fcb = NULL;
2572
2573         int ret;
2574
2575         /* fcb is at the beginning if exists */
2576         fcb = (struct rxfcb *)skb->data;
2577
2578         /* Remove the FCB from the skb */
2579         /* Remove the padded bytes, if there are any */
2580         if (amount_pull) {
2581                 skb_record_rx_queue(skb, fcb->rq);
2582                 skb_pull(skb, amount_pull);
2583         }
2584
2585         /* Get receive timestamp from the skb */
2586         if (priv->hwts_rx_en) {
2587                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2588                 u64 *ns = (u64 *) skb->data;
2589                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2590                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2591         }
2592
2593         if (priv->padding)
2594                 skb_pull(skb, priv->padding);
2595
2596         if (priv->rx_csum_enable)
2597                 gfar_rx_checksum(skb, fcb);
2598
2599         /* Tell the skb what kind of packet this is */
2600         skb->protocol = eth_type_trans(skb, dev);
2601
2602         /* Send the packet up the stack */
2603         if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2604                 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2605         else
2606                 ret = netif_receive_skb(skb);
2607
2608         if (NET_RX_DROP == ret)
2609                 priv->extra_stats.kernel_dropped++;
2610
2611         return 0;
2612 }
2613
2614 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2615  *   until the budget/quota has been reached. Returns the number
2616  *   of frames handled
2617  */
2618 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2619 {
2620         struct net_device *dev = rx_queue->dev;
2621         struct rxbd8 *bdp, *base;
2622         struct sk_buff *skb;
2623         int pkt_len;
2624         int amount_pull;
2625         int howmany = 0;
2626         struct gfar_private *priv = netdev_priv(dev);
2627
2628         /* Get the first full descriptor */
2629         bdp = rx_queue->cur_rx;
2630         base = rx_queue->rx_bd_base;
2631
2632         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2633
2634         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2635                 struct sk_buff *newskb;
2636                 rmb();
2637
2638                 /* Add another skb for the future */
2639                 newskb = gfar_new_skb(dev);
2640
2641                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2642
2643                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2644                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2645
2646                 /* We drop the frame if we failed to allocate a new buffer */
2647                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2648                                  bdp->status & RXBD_ERR)) {
2649                         count_errors(bdp->status, dev);
2650
2651                         if (unlikely(!newskb))
2652                                 newskb = skb;
2653                         else if (skb) {
2654                                 /*
2655                                  * We need to un-reserve() the skb to what it
2656                                  * was before gfar_new_skb() re-aligned
2657                                  * it to an RXBUF_ALIGNMENT boundary
2658                                  * before we put the skb back on the
2659                                  * recycle list.
2660                                  */
2661                                 skb_reserve(skb, -GFAR_CB(skb)->alignamount);
2662                                 __skb_queue_head(&priv->rx_recycle, skb);
2663                         }
2664                 } else {
2665                         /* Increment the number of packets */
2666                         rx_queue->stats.rx_packets++;
2667                         howmany++;
2668
2669                         if (likely(skb)) {
2670                                 pkt_len = bdp->length - ETH_FCS_LEN;
2671                                 /* Remove the FCS from the packet length */
2672                                 skb_put(skb, pkt_len);
2673                                 rx_queue->stats.rx_bytes += pkt_len;
2674                                 skb_record_rx_queue(skb, rx_queue->qindex);
2675                                 gfar_process_frame(dev, skb, amount_pull);
2676
2677                         } else {
2678                                 if (netif_msg_rx_err(priv))
2679                                         printk(KERN_WARNING
2680                                                "%s: Missing skb!\n", dev->name);
2681                                 rx_queue->stats.rx_dropped++;
2682                                 priv->extra_stats.rx_skbmissing++;
2683                         }
2684
2685                 }
2686
2687                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2688
2689                 /* Setup the new bdp */
2690                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2691
2692                 /* Update to the next pointer */
2693                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2694
2695                 /* update to point at the next skb */
2696                 rx_queue->skb_currx =
2697                     (rx_queue->skb_currx + 1) &
2698                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2699         }
2700
2701         /* Update the current rxbd pointer to be the next one */
2702         rx_queue->cur_rx = bdp;
2703
2704         return howmany;
2705 }
2706
2707 static int gfar_poll(struct napi_struct *napi, int budget)
2708 {
2709         struct gfar_priv_grp *gfargrp = container_of(napi,
2710                         struct gfar_priv_grp, napi);
2711         struct gfar_private *priv = gfargrp->priv;
2712         struct gfar __iomem *regs = gfargrp->regs;
2713         struct gfar_priv_tx_q *tx_queue = NULL;
2714         struct gfar_priv_rx_q *rx_queue = NULL;
2715         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2716         int tx_cleaned = 0, i, left_over_budget = budget;
2717         unsigned long serviced_queues = 0;
2718         int num_queues = 0;
2719
2720         num_queues = gfargrp->num_rx_queues;
2721         budget_per_queue = budget/num_queues;
2722
2723         /* Clear IEVENT, so interrupts aren't called again
2724          * because of the packets that have already arrived */
2725         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2726
2727         while (num_queues && left_over_budget) {
2728
2729                 budget_per_queue = left_over_budget/num_queues;
2730                 left_over_budget = 0;
2731
2732                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2733                         if (test_bit(i, &serviced_queues))
2734                                 continue;
2735                         rx_queue = priv->rx_queue[i];
2736                         tx_queue = priv->tx_queue[rx_queue->qindex];
2737
2738                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2739                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2740                                                         budget_per_queue);
2741                         rx_cleaned += rx_cleaned_per_queue;
2742                         if(rx_cleaned_per_queue < budget_per_queue) {
2743                                 left_over_budget = left_over_budget +
2744                                         (budget_per_queue - rx_cleaned_per_queue);
2745                                 set_bit(i, &serviced_queues);
2746                                 num_queues--;
2747                         }
2748                 }
2749         }
2750
2751         if (tx_cleaned)
2752                 return budget;
2753
2754         if (rx_cleaned < budget) {
2755                 napi_complete(napi);
2756
2757                 /* Clear the halt bit in RSTAT */
2758                 gfar_write(&regs->rstat, gfargrp->rstat);
2759
2760                 gfar_write(&regs->imask, IMASK_DEFAULT);
2761
2762                 /* If we are coalescing interrupts, update the timer */
2763                 /* Otherwise, clear it */
2764                 gfar_configure_coalescing(priv,
2765                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2766         }
2767
2768         return rx_cleaned;
2769 }
2770
2771 #ifdef CONFIG_NET_POLL_CONTROLLER
2772 /*
2773  * Polling 'interrupt' - used by things like netconsole to send skbs
2774  * without having to re-enable interrupts. It's not called while
2775  * the interrupt routine is executing.
2776  */
2777 static void gfar_netpoll(struct net_device *dev)
2778 {
2779         struct gfar_private *priv = netdev_priv(dev);
2780         int i = 0;
2781
2782         /* If the device has multiple interrupts, run tx/rx */
2783         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2784                 for (i = 0; i < priv->num_grps; i++) {
2785                         disable_irq(priv->gfargrp[i].interruptTransmit);
2786                         disable_irq(priv->gfargrp[i].interruptReceive);
2787                         disable_irq(priv->gfargrp[i].interruptError);
2788                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2789                                                 &priv->gfargrp[i]);
2790                         enable_irq(priv->gfargrp[i].interruptError);
2791                         enable_irq(priv->gfargrp[i].interruptReceive);
2792                         enable_irq(priv->gfargrp[i].interruptTransmit);
2793                 }
2794         } else {
2795                 for (i = 0; i < priv->num_grps; i++) {
2796                         disable_irq(priv->gfargrp[i].interruptTransmit);
2797                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2798                                                 &priv->gfargrp[i]);
2799                         enable_irq(priv->gfargrp[i].interruptTransmit);
2800                 }
2801         }
2802 }
2803 #endif
2804
2805 /* The interrupt handler for devices with one interrupt */
2806 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2807 {
2808         struct gfar_priv_grp *gfargrp = grp_id;
2809
2810         /* Save ievent for future reference */
2811         u32 events = gfar_read(&gfargrp->regs->ievent);
2812
2813         /* Check for reception */
2814         if (events & IEVENT_RX_MASK)
2815                 gfar_receive(irq, grp_id);
2816
2817         /* Check for transmit completion */
2818         if (events & IEVENT_TX_MASK)
2819                 gfar_transmit(irq, grp_id);
2820
2821         /* Check for errors */
2822         if (events & IEVENT_ERR_MASK)
2823                 gfar_error(irq, grp_id);
2824
2825         return IRQ_HANDLED;
2826 }
2827
2828 /* Called every time the controller might need to be made
2829  * aware of new link state.  The PHY code conveys this
2830  * information through variables in the phydev structure, and this
2831  * function converts those variables into the appropriate
2832  * register values, and can bring down the device if needed.
2833  */
2834 static void adjust_link(struct net_device *dev)
2835 {
2836         struct gfar_private *priv = netdev_priv(dev);
2837         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2838         unsigned long flags;
2839         struct phy_device *phydev = priv->phydev;
2840         int new_state = 0;
2841
2842         local_irq_save(flags);
2843         lock_tx_qs(priv);
2844
2845         if (phydev->link) {
2846                 u32 tempval = gfar_read(&regs->maccfg2);
2847                 u32 ecntrl = gfar_read(&regs->ecntrl);
2848
2849                 /* Now we make sure that we can be in full duplex mode.
2850                  * If not, we operate in half-duplex mode. */
2851                 if (phydev->duplex != priv->oldduplex) {
2852                         new_state = 1;
2853                         if (!(phydev->duplex))
2854                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2855                         else
2856                                 tempval |= MACCFG2_FULL_DUPLEX;
2857
2858                         priv->oldduplex = phydev->duplex;
2859                 }
2860
2861                 if (phydev->speed != priv->oldspeed) {
2862                         new_state = 1;
2863                         switch (phydev->speed) {
2864                         case 1000:
2865                                 tempval =
2866                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2867
2868                                 ecntrl &= ~(ECNTRL_R100);
2869                                 break;
2870                         case 100:
2871                         case 10:
2872                                 tempval =
2873                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2874
2875                                 /* Reduced mode distinguishes
2876                                  * between 10 and 100 */
2877                                 if (phydev->speed == SPEED_100)
2878                                         ecntrl |= ECNTRL_R100;
2879                                 else
2880                                         ecntrl &= ~(ECNTRL_R100);
2881                                 break;
2882                         default:
2883                                 if (netif_msg_link(priv))
2884                                         printk(KERN_WARNING
2885                                                 "%s: Ack!  Speed (%d) is not 10/100/1000!\n",
2886                                                 dev->name, phydev->speed);
2887                                 break;
2888                         }
2889
2890                         priv->oldspeed = phydev->speed;
2891                 }
2892
2893                 gfar_write(&regs->maccfg2, tempval);
2894                 gfar_write(&regs->ecntrl, ecntrl);
2895
2896                 if (!priv->oldlink) {
2897                         new_state = 1;
2898                         priv->oldlink = 1;
2899                 }
2900         } else if (priv->oldlink) {
2901                 new_state = 1;
2902                 priv->oldlink = 0;
2903                 priv->oldspeed = 0;
2904                 priv->oldduplex = -1;
2905         }
2906
2907         if (new_state && netif_msg_link(priv))
2908                 phy_print_status(phydev);
2909         unlock_tx_qs(priv);
2910         local_irq_restore(flags);
2911 }
2912
2913 /* Update the hash table based on the current list of multicast
2914  * addresses we subscribe to.  Also, change the promiscuity of
2915  * the device based on the flags (this function is called
2916  * whenever dev->flags is changed */
2917 static void gfar_set_multi(struct net_device *dev)
2918 {
2919         struct netdev_hw_addr *ha;
2920         struct gfar_private *priv = netdev_priv(dev);
2921         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2922         u32 tempval;
2923
2924         if (dev->flags & IFF_PROMISC) {
2925                 /* Set RCTRL to PROM */
2926                 tempval = gfar_read(&regs->rctrl);
2927                 tempval |= RCTRL_PROM;
2928                 gfar_write(&regs->rctrl, tempval);
2929         } else {
2930                 /* Set RCTRL to not PROM */
2931                 tempval = gfar_read(&regs->rctrl);
2932                 tempval &= ~(RCTRL_PROM);
2933                 gfar_write(&regs->rctrl, tempval);
2934         }
2935
2936         if (dev->flags & IFF_ALLMULTI) {
2937                 /* Set the hash to rx all multicast frames */
2938                 gfar_write(&regs->igaddr0, 0xffffffff);
2939                 gfar_write(&regs->igaddr1, 0xffffffff);
2940                 gfar_write(&regs->igaddr2, 0xffffffff);
2941                 gfar_write(&regs->igaddr3, 0xffffffff);
2942                 gfar_write(&regs->igaddr4, 0xffffffff);
2943                 gfar_write(&regs->igaddr5, 0xffffffff);
2944                 gfar_write(&regs->igaddr6, 0xffffffff);
2945                 gfar_write(&regs->igaddr7, 0xffffffff);
2946                 gfar_write(&regs->gaddr0, 0xffffffff);
2947                 gfar_write(&regs->gaddr1, 0xffffffff);
2948                 gfar_write(&regs->gaddr2, 0xffffffff);
2949                 gfar_write(&regs->gaddr3, 0xffffffff);
2950                 gfar_write(&regs->gaddr4, 0xffffffff);
2951                 gfar_write(&regs->gaddr5, 0xffffffff);
2952                 gfar_write(&regs->gaddr6, 0xffffffff);
2953                 gfar_write(&regs->gaddr7, 0xffffffff);
2954         } else {
2955                 int em_num;
2956                 int idx;
2957
2958                 /* zero out the hash */
2959                 gfar_write(&regs->igaddr0, 0x0);
2960                 gfar_write(&regs->igaddr1, 0x0);
2961                 gfar_write(&regs->igaddr2, 0x0);
2962                 gfar_write(&regs->igaddr3, 0x0);
2963                 gfar_write(&regs->igaddr4, 0x0);
2964                 gfar_write(&regs->igaddr5, 0x0);
2965                 gfar_write(&regs->igaddr6, 0x0);
2966                 gfar_write(&regs->igaddr7, 0x0);
2967                 gfar_write(&regs->gaddr0, 0x0);
2968                 gfar_write(&regs->gaddr1, 0x0);
2969                 gfar_write(&regs->gaddr2, 0x0);
2970                 gfar_write(&regs->gaddr3, 0x0);
2971                 gfar_write(&regs->gaddr4, 0x0);
2972                 gfar_write(&regs->gaddr5, 0x0);
2973                 gfar_write(&regs->gaddr6, 0x0);
2974                 gfar_write(&regs->gaddr7, 0x0);
2975
2976                 /* If we have extended hash tables, we need to
2977                  * clear the exact match registers to prepare for
2978                  * setting them */
2979                 if (priv->extended_hash) {
2980                         em_num = GFAR_EM_NUM + 1;
2981                         gfar_clear_exact_match(dev);
2982                         idx = 1;
2983                 } else {
2984                         idx = 0;
2985                         em_num = 0;
2986                 }
2987
2988                 if (netdev_mc_empty(dev))
2989                         return;
2990
2991                 /* Parse the list, and set the appropriate bits */
2992                 netdev_for_each_mc_addr(ha, dev) {
2993                         if (idx < em_num) {
2994                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
2995                                 idx++;
2996                         } else
2997                                 gfar_set_hash_for_addr(dev, ha->addr);
2998                 }
2999         }
3000 }
3001
3002
3003 /* Clears each of the exact match registers to zero, so they
3004  * don't interfere with normal reception */
3005 static void gfar_clear_exact_match(struct net_device *dev)
3006 {
3007         int idx;
3008         u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
3009
3010         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3011                 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
3012 }
3013
3014 /* Set the appropriate hash bit for the given addr */
3015 /* The algorithm works like so:
3016  * 1) Take the Destination Address (ie the multicast address), and
3017  * do a CRC on it (little endian), and reverse the bits of the
3018  * result.
3019  * 2) Use the 8 most significant bits as a hash into a 256-entry
3020  * table.  The table is controlled through 8 32-bit registers:
3021  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3022  * gaddr7.  This means that the 3 most significant bits in the
3023  * hash index which gaddr register to use, and the 5 other bits
3024  * indicate which bit (assuming an IBM numbering scheme, which
3025  * for PowerPC (tm) is usually the case) in the register holds
3026  * the entry. */
3027 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3028 {
3029         u32 tempval;
3030         struct gfar_private *priv = netdev_priv(dev);
3031         u32 result = ether_crc(MAC_ADDR_LEN, addr);
3032         int width = priv->hash_width;
3033         u8 whichbit = (result >> (32 - width)) & 0x1f;
3034         u8 whichreg = result >> (32 - width + 5);
3035         u32 value = (1 << (31-whichbit));
3036
3037         tempval = gfar_read(priv->hash_regs[whichreg]);
3038         tempval |= value;
3039         gfar_write(priv->hash_regs[whichreg], tempval);
3040 }
3041
3042
3043 /* There are multiple MAC Address register pairs on some controllers
3044  * This function sets the numth pair to a given address
3045  */
3046 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
3047 {
3048         struct gfar_private *priv = netdev_priv(dev);
3049         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3050         int idx;
3051         char tmpbuf[MAC_ADDR_LEN];
3052         u32 tempval;
3053         u32 __iomem *macptr = &regs->macstnaddr1;
3054
3055         macptr += num*2;
3056
3057         /* Now copy it into the mac registers backwards, cuz */
3058         /* little endian is silly */
3059         for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3060                 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3061
3062         gfar_write(macptr, *((u32 *) (tmpbuf)));
3063
3064         tempval = *((u32 *) (tmpbuf + 4));
3065
3066         gfar_write(macptr+1, tempval);
3067 }
3068
3069 /* GFAR error interrupt handler */
3070 static irqreturn_t gfar_error(int irq, void *grp_id)
3071 {
3072         struct gfar_priv_grp *gfargrp = grp_id;
3073         struct gfar __iomem *regs = gfargrp->regs;
3074         struct gfar_private *priv= gfargrp->priv;
3075         struct net_device *dev = priv->ndev;
3076
3077         /* Save ievent for future reference */
3078         u32 events = gfar_read(&regs->ievent);
3079
3080         /* Clear IEVENT */
3081         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3082
3083         /* Magic Packet is not an error. */
3084         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3085             (events & IEVENT_MAG))
3086                 events &= ~IEVENT_MAG;
3087
3088         /* Hmm... */
3089         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3090                 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3091                        dev->name, events, gfar_read(&regs->imask));
3092
3093         /* Update the error counters */
3094         if (events & IEVENT_TXE) {
3095                 dev->stats.tx_errors++;
3096
3097                 if (events & IEVENT_LC)
3098                         dev->stats.tx_window_errors++;
3099                 if (events & IEVENT_CRL)
3100                         dev->stats.tx_aborted_errors++;
3101                 if (events & IEVENT_XFUN) {
3102                         unsigned long flags;
3103
3104                         if (netif_msg_tx_err(priv))
3105                                 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3106                                        "packet dropped.\n", dev->name);
3107                         dev->stats.tx_dropped++;
3108                         priv->extra_stats.tx_underrun++;
3109
3110                         local_irq_save(flags);
3111                         lock_tx_qs(priv);
3112
3113                         /* Reactivate the Tx Queues */
3114                         gfar_write(&regs->tstat, gfargrp->tstat);
3115
3116                         unlock_tx_qs(priv);
3117                         local_irq_restore(flags);
3118                 }
3119                 if (netif_msg_tx_err(priv))
3120                         printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
3121         }
3122         if (events & IEVENT_BSY) {
3123                 dev->stats.rx_errors++;
3124                 priv->extra_stats.rx_bsy++;
3125
3126                 gfar_receive(irq, grp_id);
3127
3128                 if (netif_msg_rx_err(priv))
3129                         printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
3130                                dev->name, gfar_read(&regs->rstat));
3131         }
3132         if (events & IEVENT_BABR) {
3133                 dev->stats.rx_errors++;
3134                 priv->extra_stats.rx_babr++;
3135
3136                 if (netif_msg_rx_err(priv))
3137                         printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
3138         }
3139         if (events & IEVENT_EBERR) {
3140                 priv->extra_stats.eberr++;
3141                 if (netif_msg_rx_err(priv))
3142                         printk(KERN_DEBUG "%s: bus error\n", dev->name);
3143         }
3144         if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
3145                 printk(KERN_DEBUG "%s: control frame\n", dev->name);
3146
3147         if (events & IEVENT_BABT) {
3148                 priv->extra_stats.tx_babt++;
3149                 if (netif_msg_tx_err(priv))
3150                         printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
3151         }
3152         return IRQ_HANDLED;
3153 }
3154
3155 static struct of_device_id gfar_match[] =
3156 {
3157         {
3158                 .type = "network",
3159                 .compatible = "gianfar",
3160         },
3161         {
3162                 .compatible = "fsl,etsec2",
3163         },
3164         {},
3165 };
3166 MODULE_DEVICE_TABLE(of, gfar_match);
3167
3168 /* Structure for a device driver */
3169 static struct of_platform_driver gfar_driver = {
3170         .driver = {
3171                 .name = "fsl-gianfar",
3172                 .owner = THIS_MODULE,
3173                 .pm = GFAR_PM_OPS,
3174                 .of_match_table = gfar_match,
3175         },
3176         .probe = gfar_probe,
3177         .remove = gfar_remove,
3178 };
3179
3180 static int __init gfar_init(void)
3181 {
3182         return of_register_platform_driver(&gfar_driver);
3183 }
3184
3185 static void __exit gfar_exit(void)
3186 {
3187         of_unregister_platform_driver(&gfar_driver);
3188 }
3189
3190 module_init(gfar_init);
3191 module_exit(gfar_exit);
3192