drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,5,6 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Changelog:
  33  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  34  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  35  *                         Check all PCI BARs for the register window.
  36  *                         udelay added to mii_rw.
  37  *      0.03: 06 Oct 2003: Initialize dev->irq.
  38  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  39  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  40  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  41  *                         irq mask updated
  42  *      0.07: 14 Oct 2003: Further irq mask updates.
  43  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  44  *                         added into irq handler, NULL check for drain_ring.
  45  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  46  *                         requested interrupt sources.
  47  *      0.10: 20 Oct 2003: First cleanup for release.
  48  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  49  *                         MAC Address init fix, set_multicast cleanup.
  50  *      0.12: 23 Oct 2003: Cleanups for release.
  51  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  52  *                         Set link speed correctly. start rx before starting
  53  *                         tx (nv_start_rx sets the link speed).
  54  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  55  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  56  *                         open.
  57  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  58  *                         increased to 1628 bytes.
  59  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  60  *                         the tx length.
  61  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  62  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  63  *                         addresses, really stop rx if already running
  64  *                         in nv_start_rx, clean up a bit.
  65  *      0.20: 07 Dec 2003: alloc fixes
  66  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  67  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  68  *                         on close.
  69  *      0.23: 26 Jan 2004: various small cleanups
  70  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  71  *      0.25: 09 Mar 2004: wol support
  72  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  73  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  74  *                         added CK804/MCP04 device IDs, code fixes
  75  *                         for registers, link status and other minor fixes.
  76  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  77  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  78  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  79  *                         into nv_close, otherwise reenabling for wol can
  80  *                         cause DMA to kfree'd memory.
  81  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  82  *                         capabilities.
  83  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  84  *      0.33: 16 May 2005: Support for MCP51 added.
  85  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  86  *      0.35: 26 Jun 2005: Support for MCP55 added.
  87  *      0.36: 28 Jun 2005: Add jumbo frame support.
  88  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  89  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  90  *                         per-packet flags.
  91  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  92  *      0.40: 19 Jul 2005: Add support for mac address change.
  93  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  94  *                         of nv_remove
  95  *      0.42: 06 Aug 2005: Fix lack of link speed initialization
  96  *                         in the second (and later) nv_open call
  97  *      0.43: 10 Aug 2005: Add support for tx checksum.
  98  *      0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
  99  *      0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
 100  *      0.46: 20 Oct 2005: Add irq optimization modes.
 101  *      0.47: 26 Oct 2005: Add phyaddr 0 in phy scan.
 102  *      0.48: 24 Dec 2005: Disable TSO, bugfix for pci_map_single
 103  *      0.49: 10 Dec 2005: Fix tso for large buffers.
 104  *      0.50: 20 Jan 2006: Add 8021pq tagging support.
 105  *      0.51: 20 Jan 2006: Add 64bit consistent memory allocation for rings.
 106  *      0.52: 20 Jan 2006: Add MSI/MSIX support.
 107  *      0.53: 19 Mar 2006: Fix init from low power mode and add hw reset.
 108  *      0.54: 21 Mar 2006: Fix spin locks for multi irqs and cleanup.
 109  *      0.55: 22 Mar 2006: Add flow control (pause frame).
 110  *      0.56: 22 Mar 2006: Additional ethtool config and moduleparam support.
 111  *      0.57: 14 May 2006: Mac address set in probe/remove and order corrections.
 112  *      0.58: 30 Oct 2006: Added support for sideband management unit.
 113  *      0.59: 30 Oct 2006: Added support for recoverable error.
 114  *      0.60: 20 Jan 2007: Code optimizations for rings, rx & tx data paths, and stats.
 115  *
 116  * Known bugs:
 117  * We suspect that on some hardware no TX done interrupts are generated.
 118  * This means recovery from netif_stop_queue only happens if the hw timer
 119  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 120  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 121  * If your hardware reliably generates tx done interrupts, then you can remove
 122  * DEV_NEED_TIMERIRQ from the driver_data flags.
 123  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 124  * superfluous timer interrupts from the nic.
 125  */
 126 #ifdef CONFIG_FORCEDETH_NAPI
 127 #define DRIVERNAPI "-NAPI"
 128 #else
 129 #define DRIVERNAPI
 130 #endif
 131 #define FORCEDETH_VERSION               "0.61"
 132 #define DRV_NAME                        "forcedeth"
 133
 134 #include <linux/module.h>
 135 #include <linux/types.h>
 136 #include <linux/pci.h>
 137 #include <linux/interrupt.h>
 138 #include <linux/netdevice.h>
 139 #include <linux/etherdevice.h>
 140 #include <linux/delay.h>
 141 #include <linux/spinlock.h>
 142 #include <linux/ethtool.h>
 143 #include <linux/timer.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/mii.h>
 146 #include <linux/random.h>
 147 #include <linux/init.h>
 148 #include <linux/if_vlan.h>
 149 #include <linux/dma-mapping.h>
 150
 151 #include <asm/irq.h>
 152 #include <asm/io.h>
 153 #include <asm/uaccess.h>
 154 #include <asm/system.h>
 155
 156 #if 0
 157 #define dprintk                 printk
 158 #else
 159 #define dprintk(x...)           do { } while (0)
 160 #endif
 161
 162 #define TX_WORK_PER_LOOP  64
 163 #define RX_WORK_PER_LOOP  64
 164
 165 /*
 166  * Hardware access:
 167  */
 168
 169 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 170 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 171 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 172 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 173 #define DEV_HAS_CHECKSUM        0x0010  /* device supports tx and rx checksum offloads */
 174 #define DEV_HAS_VLAN            0x0020  /* device supports vlan tagging and striping */
 175 #define DEV_HAS_MSI             0x0040  /* device supports MSI */
 176 #define DEV_HAS_MSI_X           0x0080  /* device supports MSI-X */
 177 #define DEV_HAS_POWER_CNTRL     0x0100  /* device supports power savings */
 178 #define DEV_HAS_PAUSEFRAME_TX   0x0200  /* device supports tx pause frames */
 179 #define DEV_HAS_STATISTICS_V1   0x0400  /* device supports hw statistics version 1 */
 180 #define DEV_HAS_STATISTICS_V2   0x0800  /* device supports hw statistics version 2 */
 181 #define DEV_HAS_TEST_EXTENDED   0x1000  /* device supports extended diagnostic test */
 182 #define DEV_HAS_MGMT_UNIT       0x2000  /* device supports management unit */
 183 #define DEV_HAS_CORRECT_MACADDR 0x4000  /* device supports correct mac address order */
 184
 185 enum {
 186         NvRegIrqStatus = 0x000,
 187 #define NVREG_IRQSTAT_MIIEVENT  0x040
 188 #define NVREG_IRQSTAT_MASK              0x81ff
 189         NvRegIrqMask = 0x004,
 190 #define NVREG_IRQ_RX_ERROR              0x0001
 191 #define NVREG_IRQ_RX                    0x0002
 192 #define NVREG_IRQ_RX_NOBUF              0x0004
 193 #define NVREG_IRQ_TX_ERR                0x0008
 194 #define NVREG_IRQ_TX_OK                 0x0010
 195 #define NVREG_IRQ_TIMER                 0x0020
 196 #define NVREG_IRQ_LINK                  0x0040
 197 #define NVREG_IRQ_RX_FORCED             0x0080
 198 #define NVREG_IRQ_TX_FORCED             0x0100
 199 #define NVREG_IRQ_RECOVER_ERROR         0x8000
 200 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 201 #define NVREG_IRQMASK_CPU               0x0060
 202 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 203 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 204 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 205
 206 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 207                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \
 208                                         NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR))
 209
 210         NvRegUnknownSetupReg6 = 0x008,
 211 #define NVREG_UNKSETUP6_VAL             3
 212
 213 /*
 214  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 215  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 216  */
 217         NvRegPollingInterval = 0x00c,
 218 #define NVREG_POLL_DEFAULT_THROUGHPUT   970 /* backup tx cleanup if loop max reached */
 219 #define NVREG_POLL_DEFAULT_CPU  13
 220         NvRegMSIMap0 = 0x020,
 221         NvRegMSIMap1 = 0x024,
 222         NvRegMSIIrqMask = 0x030,
 223 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 224         NvRegMisc1 = 0x080,
 225 #define NVREG_MISC1_PAUSE_TX    0x01
 226 #define NVREG_MISC1_HD          0x02
 227 #define NVREG_MISC1_FORCE       0x3b0f3c
 228
 229         NvRegMacReset = 0x3c,
 230 #define NVREG_MAC_RESET_ASSERT  0x0F3
 231         NvRegTransmitterControl = 0x084,
 232 #define NVREG_XMITCTL_START     0x01
 233 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 234 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 235 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 236 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 237 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 238 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 239 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 240 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 241 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 242 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 243         NvRegTransmitterStatus = 0x088,
 244 #define NVREG_XMITSTAT_BUSY     0x01
 245
 246         NvRegPacketFilterFlags = 0x8c,
 247 #define NVREG_PFF_PAUSE_RX      0x08
 248 #define NVREG_PFF_ALWAYS        0x7F0000
 249 #define NVREG_PFF_PROMISC       0x80
 250 #define NVREG_PFF_MYADDR        0x20
 251 #define NVREG_PFF_LOOPBACK      0x10
 252
 253         NvRegOffloadConfig = 0x90,
 254 #define NVREG_OFFLOAD_HOMEPHY   0x601
 255 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 256         NvRegReceiverControl = 0x094,
 257 #define NVREG_RCVCTL_START      0x01
 258 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 259         NvRegReceiverStatus = 0x98,
 260 #define NVREG_RCVSTAT_BUSY      0x01
 261
 262         NvRegRandomSeed = 0x9c,
 263 #define NVREG_RNDSEED_MASK      0x00ff
 264 #define NVREG_RNDSEED_FORCE     0x7f00
 265 #define NVREG_RNDSEED_FORCE2    0x2d00
 266 #define NVREG_RNDSEED_FORCE3    0x7400
 267
 268         NvRegTxDeferral = 0xA0,
 269 #define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
 270 #define NVREG_TX_DEFERRAL_RGMII_10_100  0x16070f
 271 #define NVREG_TX_DEFERRAL_RGMII_1000    0x14050f
 272         NvRegRxDeferral = 0xA4,
 273 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 274         NvRegMacAddrA = 0xA8,
 275         NvRegMacAddrB = 0xAC,
 276         NvRegMulticastAddrA = 0xB0,
 277 #define NVREG_MCASTADDRA_FORCE  0x01
 278         NvRegMulticastAddrB = 0xB4,
 279         NvRegMulticastMaskA = 0xB8,
 280         NvRegMulticastMaskB = 0xBC,
 281
 282         NvRegPhyInterface = 0xC0,
 283 #define PHY_RGMII               0x10000000
 284
 285         NvRegTxRingPhysAddr = 0x100,
 286         NvRegRxRingPhysAddr = 0x104,
 287         NvRegRingSizes = 0x108,
 288 #define NVREG_RINGSZ_TXSHIFT 0
 289 #define NVREG_RINGSZ_RXSHIFT 16
 290         NvRegTransmitPoll = 0x10c,
 291 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 292         NvRegLinkSpeed = 0x110,
 293 #define NVREG_LINKSPEED_FORCE 0x10000
 294 #define NVREG_LINKSPEED_10      1000
 295 #define NVREG_LINKSPEED_100     100
 296 #define NVREG_LINKSPEED_1000    50
 297 #define NVREG_LINKSPEED_MASK    (0xFFF)
 298         NvRegUnknownSetupReg5 = 0x130,
 299 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 300         NvRegTxWatermark = 0x13c,
 301 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 302 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 303 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 304         NvRegTxRxControl = 0x144,
 305 #define NVREG_TXRXCTL_KICK      0x0001
 306 #define NVREG_TXRXCTL_BIT1      0x0002
 307 #define NVREG_TXRXCTL_BIT2      0x0004
 308 #define NVREG_TXRXCTL_IDLE      0x0008
 309 #define NVREG_TXRXCTL_RESET     0x0010
 310 #define NVREG_TXRXCTL_RXCHECK   0x0400
 311 #define NVREG_TXRXCTL_DESC_1    0
 312 #define NVREG_TXRXCTL_DESC_2    0x002100
 313 #define NVREG_TXRXCTL_DESC_3    0xc02200
 314 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 315 #define NVREG_TXRXCTL_VLANINS   0x00080
 316         NvRegTxRingPhysAddrHigh = 0x148,
 317         NvRegRxRingPhysAddrHigh = 0x14C,
 318         NvRegTxPauseFrame = 0x170,
 319 #define NVREG_TX_PAUSEFRAME_DISABLE     0x1ff0080
 320 #define NVREG_TX_PAUSEFRAME_ENABLE      0x0c00030
 321         NvRegMIIStatus = 0x180,
 322 #define NVREG_MIISTAT_ERROR             0x0001
 323 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 324 #define NVREG_MIISTAT_MASK              0x000f
 325 #define NVREG_MIISTAT_MASK2             0x000f
 326         NvRegMIIMask = 0x184,
 327 #define NVREG_MII_LINKCHANGE            0x0008
 328
 329         NvRegAdapterControl = 0x188,
 330 #define NVREG_ADAPTCTL_START    0x02
 331 #define NVREG_ADAPTCTL_LINKUP   0x04
 332 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 333 #define NVREG_ADAPTCTL_RUNNING  0x100000
 334 #define NVREG_ADAPTCTL_PHYSHIFT 24
 335         NvRegMIISpeed = 0x18c,
 336 #define NVREG_MIISPEED_BIT8     (1<<8)
 337 #define NVREG_MIIDELAY  5
 338         NvRegMIIControl = 0x190,
 339 #define NVREG_MIICTL_INUSE      0x08000
 340 #define NVREG_MIICTL_WRITE      0x00400
 341 #define NVREG_MIICTL_ADDRSHIFT  5
 342         NvRegMIIData = 0x194,
 343         NvRegWakeUpFlags = 0x200,
 344 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 345 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 346 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 347 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 348 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 349 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 350 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 351 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 352 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 353 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 354 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 355
 356         NvRegPatternCRC = 0x204,
 357         NvRegPatternMask = 0x208,
 358         NvRegPowerCap = 0x268,
 359 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 360 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 361 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 362         NvRegPowerState = 0x26c,
 363 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 364 #define NVREG_POWERSTATE_VALID          0x0100
 365 #define NVREG_POWERSTATE_MASK           0x0003
 366 #define NVREG_POWERSTATE_D0             0x0000
 367 #define NVREG_POWERSTATE_D1             0x0001
 368 #define NVREG_POWERSTATE_D2             0x0002
 369 #define NVREG_POWERSTATE_D3             0x0003
 370         NvRegTxCnt = 0x280,
 371         NvRegTxZeroReXmt = 0x284,
 372         NvRegTxOneReXmt = 0x288,
 373         NvRegTxManyReXmt = 0x28c,
 374         NvRegTxLateCol = 0x290,
 375         NvRegTxUnderflow = 0x294,
 376         NvRegTxLossCarrier = 0x298,
 377         NvRegTxExcessDef = 0x29c,
 378         NvRegTxRetryErr = 0x2a0,
 379         NvRegRxFrameErr = 0x2a4,
 380         NvRegRxExtraByte = 0x2a8,
 381         NvRegRxLateCol = 0x2ac,
 382         NvRegRxRunt = 0x2b0,
 383         NvRegRxFrameTooLong = 0x2b4,
 384         NvRegRxOverflow = 0x2b8,
 385         NvRegRxFCSErr = 0x2bc,
 386         NvRegRxFrameAlignErr = 0x2c0,
 387         NvRegRxLenErr = 0x2c4,
 388         NvRegRxUnicast = 0x2c8,
 389         NvRegRxMulticast = 0x2cc,
 390         NvRegRxBroadcast = 0x2d0,
 391         NvRegTxDef = 0x2d4,
 392         NvRegTxFrame = 0x2d8,
 393         NvRegRxCnt = 0x2dc,
 394         NvRegTxPause = 0x2e0,
 395         NvRegRxPause = 0x2e4,
 396         NvRegRxDropFrame = 0x2e8,
 397         NvRegVlanControl = 0x300,
 398 #define NVREG_VLANCONTROL_ENABLE        0x2000
 399         NvRegMSIXMap0 = 0x3e0,
 400         NvRegMSIXMap1 = 0x3e4,
 401         NvRegMSIXIrqStatus = 0x3f0,
 402
 403         NvRegPowerState2 = 0x600,
 404 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F11
 405 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 406 };
 407
 408 /* Big endian: should work, but is untested */
 409 struct ring_desc {
 410         __le32 buf;
 411         __le32 flaglen;
 412 };
 413
 414 struct ring_desc_ex {
 415         __le32 bufhigh;
 416         __le32 buflow;
 417         __le32 txvlan;
 418         __le32 flaglen;
 419 };
 420
 421 union ring_type {
 422         struct ring_desc* orig;
 423         struct ring_desc_ex* ex;
 424 };
 425
 426 #define FLAG_MASK_V1 0xffff0000
 427 #define FLAG_MASK_V2 0xffffc000
 428 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 429 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 430
 431 #define NV_TX_LASTPACKET        (1<<16)
 432 #define NV_TX_RETRYERROR        (1<<19)
 433 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 434 #define NV_TX_DEFERRED          (1<<26)
 435 #define NV_TX_CARRIERLOST       (1<<27)
 436 #define NV_TX_LATECOLLISION     (1<<28)
 437 #define NV_TX_UNDERFLOW         (1<<29)
 438 #define NV_TX_ERROR             (1<<30)
 439 #define NV_TX_VALID             (1<<31)
 440
 441 #define NV_TX2_LASTPACKET       (1<<29)
 442 #define NV_TX2_RETRYERROR       (1<<18)
 443 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 444 #define NV_TX2_DEFERRED         (1<<25)
 445 #define NV_TX2_CARRIERLOST      (1<<26)
 446 #define NV_TX2_LATECOLLISION    (1<<27)
 447 #define NV_TX2_UNDERFLOW        (1<<28)
 448 /* error and valid are the same for both */
 449 #define NV_TX2_ERROR            (1<<30)
 450 #define NV_TX2_VALID            (1<<31)
 451 #define NV_TX2_TSO              (1<<28)
 452 #define NV_TX2_TSO_SHIFT        14
 453 #define NV_TX2_TSO_MAX_SHIFT    14
 454 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 455 #define NV_TX2_CHECKSUM_L3      (1<<27)
 456 #define NV_TX2_CHECKSUM_L4      (1<<26)
 457
 458 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 459
 460 #define NV_RX_DESCRIPTORVALID   (1<<16)
 461 #define NV_RX_MISSEDFRAME       (1<<17)
 462 #define NV_RX_SUBSTRACT1        (1<<18)
 463 #define NV_RX_ERROR1            (1<<23)
 464 #define NV_RX_ERROR2            (1<<24)
 465 #define NV_RX_ERROR3            (1<<25)
 466 #define NV_RX_ERROR4            (1<<26)
 467 #define NV_RX_CRCERR            (1<<27)
 468 #define NV_RX_OVERFLOW          (1<<28)
 469 #define NV_RX_FRAMINGERR        (1<<29)
 470 #define NV_RX_ERROR             (1<<30)
 471 #define NV_RX_AVAIL             (1<<31)
 472
 473 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 474 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 475 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 476 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 477 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 478 #define NV_RX2_SUBSTRACT1       (1<<25)
 479 #define NV_RX2_ERROR1           (1<<18)
 480 #define NV_RX2_ERROR2           (1<<19)
 481 #define NV_RX2_ERROR3           (1<<20)
 482 #define NV_RX2_ERROR4           (1<<21)
 483 #define NV_RX2_CRCERR           (1<<22)
 484 #define NV_RX2_OVERFLOW         (1<<23)
 485 #define NV_RX2_FRAMINGERR       (1<<24)
 486 /* error and avail are the same for both */
 487 #define NV_RX2_ERROR            (1<<30)
 488 #define NV_RX2_AVAIL            (1<<31)
 489
 490 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 491 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 492
 493 /* Miscelaneous hardware related defines: */
 494 #define NV_PCI_REGSZ_VER1       0x270
 495 #define NV_PCI_REGSZ_VER2       0x2d4
 496 #define NV_PCI_REGSZ_VER3       0x604
 497
 498 /* various timeout delays: all in usec */
 499 #define NV_TXRX_RESET_DELAY     4
 500 #define NV_TXSTOP_DELAY1        10
 501 #define NV_TXSTOP_DELAY1MAX     500000
 502 #define NV_TXSTOP_DELAY2        100
 503 #define NV_RXSTOP_DELAY1        10
 504 #define NV_RXSTOP_DELAY1MAX     500000
 505 #define NV_RXSTOP_DELAY2        100
 506 #define NV_SETUP5_DELAY         5
 507 #define NV_SETUP5_DELAYMAX      50000
 508 #define NV_POWERUP_DELAY        5
 509 #define NV_POWERUP_DELAYMAX     5000
 510 #define NV_MIIBUSY_DELAY        50
 511 #define NV_MIIPHY_DELAY 10
 512 #define NV_MIIPHY_DELAYMAX      10000
 513 #define NV_MAC_RESET_DELAY      64
 514
 515 #define NV_WAKEUPPATTERNS       5
 516 #define NV_WAKEUPMASKENTRIES    4
 517
 518 /* General driver defaults */
 519 #define NV_WATCHDOG_TIMEO       (5*HZ)
 520
 521 #define RX_RING_DEFAULT         128
 522 #define TX_RING_DEFAULT         256
 523 #define RX_RING_MIN             128
 524 #define TX_RING_MIN             64
 525 #define RING_MAX_DESC_VER_1     1024
 526 #define RING_MAX_DESC_VER_2_3   16384
 527
 528 /* rx/tx mac addr + type + vlan + align + slack*/
 529 #define NV_RX_HEADERS           (64)
 530 /* even more slack. */
 531 #define NV_RX_ALLOC_PAD         (64)
 532
 533 /* maximum mtu size */
 534 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 535 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 536
 537 #define OOM_REFILL      (1+HZ/20)
 538 #define POLL_WAIT       (1+HZ/100)
 539 #define LINK_TIMEOUT    (3*HZ)
 540 #define STATS_INTERVAL  (10*HZ)
 541
 542 /*
 543  * desc_ver values:
 544  * The nic supports three different descriptor types:
 545  * - DESC_VER_1: Original
 546  * - DESC_VER_2: support for jumbo frames.
 547  * - DESC_VER_3: 64-bit format.
 548  */
 549 #define DESC_VER_1      1
 550 #define DESC_VER_2      2
 551 #define DESC_VER_3      3
 552
 553 /* PHY defines */
 554 #define PHY_OUI_MARVELL 0x5043
 555 #define PHY_OUI_CICADA  0x03f1
 556 #define PHY_OUI_VITESSE 0x01c1
 557 #define PHY_OUI_REALTEK 0x0732
 558 #define PHYID1_OUI_MASK 0x03ff
 559 #define PHYID1_OUI_SHFT 6
 560 #define PHYID2_OUI_MASK 0xfc00
 561 #define PHYID2_OUI_SHFT 10
 562 #define PHYID2_MODEL_MASK               0x03f0
 563 #define PHY_MODEL_MARVELL_E3016         0x220
 564 #define PHY_MARVELL_E3016_INITMASK      0x0300
 565 #define PHY_CICADA_INIT1        0x0f000
 566 #define PHY_CICADA_INIT2        0x0e00
 567 #define PHY_CICADA_INIT3        0x01000
 568 #define PHY_CICADA_INIT4        0x0200
 569 #define PHY_CICADA_INIT5        0x0004
 570 #define PHY_CICADA_INIT6        0x02000
 571 #define PHY_VITESSE_INIT_REG1   0x1f
 572 #define PHY_VITESSE_INIT_REG2   0x10
 573 #define PHY_VITESSE_INIT_REG3   0x11
 574 #define PHY_VITESSE_INIT_REG4   0x12
 575 #define PHY_VITESSE_INIT_MSK1   0xc
 576 #define PHY_VITESSE_INIT_MSK2   0x0180
 577 #define PHY_VITESSE_INIT1       0x52b5
 578 #define PHY_VITESSE_INIT2       0xaf8a
 579 #define PHY_VITESSE_INIT3       0x8
 580 #define PHY_VITESSE_INIT4       0x8f8a
 581 #define PHY_VITESSE_INIT5       0xaf86
 582 #define PHY_VITESSE_INIT6       0x8f86
 583 #define PHY_VITESSE_INIT7       0xaf82
 584 #define PHY_VITESSE_INIT8       0x0100
 585 #define PHY_VITESSE_INIT9       0x8f82
 586 #define PHY_VITESSE_INIT10      0x0
 587 #define PHY_REALTEK_INIT_REG1   0x1f
 588 #define PHY_REALTEK_INIT_REG2   0x19
 589 #define PHY_REALTEK_INIT_REG3   0x13
 590 #define PHY_REALTEK_INIT1       0x0000
 591 #define PHY_REALTEK_INIT2       0x8e00
 592 #define PHY_REALTEK_INIT3       0x0001
 593 #define PHY_REALTEK_INIT4       0xad17
 594
 595 #define PHY_GIGABIT     0x0100
 596
 597 #define PHY_TIMEOUT     0x1
 598 #define PHY_ERROR       0x2
 599
 600 #define PHY_100 0x1
 601 #define PHY_1000        0x2
 602 #define PHY_HALF        0x100
 603
 604 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 605 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 606 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 607 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 608 #define NV_PAUSEFRAME_RX_REQ     0x0010
 609 #define NV_PAUSEFRAME_TX_REQ     0x0020
 610 #define NV_PAUSEFRAME_AUTONEG    0x0040
 611
 612 /* MSI/MSI-X defines */
 613 #define NV_MSI_X_MAX_VECTORS  8
 614 #define NV_MSI_X_VECTORS_MASK 0x000f
 615 #define NV_MSI_CAPABLE        0x0010
 616 #define NV_MSI_X_CAPABLE      0x0020
 617 #define NV_MSI_ENABLED        0x0040
 618 #define NV_MSI_X_ENABLED      0x0080
 619
 620 #define NV_MSI_X_VECTOR_ALL   0x0
 621 #define NV_MSI_X_VECTOR_RX    0x0
 622 #define NV_MSI_X_VECTOR_TX    0x1
 623 #define NV_MSI_X_VECTOR_OTHER 0x2
 624
 625 /* statistics */
 626 struct nv_ethtool_str {
 627         char name[ETH_GSTRING_LEN];
 628 };
 629
 630 static const struct nv_ethtool_str nv_estats_str[] = {
 631         { "tx_bytes" },
 632         { "tx_zero_rexmt" },
 633         { "tx_one_rexmt" },
 634         { "tx_many_rexmt" },
 635         { "tx_late_collision" },
 636         { "tx_fifo_errors" },
 637         { "tx_carrier_errors" },
 638         { "tx_excess_deferral" },
 639         { "tx_retry_error" },
 640         { "rx_frame_error" },
 641         { "rx_extra_byte" },
 642         { "rx_late_collision" },
 643         { "rx_runt" },
 644         { "rx_frame_too_long" },
 645         { "rx_over_errors" },
 646         { "rx_crc_errors" },
 647         { "rx_frame_align_error" },
 648         { "rx_length_error" },
 649         { "rx_unicast" },
 650         { "rx_multicast" },
 651         { "rx_broadcast" },
 652         { "rx_packets" },
 653         { "rx_errors_total" },
 654         { "tx_errors_total" },
 655
 656         /* version 2 stats */
 657         { "tx_deferral" },
 658         { "tx_packets" },
 659         { "rx_bytes" },
 660         { "tx_pause" },
 661         { "rx_pause" },
 662         { "rx_drop_frame" }
 663 };
 664
 665 struct nv_ethtool_stats {
 666         u64 tx_bytes;
 667         u64 tx_zero_rexmt;
 668         u64 tx_one_rexmt;
 669         u64 tx_many_rexmt;
 670         u64 tx_late_collision;
 671         u64 tx_fifo_errors;
 672         u64 tx_carrier_errors;
 673         u64 tx_excess_deferral;
 674         u64 tx_retry_error;
 675         u64 rx_frame_error;
 676         u64 rx_extra_byte;
 677         u64 rx_late_collision;
 678         u64 rx_runt;
 679         u64 rx_frame_too_long;
 680         u64 rx_over_errors;
 681         u64 rx_crc_errors;
 682         u64 rx_frame_align_error;
 683         u64 rx_length_error;
 684         u64 rx_unicast;
 685         u64 rx_multicast;
 686         u64 rx_broadcast;
 687         u64 rx_packets;
 688         u64 rx_errors_total;
 689         u64 tx_errors_total;
 690
 691         /* version 2 stats */
 692         u64 tx_deferral;
 693         u64 tx_packets;
 694         u64 rx_bytes;
 695         u64 tx_pause;
 696         u64 rx_pause;
 697         u64 rx_drop_frame;
 698 };
 699
 700 #define NV_DEV_STATISTICS_V2_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 701 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 702
 703 /* diagnostics */
 704 #define NV_TEST_COUNT_BASE 3
 705 #define NV_TEST_COUNT_EXTENDED 4
 706
 707 static const struct nv_ethtool_str nv_etests_str[] = {
 708         { "link      (online/offline)" },
 709         { "register  (offline)       " },
 710         { "interrupt (offline)       " },
 711         { "loopback  (offline)       " }
 712 };
 713
 714 struct register_test {
 715         __le32 reg;
 716         __le32 mask;
 717 };
 718
 719 static const struct register_test nv_registers_test[] = {
 720         { NvRegUnknownSetupReg6, 0x01 },
 721         { NvRegMisc1, 0x03c },
 722         { NvRegOffloadConfig, 0x03ff },
 723         { NvRegMulticastAddrA, 0xffffffff },
 724         { NvRegTxWatermark, 0x0ff },
 725         { NvRegWakeUpFlags, 0x07777 },
 726         { 0,0 }
 727 };
 728
 729 struct nv_skb_map {
 730         struct sk_buff *skb;
 731         dma_addr_t dma;
 732         unsigned int dma_len;
 733 };
 734
 735 /*
 736  * SMP locking:
 737  * All hardware access under dev->priv->lock, except the performance
 738  * critical parts:
 739  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 740  *      by the arch code for interrupts.
 741  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 742  *      needs dev->priv->lock :-(
 743  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 744  */
 745
 746 /* in dev: base, irq */
 747 struct fe_priv {
 748         spinlock_t lock;
 749
 750         struct net_device *dev;
 751         struct napi_struct napi;
 752
 753         /* General data:
 754          * Locking: spin_lock(&np->lock); */
 755         struct nv_ethtool_stats estats;
 756         int in_shutdown;
 757         u32 linkspeed;
 758         int duplex;
 759         int autoneg;
 760         int fixed_mode;
 761         int phyaddr;
 762         int wolenabled;
 763         unsigned int phy_oui;
 764         unsigned int phy_model;
 765         u16 gigabit;
 766         int intr_test;
 767         int recover_error;
 768
 769         /* General data: RO fields */
 770         dma_addr_t ring_addr;
 771         struct pci_dev *pci_dev;
 772         u32 orig_mac[2];
 773         u32 irqmask;
 774         u32 desc_ver;
 775         u32 txrxctl_bits;
 776         u32 vlanctl_bits;
 777         u32 driver_data;
 778         u32 register_size;
 779         int rx_csum;
 780         u32 mac_in_use;
 781
 782         void __iomem *base;
 783
 784         /* rx specific fields.
 785          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 786          */
 787         union ring_type get_rx, put_rx, first_rx, last_rx;
 788         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 789         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 790         struct nv_skb_map *rx_skb;
 791
 792         union ring_type rx_ring;
 793         unsigned int rx_buf_sz;
 794         unsigned int pkt_limit;
 795         struct timer_list oom_kick;
 796         struct timer_list nic_poll;
 797         struct timer_list stats_poll;
 798         u32 nic_poll_irq;
 799         int rx_ring_size;
 800
 801         /* media detection workaround.
 802          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 803          */
 804         int need_linktimer;
 805         unsigned long link_timeout;
 806         /*
 807          * tx specific fields.
 808          */
 809         union ring_type get_tx, put_tx, first_tx, last_tx;
 810         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 811         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 812         struct nv_skb_map *tx_skb;
 813
 814         union ring_type tx_ring;
 815         u32 tx_flags;
 816         int tx_ring_size;
 817         int tx_stop;
 818
 819         /* vlan fields */
 820         struct vlan_group *vlangrp;
 821
 822         /* msi/msi-x fields */
 823         u32 msi_flags;
 824         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 825
 826         /* flow control */
 827         u32 pause_flags;
 828 };
 829
 830 /*
 831  * Maximum number of loops until we assume that a bit in the irq mask
 832  * is stuck. Overridable with module param.
 833  */
 834 static int max_interrupt_work = 5;
 835
 836 /*
 837  * Optimization can be either throuput mode or cpu mode
 838  *
 839  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 840  * CPU Mode: Interrupts are controlled by a timer.
 841  */
 842 enum {
 843         NV_OPTIMIZATION_MODE_THROUGHPUT,
 844         NV_OPTIMIZATION_MODE_CPU
 845 };
 846 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
 847
 848 /*
 849  * Poll interval for timer irq
 850  *
 851  * This interval determines how frequent an interrupt is generated.
 852  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 853  * Min = 0, and Max = 65535
 854  */
 855 static int poll_interval = -1;
 856
 857 /*
 858  * MSI interrupts
 859  */
 860 enum {
 861         NV_MSI_INT_DISABLED,
 862         NV_MSI_INT_ENABLED
 863 };
 864 static int msi = NV_MSI_INT_ENABLED;
 865
 866 /*
 867  * MSIX interrupts
 868  */
 869 enum {
 870         NV_MSIX_INT_DISABLED,
 871         NV_MSIX_INT_ENABLED
 872 };
 873 static int msix = NV_MSIX_INT_DISABLED;
 874
 875 /*
 876  * DMA 64bit
 877  */
 878 enum {
 879         NV_DMA_64BIT_DISABLED,
 880         NV_DMA_64BIT_ENABLED
 881 };
 882 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 883
 884 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 885 {
 886         return netdev_priv(dev);
 887 }
 888
 889 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 890 {
 891         return ((struct fe_priv *)netdev_priv(dev))->base;
 892 }
 893
 894 static inline void pci_push(u8 __iomem *base)
 895 {
 896         /* force out pending posted writes */
 897         readl(base);
 898 }
 899
 900 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 901 {
 902         return le32_to_cpu(prd->flaglen)
 903                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 904 }
 905
 906 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 907 {
 908         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 909 }
 910
 911 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 912                                 int delay, int delaymax, const char *msg)
 913 {
 914         u8 __iomem *base = get_hwbase(dev);
 915
 916         pci_push(base);
 917         do {
 918                 udelay(delay);
 919                 delaymax -= delay;
 920                 if (delaymax < 0) {
 921                         if (msg)
 922                                 printk(msg);
 923                         return 1;
 924                 }
 925         } while ((readl(base + offset) & mask) != target);
 926         return 0;
 927 }
 928
 929 #define NV_SETUP_RX_RING 0x01
 930 #define NV_SETUP_TX_RING 0x02
 931
 932 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 933 {
 934         struct fe_priv *np = get_nvpriv(dev);
 935         u8 __iomem *base = get_hwbase(dev);
 936
 937         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 938                 if (rxtx_flags & NV_SETUP_RX_RING) {
 939                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 940                 }
 941                 if (rxtx_flags & NV_SETUP_TX_RING) {
 942                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 943                 }
 944         } else {
 945                 if (rxtx_flags & NV_SETUP_RX_RING) {
 946                         writel((u32) cpu_to_le64(np->ring_addr), base + NvRegRxRingPhysAddr);
 947                         writel((u32) (cpu_to_le64(np->ring_addr) >> 32), base + NvRegRxRingPhysAddrHigh);
 948                 }
 949                 if (rxtx_flags & NV_SETUP_TX_RING) {
 950                         writel((u32) cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 951                         writel((u32) (cpu_to_le64(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)) >> 32), base + NvRegTxRingPhysAddrHigh);
 952                 }
 953         }
 954 }
 955
 956 static void free_rings(struct net_device *dev)
 957 {
 958         struct fe_priv *np = get_nvpriv(dev);
 959
 960         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 961                 if (np->rx_ring.orig)
 962                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
 963                                             np->rx_ring.orig, np->ring_addr);
 964         } else {
 965                 if (np->rx_ring.ex)
 966                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
 967                                             np->rx_ring.ex, np->ring_addr);
 968         }
 969         if (np->rx_skb)
 970                 kfree(np->rx_skb);
 971         if (np->tx_skb)
 972                 kfree(np->tx_skb);
 973 }
 974
 975 static int using_multi_irqs(struct net_device *dev)
 976 {
 977         struct fe_priv *np = get_nvpriv(dev);
 978
 979         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
 980             ((np->msi_flags & NV_MSI_X_ENABLED) &&
 981              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
 982                 return 0;
 983         else
 984                 return 1;
 985 }
 986
 987 static void nv_enable_irq(struct net_device *dev)
 988 {
 989         struct fe_priv *np = get_nvpriv(dev);
 990
 991         if (!using_multi_irqs(dev)) {
 992                 if (np->msi_flags & NV_MSI_X_ENABLED)
 993                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
 994                 else
 995                         enable_irq(np->pci_dev->irq);
 996         } else {
 997                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
 998                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
 999                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1000         }
1001 }
1002
1003 static void nv_disable_irq(struct net_device *dev)
1004 {
1005         struct fe_priv *np = get_nvpriv(dev);
1006
1007         if (!using_multi_irqs(dev)) {
1008                 if (np->msi_flags & NV_MSI_X_ENABLED)
1009                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1010                 else
1011                         disable_irq(np->pci_dev->irq);
1012         } else {
1013                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1014                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1015                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1016         }
1017 }
1018
1019 /* In MSIX mode, a write to irqmask behaves as XOR */
1020 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1021 {
1022         u8 __iomem *base = get_hwbase(dev);
1023
1024         writel(mask, base + NvRegIrqMask);
1025 }
1026
1027 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1028 {
1029         struct fe_priv *np = get_nvpriv(dev);
1030         u8 __iomem *base = get_hwbase(dev);
1031
1032         if (np->msi_flags & NV_MSI_X_ENABLED) {
1033                 writel(mask, base + NvRegIrqMask);
1034         } else {
1035                 if (np->msi_flags & NV_MSI_ENABLED)
1036                         writel(0, base + NvRegMSIIrqMask);
1037                 writel(0, base + NvRegIrqMask);
1038         }
1039 }
1040
1041 #define MII_READ        (-1)
1042 /* mii_rw: read/write a register on the PHY.
1043  *
1044  * Caller must guarantee serialization
1045  */
1046 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1047 {
1048         u8 __iomem *base = get_hwbase(dev);
1049         u32 reg;
1050         int retval;
1051
1052         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1053
1054         reg = readl(base + NvRegMIIControl);
1055         if (reg & NVREG_MIICTL_INUSE) {
1056                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1057                 udelay(NV_MIIBUSY_DELAY);
1058         }
1059
1060         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1061         if (value != MII_READ) {
1062                 writel(value, base + NvRegMIIData);
1063                 reg |= NVREG_MIICTL_WRITE;
1064         }
1065         writel(reg, base + NvRegMIIControl);
1066
1067         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1068                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
1069                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
1070                                 dev->name, miireg, addr);
1071                 retval = -1;
1072         } else if (value != MII_READ) {
1073                 /* it was a write operation - fewer failures are detectable */
1074                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
1075                                 dev->name, value, miireg, addr);
1076                 retval = 0;
1077         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1078                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
1079                                 dev->name, miireg, addr);
1080                 retval = -1;
1081         } else {
1082                 retval = readl(base + NvRegMIIData);
1083                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
1084                                 dev->name, miireg, addr, retval);
1085         }
1086
1087         return retval;
1088 }
1089
1090 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1091 {
1092         struct fe_priv *np = netdev_priv(dev);
1093         u32 miicontrol;
1094         unsigned int tries = 0;
1095
1096         miicontrol = BMCR_RESET | bmcr_setup;
1097         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
1098                 return -1;
1099         }
1100
1101         /* wait for 500ms */
1102         msleep(500);
1103
1104         /* must wait till reset is deasserted */
1105         while (miicontrol & BMCR_RESET) {
1106                 msleep(10);
1107                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1108                 /* FIXME: 100 tries seem excessive */
1109                 if (tries++ > 100)
1110                         return -1;
1111         }
1112         return 0;
1113 }
1114
1115 static int phy_init(struct net_device *dev)
1116 {
1117         struct fe_priv *np = get_nvpriv(dev);
1118         u8 __iomem *base = get_hwbase(dev);
1119         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
1120
1121         /* phy errata for E3016 phy */
1122         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1123                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1124                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1125                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1126                         printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
1127                         return PHY_ERROR;
1128                 }
1129         }
1130         if (np->phy_oui == PHY_OUI_REALTEK) {
1131                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1132                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1133                         return PHY_ERROR;
1134                 }
1135                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1136                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1137                         return PHY_ERROR;
1138                 }
1139                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1140                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1141                         return PHY_ERROR;
1142                 }
1143                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1144                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1145                         return PHY_ERROR;
1146                 }
1147                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1148                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1149                         return PHY_ERROR;
1150                 }
1151         }
1152
1153         /* set advertise register */
1154         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1155         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
1156         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1157                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
1158                 return PHY_ERROR;
1159         }
1160
1161         /* get phy interface type */
1162         phyinterface = readl(base + NvRegPhyInterface);
1163
1164         /* see if gigabit phy */
1165         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1166         if (mii_status & PHY_GIGABIT) {
1167                 np->gigabit = PHY_GIGABIT;
1168                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
1169                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1170                 if (phyinterface & PHY_RGMII)
1171                         mii_control_1000 |= ADVERTISE_1000FULL;
1172                 else
1173                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1174
1175                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1176                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1177                         return PHY_ERROR;
1178                 }
1179         }
1180         else
1181                 np->gigabit = 0;
1182
1183         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1184         mii_control |= BMCR_ANENABLE;
1185
1186         /* reset the phy
1187          * (certain phys need bmcr to be setup with reset)
1188          */
1189         if (phy_reset(dev, mii_control)) {
1190                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
1191                 return PHY_ERROR;
1192         }
1193
1194         /* phy vendor specific configuration */
1195         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
1196                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1197                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1198                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1199                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
1200                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1201                         return PHY_ERROR;
1202                 }
1203                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1204                 phy_reserved |= PHY_CICADA_INIT5;
1205                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
1206                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1207                         return PHY_ERROR;
1208                 }
1209         }
1210         if (np->phy_oui == PHY_OUI_CICADA) {
1211                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1212                 phy_reserved |= PHY_CICADA_INIT6;
1213                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
1214                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1215                         return PHY_ERROR;
1216                 }
1217         }
1218         if (np->phy_oui == PHY_OUI_VITESSE) {
1219                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
1220                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1221                         return PHY_ERROR;
1222                 }
1223                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
1224                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1225                         return PHY_ERROR;
1226                 }
1227                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1228                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1229                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1230                         return PHY_ERROR;
1231                 }
1232                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1233                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1234                 phy_reserved |= PHY_VITESSE_INIT3;
1235                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1236                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1237                         return PHY_ERROR;
1238                 }
1239                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
1240                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1241                         return PHY_ERROR;
1242                 }
1243                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
1244                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1245                         return PHY_ERROR;
1246                 }
1247                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1248                 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1249                 phy_reserved |= PHY_VITESSE_INIT3;
1250                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1251                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1252                         return PHY_ERROR;
1253                 }
1254                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1255                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1256                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1257                         return PHY_ERROR;
1258                 }
1259                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
1260                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1261                         return PHY_ERROR;
1262                 }
1263                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
1264                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1265                         return PHY_ERROR;
1266                 }
1267                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
1268                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
1269                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1270                         return PHY_ERROR;
1271                 }
1272                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
1273                 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1274                 phy_reserved |= PHY_VITESSE_INIT8;
1275                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
1276                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1277                         return PHY_ERROR;
1278                 }
1279                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
1280                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1281                         return PHY_ERROR;
1282                 }
1283                 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
1284                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1285                         return PHY_ERROR;
1286                 }
1287         }
1288         if (np->phy_oui == PHY_OUI_REALTEK) {
1289                 /* reset could have cleared these out, set them back */
1290                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1291                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1292                         return PHY_ERROR;
1293                 }
1294                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
1295                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1296                         return PHY_ERROR;
1297                 }
1298                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
1299                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1300                         return PHY_ERROR;
1301                 }
1302                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
1303                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1304                         return PHY_ERROR;
1305                 }
1306                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
1307                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
1308                         return PHY_ERROR;
1309                 }
1310         }
1311
1312         /* some phys clear out pause advertisment on reset, set it back */
1313         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1314
1315         /* restart auto negotiation */
1316         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1317         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1318         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1319                 return PHY_ERROR;
1320         }
1321
1322         return 0;
1323 }
1324
1325 static void nv_start_rx(struct net_device *dev)
1326 {
1327         struct fe_priv *np = netdev_priv(dev);
1328         u8 __iomem *base = get_hwbase(dev);
1329         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1330
1331         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
1332         /* Already running? Stop it. */
1333         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1334                 rx_ctrl &= ~NVREG_RCVCTL_START;
1335                 writel(rx_ctrl, base + NvRegReceiverControl);
1336                 pci_push(base);
1337         }
1338         writel(np->linkspeed, base + NvRegLinkSpeed);
1339         pci_push(base);
1340         rx_ctrl |= NVREG_RCVCTL_START;
1341         if (np->mac_in_use)
1342                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1343         writel(rx_ctrl, base + NvRegReceiverControl);
1344         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
1345                                 dev->name, np->duplex, np->linkspeed);
1346         pci_push(base);
1347 }
1348
1349 static void nv_stop_rx(struct net_device *dev)
1350 {
1351         struct fe_priv *np = netdev_priv(dev);
1352         u8 __iomem *base = get_hwbase(dev);
1353         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1354
1355         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
1356         if (!np->mac_in_use)
1357                 rx_ctrl &= ~NVREG_RCVCTL_START;
1358         else
1359                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1360         writel(rx_ctrl, base + NvRegReceiverControl);
1361         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1362                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
1363                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
1364
1365         udelay(NV_RXSTOP_DELAY2);
1366         if (!np->mac_in_use)
1367                 writel(0, base + NvRegLinkSpeed);
1368 }
1369
1370 static void nv_start_tx(struct net_device *dev)
1371 {
1372         struct fe_priv *np = netdev_priv(dev);
1373         u8 __iomem *base = get_hwbase(dev);
1374         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1375
1376         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
1377         tx_ctrl |= NVREG_XMITCTL_START;
1378         if (np->mac_in_use)
1379                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1380         writel(tx_ctrl, base + NvRegTransmitterControl);
1381         pci_push(base);
1382 }
1383
1384 static void nv_stop_tx(struct net_device *dev)
1385 {
1386         struct fe_priv *np = netdev_priv(dev);
1387         u8 __iomem *base = get_hwbase(dev);
1388         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1389
1390         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
1391         if (!np->mac_in_use)
1392                 tx_ctrl &= ~NVREG_XMITCTL_START;
1393         else
1394                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1395         writel(tx_ctrl, base + NvRegTransmitterControl);
1396         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1397                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
1398                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
1399
1400         udelay(NV_TXSTOP_DELAY2);
1401         if (!np->mac_in_use)
1402                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1403                        base + NvRegTransmitPoll);
1404 }
1405
1406 static void nv_txrx_reset(struct net_device *dev)
1407 {
1408         struct fe_priv *np = netdev_priv(dev);
1409         u8 __iomem *base = get_hwbase(dev);
1410
1411         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
1412         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1413         pci_push(base);
1414         udelay(NV_TXRX_RESET_DELAY);
1415         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1416         pci_push(base);
1417 }
1418
1419 static void nv_mac_reset(struct net_device *dev)
1420 {
1421         struct fe_priv *np = netdev_priv(dev);
1422         u8 __iomem *base = get_hwbase(dev);
1423
1424         dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
1425         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1426         pci_push(base);
1427         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1428         pci_push(base);
1429         udelay(NV_MAC_RESET_DELAY);
1430         writel(0, base + NvRegMacReset);
1431         pci_push(base);
1432         udelay(NV_MAC_RESET_DELAY);
1433         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1434         pci_push(base);
1435 }
1436
1437 static void nv_get_hw_stats(struct net_device *dev)
1438 {
1439         struct fe_priv *np = netdev_priv(dev);
1440         u8 __iomem *base = get_hwbase(dev);
1441
1442         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1443         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1444         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1445         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1446         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1447         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1448         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1449         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1450         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1451         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1452         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1453         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1454         np->estats.rx_runt += readl(base + NvRegRxRunt);
1455         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1456         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1457         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1458         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1459         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1460         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1461         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1462         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1463         np->estats.rx_packets =
1464                 np->estats.rx_unicast +
1465                 np->estats.rx_multicast +
1466                 np->estats.rx_broadcast;
1467         np->estats.rx_errors_total =
1468                 np->estats.rx_crc_errors +
1469                 np->estats.rx_over_errors +
1470                 np->estats.rx_frame_error +
1471                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1472                 np->estats.rx_late_collision +
1473                 np->estats.rx_runt +
1474                 np->estats.rx_frame_too_long;
1475         np->estats.tx_errors_total =
1476                 np->estats.tx_late_collision +
1477                 np->estats.tx_fifo_errors +
1478                 np->estats.tx_carrier_errors +
1479                 np->estats.tx_excess_deferral +
1480                 np->estats.tx_retry_error;
1481
1482         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1483                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1484                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1485                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1486                 np->estats.tx_pause += readl(base + NvRegTxPause);
1487                 np->estats.rx_pause += readl(base + NvRegRxPause);
1488                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1489         }
1490 }
1491
1492 /*
1493  * nv_get_stats: dev->get_stats function
1494  * Get latest stats value from the nic.
1495  * Called with read_lock(&dev_base_lock) held for read -
1496  * only synchronized against unregister_netdevice.
1497  */
1498 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1499 {
1500         struct fe_priv *np = netdev_priv(dev);
1501
1502         /* If the nic supports hw counters then retrieve latest values */
1503         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2)) {
1504                 nv_get_hw_stats(dev);
1505
1506                 /* copy to net_device stats */
1507                 dev->stats.tx_bytes = np->estats.tx_bytes;
1508                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1509                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1510                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1511                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1512                 dev->stats.rx_errors = np->estats.rx_errors_total;
1513                 dev->stats.tx_errors = np->estats.tx_errors_total;
1514         }
1515
1516         return &dev->stats;
1517 }
1518
1519 /*
1520  * nv_alloc_rx: fill rx ring entries.
1521  * Return 1 if the allocations for the skbs failed and the
1522  * rx engine is without Available descriptors
1523  */
1524 static int nv_alloc_rx(struct net_device *dev)
1525 {
1526         struct fe_priv *np = netdev_priv(dev);
1527         struct ring_desc* less_rx;
1528
1529         less_rx = np->get_rx.orig;
1530         if (less_rx-- == np->first_rx.orig)
1531                 less_rx = np->last_rx.orig;
1532
1533         while (np->put_rx.orig != less_rx) {
1534                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1535                 if (skb) {
1536                         np->put_rx_ctx->skb = skb;
1537                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1538                                                              skb->data,
1539                                                              skb_tailroom(skb),
1540                                                              PCI_DMA_FROMDEVICE);
1541                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1542                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1543                         wmb();
1544                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1545                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1546                                 np->put_rx.orig = np->first_rx.orig;
1547                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1548                                 np->put_rx_ctx = np->first_rx_ctx;
1549                 } else {
1550                         return 1;
1551                 }
1552         }
1553         return 0;
1554 }
1555
1556 static int nv_alloc_rx_optimized(struct net_device *dev)
1557 {
1558         struct fe_priv *np = netdev_priv(dev);
1559         struct ring_desc_ex* less_rx;
1560
1561         less_rx = np->get_rx.ex;
1562         if (less_rx-- == np->first_rx.ex)
1563                 less_rx = np->last_rx.ex;
1564
1565         while (np->put_rx.ex != less_rx) {
1566                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1567                 if (skb) {
1568                         np->put_rx_ctx->skb = skb;
1569                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1570                                                              skb->data,
1571                                                              skb_tailroom(skb),
1572                                                              PCI_DMA_FROMDEVICE);
1573                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1574                         np->put_rx.ex->bufhigh = cpu_to_le64(np->put_rx_ctx->dma) >> 32;
1575                         np->put_rx.ex->buflow = cpu_to_le64(np->put_rx_ctx->dma) & 0x0FFFFFFFF;
1576                         wmb();
1577                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1578                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1579                                 np->put_rx.ex = np->first_rx.ex;
1580                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1581                                 np->put_rx_ctx = np->first_rx_ctx;
1582                 } else {
1583                         return 1;
1584                 }
1585         }
1586         return 0;
1587 }
1588
1589 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1590 #ifdef CONFIG_FORCEDETH_NAPI
1591 static void nv_do_rx_refill(unsigned long data)
1592 {
1593         struct net_device *dev = (struct net_device *) data;
1594         struct fe_priv *np = netdev_priv(dev);
1595
1596         /* Just reschedule NAPI rx processing */
1597         netif_rx_schedule(dev, &np->napi);
1598 }
1599 #else
1600 static void nv_do_rx_refill(unsigned long data)
1601 {
1602         struct net_device *dev = (struct net_device *) data;
1603         struct fe_priv *np = netdev_priv(dev);
1604         int retcode;
1605
1606         if (!using_multi_irqs(dev)) {
1607                 if (np->msi_flags & NV_MSI_X_ENABLED)
1608                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1609                 else
1610                         disable_irq(np->pci_dev->irq);
1611         } else {
1612                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1613         }
1614         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1615                 retcode = nv_alloc_rx(dev);
1616         else
1617                 retcode = nv_alloc_rx_optimized(dev);
1618         if (retcode) {
1619                 spin_lock_irq(&np->lock);
1620                 if (!np->in_shutdown)
1621                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1622                 spin_unlock_irq(&np->lock);
1623         }
1624         if (!using_multi_irqs(dev)) {
1625                 if (np->msi_flags & NV_MSI_X_ENABLED)
1626                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1627                 else
1628                         enable_irq(np->pci_dev->irq);
1629         } else {
1630                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1631         }
1632 }
1633 #endif
1634
1635 static void nv_init_rx(struct net_device *dev)
1636 {
1637         struct fe_priv *np = netdev_priv(dev);
1638         int i;
1639         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1640         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1641                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1642         else
1643                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1644         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1645         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1646
1647         for (i = 0; i < np->rx_ring_size; i++) {
1648                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1649                         np->rx_ring.orig[i].flaglen = 0;
1650                         np->rx_ring.orig[i].buf = 0;
1651                 } else {
1652                         np->rx_ring.ex[i].flaglen = 0;
1653                         np->rx_ring.ex[i].txvlan = 0;
1654                         np->rx_ring.ex[i].bufhigh = 0;
1655                         np->rx_ring.ex[i].buflow = 0;
1656                 }
1657                 np->rx_skb[i].skb = NULL;
1658                 np->rx_skb[i].dma = 0;
1659         }
1660 }
1661
1662 static void nv_init_tx(struct net_device *dev)
1663 {
1664         struct fe_priv *np = netdev_priv(dev);
1665         int i;
1666         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1667         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1668                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1669         else
1670                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1671         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1672         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1673
1674         for (i = 0; i < np->tx_ring_size; i++) {
1675                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1676                         np->tx_ring.orig[i].flaglen = 0;
1677                         np->tx_ring.orig[i].buf = 0;
1678                 } else {
1679                         np->tx_ring.ex[i].flaglen = 0;
1680                         np->tx_ring.ex[i].txvlan = 0;
1681                         np->tx_ring.ex[i].bufhigh = 0;
1682                         np->tx_ring.ex[i].buflow = 0;
1683                 }
1684                 np->tx_skb[i].skb = NULL;
1685                 np->tx_skb[i].dma = 0;
1686         }
1687 }
1688
1689 static int nv_init_ring(struct net_device *dev)
1690 {
1691         struct fe_priv *np = netdev_priv(dev);
1692
1693         nv_init_tx(dev);
1694         nv_init_rx(dev);
1695         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1696                 return nv_alloc_rx(dev);
1697         else
1698                 return nv_alloc_rx_optimized(dev);
1699 }
1700
1701 static int nv_release_txskb(struct net_device *dev, struct nv_skb_map* tx_skb)
1702 {
1703         struct fe_priv *np = netdev_priv(dev);
1704
1705         if (tx_skb->dma) {
1706                 pci_unmap_page(np->pci_dev, tx_skb->dma,
1707                                tx_skb->dma_len,
1708                                PCI_DMA_TODEVICE);
1709                 tx_skb->dma = 0;
1710         }
1711         if (tx_skb->skb) {
1712                 dev_kfree_skb_any(tx_skb->skb);
1713                 tx_skb->skb = NULL;
1714                 return 1;
1715         } else {
1716                 return 0;
1717         }
1718 }
1719
1720 static void nv_drain_tx(struct net_device *dev)
1721 {
1722         struct fe_priv *np = netdev_priv(dev);
1723         unsigned int i;
1724
1725         for (i = 0; i < np->tx_ring_size; i++) {
1726                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1727                         np->tx_ring.orig[i].flaglen = 0;
1728                         np->tx_ring.orig[i].buf = 0;
1729                 } else {
1730                         np->tx_ring.ex[i].flaglen = 0;
1731                         np->tx_ring.ex[i].txvlan = 0;
1732                         np->tx_ring.ex[i].bufhigh = 0;
1733                         np->tx_ring.ex[i].buflow = 0;
1734                 }
1735                 if (nv_release_txskb(dev, &np->tx_skb[i]))
1736                         dev->stats.tx_dropped++;
1737         }
1738 }
1739
1740 static void nv_drain_rx(struct net_device *dev)
1741 {
1742         struct fe_priv *np = netdev_priv(dev);
1743         int i;
1744
1745         for (i = 0; i < np->rx_ring_size; i++) {
1746                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1747                         np->rx_ring.orig[i].flaglen = 0;
1748                         np->rx_ring.orig[i].buf = 0;
1749                 } else {
1750                         np->rx_ring.ex[i].flaglen = 0;
1751                         np->rx_ring.ex[i].txvlan = 0;
1752                         np->rx_ring.ex[i].bufhigh = 0;
1753                         np->rx_ring.ex[i].buflow = 0;
1754                 }
1755                 wmb();
1756                 if (np->rx_skb[i].skb) {
1757                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1758                                          (skb_end_pointer(np->rx_skb[i].skb) -
1759                                           np->rx_skb[i].skb->data),
1760                                          PCI_DMA_FROMDEVICE);
1761                         dev_kfree_skb(np->rx_skb[i].skb);
1762                         np->rx_skb[i].skb = NULL;
1763                 }
1764         }
1765 }
1766
1767 static void drain_ring(struct net_device *dev)
1768 {
1769         nv_drain_tx(dev);
1770         nv_drain_rx(dev);
1771 }
1772
1773 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1774 {
1775         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1776 }
1777
1778 /*
1779  * nv_start_xmit: dev->hard_start_xmit function
1780  * Called with netif_tx_lock held.
1781  */
1782 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1783 {
1784         struct fe_priv *np = netdev_priv(dev);
1785         u32 tx_flags = 0;
1786         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1787         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1788         unsigned int i;
1789         u32 offset = 0;
1790         u32 bcnt;
1791         u32 size = skb->len-skb->data_len;
1792         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1793         u32 empty_slots;
1794         struct ring_desc* put_tx;
1795         struct ring_desc* start_tx;
1796         struct ring_desc* prev_tx;
1797         struct nv_skb_map* prev_tx_ctx;
1798
1799         /* add fragments to entries count */
1800         for (i = 0; i < fragments; i++) {
1801                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1802                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1803         }
1804
1805         empty_slots = nv_get_empty_tx_slots(np);
1806         if (unlikely(empty_slots <= entries)) {
1807                 spin_lock_irq(&np->lock);
1808                 netif_stop_queue(dev);
1809                 np->tx_stop = 1;
1810                 spin_unlock_irq(&np->lock);
1811                 return NETDEV_TX_BUSY;
1812         }
1813
1814         start_tx = put_tx = np->put_tx.orig;
1815
1816         /* setup the header buffer */
1817         do {
1818                 prev_tx = put_tx;
1819                 prev_tx_ctx = np->put_tx_ctx;
1820                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1821                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1822                                                 PCI_DMA_TODEVICE);
1823                 np->put_tx_ctx->dma_len = bcnt;
1824                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1825                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1826
1827                 tx_flags = np->tx_flags;
1828                 offset += bcnt;
1829                 size -= bcnt;
1830                 if (unlikely(put_tx++ == np->last_tx.orig))
1831                         put_tx = np->first_tx.orig;
1832                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1833                         np->put_tx_ctx = np->first_tx_ctx;
1834         } while (size);
1835
1836         /* setup the fragments */
1837         for (i = 0; i < fragments; i++) {
1838                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1839                 u32 size = frag->size;
1840                 offset = 0;
1841
1842                 do {
1843                         prev_tx = put_tx;
1844                         prev_tx_ctx = np->put_tx_ctx;
1845                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1846                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1847                                                            PCI_DMA_TODEVICE);
1848                         np->put_tx_ctx->dma_len = bcnt;
1849                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
1850                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1851
1852                         offset += bcnt;
1853                         size -= bcnt;
1854                         if (unlikely(put_tx++ == np->last_tx.orig))
1855                                 put_tx = np->first_tx.orig;
1856                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1857                                 np->put_tx_ctx = np->first_tx_ctx;
1858                 } while (size);
1859         }
1860
1861         /* set last fragment flag  */
1862         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
1863
1864         /* save skb in this slot's context area */
1865         prev_tx_ctx->skb = skb;
1866
1867         if (skb_is_gso(skb))
1868                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1869         else
1870                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1871                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1872
1873         spin_lock_irq(&np->lock);
1874
1875         /* set tx flags */
1876         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
1877         np->put_tx.orig = put_tx;
1878
1879         spin_unlock_irq(&np->lock);
1880
1881         dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
1882                 dev->name, entries, tx_flags_extra);
1883         {
1884                 int j;
1885                 for (j=0; j<64; j++) {
1886                         if ((j%16) == 0)
1887                                 dprintk("\n%03x:", j);
1888                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1889                 }
1890                 dprintk("\n");
1891         }
1892
1893         dev->trans_start = jiffies;
1894         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1895         return NETDEV_TX_OK;
1896 }
1897
1898 static int nv_start_xmit_optimized(struct sk_buff *skb, struct net_device *dev)
1899 {
1900         struct fe_priv *np = netdev_priv(dev);
1901         u32 tx_flags = 0;
1902         u32 tx_flags_extra;
1903         unsigned int fragments = skb_shinfo(skb)->nr_frags;
1904         unsigned int i;
1905         u32 offset = 0;
1906         u32 bcnt;
1907         u32 size = skb->len-skb->data_len;
1908         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1909         u32 empty_slots;
1910         struct ring_desc_ex* put_tx;
1911         struct ring_desc_ex* start_tx;
1912         struct ring_desc_ex* prev_tx;
1913         struct nv_skb_map* prev_tx_ctx;
1914
1915         /* add fragments to entries count */
1916         for (i = 0; i < fragments; i++) {
1917                 entries += (skb_shinfo(skb)->frags[i].size >> NV_TX2_TSO_MAX_SHIFT) +
1918                            ((skb_shinfo(skb)->frags[i].size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
1919         }
1920
1921         empty_slots = nv_get_empty_tx_slots(np);
1922         if (unlikely(empty_slots <= entries)) {
1923                 spin_lock_irq(&np->lock);
1924                 netif_stop_queue(dev);
1925                 np->tx_stop = 1;
1926                 spin_unlock_irq(&np->lock);
1927                 return NETDEV_TX_BUSY;
1928         }
1929
1930         start_tx = put_tx = np->put_tx.ex;
1931
1932         /* setup the header buffer */
1933         do {
1934                 prev_tx = put_tx;
1935                 prev_tx_ctx = np->put_tx_ctx;
1936                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1937                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
1938                                                 PCI_DMA_TODEVICE);
1939                 np->put_tx_ctx->dma_len = bcnt;
1940                 put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1941                 put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1942                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1943
1944                 tx_flags = NV_TX2_VALID;
1945                 offset += bcnt;
1946                 size -= bcnt;
1947                 if (unlikely(put_tx++ == np->last_tx.ex))
1948                         put_tx = np->first_tx.ex;
1949                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1950                         np->put_tx_ctx = np->first_tx_ctx;
1951         } while (size);
1952
1953         /* setup the fragments */
1954         for (i = 0; i < fragments; i++) {
1955                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1956                 u32 size = frag->size;
1957                 offset = 0;
1958
1959                 do {
1960                         prev_tx = put_tx;
1961                         prev_tx_ctx = np->put_tx_ctx;
1962                         bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
1963                         np->put_tx_ctx->dma = pci_map_page(np->pci_dev, frag->page, frag->page_offset+offset, bcnt,
1964                                                            PCI_DMA_TODEVICE);
1965                         np->put_tx_ctx->dma_len = bcnt;
1966                         put_tx->bufhigh = cpu_to_le64(np->put_tx_ctx->dma) >> 32;
1967                         put_tx->buflow = cpu_to_le64(np->put_tx_ctx->dma) & 0x0FFFFFFFF;
1968                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
1969
1970                         offset += bcnt;
1971                         size -= bcnt;
1972                         if (unlikely(put_tx++ == np->last_tx.ex))
1973                                 put_tx = np->first_tx.ex;
1974                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
1975                                 np->put_tx_ctx = np->first_tx_ctx;
1976                 } while (size);
1977         }
1978
1979         /* set last fragment flag  */
1980         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
1981
1982         /* save skb in this slot's context area */
1983         prev_tx_ctx->skb = skb;
1984
1985         if (skb_is_gso(skb))
1986                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
1987         else
1988                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
1989                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
1990
1991         /* vlan tag */
1992         if (likely(!np->vlangrp)) {
1993                 start_tx->txvlan = 0;
1994         } else {
1995                 if (vlan_tx_tag_present(skb))
1996                         start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT | vlan_tx_tag_get(skb));
1997                 else
1998                         start_tx->txvlan = 0;
1999         }
2000
2001         spin_lock_irq(&np->lock);
2002
2003         /* set tx flags */
2004         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2005         np->put_tx.ex = put_tx;
2006
2007         spin_unlock_irq(&np->lock);
2008
2009         dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
2010                 dev->name, entries, tx_flags_extra);
2011         {
2012                 int j;
2013                 for (j=0; j<64; j++) {
2014                         if ((j%16) == 0)
2015                                 dprintk("\n%03x:", j);
2016                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2017                 }
2018                 dprintk("\n");
2019         }
2020
2021         dev->trans_start = jiffies;
2022         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2023         return NETDEV_TX_OK;
2024 }
2025
2026 /*
2027  * nv_tx_done: check for completed packets, release the skbs.
2028  *
2029  * Caller must own np->lock.
2030  */
2031 static void nv_tx_done(struct net_device *dev)
2032 {
2033         struct fe_priv *np = netdev_priv(dev);
2034         u32 flags;
2035         struct ring_desc* orig_get_tx = np->get_tx.orig;
2036
2037         while ((np->get_tx.orig != np->put_tx.orig) &&
2038                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID)) {
2039
2040                 dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
2041                                         dev->name, flags);
2042
2043                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2044                                np->get_tx_ctx->dma_len,
2045                                PCI_DMA_TODEVICE);
2046                 np->get_tx_ctx->dma = 0;
2047
2048                 if (np->desc_ver == DESC_VER_1) {
2049                         if (flags & NV_TX_LASTPACKET) {
2050                                 if (flags & NV_TX_ERROR) {
2051                                         if (flags & NV_TX_UNDERFLOW)
2052                                                 dev->stats.tx_fifo_errors++;
2053                                         if (flags & NV_TX_CARRIERLOST)
2054                                                 dev->stats.tx_carrier_errors++;
2055                                         dev->stats.tx_errors++;
2056                                 } else {
2057                                         dev->stats.tx_packets++;
2058                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2059                                 }
2060                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2061                                 np->get_tx_ctx->skb = NULL;
2062                         }
2063                 } else {
2064                         if (flags & NV_TX2_LASTPACKET) {
2065                                 if (flags & NV_TX2_ERROR) {
2066                                         if (flags & NV_TX2_UNDERFLOW)
2067                                                 dev->stats.tx_fifo_errors++;
2068                                         if (flags & NV_TX2_CARRIERLOST)
2069                                                 dev->stats.tx_carrier_errors++;
2070                                         dev->stats.tx_errors++;
2071                                 } else {
2072                                         dev->stats.tx_packets++;
2073                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2074                                 }
2075                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2076                                 np->get_tx_ctx->skb = NULL;
2077                         }
2078                 }
2079                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2080                         np->get_tx.orig = np->first_tx.orig;
2081                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2082                         np->get_tx_ctx = np->first_tx_ctx;
2083         }
2084         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2085                 np->tx_stop = 0;
2086                 netif_wake_queue(dev);
2087         }
2088 }
2089
2090 static void nv_tx_done_optimized(struct net_device *dev, int limit)
2091 {
2092         struct fe_priv *np = netdev_priv(dev);
2093         u32 flags;
2094         struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
2095
2096         while ((np->get_tx.ex != np->put_tx.ex) &&
2097                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX_VALID) &&
2098                (limit-- > 0)) {
2099
2100                 dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
2101                                         dev->name, flags);
2102
2103                 pci_unmap_page(np->pci_dev, np->get_tx_ctx->dma,
2104                                np->get_tx_ctx->dma_len,
2105                                PCI_DMA_TODEVICE);
2106                 np->get_tx_ctx->dma = 0;
2107
2108                 if (flags & NV_TX2_LASTPACKET) {
2109                         if (!(flags & NV_TX2_ERROR))
2110                                 dev->stats.tx_packets++;
2111                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2112                         np->get_tx_ctx->skb = NULL;
2113                 }
2114                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2115                         np->get_tx.ex = np->first_tx.ex;
2116                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2117                         np->get_tx_ctx = np->first_tx_ctx;
2118         }
2119         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2120                 np->tx_stop = 0;
2121                 netif_wake_queue(dev);
2122         }
2123 }
2124
2125 /*
2126  * nv_tx_timeout: dev->tx_timeout function
2127  * Called with netif_tx_lock held.
2128  */
2129 static void nv_tx_timeout(struct net_device *dev)
2130 {
2131         struct fe_priv *np = netdev_priv(dev);
2132         u8 __iomem *base = get_hwbase(dev);
2133         u32 status;
2134
2135         if (np->msi_flags & NV_MSI_X_ENABLED)
2136                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2137         else
2138                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2139
2140         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
2141
2142         {
2143                 int i;
2144
2145                 printk(KERN_INFO "%s: Ring at %lx\n",
2146                        dev->name, (unsigned long)np->ring_addr);
2147                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
2148                 for (i=0;i<=np->register_size;i+= 32) {
2149                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2150                                         i,
2151                                         readl(base + i + 0), readl(base + i + 4),
2152                                         readl(base + i + 8), readl(base + i + 12),
2153                                         readl(base + i + 16), readl(base + i + 20),
2154                                         readl(base + i + 24), readl(base + i + 28));
2155                 }
2156                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
2157                 for (i=0;i<np->tx_ring_size;i+= 4) {
2158                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2159                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2160                                        i,
2161                                        le32_to_cpu(np->tx_ring.orig[i].buf),
2162                                        le32_to_cpu(np->tx_ring.orig[i].flaglen),
2163                                        le32_to_cpu(np->tx_ring.orig[i+1].buf),
2164                                        le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2165                                        le32_to_cpu(np->tx_ring.orig[i+2].buf),
2166                                        le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2167                                        le32_to_cpu(np->tx_ring.orig[i+3].buf),
2168                                        le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2169                         } else {
2170                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2171                                        i,
2172                                        le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2173                                        le32_to_cpu(np->tx_ring.ex[i].buflow),
2174                                        le32_to_cpu(np->tx_ring.ex[i].flaglen),
2175                                        le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2176                                        le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2177                                        le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2178                                        le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2179                                        le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2180                                        le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2181                                        le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2182                                        le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2183                                        le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2184                         }
2185                 }
2186         }
2187
2188         spin_lock_irq(&np->lock);
2189
2190         /* 1) stop tx engine */
2191         nv_stop_tx(dev);
2192
2193         /* 2) check that the packets were not sent already: */
2194         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2195                 nv_tx_done(dev);
2196         else
2197                 nv_tx_done_optimized(dev, np->tx_ring_size);
2198
2199         /* 3) if there are dead entries: clear everything */
2200         if (np->get_tx_ctx != np->put_tx_ctx) {
2201                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
2202                 nv_drain_tx(dev);
2203                 nv_init_tx(dev);
2204                 setup_hw_rings(dev, NV_SETUP_TX_RING);
2205         }
2206
2207         netif_wake_queue(dev);
2208
2209         /* 4) restart tx engine */
2210         nv_start_tx(dev);
2211         spin_unlock_irq(&np->lock);
2212 }
2213
2214 /*
2215  * Called when the nic notices a mismatch between the actual data len on the
2216  * wire and the len indicated in the 802 header
2217  */
2218 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2219 {
2220         int hdrlen;     /* length of the 802 header */
2221         int protolen;   /* length as stored in the proto field */
2222
2223         /* 1) calculate len according to header */
2224         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2225                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
2226                 hdrlen = VLAN_HLEN;
2227         } else {
2228                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
2229                 hdrlen = ETH_HLEN;
2230         }
2231         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
2232                                 dev->name, datalen, protolen, hdrlen);
2233         if (protolen > ETH_DATA_LEN)
2234                 return datalen; /* Value in proto field not a len, no checks possible */
2235
2236         protolen += hdrlen;
2237         /* consistency checks: */
2238         if (datalen > ETH_ZLEN) {
2239                 if (datalen >= protolen) {
2240                         /* more data on wire than in 802 header, trim of
2241                          * additional data.
2242                          */
2243                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2244                                         dev->name, protolen);
2245                         return protolen;
2246                 } else {
2247                         /* less data on wire than mentioned in header.
2248                          * Discard the packet.
2249                          */
2250                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
2251                                         dev->name);
2252                         return -1;
2253                 }
2254         } else {
2255                 /* short packet. Accept only if 802 values are also short */
2256                 if (protolen > ETH_ZLEN) {
2257                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
2258                                         dev->name);
2259                         return -1;
2260                 }
2261                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
2262                                 dev->name, datalen);
2263                 return datalen;
2264         }
2265 }
2266
2267 static int nv_rx_process(struct net_device *dev, int limit)
2268 {
2269         struct fe_priv *np = netdev_priv(dev);
2270         u32 flags;
2271         int rx_work = 0;
2272         struct sk_buff *skb;
2273         int len;
2274
2275         while((np->get_rx.orig != np->put_rx.orig) &&
2276               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2277                 (rx_work < limit)) {
2278
2279                 dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
2280                                         dev->name, flags);
2281
2282                 /*
2283                  * the packet is for us - immediately tear down the pci mapping.
2284                  * TODO: check if a prefetch of the first cacheline improves
2285                  * the performance.
2286                  */
2287                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2288                                 np->get_rx_ctx->dma_len,
2289                                 PCI_DMA_FROMDEVICE);
2290                 skb = np->get_rx_ctx->skb;
2291                 np->get_rx_ctx->skb = NULL;
2292
2293                 {
2294                         int j;
2295                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2296                         for (j=0; j<64; j++) {
2297                                 if ((j%16) == 0)
2298                                         dprintk("\n%03x:", j);
2299                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2300                         }
2301                         dprintk("\n");
2302                 }
2303                 /* look at what we actually got: */
2304                 if (np->desc_ver == DESC_VER_1) {
2305                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2306                                 len = flags & LEN_MASK_V1;
2307                                 if (unlikely(flags & NV_RX_ERROR)) {
2308                                         if (flags & NV_RX_ERROR4) {
2309                                                 len = nv_getlen(dev, skb->data, len);
2310                                                 if (len < 0) {
2311                                                         dev->stats.rx_errors++;
2312                                                         dev_kfree_skb(skb);
2313                                                         goto next_pkt;
2314                                                 }
2315                                         }
2316                                         /* framing errors are soft errors */
2317                                         else if (flags & NV_RX_FRAMINGERR) {
2318                                                 if (flags & NV_RX_SUBSTRACT1) {
2319                                                         len--;
2320                                                 }
2321                                         }
2322                                         /* the rest are hard errors */
2323                                         else {
2324                                                 if (flags & NV_RX_MISSEDFRAME)
2325                                                         dev->stats.rx_missed_errors++;
2326                                                 if (flags & NV_RX_CRCERR)
2327                                                         dev->stats.rx_crc_errors++;
2328                                                 if (flags & NV_RX_OVERFLOW)
2329                                                         dev->stats.rx_over_errors++;
2330                                                 dev->stats.rx_errors++;
2331                                                 dev_kfree_skb(skb);
2332                                                 goto next_pkt;
2333                                         }
2334                                 }
2335                         } else {
2336                                 dev_kfree_skb(skb);
2337                                 goto next_pkt;
2338                         }
2339                 } else {
2340                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2341                                 len = flags & LEN_MASK_V2;
2342                                 if (unlikely(flags & NV_RX2_ERROR)) {
2343                                         if (flags & NV_RX2_ERROR4) {
2344                                                 len = nv_getlen(dev, skb->data, len);
2345                                                 if (len < 0) {
2346                                                         dev->stats.rx_errors++;
2347                                                         dev_kfree_skb(skb);
2348                                                         goto next_pkt;
2349                                                 }
2350                                         }
2351                                         /* framing errors are soft errors */
2352                                         else if (flags & NV_RX2_FRAMINGERR) {
2353                                                 if (flags & NV_RX2_SUBSTRACT1) {
2354                                                         len--;
2355                                                 }
2356                                         }
2357                                         /* the rest are hard errors */
2358                                         else {
2359                                                 if (flags & NV_RX2_CRCERR)
2360                                                         dev->stats.rx_crc_errors++;
2361                                                 if (flags & NV_RX2_OVERFLOW)
2362                                                         dev->stats.rx_over_errors++;
2363                                                 dev->stats.rx_errors++;
2364                                                 dev_kfree_skb(skb);
2365                                                 goto next_pkt;
2366                                         }
2367                                 }
2368                                 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2369                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2370                                 } else {
2371                                         if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2372                                             (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2373                                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2374                                         }
2375                                 }
2376                         } else {
2377                                 dev_kfree_skb(skb);
2378                                 goto next_pkt;
2379                         }
2380                 }
2381                 /* got a valid packet - forward it to the network core */
2382                 skb_put(skb, len);
2383                 skb->protocol = eth_type_trans(skb, dev);
2384                 dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
2385                                         dev->name, len, skb->protocol);
2386 #ifdef CONFIG_FORCEDETH_NAPI
2387                 netif_receive_skb(skb);
2388 #else
2389                 netif_rx(skb);
2390 #endif
2391                 dev->last_rx = jiffies;
2392                 dev->stats.rx_packets++;
2393                 dev->stats.rx_bytes += len;
2394 next_pkt:
2395                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2396                         np->get_rx.orig = np->first_rx.orig;
2397                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2398                         np->get_rx_ctx = np->first_rx_ctx;
2399
2400                 rx_work++;
2401         }
2402
2403         return rx_work;
2404 }
2405
2406 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2407 {
2408         struct fe_priv *np = netdev_priv(dev);
2409         u32 flags;
2410         u32 vlanflags = 0;
2411         int rx_work = 0;
2412         struct sk_buff *skb;
2413         int len;
2414
2415         while((np->get_rx.ex != np->put_rx.ex) &&
2416               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2417               (rx_work < limit)) {
2418
2419                 dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
2420                                         dev->name, flags);
2421
2422                 /*
2423                  * the packet is for us - immediately tear down the pci mapping.
2424                  * TODO: check if a prefetch of the first cacheline improves
2425                  * the performance.
2426                  */
2427                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2428                                 np->get_rx_ctx->dma_len,
2429                                 PCI_DMA_FROMDEVICE);
2430                 skb = np->get_rx_ctx->skb;
2431                 np->get_rx_ctx->skb = NULL;
2432
2433                 {
2434                         int j;
2435                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
2436                         for (j=0; j<64; j++) {
2437                                 if ((j%16) == 0)
2438                                         dprintk("\n%03x:", j);
2439                                 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
2440                         }
2441                         dprintk("\n");
2442                 }
2443                 /* look at what we actually got: */
2444                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2445                         len = flags & LEN_MASK_V2;
2446                         if (unlikely(flags & NV_RX2_ERROR)) {
2447                                 if (flags & NV_RX2_ERROR4) {
2448                                         len = nv_getlen(dev, skb->data, len);
2449                                         if (len < 0) {
2450                                                 dev_kfree_skb(skb);
2451                                                 goto next_pkt;
2452                                         }
2453                                 }
2454                                 /* framing errors are soft errors */
2455                                 else if (flags & NV_RX2_FRAMINGERR) {
2456                                         if (flags & NV_RX2_SUBSTRACT1) {
2457                                                 len--;
2458                                         }
2459                                 }
2460                                 /* the rest are hard errors */
2461                                 else {
2462                                         dev_kfree_skb(skb);
2463                                         goto next_pkt;
2464                                 }
2465                         }
2466
2467                         if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK2)/*ip and tcp */ {
2468                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2469                         } else {
2470                                 if ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK1 ||
2471                                     (flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUMOK3) {
2472                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2473                                 }
2474                         }
2475
2476                         /* got a valid packet - forward it to the network core */
2477                         skb_put(skb, len);
2478                         skb->protocol = eth_type_trans(skb, dev);
2479                         prefetch(skb->data);
2480
2481                         dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
2482                                 dev->name, len, skb->protocol);
2483
2484                         if (likely(!np->vlangrp)) {
2485 #ifdef CONFIG_FORCEDETH_NAPI
2486                                 netif_receive_skb(skb);
2487 #else
2488                                 netif_rx(skb);
2489 #endif
2490                         } else {
2491                                 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2492                                 if (vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2493 #ifdef CONFIG_FORCEDETH_NAPI
2494                                         vlan_hwaccel_receive_skb(skb, np->vlangrp,
2495                                                                  vlanflags & NV_RX3_VLAN_TAG_MASK);
2496 #else
2497                                         vlan_hwaccel_rx(skb, np->vlangrp,
2498                                                         vlanflags & NV_RX3_VLAN_TAG_MASK);
2499 #endif
2500                                 } else {
2501 #ifdef CONFIG_FORCEDETH_NAPI
2502                                         netif_receive_skb(skb);
2503 #else
2504                                         netif_rx(skb);
2505 #endif
2506                                 }
2507                         }
2508
2509                         dev->last_rx = jiffies;
2510                         dev->stats.rx_packets++;
2511                         dev->stats.rx_bytes += len;
2512                 } else {
2513                         dev_kfree_skb(skb);
2514                 }
2515 next_pkt:
2516                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2517                         np->get_rx.ex = np->first_rx.ex;
2518                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2519                         np->get_rx_ctx = np->first_rx_ctx;
2520
2521                 rx_work++;
2522         }
2523
2524         return rx_work;
2525 }
2526
2527 static void set_bufsize(struct net_device *dev)
2528 {
2529         struct fe_priv *np = netdev_priv(dev);
2530
2531         if (dev->mtu <= ETH_DATA_LEN)
2532                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2533         else
2534                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2535 }
2536
2537 /*
2538  * nv_change_mtu: dev->change_mtu function
2539  * Called with dev_base_lock held for read.
2540  */
2541 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2542 {
2543         struct fe_priv *np = netdev_priv(dev);
2544         int old_mtu;
2545
2546         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2547                 return -EINVAL;
2548
2549         old_mtu = dev->mtu;
2550         dev->mtu = new_mtu;
2551
2552         /* return early if the buffer sizes will not change */
2553         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2554                 return 0;
2555         if (old_mtu == new_mtu)
2556                 return 0;
2557
2558         /* synchronized against open : rtnl_lock() held by caller */
2559         if (netif_running(dev)) {
2560                 u8 __iomem *base = get_hwbase(dev);
2561                 /*
2562                  * It seems that the nic preloads valid ring entries into an
2563                  * internal buffer. The procedure for flushing everything is
2564                  * guessed, there is probably a simpler approach.
2565                  * Changing the MTU is a rare event, it shouldn't matter.
2566                  */
2567                 nv_disable_irq(dev);
2568                 netif_tx_lock_bh(dev);
2569                 spin_lock(&np->lock);
2570                 /* stop engines */
2571                 nv_stop_rx(dev);
2572                 nv_stop_tx(dev);
2573                 nv_txrx_reset(dev);
2574                 /* drain rx queue */
2575                 nv_drain_rx(dev);
2576                 nv_drain_tx(dev);
2577                 /* reinit driver view of the rx queue */
2578                 set_bufsize(dev);
2579                 if (nv_init_ring(dev)) {
2580                         if (!np->in_shutdown)
2581                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2582                 }
2583                 /* reinit nic view of the rx queue */
2584                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2585                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2586                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2587                         base + NvRegRingSizes);
2588                 pci_push(base);
2589                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2590                 pci_push(base);
2591
2592                 /* restart rx engine */
2593                 nv_start_rx(dev);
2594                 nv_start_tx(dev);
2595                 spin_unlock(&np->lock);
2596                 netif_tx_unlock_bh(dev);
2597                 nv_enable_irq(dev);
2598         }
2599         return 0;
2600 }
2601
2602 static void nv_copy_mac_to_hw(struct net_device *dev)
2603 {
2604         u8 __iomem *base = get_hwbase(dev);
2605         u32 mac[2];
2606
2607         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2608                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2609         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2610
2611         writel(mac[0], base + NvRegMacAddrA);
2612         writel(mac[1], base + NvRegMacAddrB);
2613 }
2614
2615 /*
2616  * nv_set_mac_address: dev->set_mac_address function
2617  * Called with rtnl_lock() held.
2618  */
2619 static int nv_set_mac_address(struct net_device *dev, void *addr)
2620 {
2621         struct fe_priv *np = netdev_priv(dev);
2622         struct sockaddr *macaddr = (struct sockaddr*)addr;
2623
2624         if (!is_valid_ether_addr(macaddr->sa_data))
2625                 return -EADDRNOTAVAIL;
2626
2627         /* synchronized against open : rtnl_lock() held by caller */
2628         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2629
2630         if (netif_running(dev)) {
2631                 netif_tx_lock_bh(dev);
2632                 spin_lock_irq(&np->lock);
2633
2634                 /* stop rx engine */
2635                 nv_stop_rx(dev);
2636
2637                 /* set mac address */
2638                 nv_copy_mac_to_hw(dev);
2639
2640                 /* restart rx engine */
2641                 nv_start_rx(dev);
2642                 spin_unlock_irq(&np->lock);
2643                 netif_tx_unlock_bh(dev);
2644         } else {
2645                 nv_copy_mac_to_hw(dev);
2646         }
2647         return 0;
2648 }
2649
2650 /*
2651  * nv_set_multicast: dev->set_multicast function
2652  * Called with netif_tx_lock held.
2653  */
2654 static void nv_set_multicast(struct net_device *dev)
2655 {
2656         struct fe_priv *np = netdev_priv(dev);
2657         u8 __iomem *base = get_hwbase(dev);
2658         u32 addr[2];
2659         u32 mask[2];
2660         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2661
2662         memset(addr, 0, sizeof(addr));
2663         memset(mask, 0, sizeof(mask));
2664
2665         if (dev->flags & IFF_PROMISC) {
2666                 pff |= NVREG_PFF_PROMISC;
2667         } else {
2668                 pff |= NVREG_PFF_MYADDR;
2669
2670                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
2671                         u32 alwaysOff[2];
2672                         u32 alwaysOn[2];
2673
2674                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2675                         if (dev->flags & IFF_ALLMULTI) {
2676                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2677                         } else {
2678                                 struct dev_mc_list *walk;
2679
2680                                 walk = dev->mc_list;
2681                                 while (walk != NULL) {
2682                                         u32 a, b;
2683                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
2684                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
2685                                         alwaysOn[0] &= a;
2686                                         alwaysOff[0] &= ~a;
2687                                         alwaysOn[1] &= b;
2688                                         alwaysOff[1] &= ~b;
2689                                         walk = walk->next;
2690                                 }
2691                         }
2692                         addr[0] = alwaysOn[0];
2693                         addr[1] = alwaysOn[1];
2694                         mask[0] = alwaysOn[0] | alwaysOff[0];
2695                         mask[1] = alwaysOn[1] | alwaysOff[1];
2696                 }
2697         }
2698         addr[0] |= NVREG_MCASTADDRA_FORCE;
2699         pff |= NVREG_PFF_ALWAYS;
2700         spin_lock_irq(&np->lock);
2701         nv_stop_rx(dev);
2702         writel(addr[0], base + NvRegMulticastAddrA);
2703         writel(addr[1], base + NvRegMulticastAddrB);
2704         writel(mask[0], base + NvRegMulticastMaskA);
2705         writel(mask[1], base + NvRegMulticastMaskB);
2706         writel(pff, base + NvRegPacketFilterFlags);
2707         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
2708                 dev->name);
2709         nv_start_rx(dev);
2710         spin_unlock_irq(&np->lock);
2711 }
2712
2713 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2714 {
2715         struct fe_priv *np = netdev_priv(dev);
2716         u8 __iomem *base = get_hwbase(dev);
2717
2718         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2719
2720         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2721                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2722                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2723                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2724                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2725                 } else {
2726                         writel(pff, base + NvRegPacketFilterFlags);
2727                 }
2728         }
2729         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2730                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2731                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2732                         writel(NVREG_TX_PAUSEFRAME_ENABLE,  base + NvRegTxPauseFrame);
2733                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2734                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2735                 } else {
2736                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
2737                         writel(regmisc, base + NvRegMisc1);
2738                 }
2739         }
2740 }
2741
2742 /**
2743  * nv_update_linkspeed: Setup the MAC according to the link partner
2744  * @dev: Network device to be configured
2745  *
2746  * The function queries the PHY and checks if there is a link partner.
2747  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
2748  * set to 10 MBit HD.
2749  *
2750  * The function returns 0 if there is no link partner and 1 if there is
2751  * a good link partner.
2752  */
2753 static int nv_update_linkspeed(struct net_device *dev)
2754 {
2755         struct fe_priv *np = netdev_priv(dev);
2756         u8 __iomem *base = get_hwbase(dev);
2757         int adv = 0;
2758         int lpa = 0;
2759         int adv_lpa, adv_pause, lpa_pause;
2760         int newls = np->linkspeed;
2761         int newdup = np->duplex;
2762         int mii_status;
2763         int retval = 0;
2764         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2765
2766         /* BMSR_LSTATUS is latched, read it twice:
2767          * we want the current value.
2768          */
2769         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2770         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
2771
2772         if (!(mii_status & BMSR_LSTATUS)) {
2773                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
2774                                 dev->name);
2775                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2776                 newdup = 0;
2777                 retval = 0;
2778                 goto set_speed;
2779         }
2780
2781         if (np->autoneg == 0) {
2782                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
2783                                 dev->name, np->fixed_mode);
2784                 if (np->fixed_mode & LPA_100FULL) {
2785                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2786                         newdup = 1;
2787                 } else if (np->fixed_mode & LPA_100HALF) {
2788                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2789                         newdup = 0;
2790                 } else if (np->fixed_mode & LPA_10FULL) {
2791                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2792                         newdup = 1;
2793                 } else {
2794                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2795                         newdup = 0;
2796                 }
2797                 retval = 1;
2798                 goto set_speed;
2799         }
2800         /* check auto negotiation is complete */
2801         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
2802                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
2803                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2804                 newdup = 0;
2805                 retval = 0;
2806                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
2807                 goto set_speed;
2808         }
2809
2810         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2811         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
2812         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
2813                                 dev->name, adv, lpa);
2814
2815         retval = 1;
2816         if (np->gigabit == PHY_GIGABIT) {
2817                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
2818                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
2819
2820                 if ((control_1000 & ADVERTISE_1000FULL) &&
2821                         (status_1000 & LPA_1000FULL)) {
2822                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
2823                                 dev->name);
2824                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
2825                         newdup = 1;
2826                         goto set_speed;
2827                 }
2828         }
2829
2830         /* FIXME: handle parallel detection properly */
2831         adv_lpa = lpa & adv;
2832         if (adv_lpa & LPA_100FULL) {
2833                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2834                 newdup = 1;
2835         } else if (adv_lpa & LPA_100HALF) {
2836                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
2837                 newdup = 0;
2838         } else if (adv_lpa & LPA_10FULL) {
2839                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2840                 newdup = 1;
2841         } else if (adv_lpa & LPA_10HALF) {
2842                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2843                 newdup = 0;
2844         } else {
2845                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
2846                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2847                 newdup = 0;
2848         }
2849
2850 set_speed:
2851         if (np->duplex == newdup && np->linkspeed == newls)
2852                 return retval;
2853
2854         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
2855                         dev->name, np->linkspeed, np->duplex, newls, newdup);
2856
2857         np->duplex = newdup;
2858         np->linkspeed = newls;
2859
2860         if (np->gigabit == PHY_GIGABIT) {
2861                 phyreg = readl(base + NvRegRandomSeed);
2862                 phyreg &= ~(0x3FF00);
2863                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
2864                         phyreg |= NVREG_RNDSEED_FORCE3;
2865                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
2866                         phyreg |= NVREG_RNDSEED_FORCE2;
2867                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
2868                         phyreg |= NVREG_RNDSEED_FORCE;
2869                 writel(phyreg, base + NvRegRandomSeed);
2870         }
2871
2872         phyreg = readl(base + NvRegPhyInterface);
2873         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
2874         if (np->duplex == 0)
2875                 phyreg |= PHY_HALF;
2876         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
2877                 phyreg |= PHY_100;
2878         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2879                 phyreg |= PHY_1000;
2880         writel(phyreg, base + NvRegPhyInterface);
2881
2882         if (phyreg & PHY_RGMII) {
2883                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2884                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2885                 else
2886                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2887         } else {
2888                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2889         }
2890         writel(txreg, base + NvRegTxDeferral);
2891
2892         if (np->desc_ver == DESC_VER_1) {
2893                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
2894         } else {
2895                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2896                         txreg = NVREG_TX_WM_DESC2_3_1000;
2897                 else
2898                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
2899         }
2900         writel(txreg, base + NvRegTxWatermark);
2901
2902         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2903                 base + NvRegMisc1);
2904         pci_push(base);
2905         writel(np->linkspeed, base + NvRegLinkSpeed);
2906         pci_push(base);
2907
2908         pause_flags = 0;
2909         /* setup pause frame */
2910         if (np->duplex != 0) {
2911                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
2912                         adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
2913                         lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
2914
2915                         switch (adv_pause) {
2916                         case ADVERTISE_PAUSE_CAP:
2917                                 if (lpa_pause & LPA_PAUSE_CAP) {
2918                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2919                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2920                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2921                                 }
2922                                 break;
2923                         case ADVERTISE_PAUSE_ASYM:
2924                                 if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
2925                                 {
2926                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2927                                 }
2928                                 break;
2929                         case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
2930                                 if (lpa_pause & LPA_PAUSE_CAP)
2931                                 {
2932                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
2933                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
2934                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2935                                 }
2936                                 if (lpa_pause == LPA_PAUSE_ASYM)
2937                                 {
2938                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2939                                 }
2940                                 break;
2941                         }
2942                 } else {
2943                         pause_flags = np->pause_flags;
2944                 }
2945         }
2946         nv_update_pause(dev, pause_flags);
2947
2948         return retval;
2949 }
2950
2951 static void nv_linkchange(struct net_device *dev)
2952 {
2953         if (nv_update_linkspeed(dev)) {
2954                 if (!netif_carrier_ok(dev)) {
2955                         netif_carrier_on(dev);
2956                         printk(KERN_INFO "%s: link up.\n", dev->name);
2957                         nv_start_rx(dev);
2958                 }
2959         } else {
2960                 if (netif_carrier_ok(dev)) {
2961                         netif_carrier_off(dev);
2962                         printk(KERN_INFO "%s: link down.\n", dev->name);
2963                         nv_stop_rx(dev);
2964                 }
2965         }
2966 }
2967
2968 static void nv_link_irq(struct net_device *dev)
2969 {
2970         u8 __iomem *base = get_hwbase(dev);
2971         u32 miistat;
2972
2973         miistat = readl(base + NvRegMIIStatus);
2974         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2975         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
2976
2977         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
2978                 nv_linkchange(dev);
2979         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
2980 }
2981
2982 static irqreturn_t nv_nic_irq(int foo, void *data)
2983 {
2984         struct net_device *dev = (struct net_device *) data;
2985         struct fe_priv *np = netdev_priv(dev);
2986         u8 __iomem *base = get_hwbase(dev);
2987         u32 events;
2988         int i;
2989
2990         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
2991
2992         for (i=0; ; i++) {
2993                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
2994                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2995                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2996                 } else {
2997                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2998                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
2999                 }
3000                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3001                 if (!(events & np->irqmask))
3002                         break;
3003
3004                 spin_lock(&np->lock);
3005                 nv_tx_done(dev);
3006                 spin_unlock(&np->lock);
3007
3008 #ifdef CONFIG_FORCEDETH_NAPI
3009                 if (events & NVREG_IRQ_RX_ALL) {
3010                         netif_rx_schedule(dev, &np->napi);
3011
3012                         /* Disable furthur receive irq's */
3013                         spin_lock(&np->lock);
3014                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3015
3016                         if (np->msi_flags & NV_MSI_X_ENABLED)
3017                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3018                         else
3019                                 writel(np->irqmask, base + NvRegIrqMask);
3020                         spin_unlock(&np->lock);
3021                 }
3022 #else
3023                 if (nv_rx_process(dev, RX_WORK_PER_LOOP)) {
3024                         if (unlikely(nv_alloc_rx(dev))) {
3025                                 spin_lock(&np->lock);
3026                                 if (!np->in_shutdown)
3027                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3028                                 spin_unlock(&np->lock);
3029                         }
3030                 }
3031 #endif
3032                 if (unlikely(events & NVREG_IRQ_LINK)) {
3033                         spin_lock(&np->lock);
3034                         nv_link_irq(dev);
3035                         spin_unlock(&np->lock);
3036                 }
3037                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3038                         spin_lock(&np->lock);
3039                         nv_linkchange(dev);
3040                         spin_unlock(&np->lock);
3041                         np->link_timeout = jiffies + LINK_TIMEOUT;
3042                 }
3043                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3044                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3045                                                 dev->name, events);
3046                 }
3047                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3048                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3049                                                 dev->name, events);
3050                 }
3051                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3052                         spin_lock(&np->lock);
3053                         /* disable interrupts on the nic */
3054                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3055                                 writel(0, base + NvRegIrqMask);
3056                         else
3057                                 writel(np->irqmask, base + NvRegIrqMask);
3058                         pci_push(base);
3059
3060                         if (!np->in_shutdown) {
3061                                 np->nic_poll_irq = np->irqmask;
3062                                 np->recover_error = 1;
3063                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3064                         }
3065                         spin_unlock(&np->lock);
3066                         break;
3067                 }
3068                 if (unlikely(i > max_interrupt_work)) {
3069                         spin_lock(&np->lock);
3070                         /* disable interrupts on the nic */
3071                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3072                                 writel(0, base + NvRegIrqMask);
3073                         else
3074                                 writel(np->irqmask, base + NvRegIrqMask);
3075                         pci_push(base);
3076
3077                         if (!np->in_shutdown) {
3078                                 np->nic_poll_irq = np->irqmask;
3079                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3080                         }
3081                         spin_unlock(&np->lock);
3082                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3083                         break;
3084                 }
3085
3086         }
3087         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
3088
3089         return IRQ_RETVAL(i);
3090 }
3091
3092 /**
3093  * All _optimized functions are used to help increase performance
3094  * (reduce CPU and increase throughput). They use descripter version 3,
3095  * compiler directives, and reduce memory accesses.
3096  */
3097 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3098 {
3099         struct net_device *dev = (struct net_device *) data;
3100         struct fe_priv *np = netdev_priv(dev);
3101         u8 __iomem *base = get_hwbase(dev);
3102         u32 events;
3103         int i;
3104
3105         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
3106
3107         for (i=0; ; i++) {
3108                 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3109                         events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3110                         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3111                 } else {
3112                         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3113                         writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3114                 }
3115                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3116                 if (!(events & np->irqmask))
3117                         break;
3118
3119                 spin_lock(&np->lock);
3120                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3121                 spin_unlock(&np->lock);
3122
3123 #ifdef CONFIG_FORCEDETH_NAPI
3124                 if (events & NVREG_IRQ_RX_ALL) {
3125                         netif_rx_schedule(dev, &np->napi);
3126
3127                         /* Disable furthur receive irq's */
3128                         spin_lock(&np->lock);
3129                         np->irqmask &= ~NVREG_IRQ_RX_ALL;
3130
3131                         if (np->msi_flags & NV_MSI_X_ENABLED)
3132                                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3133                         else
3134                                 writel(np->irqmask, base + NvRegIrqMask);
3135                         spin_unlock(&np->lock);
3136                 }
3137 #else
3138                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3139                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3140                                 spin_lock(&np->lock);
3141                                 if (!np->in_shutdown)
3142                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3143                                 spin_unlock(&np->lock);
3144                         }
3145                 }
3146 #endif
3147                 if (unlikely(events & NVREG_IRQ_LINK)) {
3148                         spin_lock(&np->lock);
3149                         nv_link_irq(dev);
3150                         spin_unlock(&np->lock);
3151                 }
3152                 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3153                         spin_lock(&np->lock);
3154                         nv_linkchange(dev);
3155                         spin_unlock(&np->lock);
3156                         np->link_timeout = jiffies + LINK_TIMEOUT;
3157                 }
3158                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3159                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3160                                                 dev->name, events);
3161                 }
3162                 if (unlikely(events & (NVREG_IRQ_UNKNOWN))) {
3163                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3164                                                 dev->name, events);
3165                 }
3166                 if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) {
3167                         spin_lock(&np->lock);
3168                         /* disable interrupts on the nic */
3169                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3170                                 writel(0, base + NvRegIrqMask);
3171                         else
3172                                 writel(np->irqmask, base + NvRegIrqMask);
3173                         pci_push(base);
3174
3175                         if (!np->in_shutdown) {
3176                                 np->nic_poll_irq = np->irqmask;
3177                                 np->recover_error = 1;
3178                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3179                         }
3180                         spin_unlock(&np->lock);
3181                         break;
3182                 }
3183
3184                 if (unlikely(i > max_interrupt_work)) {
3185                         spin_lock(&np->lock);
3186                         /* disable interrupts on the nic */
3187                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3188                                 writel(0, base + NvRegIrqMask);
3189                         else
3190                                 writel(np->irqmask, base + NvRegIrqMask);
3191                         pci_push(base);
3192
3193                         if (!np->in_shutdown) {
3194                                 np->nic_poll_irq = np->irqmask;
3195                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3196                         }
3197                         spin_unlock(&np->lock);
3198                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
3199                         break;
3200                 }
3201
3202         }
3203         dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
3204
3205         return IRQ_RETVAL(i);
3206 }
3207
3208 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3209 {
3210         struct net_device *dev = (struct net_device *) data;
3211         struct fe_priv *np = netdev_priv(dev);
3212         u8 __iomem *base = get_hwbase(dev);
3213         u32 events;
3214         int i;
3215         unsigned long flags;
3216
3217         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
3218
3219         for (i=0; ; i++) {
3220                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3221                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
3222                 dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
3223                 if (!(events & np->irqmask))
3224                         break;
3225
3226                 spin_lock_irqsave(&np->lock, flags);
3227                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3228                 spin_unlock_irqrestore(&np->lock, flags);
3229
3230                 if (unlikely(events & (NVREG_IRQ_TX_ERR))) {
3231                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
3232                                                 dev->name, events);
3233                 }
3234                 if (unlikely(i > max_interrupt_work)) {
3235                         spin_lock_irqsave(&np->lock, flags);
3236                         /* disable interrupts on the nic */
3237                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3238                         pci_push(base);
3239
3240                         if (!np->in_shutdown) {
3241                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3242                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3243                         }
3244                         spin_unlock_irqrestore(&np->lock, flags);
3245                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
3246                         break;
3247                 }
3248
3249         }
3250         dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
3251
3252         return IRQ_RETVAL(i);
3253 }
3254
3255 #ifdef CONFIG_FORCEDETH_NAPI
3256 static int nv_napi_poll(struct napi_struct *napi, int budget)
3257 {
3258         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3259         struct net_device *dev = np->dev;
3260         u8 __iomem *base = get_hwbase(dev);
3261         unsigned long flags;
3262         int pkts, retcode;
3263
3264         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
3265                 pkts = nv_rx_process(dev, budget);
3266                 retcode = nv_alloc_rx(dev);
3267         } else {
3268                 pkts = nv_rx_process_optimized(dev, budget);
3269                 retcode = nv_alloc_rx_optimized(dev);
3270         }
3271
3272         if (retcode) {
3273                 spin_lock_irqsave(&np->lock, flags);
3274                 if (!np->in_shutdown)
3275                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3276                 spin_unlock_irqrestore(&np->lock, flags);
3277         }
3278
3279         if (pkts < budget) {
3280                 /* re-enable receive interrupts */
3281                 spin_lock_irqsave(&np->lock, flags);
3282
3283                 __netif_rx_complete(dev, napi);
3284
3285                 np->irqmask |= NVREG_IRQ_RX_ALL;
3286                 if (np->msi_flags & NV_MSI_X_ENABLED)
3287                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3288                 else
3289                         writel(np->irqmask, base + NvRegIrqMask);
3290
3291                 spin_unlock_irqrestore(&np->lock, flags);
3292         }
3293         return pkts;
3294 }
3295 #endif
3296
3297 #ifdef CONFIG_FORCEDETH_NAPI
3298 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3299 {
3300         struct net_device *dev = (struct net_device *) data;
3301         struct fe_priv *np = netdev_priv(dev);
3302         u8 __iomem *base = get_hwbase(dev);
3303         u32 events;
3304
3305         events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3306         writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3307
3308         if (events) {
3309                 netif_rx_schedule(dev, &np->napi);
3310                 /* disable receive interrupts on the nic */
3311                 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3312                 pci_push(base);
3313         }
3314         return IRQ_HANDLED;
3315 }
3316 #else
3317 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3318 {
3319         struct net_device *dev = (struct net_device *) data;
3320         struct fe_priv *np = netdev_priv(dev);
3321         u8 __iomem *base = get_hwbase(dev);
3322         u32 events;
3323         int i;
3324         unsigned long flags;
3325
3326         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
3327
3328         for (i=0; ; i++) {
3329                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3330                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
3331                 dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
3332                 if (!(events & np->irqmask))
3333                         break;
3334
3335                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3336                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3337                                 spin_lock_irqsave(&np->lock, flags);
3338                                 if (!np->in_shutdown)
3339                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3340                                 spin_unlock_irqrestore(&np->lock, flags);
3341                         }
3342                 }
3343
3344                 if (unlikely(i > max_interrupt_work)) {
3345                         spin_lock_irqsave(&np->lock, flags);
3346                         /* disable interrupts on the nic */
3347                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3348                         pci_push(base);
3349
3350                         if (!np->in_shutdown) {
3351                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3352                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3353                         }
3354                         spin_unlock_irqrestore(&np->lock, flags);
3355                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
3356                         break;
3357                 }
3358         }
3359         dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
3360
3361         return IRQ_RETVAL(i);
3362 }
3363 #endif
3364
3365 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3366 {
3367         struct net_device *dev = (struct net_device *) data;
3368         struct fe_priv *np = netdev_priv(dev);
3369         u8 __iomem *base = get_hwbase(dev);
3370         u32 events;
3371         int i;
3372         unsigned long flags;
3373
3374         dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
3375
3376         for (i=0; ; i++) {
3377                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3378                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
3379                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3380                 if (!(events & np->irqmask))
3381                         break;
3382
3383                 /* check tx in case we reached max loop limit in tx isr */
3384                 spin_lock_irqsave(&np->lock, flags);
3385                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3386                 spin_unlock_irqrestore(&np->lock, flags);
3387
3388                 if (events & NVREG_IRQ_LINK) {
3389                         spin_lock_irqsave(&np->lock, flags);
3390                         nv_link_irq(dev);
3391                         spin_unlock_irqrestore(&np->lock, flags);
3392                 }
3393                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3394                         spin_lock_irqsave(&np->lock, flags);
3395                         nv_linkchange(dev);
3396                         spin_unlock_irqrestore(&np->lock, flags);
3397                         np->link_timeout = jiffies + LINK_TIMEOUT;
3398                 }
3399                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3400                         spin_lock_irq(&np->lock);
3401                         /* disable interrupts on the nic */
3402                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3403                         pci_push(base);
3404
3405                         if (!np->in_shutdown) {
3406                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3407                                 np->recover_error = 1;
3408                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3409                         }
3410                         spin_unlock_irq(&np->lock);
3411                         break;
3412                 }
3413                 if (events & (NVREG_IRQ_UNKNOWN)) {
3414                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
3415                                                 dev->name, events);
3416                 }
3417                 if (unlikely(i > max_interrupt_work)) {
3418                         spin_lock_irqsave(&np->lock, flags);
3419                         /* disable interrupts on the nic */
3420                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3421                         pci_push(base);
3422
3423                         if (!np->in_shutdown) {
3424                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3425                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3426                         }
3427                         spin_unlock_irqrestore(&np->lock, flags);
3428                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
3429                         break;
3430                 }
3431
3432         }
3433         dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
3434
3435         return IRQ_RETVAL(i);
3436 }
3437
3438 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3439 {
3440         struct net_device *dev = (struct net_device *) data;
3441         struct fe_priv *np = netdev_priv(dev);
3442         u8 __iomem *base = get_hwbase(dev);
3443         u32 events;
3444
3445         dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
3446
3447         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3448                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3449                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3450         } else {
3451                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3452                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3453         }
3454         pci_push(base);
3455         dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
3456         if (!(events & NVREG_IRQ_TIMER))
3457                 return IRQ_RETVAL(0);
3458
3459         spin_lock(&np->lock);
3460         np->intr_test = 1;
3461         spin_unlock(&np->lock);
3462
3463         dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
3464
3465         return IRQ_RETVAL(1);
3466 }
3467
3468 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3469 {
3470         u8 __iomem *base = get_hwbase(dev);
3471         int i;
3472         u32 msixmap = 0;
3473
3474         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3475          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3476          * the remaining 8 interrupts.
3477          */
3478         for (i = 0; i < 8; i++) {
3479                 if ((irqmask >> i) & 0x1) {
3480                         msixmap |= vector << (i << 2);
3481                 }
3482         }
3483         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3484
3485         msixmap = 0;
3486         for (i = 0; i < 8; i++) {
3487                 if ((irqmask >> (i + 8)) & 0x1) {
3488                         msixmap |= vector << (i << 2);
3489                 }
3490         }
3491         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3492 }
3493
3494 static int nv_request_irq(struct net_device *dev, int intr_test)
3495 {
3496         struct fe_priv *np = get_nvpriv(dev);
3497         u8 __iomem *base = get_hwbase(dev);
3498         int ret = 1;
3499         int i;
3500         irqreturn_t (*handler)(int foo, void *data);
3501
3502         if (intr_test) {
3503                 handler = nv_nic_irq_test;
3504         } else {
3505                 if (np->desc_ver == DESC_VER_3)
3506                         handler = nv_nic_irq_optimized;
3507                 else
3508                         handler = nv_nic_irq;
3509         }
3510
3511         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3512                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3513                         np->msi_x_entry[i].entry = i;
3514                 }
3515                 if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
3516                         np->msi_flags |= NV_MSI_X_ENABLED;
3517                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3518                                 /* Request irq for rx handling */
3519                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, &nv_nic_irq_rx, IRQF_SHARED, dev->name, dev) != 0) {
3520                                         printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
3521                                         pci_disable_msix(np->pci_dev);
3522                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3523                                         goto out_err;
3524                                 }
3525                                 /* Request irq for tx handling */
3526                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, &nv_nic_irq_tx, IRQF_SHARED, dev->name, dev) != 0) {
3527                                         printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
3528                                         pci_disable_msix(np->pci_dev);
3529                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3530                                         goto out_free_rx;
3531                                 }
3532                                 /* Request irq for link and timer handling */
3533                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector, &nv_nic_irq_other, IRQF_SHARED, dev->name, dev) != 0) {
3534                                         printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
3535                                         pci_disable_msix(np->pci_dev);
3536                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3537                                         goto out_free_tx;
3538                                 }
3539                                 /* map interrupts to their respective vector */
3540                                 writel(0, base + NvRegMSIXMap0);
3541                                 writel(0, base + NvRegMSIXMap1);
3542                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3543                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3544                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3545                         } else {
3546                                 /* Request irq for all interrupts */
3547                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3548                                         printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3549                                         pci_disable_msix(np->pci_dev);
3550                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3551                                         goto out_err;
3552                                 }
3553
3554                                 /* map interrupts to vector 0 */
3555                                 writel(0, base + NvRegMSIXMap0);
3556                                 writel(0, base + NvRegMSIXMap1);
3557                         }
3558                 }
3559         }
3560         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3561                 if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
3562                         np->msi_flags |= NV_MSI_ENABLED;
3563                         dev->irq = np->pci_dev->irq;
3564                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3565                                 printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
3566                                 pci_disable_msi(np->pci_dev);
3567                                 np->msi_flags &= ~NV_MSI_ENABLED;
3568                                 dev->irq = np->pci_dev->irq;
3569                                 goto out_err;
3570                         }
3571
3572                         /* map interrupts to vector 0 */
3573                         writel(0, base + NvRegMSIMap0);
3574                         writel(0, base + NvRegMSIMap1);
3575                         /* enable msi vector 0 */
3576                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3577                 }
3578         }
3579         if (ret != 0) {
3580                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3581                         goto out_err;
3582
3583         }
3584
3585         return 0;
3586 out_free_tx:
3587         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3588 out_free_rx:
3589         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3590 out_err:
3591         return 1;
3592 }
3593
3594 static void nv_free_irq(struct net_device *dev)
3595 {
3596         struct fe_priv *np = get_nvpriv(dev);
3597         int i;
3598
3599         if (np->msi_flags & NV_MSI_X_ENABLED) {
3600                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
3601                         free_irq(np->msi_x_entry[i].vector, dev);
3602                 }
3603                 pci_disable_msix(np->pci_dev);
3604                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3605         } else {
3606                 free_irq(np->pci_dev->irq, dev);
3607                 if (np->msi_flags & NV_MSI_ENABLED) {
3608                         pci_disable_msi(np->pci_dev);
3609                         np->msi_flags &= ~NV_MSI_ENABLED;
3610                 }
3611         }
3612 }
3613
3614 static void nv_do_nic_poll(unsigned long data)
3615 {
3616         struct net_device *dev = (struct net_device *) data;
3617         struct fe_priv *np = netdev_priv(dev);
3618         u8 __iomem *base = get_hwbase(dev);
3619         u32 mask = 0;
3620
3621         /*
3622          * First disable irq(s) and then
3623          * reenable interrupts on the nic, we have to do this before calling
3624          * nv_nic_irq because that may decide to do otherwise
3625          */
3626
3627         if (!using_multi_irqs(dev)) {
3628                 if (np->msi_flags & NV_MSI_X_ENABLED)
3629                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3630                 else
3631                         disable_irq_lockdep(np->pci_dev->irq);
3632                 mask = np->irqmask;
3633         } else {
3634                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3635                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3636                         mask |= NVREG_IRQ_RX_ALL;
3637                 }
3638                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3639                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3640                         mask |= NVREG_IRQ_TX_ALL;
3641                 }
3642                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3643                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3644                         mask |= NVREG_IRQ_OTHER;
3645                 }
3646         }
3647         np->nic_poll_irq = 0;
3648
3649         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3650
3651         if (np->recover_error) {
3652                 np->recover_error = 0;
3653                 printk(KERN_INFO "forcedeth: MAC in recoverable error state\n");
3654                 if (netif_running(dev)) {
3655                         netif_tx_lock_bh(dev);
3656                         spin_lock(&np->lock);
3657                         /* stop engines */
3658                         nv_stop_rx(dev);
3659                         nv_stop_tx(dev);
3660                         nv_txrx_reset(dev);
3661                         /* drain rx queue */
3662                         nv_drain_rx(dev);
3663                         nv_drain_tx(dev);
3664                         /* reinit driver view of the rx queue */
3665                         set_bufsize(dev);
3666                         if (nv_init_ring(dev)) {
3667                                 if (!np->in_shutdown)
3668                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3669                         }
3670                         /* reinit nic view of the rx queue */
3671                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3672                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3673                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3674                                 base + NvRegRingSizes);
3675                         pci_push(base);
3676                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3677                         pci_push(base);
3678
3679                         /* restart rx engine */
3680                         nv_start_rx(dev);
3681                         nv_start_tx(dev);
3682                         spin_unlock(&np->lock);
3683                         netif_tx_unlock_bh(dev);
3684                 }
3685         }
3686
3687
3688         writel(mask, base + NvRegIrqMask);
3689         pci_push(base);
3690
3691         if (!using_multi_irqs(dev)) {
3692                 if (np->desc_ver == DESC_VER_3)
3693                         nv_nic_irq_optimized(0, dev);
3694                 else
3695                         nv_nic_irq(0, dev);
3696                 if (np->msi_flags & NV_MSI_X_ENABLED)
3697                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3698                 else
3699                         enable_irq_lockdep(np->pci_dev->irq);
3700         } else {
3701                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3702                         nv_nic_irq_rx(0, dev);
3703                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3704                 }
3705                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3706                         nv_nic_irq_tx(0, dev);
3707                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3708                 }
3709                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3710                         nv_nic_irq_other(0, dev);
3711                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3712                 }
3713         }
3714 }
3715
3716 #ifdef CONFIG_NET_POLL_CONTROLLER
3717 static void nv_poll_controller(struct net_device *dev)
3718 {
3719         nv_do_nic_poll((unsigned long) dev);
3720 }
3721 #endif
3722
3723 static void nv_do_stats_poll(unsigned long data)
3724 {
3725         struct net_device *dev = (struct net_device *) data;
3726         struct fe_priv *np = netdev_priv(dev);
3727
3728         nv_get_hw_stats(dev);
3729
3730         if (!np->in_shutdown)
3731                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
3732 }
3733
3734 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3735 {
3736         struct fe_priv *np = netdev_priv(dev);
3737         strcpy(info->driver, DRV_NAME);
3738         strcpy(info->version, FORCEDETH_VERSION);
3739         strcpy(info->bus_info, pci_name(np->pci_dev));
3740 }
3741
3742 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3743 {
3744         struct fe_priv *np = netdev_priv(dev);
3745         wolinfo->supported = WAKE_MAGIC;
3746
3747         spin_lock_irq(&np->lock);
3748         if (np->wolenabled)
3749                 wolinfo->wolopts = WAKE_MAGIC;
3750         spin_unlock_irq(&np->lock);
3751 }
3752
3753 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3754 {
3755         struct fe_priv *np = netdev_priv(dev);
3756         u8 __iomem *base = get_hwbase(dev);
3757         u32 flags = 0;
3758
3759         if (wolinfo->wolopts == 0) {
3760                 np->wolenabled = 0;
3761         } else if (wolinfo->wolopts & WAKE_MAGIC) {
3762                 np->wolenabled = 1;
3763                 flags = NVREG_WAKEUPFLAGS_ENABLE;
3764         }
3765         if (netif_running(dev)) {
3766                 spin_lock_irq(&np->lock);
3767                 writel(flags, base + NvRegWakeUpFlags);
3768                 spin_unlock_irq(&np->lock);
3769         }
3770         return 0;
3771 }
3772
3773 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3774 {
3775         struct fe_priv *np = netdev_priv(dev);
3776         int adv;
3777
3778         spin_lock_irq(&np->lock);
3779         ecmd->port = PORT_MII;
3780         if (!netif_running(dev)) {
3781                 /* We do not track link speed / duplex setting if the
3782                  * interface is disabled. Force a link check */
3783                 if (nv_update_linkspeed(dev)) {
3784                         if (!netif_carrier_ok(dev))
3785                                 netif_carrier_on(dev);
3786                 } else {
3787                         if (netif_carrier_ok(dev))
3788                                 netif_carrier_off(dev);
3789                 }
3790         }
3791
3792         if (netif_carrier_ok(dev)) {
3793                 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3794                 case NVREG_LINKSPEED_10:
3795                         ecmd->speed = SPEED_10;
3796                         break;
3797                 case NVREG_LINKSPEED_100:
3798                         ecmd->speed = SPEED_100;
3799                         break;
3800                 case NVREG_LINKSPEED_1000:
3801                         ecmd->speed = SPEED_1000;
3802                         break;
3803                 }
3804                 ecmd->duplex = DUPLEX_HALF;
3805                 if (np->duplex)
3806                         ecmd->duplex = DUPLEX_FULL;
3807         } else {
3808                 ecmd->speed = -1;
3809                 ecmd->duplex = -1;
3810         }
3811
3812         ecmd->autoneg = np->autoneg;
3813
3814         ecmd->advertising = ADVERTISED_MII;
3815         if (np->autoneg) {
3816                 ecmd->advertising |= ADVERTISED_Autoneg;
3817                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3818                 if (adv & ADVERTISE_10HALF)
3819                         ecmd->advertising |= ADVERTISED_10baseT_Half;
3820                 if (adv & ADVERTISE_10FULL)
3821                         ecmd->advertising |= ADVERTISED_10baseT_Full;
3822                 if (adv & ADVERTISE_100HALF)
3823                         ecmd->advertising |= ADVERTISED_100baseT_Half;
3824                 if (adv & ADVERTISE_100FULL)
3825                         ecmd->advertising |= ADVERTISED_100baseT_Full;
3826                 if (np->gigabit == PHY_GIGABIT) {
3827                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3828                         if (adv & ADVERTISE_1000FULL)
3829                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3830                 }
3831         }
3832         ecmd->supported = (SUPPORTED_Autoneg |
3833                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
3834                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
3835                 SUPPORTED_MII);
3836         if (np->gigabit == PHY_GIGABIT)
3837                 ecmd->supported |= SUPPORTED_1000baseT_Full;
3838
3839         ecmd->phy_address = np->phyaddr;
3840         ecmd->transceiver = XCVR_EXTERNAL;
3841
3842         /* ignore maxtxpkt, maxrxpkt for now */
3843         spin_unlock_irq(&np->lock);
3844         return 0;
3845 }
3846
3847 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3848 {
3849         struct fe_priv *np = netdev_priv(dev);
3850
3851         if (ecmd->port != PORT_MII)
3852                 return -EINVAL;
3853         if (ecmd->transceiver != XCVR_EXTERNAL)
3854                 return -EINVAL;
3855         if (ecmd->phy_address != np->phyaddr) {
3856                 /* TODO: support switching between multiple phys. Should be
3857                  * trivial, but not enabled due to lack of test hardware. */
3858                 return -EINVAL;
3859         }
3860         if (ecmd->autoneg == AUTONEG_ENABLE) {
3861                 u32 mask;
3862
3863                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3864                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
3865                 if (np->gigabit == PHY_GIGABIT)
3866                         mask |= ADVERTISED_1000baseT_Full;
3867
3868                 if ((ecmd->advertising & mask) == 0)
3869                         return -EINVAL;
3870
3871         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
3872                 /* Note: autonegotiation disable, speed 1000 intentionally
3873                  * forbidden - noone should need that. */
3874
3875                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
3876                         return -EINVAL;
3877                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
3878                         return -EINVAL;
3879         } else {
3880                 return -EINVAL;
3881         }
3882
3883         netif_carrier_off(dev);
3884         if (netif_running(dev)) {
3885                 nv_disable_irq(dev);
3886                 netif_tx_lock_bh(dev);
3887                 spin_lock(&np->lock);
3888                 /* stop engines */
3889                 nv_stop_rx(dev);
3890                 nv_stop_tx(dev);
3891                 spin_unlock(&np->lock);
3892                 netif_tx_unlock_bh(dev);
3893         }
3894
3895         if (ecmd->autoneg == AUTONEG_ENABLE) {
3896                 int adv, bmcr;
3897
3898                 np->autoneg = 1;
3899
3900                 /* advertise only what has been requested */
3901                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3902                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3903                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
3904                         adv |= ADVERTISE_10HALF;
3905                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
3906                         adv |= ADVERTISE_10FULL;
3907                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
3908                         adv |= ADVERTISE_100HALF;
3909                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
3910                         adv |= ADVERTISE_100FULL;
3911                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisments but disable tx pause */
3912                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3913                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3914                         adv |=  ADVERTISE_PAUSE_ASYM;
3915                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3916
3917                 if (np->gigabit == PHY_GIGABIT) {
3918                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3919                         adv &= ~ADVERTISE_1000FULL;
3920                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
3921                                 adv |= ADVERTISE_1000FULL;
3922                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3923                 }
3924
3925                 if (netif_running(dev))
3926                         printk(KERN_INFO "%s: link down.\n", dev->name);
3927                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3928                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
3929                         bmcr |= BMCR_ANENABLE;
3930                         /* reset the phy in order for settings to stick,
3931                          * and cause autoneg to start */
3932                         if (phy_reset(dev, bmcr)) {
3933                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3934                                 return -EINVAL;
3935                         }
3936                 } else {
3937                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
3938                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3939                 }
3940         } else {
3941                 int adv, bmcr;
3942
3943                 np->autoneg = 0;
3944
3945                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3946                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3947                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
3948                         adv |= ADVERTISE_10HALF;
3949                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
3950                         adv |= ADVERTISE_10FULL;
3951                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
3952                         adv |= ADVERTISE_100HALF;
3953                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
3954                         adv |= ADVERTISE_100FULL;
3955                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
3956                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisments but disable tx pause */
3957                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3958                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3959                 }
3960                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
3961                         adv |=  ADVERTISE_PAUSE_ASYM;
3962                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3963                 }
3964                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
3965                 np->fixed_mode = adv;
3966
3967                 if (np->gigabit == PHY_GIGABIT) {
3968                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3969                         adv &= ~ADVERTISE_1000FULL;
3970                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
3971                 }
3972
3973                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3974                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
3975                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
3976                         bmcr |= BMCR_FULLDPLX;
3977                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
3978                         bmcr |= BMCR_SPEED100;
3979                 if (np->phy_oui == PHY_OUI_MARVELL) {
3980                         /* reset the phy in order for forced mode settings to stick */
3981                         if (phy_reset(dev, bmcr)) {
3982                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
3983                                 return -EINVAL;
3984                         }
3985                 } else {
3986                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
3987                         if (netif_running(dev)) {
3988                                 /* Wait a bit and then reconfigure the nic. */
3989                                 udelay(10);
3990                                 nv_linkchange(dev);
3991                         }
3992                 }
3993         }
3994
3995         if (netif_running(dev)) {
3996                 nv_start_rx(dev);
3997                 nv_start_tx(dev);
3998                 nv_enable_irq(dev);
3999         }
4000
4001         return 0;
4002 }
4003
4004 #define FORCEDETH_REGS_VER      1
4005
4006 static int nv_get_regs_len(struct net_device *dev)
4007 {
4008         struct fe_priv *np = netdev_priv(dev);
4009         return np->register_size;
4010 }
4011
4012 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4013 {
4014         struct fe_priv *np = netdev_priv(dev);
4015         u8 __iomem *base = get_hwbase(dev);
4016         u32 *rbuf = buf;
4017         int i;
4018
4019         regs->version = FORCEDETH_REGS_VER;
4020         spin_lock_irq(&np->lock);
4021         for (i = 0;i <= np->register_size/sizeof(u32); i++)
4022                 rbuf[i] = readl(base + i*sizeof(u32));
4023         spin_unlock_irq(&np->lock);
4024 }
4025
4026 static int nv_nway_reset(struct net_device *dev)
4027 {
4028         struct fe_priv *np = netdev_priv(dev);
4029         int ret;
4030
4031         if (np->autoneg) {
4032                 int bmcr;
4033
4034                 netif_carrier_off(dev);
4035                 if (netif_running(dev)) {
4036                         nv_disable_irq(dev);
4037                         netif_tx_lock_bh(dev);
4038                         spin_lock(&np->lock);
4039                         /* stop engines */
4040                         nv_stop_rx(dev);
4041                         nv_stop_tx(dev);
4042                         spin_unlock(&np->lock);
4043                         netif_tx_unlock_bh(dev);
4044                         printk(KERN_INFO "%s: link down.\n", dev->name);
4045                 }
4046
4047                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4048                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4049                         bmcr |= BMCR_ANENABLE;
4050                         /* reset the phy in order for settings to stick*/
4051                         if (phy_reset(dev, bmcr)) {
4052                                 printk(KERN_INFO "%s: phy reset failed\n", dev->name);
4053                                 return -EINVAL;
4054                         }
4055                 } else {
4056                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4057                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4058                 }
4059
4060                 if (netif_running(dev)) {
4061                         nv_start_rx(dev);
4062                         nv_start_tx(dev);
4063                         nv_enable_irq(dev);
4064                 }
4065                 ret = 0;
4066         } else {
4067                 ret = -EINVAL;
4068         }
4069
4070         return ret;
4071 }
4072
4073 static int nv_set_tso(struct net_device *dev, u32 value)
4074 {
4075         struct fe_priv *np = netdev_priv(dev);
4076
4077         if ((np->driver_data & DEV_HAS_CHECKSUM))
4078                 return ethtool_op_set_tso(dev, value);
4079         else
4080                 return -EOPNOTSUPP;
4081 }
4082
4083 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4084 {
4085         struct fe_priv *np = netdev_priv(dev);
4086
4087         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4088         ring->rx_mini_max_pending = 0;
4089         ring->rx_jumbo_max_pending = 0;
4090         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4091
4092         ring->rx_pending = np->rx_ring_size;
4093         ring->rx_mini_pending = 0;
4094         ring->rx_jumbo_pending = 0;
4095         ring->tx_pending = np->tx_ring_size;
4096 }
4097
4098 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4099 {
4100         struct fe_priv *np = netdev_priv(dev);
4101         u8 __iomem *base = get_hwbase(dev);
4102         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4103         dma_addr_t ring_addr;
4104
4105         if (ring->rx_pending < RX_RING_MIN ||
4106             ring->tx_pending < TX_RING_MIN ||
4107             ring->rx_mini_pending != 0 ||
4108             ring->rx_jumbo_pending != 0 ||
4109             (np->desc_ver == DESC_VER_1 &&
4110              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4111               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4112             (np->desc_ver != DESC_VER_1 &&
4113              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4114               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4115                 return -EINVAL;
4116         }
4117
4118         /* allocate new rings */
4119         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4120                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4121                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4122                                             &ring_addr);
4123         } else {
4124                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4125                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4126                                             &ring_addr);
4127         }
4128         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4129         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4130         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4131                 /* fall back to old rings */
4132                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4133                         if (rxtx_ring)
4134                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4135                                                     rxtx_ring, ring_addr);
4136                 } else {
4137                         if (rxtx_ring)
4138                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4139                                                     rxtx_ring, ring_addr);
4140                 }
4141                 if (rx_skbuff)
4142                         kfree(rx_skbuff);
4143                 if (tx_skbuff)
4144                         kfree(tx_skbuff);
4145                 goto exit;
4146         }
4147
4148         if (netif_running(dev)) {
4149                 nv_disable_irq(dev);
4150                 netif_tx_lock_bh(dev);
4151                 spin_lock(&np->lock);
4152                 /* stop engines */
4153                 nv_stop_rx(dev);
4154                 nv_stop_tx(dev);
4155                 nv_txrx_reset(dev);
4156                 /* drain queues */
4157                 nv_drain_rx(dev);
4158                 nv_drain_tx(dev);
4159                 /* delete queues */
4160                 free_rings(dev);
4161         }
4162
4163         /* set new values */
4164         np->rx_ring_size = ring->rx_pending;
4165         np->tx_ring_size = ring->tx_pending;
4166         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4167                 np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
4168                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4169         } else {
4170                 np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
4171                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4172         }
4173         np->rx_skb = (struct nv_skb_map*)rx_skbuff;
4174         np->tx_skb = (struct nv_skb_map*)tx_skbuff;
4175         np->ring_addr = ring_addr;
4176
4177         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4178         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4179
4180         if (netif_running(dev)) {
4181                 /* reinit driver view of the queues */
4182                 set_bufsize(dev);
4183                 if (nv_init_ring(dev)) {
4184                         if (!np->in_shutdown)
4185                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4186                 }
4187
4188                 /* reinit nic view of the queues */
4189                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4190                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4191                 writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4192                         base + NvRegRingSizes);
4193                 pci_push(base);
4194                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4195                 pci_push(base);
4196
4197                 /* restart engines */
4198                 nv_start_rx(dev);
4199                 nv_start_tx(dev);
4200                 spin_unlock(&np->lock);
4201                 netif_tx_unlock_bh(dev);
4202                 nv_enable_irq(dev);
4203         }
4204         return 0;
4205 exit:
4206         return -ENOMEM;
4207 }
4208
4209 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4210 {
4211         struct fe_priv *np = netdev_priv(dev);
4212
4213         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4214         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4215         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4216 }
4217
4218 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4219 {
4220         struct fe_priv *np = netdev_priv(dev);
4221         int adv, bmcr;
4222
4223         if ((!np->autoneg && np->duplex == 0) ||
4224             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4225                 printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
4226                        dev->name);
4227                 return -EINVAL;
4228         }
4229         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4230                 printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
4231                 return -EINVAL;
4232         }
4233
4234         netif_carrier_off(dev);
4235         if (netif_running(dev)) {
4236                 nv_disable_irq(dev);
4237                 netif_tx_lock_bh(dev);
4238                 spin_lock(&np->lock);
4239                 /* stop engines */
4240                 nv_stop_rx(dev);
4241                 nv_stop_tx(dev);
4242                 spin_unlock(&np->lock);
4243                 netif_tx_unlock_bh(dev);
4244         }
4245
4246         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4247         if (pause->rx_pause)
4248                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4249         if (pause->tx_pause)
4250                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4251
4252         if (np->autoneg && pause->autoneg) {
4253                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4254
4255                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4256                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4257                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisments but disable tx pause */
4258                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4259                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4260                         adv |=  ADVERTISE_PAUSE_ASYM;
4261                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4262
4263                 if (netif_running(dev))
4264                         printk(KERN_INFO "%s: link down.\n", dev->name);
4265                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4266                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4267                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4268         } else {
4269                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4270                 if (pause->rx_pause)
4271                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4272                 if (pause->tx_pause)
4273                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4274
4275                 if (!netif_running(dev))
4276                         nv_update_linkspeed(dev);
4277                 else
4278                         nv_update_pause(dev, np->pause_flags);
4279         }
4280
4281         if (netif_running(dev)) {
4282                 nv_start_rx(dev);
4283                 nv_start_tx(dev);
4284                 nv_enable_irq(dev);
4285         }
4286         return 0;
4287 }
4288
4289 static u32 nv_get_rx_csum(struct net_device *dev)
4290 {
4291         struct fe_priv *np = netdev_priv(dev);
4292         return (np->rx_csum) != 0;
4293 }
4294
4295 static int nv_set_rx_csum(struct net_device *dev, u32 data)
4296 {
4297         struct fe_priv *np = netdev_priv(dev);
4298         u8 __iomem *base = get_hwbase(dev);
4299         int retcode = 0;
4300
4301         if (np->driver_data & DEV_HAS_CHECKSUM) {
4302                 if (data) {
4303                         np->rx_csum = 1;
4304                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4305                 } else {
4306                         np->rx_csum = 0;
4307                         /* vlan is dependent on rx checksum offload */
4308                         if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE))
4309                                 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4310                 }
4311                 if (netif_running(dev)) {
4312                         spin_lock_irq(&np->lock);
4313                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4314                         spin_unlock_irq(&np->lock);
4315                 }
4316         } else {
4317                 return -EINVAL;
4318         }
4319
4320         return retcode;
4321 }
4322
4323 static int nv_set_tx_csum(struct net_device *dev, u32 data)
4324 {
4325         struct fe_priv *np = netdev_priv(dev);
4326
4327         if (np->driver_data & DEV_HAS_CHECKSUM)
4328                 return ethtool_op_set_tx_hw_csum(dev, data);
4329         else
4330                 return -EOPNOTSUPP;
4331 }
4332
4333 static int nv_set_sg(struct net_device *dev, u32 data)
4334 {
4335         struct fe_priv *np = netdev_priv(dev);
4336
4337         if (np->driver_data & DEV_HAS_CHECKSUM)
4338                 return ethtool_op_set_sg(dev, data);
4339         else
4340                 return -EOPNOTSUPP;
4341 }
4342
4343 static int nv_get_sset_count(struct net_device *dev, int sset)
4344 {
4345         struct fe_priv *np = netdev_priv(dev);
4346
4347         switch (sset) {
4348         case ETH_SS_TEST:
4349                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4350                         return NV_TEST_COUNT_EXTENDED;
4351                 else
4352                         return NV_TEST_COUNT_BASE;
4353         case ETH_SS_STATS:
4354                 if (np->driver_data & DEV_HAS_STATISTICS_V1)
4355                         return NV_DEV_STATISTICS_V1_COUNT;
4356                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4357                         return NV_DEV_STATISTICS_V2_COUNT;
4358                 else
4359                         return 0;
4360         default:
4361                 return -EOPNOTSUPP;
4362         }
4363 }
4364
4365 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4366 {
4367         struct fe_priv *np = netdev_priv(dev);
4368
4369         /* update stats */
4370         nv_do_stats_poll((unsigned long)dev);
4371
4372         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4373 }
4374
4375 static int nv_link_test(struct net_device *dev)
4376 {
4377         struct fe_priv *np = netdev_priv(dev);
4378         int mii_status;
4379
4380         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4381         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4382
4383         /* check phy link status */
4384         if (!(mii_status & BMSR_LSTATUS))
4385                 return 0;
4386         else
4387                 return 1;
4388 }
4389
4390 static int nv_register_test(struct net_device *dev)
4391 {
4392         u8 __iomem *base = get_hwbase(dev);
4393         int i = 0;
4394         u32 orig_read, new_read;
4395
4396         do {
4397                 orig_read = readl(base + nv_registers_test[i].reg);
4398
4399                 /* xor with mask to toggle bits */
4400                 orig_read ^= nv_registers_test[i].mask;
4401
4402                 writel(orig_read, base + nv_registers_test[i].reg);
4403
4404                 new_read = readl(base + nv_registers_test[i].reg);
4405
4406                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4407                         return 0;
4408
4409                 /* restore original value */
4410                 orig_read ^= nv_registers_test[i].mask;
4411                 writel(orig_read, base + nv_registers_test[i].reg);
4412
4413         } while (nv_registers_test[++i].reg != 0);
4414
4415         return 1;
4416 }
4417
4418 static int nv_interrupt_test(struct net_device *dev)
4419 {
4420         struct fe_priv *np = netdev_priv(dev);
4421         u8 __iomem *base = get_hwbase(dev);
4422         int ret = 1;
4423         int testcnt;
4424         u32 save_msi_flags, save_poll_interval = 0;
4425
4426         if (netif_running(dev)) {
4427                 /* free current irq */
4428                 nv_free_irq(dev);
4429                 save_poll_interval = readl(base+NvRegPollingInterval);
4430         }
4431
4432         /* flag to test interrupt handler */
4433         np->intr_test = 0;
4434
4435         /* setup test irq */
4436         save_msi_flags = np->msi_flags;
4437         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4438         np->msi_flags |= 0x001; /* setup 1 vector */
4439         if (nv_request_irq(dev, 1))
4440                 return 0;
4441
4442         /* setup timer interrupt */
4443         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4444         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4445
4446         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4447
4448         /* wait for at least one interrupt */
4449         msleep(100);
4450
4451         spin_lock_irq(&np->lock);
4452
4453         /* flag should be set within ISR */
4454         testcnt = np->intr_test;
4455         if (!testcnt)
4456                 ret = 2;
4457
4458         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4459         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4460                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4461         else
4462                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4463
4464         spin_unlock_irq(&np->lock);
4465
4466         nv_free_irq(dev);
4467
4468         np->msi_flags = save_msi_flags;
4469
4470         if (netif_running(dev)) {
4471                 writel(save_poll_interval, base + NvRegPollingInterval);
4472                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4473                 /* restore original irq */
4474                 if (nv_request_irq(dev, 0))
4475                         return 0;
4476         }
4477
4478         return ret;
4479 }
4480
4481 static int nv_loopback_test(struct net_device *dev)
4482 {
4483         struct fe_priv *np = netdev_priv(dev);
4484         u8 __iomem *base = get_hwbase(dev);
4485         struct sk_buff *tx_skb, *rx_skb;
4486         dma_addr_t test_dma_addr;
4487         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4488         u32 flags;
4489         int len, i, pkt_len;
4490         u8 *pkt_data;
4491         u32 filter_flags = 0;
4492         u32 misc1_flags = 0;
4493         int ret = 1;
4494
4495         if (netif_running(dev)) {
4496                 nv_disable_irq(dev);
4497                 filter_flags = readl(base + NvRegPacketFilterFlags);
4498                 misc1_flags = readl(base + NvRegMisc1);
4499         } else {
4500                 nv_txrx_reset(dev);
4501         }
4502
4503         /* reinit driver view of the rx queue */
4504         set_bufsize(dev);
4505         nv_init_ring(dev);
4506
4507         /* setup hardware for loopback */
4508         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4509         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4510
4511         /* reinit nic view of the rx queue */
4512         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4513         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4514         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4515                 base + NvRegRingSizes);
4516         pci_push(base);
4517
4518         /* restart rx engine */
4519         nv_start_rx(dev);
4520         nv_start_tx(dev);
4521
4522         /* setup packet for tx */
4523         pkt_len = ETH_DATA_LEN;
4524         tx_skb = dev_alloc_skb(pkt_len);
4525         if (!tx_skb) {
4526                 printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
4527                          " of %s\n", dev->name);
4528                 ret = 0;
4529                 goto out;
4530         }
4531         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4532                                        skb_tailroom(tx_skb),
4533                                        PCI_DMA_FROMDEVICE);
4534         pkt_data = skb_put(tx_skb, pkt_len);
4535         for (i = 0; i < pkt_len; i++)
4536                 pkt_data[i] = (u8)(i & 0xff);
4537
4538         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4539                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4540                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4541         } else {
4542                 np->tx_ring.ex[0].bufhigh = cpu_to_le64(test_dma_addr) >> 32;
4543                 np->tx_ring.ex[0].buflow = cpu_to_le64(test_dma_addr) & 0x0FFFFFFFF;
4544                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4545         }
4546         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4547         pci_push(get_hwbase(dev));
4548
4549         msleep(500);
4550
4551         /* check for rx of the packet */
4552         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
4553                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4554                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4555
4556         } else {
4557                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4558                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4559         }
4560
4561         if (flags & NV_RX_AVAIL) {
4562                 ret = 0;
4563         } else if (np->desc_ver == DESC_VER_1) {
4564                 if (flags & NV_RX_ERROR)
4565                         ret = 0;
4566         } else {
4567                 if (flags & NV_RX2_ERROR) {
4568                         ret = 0;
4569                 }
4570         }
4571
4572         if (ret) {
4573                 if (len != pkt_len) {
4574                         ret = 0;
4575                         dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
4576                                 dev->name, len, pkt_len);
4577                 } else {
4578                         rx_skb = np->rx_skb[0].skb;
4579                         for (i = 0; i < pkt_len; i++) {
4580                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4581                                         ret = 0;
4582                                         dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
4583                                                 dev->name, i);
4584                                         break;
4585                                 }
4586                         }
4587                 }
4588         } else {
4589                 dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
4590         }
4591
4592         pci_unmap_page(np->pci_dev, test_dma_addr,
4593                        (skb_end_pointer(tx_skb) - tx_skb->data),
4594                        PCI_DMA_TODEVICE);
4595         dev_kfree_skb_any(tx_skb);
4596  out:
4597         /* stop engines */
4598         nv_stop_rx(dev);
4599         nv_stop_tx(dev);
4600         nv_txrx_reset(dev);
4601         /* drain rx queue */
4602         nv_drain_rx(dev);
4603         nv_drain_tx(dev);
4604
4605         if (netif_running(dev)) {
4606                 writel(misc1_flags, base + NvRegMisc1);
4607                 writel(filter_flags, base + NvRegPacketFilterFlags);
4608                 nv_enable_irq(dev);
4609         }
4610
4611         return ret;
4612 }
4613
4614 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4615 {
4616         struct fe_priv *np = netdev_priv(dev);
4617         u8 __iomem *base = get_hwbase(dev);
4618         int result;
4619         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4620
4621         if (!nv_link_test(dev)) {
4622                 test->flags |= ETH_TEST_FL_FAILED;
4623                 buffer[0] = 1;
4624         }
4625
4626         if (test->flags & ETH_TEST_FL_OFFLINE) {
4627                 if (netif_running(dev)) {
4628                         netif_stop_queue(dev);
4629 #ifdef CONFIG_FORCEDETH_NAPI
4630                         napi_disable(&np->napi);
4631 #endif
4632                         netif_tx_lock_bh(dev);
4633                         spin_lock_irq(&np->lock);
4634                         nv_disable_hw_interrupts(dev, np->irqmask);
4635                         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
4636                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4637                         } else {
4638                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4639                         }
4640                         /* stop engines */
4641                         nv_stop_rx(dev);
4642                         nv_stop_tx(dev);
4643                         nv_txrx_reset(dev);
4644                         /* drain rx queue */
4645                         nv_drain_rx(dev);
4646                         nv_drain_tx(dev);
4647                         spin_unlock_irq(&np->lock);
4648                         netif_tx_unlock_bh(dev);
4649                 }
4650
4651                 if (!nv_register_test(dev)) {
4652                         test->flags |= ETH_TEST_FL_FAILED;
4653                         buffer[1] = 1;
4654                 }
4655
4656                 result = nv_interrupt_test(dev);
4657                 if (result != 1) {
4658                         test->flags |= ETH_TEST_FL_FAILED;
4659                         buffer[2] = 1;
4660                 }
4661                 if (result == 0) {
4662                         /* bail out */
4663                         return;
4664                 }
4665
4666                 if (!nv_loopback_test(dev)) {
4667                         test->flags |= ETH_TEST_FL_FAILED;
4668                         buffer[3] = 1;
4669                 }
4670
4671                 if (netif_running(dev)) {
4672                         /* reinit driver view of the rx queue */
4673                         set_bufsize(dev);
4674                         if (nv_init_ring(dev)) {
4675                                 if (!np->in_shutdown)
4676                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4677                         }
4678                         /* reinit nic view of the rx queue */
4679                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4680                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4681                         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4682                                 base + NvRegRingSizes);
4683                         pci_push(base);
4684                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4685                         pci_push(base);
4686                         /* restart rx engine */
4687                         nv_start_rx(dev);
4688                         nv_start_tx(dev);
4689                         netif_start_queue(dev);
4690 #ifdef CONFIG_FORCEDETH_NAPI
4691                         napi_enable(&np->napi);
4692 #endif
4693                         nv_enable_hw_interrupts(dev, np->irqmask);
4694                 }
4695         }
4696 }
4697
4698 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4699 {
4700         switch (stringset) {
4701         case ETH_SS_STATS:
4702                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4703                 break;
4704         case ETH_SS_TEST:
4705                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4706                 break;
4707         }
4708 }
4709
4710 static const struct ethtool_ops ops = {
4711         .get_drvinfo = nv_get_drvinfo,
4712         .get_link = ethtool_op_get_link,
4713         .get_wol = nv_get_wol,
4714         .set_wol = nv_set_wol,
4715         .get_settings = nv_get_settings,
4716         .set_settings = nv_set_settings,
4717         .get_regs_len = nv_get_regs_len,
4718         .get_regs = nv_get_regs,
4719         .nway_reset = nv_nway_reset,
4720         .set_tso = nv_set_tso,
4721         .get_ringparam = nv_get_ringparam,
4722         .set_ringparam = nv_set_ringparam,
4723         .get_pauseparam = nv_get_pauseparam,
4724         .set_pauseparam = nv_set_pauseparam,
4725         .get_rx_csum = nv_get_rx_csum,
4726         .set_rx_csum = nv_set_rx_csum,
4727         .set_tx_csum = nv_set_tx_csum,
4728         .set_sg = nv_set_sg,
4729         .get_strings = nv_get_strings,
4730         .get_ethtool_stats = nv_get_ethtool_stats,
4731         .get_sset_count = nv_get_sset_count,
4732         .self_test = nv_self_test,
4733 };
4734
4735 static void nv_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
4736 {
4737         struct fe_priv *np = get_nvpriv(dev);
4738
4739         spin_lock_irq(&np->lock);
4740
4741         /* save vlan group */
4742         np->vlangrp = grp;
4743
4744         if (grp) {
4745                 /* enable vlan on MAC */
4746                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS;
4747         } else {
4748                 /* disable vlan on MAC */
4749                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4750                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4751         }
4752
4753         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4754
4755         spin_unlock_irq(&np->lock);
4756 }
4757
4758 /* The mgmt unit and driver use a semaphore to access the phy during init */
4759 static int nv_mgmt_acquire_sema(struct net_device *dev)
4760 {
4761         u8 __iomem *base = get_hwbase(dev);
4762         int i;
4763         u32 tx_ctrl, mgmt_sema;
4764
4765         for (i = 0; i < 10; i++) {
4766                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4767                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4768                         break;
4769                 msleep(500);
4770         }
4771
4772         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4773                 return 0;
4774
4775         for (i = 0; i < 2; i++) {
4776                 tx_ctrl = readl(base + NvRegTransmitterControl);
4777                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4778                 writel(tx_ctrl, base + NvRegTransmitterControl);
4779
4780                 /* verify that semaphore was acquired */
4781                 tx_ctrl = readl(base + NvRegTransmitterControl);
4782                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4783                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE))
4784                         return 1;
4785                 else
4786                         udelay(50);
4787         }
4788
4789         return 0;
4790 }
4791
4792 static int nv_open(struct net_device *dev)
4793 {
4794         struct fe_priv *np = netdev_priv(dev);
4795         u8 __iomem *base = get_hwbase(dev);
4796         int ret = 1;
4797         int oom, i;
4798
4799         dprintk(KERN_DEBUG "nv_open: begin\n");
4800
4801         /* erase previous misconfiguration */
4802         if (np->driver_data & DEV_HAS_POWER_CNTRL)
4803                 nv_mac_reset(dev);
4804         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4805         writel(0, base + NvRegMulticastAddrB);
4806         writel(0, base + NvRegMulticastMaskA);
4807         writel(0, base + NvRegMulticastMaskB);
4808         writel(0, base + NvRegPacketFilterFlags);
4809
4810         writel(0, base + NvRegTransmitterControl);
4811         writel(0, base + NvRegReceiverControl);
4812
4813         writel(0, base + NvRegAdapterControl);
4814
4815         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4816                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
4817
4818         /* initialize descriptor rings */
4819         set_bufsize(dev);
4820         oom = nv_init_ring(dev);
4821
4822         writel(0, base + NvRegLinkSpeed);
4823         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
4824         nv_txrx_reset(dev);
4825         writel(0, base + NvRegUnknownSetupReg6);
4826
4827         np->in_shutdown = 0;
4828
4829         /* give hw rings */
4830         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4831         writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4832                 base + NvRegRingSizes);
4833
4834         writel(np->linkspeed, base + NvRegLinkSpeed);
4835         if (np->desc_ver == DESC_VER_1)
4836                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
4837         else
4838                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
4839         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4840         writel(np->vlanctl_bits, base + NvRegVlanControl);
4841         pci_push(base);
4842         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
4843         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
4844                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
4845                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
4846
4847         writel(0, base + NvRegMIIMask);
4848         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4849         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4850
4851         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
4852         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
4853         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
4854         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4855
4856         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
4857         get_random_bytes(&i, sizeof(i));
4858         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
4859         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
4860         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
4861         if (poll_interval == -1) {
4862                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
4863                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
4864                 else
4865                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4866         }
4867         else
4868                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
4869         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4870         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
4871                         base + NvRegAdapterControl);
4872         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
4873         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
4874         if (np->wolenabled)
4875                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
4876
4877         i = readl(base + NvRegPowerState);
4878         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
4879                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
4880
4881         pci_push(base);
4882         udelay(10);
4883         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
4884
4885         nv_disable_hw_interrupts(dev, np->irqmask);
4886         pci_push(base);
4887         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
4888         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4889         pci_push(base);
4890
4891         if (nv_request_irq(dev, 0)) {
4892                 goto out_drain;
4893         }
4894
4895         /* ask for interrupts */
4896         nv_enable_hw_interrupts(dev, np->irqmask);
4897
4898         spin_lock_irq(&np->lock);
4899         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4900         writel(0, base + NvRegMulticastAddrB);
4901         writel(0, base + NvRegMulticastMaskA);
4902         writel(0, base + NvRegMulticastMaskB);
4903         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4904         /* One manual link speed update: Interrupts are enabled, future link
4905          * speed changes cause interrupts and are handled by nv_link_irq().
4906          */
4907         {
4908                 u32 miistat;
4909                 miistat = readl(base + NvRegMIIStatus);
4910                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
4911                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
4912         }
4913         /* set linkspeed to invalid value, thus force nv_update_linkspeed
4914          * to init hw */
4915         np->linkspeed = 0;
4916         ret = nv_update_linkspeed(dev);
4917         nv_start_rx(dev);
4918         nv_start_tx(dev);
4919         netif_start_queue(dev);
4920 #ifdef CONFIG_FORCEDETH_NAPI
4921         napi_enable(&np->napi);
4922 #endif
4923
4924         if (ret) {
4925                 netif_carrier_on(dev);
4926         } else {
4927                 printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
4928                 netif_carrier_off(dev);
4929         }
4930         if (oom)
4931                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4932
4933         /* start statistics timer */
4934         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2))
4935                 mod_timer(&np->stats_poll, jiffies + STATS_INTERVAL);
4936
4937         spin_unlock_irq(&np->lock);
4938
4939         return 0;
4940 out_drain:
4941         drain_ring(dev);
4942         return ret;
4943 }
4944
4945 static int nv_close(struct net_device *dev)
4946 {
4947         struct fe_priv *np = netdev_priv(dev);
4948         u8 __iomem *base;
4949
4950         spin_lock_irq(&np->lock);
4951         np->in_shutdown = 1;
4952         spin_unlock_irq(&np->lock);
4953 #ifdef CONFIG_FORCEDETH_NAPI
4954         napi_disable(&np->napi);
4955 #endif
4956         synchronize_irq(np->pci_dev->irq);
4957
4958         del_timer_sync(&np->oom_kick);
4959         del_timer_sync(&np->nic_poll);
4960         del_timer_sync(&np->stats_poll);
4961
4962         netif_stop_queue(dev);
4963         spin_lock_irq(&np->lock);
4964         nv_stop_tx(dev);
4965         nv_stop_rx(dev);
4966         nv_txrx_reset(dev);
4967
4968         /* disable interrupts on the nic or we will lock up */
4969         base = get_hwbase(dev);
4970         nv_disable_hw_interrupts(dev, np->irqmask);
4971         pci_push(base);
4972         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
4973
4974         spin_unlock_irq(&np->lock);
4975
4976         nv_free_irq(dev);
4977
4978         drain_ring(dev);
4979
4980         if (np->wolenabled) {
4981                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
4982                 nv_start_rx(dev);
4983         }
4984
4985         /* FIXME: power down nic */
4986
4987         return 0;
4988 }
4989
4990 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
4991 {
4992         struct net_device *dev;
4993         struct fe_priv *np;
4994         unsigned long addr;
4995         u8 __iomem *base;
4996         int err, i;
4997         u32 powerstate, txreg;
4998         u32 phystate_orig = 0, phystate;
4999         int phyinitialized = 0;
5000         DECLARE_MAC_BUF(mac);
5001         static int printed_version;
5002
5003         if (!printed_version++)
5004                 printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
5005                        " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
5006
5007         dev = alloc_etherdev(sizeof(struct fe_priv));
5008         err = -ENOMEM;
5009         if (!dev)
5010                 goto out;
5011
5012         np = netdev_priv(dev);
5013         np->dev = dev;
5014         np->pci_dev = pci_dev;
5015         spin_lock_init(&np->lock);
5016         SET_NETDEV_DEV(dev, &pci_dev->dev);
5017
5018         init_timer(&np->oom_kick);
5019         np->oom_kick.data = (unsigned long) dev;
5020         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
5021         init_timer(&np->nic_poll);
5022         np->nic_poll.data = (unsigned long) dev;
5023         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
5024         init_timer(&np->stats_poll);
5025         np->stats_poll.data = (unsigned long) dev;
5026         np->stats_poll.function = &nv_do_stats_poll;    /* timer handler */
5027
5028         err = pci_enable_device(pci_dev);
5029         if (err)
5030                 goto out_free;
5031
5032         pci_set_master(pci_dev);
5033
5034         err = pci_request_regions(pci_dev, DRV_NAME);
5035         if (err < 0)
5036                 goto out_disable;
5037
5038         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2))
5039                 np->register_size = NV_PCI_REGSZ_VER3;
5040         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5041                 np->register_size = NV_PCI_REGSZ_VER2;
5042         else
5043                 np->register_size = NV_PCI_REGSZ_VER1;
5044
5045         err = -EINVAL;
5046         addr = 0;
5047         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5048                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
5049                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
5050                                 pci_resource_len(pci_dev, i),
5051                                 pci_resource_flags(pci_dev, i));
5052                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5053                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5054                         addr = pci_resource_start(pci_dev, i);
5055                         break;
5056                 }
5057         }
5058         if (i == DEVICE_COUNT_RESOURCE) {
5059                 dev_printk(KERN_INFO, &pci_dev->dev,
5060                            "Couldn't find register window\n");
5061                 goto out_relreg;
5062         }
5063
5064         /* copy of driver data */
5065         np->driver_data = id->driver_data;
5066
5067         /* handle different descriptor versions */
5068         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5069                 /* packet format 3: supports 40-bit addressing */
5070                 np->desc_ver = DESC_VER_3;
5071                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5072                 if (dma_64bit) {
5073                         if (pci_set_dma_mask(pci_dev, DMA_39BIT_MASK))
5074                                 dev_printk(KERN_INFO, &pci_dev->dev,
5075                                         "64-bit DMA failed, using 32-bit addressing\n");
5076                         else
5077                                 dev->features |= NETIF_F_HIGHDMA;
5078                         if (pci_set_consistent_dma_mask(pci_dev, DMA_39BIT_MASK)) {
5079                                 dev_printk(KERN_INFO, &pci_dev->dev,
5080                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5081                         }
5082                 }
5083         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5084                 /* packet format 2: supports jumbo frames */
5085                 np->desc_ver = DESC_VER_2;
5086                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5087         } else {
5088                 /* original packet format */
5089                 np->desc_ver = DESC_VER_1;
5090                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5091         }
5092
5093         np->pkt_limit = NV_PKTLIMIT_1;
5094         if (id->driver_data & DEV_HAS_LARGEDESC)
5095                 np->pkt_limit = NV_PKTLIMIT_2;
5096
5097         if (id->driver_data & DEV_HAS_CHECKSUM) {
5098                 np->rx_csum = 1;
5099                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5100                 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
5101                 dev->features |= NETIF_F_TSO;
5102         }
5103
5104         np->vlanctl_bits = 0;
5105         if (id->driver_data & DEV_HAS_VLAN) {
5106                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5107                 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5108                 dev->vlan_rx_register = nv_vlan_rx_register;
5109         }
5110
5111         np->msi_flags = 0;
5112         if ((id->driver_data & DEV_HAS_MSI) && msi) {
5113                 np->msi_flags |= NV_MSI_CAPABLE;
5114         }
5115         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5116                 np->msi_flags |= NV_MSI_X_CAPABLE;
5117         }
5118
5119         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5120         if (id->driver_data & DEV_HAS_PAUSEFRAME_TX) {
5121                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5122         }
5123
5124
5125         err = -ENOMEM;
5126         np->base = ioremap(addr, np->register_size);
5127         if (!np->base)
5128                 goto out_relreg;
5129         dev->base_addr = (unsigned long)np->base;
5130
5131         dev->irq = pci_dev->irq;
5132
5133         np->rx_ring_size = RX_RING_DEFAULT;
5134         np->tx_ring_size = TX_RING_DEFAULT;
5135
5136         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
5137                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5138                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5139                                         &np->ring_addr);
5140                 if (!np->rx_ring.orig)
5141                         goto out_unmap;
5142                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5143         } else {
5144                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5145                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5146                                         &np->ring_addr);
5147                 if (!np->rx_ring.ex)
5148                         goto out_unmap;
5149                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5150         }
5151         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5152         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5153         if (!np->rx_skb || !np->tx_skb)
5154                 goto out_freering;
5155
5156         dev->open = nv_open;
5157         dev->stop = nv_close;
5158         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
5159                 dev->hard_start_xmit = nv_start_xmit;
5160         else
5161                 dev->hard_start_xmit = nv_start_xmit_optimized;
5162         dev->get_stats = nv_get_stats;
5163         dev->change_mtu = nv_change_mtu;
5164         dev->set_mac_address = nv_set_mac_address;
5165         dev->set_multicast_list = nv_set_multicast;
5166 #ifdef CONFIG_NET_POLL_CONTROLLER
5167         dev->poll_controller = nv_poll_controller;
5168 #endif
5169 #ifdef CONFIG_FORCEDETH_NAPI
5170         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5171 #endif
5172         SET_ETHTOOL_OPS(dev, &ops);
5173         dev->tx_timeout = nv_tx_timeout;
5174         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5175
5176         pci_set_drvdata(pci_dev, dev);
5177
5178         /* read the mac address */
5179         base = get_hwbase(dev);
5180         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5181         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5182
5183         /* check the workaround bit for correct mac address order */
5184         txreg = readl(base + NvRegTransmitPoll);
5185         if ((txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) ||
5186             (id->driver_data & DEV_HAS_CORRECT_MACADDR)) {
5187                 /* mac address is already in correct order */
5188                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5189                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5190                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5191                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5192                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5193                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5194         } else {
5195                 /* need to reverse mac address to correct order */
5196                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5197                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5198                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5199                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5200                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5201                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5202                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5203         }
5204         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5205
5206         if (!is_valid_ether_addr(dev->perm_addr)) {
5207                 /*
5208                  * Bad mac address. At least one bios sets the mac address
5209                  * to 01:23:45:67:89:ab
5210                  */
5211                 dev_printk(KERN_ERR, &pci_dev->dev,
5212                         "Invalid Mac address detected: %s\n",
5213                         print_mac(mac, dev->dev_addr));
5214                 dev_printk(KERN_ERR, &pci_dev->dev,
5215                         "Please complain to your hardware vendor. Switching to a random MAC.\n");
5216                 dev->dev_addr[0] = 0x00;
5217                 dev->dev_addr[1] = 0x00;
5218                 dev->dev_addr[2] = 0x6c;
5219                 get_random_bytes(&dev->dev_addr[3], 3);
5220         }
5221
5222         dprintk(KERN_DEBUG "%s: MAC Address %s\n",
5223                 pci_name(pci_dev), print_mac(mac, dev->dev_addr));
5224
5225         /* set mac address */
5226         nv_copy_mac_to_hw(dev);
5227
5228         /* disable WOL */
5229         writel(0, base + NvRegWakeUpFlags);
5230         np->wolenabled = 0;
5231
5232         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5233
5234                 /* take phy and nic out of low power mode */
5235                 powerstate = readl(base + NvRegPowerState2);
5236                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5237                 if ((id->device == PCI_DEVICE_ID_NVIDIA_NVENET_12 ||
5238                      id->device == PCI_DEVICE_ID_NVIDIA_NVENET_13) &&
5239                     pci_dev->revision >= 0xA3)
5240                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5241                 writel(powerstate, base + NvRegPowerState2);
5242         }
5243
5244         if (np->desc_ver == DESC_VER_1) {
5245                 np->tx_flags = NV_TX_VALID;
5246         } else {
5247                 np->tx_flags = NV_TX2_VALID;
5248         }
5249         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) {
5250                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5251                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5252                         np->msi_flags |= 0x0003;
5253         } else {
5254                 np->irqmask = NVREG_IRQMASK_CPU;
5255                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5256                         np->msi_flags |= 0x0001;
5257         }
5258
5259         if (id->driver_data & DEV_NEED_TIMERIRQ)
5260                 np->irqmask |= NVREG_IRQ_TIMER;
5261         if (id->driver_data & DEV_NEED_LINKTIMER) {
5262                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
5263                 np->need_linktimer = 1;
5264                 np->link_timeout = jiffies + LINK_TIMEOUT;
5265         } else {
5266                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
5267                 np->need_linktimer = 0;
5268         }
5269
5270         /* clear phy state and temporarily halt phy interrupts */
5271         writel(0, base + NvRegMIIMask);
5272         phystate = readl(base + NvRegAdapterControl);
5273         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5274                 phystate_orig = 1;
5275                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5276                 writel(phystate, base + NvRegAdapterControl);
5277         }
5278         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
5279
5280         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5281                 /* management unit running on the mac? */
5282                 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
5283                         np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
5284                         dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
5285                         if (nv_mgmt_acquire_sema(dev)) {
5286                                 /* management unit setup the phy already? */
5287                                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5288                                     NVREG_XMITCTL_SYNC_PHY_INIT) {
5289                                         /* phy is inited by mgmt unit */
5290                                         phyinitialized = 1;
5291                                         dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
5292                                 } else {
5293                                         /* we need to init the phy */
5294                                 }
5295                         }
5296                 }
5297         }
5298
5299         /* find a suitable phy */
5300         for (i = 1; i <= 32; i++) {
5301                 int id1, id2;
5302                 int phyaddr = i & 0x1F;
5303
5304                 spin_lock_irq(&np->lock);
5305                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5306                 spin_unlock_irq(&np->lock);
5307                 if (id1 < 0 || id1 == 0xffff)
5308                         continue;
5309                 spin_lock_irq(&np->lock);
5310                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5311                 spin_unlock_irq(&np->lock);
5312                 if (id2 < 0 || id2 == 0xffff)
5313                         continue;
5314
5315                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5316                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5317                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5318                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
5319                         pci_name(pci_dev), id1, id2, phyaddr);
5320                 np->phyaddr = phyaddr;
5321                 np->phy_oui = id1 | id2;
5322                 break;
5323         }
5324         if (i == 33) {
5325                 dev_printk(KERN_INFO, &pci_dev->dev,
5326                         "open: Could not find a valid PHY.\n");
5327                 goto out_error;
5328         }
5329
5330         if (!phyinitialized) {
5331                 /* reset it */
5332                 phy_init(dev);
5333         } else {
5334                 /* see if it is a gigabit phy */
5335                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5336                 if (mii_status & PHY_GIGABIT) {
5337                         np->gigabit = PHY_GIGABIT;
5338                 }
5339         }
5340
5341         /* set default link speed settings */
5342         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5343         np->duplex = 0;
5344         np->autoneg = 1;
5345
5346         err = register_netdev(dev);
5347         if (err) {
5348                 dev_printk(KERN_INFO, &pci_dev->dev,
5349                            "unable to register netdev: %d\n", err);
5350                 goto out_error;
5351         }
5352
5353         dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
5354                    "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
5355                    dev->name,
5356                    np->phy_oui,
5357                    np->phyaddr,
5358                    dev->dev_addr[0],
5359                    dev->dev_addr[1],
5360                    dev->dev_addr[2],
5361                    dev->dev_addr[3],
5362                    dev->dev_addr[4],
5363                    dev->dev_addr[5]);
5364
5365         dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5366                    dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5367                    dev->features & (NETIF_F_HW_CSUM | NETIF_F_SG) ?
5368                         "csum " : "",
5369                    dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5370                         "vlan " : "",
5371                    id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5372                    id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5373                    id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5374                    np->gigabit == PHY_GIGABIT ? "gbit " : "",
5375                    np->need_linktimer ? "lnktim " : "",
5376                    np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5377                    np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5378                    np->desc_ver);
5379
5380         return 0;
5381
5382 out_error:
5383         if (phystate_orig)
5384                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5385         pci_set_drvdata(pci_dev, NULL);
5386 out_freering:
5387         free_rings(dev);
5388 out_unmap:
5389         iounmap(get_hwbase(dev));
5390 out_relreg:
5391         pci_release_regions(pci_dev);
5392 out_disable:
5393         pci_disable_device(pci_dev);
5394 out_free:
5395         free_netdev(dev);
5396 out:
5397         return err;
5398 }
5399
5400 static void __devexit nv_remove(struct pci_dev *pci_dev)
5401 {
5402         struct net_device *dev = pci_get_drvdata(pci_dev);
5403         struct fe_priv *np = netdev_priv(dev);
5404         u8 __iomem *base = get_hwbase(dev);
5405
5406         unregister_netdev(dev);
5407
5408         /* special op: write back the misordered MAC address - otherwise
5409          * the next nv_probe would see a wrong address.
5410          */
5411         writel(np->orig_mac[0], base + NvRegMacAddrA);
5412         writel(np->orig_mac[1], base + NvRegMacAddrB);
5413         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5414                base + NvRegTransmitPoll);
5415
5416         /* free all structures */
5417         free_rings(dev);
5418         iounmap(get_hwbase(dev));
5419         pci_release_regions(pci_dev);
5420         pci_disable_device(pci_dev);
5421         free_netdev(dev);
5422         pci_set_drvdata(pci_dev, NULL);
5423 }
5424
5425 #ifdef CONFIG_PM
5426 static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
5427 {
5428         struct net_device *dev = pci_get_drvdata(pdev);
5429         struct fe_priv *np = netdev_priv(dev);
5430
5431         if (!netif_running(dev))
5432                 goto out;
5433
5434         netif_device_detach(dev);
5435
5436         // Gross.
5437         nv_close(dev);
5438
5439         pci_save_state(pdev);
5440         pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
5441         pci_set_power_state(pdev, pci_choose_state(pdev, state));
5442 out:
5443         return 0;
5444 }
5445
5446 static int nv_resume(struct pci_dev *pdev)
5447 {
5448         struct net_device *dev = pci_get_drvdata(pdev);
5449         int rc = 0;
5450
5451         if (!netif_running(dev))
5452                 goto out;
5453
5454         netif_device_attach(dev);
5455
5456         pci_set_power_state(pdev, PCI_D0);
5457         pci_restore_state(pdev);
5458         pci_enable_wake(pdev, PCI_D0, 0);
5459
5460         rc = nv_open(dev);
5461 out:
5462         return rc;
5463 }
5464 #else
5465 #define nv_suspend NULL
5466 #define nv_resume NULL
5467 #endif /* CONFIG_PM */
5468
5469 static struct pci_device_id pci_tbl[] = {
5470         {       /* nForce Ethernet Controller */
5471                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
5472                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5473         },
5474         {       /* nForce2 Ethernet Controller */
5475                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
5476                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5477         },
5478         {       /* nForce3 Ethernet Controller */
5479                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
5480                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5481         },
5482         {       /* nForce3 Ethernet Controller */
5483                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
5484                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5485         },
5486         {       /* nForce3 Ethernet Controller */
5487                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
5488                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5489         },
5490         {       /* nForce3 Ethernet Controller */
5491                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
5492                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5493         },
5494         {       /* nForce3 Ethernet Controller */
5495                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
5496                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5497         },
5498         {       /* CK804 Ethernet Controller */
5499                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
5500                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5501         },
5502         {       /* CK804 Ethernet Controller */
5503                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
5504                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5505         },
5506         {       /* MCP04 Ethernet Controller */
5507                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
5508                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5509         },
5510         {       /* MCP04 Ethernet Controller */
5511                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
5512                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1,
5513         },
5514         {       /* MCP51 Ethernet Controller */
5515                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
5516                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5517         },
5518         {       /* MCP51 Ethernet Controller */
5519                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
5520                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1,
5521         },
5522         {       /* MCP55 Ethernet Controller */
5523                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
5524                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5525         },
5526         {       /* MCP55 Ethernet Controller */
5527                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
5528                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5529         },
5530         {       /* MCP61 Ethernet Controller */
5531                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_16),
5532                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5533         },
5534         {       /* MCP61 Ethernet Controller */
5535                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_17),
5536                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5537         },
5538         {       /* MCP61 Ethernet Controller */
5539                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_18),
5540                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5541         },
5542         {       /* MCP61 Ethernet Controller */
5543                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_19),
5544                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5545         },
5546         {       /* MCP65 Ethernet Controller */
5547                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_20),
5548                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5549         },
5550         {       /* MCP65 Ethernet Controller */
5551                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_21),
5552                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5553         },
5554         {       /* MCP65 Ethernet Controller */
5555                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_22),
5556                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5557         },
5558         {       /* MCP65 Ethernet Controller */
5559                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_23),
5560                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5561         },
5562         {       /* MCP67 Ethernet Controller */
5563                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_24),
5564                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5565         },
5566         {       /* MCP67 Ethernet Controller */
5567                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_25),
5568                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5569         },
5570         {       /* MCP67 Ethernet Controller */
5571                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_26),
5572                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5573         },
5574         {       /* MCP67 Ethernet Controller */
5575                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_27),
5576                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5577         },
5578         {       /* MCP73 Ethernet Controller */
5579                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_28),
5580                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5581         },
5582         {       /* MCP73 Ethernet Controller */
5583                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_29),
5584                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5585         },
5586         {       /* MCP73 Ethernet Controller */
5587                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_30),
5588                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5589         },
5590         {       /* MCP73 Ethernet Controller */
5591                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_31),
5592                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR,
5593         },
5594         {       /* MCP77 Ethernet Controller */
5595                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_32),
5596                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5597         },
5598         {       /* MCP77 Ethernet Controller */
5599                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_33),
5600                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5601         },
5602         {       /* MCP77 Ethernet Controller */
5603                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_34),
5604                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5605         },
5606         {       /* MCP77 Ethernet Controller */
5607                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_35),
5608                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5609         },
5610         {       /* MCP79 Ethernet Controller */
5611                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_36),
5612                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5613         },
5614         {       /* MCP79 Ethernet Controller */
5615                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_37),
5616                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5617         },
5618         {       /* MCP79 Ethernet Controller */
5619                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_38),
5620                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5621         },
5622         {       /* MCP79 Ethernet Controller */
5623                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_39),
5624                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX|DEV_HAS_STATISTICS_V2|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT,
5625         },
5626         {0,},
5627 };
5628
5629 static struct pci_driver driver = {
5630         .name           = DRV_NAME,
5631         .id_table       = pci_tbl,
5632         .probe          = nv_probe,
5633         .remove         = __devexit_p(nv_remove),
5634         .suspend        = nv_suspend,
5635         .resume         = nv_resume,
5636 };
5637
5638 static int __init init_nic(void)
5639 {
5640         return pci_register_driver(&driver);
5641 }
5642
5643 static void __exit exit_nic(void)
5644 {
5645         pci_unregister_driver(&driver);
5646 }
5647
5648 module_param(max_interrupt_work, int, 0);
5649 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5650 module_param(optimization_mode, int, 0);
5651 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
5652 module_param(poll_interval, int, 0);
5653 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5654 module_param(msi, int, 0);
5655 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5656 module_param(msix, int, 0);
5657 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5658 module_param(dma_64bit, int, 0);
5659 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5660
5661 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5662 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5663 MODULE_LICENSE("GPL");
5664
5665 MODULE_DEVICE_TABLE(pci, pci_tbl);
5666
5667 module_init(init_nic);
5668 module_exit(exit_nic);