2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
59 #include <linux/uaccess.h>
60 #include <linux/davinci_emac.h>
65 #include "davinci_cpdma.h"
67 static int debug_level;
68 module_param(debug_level, int, 0);
69 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
71 /* Netif debug messages possible */
72 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
80 NETIF_MSG_TX_QUEUED | \
83 NETIF_MSG_RX_STATUS | \
89 #define EMAC_MAJOR_VERSION 6
90 #define EMAC_MINOR_VERSION 1
91 #define EMAC_MODULE_VERSION "6.1"
92 MODULE_VERSION(EMAC_MODULE_VERSION);
93 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
95 /* Configuration items */
96 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
97 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
98 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
99 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
100 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
101 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
102 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
103 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
104 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
105 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
106 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
107 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
109 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
110 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
112 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
113 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
114 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
115 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
116 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
117 #define EMAC_DEF_RX_NUM_DESC (128)
118 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
119 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
120 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
122 /* Buffer descriptor parameters */
123 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
124 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
126 /* EMAC register related defines */
127 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
128 #define EMAC_NUM_MULTICAST_BITS (64)
129 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
130 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
131 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
132 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
133 #define EMAC_INT_MASK_CLEAR (0xFF)
135 /* RX MBP register bit positions */
136 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
137 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
138 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
139 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
140 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
141 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
142 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
143 #define EMAC_RXMBP_PROMCH_SHIFT (16)
144 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
145 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
146 #define EMAC_RXMBP_BROADCH_SHIFT (8)
147 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
148 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
149 #define EMAC_RXMBP_MULTICH_SHIFT (0)
150 #define EMAC_RXMBP_MULTICH_MASK (0x7)
151 #define EMAC_RXMBP_CHMASK (0x7)
153 /* EMAC register definitions/bit maps used */
154 # define EMAC_MBP_RXPROMISC (0x00200000)
155 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
156 # define EMAC_MBP_RXBCAST (0x00002000)
157 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
158 # define EMAC_MBP_RXMCAST (0x00000020)
159 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
161 /* EMAC mac_control register */
162 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
163 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
164 #define EMAC_MACCONTROL_GMIIEN BIT(5)
165 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
166 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
167 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
169 /* GIGABIT MODE related bits */
170 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
171 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
173 /* EMAC mac_status register */
174 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
175 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
176 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
177 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
178 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
179 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
180 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
181 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
183 /* EMAC RX register masks */
184 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
185 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
187 /* MAC_IN_VECTOR (0x180) register bit fields */
188 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
189 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
190 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
191 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
193 /** NOTE:: For DM646x the IN_VECTOR has changed */
194 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
195 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
196 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
197 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
199 /* CPPI bit positions */
200 #define EMAC_CPPI_SOP_BIT BIT(31)
201 #define EMAC_CPPI_EOP_BIT BIT(30)
202 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
203 #define EMAC_CPPI_EOQ_BIT BIT(28)
204 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
205 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
206 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
207 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
208 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
210 /* Max hardware defines */
211 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
212 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
214 /* EMAC Peripheral Device Register Memory Layout structure */
215 #define EMAC_MACINVECTOR 0x90
217 #define EMAC_DM646X_MACEOIVECTOR 0x94
219 #define EMAC_MACINTSTATRAW 0xB0
220 #define EMAC_MACINTSTATMASKED 0xB4
221 #define EMAC_MACINTMASKSET 0xB8
222 #define EMAC_MACINTMASKCLEAR 0xBC
224 #define EMAC_RXMBPENABLE 0x100
225 #define EMAC_RXUNICASTSET 0x104
226 #define EMAC_RXUNICASTCLEAR 0x108
227 #define EMAC_RXMAXLEN 0x10C
228 #define EMAC_RXBUFFEROFFSET 0x110
229 #define EMAC_RXFILTERLOWTHRESH 0x114
231 #define EMAC_MACCONTROL 0x160
232 #define EMAC_MACSTATUS 0x164
233 #define EMAC_EMCONTROL 0x168
234 #define EMAC_FIFOCONTROL 0x16C
235 #define EMAC_MACCONFIG 0x170
236 #define EMAC_SOFTRESET 0x174
237 #define EMAC_MACSRCADDRLO 0x1D0
238 #define EMAC_MACSRCADDRHI 0x1D4
239 #define EMAC_MACHASH1 0x1D8
240 #define EMAC_MACHASH2 0x1DC
241 #define EMAC_MACADDRLO 0x500
242 #define EMAC_MACADDRHI 0x504
243 #define EMAC_MACINDEX 0x508
245 /* EMAC statistics registers */
246 #define EMAC_RXGOODFRAMES 0x200
247 #define EMAC_RXBCASTFRAMES 0x204
248 #define EMAC_RXMCASTFRAMES 0x208
249 #define EMAC_RXPAUSEFRAMES 0x20C
250 #define EMAC_RXCRCERRORS 0x210
251 #define EMAC_RXALIGNCODEERRORS 0x214
252 #define EMAC_RXOVERSIZED 0x218
253 #define EMAC_RXJABBER 0x21C
254 #define EMAC_RXUNDERSIZED 0x220
255 #define EMAC_RXFRAGMENTS 0x224
256 #define EMAC_RXFILTERED 0x228
257 #define EMAC_RXQOSFILTERED 0x22C
258 #define EMAC_RXOCTETS 0x230
259 #define EMAC_TXGOODFRAMES 0x234
260 #define EMAC_TXBCASTFRAMES 0x238
261 #define EMAC_TXMCASTFRAMES 0x23C
262 #define EMAC_TXPAUSEFRAMES 0x240
263 #define EMAC_TXDEFERRED 0x244
264 #define EMAC_TXCOLLISION 0x248
265 #define EMAC_TXSINGLECOLL 0x24C
266 #define EMAC_TXMULTICOLL 0x250
267 #define EMAC_TXEXCESSIVECOLL 0x254
268 #define EMAC_TXLATECOLL 0x258
269 #define EMAC_TXUNDERRUN 0x25C
270 #define EMAC_TXCARRIERSENSE 0x260
271 #define EMAC_TXOCTETS 0x264
272 #define EMAC_NETOCTETS 0x280
273 #define EMAC_RXSOFOVERRUNS 0x284
274 #define EMAC_RXMOFOVERRUNS 0x288
275 #define EMAC_RXDMAOVERRUNS 0x28C
277 /* EMAC DM644x control registers */
278 #define EMAC_CTRL_EWCTL (0x4)
279 #define EMAC_CTRL_EWINTTCNT (0x8)
281 /* EMAC DM644x control module masks */
282 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
283 #define EMAC_DM644X_INTMIN_INTVL 0x1
284 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
286 /* EMAC DM646X control module registers */
287 #define EMAC_DM646X_CMINTCTRL 0x0C
288 #define EMAC_DM646X_CMRXINTEN 0x14
289 #define EMAC_DM646X_CMTXINTEN 0x18
290 #define EMAC_DM646X_CMRXINTMAX 0x70
291 #define EMAC_DM646X_CMTXINTMAX 0x74
293 /* EMAC DM646X control module masks */
294 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
295 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
296 #define EMAC_DM646X_CMINTMAX_CNT 63
297 #define EMAC_DM646X_CMINTMIN_CNT 2
298 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
299 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
302 /* EMAC EOI codes for C0 */
303 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
304 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
306 /* EMAC Stats Clear Mask */
307 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
309 /* emac_priv: EMAC private data structure
311 * EMAC adapter private data structure
315 struct net_device *ndev;
316 struct platform_device *pdev;
317 struct napi_struct napi;
319 void __iomem *remap_addr;
321 void __iomem *emac_base;
322 void __iomem *ctrl_base;
323 struct cpdma_ctlr *dma;
324 struct cpdma_chan *txchan;
325 struct cpdma_chan *rxchan;
326 u32 link; /* 1=link on, 0=link off */
327 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
328 u32 duplex; /* Link duplex: 0=Half, 1=Full */
337 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
340 struct phy_device *phydev;
342 /*platform specific members*/
343 void (*int_enable) (void);
344 void (*int_disable) (void);
347 /* clock frequency for EMAC */
348 static struct clk *emac_clk;
349 static unsigned long emac_bus_frequency;
351 /* EMAC TX Host Error description strings */
352 static char *emac_txhost_errcodes[16] = {
353 "No error", "SOP error", "Ownership bit not set in SOP buffer",
354 "Zero Next Buffer Descriptor Pointer Without EOP",
355 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
356 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
357 "Reserved", "Reserved", "Reserved", "Reserved"
360 /* EMAC RX Host Error description strings */
361 static char *emac_rxhost_errcodes[16] = {
362 "No error", "Reserved", "Ownership bit not set in input buffer",
363 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
364 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
365 "Reserved", "Reserved", "Reserved", "Reserved"
369 #define emac_read(reg) ioread32(priv->emac_base + (reg))
370 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
372 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
373 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
376 * emac_dump_regs: Dump important EMAC registers to debug terminal
377 * @priv: The DaVinci EMAC private adapter structure
379 * Executes ethtool set cmd & sets phy mode
382 static void emac_dump_regs(struct emac_priv *priv)
384 struct device *emac_dev = &priv->ndev->dev;
386 /* Print important registers in EMAC */
387 dev_info(emac_dev, "EMAC Basic registers\n");
388 if (priv->version == EMAC_VERSION_1) {
389 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
390 emac_ctrl_read(EMAC_CTRL_EWCTL),
391 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
393 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
394 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
395 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
396 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
397 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
398 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
399 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
400 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
401 dev_info(emac_dev, "EMAC Statistics\n");
402 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
403 emac_read(EMAC_RXGOODFRAMES));
404 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
405 emac_read(EMAC_RXBCASTFRAMES));
406 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
407 emac_read(EMAC_RXMCASTFRAMES));
408 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
409 emac_read(EMAC_RXPAUSEFRAMES));
410 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
411 emac_read(EMAC_RXCRCERRORS));
412 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
413 emac_read(EMAC_RXALIGNCODEERRORS));
414 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
415 emac_read(EMAC_RXOVERSIZED));
416 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
417 emac_read(EMAC_RXJABBER));
418 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
419 emac_read(EMAC_RXUNDERSIZED));
420 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
421 emac_read(EMAC_RXFRAGMENTS));
422 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
423 emac_read(EMAC_RXFILTERED));
424 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
425 emac_read(EMAC_RXQOSFILTERED));
426 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
427 emac_read(EMAC_RXOCTETS));
428 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
429 emac_read(EMAC_TXGOODFRAMES));
430 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
431 emac_read(EMAC_TXBCASTFRAMES));
432 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
433 emac_read(EMAC_TXMCASTFRAMES));
434 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
435 emac_read(EMAC_TXPAUSEFRAMES));
436 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
437 emac_read(EMAC_TXDEFERRED));
438 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
439 emac_read(EMAC_TXCOLLISION));
440 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
441 emac_read(EMAC_TXSINGLECOLL));
442 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
443 emac_read(EMAC_TXMULTICOLL));
444 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
445 emac_read(EMAC_TXEXCESSIVECOLL));
446 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
447 emac_read(EMAC_TXLATECOLL));
448 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
449 emac_read(EMAC_TXUNDERRUN));
450 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
451 emac_read(EMAC_TXCARRIERSENSE));
452 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
453 emac_read(EMAC_TXOCTETS));
454 dev_info(emac_dev, "EMAC: net_octets:%d\n",
455 emac_read(EMAC_NETOCTETS));
456 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
457 emac_read(EMAC_RXSOFOVERRUNS));
458 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
459 emac_read(EMAC_RXMOFOVERRUNS));
460 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
461 emac_read(EMAC_RXDMAOVERRUNS));
463 cpdma_ctlr_dump(priv->dma);
467 * emac_get_drvinfo: Get EMAC driver information
468 * @ndev: The DaVinci EMAC network adapter
469 * @info: ethtool info structure containing name and version
471 * Returns EMAC driver information (name and version)
474 static void emac_get_drvinfo(struct net_device *ndev,
475 struct ethtool_drvinfo *info)
477 strcpy(info->driver, emac_version_string);
478 strcpy(info->version, EMAC_MODULE_VERSION);
482 * emac_get_settings: Get EMAC settings
483 * @ndev: The DaVinci EMAC network adapter
484 * @ecmd: ethtool command
486 * Executes ethool get command
489 static int emac_get_settings(struct net_device *ndev,
490 struct ethtool_cmd *ecmd)
492 struct emac_priv *priv = netdev_priv(ndev);
494 return phy_ethtool_gset(priv->phydev, ecmd);
501 * emac_set_settings: Set EMAC settings
502 * @ndev: The DaVinci EMAC network adapter
503 * @ecmd: ethtool command
505 * Executes ethool set command
508 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
510 struct emac_priv *priv = netdev_priv(ndev);
512 return phy_ethtool_sset(priv->phydev, ecmd);
519 * emac_get_coalesce : Get interrupt coalesce settings for this device
520 * @ndev : The DaVinci EMAC network adapter
521 * @coal : ethtool coalesce settings structure
523 * Fetch the current interrupt coalesce settings
526 static int emac_get_coalesce(struct net_device *ndev,
527 struct ethtool_coalesce *coal)
529 struct emac_priv *priv = netdev_priv(ndev);
531 coal->rx_coalesce_usecs = priv->coal_intvl;
537 * emac_set_coalesce : Set interrupt coalesce settings for this device
538 * @ndev : The DaVinci EMAC network adapter
539 * @coal : ethtool coalesce settings structure
541 * Set interrupt coalesce parameters
544 static int emac_set_coalesce(struct net_device *ndev,
545 struct ethtool_coalesce *coal)
547 struct emac_priv *priv = netdev_priv(ndev);
548 u32 int_ctrl, num_interrupts = 0;
549 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
551 if (!coal->rx_coalesce_usecs)
554 coal_intvl = coal->rx_coalesce_usecs;
556 switch (priv->version) {
558 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
559 prescale = priv->bus_freq_mhz * 4;
561 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
562 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
564 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
566 * Interrupt pacer works with 4us Pulse, we can
567 * throttle further by dilating the 4us pulse.
569 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
571 if (addnl_dvdr > 1) {
572 prescale *= addnl_dvdr;
573 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
575 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
579 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
583 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
585 int_ctrl |= EMAC_DM646X_INTPACEEN;
586 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
587 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
588 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
590 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
591 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
595 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
596 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
597 prescale = coal_intvl * priv->bus_freq_mhz;
598 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
599 prescale = EMAC_DM644X_EWINTCNT_MASK;
600 coal_intvl = prescale / priv->bus_freq_mhz;
602 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
607 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
608 priv->coal_intvl = coal_intvl;
616 * ethtool_ops: DaVinci EMAC Ethtool structure
618 * Ethtool support for EMAC adapter
621 static const struct ethtool_ops ethtool_ops = {
622 .get_drvinfo = emac_get_drvinfo,
623 .get_settings = emac_get_settings,
624 .set_settings = emac_set_settings,
625 .get_link = ethtool_op_get_link,
626 .get_coalesce = emac_get_coalesce,
627 .set_coalesce = emac_set_coalesce,
631 * emac_update_phystatus: Update Phy status
632 * @priv: The DaVinci EMAC private adapter structure
634 * Updates phy status and takes action for network queue if required
635 * based upon link status
638 static void emac_update_phystatus(struct emac_priv *priv)
643 struct net_device *ndev = priv->ndev;
645 mac_control = emac_read(EMAC_MACCONTROL);
646 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
647 DUPLEX_FULL : DUPLEX_HALF;
649 new_duplex = priv->phydev->duplex;
651 new_duplex = DUPLEX_FULL;
653 /* We get called only if link has changed (speed/duplex/status) */
654 if ((priv->link) && (new_duplex != cur_duplex)) {
655 priv->duplex = new_duplex;
656 if (DUPLEX_FULL == priv->duplex)
657 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
659 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
662 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
663 mac_control = emac_read(EMAC_MACCONTROL);
664 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
665 EMAC_DM646X_MACCONTORL_GIGFORCE);
667 /* Clear the GIG bit and GIGFORCE bit */
668 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
669 EMAC_DM646X_MACCONTORL_GIG);
671 if (priv->rmii_en && (priv->speed == SPEED_100))
672 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
674 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
677 /* Update mac_control if changed */
678 emac_write(EMAC_MACCONTROL, mac_control);
682 if (!netif_carrier_ok(ndev))
683 netif_carrier_on(ndev);
684 /* reactivate the transmit queue if it is stopped */
685 if (netif_running(ndev) && netif_queue_stopped(ndev))
686 netif_wake_queue(ndev);
689 if (netif_carrier_ok(ndev))
690 netif_carrier_off(ndev);
691 if (!netif_queue_stopped(ndev))
692 netif_stop_queue(ndev);
697 * hash_get: Calculate hash value from mac address
698 * @addr: mac address to delete from hash table
700 * Calculates hash value from mac address
703 static u32 hash_get(u8 *addr)
710 for (cnt = 0; cnt < 2; cnt++) {
712 hash ^= (tmpval >> 2) ^ (tmpval << 4);
714 hash ^= (tmpval >> 4) ^ (tmpval << 2);
716 hash ^= (tmpval >> 6) ^ (tmpval);
723 * hash_add: Hash function to add mac addr from hash table
724 * @priv: The DaVinci EMAC private adapter structure
725 * mac_addr: mac address to delete from hash table
727 * Adds mac address to the internal hash table
730 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
732 struct device *emac_dev = &priv->ndev->dev;
735 u32 hash_value = hash_get(mac_addr);
737 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
738 if (netif_msg_drv(priv)) {
739 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
740 "Hash %08x, should not be greater than %08x",
741 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
746 /* set the hash bit only if not previously set */
747 if (priv->multicast_hash_cnt[hash_value] == 0) {
748 rc = 1; /* hash value changed */
749 if (hash_value < 32) {
750 hash_bit = BIT(hash_value);
751 priv->mac_hash1 |= hash_bit;
753 hash_bit = BIT((hash_value - 32));
754 priv->mac_hash2 |= hash_bit;
758 /* incr counter for num of mcast addr's mapped to "this" hash bit */
759 ++priv->multicast_hash_cnt[hash_value];
765 * hash_del: Hash function to delete mac addr from hash table
766 * @priv: The DaVinci EMAC private adapter structure
767 * mac_addr: mac address to delete from hash table
769 * Removes mac address from the internal hash table
772 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
777 hash_value = hash_get(mac_addr);
778 if (priv->multicast_hash_cnt[hash_value] > 0) {
779 /* dec cntr for num of mcast addr's mapped to this hash bit */
780 --priv->multicast_hash_cnt[hash_value];
783 /* if counter still > 0, at least one multicast address refers
784 * to this hash bit. so return 0 */
785 if (priv->multicast_hash_cnt[hash_value] > 0)
788 if (hash_value < 32) {
789 hash_bit = BIT(hash_value);
790 priv->mac_hash1 &= ~hash_bit;
792 hash_bit = BIT((hash_value - 32));
793 priv->mac_hash2 &= ~hash_bit;
796 /* return 1 to indicate change in mac_hash registers reqd */
800 /* EMAC multicast operation */
801 #define EMAC_MULTICAST_ADD 0
802 #define EMAC_MULTICAST_DEL 1
803 #define EMAC_ALL_MULTI_SET 2
804 #define EMAC_ALL_MULTI_CLR 3
807 * emac_add_mcast: Set multicast address in the EMAC adapter (Internal)
808 * @priv: The DaVinci EMAC private adapter structure
809 * @action: multicast operation to perform
810 * mac_addr: mac address to set
812 * Set multicast addresses in EMAC adapter - internal function
815 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
817 struct device *emac_dev = &priv->ndev->dev;
821 case EMAC_MULTICAST_ADD:
822 update = hash_add(priv, mac_addr);
824 case EMAC_MULTICAST_DEL:
825 update = hash_del(priv, mac_addr);
827 case EMAC_ALL_MULTI_SET:
829 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
830 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
832 case EMAC_ALL_MULTI_CLR:
836 memset(&(priv->multicast_hash_cnt[0]), 0,
837 sizeof(priv->multicast_hash_cnt[0]) *
838 EMAC_NUM_MULTICAST_BITS);
841 if (netif_msg_drv(priv))
842 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
843 ": bad operation %d", action);
847 /* write to the hardware only if the register status chances */
849 emac_write(EMAC_MACHASH1, priv->mac_hash1);
850 emac_write(EMAC_MACHASH2, priv->mac_hash2);
855 * emac_dev_mcast_set: Set multicast address in the EMAC adapter
856 * @ndev: The DaVinci EMAC network adapter
858 * Set multicast addresses in EMAC adapter
861 static void emac_dev_mcast_set(struct net_device *ndev)
864 struct emac_priv *priv = netdev_priv(ndev);
866 mbp_enable = emac_read(EMAC_RXMBPENABLE);
867 if (ndev->flags & IFF_PROMISC) {
868 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
869 mbp_enable |= (EMAC_MBP_RXPROMISC);
871 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
872 if ((ndev->flags & IFF_ALLMULTI) ||
873 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
874 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
875 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
876 } else if (!netdev_mc_empty(ndev)) {
877 struct netdev_hw_addr *ha;
879 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
880 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
881 /* program multicast address list into EMAC hardware */
882 netdev_for_each_mc_addr(ha, ndev) {
883 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
887 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
888 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
891 /* Set mbp config register */
892 emac_write(EMAC_RXMBPENABLE, mbp_enable);
895 /*************************************************************************
896 * EMAC Hardware manipulation
897 *************************************************************************/
900 * emac_int_disable: Disable EMAC module interrupt (from adapter)
901 * @priv: The DaVinci EMAC private adapter structure
903 * Disable EMAC interrupt on the adapter
906 static void emac_int_disable(struct emac_priv *priv)
908 if (priv->version == EMAC_VERSION_2) {
911 local_irq_save(flags);
913 /* Program C0_Int_En to zero to turn off
914 * interrupts to the CPU */
915 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
916 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
917 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
918 if (priv->int_disable)
921 local_irq_restore(flags);
924 /* Set DM644x control registers for interrupt control */
925 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
930 * emac_int_enable: Enable EMAC module interrupt (from adapter)
931 * @priv: The DaVinci EMAC private adapter structure
933 * Enable EMAC interrupt on the adapter
936 static void emac_int_enable(struct emac_priv *priv)
938 if (priv->version == EMAC_VERSION_2) {
939 if (priv->int_enable)
942 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
943 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
945 /* In addition to turning on interrupt Enable, we need
946 * ack by writing appropriate values to the EOI
949 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
951 /* ack rxen only then a new pulse will be generated */
952 emac_write(EMAC_DM646X_MACEOIVECTOR,
953 EMAC_DM646X_MAC_EOI_C0_RXEN);
955 /* ack txen- only then a new pulse will be generated */
956 emac_write(EMAC_DM646X_MACEOIVECTOR,
957 EMAC_DM646X_MAC_EOI_C0_TXEN);
960 /* Set DM644x control registers for interrupt control */
961 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
966 * emac_irq: EMAC interrupt handler
967 * @irq: interrupt number
968 * @dev_id: EMAC network adapter data structure ptr
970 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
971 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
973 * Returns interrupt handled condition
975 static irqreturn_t emac_irq(int irq, void *dev_id)
977 struct net_device *ndev = (struct net_device *)dev_id;
978 struct emac_priv *priv = netdev_priv(ndev);
981 if (likely(netif_running(priv->ndev))) {
982 emac_int_disable(priv);
983 napi_schedule(&priv->napi);
985 /* we are closing down, so dont process anything */
990 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
992 struct sk_buff *skb = dev_alloc_skb(priv->rx_buf_size);
995 skb->dev = priv->ndev;
996 skb_reserve(skb, NET_IP_ALIGN);
1000 static void emac_rx_handler(void *token, int len, int status)
1002 struct sk_buff *skb = token;
1003 struct net_device *ndev = skb->dev;
1004 struct emac_priv *priv = netdev_priv(ndev);
1005 struct device *emac_dev = &ndev->dev;
1008 /* free and bail if we are shutting down */
1009 if (unlikely(!netif_running(ndev))) {
1010 dev_kfree_skb_any(skb);
1014 /* recycle on receive error */
1016 ndev->stats.rx_errors++;
1020 /* feed received packet up the stack */
1022 skb->protocol = eth_type_trans(skb, ndev);
1023 netif_receive_skb(skb);
1024 ndev->stats.rx_bytes += len;
1025 ndev->stats.rx_packets++;
1027 /* alloc a new packet for receive */
1028 skb = emac_rx_alloc(priv);
1030 if (netif_msg_rx_err(priv) && net_ratelimit())
1031 dev_err(emac_dev, "failed rx buffer alloc\n");
1036 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1037 skb_tailroom(skb), GFP_KERNEL);
1039 WARN_ON(ret == -ENOMEM);
1040 if (unlikely(ret < 0))
1041 dev_kfree_skb_any(skb);
1044 static void emac_tx_handler(void *token, int len, int status)
1046 struct sk_buff *skb = token;
1047 struct net_device *ndev = skb->dev;
1049 if (unlikely(netif_queue_stopped(ndev)))
1050 netif_wake_queue(ndev);
1051 ndev->stats.tx_packets++;
1052 ndev->stats.tx_bytes += len;
1053 dev_kfree_skb_any(skb);
1057 * emac_dev_xmit: EMAC Transmit function
1059 * @ndev: The DaVinci EMAC network adapter
1061 * Called by the system to transmit a packet - we queue the packet in
1062 * EMAC hardware transmit queue
1064 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1066 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1068 struct device *emac_dev = &ndev->dev;
1070 struct emac_priv *priv = netdev_priv(ndev);
1072 /* If no link, return */
1073 if (unlikely(!priv->link)) {
1074 if (netif_msg_tx_err(priv) && net_ratelimit())
1075 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1079 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1080 if (unlikely(ret_code < 0)) {
1081 if (netif_msg_tx_err(priv) && net_ratelimit())
1082 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1086 skb_tx_timestamp(skb);
1088 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1090 if (unlikely(ret_code != 0)) {
1091 if (netif_msg_tx_err(priv) && net_ratelimit())
1092 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1096 return NETDEV_TX_OK;
1099 ndev->stats.tx_dropped++;
1100 netif_stop_queue(ndev);
1101 return NETDEV_TX_BUSY;
1105 * emac_dev_tx_timeout: EMAC Transmit timeout function
1106 * @ndev: The DaVinci EMAC network adapter
1108 * Called when system detects that a skb timeout period has expired
1109 * potentially due to a fault in the adapter in not being able to send
1110 * it out on the wire. We teardown the TX channel assuming a hardware
1111 * error and re-initialize the TX channel for hardware operation
1114 static void emac_dev_tx_timeout(struct net_device *ndev)
1116 struct emac_priv *priv = netdev_priv(ndev);
1117 struct device *emac_dev = &ndev->dev;
1119 if (netif_msg_tx_err(priv))
1120 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1122 emac_dump_regs(priv);
1124 ndev->stats.tx_errors++;
1125 emac_int_disable(priv);
1126 cpdma_chan_stop(priv->txchan);
1127 cpdma_chan_start(priv->txchan);
1128 emac_int_enable(priv);
1132 * emac_set_type0addr: Set EMAC Type0 mac address
1133 * @priv: The DaVinci EMAC private adapter structure
1134 * @ch: RX channel number
1135 * @mac_addr: MAC address to set in device
1137 * Called internally to set Type0 mac address of the adapter (Device)
1139 * Returns success (0) or appropriate error code (none as of now)
1141 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1144 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1145 emac_write(EMAC_MACSRCADDRLO, val);
1147 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1148 (mac_addr[1] << 8) | (mac_addr[0]));
1149 emac_write(EMAC_MACSRCADDRHI, val);
1150 val = emac_read(EMAC_RXUNICASTSET);
1152 emac_write(EMAC_RXUNICASTSET, val);
1153 val = emac_read(EMAC_RXUNICASTCLEAR);
1155 emac_write(EMAC_RXUNICASTCLEAR, val);
1159 * emac_set_type1addr: Set EMAC Type1 mac address
1160 * @priv: The DaVinci EMAC private adapter structure
1161 * @ch: RX channel number
1162 * @mac_addr: MAC address to set in device
1164 * Called internally to set Type1 mac address of the adapter (Device)
1166 * Returns success (0) or appropriate error code (none as of now)
1168 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1171 emac_write(EMAC_MACINDEX, ch);
1172 val = ((mac_addr[5] << 8) | mac_addr[4]);
1173 emac_write(EMAC_MACADDRLO, val);
1174 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1175 (mac_addr[1] << 8) | (mac_addr[0]));
1176 emac_write(EMAC_MACADDRHI, val);
1177 emac_set_type0addr(priv, ch, mac_addr);
1181 * emac_set_type2addr: Set EMAC Type2 mac address
1182 * @priv: The DaVinci EMAC private adapter structure
1183 * @ch: RX channel number
1184 * @mac_addr: MAC address to set in device
1185 * @index: index into RX address entries
1186 * @match: match parameter for RX address matching logic
1188 * Called internally to set Type2 mac address of the adapter (Device)
1190 * Returns success (0) or appropriate error code (none as of now)
1192 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1193 char *mac_addr, int index, int match)
1196 emac_write(EMAC_MACINDEX, index);
1197 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1198 (mac_addr[1] << 8) | (mac_addr[0]));
1199 emac_write(EMAC_MACADDRHI, val);
1200 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1201 (match << 19) | BIT(20));
1202 emac_write(EMAC_MACADDRLO, val);
1203 emac_set_type0addr(priv, ch, mac_addr);
1207 * emac_setmac: Set mac address in the adapter (internal function)
1208 * @priv: The DaVinci EMAC private adapter structure
1209 * @ch: RX channel number
1210 * @mac_addr: MAC address to set in device
1212 * Called internally to set the mac address of the adapter (Device)
1214 * Returns success (0) or appropriate error code (none as of now)
1216 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1218 struct device *emac_dev = &priv->ndev->dev;
1220 if (priv->rx_addr_type == 0) {
1221 emac_set_type0addr(priv, ch, mac_addr);
1222 } else if (priv->rx_addr_type == 1) {
1224 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1225 emac_set_type1addr(priv, ch, mac_addr);
1226 } else if (priv->rx_addr_type == 2) {
1227 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1228 emac_set_type0addr(priv, ch, mac_addr);
1230 if (netif_msg_drv(priv))
1231 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1236 * emac_dev_setmac_addr: Set mac address in the adapter
1237 * @ndev: The DaVinci EMAC network adapter
1238 * @addr: MAC address to set in device
1240 * Called by the system to set the mac address of the adapter (Device)
1242 * Returns success (0) or appropriate error code (none as of now)
1244 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1246 struct emac_priv *priv = netdev_priv(ndev);
1247 struct device *emac_dev = &priv->ndev->dev;
1248 struct sockaddr *sa = addr;
1250 if (!is_valid_ether_addr(sa->sa_data))
1253 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1254 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1255 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1257 /* MAC address is configured only after the interface is enabled. */
1258 if (netif_running(ndev)) {
1259 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1260 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1263 if (netif_msg_drv(priv))
1264 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1271 * emac_hw_enable: Enable EMAC hardware for packet transmission/reception
1272 * @priv: The DaVinci EMAC private adapter structure
1274 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1275 * for packet reception and enables device interrupts and then NAPI
1277 * Returns success (0) or appropriate error code (none right now)
1279 static int emac_hw_enable(struct emac_priv *priv)
1281 u32 val, mbp_enable, mac_control;
1284 emac_write(EMAC_SOFTRESET, 1);
1285 while (emac_read(EMAC_SOFTRESET))
1288 /* Disable interrupt & Set pacing for more interrupts initially */
1289 emac_int_disable(priv);
1291 /* Full duplex enable bit set when auto negotiation happens */
1293 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1294 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1295 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1296 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1297 emac_write(EMAC_MACCONTROL, mac_control);
1300 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1301 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1302 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1303 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1304 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1305 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1306 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1307 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1308 EMAC_RXMBP_PROMCH_SHIFT) |
1309 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1310 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1311 EMAC_RXMBP_BROADCH_SHIFT) |
1312 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1313 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1314 EMAC_RXMBP_MULTICH_SHIFT));
1315 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1316 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1317 EMAC_RX_MAX_LEN_MASK));
1318 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1319 EMAC_RX_BUFFER_OFFSET_MASK));
1320 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1321 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1322 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1324 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1326 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1329 val = emac_read(EMAC_MACCONTROL);
1330 val |= (EMAC_MACCONTROL_GMIIEN);
1331 emac_write(EMAC_MACCONTROL, val);
1333 /* Enable NAPI and interrupts */
1334 napi_enable(&priv->napi);
1335 emac_int_enable(priv);
1341 * emac_poll: EMAC NAPI Poll function
1342 * @ndev: The DaVinci EMAC network adapter
1343 * @budget: Number of receive packets to process (as told by NAPI layer)
1345 * NAPI Poll function implemented to process packets as per budget. We check
1346 * the type of interrupt on the device and accordingly call the TX or RX
1347 * packet processing functions. We follow the budget for RX processing and
1348 * also put a cap on number of TX pkts processed through config param. The
1349 * NAPI schedule function is called if more packets pending.
1351 * Returns number of packets received (in most cases; else TX pkts - rarely)
1353 static int emac_poll(struct napi_struct *napi, int budget)
1356 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1357 struct net_device *ndev = priv->ndev;
1358 struct device *emac_dev = &ndev->dev;
1360 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1362 /* Check interrupt vectors and call packet processing */
1363 status = emac_read(EMAC_MACINVECTOR);
1365 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1367 if (priv->version == EMAC_VERSION_2)
1368 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1370 if (status & mask) {
1371 num_tx_pkts = cpdma_chan_process(priv->txchan,
1372 EMAC_DEF_TX_MAX_SERVICE);
1373 } /* TX processing */
1375 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1377 if (priv->version == EMAC_VERSION_2)
1378 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1380 if (status & mask) {
1381 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1382 } /* RX processing */
1384 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1385 if (priv->version == EMAC_VERSION_2)
1386 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1388 if (unlikely(status & mask)) {
1390 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1391 netif_stop_queue(ndev);
1392 napi_disable(&priv->napi);
1394 status = emac_read(EMAC_MACSTATUS);
1395 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1396 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1398 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1399 EMAC_MACSTATUS_TXERRCH_SHIFT);
1400 if (net_ratelimit()) {
1401 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1402 &emac_txhost_errcodes[cause][0], ch);
1405 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1406 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1408 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1409 EMAC_MACSTATUS_RXERRCH_SHIFT);
1410 if (netif_msg_hw(priv) && net_ratelimit())
1411 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1412 &emac_rxhost_errcodes[cause][0], ch);
1414 } else if (num_rx_pkts < budget) {
1415 napi_complete(napi);
1416 emac_int_enable(priv);
1422 #ifdef CONFIG_NET_POLL_CONTROLLER
1424 * emac_poll_controller: EMAC Poll controller function
1425 * @ndev: The DaVinci EMAC network adapter
1427 * Polled functionality used by netconsole and others in non interrupt mode
1430 void emac_poll_controller(struct net_device *ndev)
1432 struct emac_priv *priv = netdev_priv(ndev);
1434 emac_int_disable(priv);
1435 emac_irq(ndev->irq, ndev);
1436 emac_int_enable(priv);
1440 static void emac_adjust_link(struct net_device *ndev)
1442 struct emac_priv *priv = netdev_priv(ndev);
1443 struct phy_device *phydev = priv->phydev;
1444 unsigned long flags;
1447 spin_lock_irqsave(&priv->lock, flags);
1450 /* check the mode of operation - full/half duplex */
1451 if (phydev->duplex != priv->duplex) {
1453 priv->duplex = phydev->duplex;
1455 if (phydev->speed != priv->speed) {
1457 priv->speed = phydev->speed;
1464 } else if (priv->link) {
1471 emac_update_phystatus(priv);
1472 phy_print_status(priv->phydev);
1475 spin_unlock_irqrestore(&priv->lock, flags);
1478 /*************************************************************************
1479 * Linux Driver Model
1480 *************************************************************************/
1483 * emac_devioctl: EMAC adapter ioctl
1484 * @ndev: The DaVinci EMAC network adapter
1485 * @ifrq: request parameter
1486 * @cmd: command parameter
1488 * EMAC driver ioctl function
1490 * Returns success(0) or appropriate error code
1492 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1494 struct emac_priv *priv = netdev_priv(ndev);
1496 if (!(netif_running(ndev)))
1499 /* TODO: Add phy read and write and private statistics get feature */
1501 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1504 static int match_first_device(struct device *dev, void *data)
1510 * emac_dev_open: EMAC device open
1511 * @ndev: The DaVinci EMAC network adapter
1513 * Called when system wants to start the interface. We init TX/RX channels
1514 * and enable the hardware for packet reception/transmission and start the
1517 * Returns 0 for a successful open, or appropriate error code
1519 static int emac_dev_open(struct net_device *ndev)
1521 struct device *emac_dev = &ndev->dev;
1523 struct resource *res;
1527 struct emac_priv *priv = netdev_priv(ndev);
1529 netif_carrier_off(ndev);
1530 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1531 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1533 /* Configuration items */
1534 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1536 priv->mac_hash1 = 0;
1537 priv->mac_hash2 = 0;
1538 emac_write(EMAC_MACHASH1, 0);
1539 emac_write(EMAC_MACHASH2, 0);
1541 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1542 struct sk_buff *skb = emac_rx_alloc(priv);
1547 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1548 skb_tailroom(skb), GFP_KERNEL);
1549 if (WARN_ON(ret < 0))
1555 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1556 for (i = res->start; i <= res->end; i++) {
1557 if (request_irq(i, emac_irq, IRQF_DISABLED,
1564 /* Start/Enable EMAC hardware */
1565 emac_hw_enable(priv);
1567 /* Enable Interrupt pacing if configured */
1568 if (priv->coal_intvl != 0) {
1569 struct ethtool_coalesce coal;
1571 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1572 emac_set_coalesce(ndev, &coal);
1575 cpdma_ctlr_start(priv->dma);
1577 priv->phydev = NULL;
1578 /* use the first phy on the bus if pdata did not give us a phy id */
1579 if (!priv->phy_id) {
1582 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1583 match_first_device);
1585 priv->phy_id = dev_name(phy);
1588 if (priv->phy_id && *priv->phy_id) {
1589 priv->phydev = phy_connect(ndev, priv->phy_id,
1590 &emac_adjust_link, 0,
1591 PHY_INTERFACE_MODE_MII);
1593 if (IS_ERR(priv->phydev)) {
1594 dev_err(emac_dev, "could not connect to phy %s\n",
1596 priv->phydev = NULL;
1597 return PTR_ERR(priv->phydev);
1604 dev_info(emac_dev, "attached PHY driver [%s] "
1605 "(mii_bus:phy_addr=%s, id=%x)\n",
1606 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1607 priv->phydev->phy_id);
1609 /* No PHY , fix the link, speed and duplex settings */
1610 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1612 priv->speed = SPEED_100;
1613 priv->duplex = DUPLEX_FULL;
1614 emac_update_phystatus(priv);
1617 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1618 emac_dump_regs(priv);
1620 if (netif_msg_drv(priv))
1621 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1624 phy_start(priv->phydev);
1630 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
1632 for (q = k; k >= 0; k--) {
1633 for (m = i; m >= res->start; m--)
1635 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
1642 * emac_dev_stop: EMAC device stop
1643 * @ndev: The DaVinci EMAC network adapter
1645 * Called when system wants to stop or down the interface. We stop the network
1646 * queue, disable interrupts and cleanup TX/RX channels.
1648 * We return the statistics in net_device_stats structure pulled from emac
1650 static int emac_dev_stop(struct net_device *ndev)
1652 struct resource *res;
1655 struct emac_priv *priv = netdev_priv(ndev);
1656 struct device *emac_dev = &ndev->dev;
1658 /* inform the upper layers. */
1659 netif_stop_queue(ndev);
1660 napi_disable(&priv->napi);
1662 netif_carrier_off(ndev);
1663 emac_int_disable(priv);
1664 cpdma_ctlr_stop(priv->dma);
1665 emac_write(EMAC_SOFTRESET, 1);
1668 phy_disconnect(priv->phydev);
1671 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1672 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1673 free_irq(irq_num, priv->ndev);
1677 if (netif_msg_drv(priv))
1678 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1684 * emac_dev_getnetstats: EMAC get statistics function
1685 * @ndev: The DaVinci EMAC network adapter
1687 * Called when system wants to get statistics from the device.
1689 * We return the statistics in net_device_stats structure pulled from emac
1691 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1693 struct emac_priv *priv = netdev_priv(ndev);
1695 u32 stats_clear_mask;
1697 /* update emac hardware stats and reset the registers*/
1699 mac_control = emac_read(EMAC_MACCONTROL);
1701 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1702 stats_clear_mask = EMAC_STATS_CLR_MASK;
1704 stats_clear_mask = 0;
1706 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1707 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1709 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1710 emac_read(EMAC_TXSINGLECOLL) +
1711 emac_read(EMAC_TXMULTICOLL));
1712 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1713 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1714 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1716 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1717 emac_read(EMAC_RXJABBER) +
1718 emac_read(EMAC_RXUNDERSIZED));
1719 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1720 emac_write(EMAC_RXJABBER, stats_clear_mask);
1721 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1723 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1724 emac_read(EMAC_RXMOFOVERRUNS));
1725 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1726 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1728 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1729 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1731 ndev->stats.tx_carrier_errors +=
1732 emac_read(EMAC_TXCARRIERSENSE);
1733 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1735 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1736 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1738 return &ndev->stats;
1741 static const struct net_device_ops emac_netdev_ops = {
1742 .ndo_open = emac_dev_open,
1743 .ndo_stop = emac_dev_stop,
1744 .ndo_start_xmit = emac_dev_xmit,
1745 .ndo_set_rx_mode = emac_dev_mcast_set,
1746 .ndo_set_mac_address = emac_dev_setmac_addr,
1747 .ndo_do_ioctl = emac_devioctl,
1748 .ndo_tx_timeout = emac_dev_tx_timeout,
1749 .ndo_get_stats = emac_dev_getnetstats,
1750 #ifdef CONFIG_NET_POLL_CONTROLLER
1751 .ndo_poll_controller = emac_poll_controller,
1756 * davinci_emac_probe: EMAC device probe
1757 * @pdev: The DaVinci EMAC device that we are removing
1759 * Called when probing for emac devicesr. We get details of instances and
1760 * resource information from platform init and register a network device
1761 * and allocate resources necessary for driver to perform
1763 static int __devinit davinci_emac_probe(struct platform_device *pdev)
1766 struct resource *res;
1767 struct net_device *ndev;
1768 struct emac_priv *priv;
1769 unsigned long size, hw_ram_addr;
1770 struct emac_platform_data *pdata;
1771 struct device *emac_dev;
1772 struct cpdma_params dma_params;
1774 /* obtain emac clock from kernel */
1775 emac_clk = clk_get(&pdev->dev, NULL);
1776 if (IS_ERR(emac_clk)) {
1777 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1780 emac_bus_frequency = clk_get_rate(emac_clk);
1781 /* TODO: Probe PHY here if possible */
1783 ndev = alloc_etherdev(sizeof(struct emac_priv));
1785 dev_err(&pdev->dev, "error allocating net_device\n");
1790 platform_set_drvdata(pdev, ndev);
1791 priv = netdev_priv(ndev);
1794 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1796 spin_lock_init(&priv->lock);
1798 pdata = pdev->dev.platform_data;
1800 dev_err(&pdev->dev, "no platform data\n");
1805 /* MAC addr and PHY mask , RMII enable info from platform_data */
1806 memcpy(priv->mac_addr, pdata->mac_addr, 6);
1807 priv->phy_id = pdata->phy_id;
1808 priv->rmii_en = pdata->rmii_en;
1809 priv->version = pdata->version;
1810 priv->int_enable = pdata->interrupt_enable;
1811 priv->int_disable = pdata->interrupt_disable;
1813 priv->coal_intvl = 0;
1814 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1816 emac_dev = &ndev->dev;
1817 /* Get EMAC platform data */
1818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1820 dev_err(&pdev->dev,"error getting res\n");
1825 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1826 size = resource_size(res);
1827 if (!request_mem_region(res->start, size, ndev->name)) {
1828 dev_err(&pdev->dev, "failed request_mem_region() for regs\n");
1833 priv->remap_addr = ioremap(res->start, size);
1834 if (!priv->remap_addr) {
1835 dev_err(&pdev->dev, "unable to map IO\n");
1837 release_mem_region(res->start, size);
1840 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1841 ndev->base_addr = (unsigned long)priv->remap_addr;
1843 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1845 hw_ram_addr = pdata->hw_ram_addr;
1847 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1849 memset(&dma_params, 0, sizeof(dma_params));
1850 dma_params.dev = emac_dev;
1851 dma_params.dmaregs = priv->emac_base;
1852 dma_params.rxthresh = priv->emac_base + 0x120;
1853 dma_params.rxfree = priv->emac_base + 0x140;
1854 dma_params.txhdp = priv->emac_base + 0x600;
1855 dma_params.rxhdp = priv->emac_base + 0x620;
1856 dma_params.txcp = priv->emac_base + 0x640;
1857 dma_params.rxcp = priv->emac_base + 0x660;
1858 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1859 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1860 dma_params.desc_hw_addr = hw_ram_addr;
1861 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1862 dma_params.desc_align = 16;
1864 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1865 (u32 __force)res->start + pdata->ctrl_ram_offset;
1867 priv->dma = cpdma_ctlr_create(&dma_params);
1869 dev_err(&pdev->dev, "error initializing DMA\n");
1874 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1876 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1878 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1883 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1885 dev_err(&pdev->dev, "error getting irq res\n");
1889 ndev->irq = res->start;
1891 if (!is_valid_ether_addr(priv->mac_addr)) {
1892 /* Use random MAC if none passed */
1893 random_ether_addr(priv->mac_addr);
1894 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1898 ndev->netdev_ops = &emac_netdev_ops;
1899 SET_ETHTOOL_OPS(ndev, ðtool_ops);
1900 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1902 clk_enable(emac_clk);
1904 /* register the network device */
1905 SET_NETDEV_DEV(ndev, &pdev->dev);
1906 rc = register_netdev(ndev);
1908 dev_err(&pdev->dev, "error in register_netdev\n");
1910 goto netdev_reg_err;
1914 if (netif_msg_probe(priv)) {
1915 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
1916 "(regs: %p, irq: %d)\n",
1917 (void *)priv->emac_base_phys, ndev->irq);
1922 clk_disable(emac_clk);
1925 cpdma_chan_destroy(priv->txchan);
1927 cpdma_chan_destroy(priv->rxchan);
1928 cpdma_ctlr_destroy(priv->dma);
1930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1931 release_mem_region(res->start, resource_size(res));
1932 iounmap(priv->remap_addr);
1942 * davinci_emac_remove: EMAC device remove
1943 * @pdev: The DaVinci EMAC device that we are removing
1945 * Called when removing the device driver. We disable clock usage and release
1946 * the resources taken up by the driver and unregister network device
1948 static int __devexit davinci_emac_remove(struct platform_device *pdev)
1950 struct resource *res;
1951 struct net_device *ndev = platform_get_drvdata(pdev);
1952 struct emac_priv *priv = netdev_priv(ndev);
1954 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1956 platform_set_drvdata(pdev, NULL);
1957 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1960 cpdma_chan_destroy(priv->txchan);
1962 cpdma_chan_destroy(priv->rxchan);
1963 cpdma_ctlr_destroy(priv->dma);
1965 release_mem_region(res->start, resource_size(res));
1967 unregister_netdev(ndev);
1968 iounmap(priv->remap_addr);
1971 clk_disable(emac_clk);
1977 static int davinci_emac_suspend(struct device *dev)
1979 struct platform_device *pdev = to_platform_device(dev);
1980 struct net_device *ndev = platform_get_drvdata(pdev);
1982 if (netif_running(ndev))
1983 emac_dev_stop(ndev);
1985 clk_disable(emac_clk);
1990 static int davinci_emac_resume(struct device *dev)
1992 struct platform_device *pdev = to_platform_device(dev);
1993 struct net_device *ndev = platform_get_drvdata(pdev);
1995 clk_enable(emac_clk);
1997 if (netif_running(ndev))
1998 emac_dev_open(ndev);
2003 static const struct dev_pm_ops davinci_emac_pm_ops = {
2004 .suspend = davinci_emac_suspend,
2005 .resume = davinci_emac_resume,
2009 * davinci_emac_driver: EMAC platform driver structure
2011 static struct platform_driver davinci_emac_driver = {
2013 .name = "davinci_emac",
2014 .owner = THIS_MODULE,
2015 .pm = &davinci_emac_pm_ops,
2017 .probe = davinci_emac_probe,
2018 .remove = __devexit_p(davinci_emac_remove),
2022 * davinci_emac_init: EMAC driver module init
2024 * Called when initializing the driver. We register the driver with
2027 static int __init davinci_emac_init(void)
2029 return platform_driver_register(&davinci_emac_driver);
2031 late_initcall(davinci_emac_init);
2034 * davinci_emac_exit: EMAC driver module exit
2036 * Called when exiting the driver completely. We unregister the driver with
2037 * the platform and exit
2039 static void __exit davinci_emac_exit(void)
2041 platform_driver_unregister(&davinci_emac_driver);
2043 module_exit(davinci_emac_exit);
2045 MODULE_LICENSE("GPL");
2046 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2047 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2048 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");