drivers/net/ethernet/realtek/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8168E_3        "rtl_nic/rtl8168e-3.fw"
  45 #define FIRMWARE_8168F_1        "rtl_nic/rtl8168f-1.fw"
  46 #define FIRMWARE_8168F_2        "rtl_nic/rtl8168f-2.fw"
  47 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  48
  49 #ifdef RTL8169_DEBUG
  50 #define assert(expr) \
  51         if (!(expr)) {                                  \
  52                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  53                 #expr,__FILE__,__func__,__LINE__);              \
  54         }
  55 #define dprintk(fmt, args...) \
  56         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  57 #else
  58 #define assert(expr) do {} while (0)
  59 #define dprintk(fmt, args...)   do {} while (0)
  60 #endif /* RTL8169_DEBUG */
  61
  62 #define R8169_MSG_DEFAULT \
  63         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  64
  65 #define TX_BUFFS_AVAIL(tp) \
  66         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  67
  68 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  69    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  70 static const int multicast_filter_limit = 32;
  71
  72 /* MAC address length */
  73 #define MAC_ADDR_LEN    6
  74
  75 #define MAX_READ_REQUEST_SHIFT  12
  76 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  77 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  78 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  79
  80 #define R8169_REGS_SIZE         256
  81 #define R8169_NAPI_WEIGHT       64
  82 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  83 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  84 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  85 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  86 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  87
  88 #define RTL8169_TX_TIMEOUT      (6*HZ)
  89 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  90
  91 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  92 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  93 #define RTL_EEPROM_SIG_ADDR     0x0000
  94
  95 /* write/read MMIO register */
  96 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  97 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  98 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  99 #define RTL_R8(reg)             readb (ioaddr + (reg))
 100 #define RTL_R16(reg)            readw (ioaddr + (reg))
 101 #define RTL_R32(reg)            readl (ioaddr + (reg))
 102
 103 enum mac_version {
 104         RTL_GIGA_MAC_VER_01 = 0,
 105         RTL_GIGA_MAC_VER_02,
 106         RTL_GIGA_MAC_VER_03,
 107         RTL_GIGA_MAC_VER_04,
 108         RTL_GIGA_MAC_VER_05,
 109         RTL_GIGA_MAC_VER_06,
 110         RTL_GIGA_MAC_VER_07,
 111         RTL_GIGA_MAC_VER_08,
 112         RTL_GIGA_MAC_VER_09,
 113         RTL_GIGA_MAC_VER_10,
 114         RTL_GIGA_MAC_VER_11,
 115         RTL_GIGA_MAC_VER_12,
 116         RTL_GIGA_MAC_VER_13,
 117         RTL_GIGA_MAC_VER_14,
 118         RTL_GIGA_MAC_VER_15,
 119         RTL_GIGA_MAC_VER_16,
 120         RTL_GIGA_MAC_VER_17,
 121         RTL_GIGA_MAC_VER_18,
 122         RTL_GIGA_MAC_VER_19,
 123         RTL_GIGA_MAC_VER_20,
 124         RTL_GIGA_MAC_VER_21,
 125         RTL_GIGA_MAC_VER_22,
 126         RTL_GIGA_MAC_VER_23,
 127         RTL_GIGA_MAC_VER_24,
 128         RTL_GIGA_MAC_VER_25,
 129         RTL_GIGA_MAC_VER_26,
 130         RTL_GIGA_MAC_VER_27,
 131         RTL_GIGA_MAC_VER_28,
 132         RTL_GIGA_MAC_VER_29,
 133         RTL_GIGA_MAC_VER_30,
 134         RTL_GIGA_MAC_VER_31,
 135         RTL_GIGA_MAC_VER_32,
 136         RTL_GIGA_MAC_VER_33,
 137         RTL_GIGA_MAC_VER_34,
 138         RTL_GIGA_MAC_VER_35,
 139         RTL_GIGA_MAC_VER_36,
 140         RTL_GIGA_MAC_NONE   = 0xff,
 141 };
 142
 143 enum rtl_tx_desc_version {
 144         RTL_TD_0        = 0,
 145         RTL_TD_1        = 1,
 146 };
 147
 148 #define JUMBO_1K        ETH_DATA_LEN
 149 #define JUMBO_4K        (4*1024 - ETH_HLEN - 2)
 150 #define JUMBO_6K        (6*1024 - ETH_HLEN - 2)
 151 #define JUMBO_7K        (7*1024 - ETH_HLEN - 2)
 152 #define JUMBO_9K        (9*1024 - ETH_HLEN - 2)
 153
 154 #define _R(NAME,TD,FW,SZ,B) {   \
 155         .name = NAME,           \
 156         .txd_version = TD,      \
 157         .fw_name = FW,          \
 158         .jumbo_max = SZ,        \
 159         .jumbo_tx_csum = B      \
 160 }
 161
 162 static const struct {
 163         const char *name;
 164         enum rtl_tx_desc_version txd_version;
 165         const char *fw_name;
 166         u16 jumbo_max;
 167         bool jumbo_tx_csum;
 168 } rtl_chip_infos[] = {
 169         /* PCI devices. */
 170         [RTL_GIGA_MAC_VER_01] =
 171                 _R("RTL8169",           RTL_TD_0, NULL, JUMBO_7K, true),
 172         [RTL_GIGA_MAC_VER_02] =
 173                 _R("RTL8169s",          RTL_TD_0, NULL, JUMBO_7K, true),
 174         [RTL_GIGA_MAC_VER_03] =
 175                 _R("RTL8110s",          RTL_TD_0, NULL, JUMBO_7K, true),
 176         [RTL_GIGA_MAC_VER_04] =
 177                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL, JUMBO_7K, true),
 178         [RTL_GIGA_MAC_VER_05] =
 179                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 180         [RTL_GIGA_MAC_VER_06] =
 181                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL, JUMBO_7K, true),
 182         /* PCI-E devices. */
 183         [RTL_GIGA_MAC_VER_07] =
 184                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 185         [RTL_GIGA_MAC_VER_08] =
 186                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 187         [RTL_GIGA_MAC_VER_09] =
 188                 _R("RTL8102e",          RTL_TD_1, NULL, JUMBO_1K, true),
 189         [RTL_GIGA_MAC_VER_10] =
 190                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 191         [RTL_GIGA_MAC_VER_11] =
 192                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 193         [RTL_GIGA_MAC_VER_12] =
 194                 _R("RTL8168b/8111b",    RTL_TD_0, NULL, JUMBO_4K, false),
 195         [RTL_GIGA_MAC_VER_13] =
 196                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 197         [RTL_GIGA_MAC_VER_14] =
 198                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 199         [RTL_GIGA_MAC_VER_15] =
 200                 _R("RTL8100e",          RTL_TD_0, NULL, JUMBO_1K, true),
 201         [RTL_GIGA_MAC_VER_16] =
 202                 _R("RTL8101e",          RTL_TD_0, NULL, JUMBO_1K, true),
 203         [RTL_GIGA_MAC_VER_17] =
 204                 _R("RTL8168b/8111b",    RTL_TD_1, NULL, JUMBO_4K, false),
 205         [RTL_GIGA_MAC_VER_18] =
 206                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 207         [RTL_GIGA_MAC_VER_19] =
 208                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 209         [RTL_GIGA_MAC_VER_20] =
 210                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 211         [RTL_GIGA_MAC_VER_21] =
 212                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 213         [RTL_GIGA_MAC_VER_22] =
 214                 _R("RTL8168c/8111c",    RTL_TD_1, NULL, JUMBO_6K, false),
 215         [RTL_GIGA_MAC_VER_23] =
 216                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 217         [RTL_GIGA_MAC_VER_24] =
 218                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL, JUMBO_6K, false),
 219         [RTL_GIGA_MAC_VER_25] =
 220                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1,
 221                                                         JUMBO_9K, false),
 222         [RTL_GIGA_MAC_VER_26] =
 223                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2,
 224                                                         JUMBO_9K, false),
 225         [RTL_GIGA_MAC_VER_27] =
 226                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 227         [RTL_GIGA_MAC_VER_28] =
 228                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 229         [RTL_GIGA_MAC_VER_29] =
 230                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 231                                                         JUMBO_1K, true),
 232         [RTL_GIGA_MAC_VER_30] =
 233                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1,
 234                                                         JUMBO_1K, true),
 235         [RTL_GIGA_MAC_VER_31] =
 236                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL, JUMBO_9K, false),
 237         [RTL_GIGA_MAC_VER_32] =
 238                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1,
 239                                                         JUMBO_9K, false),
 240         [RTL_GIGA_MAC_VER_33] =
 241                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2,
 242                                                         JUMBO_9K, false),
 243         [RTL_GIGA_MAC_VER_34] =
 244                 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
 245                                                         JUMBO_9K, false),
 246         [RTL_GIGA_MAC_VER_35] =
 247                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_1,
 248                                                         JUMBO_9K, false),
 249         [RTL_GIGA_MAC_VER_36] =
 250                 _R("RTL8168f/8111f",    RTL_TD_1, FIRMWARE_8168F_2,
 251                                                         JUMBO_9K, false),
 252 };
 253 #undef _R
 254
 255 enum cfg_version {
 256         RTL_CFG_0 = 0x00,
 257         RTL_CFG_1,
 258         RTL_CFG_2
 259 };
 260
 261 static void rtl_hw_start_8169(struct net_device *);
 262 static void rtl_hw_start_8168(struct net_device *);
 263 static void rtl_hw_start_8101(struct net_device *);
 264
 265 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 266         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 267         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 268         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 269         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 270         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 271         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 272         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4302), 0, 0, RTL_CFG_0 },
 273         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 274         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 275         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 276                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 277         { 0x0001,                               0x8168,
 278                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 279         {0,},
 280 };
 281
 282 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 283
 284 static int rx_buf_sz = 16383;
 285 static int use_dac;
 286 static struct {
 287         u32 msg_enable;
 288 } debug = { -1 };
 289
 290 enum rtl_registers {
 291         MAC0            = 0,    /* Ethernet hardware address. */
 292         MAC4            = 4,
 293         MAR0            = 8,    /* Multicast filter. */
 294         CounterAddrLow          = 0x10,
 295         CounterAddrHigh         = 0x14,
 296         TxDescStartAddrLow      = 0x20,
 297         TxDescStartAddrHigh     = 0x24,
 298         TxHDescStartAddrLow     = 0x28,
 299         TxHDescStartAddrHigh    = 0x2c,
 300         FLASH           = 0x30,
 301         ERSR            = 0x36,
 302         ChipCmd         = 0x37,
 303         TxPoll          = 0x38,
 304         IntrMask        = 0x3c,
 305         IntrStatus      = 0x3e,
 306
 307         TxConfig        = 0x40,
 308 #define TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
 309 #define TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
 310
 311         RxConfig        = 0x44,
 312 #define RX128_INT_EN                    (1 << 15)       /* 8111c and later */
 313 #define RX_MULTI_EN                     (1 << 14)       /* 8111c only */
 314 #define RXCFG_FIFO_SHIFT                13
 315                                         /* No threshold before first PCI xfer */
 316 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
 317 #define RXCFG_DMA_SHIFT                 8
 318                                         /* Unlimited maximum PCI burst. */
 319 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
 320
 321         RxMissed        = 0x4c,
 322         Cfg9346         = 0x50,
 323         Config0         = 0x51,
 324         Config1         = 0x52,
 325         Config2         = 0x53,
 326         Config3         = 0x54,
 327         Config4         = 0x55,
 328         Config5         = 0x56,
 329         MultiIntr       = 0x5c,
 330         PHYAR           = 0x60,
 331         PHYstatus       = 0x6c,
 332         RxMaxSize       = 0xda,
 333         CPlusCmd        = 0xe0,
 334         IntrMitigate    = 0xe2,
 335         RxDescAddrLow   = 0xe4,
 336         RxDescAddrHigh  = 0xe8,
 337         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 338
 339 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 340
 341         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 342
 343 #define TxPacketMax     (8064 >> 7)
 344 #define EarlySize       0x27
 345
 346         FuncEvent       = 0xf0,
 347         FuncEventMask   = 0xf4,
 348         FuncPresetState = 0xf8,
 349         FuncForceEvent  = 0xfc,
 350 };
 351
 352 enum rtl8110_registers {
 353         TBICSR                  = 0x64,
 354         TBI_ANAR                = 0x68,
 355         TBI_LPAR                = 0x6a,
 356 };
 357
 358 enum rtl8168_8101_registers {
 359         CSIDR                   = 0x64,
 360         CSIAR                   = 0x68,
 361 #define CSIAR_FLAG                      0x80000000
 362 #define CSIAR_WRITE_CMD                 0x80000000
 363 #define CSIAR_BYTE_ENABLE               0x0f
 364 #define CSIAR_BYTE_ENABLE_SHIFT         12
 365 #define CSIAR_ADDR_MASK                 0x0fff
 366         PMCH                    = 0x6f,
 367         EPHYAR                  = 0x80,
 368 #define EPHYAR_FLAG                     0x80000000
 369 #define EPHYAR_WRITE_CMD                0x80000000
 370 #define EPHYAR_REG_MASK                 0x1f
 371 #define EPHYAR_REG_SHIFT                16
 372 #define EPHYAR_DATA_MASK                0xffff
 373         DLLPR                   = 0xd0,
 374 #define PFM_EN                          (1 << 6)
 375         DBG_REG                 = 0xd1,
 376 #define FIX_NAK_1                       (1 << 4)
 377 #define FIX_NAK_2                       (1 << 3)
 378         TWSI                    = 0xd2,
 379         MCU                     = 0xd3,
 380 #define NOW_IS_OOB                      (1 << 7)
 381 #define EN_NDP                          (1 << 3)
 382 #define EN_OOB_RESET                    (1 << 2)
 383         EFUSEAR                 = 0xdc,
 384 #define EFUSEAR_FLAG                    0x80000000
 385 #define EFUSEAR_WRITE_CMD               0x80000000
 386 #define EFUSEAR_READ_CMD                0x00000000
 387 #define EFUSEAR_REG_MASK                0x03ff
 388 #define EFUSEAR_REG_SHIFT               8
 389 #define EFUSEAR_DATA_MASK               0xff
 390 };
 391
 392 enum rtl8168_registers {
 393         LED_FREQ                = 0x1a,
 394         EEE_LED                 = 0x1b,
 395         ERIDR                   = 0x70,
 396         ERIAR                   = 0x74,
 397 #define ERIAR_FLAG                      0x80000000
 398 #define ERIAR_WRITE_CMD                 0x80000000
 399 #define ERIAR_READ_CMD                  0x00000000
 400 #define ERIAR_ADDR_BYTE_ALIGN           4
 401 #define ERIAR_TYPE_SHIFT                16
 402 #define ERIAR_EXGMAC                    (0x00 << ERIAR_TYPE_SHIFT)
 403 #define ERIAR_MSIX                      (0x01 << ERIAR_TYPE_SHIFT)
 404 #define ERIAR_ASF                       (0x02 << ERIAR_TYPE_SHIFT)
 405 #define ERIAR_MASK_SHIFT                12
 406 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 407 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
 408 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
 409         EPHY_RXER_NUM           = 0x7c,
 410         OCPDR                   = 0xb0, /* OCP GPHY access */
 411 #define OCPDR_WRITE_CMD                 0x80000000
 412 #define OCPDR_READ_CMD                  0x00000000
 413 #define OCPDR_REG_MASK                  0x7f
 414 #define OCPDR_GPHY_REG_SHIFT            16
 415 #define OCPDR_DATA_MASK                 0xffff
 416         OCPAR                   = 0xb4,
 417 #define OCPAR_FLAG                      0x80000000
 418 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 419 #define OCPAR_GPHY_READ_CMD             0x0000f060
 420         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 421         MISC                    = 0xf0, /* 8168e only. */
 422 #define TXPLA_RST                       (1 << 29)
 423 #define PWM_EN                          (1 << 22)
 424 };
 425
 426 enum rtl_register_content {
 427         /* InterruptStatusBits */
 428         SYSErr          = 0x8000,
 429         PCSTimeout      = 0x4000,
 430         SWInt           = 0x0100,
 431         TxDescUnavail   = 0x0080,
 432         RxFIFOOver      = 0x0040,
 433         LinkChg         = 0x0020,
 434         RxOverflow      = 0x0010,
 435         TxErr           = 0x0008,
 436         TxOK            = 0x0004,
 437         RxErr           = 0x0002,
 438         RxOK            = 0x0001,
 439
 440         /* RxStatusDesc */
 441         RxBOVF  = (1 << 24),
 442         RxFOVF  = (1 << 23),
 443         RxRWT   = (1 << 22),
 444         RxRES   = (1 << 21),
 445         RxRUNT  = (1 << 20),
 446         RxCRC   = (1 << 19),
 447
 448         /* ChipCmdBits */
 449         StopReq         = 0x80,
 450         CmdReset        = 0x10,
 451         CmdRxEnb        = 0x08,
 452         CmdTxEnb        = 0x04,
 453         RxBufEmpty      = 0x01,
 454
 455         /* TXPoll register p.5 */
 456         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 457         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 458         FSWInt          = 0x01,         /* Forced software interrupt */
 459
 460         /* Cfg9346Bits */
 461         Cfg9346_Lock    = 0x00,
 462         Cfg9346_Unlock  = 0xc0,
 463
 464         /* rx_mode_bits */
 465         AcceptErr       = 0x20,
 466         AcceptRunt      = 0x10,
 467         AcceptBroadcast = 0x08,
 468         AcceptMulticast = 0x04,
 469         AcceptMyPhys    = 0x02,
 470         AcceptAllPhys   = 0x01,
 471 #define RX_CONFIG_ACCEPT_MASK           0x3f
 472
 473         /* TxConfigBits */
 474         TxInterFrameGapShift = 24,
 475         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 476
 477         /* Config1 register p.24 */
 478         LEDS1           = (1 << 7),
 479         LEDS0           = (1 << 6),
 480         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 481         Speed_down      = (1 << 4),
 482         MEMMAP          = (1 << 3),
 483         IOMAP           = (1 << 2),
 484         VPD             = (1 << 1),
 485         PMEnable        = (1 << 0),     /* Power Management Enable */
 486
 487         /* Config2 register p. 25 */
 488         PCI_Clock_66MHz = 0x01,
 489         PCI_Clock_33MHz = 0x00,
 490
 491         /* Config3 register p.25 */
 492         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 493         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 494         Jumbo_En0       = (1 << 2),     /* 8168 only. Reserved in the 8168b */
 495         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 496
 497         /* Config4 register */
 498         Jumbo_En1       = (1 << 1),     /* 8168 only. Reserved in the 8168b */
 499
 500         /* Config5 register p.27 */
 501         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 502         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 503         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 504         Spi_en          = (1 << 3),
 505         LanWake         = (1 << 1),     /* LanWake enable/disable */
 506         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 507
 508         /* TBICSR p.28 */
 509         TBIReset        = 0x80000000,
 510         TBILoopback     = 0x40000000,
 511         TBINwEnable     = 0x20000000,
 512         TBINwRestart    = 0x10000000,
 513         TBILinkOk       = 0x02000000,
 514         TBINwComplete   = 0x01000000,
 515
 516         /* CPlusCmd p.31 */
 517         EnableBist      = (1 << 15),    // 8168 8101
 518         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 519         Normal_mode     = (1 << 13),    // unused
 520         Force_half_dup  = (1 << 12),    // 8168 8101
 521         Force_rxflow_en = (1 << 11),    // 8168 8101
 522         Force_txflow_en = (1 << 10),    // 8168 8101
 523         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 524         ASF             = (1 << 8),     // 8168 8101
 525         PktCntrDisable  = (1 << 7),     // 8168 8101
 526         Mac_dbgo_sel    = 0x001c,       // 8168
 527         RxVlan          = (1 << 6),
 528         RxChkSum        = (1 << 5),
 529         PCIDAC          = (1 << 4),
 530         PCIMulRW        = (1 << 3),
 531         INTT_0          = 0x0000,       // 8168
 532         INTT_1          = 0x0001,       // 8168
 533         INTT_2          = 0x0002,       // 8168
 534         INTT_3          = 0x0003,       // 8168
 535
 536         /* rtl8169_PHYstatus */
 537         TBI_Enable      = 0x80,
 538         TxFlowCtrl      = 0x40,
 539         RxFlowCtrl      = 0x20,
 540         _1000bpsF       = 0x10,
 541         _100bps         = 0x08,
 542         _10bps          = 0x04,
 543         LinkStatus      = 0x02,
 544         FullDup         = 0x01,
 545
 546         /* _TBICSRBit */
 547         TBILinkOK       = 0x02000000,
 548
 549         /* DumpCounterCommand */
 550         CounterDump     = 0x8,
 551 };
 552
 553 enum rtl_desc_bit {
 554         /* First doubleword. */
 555         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 556         RingEnd         = (1 << 30), /* End of descriptor ring */
 557         FirstFrag       = (1 << 29), /* First segment of a packet */
 558         LastFrag        = (1 << 28), /* Final segment of a packet */
 559 };
 560
 561 /* Generic case. */
 562 enum rtl_tx_desc_bit {
 563         /* First doubleword. */
 564         TD_LSO          = (1 << 27),            /* Large Send Offload */
 565 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 566
 567         /* Second doubleword. */
 568         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 569 };
 570
 571 /* 8169, 8168b and 810x except 8102e. */
 572 enum rtl_tx_desc_bit_0 {
 573         /* First doubleword. */
 574 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 575         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 576         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 577         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 578 };
 579
 580 /* 8102e, 8168c and beyond. */
 581 enum rtl_tx_desc_bit_1 {
 582         /* Second doubleword. */
 583 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 584         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 585         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 586         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 587 };
 588
 589 static const struct rtl_tx_desc_info {
 590         struct {
 591                 u32 udp;
 592                 u32 tcp;
 593         } checksum;
 594         u16 mss_shift;
 595         u16 opts_offset;
 596 } tx_desc_info [] = {
 597         [RTL_TD_0] = {
 598                 .checksum = {
 599                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 600                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 601                 },
 602                 .mss_shift      = TD0_MSS_SHIFT,
 603                 .opts_offset    = 0
 604         },
 605         [RTL_TD_1] = {
 606                 .checksum = {
 607                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 608                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 609                 },
 610                 .mss_shift      = TD1_MSS_SHIFT,
 611                 .opts_offset    = 1
 612         }
 613 };
 614
 615 enum rtl_rx_desc_bit {
 616         /* Rx private */
 617         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 618         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 619
 620 #define RxProtoUDP      (PID1)
 621 #define RxProtoTCP      (PID0)
 622 #define RxProtoIP       (PID1 | PID0)
 623 #define RxProtoMask     RxProtoIP
 624
 625         IPFail          = (1 << 16), /* IP checksum failed */
 626         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 627         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 628         RxVlanTag       = (1 << 16), /* VLAN tag available */
 629 };
 630
 631 #define RsvdMask        0x3fffc000
 632
 633 struct TxDesc {
 634         __le32 opts1;
 635         __le32 opts2;
 636         __le64 addr;
 637 };
 638
 639 struct RxDesc {
 640         __le32 opts1;
 641         __le32 opts2;
 642         __le64 addr;
 643 };
 644
 645 struct ring_info {
 646         struct sk_buff  *skb;
 647         u32             len;
 648         u8              __pad[sizeof(void *) - sizeof(u32)];
 649 };
 650
 651 enum features {
 652         RTL_FEATURE_WOL         = (1 << 0),
 653         RTL_FEATURE_MSI         = (1 << 1),
 654         RTL_FEATURE_GMII        = (1 << 2),
 655 };
 656
 657 struct rtl8169_counters {
 658         __le64  tx_packets;
 659         __le64  rx_packets;
 660         __le64  tx_errors;
 661         __le32  rx_errors;
 662         __le16  rx_missed;
 663         __le16  align_errors;
 664         __le32  tx_one_collision;
 665         __le32  tx_multi_collision;
 666         __le64  rx_unicast;
 667         __le64  rx_broadcast;
 668         __le32  rx_multicast;
 669         __le16  tx_aborted;
 670         __le16  tx_underun;
 671 };
 672
 673 struct rtl8169_private {
 674         void __iomem *mmio_addr;        /* memory map physical address */
 675         struct pci_dev *pci_dev;
 676         struct net_device *dev;
 677         struct napi_struct napi;
 678         spinlock_t lock;
 679         u32 msg_enable;
 680         u16 txd_version;
 681         u16 mac_version;
 682         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 683         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 684         u32 dirty_rx;
 685         u32 dirty_tx;
 686         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 687         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 688         dma_addr_t TxPhyAddr;
 689         dma_addr_t RxPhyAddr;
 690         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 691         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 692         struct timer_list timer;
 693         u16 cp_cmd;
 694         u16 intr_event;
 695         u16 napi_event;
 696         u16 intr_mask;
 697
 698         struct mdio_ops {
 699                 void (*write)(void __iomem *, int, int);
 700                 int (*read)(void __iomem *, int);
 701         } mdio_ops;
 702
 703         struct pll_power_ops {
 704                 void (*down)(struct rtl8169_private *);
 705                 void (*up)(struct rtl8169_private *);
 706         } pll_power_ops;
 707
 708         struct jumbo_ops {
 709                 void (*enable)(struct rtl8169_private *);
 710                 void (*disable)(struct rtl8169_private *);
 711         } jumbo_ops;
 712
 713         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 714         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 715         void (*phy_reset_enable)(struct rtl8169_private *tp);
 716         void (*hw_start)(struct net_device *);
 717         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 718         unsigned int (*link_ok)(void __iomem *);
 719         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 720         struct delayed_work task;
 721         unsigned features;
 722
 723         struct mii_if_info mii;
 724         struct rtl8169_counters counters;
 725         u32 saved_wolopts;
 726         u32 opts1_mask;
 727
 728         struct rtl_fw {
 729                 const struct firmware *fw;
 730
 731 #define RTL_VER_SIZE            32
 732
 733                 char version[RTL_VER_SIZE];
 734
 735                 struct rtl_fw_phy_action {
 736                         __le32 *code;
 737                         size_t size;
 738                 } phy_action;
 739         } *rtl_fw;
 740 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN)
 741 };
 742
 743 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 744 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 745 module_param(use_dac, int, 0);
 746 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 747 module_param_named(debug, debug.msg_enable, int, 0);
 748 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 749 MODULE_LICENSE("GPL");
 750 MODULE_VERSION(RTL8169_VERSION);
 751 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 752 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 753 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 754 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 755 MODULE_FIRMWARE(FIRMWARE_8168E_3);
 756 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 757 MODULE_FIRMWARE(FIRMWARE_8168F_1);
 758 MODULE_FIRMWARE(FIRMWARE_8168F_2);
 759
 760 static int rtl8169_open(struct net_device *dev);
 761 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 762                                       struct net_device *dev);
 763 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 764 static int rtl8169_init_ring(struct net_device *dev);
 765 static void rtl_hw_start(struct net_device *dev);
 766 static int rtl8169_close(struct net_device *dev);
 767 static void rtl_set_rx_mode(struct net_device *dev);
 768 static void rtl8169_tx_timeout(struct net_device *dev);
 769 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 770 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 771                                 void __iomem *, u32 budget);
 772 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 773 static void rtl8169_down(struct net_device *dev);
 774 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 775 static int rtl8169_poll(struct napi_struct *napi, int budget);
 776
 777 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
 778 {
 779         int cap = pci_pcie_cap(pdev);
 780
 781         if (cap) {
 782                 u16 ctl;
 783
 784                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
 785                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
 786                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
 787         }
 788 }
 789
 790 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 791 {
 792         void __iomem *ioaddr = tp->mmio_addr;
 793         int i;
 794
 795         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 796         for (i = 0; i < 20; i++) {
 797                 udelay(100);
 798                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 799                         break;
 800         }
 801         return RTL_R32(OCPDR);
 802 }
 803
 804 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 805 {
 806         void __iomem *ioaddr = tp->mmio_addr;
 807         int i;
 808
 809         RTL_W32(OCPDR, data);
 810         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 811         for (i = 0; i < 20; i++) {
 812                 udelay(100);
 813                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 814                         break;
 815         }
 816 }
 817
 818 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 819 {
 820         void __iomem *ioaddr = tp->mmio_addr;
 821         int i;
 822
 823         RTL_W8(ERIDR, cmd);
 824         RTL_W32(ERIAR, 0x800010e8);
 825         msleep(2);
 826         for (i = 0; i < 5; i++) {
 827                 udelay(100);
 828                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
 829                         break;
 830         }
 831
 832         ocp_write(tp, 0x1, 0x30, 0x00000001);
 833 }
 834
 835 #define OOB_CMD_RESET           0x00
 836 #define OOB_CMD_DRIVER_START    0x05
 837 #define OOB_CMD_DRIVER_STOP     0x06
 838
 839 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 840 {
 841         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 842 }
 843
 844 static void rtl8168_driver_start(struct rtl8169_private *tp)
 845 {
 846         u16 reg;
 847         int i;
 848
 849         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 850
 851         reg = rtl8168_get_ocp_reg(tp);
 852
 853         for (i = 0; i < 10; i++) {
 854                 msleep(10);
 855                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 856                         break;
 857         }
 858 }
 859
 860 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 861 {
 862         u16 reg;
 863         int i;
 864
 865         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 866
 867         reg = rtl8168_get_ocp_reg(tp);
 868
 869         for (i = 0; i < 10; i++) {
 870                 msleep(10);
 871                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 872                         break;
 873         }
 874 }
 875
 876 static int r8168dp_check_dash(struct rtl8169_private *tp)
 877 {
 878         u16 reg = rtl8168_get_ocp_reg(tp);
 879
 880         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 881 }
 882
 883 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 884 {
 885         int i;
 886
 887         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 888
 889         for (i = 20; i > 0; i--) {
 890                 /*
 891                  * Check if the RTL8169 has completed writing to the specified
 892                  * MII register.
 893                  */
 894                 if (!(RTL_R32(PHYAR) & 0x80000000))
 895                         break;
 896                 udelay(25);
 897         }
 898         /*
 899          * According to hardware specs a 20us delay is required after write
 900          * complete indication, but before sending next command.
 901          */
 902         udelay(20);
 903 }
 904
 905 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 906 {
 907         int i, value = -1;
 908
 909         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 910
 911         for (i = 20; i > 0; i--) {
 912                 /*
 913                  * Check if the RTL8169 has completed retrieving data from
 914                  * the specified MII register.
 915                  */
 916                 if (RTL_R32(PHYAR) & 0x80000000) {
 917                         value = RTL_R32(PHYAR) & 0xffff;
 918                         break;
 919                 }
 920                 udelay(25);
 921         }
 922         /*
 923          * According to hardware specs a 20us delay is required after read
 924          * complete indication, but before sending next command.
 925          */
 926         udelay(20);
 927
 928         return value;
 929 }
 930
 931 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 932 {
 933         int i;
 934
 935         RTL_W32(OCPDR, data |
 936                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 937         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 938         RTL_W32(EPHY_RXER_NUM, 0);
 939
 940         for (i = 0; i < 100; i++) {
 941                 mdelay(1);
 942                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 943                         break;
 944         }
 945 }
 946
 947 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 948 {
 949         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 950                 (value & OCPDR_DATA_MASK));
 951 }
 952
 953 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 954 {
 955         int i;
 956
 957         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 958
 959         mdelay(1);
 960         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 961         RTL_W32(EPHY_RXER_NUM, 0);
 962
 963         for (i = 0; i < 100; i++) {
 964                 mdelay(1);
 965                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 966                         break;
 967         }
 968
 969         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 970 }
 971
 972 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 973
 974 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 975 {
 976         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 977 }
 978
 979 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 980 {
 981         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 982 }
 983
 984 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 985 {
 986         r8168dp_2_mdio_start(ioaddr);
 987
 988         r8169_mdio_write(ioaddr, reg_addr, value);
 989
 990         r8168dp_2_mdio_stop(ioaddr);
 991 }
 992
 993 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 994 {
 995         int value;
 996
 997         r8168dp_2_mdio_start(ioaddr);
 998
 999         value = r8169_mdio_read(ioaddr, reg_addr);
1000
1001         r8168dp_2_mdio_stop(ioaddr);
1002
1003         return value;
1004 }
1005
1006 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1007 {
1008         tp->mdio_ops.write(tp->mmio_addr, location, val);
1009 }
1010
1011 static int rtl_readphy(struct rtl8169_private *tp, int location)
1012 {
1013         return tp->mdio_ops.read(tp->mmio_addr, location);
1014 }
1015
1016 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1017 {
1018         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1019 }
1020
1021 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1022 {
1023         int val;
1024
1025         val = rtl_readphy(tp, reg_addr);
1026         rtl_writephy(tp, reg_addr, (val | p) & ~m);
1027 }
1028
1029 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1030                            int val)
1031 {
1032         struct rtl8169_private *tp = netdev_priv(dev);
1033
1034         rtl_writephy(tp, location, val);
1035 }
1036
1037 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1038 {
1039         struct rtl8169_private *tp = netdev_priv(dev);
1040
1041         return rtl_readphy(tp, location);
1042 }
1043
1044 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
1045 {
1046         unsigned int i;
1047
1048         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051         for (i = 0; i < 100; i++) {
1052                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
1053                         break;
1054                 udelay(10);
1055         }
1056 }
1057
1058 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1059 {
1060         u16 value = 0xffff;
1061         unsigned int i;
1062
1063         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1064
1065         for (i = 0; i < 100; i++) {
1066                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1067                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1068                         break;
1069                 }
1070                 udelay(10);
1071         }
1072
1073         return value;
1074 }
1075
1076 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1077 {
1078         unsigned int i;
1079
1080         RTL_W32(CSIDR, value);
1081         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1082                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1083
1084         for (i = 0; i < 100; i++) {
1085                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1086                         break;
1087                 udelay(10);
1088         }
1089 }
1090
1091 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1092 {
1093         u32 value = ~0x00;
1094         unsigned int i;
1095
1096         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1097                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1098
1099         for (i = 0; i < 100; i++) {
1100                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1101                         value = RTL_R32(CSIDR);
1102                         break;
1103                 }
1104                 udelay(10);
1105         }
1106
1107         return value;
1108 }
1109
1110 static
1111 void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1112 {
1113         unsigned int i;
1114
1115         BUG_ON((addr & 3) || (mask == 0));
1116         RTL_W32(ERIDR, val);
1117         RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1118
1119         for (i = 0; i < 100; i++) {
1120                 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1121                         break;
1122                 udelay(100);
1123         }
1124 }
1125
1126 static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1127 {
1128         u32 value = ~0x00;
1129         unsigned int i;
1130
1131         RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1132
1133         for (i = 0; i < 100; i++) {
1134                 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1135                         value = RTL_R32(ERIDR);
1136                         break;
1137                 }
1138                 udelay(100);
1139         }
1140
1141         return value;
1142 }
1143
1144 static void
1145 rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1146 {
1147         u32 val;
1148
1149         val = rtl_eri_read(ioaddr, addr, type);
1150         rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1151 }
1152
1153 struct exgmac_reg {
1154         u16 addr;
1155         u16 mask;
1156         u32 val;
1157 };
1158
1159 static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1160                                    const struct exgmac_reg *r, int len)
1161 {
1162         while (len-- > 0) {
1163                 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1164                 r++;
1165         }
1166 }
1167
1168 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1169 {
1170         u8 value = 0xff;
1171         unsigned int i;
1172
1173         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1174
1175         for (i = 0; i < 300; i++) {
1176                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1177                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1178                         break;
1179                 }
1180                 udelay(100);
1181         }
1182
1183         return value;
1184 }
1185
1186 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1187 {
1188         RTL_W16(IntrMask, 0x0000);
1189
1190         RTL_W16(IntrStatus, 0xffff);
1191 }
1192
1193 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1194 {
1195         void __iomem *ioaddr = tp->mmio_addr;
1196
1197         return RTL_R32(TBICSR) & TBIReset;
1198 }
1199
1200 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1201 {
1202         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1203 }
1204
1205 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1206 {
1207         return RTL_R32(TBICSR) & TBILinkOk;
1208 }
1209
1210 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1211 {
1212         return RTL_R8(PHYstatus) & LinkStatus;
1213 }
1214
1215 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1216 {
1217         void __iomem *ioaddr = tp->mmio_addr;
1218
1219         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1220 }
1221
1222 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1223 {
1224         unsigned int val;
1225
1226         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1227         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1228 }
1229
1230 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1231 {
1232         void __iomem *ioaddr = tp->mmio_addr;
1233         struct net_device *dev = tp->dev;
1234
1235         if (!netif_running(dev))
1236                 return;
1237
1238         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1239                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1240                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1241                                       0x00000011, ERIAR_EXGMAC);
1242                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1243                                       0x00000005, ERIAR_EXGMAC);
1244                 } else if (RTL_R8(PHYstatus) & _100bps) {
1245                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1246                                       0x0000001f, ERIAR_EXGMAC);
1247                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1248                                       0x00000005, ERIAR_EXGMAC);
1249                 } else {
1250                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1251                                       0x0000001f, ERIAR_EXGMAC);
1252                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1253                                       0x0000003f, ERIAR_EXGMAC);
1254                 }
1255                 /* Reset packet filter */
1256                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1257                              ERIAR_EXGMAC);
1258                 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1259                              ERIAR_EXGMAC);
1260         } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1261                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
1262                 if (RTL_R8(PHYstatus) & _1000bpsF) {
1263                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1264                                       0x00000011, ERIAR_EXGMAC);
1265                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1266                                       0x00000005, ERIAR_EXGMAC);
1267                 } else {
1268                         rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1269                                       0x0000001f, ERIAR_EXGMAC);
1270                         rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1271                                       0x0000003f, ERIAR_EXGMAC);
1272                 }
1273         }
1274 }
1275
1276 static void __rtl8169_check_link_status(struct net_device *dev,
1277                                         struct rtl8169_private *tp,
1278                                         void __iomem *ioaddr, bool pm)
1279 {
1280         unsigned long flags;
1281
1282         spin_lock_irqsave(&tp->lock, flags);
1283         if (tp->link_ok(ioaddr)) {
1284                 rtl_link_chg_patch(tp);
1285                 /* This is to cancel a scheduled suspend if there's one. */
1286                 if (pm)
1287                         pm_request_resume(&tp->pci_dev->dev);
1288                 netif_carrier_on(dev);
1289                 if (net_ratelimit())
1290                         netif_info(tp, ifup, dev, "link up\n");
1291         } else {
1292                 netif_carrier_off(dev);
1293                 netif_info(tp, ifdown, dev, "link down\n");
1294                 if (pm)
1295                         pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1296         }
1297         spin_unlock_irqrestore(&tp->lock, flags);
1298 }
1299
1300 static void rtl8169_check_link_status(struct net_device *dev,
1301                                       struct rtl8169_private *tp,
1302                                       void __iomem *ioaddr)
1303 {
1304         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1305 }
1306
1307 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1308
1309 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1310 {
1311         void __iomem *ioaddr = tp->mmio_addr;
1312         u8 options;
1313         u32 wolopts = 0;
1314
1315         options = RTL_R8(Config1);
1316         if (!(options & PMEnable))
1317                 return 0;
1318
1319         options = RTL_R8(Config3);
1320         if (options & LinkUp)
1321                 wolopts |= WAKE_PHY;
1322         if (options & MagicPacket)
1323                 wolopts |= WAKE_MAGIC;
1324
1325         options = RTL_R8(Config5);
1326         if (options & UWF)
1327                 wolopts |= WAKE_UCAST;
1328         if (options & BWF)
1329                 wolopts |= WAKE_BCAST;
1330         if (options & MWF)
1331                 wolopts |= WAKE_MCAST;
1332
1333         return wolopts;
1334 }
1335
1336 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1337 {
1338         struct rtl8169_private *tp = netdev_priv(dev);
1339
1340         spin_lock_irq(&tp->lock);
1341
1342         wol->supported = WAKE_ANY;
1343         wol->wolopts = __rtl8169_get_wol(tp);
1344
1345         spin_unlock_irq(&tp->lock);
1346 }
1347
1348 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1349 {
1350         void __iomem *ioaddr = tp->mmio_addr;
1351         unsigned int i;
1352         static const struct {
1353                 u32 opt;
1354                 u16 reg;
1355                 u8  mask;
1356         } cfg[] = {
1357                 { WAKE_ANY,   Config1, PMEnable },
1358                 { WAKE_PHY,   Config3, LinkUp },
1359                 { WAKE_MAGIC, Config3, MagicPacket },
1360                 { WAKE_UCAST, Config5, UWF },
1361                 { WAKE_BCAST, Config5, BWF },
1362                 { WAKE_MCAST, Config5, MWF },
1363                 { WAKE_ANY,   Config5, LanWake }
1364         };
1365
1366         RTL_W8(Cfg9346, Cfg9346_Unlock);
1367
1368         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1369                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1370                 if (wolopts & cfg[i].opt)
1371                         options |= cfg[i].mask;
1372                 RTL_W8(cfg[i].reg, options);
1373         }
1374
1375         RTL_W8(Cfg9346, Cfg9346_Lock);
1376 }
1377
1378 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1379 {
1380         struct rtl8169_private *tp = netdev_priv(dev);
1381
1382         spin_lock_irq(&tp->lock);
1383
1384         if (wol->wolopts)
1385                 tp->features |= RTL_FEATURE_WOL;
1386         else
1387                 tp->features &= ~RTL_FEATURE_WOL;
1388         __rtl8169_set_wol(tp, wol->wolopts);
1389         spin_unlock_irq(&tp->lock);
1390
1391         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1392
1393         return 0;
1394 }
1395
1396 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1397 {
1398         return rtl_chip_infos[tp->mac_version].fw_name;
1399 }
1400
1401 static void rtl8169_get_drvinfo(struct net_device *dev,
1402                                 struct ethtool_drvinfo *info)
1403 {
1404         struct rtl8169_private *tp = netdev_priv(dev);
1405         struct rtl_fw *rtl_fw = tp->rtl_fw;
1406
1407         strcpy(info->driver, MODULENAME);
1408         strcpy(info->version, RTL8169_VERSION);
1409         strcpy(info->bus_info, pci_name(tp->pci_dev));
1410         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1411         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1412                rtl_fw->version);
1413 }
1414
1415 static int rtl8169_get_regs_len(struct net_device *dev)
1416 {
1417         return R8169_REGS_SIZE;
1418 }
1419
1420 static int rtl8169_set_speed_tbi(struct net_device *dev,
1421                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1422 {
1423         struct rtl8169_private *tp = netdev_priv(dev);
1424         void __iomem *ioaddr = tp->mmio_addr;
1425         int ret = 0;
1426         u32 reg;
1427
1428         reg = RTL_R32(TBICSR);
1429         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1430             (duplex == DUPLEX_FULL)) {
1431                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1432         } else if (autoneg == AUTONEG_ENABLE)
1433                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1434         else {
1435                 netif_warn(tp, link, dev,
1436                            "incorrect speed setting refused in TBI mode\n");
1437                 ret = -EOPNOTSUPP;
1438         }
1439
1440         return ret;
1441 }
1442
1443 static int rtl8169_set_speed_xmii(struct net_device *dev,
1444                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1445 {
1446         struct rtl8169_private *tp = netdev_priv(dev);
1447         int giga_ctrl, bmcr;
1448         int rc = -EINVAL;
1449
1450         rtl_writephy(tp, 0x1f, 0x0000);
1451
1452         if (autoneg == AUTONEG_ENABLE) {
1453                 int auto_nego;
1454
1455                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1456                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1457                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1458
1459                 if (adv & ADVERTISED_10baseT_Half)
1460                         auto_nego |= ADVERTISE_10HALF;
1461                 if (adv & ADVERTISED_10baseT_Full)
1462                         auto_nego |= ADVERTISE_10FULL;
1463                 if (adv & ADVERTISED_100baseT_Half)
1464                         auto_nego |= ADVERTISE_100HALF;
1465                 if (adv & ADVERTISED_100baseT_Full)
1466                         auto_nego |= ADVERTISE_100FULL;
1467
1468                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1469
1470                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1471                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1472
1473                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1474                 if (tp->mii.supports_gmii) {
1475                         if (adv & ADVERTISED_1000baseT_Half)
1476                                 giga_ctrl |= ADVERTISE_1000HALF;
1477                         if (adv & ADVERTISED_1000baseT_Full)
1478                                 giga_ctrl |= ADVERTISE_1000FULL;
1479                 } else if (adv & (ADVERTISED_1000baseT_Half |
1480                                   ADVERTISED_1000baseT_Full)) {
1481                         netif_info(tp, link, dev,
1482                                    "PHY does not support 1000Mbps\n");
1483                         goto out;
1484                 }
1485
1486                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1487
1488                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1489                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1490         } else {
1491                 giga_ctrl = 0;
1492
1493                 if (speed == SPEED_10)
1494                         bmcr = 0;
1495                 else if (speed == SPEED_100)
1496                         bmcr = BMCR_SPEED100;
1497                 else
1498                         goto out;
1499
1500                 if (duplex == DUPLEX_FULL)
1501                         bmcr |= BMCR_FULLDPLX;
1502         }
1503
1504         rtl_writephy(tp, MII_BMCR, bmcr);
1505
1506         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1507             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1508                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1509                         rtl_writephy(tp, 0x17, 0x2138);
1510                         rtl_writephy(tp, 0x0e, 0x0260);
1511                 } else {
1512                         rtl_writephy(tp, 0x17, 0x2108);
1513                         rtl_writephy(tp, 0x0e, 0x0000);
1514                 }
1515         }
1516
1517         rc = 0;
1518 out:
1519         return rc;
1520 }
1521
1522 static int rtl8169_set_speed(struct net_device *dev,
1523                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1524 {
1525         struct rtl8169_private *tp = netdev_priv(dev);
1526         int ret;
1527
1528         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1529         if (ret < 0)
1530                 goto out;
1531
1532         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1533             (advertising & ADVERTISED_1000baseT_Full)) {
1534                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1535         }
1536 out:
1537         return ret;
1538 }
1539
1540 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1541 {
1542         struct rtl8169_private *tp = netdev_priv(dev);
1543         unsigned long flags;
1544         int ret;
1545
1546         del_timer_sync(&tp->timer);
1547
1548         spin_lock_irqsave(&tp->lock, flags);
1549         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1550                                 cmd->duplex, cmd->advertising);
1551         spin_unlock_irqrestore(&tp->lock, flags);
1552
1553         return ret;
1554 }
1555
1556 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1557 {
1558         struct rtl8169_private *tp = netdev_priv(dev);
1559
1560         if (dev->mtu > TD_MSS_MAX)
1561                 features &= ~NETIF_F_ALL_TSO;
1562
1563         if (dev->mtu > JUMBO_1K &&
1564             !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
1565                 features &= ~NETIF_F_IP_CSUM;
1566
1567         return features;
1568 }
1569
1570 static int rtl8169_set_features(struct net_device *dev, u32 features)
1571 {
1572         struct rtl8169_private *tp = netdev_priv(dev);
1573         void __iomem *ioaddr = tp->mmio_addr;
1574         unsigned long flags;
1575
1576         spin_lock_irqsave(&tp->lock, flags);
1577
1578         if (features & NETIF_F_RXCSUM)
1579                 tp->cp_cmd |= RxChkSum;
1580         else
1581                 tp->cp_cmd &= ~RxChkSum;
1582
1583         if (dev->features & NETIF_F_HW_VLAN_RX)
1584                 tp->cp_cmd |= RxVlan;
1585         else
1586                 tp->cp_cmd &= ~RxVlan;
1587
1588         RTL_W16(CPlusCmd, tp->cp_cmd);
1589         RTL_R16(CPlusCmd);
1590
1591         spin_unlock_irqrestore(&tp->lock, flags);
1592
1593         return 0;
1594 }
1595
1596 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1597                                       struct sk_buff *skb)
1598 {
1599         return (vlan_tx_tag_present(skb)) ?
1600                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1601 }
1602
1603 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1604 {
1605         u32 opts2 = le32_to_cpu(desc->opts2);
1606
1607         if (opts2 & RxVlanTag)
1608                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1609
1610         desc->opts2 = 0;
1611 }
1612
1613 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1614 {
1615         struct rtl8169_private *tp = netdev_priv(dev);
1616         void __iomem *ioaddr = tp->mmio_addr;
1617         u32 status;
1618
1619         cmd->supported =
1620                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1621         cmd->port = PORT_FIBRE;
1622         cmd->transceiver = XCVR_INTERNAL;
1623
1624         status = RTL_R32(TBICSR);
1625         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1626         cmd->autoneg = !!(status & TBINwEnable);
1627
1628         ethtool_cmd_speed_set(cmd, SPEED_1000);
1629         cmd->duplex = DUPLEX_FULL; /* Always set */
1630
1631         return 0;
1632 }
1633
1634 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1635 {
1636         struct rtl8169_private *tp = netdev_priv(dev);
1637
1638         return mii_ethtool_gset(&tp->mii, cmd);
1639 }
1640
1641 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1642 {
1643         struct rtl8169_private *tp = netdev_priv(dev);
1644         unsigned long flags;
1645         int rc;
1646
1647         spin_lock_irqsave(&tp->lock, flags);
1648
1649         rc = tp->get_settings(dev, cmd);
1650
1651         spin_unlock_irqrestore(&tp->lock, flags);
1652         return rc;
1653 }
1654
1655 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1656                              void *p)
1657 {
1658         struct rtl8169_private *tp = netdev_priv(dev);
1659         unsigned long flags;
1660
1661         if (regs->len > R8169_REGS_SIZE)
1662                 regs->len = R8169_REGS_SIZE;
1663
1664         spin_lock_irqsave(&tp->lock, flags);
1665         memcpy_fromio(p, tp->mmio_addr, regs->len);
1666         spin_unlock_irqrestore(&tp->lock, flags);
1667 }
1668
1669 static u32 rtl8169_get_msglevel(struct net_device *dev)
1670 {
1671         struct rtl8169_private *tp = netdev_priv(dev);
1672
1673         return tp->msg_enable;
1674 }
1675
1676 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1677 {
1678         struct rtl8169_private *tp = netdev_priv(dev);
1679
1680         tp->msg_enable = value;
1681 }
1682
1683 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1684         "tx_packets",
1685         "rx_packets",
1686         "tx_errors",
1687         "rx_errors",
1688         "rx_missed",
1689         "align_errors",
1690         "tx_single_collisions",
1691         "tx_multi_collisions",
1692         "unicast",
1693         "broadcast",
1694         "multicast",
1695         "tx_aborted",
1696         "tx_underrun",
1697 };
1698
1699 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1700 {
1701         switch (sset) {
1702         case ETH_SS_STATS:
1703                 return ARRAY_SIZE(rtl8169_gstrings);
1704         default:
1705                 return -EOPNOTSUPP;
1706         }
1707 }
1708
1709 static void rtl8169_update_counters(struct net_device *dev)
1710 {
1711         struct rtl8169_private *tp = netdev_priv(dev);
1712         void __iomem *ioaddr = tp->mmio_addr;
1713         struct device *d = &tp->pci_dev->dev;
1714         struct rtl8169_counters *counters;
1715         dma_addr_t paddr;
1716         u32 cmd;
1717         int wait = 1000;
1718
1719         /*
1720          * Some chips are unable to dump tally counters when the receiver
1721          * is disabled.
1722          */
1723         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1724                 return;
1725
1726         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1727         if (!counters)
1728                 return;
1729
1730         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1731         cmd = (u64)paddr & DMA_BIT_MASK(32);
1732         RTL_W32(CounterAddrLow, cmd);
1733         RTL_W32(CounterAddrLow, cmd | CounterDump);
1734
1735         while (wait--) {
1736                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1737                         memcpy(&tp->counters, counters, sizeof(*counters));
1738                         break;
1739                 }
1740                 udelay(10);
1741         }
1742
1743         RTL_W32(CounterAddrLow, 0);
1744         RTL_W32(CounterAddrHigh, 0);
1745
1746         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1747 }
1748
1749 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1750                                       struct ethtool_stats *stats, u64 *data)
1751 {
1752         struct rtl8169_private *tp = netdev_priv(dev);
1753
1754         ASSERT_RTNL();
1755
1756         rtl8169_update_counters(dev);
1757
1758         data[0] = le64_to_cpu(tp->counters.tx_packets);
1759         data[1] = le64_to_cpu(tp->counters.rx_packets);
1760         data[2] = le64_to_cpu(tp->counters.tx_errors);
1761         data[3] = le32_to_cpu(tp->counters.rx_errors);
1762         data[4] = le16_to_cpu(tp->counters.rx_missed);
1763         data[5] = le16_to_cpu(tp->counters.align_errors);
1764         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1765         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1766         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1767         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1768         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1769         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1770         data[12] = le16_to_cpu(tp->counters.tx_underun);
1771 }
1772
1773 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1774 {
1775         switch(stringset) {
1776         case ETH_SS_STATS:
1777                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1778                 break;
1779         }
1780 }
1781
1782 static const struct ethtool_ops rtl8169_ethtool_ops = {
1783         .get_drvinfo            = rtl8169_get_drvinfo,
1784         .get_regs_len           = rtl8169_get_regs_len,
1785         .get_link               = ethtool_op_get_link,
1786         .get_settings           = rtl8169_get_settings,
1787         .set_settings           = rtl8169_set_settings,
1788         .get_msglevel           = rtl8169_get_msglevel,
1789         .set_msglevel           = rtl8169_set_msglevel,
1790         .get_regs               = rtl8169_get_regs,
1791         .get_wol                = rtl8169_get_wol,
1792         .set_wol                = rtl8169_set_wol,
1793         .get_strings            = rtl8169_get_strings,
1794         .get_sset_count         = rtl8169_get_sset_count,
1795         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1796 };
1797
1798 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1799                                     struct net_device *dev, u8 default_version)
1800 {
1801         void __iomem *ioaddr = tp->mmio_addr;
1802         /*
1803          * The driver currently handles the 8168Bf and the 8168Be identically
1804          * but they can be identified more specifically through the test below
1805          * if needed:
1806          *
1807          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1808          *
1809          * Same thing for the 8101Eb and the 8101Ec:
1810          *
1811          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1812          */
1813         static const struct rtl_mac_info {
1814                 u32 mask;
1815                 u32 val;
1816                 int mac_version;
1817         } mac_info[] = {
1818                 /* 8168F family. */
1819                 { 0x7cf00000, 0x48100000,       RTL_GIGA_MAC_VER_36 },
1820                 { 0x7cf00000, 0x48000000,       RTL_GIGA_MAC_VER_35 },
1821
1822                 /* 8168E family. */
1823                 { 0x7c800000, 0x2c800000,       RTL_GIGA_MAC_VER_34 },
1824                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1825                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1826                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1827
1828                 /* 8168D family. */
1829                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1830                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1831                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1832
1833                 /* 8168DP family. */
1834                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1835                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1836                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1837
1838                 /* 8168C family. */
1839                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1840                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1841                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1842                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1843                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1844                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1845                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1846                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1847                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1848
1849                 /* 8168B family. */
1850                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1851                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1852                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1853                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1854
1855                 /* 8101 family. */
1856                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1857                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1858                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1859                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1860                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1861                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1862                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1863                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1864                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1865                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1866                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1867                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1868                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1869                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1870                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1871                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1872                 /* FIXME: where did these entries come from ? -- FR */
1873                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1874                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1875
1876                 /* 8110 family. */
1877                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1878                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1879                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1880                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1881                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1882                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1883
1884                 /* Catch-all */
1885                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1886         };
1887         const struct rtl_mac_info *p = mac_info;
1888         u32 reg;
1889
1890         reg = RTL_R32(TxConfig);
1891         while ((reg & p->mask) != p->val)
1892                 p++;
1893         tp->mac_version = p->mac_version;
1894
1895         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1896                 netif_notice(tp, probe, dev,
1897                              "unknown MAC, using family default\n");
1898                 tp->mac_version = default_version;
1899         }
1900 }
1901
1902 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1903 {
1904         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1905 }
1906
1907 struct phy_reg {
1908         u16 reg;
1909         u16 val;
1910 };
1911
1912 static void rtl_writephy_batch(struct rtl8169_private *tp,
1913                                const struct phy_reg *regs, int len)
1914 {
1915         while (len-- > 0) {
1916                 rtl_writephy(tp, regs->reg, regs->val);
1917                 regs++;
1918         }
1919 }
1920
1921 #define PHY_READ                0x00000000
1922 #define PHY_DATA_OR             0x10000000
1923 #define PHY_DATA_AND            0x20000000
1924 #define PHY_BJMPN               0x30000000
1925 #define PHY_READ_EFUSE          0x40000000
1926 #define PHY_READ_MAC_BYTE       0x50000000
1927 #define PHY_WRITE_MAC_BYTE      0x60000000
1928 #define PHY_CLEAR_READCOUNT     0x70000000
1929 #define PHY_WRITE               0x80000000
1930 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1931 #define PHY_COMP_EQ_SKIPN       0xa0000000
1932 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1933 #define PHY_WRITE_PREVIOUS      0xc0000000
1934 #define PHY_SKIPN               0xd0000000
1935 #define PHY_DELAY_MS            0xe0000000
1936 #define PHY_WRITE_ERI_WORD      0xf0000000
1937
1938 struct fw_info {
1939         u32     magic;
1940         char    version[RTL_VER_SIZE];
1941         __le32  fw_start;
1942         __le32  fw_len;
1943         u8      chksum;
1944 } __packed;
1945
1946 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1947
1948 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1949 {
1950         const struct firmware *fw = rtl_fw->fw;
1951         struct fw_info *fw_info = (struct fw_info *)fw->data;
1952         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1953         char *version = rtl_fw->version;
1954         bool rc = false;
1955
1956         if (fw->size < FW_OPCODE_SIZE)
1957                 goto out;
1958
1959         if (!fw_info->magic) {
1960                 size_t i, size, start;
1961                 u8 checksum = 0;
1962
1963                 if (fw->size < sizeof(*fw_info))
1964                         goto out;
1965
1966                 for (i = 0; i < fw->size; i++)
1967                         checksum += fw->data[i];
1968                 if (checksum != 0)
1969                         goto out;
1970
1971                 start = le32_to_cpu(fw_info->fw_start);
1972                 if (start > fw->size)
1973                         goto out;
1974
1975                 size = le32_to_cpu(fw_info->fw_len);
1976                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1977                         goto out;
1978
1979                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1980
1981                 pa->code = (__le32 *)(fw->data + start);
1982                 pa->size = size;
1983         } else {
1984                 if (fw->size % FW_OPCODE_SIZE)
1985                         goto out;
1986
1987                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1988
1989                 pa->code = (__le32 *)fw->data;
1990                 pa->size = fw->size / FW_OPCODE_SIZE;
1991         }
1992         version[RTL_VER_SIZE - 1] = 0;
1993
1994         rc = true;
1995 out:
1996         return rc;
1997 }
1998
1999 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2000                            struct rtl_fw_phy_action *pa)
2001 {
2002         bool rc = false;
2003         size_t index;
2004
2005         for (index = 0; index < pa->size; index++) {
2006                 u32 action = le32_to_cpu(pa->code[index]);
2007                 u32 regno = (action & 0x0fff0000) >> 16;
2008
2009                 switch(action & 0xf0000000) {
2010                 case PHY_READ:
2011                 case PHY_DATA_OR:
2012                 case PHY_DATA_AND:
2013                 case PHY_READ_EFUSE:
2014                 case PHY_CLEAR_READCOUNT:
2015                 case PHY_WRITE:
2016                 case PHY_WRITE_PREVIOUS:
2017                 case PHY_DELAY_MS:
2018                         break;
2019
2020                 case PHY_BJMPN:
2021                         if (regno > index) {
2022                                 netif_err(tp, ifup, tp->dev,
2023                                           "Out of range of firmware\n");
2024                                 goto out;
2025                         }
2026                         break;
2027                 case PHY_READCOUNT_EQ_SKIP:
2028                         if (index + 2 >= pa->size) {
2029                                 netif_err(tp, ifup, tp->dev,
2030                                           "Out of range of firmware\n");
2031                                 goto out;
2032                         }
2033                         break;
2034                 case PHY_COMP_EQ_SKIPN:
2035                 case PHY_COMP_NEQ_SKIPN:
2036                 case PHY_SKIPN:
2037                         if (index + 1 + regno >= pa->size) {
2038                                 netif_err(tp, ifup, tp->dev,
2039                                           "Out of range of firmware\n");
2040                                 goto out;
2041                         }
2042                         break;
2043
2044                 case PHY_READ_MAC_BYTE:
2045                 case PHY_WRITE_MAC_BYTE:
2046                 case PHY_WRITE_ERI_WORD:
2047                 default:
2048                         netif_err(tp, ifup, tp->dev,
2049                                   "Invalid action 0x%08x\n", action);
2050                         goto out;
2051                 }
2052         }
2053         rc = true;
2054 out:
2055         return rc;
2056 }
2057
2058 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2059 {
2060         struct net_device *dev = tp->dev;
2061         int rc = -EINVAL;
2062
2063         if (!rtl_fw_format_ok(tp, rtl_fw)) {
2064                 netif_err(tp, ifup, dev, "invalid firwmare\n");
2065                 goto out;
2066         }
2067
2068         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2069                 rc = 0;
2070 out:
2071         return rc;
2072 }
2073
2074 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2075 {
2076         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2077         u32 predata, count;
2078         size_t index;
2079
2080         predata = count = 0;
2081
2082         for (index = 0; index < pa->size; ) {
2083                 u32 action = le32_to_cpu(pa->code[index]);
2084                 u32 data = action & 0x0000ffff;
2085                 u32 regno = (action & 0x0fff0000) >> 16;
2086
2087                 if (!action)
2088                         break;
2089
2090                 switch(action & 0xf0000000) {
2091                 case PHY_READ:
2092                         predata = rtl_readphy(tp, regno);
2093                         count++;
2094                         index++;
2095                         break;
2096                 case PHY_DATA_OR:
2097                         predata |= data;
2098                         index++;
2099                         break;
2100                 case PHY_DATA_AND:
2101                         predata &= data;
2102                         index++;
2103                         break;
2104                 case PHY_BJMPN:
2105                         index -= regno;
2106                         break;
2107                 case PHY_READ_EFUSE:
2108                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2109                         index++;
2110                         break;
2111                 case PHY_CLEAR_READCOUNT:
2112                         count = 0;
2113                         index++;
2114                         break;
2115                 case PHY_WRITE:
2116                         rtl_writephy(tp, regno, data);
2117                         index++;
2118                         break;
2119                 case PHY_READCOUNT_EQ_SKIP:
2120                         index += (count == data) ? 2 : 1;
2121                         break;
2122                 case PHY_COMP_EQ_SKIPN:
2123                         if (predata == data)
2124                                 index += regno;
2125                         index++;
2126                         break;
2127                 case PHY_COMP_NEQ_SKIPN:
2128                         if (predata != data)
2129                                 index += regno;
2130                         index++;
2131                         break;
2132                 case PHY_WRITE_PREVIOUS:
2133                         rtl_writephy(tp, regno, predata);
2134                         index++;
2135                         break;
2136                 case PHY_SKIPN:
2137                         index += regno + 1;
2138                         break;
2139                 case PHY_DELAY_MS:
2140                         mdelay(data);
2141                         index++;
2142                         break;
2143
2144                 case PHY_READ_MAC_BYTE:
2145                 case PHY_WRITE_MAC_BYTE:
2146                 case PHY_WRITE_ERI_WORD:
2147                 default:
2148                         BUG();
2149                 }
2150         }
2151 }
2152
2153 static void rtl_release_firmware(struct rtl8169_private *tp)
2154 {
2155         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2156                 release_firmware(tp->rtl_fw->fw);
2157                 kfree(tp->rtl_fw);
2158         }
2159         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2160 }
2161
2162 static void rtl_apply_firmware(struct rtl8169_private *tp)
2163 {
2164         struct rtl_fw *rtl_fw = tp->rtl_fw;
2165
2166         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2167         if (!IS_ERR_OR_NULL(rtl_fw))
2168                 rtl_phy_write_fw(tp, rtl_fw);
2169 }
2170
2171 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2172 {
2173         if (rtl_readphy(tp, reg) != val)
2174                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2175         else
2176                 rtl_apply_firmware(tp);
2177 }
2178
2179 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2180 {
2181         static const struct phy_reg phy_reg_init[] = {
2182                 { 0x1f, 0x0001 },
2183                 { 0x06, 0x006e },
2184                 { 0x08, 0x0708 },
2185                 { 0x15, 0x4000 },
2186                 { 0x18, 0x65c7 },
2187
2188                 { 0x1f, 0x0001 },
2189                 { 0x03, 0x00a1 },
2190                 { 0x02, 0x0008 },
2191                 { 0x01, 0x0120 },
2192                 { 0x00, 0x1000 },
2193                 { 0x04, 0x0800 },
2194                 { 0x04, 0x0000 },
2195
2196                 { 0x03, 0xff41 },
2197                 { 0x02, 0xdf60 },
2198                 { 0x01, 0x0140 },
2199                 { 0x00, 0x0077 },
2200                 { 0x04, 0x7800 },
2201                 { 0x04, 0x7000 },
2202
2203                 { 0x03, 0x802f },
2204                 { 0x02, 0x4f02 },
2205                 { 0x01, 0x0409 },
2206                 { 0x00, 0xf0f9 },
2207                 { 0x04, 0x9800 },
2208                 { 0x04, 0x9000 },
2209
2210                 { 0x03, 0xdf01 },
2211                 { 0x02, 0xdf20 },
2212                 { 0x01, 0xff95 },
2213                 { 0x00, 0xba00 },
2214                 { 0x04, 0xa800 },
2215                 { 0x04, 0xa000 },
2216
2217                 { 0x03, 0xff41 },
2218                 { 0x02, 0xdf20 },
2219                 { 0x01, 0x0140 },
2220                 { 0x00, 0x00bb },
2221                 { 0x04, 0xb800 },
2222                 { 0x04, 0xb000 },
2223
2224                 { 0x03, 0xdf41 },
2225                 { 0x02, 0xdc60 },
2226                 { 0x01, 0x6340 },
2227                 { 0x00, 0x007d },
2228                 { 0x04, 0xd800 },
2229                 { 0x04, 0xd000 },
2230
2231                 { 0x03, 0xdf01 },
2232                 { 0x02, 0xdf20 },
2233                 { 0x01, 0x100a },
2234                 { 0x00, 0xa0ff },
2235                 { 0x04, 0xf800 },
2236                 { 0x04, 0xf000 },
2237
2238                 { 0x1f, 0x0000 },
2239                 { 0x0b, 0x0000 },
2240                 { 0x00, 0x9200 }
2241         };
2242
2243         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2244 }
2245
2246 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2247 {
2248         static const struct phy_reg phy_reg_init[] = {
2249                 { 0x1f, 0x0002 },
2250                 { 0x01, 0x90d0 },
2251                 { 0x1f, 0x0000 }
2252         };
2253
2254         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2255 }
2256
2257 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2258 {
2259         struct pci_dev *pdev = tp->pci_dev;
2260
2261         if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2262             (pdev->subsystem_device != 0xe000))
2263                 return;
2264
2265         rtl_writephy(tp, 0x1f, 0x0001);
2266         rtl_writephy(tp, 0x10, 0xf01b);
2267         rtl_writephy(tp, 0x1f, 0x0000);
2268 }
2269
2270 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2271 {
2272         static const struct phy_reg phy_reg_init[] = {
2273                 { 0x1f, 0x0001 },
2274                 { 0x04, 0x0000 },
2275                 { 0x03, 0x00a1 },
2276                 { 0x02, 0x0008 },
2277                 { 0x01, 0x0120 },
2278                 { 0x00, 0x1000 },
2279                 { 0x04, 0x0800 },
2280                 { 0x04, 0x9000 },
2281                 { 0x03, 0x802f },
2282                 { 0x02, 0x4f02 },
2283                 { 0x01, 0x0409 },
2284                 { 0x00, 0xf099 },
2285                 { 0x04, 0x9800 },
2286                 { 0x04, 0xa000 },
2287                 { 0x03, 0xdf01 },
2288                 { 0x02, 0xdf20 },
2289                 { 0x01, 0xff95 },
2290                 { 0x00, 0xba00 },
2291                 { 0x04, 0xa800 },
2292                 { 0x04, 0xf000 },
2293                 { 0x03, 0xdf01 },
2294                 { 0x02, 0xdf20 },
2295                 { 0x01, 0x101a },
2296                 { 0x00, 0xa0ff },
2297                 { 0x04, 0xf800 },
2298                 { 0x04, 0x0000 },
2299                 { 0x1f, 0x0000 },
2300
2301                 { 0x1f, 0x0001 },
2302                 { 0x10, 0xf41b },
2303                 { 0x14, 0xfb54 },
2304                 { 0x18, 0xf5c7 },
2305                 { 0x1f, 0x0000 },
2306
2307                 { 0x1f, 0x0001 },
2308                 { 0x17, 0x0cc0 },
2309                 { 0x1f, 0x0000 }
2310         };
2311
2312         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2313
2314         rtl8169scd_hw_phy_config_quirk(tp);
2315 }
2316
2317 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2318 {
2319         static const struct phy_reg phy_reg_init[] = {
2320                 { 0x1f, 0x0001 },
2321                 { 0x04, 0x0000 },
2322                 { 0x03, 0x00a1 },
2323                 { 0x02, 0x0008 },
2324                 { 0x01, 0x0120 },
2325                 { 0x00, 0x1000 },
2326                 { 0x04, 0x0800 },
2327                 { 0x04, 0x9000 },
2328                 { 0x03, 0x802f },
2329                 { 0x02, 0x4f02 },
2330                 { 0x01, 0x0409 },
2331                 { 0x00, 0xf099 },
2332                 { 0x04, 0x9800 },
2333                 { 0x04, 0xa000 },
2334                 { 0x03, 0xdf01 },
2335                 { 0x02, 0xdf20 },
2336                 { 0x01, 0xff95 },
2337                 { 0x00, 0xba00 },
2338                 { 0x04, 0xa800 },
2339                 { 0x04, 0xf000 },
2340                 { 0x03, 0xdf01 },
2341                 { 0x02, 0xdf20 },
2342                 { 0x01, 0x101a },
2343                 { 0x00, 0xa0ff },
2344                 { 0x04, 0xf800 },
2345                 { 0x04, 0x0000 },
2346                 { 0x1f, 0x0000 },
2347
2348                 { 0x1f, 0x0001 },
2349                 { 0x0b, 0x8480 },
2350                 { 0x1f, 0x0000 },
2351
2352                 { 0x1f, 0x0001 },
2353                 { 0x18, 0x67c7 },
2354                 { 0x04, 0x2000 },
2355                 { 0x03, 0x002f },
2356                 { 0x02, 0x4360 },
2357                 { 0x01, 0x0109 },
2358                 { 0x00, 0x3022 },
2359                 { 0x04, 0x2800 },
2360                 { 0x1f, 0x0000 },
2361
2362                 { 0x1f, 0x0001 },
2363                 { 0x17, 0x0cc0 },
2364                 { 0x1f, 0x0000 }
2365         };
2366
2367         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2368 }
2369
2370 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2371 {
2372         static const struct phy_reg phy_reg_init[] = {
2373                 { 0x10, 0xf41b },
2374                 { 0x1f, 0x0000 }
2375         };
2376
2377         rtl_writephy(tp, 0x1f, 0x0001);
2378         rtl_patchphy(tp, 0x16, 1 << 0);
2379
2380         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2381 }
2382
2383 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2384 {
2385         static const struct phy_reg phy_reg_init[] = {
2386                 { 0x1f, 0x0001 },
2387                 { 0x10, 0xf41b },
2388                 { 0x1f, 0x0000 }
2389         };
2390
2391         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2392 }
2393
2394 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2395 {
2396         static const struct phy_reg phy_reg_init[] = {
2397                 { 0x1f, 0x0000 },
2398                 { 0x1d, 0x0f00 },
2399                 { 0x1f, 0x0002 },
2400                 { 0x0c, 0x1ec8 },
2401                 { 0x1f, 0x0000 }
2402         };
2403
2404         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2405 }
2406
2407 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2408 {
2409         static const struct phy_reg phy_reg_init[] = {
2410                 { 0x1f, 0x0001 },
2411                 { 0x1d, 0x3d98 },
2412                 { 0x1f, 0x0000 }
2413         };
2414
2415         rtl_writephy(tp, 0x1f, 0x0000);
2416         rtl_patchphy(tp, 0x14, 1 << 5);
2417         rtl_patchphy(tp, 0x0d, 1 << 5);
2418
2419         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2420 }
2421
2422 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2423 {
2424         static const struct phy_reg phy_reg_init[] = {
2425                 { 0x1f, 0x0001 },
2426                 { 0x12, 0x2300 },
2427                 { 0x1f, 0x0002 },
2428                 { 0x00, 0x88d4 },
2429                 { 0x01, 0x82b1 },
2430                 { 0x03, 0x7002 },
2431                 { 0x08, 0x9e30 },
2432                 { 0x09, 0x01f0 },
2433                 { 0x0a, 0x5500 },
2434                 { 0x0c, 0x00c8 },
2435                 { 0x1f, 0x0003 },
2436                 { 0x12, 0xc096 },
2437                 { 0x16, 0x000a },
2438                 { 0x1f, 0x0000 },
2439                 { 0x1f, 0x0000 },
2440                 { 0x09, 0x2000 },
2441                 { 0x09, 0x0000 }
2442         };
2443
2444         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2445
2446         rtl_patchphy(tp, 0x14, 1 << 5);
2447         rtl_patchphy(tp, 0x0d, 1 << 5);
2448         rtl_writephy(tp, 0x1f, 0x0000);
2449 }
2450
2451 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2452 {
2453         static const struct phy_reg phy_reg_init[] = {
2454                 { 0x1f, 0x0001 },
2455                 { 0x12, 0x2300 },
2456                 { 0x03, 0x802f },
2457                 { 0x02, 0x4f02 },
2458                 { 0x01, 0x0409 },
2459                 { 0x00, 0xf099 },
2460                 { 0x04, 0x9800 },
2461                 { 0x04, 0x9000 },
2462                 { 0x1d, 0x3d98 },
2463                 { 0x1f, 0x0002 },
2464                 { 0x0c, 0x7eb8 },
2465                 { 0x06, 0x0761 },
2466                 { 0x1f, 0x0003 },
2467                 { 0x16, 0x0f0a },
2468                 { 0x1f, 0x0000 }
2469         };
2470
2471         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2472
2473         rtl_patchphy(tp, 0x16, 1 << 0);
2474         rtl_patchphy(tp, 0x14, 1 << 5);
2475         rtl_patchphy(tp, 0x0d, 1 << 5);
2476         rtl_writephy(tp, 0x1f, 0x0000);
2477 }
2478
2479 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2480 {
2481         static const struct phy_reg phy_reg_init[] = {
2482                 { 0x1f, 0x0001 },
2483                 { 0x12, 0x2300 },
2484                 { 0x1d, 0x3d98 },
2485                 { 0x1f, 0x0002 },
2486                 { 0x0c, 0x7eb8 },
2487                 { 0x06, 0x5461 },
2488                 { 0x1f, 0x0003 },
2489                 { 0x16, 0x0f0a },
2490                 { 0x1f, 0x0000 }
2491         };
2492
2493         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2494
2495         rtl_patchphy(tp, 0x16, 1 << 0);
2496         rtl_patchphy(tp, 0x14, 1 << 5);
2497         rtl_patchphy(tp, 0x0d, 1 << 5);
2498         rtl_writephy(tp, 0x1f, 0x0000);
2499 }
2500
2501 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2502 {
2503         rtl8168c_3_hw_phy_config(tp);
2504 }
2505
2506 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2507 {
2508         static const struct phy_reg phy_reg_init_0[] = {
2509                 /* Channel Estimation */
2510                 { 0x1f, 0x0001 },
2511                 { 0x06, 0x4064 },
2512                 { 0x07, 0x2863 },
2513                 { 0x08, 0x059c },
2514                 { 0x09, 0x26b4 },
2515                 { 0x0a, 0x6a19 },
2516                 { 0x0b, 0xdcc8 },
2517                 { 0x10, 0xf06d },
2518                 { 0x14, 0x7f68 },
2519                 { 0x18, 0x7fd9 },
2520                 { 0x1c, 0xf0ff },
2521                 { 0x1d, 0x3d9c },
2522                 { 0x1f, 0x0003 },
2523                 { 0x12, 0xf49f },
2524                 { 0x13, 0x070b },
2525                 { 0x1a, 0x05ad },
2526                 { 0x14, 0x94c0 },
2527
2528                 /*
2529                  * Tx Error Issue
2530                  * Enhance line driver power
2531                  */
2532                 { 0x1f, 0x0002 },
2533                 { 0x06, 0x5561 },
2534                 { 0x1f, 0x0005 },
2535                 { 0x05, 0x8332 },
2536                 { 0x06, 0x5561 },
2537
2538                 /*
2539                  * Can not link to 1Gbps with bad cable
2540                  * Decrease SNR threshold form 21.07dB to 19.04dB
2541                  */
2542                 { 0x1f, 0x0001 },
2543                 { 0x17, 0x0cc0 },
2544
2545                 { 0x1f, 0x0000 },
2546                 { 0x0d, 0xf880 }
2547         };
2548         void __iomem *ioaddr = tp->mmio_addr;
2549
2550         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2551
2552         /*
2553          * Rx Error Issue
2554          * Fine Tune Switching regulator parameter
2555          */
2556         rtl_writephy(tp, 0x1f, 0x0002);
2557         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2558         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2559
2560         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2561                 static const struct phy_reg phy_reg_init[] = {
2562                         { 0x1f, 0x0002 },
2563                         { 0x05, 0x669a },
2564                         { 0x1f, 0x0005 },
2565                         { 0x05, 0x8330 },
2566                         { 0x06, 0x669a },
2567                         { 0x1f, 0x0002 }
2568                 };
2569                 int val;
2570
2571                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2572
2573                 val = rtl_readphy(tp, 0x0d);
2574
2575                 if ((val & 0x00ff) != 0x006c) {
2576                         static const u32 set[] = {
2577                                 0x0065, 0x0066, 0x0067, 0x0068,
2578                                 0x0069, 0x006a, 0x006b, 0x006c
2579                         };
2580                         int i;
2581
2582                         rtl_writephy(tp, 0x1f, 0x0002);
2583
2584                         val &= 0xff00;
2585                         for (i = 0; i < ARRAY_SIZE(set); i++)
2586                                 rtl_writephy(tp, 0x0d, val | set[i]);
2587                 }
2588         } else {
2589                 static const struct phy_reg phy_reg_init[] = {
2590                         { 0x1f, 0x0002 },
2591                         { 0x05, 0x6662 },
2592                         { 0x1f, 0x0005 },
2593                         { 0x05, 0x8330 },
2594                         { 0x06, 0x6662 }
2595                 };
2596
2597                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2598         }
2599
2600         /* RSET couple improve */
2601         rtl_writephy(tp, 0x1f, 0x0002);
2602         rtl_patchphy(tp, 0x0d, 0x0300);
2603         rtl_patchphy(tp, 0x0f, 0x0010);
2604
2605         /* Fine tune PLL performance */
2606         rtl_writephy(tp, 0x1f, 0x0002);
2607         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2608         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2609
2610         rtl_writephy(tp, 0x1f, 0x0005);
2611         rtl_writephy(tp, 0x05, 0x001b);
2612
2613         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2614
2615         rtl_writephy(tp, 0x1f, 0x0000);
2616 }
2617
2618 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2619 {
2620         static const struct phy_reg phy_reg_init_0[] = {
2621                 /* Channel Estimation */
2622                 { 0x1f, 0x0001 },
2623                 { 0x06, 0x4064 },
2624                 { 0x07, 0x2863 },
2625                 { 0x08, 0x059c },
2626                 { 0x09, 0x26b4 },
2627                 { 0x0a, 0x6a19 },
2628                 { 0x0b, 0xdcc8 },
2629                 { 0x10, 0xf06d },
2630                 { 0x14, 0x7f68 },
2631                 { 0x18, 0x7fd9 },
2632                 { 0x1c, 0xf0ff },
2633                 { 0x1d, 0x3d9c },
2634                 { 0x1f, 0x0003 },
2635                 { 0x12, 0xf49f },
2636                 { 0x13, 0x070b },
2637                 { 0x1a, 0x05ad },
2638                 { 0x14, 0x94c0 },
2639
2640                 /*
2641                  * Tx Error Issue
2642                  * Enhance line driver power
2643                  */
2644                 { 0x1f, 0x0002 },
2645                 { 0x06, 0x5561 },
2646                 { 0x1f, 0x0005 },
2647                 { 0x05, 0x8332 },
2648                 { 0x06, 0x5561 },
2649
2650                 /*
2651                  * Can not link to 1Gbps with bad cable
2652                  * Decrease SNR threshold form 21.07dB to 19.04dB
2653                  */
2654                 { 0x1f, 0x0001 },
2655                 { 0x17, 0x0cc0 },
2656
2657                 { 0x1f, 0x0000 },
2658                 { 0x0d, 0xf880 }
2659         };
2660         void __iomem *ioaddr = tp->mmio_addr;
2661
2662         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2663
2664         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2665                 static const struct phy_reg phy_reg_init[] = {
2666                         { 0x1f, 0x0002 },
2667                         { 0x05, 0x669a },
2668                         { 0x1f, 0x0005 },
2669                         { 0x05, 0x8330 },
2670                         { 0x06, 0x669a },
2671
2672                         { 0x1f, 0x0002 }
2673                 };
2674                 int val;
2675
2676                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2677
2678                 val = rtl_readphy(tp, 0x0d);
2679                 if ((val & 0x00ff) != 0x006c) {
2680                         static const u32 set[] = {
2681                                 0x0065, 0x0066, 0x0067, 0x0068,
2682                                 0x0069, 0x006a, 0x006b, 0x006c
2683                         };
2684                         int i;
2685
2686                         rtl_writephy(tp, 0x1f, 0x0002);
2687
2688                         val &= 0xff00;
2689                         for (i = 0; i < ARRAY_SIZE(set); i++)
2690                                 rtl_writephy(tp, 0x0d, val | set[i]);
2691                 }
2692         } else {
2693                 static const struct phy_reg phy_reg_init[] = {
2694                         { 0x1f, 0x0002 },
2695                         { 0x05, 0x2642 },
2696                         { 0x1f, 0x0005 },
2697                         { 0x05, 0x8330 },
2698                         { 0x06, 0x2642 }
2699                 };
2700
2701                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2702         }
2703
2704         /* Fine tune PLL performance */
2705         rtl_writephy(tp, 0x1f, 0x0002);
2706         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2707         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2708
2709         /* Switching regulator Slew rate */
2710         rtl_writephy(tp, 0x1f, 0x0002);
2711         rtl_patchphy(tp, 0x0f, 0x0017);
2712
2713         rtl_writephy(tp, 0x1f, 0x0005);
2714         rtl_writephy(tp, 0x05, 0x001b);
2715
2716         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2717
2718         rtl_writephy(tp, 0x1f, 0x0000);
2719 }
2720
2721 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2722 {
2723         static const struct phy_reg phy_reg_init[] = {
2724                 { 0x1f, 0x0002 },
2725                 { 0x10, 0x0008 },
2726                 { 0x0d, 0x006c },
2727
2728                 { 0x1f, 0x0000 },
2729                 { 0x0d, 0xf880 },
2730
2731                 { 0x1f, 0x0001 },
2732                 { 0x17, 0x0cc0 },
2733
2734                 { 0x1f, 0x0001 },
2735                 { 0x0b, 0xa4d8 },
2736                 { 0x09, 0x281c },
2737                 { 0x07, 0x2883 },
2738                 { 0x0a, 0x6b35 },
2739                 { 0x1d, 0x3da4 },
2740                 { 0x1c, 0xeffd },
2741                 { 0x14, 0x7f52 },
2742                 { 0x18, 0x7fc6 },
2743                 { 0x08, 0x0601 },
2744                 { 0x06, 0x4063 },
2745                 { 0x10, 0xf074 },
2746                 { 0x1f, 0x0003 },
2747                 { 0x13, 0x0789 },
2748                 { 0x12, 0xf4bd },
2749                 { 0x1a, 0x04fd },
2750                 { 0x14, 0x84b0 },
2751                 { 0x1f, 0x0000 },
2752                 { 0x00, 0x9200 },
2753
2754                 { 0x1f, 0x0005 },
2755                 { 0x01, 0x0340 },
2756                 { 0x1f, 0x0001 },
2757                 { 0x04, 0x4000 },
2758                 { 0x03, 0x1d21 },
2759                 { 0x02, 0x0c32 },
2760                 { 0x01, 0x0200 },
2761                 { 0x00, 0x5554 },
2762                 { 0x04, 0x4800 },
2763                 { 0x04, 0x4000 },
2764                 { 0x04, 0xf000 },
2765                 { 0x03, 0xdf01 },
2766                 { 0x02, 0xdf20 },
2767                 { 0x01, 0x101a },
2768                 { 0x00, 0xa0ff },
2769                 { 0x04, 0xf800 },
2770                 { 0x04, 0xf000 },
2771                 { 0x1f, 0x0000 },
2772
2773                 { 0x1f, 0x0007 },
2774                 { 0x1e, 0x0023 },
2775                 { 0x16, 0x0000 },
2776                 { 0x1f, 0x0000 }
2777         };
2778
2779         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2780 }
2781
2782 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2783 {
2784         static const struct phy_reg phy_reg_init[] = {
2785                 { 0x1f, 0x0001 },
2786                 { 0x17, 0x0cc0 },
2787
2788                 { 0x1f, 0x0007 },
2789                 { 0x1e, 0x002d },
2790                 { 0x18, 0x0040 },
2791                 { 0x1f, 0x0000 }
2792         };
2793
2794         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2795         rtl_patchphy(tp, 0x0d, 1 << 5);
2796 }
2797
2798 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
2799 {
2800         static const struct phy_reg phy_reg_init[] = {
2801                 /* Enable Delay cap */
2802                 { 0x1f, 0x0005 },
2803                 { 0x05, 0x8b80 },
2804                 { 0x06, 0xc896 },
2805                 { 0x1f, 0x0000 },
2806
2807                 /* Channel estimation fine tune */
2808                 { 0x1f, 0x0001 },
2809                 { 0x0b, 0x6c20 },
2810                 { 0x07, 0x2872 },
2811                 { 0x1c, 0xefff },
2812                 { 0x1f, 0x0003 },
2813                 { 0x14, 0x6420 },
2814                 { 0x1f, 0x0000 },
2815
2816                 /* Update PFM & 10M TX idle timer */
2817                 { 0x1f, 0x0007 },
2818                 { 0x1e, 0x002f },
2819                 { 0x15, 0x1919 },
2820                 { 0x1f, 0x0000 },
2821
2822                 { 0x1f, 0x0007 },
2823                 { 0x1e, 0x00ac },
2824                 { 0x18, 0x0006 },
2825                 { 0x1f, 0x0000 }
2826         };
2827
2828         rtl_apply_firmware(tp);
2829
2830         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2831
2832         /* DCO enable for 10M IDLE Power */
2833         rtl_writephy(tp, 0x1f, 0x0007);
2834         rtl_writephy(tp, 0x1e, 0x0023);
2835         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2836         rtl_writephy(tp, 0x1f, 0x0000);
2837
2838         /* For impedance matching */
2839         rtl_writephy(tp, 0x1f, 0x0002);
2840         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2841         rtl_writephy(tp, 0x1f, 0x0000);
2842
2843         /* PHY auto speed down */
2844         rtl_writephy(tp, 0x1f, 0x0007);
2845         rtl_writephy(tp, 0x1e, 0x002d);
2846         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2847         rtl_writephy(tp, 0x1f, 0x0000);
2848         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2849
2850         rtl_writephy(tp, 0x1f, 0x0005);
2851         rtl_writephy(tp, 0x05, 0x8b86);
2852         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2853         rtl_writephy(tp, 0x1f, 0x0000);
2854
2855         rtl_writephy(tp, 0x1f, 0x0005);
2856         rtl_writephy(tp, 0x05, 0x8b85);
2857         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2858         rtl_writephy(tp, 0x1f, 0x0007);
2859         rtl_writephy(tp, 0x1e, 0x0020);
2860         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2861         rtl_writephy(tp, 0x1f, 0x0006);
2862         rtl_writephy(tp, 0x00, 0x5a00);
2863         rtl_writephy(tp, 0x1f, 0x0000);
2864         rtl_writephy(tp, 0x0d, 0x0007);
2865         rtl_writephy(tp, 0x0e, 0x003c);
2866         rtl_writephy(tp, 0x0d, 0x4007);
2867         rtl_writephy(tp, 0x0e, 0x0000);
2868         rtl_writephy(tp, 0x0d, 0x0000);
2869 }
2870
2871 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2872 {
2873         static const struct phy_reg phy_reg_init[] = {
2874                 /* Enable Delay cap */
2875                 { 0x1f, 0x0004 },
2876                 { 0x1f, 0x0007 },
2877                 { 0x1e, 0x00ac },
2878                 { 0x18, 0x0006 },
2879                 { 0x1f, 0x0002 },
2880                 { 0x1f, 0x0000 },
2881                 { 0x1f, 0x0000 },
2882
2883                 /* Channel estimation fine tune */
2884                 { 0x1f, 0x0003 },
2885                 { 0x09, 0xa20f },
2886                 { 0x1f, 0x0000 },
2887                 { 0x1f, 0x0000 },
2888
2889                 /* Green Setting */
2890                 { 0x1f, 0x0005 },
2891                 { 0x05, 0x8b5b },
2892                 { 0x06, 0x9222 },
2893                 { 0x05, 0x8b6d },
2894                 { 0x06, 0x8000 },
2895                 { 0x05, 0x8b76 },
2896                 { 0x06, 0x8000 },
2897                 { 0x1f, 0x0000 }
2898         };
2899
2900         rtl_apply_firmware(tp);
2901
2902         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2903
2904         /* For 4-corner performance improve */
2905         rtl_writephy(tp, 0x1f, 0x0005);
2906         rtl_writephy(tp, 0x05, 0x8b80);
2907         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2908         rtl_writephy(tp, 0x1f, 0x0000);
2909
2910         /* PHY auto speed down */
2911         rtl_writephy(tp, 0x1f, 0x0004);
2912         rtl_writephy(tp, 0x1f, 0x0007);
2913         rtl_writephy(tp, 0x1e, 0x002d);
2914         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2915         rtl_writephy(tp, 0x1f, 0x0002);
2916         rtl_writephy(tp, 0x1f, 0x0000);
2917         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2918
2919         /* improve 10M EEE waveform */
2920         rtl_writephy(tp, 0x1f, 0x0005);
2921         rtl_writephy(tp, 0x05, 0x8b86);
2922         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2923         rtl_writephy(tp, 0x1f, 0x0000);
2924
2925         /* Improve 2-pair detection performance */
2926         rtl_writephy(tp, 0x1f, 0x0005);
2927         rtl_writephy(tp, 0x05, 0x8b85);
2928         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2929         rtl_writephy(tp, 0x1f, 0x0000);
2930
2931         /* EEE setting */
2932         rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2933                      ERIAR_EXGMAC);
2934         rtl_writephy(tp, 0x1f, 0x0005);
2935         rtl_writephy(tp, 0x05, 0x8b85);
2936         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2937         rtl_writephy(tp, 0x1f, 0x0004);
2938         rtl_writephy(tp, 0x1f, 0x0007);
2939         rtl_writephy(tp, 0x1e, 0x0020);
2940         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0100);
2941         rtl_writephy(tp, 0x1f, 0x0002);
2942         rtl_writephy(tp, 0x1f, 0x0000);
2943         rtl_writephy(tp, 0x0d, 0x0007);
2944         rtl_writephy(tp, 0x0e, 0x003c);
2945         rtl_writephy(tp, 0x0d, 0x4007);
2946         rtl_writephy(tp, 0x0e, 0x0000);
2947         rtl_writephy(tp, 0x0d, 0x0000);
2948
2949         /* Green feature */
2950         rtl_writephy(tp, 0x1f, 0x0003);
2951         rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2952         rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2953         rtl_writephy(tp, 0x1f, 0x0000);
2954 }
2955
2956 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
2957 {
2958         static const struct phy_reg phy_reg_init[] = {
2959                 /* Channel estimation fine tune */
2960                 { 0x1f, 0x0003 },
2961                 { 0x09, 0xa20f },
2962                 { 0x1f, 0x0000 },
2963
2964                 /* Modify green table for giga & fnet */
2965                 { 0x1f, 0x0005 },
2966                 { 0x05, 0x8b55 },
2967                 { 0x06, 0x0000 },
2968                 { 0x05, 0x8b5e },
2969                 { 0x06, 0x0000 },
2970                 { 0x05, 0x8b67 },
2971                 { 0x06, 0x0000 },
2972                 { 0x05, 0x8b70 },
2973                 { 0x06, 0x0000 },
2974                 { 0x1f, 0x0000 },
2975                 { 0x1f, 0x0007 },
2976                 { 0x1e, 0x0078 },
2977                 { 0x17, 0x0000 },
2978                 { 0x19, 0x00fb },
2979                 { 0x1f, 0x0000 },
2980
2981                 /* Modify green table for 10M */
2982                 { 0x1f, 0x0005 },
2983                 { 0x05, 0x8b79 },
2984                 { 0x06, 0xaa00 },
2985                 { 0x1f, 0x0000 },
2986
2987                 /* Disable hiimpedance detection (RTCT) */
2988                 { 0x1f, 0x0003 },
2989                 { 0x01, 0x328a },
2990                 { 0x1f, 0x0000 }
2991         };
2992
2993         rtl_apply_firmware(tp);
2994
2995         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2996
2997         /* For 4-corner performance improve */
2998         rtl_writephy(tp, 0x1f, 0x0005);
2999         rtl_writephy(tp, 0x05, 0x8b80);
3000         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3001         rtl_writephy(tp, 0x1f, 0x0000);
3002
3003         /* PHY auto speed down */
3004         rtl_writephy(tp, 0x1f, 0x0007);
3005         rtl_writephy(tp, 0x1e, 0x002d);
3006         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3007         rtl_writephy(tp, 0x1f, 0x0000);
3008         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3009
3010         /* Improve 10M EEE waveform */
3011         rtl_writephy(tp, 0x1f, 0x0005);
3012         rtl_writephy(tp, 0x05, 0x8b86);
3013         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3014         rtl_writephy(tp, 0x1f, 0x0000);
3015
3016         /* Improve 2-pair detection performance */
3017         rtl_writephy(tp, 0x1f, 0x0005);
3018         rtl_writephy(tp, 0x05, 0x8b85);
3019         rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
3020         rtl_writephy(tp, 0x1f, 0x0000);
3021 }
3022
3023 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3024 {
3025         rtl_apply_firmware(tp);
3026
3027         /* For 4-corner performance improve */
3028         rtl_writephy(tp, 0x1f, 0x0005);
3029         rtl_writephy(tp, 0x05, 0x8b80);
3030         rtl_w1w0_phy(tp, 0x06, 0x0006, 0x0000);
3031         rtl_writephy(tp, 0x1f, 0x0000);
3032
3033         /* PHY auto speed down */
3034         rtl_writephy(tp, 0x1f, 0x0007);
3035         rtl_writephy(tp, 0x1e, 0x002d);
3036         rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
3037         rtl_writephy(tp, 0x1f, 0x0000);
3038         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
3039
3040         /* Improve 10M EEE waveform */
3041         rtl_writephy(tp, 0x1f, 0x0005);
3042         rtl_writephy(tp, 0x05, 0x8b86);
3043         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
3044         rtl_writephy(tp, 0x1f, 0x0000);
3045 }
3046
3047 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3048 {
3049         static const struct phy_reg phy_reg_init[] = {
3050                 { 0x1f, 0x0003 },
3051                 { 0x08, 0x441d },
3052                 { 0x01, 0x9100 },
3053                 { 0x1f, 0x0000 }
3054         };
3055
3056         rtl_writephy(tp, 0x1f, 0x0000);
3057         rtl_patchphy(tp, 0x11, 1 << 12);
3058         rtl_patchphy(tp, 0x19, 1 << 13);
3059         rtl_patchphy(tp, 0x10, 1 << 15);
3060
3061         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3062 }
3063
3064 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3065 {
3066         static const struct phy_reg phy_reg_init[] = {
3067                 { 0x1f, 0x0005 },
3068                 { 0x1a, 0x0000 },
3069                 { 0x1f, 0x0000 },
3070
3071                 { 0x1f, 0x0004 },
3072                 { 0x1c, 0x0000 },
3073                 { 0x1f, 0x0000 },
3074
3075                 { 0x1f, 0x0001 },
3076                 { 0x15, 0x7701 },
3077                 { 0x1f, 0x0000 }
3078         };
3079
3080         /* Disable ALDPS before ram code */
3081         rtl_writephy(tp, 0x1f, 0x0000);
3082         rtl_writephy(tp, 0x18, 0x0310);
3083         msleep(100);
3084
3085         rtl_apply_firmware(tp);
3086
3087         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3088 }
3089
3090 static void rtl_hw_phy_config(struct net_device *dev)
3091 {
3092         struct rtl8169_private *tp = netdev_priv(dev);
3093
3094         rtl8169_print_mac_version(tp);
3095
3096         switch (tp->mac_version) {
3097         case RTL_GIGA_MAC_VER_01:
3098                 break;
3099         case RTL_GIGA_MAC_VER_02:
3100         case RTL_GIGA_MAC_VER_03:
3101                 rtl8169s_hw_phy_config(tp);
3102                 break;
3103         case RTL_GIGA_MAC_VER_04:
3104                 rtl8169sb_hw_phy_config(tp);
3105                 break;
3106         case RTL_GIGA_MAC_VER_05:
3107                 rtl8169scd_hw_phy_config(tp);
3108                 break;
3109         case RTL_GIGA_MAC_VER_06:
3110                 rtl8169sce_hw_phy_config(tp);
3111                 break;
3112         case RTL_GIGA_MAC_VER_07:
3113         case RTL_GIGA_MAC_VER_08:
3114         case RTL_GIGA_MAC_VER_09:
3115                 rtl8102e_hw_phy_config(tp);
3116                 break;
3117         case RTL_GIGA_MAC_VER_11:
3118                 rtl8168bb_hw_phy_config(tp);
3119                 break;
3120         case RTL_GIGA_MAC_VER_12:
3121                 rtl8168bef_hw_phy_config(tp);
3122                 break;
3123         case RTL_GIGA_MAC_VER_17:
3124                 rtl8168bef_hw_phy_config(tp);
3125                 break;
3126         case RTL_GIGA_MAC_VER_18:
3127                 rtl8168cp_1_hw_phy_config(tp);
3128                 break;
3129         case RTL_GIGA_MAC_VER_19:
3130                 rtl8168c_1_hw_phy_config(tp);
3131                 break;
3132         case RTL_GIGA_MAC_VER_20:
3133                 rtl8168c_2_hw_phy_config(tp);
3134                 break;
3135         case RTL_GIGA_MAC_VER_21:
3136                 rtl8168c_3_hw_phy_config(tp);
3137                 break;
3138         case RTL_GIGA_MAC_VER_22:
3139                 rtl8168c_4_hw_phy_config(tp);
3140                 break;
3141         case RTL_GIGA_MAC_VER_23:
3142         case RTL_GIGA_MAC_VER_24:
3143                 rtl8168cp_2_hw_phy_config(tp);
3144                 break;
3145         case RTL_GIGA_MAC_VER_25:
3146                 rtl8168d_1_hw_phy_config(tp);
3147                 break;
3148         case RTL_GIGA_MAC_VER_26:
3149                 rtl8168d_2_hw_phy_config(tp);
3150                 break;
3151         case RTL_GIGA_MAC_VER_27:
3152                 rtl8168d_3_hw_phy_config(tp);
3153                 break;
3154         case RTL_GIGA_MAC_VER_28:
3155                 rtl8168d_4_hw_phy_config(tp);
3156                 break;
3157         case RTL_GIGA_MAC_VER_29:
3158         case RTL_GIGA_MAC_VER_30:
3159                 rtl8105e_hw_phy_config(tp);
3160                 break;
3161         case RTL_GIGA_MAC_VER_31:
3162                 /* None. */
3163                 break;
3164         case RTL_GIGA_MAC_VER_32:
3165         case RTL_GIGA_MAC_VER_33:
3166                 rtl8168e_1_hw_phy_config(tp);
3167                 break;
3168         case RTL_GIGA_MAC_VER_34:
3169                 rtl8168e_2_hw_phy_config(tp);
3170                 break;
3171         case RTL_GIGA_MAC_VER_35:
3172                 rtl8168f_1_hw_phy_config(tp);
3173                 break;
3174         case RTL_GIGA_MAC_VER_36:
3175                 rtl8168f_2_hw_phy_config(tp);
3176                 break;
3177
3178         default:
3179                 break;
3180         }
3181 }
3182
3183 static void rtl8169_phy_timer(unsigned long __opaque)
3184 {
3185         struct net_device *dev = (struct net_device *)__opaque;
3186         struct rtl8169_private *tp = netdev_priv(dev);
3187         struct timer_list *timer = &tp->timer;
3188         void __iomem *ioaddr = tp->mmio_addr;
3189         unsigned long timeout = RTL8169_PHY_TIMEOUT;
3190
3191         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
3192
3193         spin_lock_irq(&tp->lock);
3194
3195         if (tp->phy_reset_pending(tp)) {
3196                 /*
3197                  * A busy loop could burn quite a few cycles on nowadays CPU.
3198                  * Let's delay the execution of the timer for a few ticks.
3199                  */
3200                 timeout = HZ/10;
3201                 goto out_mod_timer;
3202         }
3203
3204         if (tp->link_ok(ioaddr))
3205                 goto out_unlock;
3206
3207         netif_warn(tp, link, dev, "PHY reset until link up\n");
3208
3209         tp->phy_reset_enable(tp);
3210
3211 out_mod_timer:
3212         mod_timer(timer, jiffies + timeout);
3213 out_unlock:
3214         spin_unlock_irq(&tp->lock);
3215 }
3216
3217 #ifdef CONFIG_NET_POLL_CONTROLLER
3218 /*
3219  * Polling 'interrupt' - used by things like netconsole to send skbs
3220  * without having to re-enable interrupts. It's not called while
3221  * the interrupt routine is executing.
3222  */
3223 static void rtl8169_netpoll(struct net_device *dev)
3224 {
3225         struct rtl8169_private *tp = netdev_priv(dev);
3226         struct pci_dev *pdev = tp->pci_dev;
3227
3228         disable_irq(pdev->irq);
3229         rtl8169_interrupt(pdev->irq, dev);
3230         enable_irq(pdev->irq);
3231 }
3232 #endif
3233
3234 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3235                                   void __iomem *ioaddr)
3236 {
3237         iounmap(ioaddr);
3238         pci_release_regions(pdev);
3239         pci_clear_mwi(pdev);
3240         pci_disable_device(pdev);
3241         free_netdev(dev);
3242 }
3243
3244 static void rtl8169_phy_reset(struct net_device *dev,
3245                               struct rtl8169_private *tp)
3246 {
3247         unsigned int i;
3248
3249         tp->phy_reset_enable(tp);
3250         for (i = 0; i < 100; i++) {
3251                 if (!tp->phy_reset_pending(tp))
3252                         return;
3253                 msleep(1);
3254         }
3255         netif_err(tp, link, dev, "PHY reset failed\n");
3256 }
3257
3258 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
3259 {
3260         void __iomem *ioaddr = tp->mmio_addr;
3261
3262         return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
3263             (RTL_R8(PHYstatus) & TBI_Enable);
3264 }
3265
3266 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3267 {
3268         void __iomem *ioaddr = tp->mmio_addr;
3269
3270         rtl_hw_phy_config(dev);
3271
3272         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3273                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3274                 RTL_W8(0x82, 0x01);
3275         }
3276
3277         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3278
3279         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3280                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3281
3282         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
3283                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3284                 RTL_W8(0x82, 0x01);
3285                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
3286                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
3287         }
3288
3289         rtl8169_phy_reset(dev, tp);
3290
3291         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
3292                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3293                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3294                           (tp->mii.supports_gmii ?
3295                            ADVERTISED_1000baseT_Half |
3296                            ADVERTISED_1000baseT_Full : 0));
3297
3298         if (rtl_tbi_enabled(tp))
3299                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
3300 }
3301
3302 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3303 {
3304         void __iomem *ioaddr = tp->mmio_addr;
3305         u32 high;
3306         u32 low;
3307
3308         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3309         high = addr[4] | (addr[5] << 8);
3310
3311         spin_lock_irq(&tp->lock);
3312
3313         RTL_W8(Cfg9346, Cfg9346_Unlock);
3314
3315         RTL_W32(MAC4, high);
3316         RTL_R32(MAC4);
3317
3318         RTL_W32(MAC0, low);
3319         RTL_R32(MAC0);
3320
3321         if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3322                 const struct exgmac_reg e[] = {
3323                         { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3324                         { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3325                         { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3326                         { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3327                                                                 low  >> 16 },
3328                 };
3329
3330                 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3331         }
3332
3333         RTL_W8(Cfg9346, Cfg9346_Lock);
3334
3335         spin_unlock_irq(&tp->lock);
3336 }
3337
3338 static int rtl_set_mac_address(struct net_device *dev, void *p)
3339 {
3340         struct rtl8169_private *tp = netdev_priv(dev);
3341         struct sockaddr *addr = p;
3342
3343         if (!is_valid_ether_addr(addr->sa_data))
3344                 return -EADDRNOTAVAIL;
3345
3346         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3347
3348         rtl_rar_set(tp, dev->dev_addr);
3349
3350         return 0;
3351 }
3352
3353 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3354 {
3355         struct rtl8169_private *tp = netdev_priv(dev);
3356         struct mii_ioctl_data *data = if_mii(ifr);
3357
3358         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3359 }
3360
3361 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3362                           struct mii_ioctl_data *data, int cmd)
3363 {
3364         switch (cmd) {
3365         case SIOCGMIIPHY:
3366                 data->phy_id = 32; /* Internal PHY */
3367                 return 0;
3368
3369         case SIOCGMIIREG:
3370                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
3371                 return 0;
3372
3373         case SIOCSMIIREG:
3374                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
3375                 return 0;
3376         }
3377         return -EOPNOTSUPP;
3378 }
3379
3380 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3381 {
3382         return -EOPNOTSUPP;
3383 }
3384
3385 static const struct rtl_cfg_info {
3386         void (*hw_start)(struct net_device *);
3387         unsigned int region;
3388         unsigned int align;
3389         u16 intr_event;
3390         u16 napi_event;
3391         unsigned features;
3392         u8 default_ver;
3393 } rtl_cfg_infos [] = {
3394         [RTL_CFG_0] = {
3395                 .hw_start       = rtl_hw_start_8169,
3396                 .region         = 1,
3397                 .align          = 0,
3398                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3399                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3400                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3401                 .features       = RTL_FEATURE_GMII,
3402                 .default_ver    = RTL_GIGA_MAC_VER_01,
3403         },
3404         [RTL_CFG_1] = {
3405                 .hw_start       = rtl_hw_start_8168,
3406                 .region         = 2,
3407                 .align          = 8,
3408                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3409                                   TxErr | TxOK | RxOK | RxErr,
3410                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3411                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3412                 .default_ver    = RTL_GIGA_MAC_VER_11,
3413         },
3414         [RTL_CFG_2] = {
3415                 .hw_start       = rtl_hw_start_8101,
3416                 .region         = 2,
3417                 .align          = 8,
3418                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3419                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3420                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3421                 .features       = RTL_FEATURE_MSI,
3422                 .default_ver    = RTL_GIGA_MAC_VER_13,
3423         }
3424 };
3425
3426 /* Cfg9346_Unlock assumed. */
3427 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3428                             const struct rtl_cfg_info *cfg)
3429 {
3430         unsigned msi = 0;
3431         u8 cfg2;
3432
3433         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3434         if (cfg->features & RTL_FEATURE_MSI) {
3435                 if (pci_enable_msi(pdev)) {
3436                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3437                 } else {
3438                         cfg2 |= MSIEnable;
3439                         msi = RTL_FEATURE_MSI;
3440                 }
3441         }
3442         RTL_W8(Config2, cfg2);
3443         return msi;
3444 }
3445
3446 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3447 {
3448         if (tp->features & RTL_FEATURE_MSI) {
3449                 pci_disable_msi(pdev);
3450                 tp->features &= ~RTL_FEATURE_MSI;
3451         }
3452 }
3453
3454 static const struct net_device_ops rtl8169_netdev_ops = {
3455         .ndo_open               = rtl8169_open,
3456         .ndo_stop               = rtl8169_close,
3457         .ndo_get_stats          = rtl8169_get_stats,
3458         .ndo_start_xmit         = rtl8169_start_xmit,
3459         .ndo_tx_timeout         = rtl8169_tx_timeout,
3460         .ndo_validate_addr      = eth_validate_addr,
3461         .ndo_change_mtu         = rtl8169_change_mtu,
3462         .ndo_fix_features       = rtl8169_fix_features,
3463         .ndo_set_features       = rtl8169_set_features,
3464         .ndo_set_mac_address    = rtl_set_mac_address,
3465         .ndo_do_ioctl           = rtl8169_ioctl,
3466         .ndo_set_rx_mode        = rtl_set_rx_mode,
3467 #ifdef CONFIG_NET_POLL_CONTROLLER
3468         .ndo_poll_controller    = rtl8169_netpoll,
3469 #endif
3470
3471 };
3472
3473 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3474 {
3475         struct mdio_ops *ops = &tp->mdio_ops;
3476
3477         switch (tp->mac_version) {
3478         case RTL_GIGA_MAC_VER_27:
3479                 ops->write      = r8168dp_1_mdio_write;
3480                 ops->read       = r8168dp_1_mdio_read;
3481                 break;
3482         case RTL_GIGA_MAC_VER_28:
3483         case RTL_GIGA_MAC_VER_31:
3484                 ops->write      = r8168dp_2_mdio_write;
3485                 ops->read       = r8168dp_2_mdio_read;
3486                 break;
3487         default:
3488                 ops->write      = r8169_mdio_write;
3489                 ops->read       = r8169_mdio_read;
3490                 break;
3491         }
3492 }
3493
3494 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
3495 {
3496         void __iomem *ioaddr = tp->mmio_addr;
3497
3498         switch (tp->mac_version) {
3499         case RTL_GIGA_MAC_VER_29:
3500         case RTL_GIGA_MAC_VER_30:
3501         case RTL_GIGA_MAC_VER_32:
3502         case RTL_GIGA_MAC_VER_33:
3503         case RTL_GIGA_MAC_VER_34:
3504                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3505                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3506                 break;
3507         default:
3508                 break;
3509         }
3510 }
3511
3512 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
3513 {
3514         if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
3515                 return false;
3516
3517         rtl_writephy(tp, 0x1f, 0x0000);
3518         rtl_writephy(tp, MII_BMCR, 0x0000);
3519
3520         rtl_wol_suspend_quirk(tp);
3521
3522         return true;
3523 }
3524
3525 static void r810x_phy_power_down(struct rtl8169_private *tp)
3526 {
3527         rtl_writephy(tp, 0x1f, 0x0000);
3528         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3529 }
3530
3531 static void r810x_phy_power_up(struct rtl8169_private *tp)
3532 {
3533         rtl_writephy(tp, 0x1f, 0x0000);
3534         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3535 }
3536
3537 static void r810x_pll_power_down(struct rtl8169_private *tp)
3538 {
3539         if (rtl_wol_pll_power_down(tp))
3540                 return;
3541
3542         r810x_phy_power_down(tp);
3543 }
3544
3545 static void r810x_pll_power_up(struct rtl8169_private *tp)
3546 {
3547         r810x_phy_power_up(tp);
3548 }
3549
3550 static void r8168_phy_power_up(struct rtl8169_private *tp)
3551 {
3552         rtl_writephy(tp, 0x1f, 0x0000);
3553         switch (tp->mac_version) {
3554         case RTL_GIGA_MAC_VER_11:
3555         case RTL_GIGA_MAC_VER_12:
3556         case RTL_GIGA_MAC_VER_17:
3557         case RTL_GIGA_MAC_VER_18:
3558         case RTL_GIGA_MAC_VER_19:
3559         case RTL_GIGA_MAC_VER_20:
3560         case RTL_GIGA_MAC_VER_21:
3561         case RTL_GIGA_MAC_VER_22:
3562         case RTL_GIGA_MAC_VER_23:
3563         case RTL_GIGA_MAC_VER_24:
3564         case RTL_GIGA_MAC_VER_25:
3565         case RTL_GIGA_MAC_VER_26:
3566         case RTL_GIGA_MAC_VER_27:
3567         case RTL_GIGA_MAC_VER_28:
3568         case RTL_GIGA_MAC_VER_31:
3569                 rtl_writephy(tp, 0x0e, 0x0000);
3570                 break;
3571         default:
3572                 break;
3573         }
3574         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3575 }
3576
3577 static void r8168_phy_power_down(struct rtl8169_private *tp)
3578 {
3579         rtl_writephy(tp, 0x1f, 0x0000);
3580         switch (tp->mac_version) {
3581         case RTL_GIGA_MAC_VER_32:
3582         case RTL_GIGA_MAC_VER_33:
3583                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3584                 break;
3585
3586         case RTL_GIGA_MAC_VER_11:
3587         case RTL_GIGA_MAC_VER_12:
3588         case RTL_GIGA_MAC_VER_17:
3589         case RTL_GIGA_MAC_VER_18:
3590         case RTL_GIGA_MAC_VER_19:
3591         case RTL_GIGA_MAC_VER_20:
3592         case RTL_GIGA_MAC_VER_21:
3593         case RTL_GIGA_MAC_VER_22:
3594         case RTL_GIGA_MAC_VER_23:
3595         case RTL_GIGA_MAC_VER_24:
3596         case RTL_GIGA_MAC_VER_25:
3597         case RTL_GIGA_MAC_VER_26:
3598         case RTL_GIGA_MAC_VER_27:
3599         case RTL_GIGA_MAC_VER_28:
3600         case RTL_GIGA_MAC_VER_31:
3601                 rtl_writephy(tp, 0x0e, 0x0200);
3602         default:
3603                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3604                 break;
3605         }
3606 }
3607
3608 static void r8168_pll_power_down(struct rtl8169_private *tp)
3609 {
3610         void __iomem *ioaddr = tp->mmio_addr;
3611
3612         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3613              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3614              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3615             r8168dp_check_dash(tp)) {
3616                 return;
3617         }
3618
3619         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3620              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3621             (RTL_R16(CPlusCmd) & ASF)) {
3622                 return;
3623         }
3624
3625         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3626             tp->mac_version == RTL_GIGA_MAC_VER_33)
3627                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3628
3629         if (rtl_wol_pll_power_down(tp))
3630                 return;
3631
3632         r8168_phy_power_down(tp);
3633
3634         switch (tp->mac_version) {
3635         case RTL_GIGA_MAC_VER_25:
3636         case RTL_GIGA_MAC_VER_26:
3637         case RTL_GIGA_MAC_VER_27:
3638         case RTL_GIGA_MAC_VER_28:
3639         case RTL_GIGA_MAC_VER_31:
3640         case RTL_GIGA_MAC_VER_32:
3641         case RTL_GIGA_MAC_VER_33:
3642                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3643                 break;
3644         }
3645 }
3646
3647 static void r8168_pll_power_up(struct rtl8169_private *tp)
3648 {
3649         void __iomem *ioaddr = tp->mmio_addr;
3650
3651         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3652              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3653              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3654             r8168dp_check_dash(tp)) {
3655                 return;
3656         }
3657
3658         switch (tp->mac_version) {
3659         case RTL_GIGA_MAC_VER_25:
3660         case RTL_GIGA_MAC_VER_26:
3661         case RTL_GIGA_MAC_VER_27:
3662         case RTL_GIGA_MAC_VER_28:
3663         case RTL_GIGA_MAC_VER_31:
3664         case RTL_GIGA_MAC_VER_32:
3665         case RTL_GIGA_MAC_VER_33:
3666                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3667                 break;
3668         }
3669
3670         r8168_phy_power_up(tp);
3671 }
3672
3673 static void rtl_generic_op(struct rtl8169_private *tp,
3674                            void (*op)(struct rtl8169_private *))
3675 {
3676         if (op)
3677                 op(tp);
3678 }
3679
3680 static void rtl_pll_power_down(struct rtl8169_private *tp)
3681 {
3682         rtl_generic_op(tp, tp->pll_power_ops.down);
3683 }
3684
3685 static void rtl_pll_power_up(struct rtl8169_private *tp)
3686 {
3687         rtl_generic_op(tp, tp->pll_power_ops.up);
3688 }
3689
3690 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3691 {
3692         struct pll_power_ops *ops = &tp->pll_power_ops;
3693
3694         switch (tp->mac_version) {
3695         case RTL_GIGA_MAC_VER_07:
3696         case RTL_GIGA_MAC_VER_08:
3697         case RTL_GIGA_MAC_VER_09:
3698         case RTL_GIGA_MAC_VER_10:
3699         case RTL_GIGA_MAC_VER_16:
3700         case RTL_GIGA_MAC_VER_29:
3701         case RTL_GIGA_MAC_VER_30:
3702                 ops->down       = r810x_pll_power_down;
3703                 ops->up         = r810x_pll_power_up;
3704                 break;
3705
3706         case RTL_GIGA_MAC_VER_11:
3707         case RTL_GIGA_MAC_VER_12:
3708         case RTL_GIGA_MAC_VER_17:
3709         case RTL_GIGA_MAC_VER_18:
3710         case RTL_GIGA_MAC_VER_19:
3711         case RTL_GIGA_MAC_VER_20:
3712         case RTL_GIGA_MAC_VER_21:
3713         case RTL_GIGA_MAC_VER_22:
3714         case RTL_GIGA_MAC_VER_23:
3715         case RTL_GIGA_MAC_VER_24:
3716         case RTL_GIGA_MAC_VER_25:
3717         case RTL_GIGA_MAC_VER_26:
3718         case RTL_GIGA_MAC_VER_27:
3719         case RTL_GIGA_MAC_VER_28:
3720         case RTL_GIGA_MAC_VER_31:
3721         case RTL_GIGA_MAC_VER_32:
3722         case RTL_GIGA_MAC_VER_33:
3723         case RTL_GIGA_MAC_VER_34:
3724         case RTL_GIGA_MAC_VER_35:
3725         case RTL_GIGA_MAC_VER_36:
3726                 ops->down       = r8168_pll_power_down;
3727                 ops->up         = r8168_pll_power_up;
3728                 break;
3729
3730         default:
3731                 ops->down       = NULL;
3732                 ops->up         = NULL;
3733                 break;
3734         }
3735 }
3736
3737 static void rtl_init_rxcfg(struct rtl8169_private *tp)
3738 {
3739         void __iomem *ioaddr = tp->mmio_addr;
3740
3741         switch (tp->mac_version) {
3742         case RTL_GIGA_MAC_VER_01:
3743         case RTL_GIGA_MAC_VER_02:
3744         case RTL_GIGA_MAC_VER_03:
3745         case RTL_GIGA_MAC_VER_04:
3746         case RTL_GIGA_MAC_VER_05:
3747         case RTL_GIGA_MAC_VER_06:
3748         case RTL_GIGA_MAC_VER_10:
3749         case RTL_GIGA_MAC_VER_11:
3750         case RTL_GIGA_MAC_VER_12:
3751         case RTL_GIGA_MAC_VER_13:
3752         case RTL_GIGA_MAC_VER_14:
3753         case RTL_GIGA_MAC_VER_15:
3754         case RTL_GIGA_MAC_VER_16:
3755         case RTL_GIGA_MAC_VER_17:
3756                 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3757                 break;
3758         case RTL_GIGA_MAC_VER_18:
3759         case RTL_GIGA_MAC_VER_19:
3760         case RTL_GIGA_MAC_VER_20:
3761         case RTL_GIGA_MAC_VER_21:
3762         case RTL_GIGA_MAC_VER_22:
3763         case RTL_GIGA_MAC_VER_23:
3764         case RTL_GIGA_MAC_VER_24:
3765                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3766                 break;
3767         default:
3768                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3769                 break;
3770         }
3771 }
3772
3773 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3774 {
3775         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3776 }
3777
3778 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
3779 {
3780         rtl_generic_op(tp, tp->jumbo_ops.enable);
3781 }
3782
3783 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
3784 {
3785         rtl_generic_op(tp, tp->jumbo_ops.disable);
3786 }
3787
3788 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
3789 {
3790         void __iomem *ioaddr = tp->mmio_addr;
3791
3792         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3793         RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
3794         rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
3795 }
3796
3797 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
3798 {
3799         void __iomem *ioaddr = tp->mmio_addr;
3800
3801         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3802         RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
3803         rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
3804 }
3805
3806 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
3807 {
3808         void __iomem *ioaddr = tp->mmio_addr;
3809
3810         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3811 }
3812
3813 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
3814 {
3815         void __iomem *ioaddr = tp->mmio_addr;
3816
3817         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3818 }
3819
3820 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
3821 {
3822         void __iomem *ioaddr = tp->mmio_addr;
3823         struct pci_dev *pdev = tp->pci_dev;
3824
3825         RTL_W8(MaxTxPacketSize, 0x3f);
3826         RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
3827         RTL_W8(Config4, RTL_R8(Config4) | 0x01);
3828         pci_write_config_byte(pdev, 0x79, 0x20);
3829 }
3830
3831 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
3832 {
3833         void __iomem *ioaddr = tp->mmio_addr;
3834         struct pci_dev *pdev = tp->pci_dev;
3835
3836         RTL_W8(MaxTxPacketSize, 0x0c);
3837         RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
3838         RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
3839         pci_write_config_byte(pdev, 0x79, 0x50);
3840 }
3841
3842 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
3843 {
3844         rtl_tx_performance_tweak(tp->pci_dev,
3845                 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3846 }
3847
3848 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
3849 {
3850         rtl_tx_performance_tweak(tp->pci_dev,
3851                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3852 }
3853
3854 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
3855 {
3856         void __iomem *ioaddr = tp->mmio_addr;
3857
3858         r8168b_0_hw_jumbo_enable(tp);
3859
3860         RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
3861 }
3862
3863 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
3864 {
3865         void __iomem *ioaddr = tp->mmio_addr;
3866
3867         r8168b_0_hw_jumbo_disable(tp);
3868
3869         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3870 }
3871
3872 static void __devinit rtl_init_jumbo_ops(struct rtl8169_private *tp)
3873 {
3874         struct jumbo_ops *ops = &tp->jumbo_ops;
3875
3876         switch (tp->mac_version) {
3877         case RTL_GIGA_MAC_VER_11:
3878                 ops->disable    = r8168b_0_hw_jumbo_disable;
3879                 ops->enable     = r8168b_0_hw_jumbo_enable;
3880                 break;
3881         case RTL_GIGA_MAC_VER_12:
3882         case RTL_GIGA_MAC_VER_17:
3883                 ops->disable    = r8168b_1_hw_jumbo_disable;
3884                 ops->enable     = r8168b_1_hw_jumbo_enable;
3885                 break;
3886         case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
3887         case RTL_GIGA_MAC_VER_19:
3888         case RTL_GIGA_MAC_VER_20:
3889         case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
3890         case RTL_GIGA_MAC_VER_22:
3891         case RTL_GIGA_MAC_VER_23:
3892         case RTL_GIGA_MAC_VER_24:
3893         case RTL_GIGA_MAC_VER_25:
3894         case RTL_GIGA_MAC_VER_26:
3895                 ops->disable    = r8168c_hw_jumbo_disable;
3896                 ops->enable     = r8168c_hw_jumbo_enable;
3897                 break;
3898         case RTL_GIGA_MAC_VER_27:
3899         case RTL_GIGA_MAC_VER_28:
3900                 ops->disable    = r8168dp_hw_jumbo_disable;
3901                 ops->enable     = r8168dp_hw_jumbo_enable;
3902                 break;
3903         case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
3904         case RTL_GIGA_MAC_VER_32:
3905         case RTL_GIGA_MAC_VER_33:
3906         case RTL_GIGA_MAC_VER_34:
3907                 ops->disable    = r8168e_hw_jumbo_disable;
3908                 ops->enable     = r8168e_hw_jumbo_enable;
3909                 break;
3910
3911         /*
3912          * No action needed for jumbo frames with 8169.
3913          * No jumbo for 810x at all.
3914          */
3915         default:
3916                 ops->disable    = NULL;
3917                 ops->enable     = NULL;
3918                 break;
3919         }
3920 }
3921
3922 static void rtl_hw_reset(struct rtl8169_private *tp)
3923 {
3924         void __iomem *ioaddr = tp->mmio_addr;
3925         int i;
3926
3927         /* Soft reset the chip. */
3928         RTL_W8(ChipCmd, CmdReset);
3929
3930         /* Check that the chip has finished the reset. */
3931         for (i = 0; i < 100; i++) {
3932                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3933                         break;
3934                 udelay(100);
3935         }
3936
3937         rtl8169_init_ring_indexes(tp);
3938 }
3939
3940 static int __devinit
3941 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3942 {
3943         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3944         const unsigned int region = cfg->region;
3945         struct rtl8169_private *tp;
3946         struct mii_if_info *mii;
3947         struct net_device *dev;
3948         void __iomem *ioaddr;
3949         int chipset, i;
3950         int rc;
3951
3952         if (netif_msg_drv(&debug)) {
3953                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3954                        MODULENAME, RTL8169_VERSION);
3955         }
3956
3957         dev = alloc_etherdev(sizeof (*tp));
3958         if (!dev) {
3959                 if (netif_msg_drv(&debug))
3960                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3961                 rc = -ENOMEM;
3962                 goto out;
3963         }
3964
3965         SET_NETDEV_DEV(dev, &pdev->dev);
3966         dev->netdev_ops = &rtl8169_netdev_ops;
3967         tp = netdev_priv(dev);
3968         tp->dev = dev;
3969         tp->pci_dev = pdev;
3970         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3971
3972         mii = &tp->mii;
3973         mii->dev = dev;
3974         mii->mdio_read = rtl_mdio_read;
3975         mii->mdio_write = rtl_mdio_write;
3976         mii->phy_id_mask = 0x1f;
3977         mii->reg_num_mask = 0x1f;
3978         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3979
3980         /* disable ASPM completely as that cause random device stop working
3981          * problems as well as full system hangs for some PCIe devices users */
3982         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3983                                      PCIE_LINK_STATE_CLKPM);
3984
3985         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3986         rc = pci_enable_device(pdev);
3987         if (rc < 0) {
3988                 netif_err(tp, probe, dev, "enable failure\n");
3989                 goto err_out_free_dev_1;
3990         }
3991
3992         if (pci_set_mwi(pdev) < 0)
3993                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3994
3995         /* make sure PCI base addr 1 is MMIO */
3996         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3997                 netif_err(tp, probe, dev,
3998                           "region #%d not an MMIO resource, aborting\n",
3999                           region);
4000                 rc = -ENODEV;
4001                 goto err_out_mwi_2;
4002         }
4003
4004         /* check for weird/broken PCI region reporting */
4005         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4006                 netif_err(tp, probe, dev,
4007                           "Invalid PCI region size(s), aborting\n");
4008                 rc = -ENODEV;
4009                 goto err_out_mwi_2;
4010         }
4011
4012         rc = pci_request_regions(pdev, MODULENAME);
4013         if (rc < 0) {
4014                 netif_err(tp, probe, dev, "could not request regions\n");
4015                 goto err_out_mwi_2;
4016         }
4017
4018         tp->cp_cmd = RxChkSum;
4019
4020         if ((sizeof(dma_addr_t) > 4) &&
4021             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
4022                 tp->cp_cmd |= PCIDAC;
4023                 dev->features |= NETIF_F_HIGHDMA;
4024         } else {
4025                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4026                 if (rc < 0) {
4027                         netif_err(tp, probe, dev, "DMA configuration failed\n");
4028                         goto err_out_free_res_3;
4029                 }
4030         }
4031
4032         /* ioremap MMIO region */
4033         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4034         if (!ioaddr) {
4035                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
4036                 rc = -EIO;
4037                 goto err_out_free_res_3;
4038         }
4039         tp->mmio_addr = ioaddr;
4040
4041         if (!pci_is_pcie(pdev))
4042                 netif_info(tp, probe, dev, "not PCI Express\n");
4043
4044         /* Identify chip attached to board */
4045         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
4046
4047         rtl_init_rxcfg(tp);
4048
4049         RTL_W16(IntrMask, 0x0000);
4050
4051         rtl_hw_reset(tp);
4052
4053         RTL_W16(IntrStatus, 0xffff);
4054
4055         pci_set_master(pdev);
4056
4057         /*
4058          * Pretend we are using VLANs; This bypasses a nasty bug where
4059          * Interrupts stop flowing on high load on 8110SCd controllers.
4060          */
4061         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4062                 tp->cp_cmd |= RxVlan;
4063
4064         rtl_init_mdio_ops(tp);
4065         rtl_init_pll_power_ops(tp);
4066         rtl_init_jumbo_ops(tp);
4067
4068         rtl8169_print_mac_version(tp);
4069
4070         chipset = tp->mac_version;
4071         tp->txd_version = rtl_chip_infos[chipset].txd_version;
4072
4073         RTL_W8(Cfg9346, Cfg9346_Unlock);
4074         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
4075         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
4076         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
4077                 tp->features |= RTL_FEATURE_WOL;
4078         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
4079                 tp->features |= RTL_FEATURE_WOL;
4080         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
4081         RTL_W8(Cfg9346, Cfg9346_Lock);
4082
4083         if (rtl_tbi_enabled(tp)) {
4084                 tp->set_speed = rtl8169_set_speed_tbi;
4085                 tp->get_settings = rtl8169_gset_tbi;
4086                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
4087                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
4088                 tp->link_ok = rtl8169_tbi_link_ok;
4089                 tp->do_ioctl = rtl_tbi_ioctl;
4090         } else {
4091                 tp->set_speed = rtl8169_set_speed_xmii;
4092                 tp->get_settings = rtl8169_gset_xmii;
4093                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
4094                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
4095                 tp->link_ok = rtl8169_xmii_link_ok;
4096                 tp->do_ioctl = rtl_xmii_ioctl;
4097         }
4098
4099         spin_lock_init(&tp->lock);
4100
4101         /* Get MAC address */
4102         for (i = 0; i < MAC_ADDR_LEN; i++)
4103                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
4104         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4105
4106         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
4107         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
4108         dev->irq = pdev->irq;
4109         dev->base_addr = (unsigned long) ioaddr;
4110
4111         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
4112
4113         /* don't enable SG, IP_CSUM and TSO by default - it might not work
4114          * properly for all devices */
4115         dev->features |= NETIF_F_RXCSUM |
4116                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4117
4118         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4119                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4120         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4121                 NETIF_F_HIGHDMA;
4122
4123         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4124                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
4125                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
4126
4127         tp->intr_mask = 0xffff;
4128         tp->hw_start = cfg->hw_start;
4129         tp->intr_event = cfg->intr_event;
4130         tp->napi_event = cfg->napi_event;
4131
4132         tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
4133                 ~(RxBOVF | RxFOVF) : ~0;
4134
4135         init_timer(&tp->timer);
4136         tp->timer.data = (unsigned long) dev;
4137         tp->timer.function = rtl8169_phy_timer;
4138
4139         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
4140
4141         rc = register_netdev(dev);
4142         if (rc < 0)
4143                 goto err_out_msi_4;
4144
4145         pci_set_drvdata(pdev, dev);
4146
4147         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
4148                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
4149                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
4150         if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
4151                 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
4152                            "tx checksumming: %s]\n",
4153                            rtl_chip_infos[chipset].jumbo_max,
4154                            rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
4155         }
4156
4157         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4158             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4159             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4160                 rtl8168_driver_start(tp);
4161         }
4162
4163         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
4164
4165         if (pci_dev_run_wake(pdev))
4166                 pm_runtime_put_noidle(&pdev->dev);
4167
4168         netif_carrier_off(dev);
4169
4170 out:
4171         return rc;
4172
4173 err_out_msi_4:
4174         rtl_disable_msi(pdev, tp);
4175         iounmap(ioaddr);
4176 err_out_free_res_3:
4177         pci_release_regions(pdev);
4178 err_out_mwi_2:
4179         pci_clear_mwi(pdev);
4180         pci_disable_device(pdev);
4181 err_out_free_dev_1:
4182         free_netdev(dev);
4183         goto out;
4184 }
4185
4186 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
4187 {
4188         struct net_device *dev = pci_get_drvdata(pdev);
4189         struct rtl8169_private *tp = netdev_priv(dev);
4190
4191         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4192             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4193             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4194                 rtl8168_driver_stop(tp);
4195         }
4196
4197         cancel_delayed_work_sync(&tp->task);
4198
4199         unregister_netdev(dev);
4200
4201         rtl_release_firmware(tp);
4202
4203         if (pci_dev_run_wake(pdev))
4204                 pm_runtime_get_noresume(&pdev->dev);
4205
4206         /* restore original MAC address */
4207         rtl_rar_set(tp, dev->perm_addr);
4208
4209         rtl_disable_msi(pdev, tp);
4210         rtl8169_release_board(pdev, dev, tp->mmio_addr);
4211         pci_set_drvdata(pdev, NULL);
4212 }
4213
4214 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4215 {
4216         struct rtl_fw *rtl_fw;
4217         const char *name;
4218         int rc = -ENOMEM;
4219
4220         name = rtl_lookup_firmware_name(tp);
4221         if (!name)
4222                 goto out_no_firmware;
4223
4224         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4225         if (!rtl_fw)
4226                 goto err_warn;
4227
4228         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
4229         if (rc < 0)
4230                 goto err_free;
4231
4232         rc = rtl_check_firmware(tp, rtl_fw);
4233         if (rc < 0)
4234                 goto err_release_firmware;
4235
4236         tp->rtl_fw = rtl_fw;
4237 out:
4238         return;
4239
4240 err_release_firmware:
4241         release_firmware(rtl_fw->fw);
4242 err_free:
4243         kfree(rtl_fw);
4244 err_warn:
4245         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4246                    name, rc);
4247 out_no_firmware:
4248         tp->rtl_fw = NULL;
4249         goto out;
4250 }
4251
4252 static void rtl_request_firmware(struct rtl8169_private *tp)
4253 {
4254         if (IS_ERR(tp->rtl_fw))
4255                 rtl_request_uncached_firmware(tp);
4256 }
4257
4258 static int rtl8169_open(struct net_device *dev)
4259 {
4260         struct rtl8169_private *tp = netdev_priv(dev);
4261         void __iomem *ioaddr = tp->mmio_addr;
4262         struct pci_dev *pdev = tp->pci_dev;
4263         int retval = -ENOMEM;
4264
4265         pm_runtime_get_sync(&pdev->dev);
4266
4267         /*
4268          * Rx and Tx desscriptors needs 256 bytes alignment.
4269          * dma_alloc_coherent provides more.
4270          */
4271         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4272                                              &tp->TxPhyAddr, GFP_KERNEL);
4273         if (!tp->TxDescArray)
4274                 goto err_pm_runtime_put;
4275
4276         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4277                                              &tp->RxPhyAddr, GFP_KERNEL);
4278         if (!tp->RxDescArray)
4279                 goto err_free_tx_0;
4280
4281         retval = rtl8169_init_ring(dev);
4282         if (retval < 0)
4283                 goto err_free_rx_1;
4284
4285         INIT_DELAYED_WORK(&tp->task, NULL);
4286
4287         smp_mb();
4288
4289         rtl_request_firmware(tp);
4290
4291         retval = request_irq(dev->irq, rtl8169_interrupt,
4292                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
4293                              dev->name, dev);
4294         if (retval < 0)
4295                 goto err_release_fw_2;
4296
4297         napi_enable(&tp->napi);
4298
4299         rtl8169_init_phy(dev, tp);
4300
4301         rtl8169_set_features(dev, dev->features);
4302
4303         rtl_pll_power_up(tp);
4304
4305         rtl_hw_start(dev);
4306
4307         tp->saved_wolopts = 0;
4308         pm_runtime_put_noidle(&pdev->dev);
4309
4310         rtl8169_check_link_status(dev, tp, ioaddr);
4311 out:
4312         return retval;
4313
4314 err_release_fw_2:
4315         rtl_release_firmware(tp);
4316         rtl8169_rx_clear(tp);
4317 err_free_rx_1:
4318         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4319                           tp->RxPhyAddr);
4320         tp->RxDescArray = NULL;
4321 err_free_tx_0:
4322         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4323                           tp->TxPhyAddr);
4324         tp->TxDescArray = NULL;
4325 err_pm_runtime_put:
4326         pm_runtime_put_noidle(&pdev->dev);
4327         goto out;
4328 }
4329
4330 static void rtl_rx_close(struct rtl8169_private *tp)
4331 {
4332         void __iomem *ioaddr = tp->mmio_addr;
4333
4334         RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4335 }
4336
4337 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4338 {
4339         void __iomem *ioaddr = tp->mmio_addr;
4340
4341         /* Disable interrupts */
4342         rtl8169_irq_mask_and_ack(ioaddr);
4343
4344         rtl_rx_close(tp);
4345
4346         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4347             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4348             tp->mac_version == RTL_GIGA_MAC_VER_31) {
4349                 while (RTL_R8(TxPoll) & NPQ)
4350                         udelay(20);
4351         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
4352                    tp->mac_version == RTL_GIGA_MAC_VER_35 ||
4353                    tp->mac_version == RTL_GIGA_MAC_VER_36) {
4354                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4355                 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4356                         udelay(100);
4357         } else {
4358                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4359                 udelay(100);
4360         }
4361
4362         rtl_hw_reset(tp);
4363 }
4364
4365 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
4366 {
4367         void __iomem *ioaddr = tp->mmio_addr;
4368
4369         /* Set DMA burst size and Interframe Gap Time */
4370         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4371                 (InterFrameGap << TxInterFrameGapShift));
4372 }
4373
4374 static void rtl_hw_start(struct net_device *dev)
4375 {
4376         struct rtl8169_private *tp = netdev_priv(dev);
4377
4378         tp->hw_start(dev);
4379
4380         netif_start_queue(dev);
4381 }
4382
4383 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4384                                          void __iomem *ioaddr)
4385 {
4386         /*
4387          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4388          * register to be written before TxDescAddrLow to work.
4389          * Switching from MMIO to I/O access fixes the issue as well.
4390          */
4391         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4392         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4393         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4394         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4395 }
4396
4397 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4398 {
4399         u16 cmd;
4400
4401         cmd = RTL_R16(CPlusCmd);
4402         RTL_W16(CPlusCmd, cmd);
4403         return cmd;
4404 }
4405
4406 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
4407 {
4408         /* Low hurts. Let's disable the filtering. */
4409         RTL_W16(RxMaxSize, rx_buf_sz + 1);
4410 }
4411
4412 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4413 {
4414         static const struct rtl_cfg2_info {
4415                 u32 mac_version;
4416                 u32 clk;
4417                 u32 val;
4418         } cfg2_info [] = {
4419                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4420                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4421                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4422                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4423         };
4424         const struct rtl_cfg2_info *p = cfg2_info;
4425         unsigned int i;
4426         u32 clk;
4427
4428         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
4429         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4430                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4431                         RTL_W32(0x7c, p->val);
4432                         break;
4433                 }
4434         }
4435 }
4436
4437 static void rtl_hw_start_8169(struct net_device *dev)
4438 {
4439         struct rtl8169_private *tp = netdev_priv(dev);
4440         void __iomem *ioaddr = tp->mmio_addr;
4441         struct pci_dev *pdev = tp->pci_dev;
4442
4443         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4444                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4445                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4446         }
4447
4448         RTL_W8(Cfg9346, Cfg9346_Unlock);
4449         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4450             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4451             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4452             tp->mac_version == RTL_GIGA_MAC_VER_04)
4453                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4454
4455         rtl_init_rxcfg(tp);
4456
4457         RTL_W8(EarlyTxThres, NoEarlyTx);
4458
4459         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4460
4461         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4462             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4463             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4464             tp->mac_version == RTL_GIGA_MAC_VER_04)
4465                 rtl_set_rx_tx_config_registers(tp);
4466
4467         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
4468
4469         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4470             tp->mac_version == RTL_GIGA_MAC_VER_03) {
4471                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
4472                         "Bit-3 and bit-14 MUST be 1\n");
4473                 tp->cp_cmd |= (1 << 14);
4474         }
4475
4476         RTL_W16(CPlusCmd, tp->cp_cmd);
4477
4478         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4479
4480         /*
4481          * Undocumented corner. Supposedly:
4482          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4483          */
4484         RTL_W16(IntrMitigate, 0x0000);
4485
4486         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4487
4488         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4489             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4490             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4491             tp->mac_version != RTL_GIGA_MAC_VER_04) {
4492                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4493                 rtl_set_rx_tx_config_registers(tp);
4494         }
4495
4496         RTL_W8(Cfg9346, Cfg9346_Lock);
4497
4498         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4499         RTL_R8(IntrMask);
4500
4501         RTL_W32(RxMissed, 0);
4502
4503         rtl_set_rx_mode(dev);
4504
4505         /* no early-rx interrupts */
4506         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4507
4508         /* Enable all known interrupts by setting the interrupt mask. */
4509         RTL_W16(IntrMask, tp->intr_event);
4510 }
4511
4512 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
4513 {
4514         u32 csi;
4515
4516         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
4517         rtl_csi_write(ioaddr, 0x070c, csi | bits);
4518 }
4519
4520 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4521 {
4522         rtl_csi_access_enable(ioaddr, 0x17000000);
4523 }
4524
4525 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4526 {
4527         rtl_csi_access_enable(ioaddr, 0x27000000);
4528 }
4529
4530 struct ephy_info {
4531         unsigned int offset;
4532         u16 mask;
4533         u16 bits;
4534 };
4535
4536 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
4537 {
4538         u16 w;
4539
4540         while (len-- > 0) {
4541                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4542                 rtl_ephy_write(ioaddr, e->offset, w);
4543                 e++;
4544         }
4545 }
4546
4547 static void rtl_disable_clock_request(struct pci_dev *pdev)
4548 {
4549         int cap = pci_pcie_cap(pdev);
4550
4551         if (cap) {
4552                 u16 ctl;
4553
4554                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4555                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4556                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4557         }
4558 }
4559
4560 static void rtl_enable_clock_request(struct pci_dev *pdev)
4561 {
4562         int cap = pci_pcie_cap(pdev);
4563
4564         if (cap) {
4565                 u16 ctl;
4566
4567                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4568                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4569                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4570         }
4571 }
4572
4573 #define R8168_CPCMD_QUIRK_MASK (\
4574         EnableBist | \
4575         Mac_dbgo_oe | \
4576         Force_half_dup | \
4577         Force_rxflow_en | \
4578         Force_txflow_en | \
4579         Cxpl_dbg_sel | \
4580         ASF | \
4581         PktCntrDisable | \
4582         Mac_dbgo_sel)
4583
4584 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4585 {
4586         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4587
4588         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4589
4590         rtl_tx_performance_tweak(pdev,
4591                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4592 }
4593
4594 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4595 {
4596         rtl_hw_start_8168bb(ioaddr, pdev);
4597
4598         RTL_W8(MaxTxPacketSize, TxPacketMax);
4599
4600         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4601 }
4602
4603 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4604 {
4605         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4606
4607         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4608
4609         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4610
4611         rtl_disable_clock_request(pdev);
4612
4613         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4614 }
4615
4616 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4617 {
4618         static const struct ephy_info e_info_8168cp[] = {
4619                 { 0x01, 0,      0x0001 },
4620                 { 0x02, 0x0800, 0x1000 },
4621                 { 0x03, 0,      0x0042 },
4622                 { 0x06, 0x0080, 0x0000 },
4623                 { 0x07, 0,      0x2000 }
4624         };
4625
4626         rtl_csi_access_enable_2(ioaddr);
4627
4628         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4629
4630         __rtl_hw_start_8168cp(ioaddr, pdev);
4631 }
4632
4633 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4634 {
4635         rtl_csi_access_enable_2(ioaddr);
4636
4637         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4638
4639         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4640
4641         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4642 }
4643
4644 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4645 {
4646         rtl_csi_access_enable_2(ioaddr);
4647
4648         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4649
4650         /* Magic. */
4651         RTL_W8(DBG_REG, 0x20);
4652
4653         RTL_W8(MaxTxPacketSize, TxPacketMax);
4654
4655         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4656
4657         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4658 }
4659
4660 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4661 {
4662         static const struct ephy_info e_info_8168c_1[] = {
4663                 { 0x02, 0x0800, 0x1000 },
4664                 { 0x03, 0,      0x0002 },
4665                 { 0x06, 0x0080, 0x0000 }
4666         };
4667
4668         rtl_csi_access_enable_2(ioaddr);
4669
4670         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4671
4672         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4673
4674         __rtl_hw_start_8168cp(ioaddr, pdev);
4675 }
4676
4677 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4678 {
4679         static const struct ephy_info e_info_8168c_2[] = {
4680                 { 0x01, 0,      0x0001 },
4681                 { 0x03, 0x0400, 0x0220 }
4682         };
4683
4684         rtl_csi_access_enable_2(ioaddr);
4685
4686         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4687
4688         __rtl_hw_start_8168cp(ioaddr, pdev);
4689 }
4690
4691 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4692 {
4693         rtl_hw_start_8168c_2(ioaddr, pdev);
4694 }
4695
4696 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4697 {
4698         rtl_csi_access_enable_2(ioaddr);
4699
4700         __rtl_hw_start_8168cp(ioaddr, pdev);
4701 }
4702
4703 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4704 {
4705         rtl_csi_access_enable_2(ioaddr);
4706
4707         rtl_disable_clock_request(pdev);
4708
4709         RTL_W8(MaxTxPacketSize, TxPacketMax);
4710
4711         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4712
4713         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4714 }
4715
4716 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4717 {
4718         rtl_csi_access_enable_1(ioaddr);
4719
4720         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4721
4722         RTL_W8(MaxTxPacketSize, TxPacketMax);
4723
4724         rtl_disable_clock_request(pdev);
4725 }
4726
4727 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4728 {
4729         static const struct ephy_info e_info_8168d_4[] = {
4730                 { 0x0b, ~0,     0x48 },
4731                 { 0x19, 0x20,   0x50 },
4732                 { 0x0c, ~0,     0x20 }
4733         };
4734         int i;
4735
4736         rtl_csi_access_enable_1(ioaddr);
4737
4738         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4739
4740         RTL_W8(MaxTxPacketSize, TxPacketMax);
4741
4742         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4743                 const struct ephy_info *e = e_info_8168d_4 + i;
4744                 u16 w;
4745
4746                 w = rtl_ephy_read(ioaddr, e->offset);
4747                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4748         }
4749
4750         rtl_enable_clock_request(pdev);
4751 }
4752
4753 static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4754 {
4755         static const struct ephy_info e_info_8168e_1[] = {
4756                 { 0x00, 0x0200, 0x0100 },
4757                 { 0x00, 0x0000, 0x0004 },
4758                 { 0x06, 0x0002, 0x0001 },
4759                 { 0x06, 0x0000, 0x0030 },
4760                 { 0x07, 0x0000, 0x2000 },
4761                 { 0x00, 0x0000, 0x0020 },
4762                 { 0x03, 0x5800, 0x2000 },
4763                 { 0x03, 0x0000, 0x0001 },
4764                 { 0x01, 0x0800, 0x1000 },
4765                 { 0x07, 0x0000, 0x4000 },
4766                 { 0x1e, 0x0000, 0x2000 },
4767                 { 0x19, 0xffff, 0xfe6c },
4768                 { 0x0a, 0x0000, 0x0040 }
4769         };
4770
4771         rtl_csi_access_enable_2(ioaddr);
4772
4773         rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
4774
4775         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4776
4777         RTL_W8(MaxTxPacketSize, TxPacketMax);
4778
4779         rtl_disable_clock_request(pdev);
4780
4781         /* Reset tx FIFO pointer */
4782         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4783         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4784
4785         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4786 }
4787
4788 static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4789 {
4790         static const struct ephy_info e_info_8168e_2[] = {
4791                 { 0x09, 0x0000, 0x0080 },
4792                 { 0x19, 0x0000, 0x0224 }
4793         };
4794
4795         rtl_csi_access_enable_1(ioaddr);
4796
4797         rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4798
4799         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4800
4801         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4802         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4803         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4804         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4805         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4806         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4807         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4808         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4809                      ERIAR_EXGMAC);
4810
4811         RTL_W8(MaxTxPacketSize, EarlySize);
4812
4813         rtl_disable_clock_request(pdev);
4814
4815         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4816         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4817
4818         /* Adjust EEE LED frequency */
4819         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4820
4821         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4822         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4823         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4824 }
4825
4826 static void rtl_hw_start_8168f_1(void __iomem *ioaddr, struct pci_dev *pdev)
4827 {
4828         static const struct ephy_info e_info_8168f_1[] = {
4829                 { 0x06, 0x00c0, 0x0020 },
4830                 { 0x08, 0x0001, 0x0002 },
4831                 { 0x09, 0x0000, 0x0080 },
4832                 { 0x19, 0x0000, 0x0224 }
4833         };
4834
4835         rtl_csi_access_enable_1(ioaddr);
4836
4837         rtl_ephy_init(ioaddr, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
4838
4839         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4840
4841         rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4842         rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4843         rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4844         rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4845         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
4846         rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
4847         rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4848         rtl_w1w0_eri(ioaddr, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4849         rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4850         rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
4851         rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4852                      ERIAR_EXGMAC);
4853
4854         RTL_W8(MaxTxPacketSize, EarlySize);
4855
4856         rtl_disable_clock_request(pdev);
4857
4858         RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4859         RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4860
4861         /* Adjust EEE LED frequency */
4862         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4863
4864         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4865         RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4866         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4867 }
4868
4869 static void rtl_hw_start_8168(struct net_device *dev)
4870 {
4871         struct rtl8169_private *tp = netdev_priv(dev);
4872         void __iomem *ioaddr = tp->mmio_addr;
4873         struct pci_dev *pdev = tp->pci_dev;
4874
4875         RTL_W8(Cfg9346, Cfg9346_Unlock);
4876
4877         RTL_W8(MaxTxPacketSize, TxPacketMax);
4878
4879         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4880
4881         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4882
4883         RTL_W16(CPlusCmd, tp->cp_cmd);
4884
4885         RTL_W16(IntrMitigate, 0x5151);
4886
4887         /* Work around for RxFIFO overflow. */
4888         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4889             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4890                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4891                 tp->intr_event &= ~RxOverflow;
4892         }
4893
4894         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4895
4896         rtl_set_rx_mode(dev);
4897
4898         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4899                 (InterFrameGap << TxInterFrameGapShift));
4900
4901         RTL_R8(IntrMask);
4902
4903         switch (tp->mac_version) {
4904         case RTL_GIGA_MAC_VER_11:
4905                 rtl_hw_start_8168bb(ioaddr, pdev);
4906                 break;
4907
4908         case RTL_GIGA_MAC_VER_12:
4909         case RTL_GIGA_MAC_VER_17:
4910                 rtl_hw_start_8168bef(ioaddr, pdev);
4911                 break;
4912
4913         case RTL_GIGA_MAC_VER_18:
4914                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4915                 break;
4916
4917         case RTL_GIGA_MAC_VER_19:
4918                 rtl_hw_start_8168c_1(ioaddr, pdev);
4919                 break;
4920
4921         case RTL_GIGA_MAC_VER_20:
4922                 rtl_hw_start_8168c_2(ioaddr, pdev);
4923                 break;
4924
4925         case RTL_GIGA_MAC_VER_21:
4926                 rtl_hw_start_8168c_3(ioaddr, pdev);
4927                 break;
4928
4929         case RTL_GIGA_MAC_VER_22:
4930                 rtl_hw_start_8168c_4(ioaddr, pdev);
4931                 break;
4932
4933         case RTL_GIGA_MAC_VER_23:
4934                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4935                 break;
4936
4937         case RTL_GIGA_MAC_VER_24:
4938                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4939                 break;
4940
4941         case RTL_GIGA_MAC_VER_25:
4942         case RTL_GIGA_MAC_VER_26:
4943         case RTL_GIGA_MAC_VER_27:
4944                 rtl_hw_start_8168d(ioaddr, pdev);
4945                 break;
4946
4947         case RTL_GIGA_MAC_VER_28:
4948                 rtl_hw_start_8168d_4(ioaddr, pdev);
4949                 break;
4950
4951         case RTL_GIGA_MAC_VER_31:
4952                 rtl_hw_start_8168dp(ioaddr, pdev);
4953                 break;
4954
4955         case RTL_GIGA_MAC_VER_32:
4956         case RTL_GIGA_MAC_VER_33:
4957                 rtl_hw_start_8168e_1(ioaddr, pdev);
4958                 break;
4959         case RTL_GIGA_MAC_VER_34:
4960                 rtl_hw_start_8168e_2(ioaddr, pdev);
4961                 break;
4962
4963         case RTL_GIGA_MAC_VER_35:
4964         case RTL_GIGA_MAC_VER_36:
4965                 rtl_hw_start_8168f_1(ioaddr, pdev);
4966                 break;
4967
4968         default:
4969                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4970                         dev->name, tp->mac_version);
4971                 break;
4972         }
4973
4974         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4975
4976         RTL_W8(Cfg9346, Cfg9346_Lock);
4977
4978         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4979
4980         RTL_W16(IntrMask, tp->intr_event);
4981 }
4982
4983 #define R810X_CPCMD_QUIRK_MASK (\
4984         EnableBist | \
4985         Mac_dbgo_oe | \
4986         Force_half_dup | \
4987         Force_rxflow_en | \
4988         Force_txflow_en | \
4989         Cxpl_dbg_sel | \
4990         ASF | \
4991         PktCntrDisable | \
4992         Mac_dbgo_sel)
4993
4994 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4995 {
4996         static const struct ephy_info e_info_8102e_1[] = {
4997                 { 0x01, 0, 0x6e65 },
4998                 { 0x02, 0, 0x091f },
4999                 { 0x03, 0, 0xc2f9 },
5000                 { 0x06, 0, 0xafb5 },
5001                 { 0x07, 0, 0x0e00 },
5002                 { 0x19, 0, 0xec80 },
5003                 { 0x01, 0, 0x2e65 },
5004                 { 0x01, 0, 0x6e65 }
5005         };
5006         u8 cfg1;
5007
5008         rtl_csi_access_enable_2(ioaddr);
5009
5010         RTL_W8(DBG_REG, FIX_NAK_1);
5011
5012         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5013
5014         RTL_W8(Config1,
5015                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5016         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5017
5018         cfg1 = RTL_R8(Config1);
5019         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5020                 RTL_W8(Config1, cfg1 & ~LEDS0);
5021
5022         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5023 }
5024
5025 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5026 {
5027         rtl_csi_access_enable_2(ioaddr);
5028
5029         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5030
5031         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
5032         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5033 }
5034
5035 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
5036 {
5037         rtl_hw_start_8102e_2(ioaddr, pdev);
5038
5039         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
5040 }
5041
5042 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
5043 {
5044         static const struct ephy_info e_info_8105e_1[] = {
5045                 { 0x07, 0, 0x4000 },
5046                 { 0x19, 0, 0x0200 },
5047                 { 0x19, 0, 0x0020 },
5048                 { 0x1e, 0, 0x2000 },
5049                 { 0x03, 0, 0x0001 },
5050                 { 0x19, 0, 0x0100 },
5051                 { 0x19, 0, 0x0004 },
5052                 { 0x0a, 0, 0x0020 }
5053         };
5054
5055         /* Force LAN exit from ASPM if Rx/Tx are not idle */
5056         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
5057
5058         /* Disable Early Tally Counter */
5059         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
5060
5061         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
5062         RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5063
5064         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5065 }
5066
5067 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
5068 {
5069         rtl_hw_start_8105e_1(ioaddr, pdev);
5070         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
5071 }
5072
5073 static void rtl_hw_start_8101(struct net_device *dev)
5074 {
5075         struct rtl8169_private *tp = netdev_priv(dev);
5076         void __iomem *ioaddr = tp->mmio_addr;
5077         struct pci_dev *pdev = tp->pci_dev;
5078
5079         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5080             tp->mac_version == RTL_GIGA_MAC_VER_16) {
5081                 int cap = pci_pcie_cap(pdev);
5082
5083                 if (cap) {
5084                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
5085                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
5086                 }
5087         }
5088
5089         RTL_W8(Cfg9346, Cfg9346_Unlock);
5090
5091         switch (tp->mac_version) {
5092         case RTL_GIGA_MAC_VER_07:
5093                 rtl_hw_start_8102e_1(ioaddr, pdev);
5094                 break;
5095
5096         case RTL_GIGA_MAC_VER_08:
5097                 rtl_hw_start_8102e_3(ioaddr, pdev);
5098                 break;
5099
5100         case RTL_GIGA_MAC_VER_09:
5101                 rtl_hw_start_8102e_2(ioaddr, pdev);
5102                 break;
5103
5104         case RTL_GIGA_MAC_VER_29:
5105                 rtl_hw_start_8105e_1(ioaddr, pdev);
5106                 break;
5107         case RTL_GIGA_MAC_VER_30:
5108                 rtl_hw_start_8105e_2(ioaddr, pdev);
5109                 break;
5110         }
5111
5112         RTL_W8(Cfg9346, Cfg9346_Lock);
5113
5114         RTL_W8(MaxTxPacketSize, TxPacketMax);
5115
5116         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5117
5118         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
5119         RTL_W16(CPlusCmd, tp->cp_cmd);
5120
5121         RTL_W16(IntrMitigate, 0x0000);
5122
5123         rtl_set_rx_tx_desc_registers(tp, ioaddr);
5124
5125         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5126         rtl_set_rx_tx_config_registers(tp);
5127
5128         RTL_R8(IntrMask);
5129
5130         rtl_set_rx_mode(dev);
5131
5132         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5133
5134         RTL_W16(IntrMask, tp->intr_event);
5135 }
5136
5137 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5138 {
5139         struct rtl8169_private *tp = netdev_priv(dev);
5140
5141         if (new_mtu < ETH_ZLEN ||
5142             new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
5143                 return -EINVAL;
5144
5145         if (new_mtu > ETH_DATA_LEN)
5146                 rtl_hw_jumbo_enable(tp);
5147         else
5148                 rtl_hw_jumbo_disable(tp);
5149
5150         dev->mtu = new_mtu;
5151         netdev_update_features(dev);
5152
5153         return 0;
5154 }
5155
5156 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5157 {
5158         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5159         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5160 }
5161
5162 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5163                                      void **data_buff, struct RxDesc *desc)
5164 {
5165         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
5166                          DMA_FROM_DEVICE);
5167
5168         kfree(*data_buff);
5169         *data_buff = NULL;
5170         rtl8169_make_unusable_by_asic(desc);
5171 }
5172
5173 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
5174 {
5175         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5176
5177         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
5178 }
5179
5180 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
5181                                        u32 rx_buf_sz)
5182 {
5183         desc->addr = cpu_to_le64(mapping);
5184         wmb();
5185         rtl8169_mark_to_asic(desc, rx_buf_sz);
5186 }
5187
5188 static inline void *rtl8169_align(void *data)
5189 {
5190         return (void *)ALIGN((long)data, 16);
5191 }
5192
5193 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5194                                              struct RxDesc *desc)
5195 {
5196         void *data;
5197         dma_addr_t mapping;
5198         struct device *d = &tp->pci_dev->dev;
5199         struct net_device *dev = tp->dev;
5200         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
5201
5202         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
5203         if (!data)
5204                 return NULL;
5205
5206         if (rtl8169_align(data) != data) {
5207                 kfree(data);
5208                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
5209                 if (!data)
5210                         return NULL;
5211         }
5212
5213         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
5214                                  DMA_FROM_DEVICE);
5215         if (unlikely(dma_mapping_error(d, mapping))) {
5216                 if (net_ratelimit())
5217                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5218                 goto err_out;
5219         }
5220
5221         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
5222         return data;
5223
5224 err_out:
5225         kfree(data);
5226         return NULL;
5227 }
5228
5229 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5230 {
5231         unsigned int i;
5232
5233         for (i = 0; i < NUM_RX_DESC; i++) {
5234                 if (tp->Rx_databuff[i]) {
5235                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5236                                             tp->RxDescArray + i);
5237                 }
5238         }
5239 }
5240
5241 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5242 {
5243         desc->opts1 |= cpu_to_le32(RingEnd);
5244 }
5245
5246 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5247 {
5248         unsigned int i;
5249
5250         for (i = 0; i < NUM_RX_DESC; i++) {
5251                 void *data;
5252
5253                 if (tp->Rx_databuff[i])
5254                         continue;
5255
5256                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5257                 if (!data) {
5258                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5259                         goto err_out;
5260                 }
5261                 tp->Rx_databuff[i] = data;
5262         }
5263
5264         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5265         return 0;
5266
5267 err_out:
5268         rtl8169_rx_clear(tp);
5269         return -ENOMEM;
5270 }
5271
5272 static int rtl8169_init_ring(struct net_device *dev)
5273 {
5274         struct rtl8169_private *tp = netdev_priv(dev);
5275
5276         rtl8169_init_ring_indexes(tp);
5277
5278         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
5279         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
5280
5281         return rtl8169_rx_fill(tp);
5282 }
5283
5284 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5285                                  struct TxDesc *desc)
5286 {
5287         unsigned int len = tx_skb->len;
5288
5289         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5290
5291         desc->opts1 = 0x00;
5292         desc->opts2 = 0x00;
5293         desc->addr = 0x00;
5294         tx_skb->len = 0;
5295 }
5296
5297 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5298                                    unsigned int n)
5299 {
5300         unsigned int i;
5301
5302         for (i = 0; i < n; i++) {
5303                 unsigned int entry = (start + i) % NUM_TX_DESC;
5304                 struct ring_info *tx_skb = tp->tx_skb + entry;
5305                 unsigned int len = tx_skb->len;
5306
5307                 if (len) {
5308                         struct sk_buff *skb = tx_skb->skb;
5309
5310                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5311                                              tp->TxDescArray + entry);
5312                         if (skb) {
5313                                 tp->dev->stats.tx_dropped++;
5314                                 dev_kfree_skb(skb);
5315                                 tx_skb->skb = NULL;
5316                         }
5317                 }
5318         }
5319 }
5320
5321 static void rtl8169_tx_clear(struct rtl8169_private *tp)
5322 {
5323         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5324         tp->cur_tx = tp->dirty_tx = 0;
5325 }
5326
5327 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
5328 {
5329         struct rtl8169_private *tp = netdev_priv(dev);
5330
5331         PREPARE_DELAYED_WORK(&tp->task, task);
5332         schedule_delayed_work(&tp->task, 4);
5333 }
5334
5335 static void rtl8169_wait_for_quiescence(struct net_device *dev)
5336 {
5337         struct rtl8169_private *tp = netdev_priv(dev);
5338         void __iomem *ioaddr = tp->mmio_addr;
5339
5340         synchronize_irq(dev->irq);
5341
5342         /* Wait for any pending NAPI task to complete */
5343         napi_disable(&tp->napi);
5344
5345         rtl8169_irq_mask_and_ack(ioaddr);
5346
5347         tp->intr_mask = 0xffff;
5348         RTL_W16(IntrMask, tp->intr_event);
5349         napi_enable(&tp->napi);
5350 }
5351
5352 static void rtl8169_reinit_task(struct work_struct *work)
5353 {
5354         struct rtl8169_private *tp =
5355                 container_of(work, struct rtl8169_private, task.work);
5356         struct net_device *dev = tp->dev;
5357         int ret;
5358
5359         rtnl_lock();
5360
5361         if (!netif_running(dev))
5362                 goto out_unlock;
5363
5364         rtl8169_wait_for_quiescence(dev);
5365         rtl8169_close(dev);
5366
5367         ret = rtl8169_open(dev);
5368         if (unlikely(ret < 0)) {
5369                 if (net_ratelimit())
5370                         netif_err(tp, drv, dev,
5371                                   "reinit failure (status = %d). Rescheduling\n",
5372                                   ret);
5373                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
5374         }
5375
5376 out_unlock:
5377         rtnl_unlock();
5378 }
5379
5380 static void rtl8169_reset_task(struct work_struct *work)
5381 {
5382         struct rtl8169_private *tp =
5383                 container_of(work, struct rtl8169_private, task.work);
5384         struct net_device *dev = tp->dev;
5385         int i;
5386
5387         rtnl_lock();
5388
5389         if (!netif_running(dev))
5390                 goto out_unlock;
5391
5392         rtl8169_wait_for_quiescence(dev);
5393
5394         for (i = 0; i < NUM_RX_DESC; i++)
5395                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
5396
5397         rtl8169_tx_clear(tp);
5398
5399         rtl8169_hw_reset(tp);
5400         rtl_hw_start(dev);
5401         netif_wake_queue(dev);
5402         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
5403
5404 out_unlock:
5405         rtnl_unlock();
5406 }
5407
5408 static void rtl8169_tx_timeout(struct net_device *dev)
5409 {
5410         struct rtl8169_private *tp = netdev_priv(dev);
5411
5412         rtl8169_hw_reset(tp);
5413
5414         /* Let's wait a bit while any (async) irq lands on */
5415         rtl8169_schedule_work(dev, rtl8169_reset_task);
5416 }
5417
5418 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5419                               u32 *opts)
5420 {
5421         struct skb_shared_info *info = skb_shinfo(skb);
5422         unsigned int cur_frag, entry;
5423         struct TxDesc * uninitialized_var(txd);
5424         struct device *d = &tp->pci_dev->dev;
5425
5426         entry = tp->cur_tx;
5427         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5428                 const skb_frag_t *frag = info->frags + cur_frag;
5429                 dma_addr_t mapping;
5430                 u32 status, len;
5431                 void *addr;
5432
5433                 entry = (entry + 1) % NUM_TX_DESC;
5434
5435                 txd = tp->TxDescArray + entry;
5436                 len = skb_frag_size(frag);
5437                 addr = skb_frag_address(frag);
5438                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5439                 if (unlikely(dma_mapping_error(d, mapping))) {
5440                         if (net_ratelimit())
5441                                 netif_err(tp, drv, tp->dev,
5442                                           "Failed to map TX fragments DMA!\n");
5443                         goto err_out;
5444                 }
5445
5446                 /* Anti gcc 2.95.3 bugware (sic) */
5447                 status = opts[0] | len |
5448                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
5449
5450                 txd->opts1 = cpu_to_le32(status);
5451                 txd->opts2 = cpu_to_le32(opts[1]);
5452                 txd->addr = cpu_to_le64(mapping);
5453
5454                 tp->tx_skb[entry].len = len;
5455         }
5456
5457         if (cur_frag) {
5458                 tp->tx_skb[entry].skb = skb;
5459                 txd->opts1 |= cpu_to_le32(LastFrag);
5460         }
5461
5462         return cur_frag;
5463
5464 err_out:
5465         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5466         return -EIO;
5467 }
5468
5469 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5470                                     struct sk_buff *skb, u32 *opts)
5471 {
5472         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
5473         u32 mss = skb_shinfo(skb)->gso_size;
5474         int offset = info->opts_offset;
5475
5476         if (mss) {
5477                 opts[0] |= TD_LSO;
5478                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5479         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5480                 const struct iphdr *ip = ip_hdr(skb);
5481
5482                 if (ip->protocol == IPPROTO_TCP)
5483                         opts[offset] |= info->checksum.tcp;
5484                 else if (ip->protocol == IPPROTO_UDP)
5485                         opts[offset] |= info->checksum.udp;
5486                 else
5487                         WARN_ON_ONCE(1);
5488         }
5489 }
5490
5491 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5492                                       struct net_device *dev)
5493 {
5494         struct rtl8169_private *tp = netdev_priv(dev);
5495         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
5496         struct TxDesc *txd = tp->TxDescArray + entry;
5497         void __iomem *ioaddr = tp->mmio_addr;
5498         struct device *d = &tp->pci_dev->dev;
5499         dma_addr_t mapping;
5500         u32 status, len;
5501         u32 opts[2];
5502         int frags;
5503
5504         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
5505                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
5506                 goto err_stop_0;
5507         }
5508
5509         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
5510                 goto err_stop_0;
5511
5512         len = skb_headlen(skb);
5513         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
5514         if (unlikely(dma_mapping_error(d, mapping))) {
5515                 if (net_ratelimit())
5516                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5517                 goto err_dma_0;
5518         }
5519
5520         tp->tx_skb[entry].len = len;
5521         txd->addr = cpu_to_le64(mapping);
5522
5523         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5524         opts[0] = DescOwn;
5525
5526         rtl8169_tso_csum(tp, skb, opts);
5527
5528         frags = rtl8169_xmit_frags(tp, skb, opts);
5529         if (frags < 0)
5530                 goto err_dma_1;
5531         else if (frags)
5532                 opts[0] |= FirstFrag;
5533         else {
5534                 opts[0] |= FirstFrag | LastFrag;
5535                 tp->tx_skb[entry].skb = skb;
5536         }
5537
5538         txd->opts2 = cpu_to_le32(opts[1]);
5539
5540         wmb();
5541
5542         /* Anti gcc 2.95.3 bugware (sic) */
5543         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5544         txd->opts1 = cpu_to_le32(status);
5545
5546         tp->cur_tx += frags + 1;
5547
5548         wmb();
5549
5550         RTL_W8(TxPoll, NPQ);
5551
5552         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5553                 netif_stop_queue(dev);
5554                 smp_rmb();
5555                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5556                         netif_wake_queue(dev);
5557         }
5558
5559         return NETDEV_TX_OK;
5560
5561 err_dma_1:
5562         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
5563 err_dma_0:
5564         dev_kfree_skb(skb);
5565         dev->stats.tx_dropped++;
5566         return NETDEV_TX_OK;
5567
5568 err_stop_0:
5569         netif_stop_queue(dev);
5570         dev->stats.tx_dropped++;
5571         return NETDEV_TX_BUSY;
5572 }
5573
5574 static void rtl8169_pcierr_interrupt(struct net_device *dev)
5575 {
5576         struct rtl8169_private *tp = netdev_priv(dev);
5577         struct pci_dev *pdev = tp->pci_dev;
5578         u16 pci_status, pci_cmd;
5579
5580         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5581         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5582
5583         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5584                   pci_cmd, pci_status);
5585
5586         /*
5587          * The recovery sequence below admits a very elaborated explanation:
5588          * - it seems to work;
5589          * - I did not see what else could be done;
5590          * - it makes iop3xx happy.
5591          *
5592          * Feel free to adjust to your needs.
5593          */
5594         if (pdev->broken_parity_status)
5595                 pci_cmd &= ~PCI_COMMAND_PARITY;
5596         else
5597                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5598
5599         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
5600
5601         pci_write_config_word(pdev, PCI_STATUS,
5602                 pci_status & (PCI_STATUS_DETECTED_PARITY |
5603                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5604                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5605
5606         /* The infamous DAC f*ckup only happens at boot time */
5607         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
5608                 void __iomem *ioaddr = tp->mmio_addr;
5609
5610                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
5611                 tp->cp_cmd &= ~PCIDAC;
5612                 RTL_W16(CPlusCmd, tp->cp_cmd);
5613                 dev->features &= ~NETIF_F_HIGHDMA;
5614         }
5615
5616         rtl8169_hw_reset(tp);
5617
5618         rtl8169_schedule_work(dev, rtl8169_reinit_task);
5619 }
5620
5621 static void rtl8169_tx_interrupt(struct net_device *dev,
5622                                  struct rtl8169_private *tp,
5623                                  void __iomem *ioaddr)
5624 {
5625         unsigned int dirty_tx, tx_left;
5626
5627         dirty_tx = tp->dirty_tx;
5628         smp_rmb();
5629         tx_left = tp->cur_tx - dirty_tx;
5630
5631         while (tx_left > 0) {
5632                 unsigned int entry = dirty_tx % NUM_TX_DESC;
5633                 struct ring_info *tx_skb = tp->tx_skb + entry;
5634                 u32 status;
5635
5636                 rmb();
5637                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5638                 if (status & DescOwn)
5639                         break;
5640
5641                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5642                                      tp->TxDescArray + entry);
5643                 if (status & LastFrag) {
5644                         dev->stats.tx_packets++;
5645                         dev->stats.tx_bytes += tx_skb->skb->len;
5646                         dev_kfree_skb(tx_skb->skb);
5647                         tx_skb->skb = NULL;
5648                 }
5649                 dirty_tx++;
5650                 tx_left--;
5651         }
5652
5653         if (tp->dirty_tx != dirty_tx) {
5654                 tp->dirty_tx = dirty_tx;
5655                 smp_wmb();
5656                 if (netif_queue_stopped(dev) &&
5657                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5658                         netif_wake_queue(dev);
5659                 }
5660                 /*
5661                  * 8168 hack: TxPoll requests are lost when the Tx packets are
5662                  * too close. Let's kick an extra TxPoll request when a burst
5663                  * of start_xmit activity is detected (if it is not detected,
5664                  * it is slow enough). -- FR
5665                  */
5666                 smp_rmb();
5667                 if (tp->cur_tx != dirty_tx)
5668                         RTL_W8(TxPoll, NPQ);
5669         }
5670 }
5671
5672 static inline int rtl8169_fragmented_frame(u32 status)
5673 {
5674         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5675 }
5676
5677 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
5678 {
5679         u32 status = opts1 & RxProtoMask;
5680
5681         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
5682             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
5683                 skb->ip_summed = CHECKSUM_UNNECESSARY;
5684         else
5685                 skb_checksum_none_assert(skb);
5686 }
5687
5688 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5689                                            struct rtl8169_private *tp,
5690                                            int pkt_size,
5691                                            dma_addr_t addr)
5692 {
5693         struct sk_buff *skb;
5694         struct device *d = &tp->pci_dev->dev;
5695
5696         data = rtl8169_align(data);
5697         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5698         prefetch(data);
5699         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5700         if (skb)
5701                 memcpy(skb->data, data, pkt_size);
5702         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5703
5704         return skb;
5705 }
5706
5707 static int rtl8169_rx_interrupt(struct net_device *dev,
5708                                 struct rtl8169_private *tp,
5709                                 void __iomem *ioaddr, u32 budget)
5710 {
5711         unsigned int cur_rx, rx_left;
5712         unsigned int count;
5713
5714         cur_rx = tp->cur_rx;
5715         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5716         rx_left = min(rx_left, budget);
5717
5718         for (; rx_left > 0; rx_left--, cur_rx++) {
5719                 unsigned int entry = cur_rx % NUM_RX_DESC;
5720                 struct RxDesc *desc = tp->RxDescArray + entry;
5721                 u32 status;
5722
5723                 rmb();
5724                 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
5725
5726                 if (status & DescOwn)
5727                         break;
5728                 if (unlikely(status & RxRES)) {
5729                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5730                                    status);
5731                         dev->stats.rx_errors++;
5732                         if (status & (RxRWT | RxRUNT))
5733                                 dev->stats.rx_length_errors++;
5734                         if (status & RxCRC)
5735                                 dev->stats.rx_crc_errors++;
5736                         if (status & RxFOVF) {
5737                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5738                                 dev->stats.rx_fifo_errors++;
5739                         }
5740                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5741                 } else {
5742                         struct sk_buff *skb;
5743                         dma_addr_t addr = le64_to_cpu(desc->addr);
5744                         int pkt_size = (status & 0x00003fff) - 4;
5745
5746                         /*
5747                          * The driver does not support incoming fragmented
5748                          * frames. They are seen as a symptom of over-mtu
5749                          * sized frames.
5750                          */
5751                         if (unlikely(rtl8169_fragmented_frame(status))) {
5752                                 dev->stats.rx_dropped++;
5753                                 dev->stats.rx_length_errors++;
5754                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5755                                 continue;
5756                         }
5757
5758                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5759                                                   tp, pkt_size, addr);
5760                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5761                         if (!skb) {
5762                                 dev->stats.rx_dropped++;
5763                                 continue;
5764                         }
5765
5766                         rtl8169_rx_csum(skb, status);
5767                         skb_put(skb, pkt_size);
5768                         skb->protocol = eth_type_trans(skb, dev);
5769
5770                         rtl8169_rx_vlan_tag(desc, skb);
5771
5772                         napi_gro_receive(&tp->napi, skb);
5773
5774                         dev->stats.rx_bytes += pkt_size;
5775                         dev->stats.rx_packets++;
5776                 }
5777
5778                 /* Work around for AMD plateform. */
5779                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5780                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5781                         desc->opts2 = 0;
5782                         cur_rx++;
5783                 }
5784         }
5785
5786         count = cur_rx - tp->cur_rx;
5787         tp->cur_rx = cur_rx;
5788
5789         tp->dirty_rx += count;
5790
5791         return count;
5792 }
5793
5794 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5795 {
5796         struct net_device *dev = dev_instance;
5797         struct rtl8169_private *tp = netdev_priv(dev);
5798         void __iomem *ioaddr = tp->mmio_addr;
5799         int handled = 0;
5800         int status;
5801
5802         /* loop handling interrupts until we have no new ones or
5803          * we hit a invalid/hotplug case.
5804          */
5805         status = RTL_R16(IntrStatus);
5806         while (status && status != 0xffff) {
5807                 handled = 1;
5808
5809                 /* Handle all of the error cases first. These will reset
5810                  * the chip, so just exit the loop.
5811                  */
5812                 if (unlikely(!netif_running(dev))) {
5813                         rtl8169_hw_reset(tp);
5814                         break;
5815                 }
5816
5817                 if (unlikely(status & RxFIFOOver)) {
5818                         switch (tp->mac_version) {
5819                         /* Work around for rx fifo overflow */
5820                         case RTL_GIGA_MAC_VER_11:
5821                         case RTL_GIGA_MAC_VER_22:
5822                         case RTL_GIGA_MAC_VER_26:
5823                                 netif_stop_queue(dev);
5824                                 rtl8169_tx_timeout(dev);
5825                                 goto done;
5826                         /* Testers needed. */
5827                         case RTL_GIGA_MAC_VER_17:
5828                         case RTL_GIGA_MAC_VER_19:
5829                         case RTL_GIGA_MAC_VER_20:
5830                         case RTL_GIGA_MAC_VER_21:
5831                         case RTL_GIGA_MAC_VER_23:
5832                         case RTL_GIGA_MAC_VER_24:
5833                         case RTL_GIGA_MAC_VER_27:
5834                         case RTL_GIGA_MAC_VER_28:
5835                         case RTL_GIGA_MAC_VER_31:
5836                         /* Experimental science. Pktgen proof. */
5837                         case RTL_GIGA_MAC_VER_12:
5838                         case RTL_GIGA_MAC_VER_25:
5839                                 if (status == RxFIFOOver)
5840                                         goto done;
5841                                 break;
5842                         default:
5843                                 break;
5844                         }
5845                 }
5846
5847                 if (unlikely(status & SYSErr)) {
5848                         rtl8169_pcierr_interrupt(dev);
5849                         break;
5850                 }
5851
5852                 if (status & LinkChg)
5853                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5854
5855                 /* We need to see the lastest version of tp->intr_mask to
5856                  * avoid ignoring an MSI interrupt and having to wait for
5857                  * another event which may never come.
5858                  */
5859                 smp_rmb();
5860                 if (status & tp->intr_mask & tp->napi_event) {
5861                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5862                         tp->intr_mask = ~tp->napi_event;
5863
5864                         if (likely(napi_schedule_prep(&tp->napi)))
5865                                 __napi_schedule(&tp->napi);
5866                         else
5867                                 netif_info(tp, intr, dev,
5868                                            "interrupt %04x in poll\n", status);
5869                 }
5870
5871                 /* We only get a new MSI interrupt when all active irq
5872                  * sources on the chip have been acknowledged. So, ack
5873                  * everything we've seen and check if new sources have become
5874                  * active to avoid blocking all interrupts from the chip.
5875                  */
5876                 RTL_W16(IntrStatus,
5877                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5878                 status = RTL_R16(IntrStatus);
5879         }
5880 done:
5881         return IRQ_RETVAL(handled);
5882 }
5883
5884 static int rtl8169_poll(struct napi_struct *napi, int budget)
5885 {
5886         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5887         struct net_device *dev = tp->dev;
5888         void __iomem *ioaddr = tp->mmio_addr;
5889         int work_done;
5890
5891         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5892         rtl8169_tx_interrupt(dev, tp, ioaddr);
5893
5894         if (work_done < budget) {
5895                 napi_complete(napi);
5896
5897                 /* We need for force the visibility of tp->intr_mask
5898                  * for other CPUs, as we can loose an MSI interrupt
5899                  * and potentially wait for a retransmit timeout if we don't.
5900                  * The posted write to IntrMask is safe, as it will
5901                  * eventually make it to the chip and we won't loose anything
5902                  * until it does.
5903                  */
5904                 tp->intr_mask = 0xffff;
5905                 wmb();
5906                 RTL_W16(IntrMask, tp->intr_event);
5907         }
5908
5909         return work_done;
5910 }
5911
5912 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5913 {
5914         struct rtl8169_private *tp = netdev_priv(dev);
5915
5916         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5917                 return;
5918
5919         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5920         RTL_W32(RxMissed, 0);
5921 }
5922
5923 static void rtl8169_down(struct net_device *dev)
5924 {
5925         struct rtl8169_private *tp = netdev_priv(dev);
5926         void __iomem *ioaddr = tp->mmio_addr;
5927
5928         del_timer_sync(&tp->timer);
5929
5930         netif_stop_queue(dev);
5931
5932         napi_disable(&tp->napi);
5933
5934         spin_lock_irq(&tp->lock);
5935
5936         rtl8169_hw_reset(tp);
5937         /*
5938          * At this point device interrupts can not be enabled in any function,
5939          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5940          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5941          */
5942         rtl8169_rx_missed(dev, ioaddr);
5943
5944         spin_unlock_irq(&tp->lock);
5945
5946         synchronize_irq(dev->irq);
5947
5948         /* Give a racing hard_start_xmit a few cycles to complete. */
5949         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5950
5951         rtl8169_tx_clear(tp);
5952
5953         rtl8169_rx_clear(tp);
5954
5955         rtl_pll_power_down(tp);
5956 }
5957
5958 static int rtl8169_close(struct net_device *dev)
5959 {
5960         struct rtl8169_private *tp = netdev_priv(dev);
5961         struct pci_dev *pdev = tp->pci_dev;
5962
5963         pm_runtime_get_sync(&pdev->dev);
5964
5965         /* Update counters before going down */
5966         rtl8169_update_counters(dev);
5967
5968         rtl8169_down(dev);
5969
5970         free_irq(dev->irq, dev);
5971
5972         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5973                           tp->RxPhyAddr);
5974         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5975                           tp->TxPhyAddr);
5976         tp->TxDescArray = NULL;
5977         tp->RxDescArray = NULL;
5978
5979         pm_runtime_put_sync(&pdev->dev);
5980
5981         return 0;
5982 }
5983
5984 static void rtl_set_rx_mode(struct net_device *dev)
5985 {
5986         struct rtl8169_private *tp = netdev_priv(dev);
5987         void __iomem *ioaddr = tp->mmio_addr;
5988         unsigned long flags;
5989         u32 mc_filter[2];       /* Multicast hash filter */
5990         int rx_mode;
5991         u32 tmp = 0;
5992
5993         if (dev->flags & IFF_PROMISC) {
5994                 /* Unconditionally log net taps. */
5995                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5996                 rx_mode =
5997                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5998                     AcceptAllPhys;
5999                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6000         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
6001                    (dev->flags & IFF_ALLMULTI)) {
6002                 /* Too many to filter perfectly -- accept all multicasts. */
6003                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
6004                 mc_filter[1] = mc_filter[0] = 0xffffffff;
6005         } else {
6006                 struct netdev_hw_addr *ha;
6007
6008                 rx_mode = AcceptBroadcast | AcceptMyPhys;
6009                 mc_filter[1] = mc_filter[0] = 0;
6010                 netdev_for_each_mc_addr(ha, dev) {
6011                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
6012                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
6013                         rx_mode |= AcceptMulticast;
6014                 }
6015         }
6016
6017         spin_lock_irqsave(&tp->lock, flags);
6018
6019         tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
6020
6021         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
6022                 u32 data = mc_filter[0];
6023
6024                 mc_filter[0] = swab32(mc_filter[1]);
6025                 mc_filter[1] = swab32(data);
6026         }
6027
6028         RTL_W32(MAR0 + 4, mc_filter[1]);
6029         RTL_W32(MAR0 + 0, mc_filter[0]);
6030
6031         RTL_W32(RxConfig, tmp);
6032
6033         spin_unlock_irqrestore(&tp->lock, flags);
6034 }
6035
6036 /**
6037  *  rtl8169_get_stats - Get rtl8169 read/write statistics
6038  *  @dev: The Ethernet Device to get statistics for
6039  *
6040  *  Get TX/RX statistics for rtl8169
6041  */
6042 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
6043 {
6044         struct rtl8169_private *tp = netdev_priv(dev);
6045         void __iomem *ioaddr = tp->mmio_addr;
6046         unsigned long flags;
6047
6048         if (netif_running(dev)) {
6049                 spin_lock_irqsave(&tp->lock, flags);
6050                 rtl8169_rx_missed(dev, ioaddr);
6051                 spin_unlock_irqrestore(&tp->lock, flags);
6052         }
6053
6054         return &dev->stats;
6055 }
6056
6057 static void rtl8169_net_suspend(struct net_device *dev)
6058 {
6059         struct rtl8169_private *tp = netdev_priv(dev);
6060
6061         if (!netif_running(dev))
6062                 return;
6063
6064         rtl_pll_power_down(tp);
6065
6066         netif_device_detach(dev);
6067         netif_stop_queue(dev);
6068 }
6069
6070 #ifdef CONFIG_PM
6071
6072 static int rtl8169_suspend(struct device *device)
6073 {
6074         struct pci_dev *pdev = to_pci_dev(device);
6075         struct net_device *dev = pci_get_drvdata(pdev);
6076
6077         rtl8169_net_suspend(dev);
6078
6079         return 0;
6080 }
6081
6082 static void __rtl8169_resume(struct net_device *dev)
6083 {
6084         struct rtl8169_private *tp = netdev_priv(dev);
6085
6086         netif_device_attach(dev);
6087
6088         rtl_pll_power_up(tp);
6089
6090         rtl8169_schedule_work(dev, rtl8169_reset_task);
6091 }
6092
6093 static int rtl8169_resume(struct device *device)
6094 {
6095         struct pci_dev *pdev = to_pci_dev(device);
6096         struct net_device *dev = pci_get_drvdata(pdev);
6097         struct rtl8169_private *tp = netdev_priv(dev);
6098
6099         rtl8169_init_phy(dev, tp);
6100
6101         if (netif_running(dev))
6102                 __rtl8169_resume(dev);
6103
6104         return 0;
6105 }
6106
6107 static int rtl8169_runtime_suspend(struct device *device)
6108 {
6109         struct pci_dev *pdev = to_pci_dev(device);
6110         struct net_device *dev = pci_get_drvdata(pdev);
6111         struct rtl8169_private *tp = netdev_priv(dev);
6112
6113         if (!tp->TxDescArray)
6114                 return 0;
6115
6116         spin_lock_irq(&tp->lock);
6117         tp->saved_wolopts = __rtl8169_get_wol(tp);
6118         __rtl8169_set_wol(tp, WAKE_ANY);
6119         spin_unlock_irq(&tp->lock);
6120
6121         rtl8169_net_suspend(dev);
6122
6123         return 0;
6124 }
6125
6126 static int rtl8169_runtime_resume(struct device *device)
6127 {
6128         struct pci_dev *pdev = to_pci_dev(device);
6129         struct net_device *dev = pci_get_drvdata(pdev);
6130         struct rtl8169_private *tp = netdev_priv(dev);
6131
6132         if (!tp->TxDescArray)
6133                 return 0;
6134
6135         spin_lock_irq(&tp->lock);
6136         __rtl8169_set_wol(tp, tp->saved_wolopts);
6137         tp->saved_wolopts = 0;
6138         spin_unlock_irq(&tp->lock);
6139
6140         rtl8169_init_phy(dev, tp);
6141
6142         __rtl8169_resume(dev);
6143
6144         return 0;
6145 }
6146
6147 static int rtl8169_runtime_idle(struct device *device)
6148 {
6149         struct pci_dev *pdev = to_pci_dev(device);
6150         struct net_device *dev = pci_get_drvdata(pdev);
6151         struct rtl8169_private *tp = netdev_priv(dev);
6152
6153         return tp->TxDescArray ? -EBUSY : 0;
6154 }
6155
6156 static const struct dev_pm_ops rtl8169_pm_ops = {
6157         .suspend                = rtl8169_suspend,
6158         .resume                 = rtl8169_resume,
6159         .freeze                 = rtl8169_suspend,
6160         .thaw                   = rtl8169_resume,
6161         .poweroff               = rtl8169_suspend,
6162         .restore                = rtl8169_resume,
6163         .runtime_suspend        = rtl8169_runtime_suspend,
6164         .runtime_resume         = rtl8169_runtime_resume,
6165         .runtime_idle           = rtl8169_runtime_idle,
6166 };
6167
6168 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
6169
6170 #else /* !CONFIG_PM */
6171
6172 #define RTL8169_PM_OPS  NULL
6173
6174 #endif /* !CONFIG_PM */
6175
6176 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6177 {
6178         void __iomem *ioaddr = tp->mmio_addr;
6179
6180         /* WoL fails with 8168b when the receiver is disabled. */
6181         switch (tp->mac_version) {
6182         case RTL_GIGA_MAC_VER_11:
6183         case RTL_GIGA_MAC_VER_12:
6184         case RTL_GIGA_MAC_VER_17:
6185                 pci_clear_master(tp->pci_dev);
6186
6187                 RTL_W8(ChipCmd, CmdRxEnb);
6188                 /* PCI commit */
6189                 RTL_R8(ChipCmd);
6190                 break;
6191         default:
6192                 break;
6193         }
6194 }
6195
6196 static void rtl_shutdown(struct pci_dev *pdev)
6197 {
6198         struct net_device *dev = pci_get_drvdata(pdev);
6199         struct rtl8169_private *tp = netdev_priv(dev);
6200
6201         rtl8169_net_suspend(dev);
6202
6203         /* Restore original MAC address */
6204         rtl_rar_set(tp, dev->perm_addr);
6205
6206         spin_lock_irq(&tp->lock);
6207
6208         rtl8169_hw_reset(tp);
6209
6210         spin_unlock_irq(&tp->lock);
6211
6212         if (system_state == SYSTEM_POWER_OFF) {
6213                 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
6214                         rtl_wol_suspend_quirk(tp);
6215                         rtl_wol_shutdown_quirk(tp);
6216                 }
6217
6218                 pci_wake_from_d3(pdev, true);
6219                 pci_set_power_state(pdev, PCI_D3hot);
6220         }
6221 }
6222
6223 static struct pci_driver rtl8169_pci_driver = {
6224         .name           = MODULENAME,
6225         .id_table       = rtl8169_pci_tbl,
6226         .probe          = rtl8169_init_one,
6227         .remove         = __devexit_p(rtl8169_remove_one),
6228         .shutdown       = rtl_shutdown,
6229         .driver.pm      = RTL8169_PM_OPS,
6230 };
6231
6232 static int __init rtl8169_init_module(void)
6233 {
6234         return pci_register_driver(&rtl8169_pci_driver);
6235 }
6236
6237 static void __exit rtl8169_cleanup_module(void)
6238 {
6239         pci_unregister_driver(&rtl8169_pci_driver);
6240 }
6241
6242 module_init(rtl8169_init_module);
6243 module_exit(rtl8169_cleanup_module);