1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
19 See the file COPYING in this distribution for more information.
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
28 * Test Tx checksumming thoroughly
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/interrupt.h>
64 #include <linux/pci.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/delay.h>
67 #include <linux/ethtool.h>
68 #include <linux/gfp.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/crc32.h>
74 #include <linux/tcp.h>
75 #include <linux/udp.h>
76 #include <linux/cache.h>
79 #include <asm/uaccess.h>
81 /* These identify the driver base version and may not be removed. */
82 static char version[] =
83 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
85 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
86 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
87 MODULE_VERSION(DRV_VERSION);
88 MODULE_LICENSE("GPL");
90 static int debug = -1;
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
94 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
95 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
96 static int multicast_filter_limit = 32;
97 module_param(multicast_filter_limit, int, 0);
98 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
100 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
103 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
104 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
105 #define CP_REGS_SIZE (0xff + 1)
106 #define CP_REGS_VER 1 /* version 1 */
107 #define CP_RX_RING_SIZE 64
108 #define CP_TX_RING_SIZE 64
109 #define CP_RING_BYTES \
110 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
111 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
113 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
114 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
115 #define TX_BUFFS_AVAIL(CP) \
116 (((CP)->tx_tail <= (CP)->tx_head) ? \
117 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
118 (CP)->tx_tail - (CP)->tx_head - 1)
120 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
121 #define CP_INTERNAL_PHY 32
123 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
124 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
125 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
126 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
129 /* Time in jiffies before concluding the transmitter is hung. */
130 #define TX_TIMEOUT (6*HZ)
132 /* hardware minimum and maximum for a single frame's data payload */
133 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
134 #define CP_MAX_MTU 4096
137 /* NIC register offsets */
138 MAC0 = 0x00, /* Ethernet hardware address. */
139 MAR0 = 0x08, /* Multicast filter. */
140 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
141 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
142 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
143 Cmd = 0x37, /* Command register */
144 IntrMask = 0x3C, /* Interrupt mask */
145 IntrStatus = 0x3E, /* Interrupt status */
146 TxConfig = 0x40, /* Tx configuration */
147 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
148 RxConfig = 0x44, /* Rx configuration */
149 RxMissed = 0x4C, /* 24 bits valid, write clears */
150 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
151 Config1 = 0x52, /* Config1 */
152 Config3 = 0x59, /* Config3 */
153 Config4 = 0x5A, /* Config4 */
154 MultiIntr = 0x5C, /* Multiple interrupt select */
155 BasicModeCtrl = 0x62, /* MII BMCR */
156 BasicModeStatus = 0x64, /* MII BMSR */
157 NWayAdvert = 0x66, /* MII ADVERTISE */
158 NWayLPAR = 0x68, /* MII LPA */
159 NWayExpansion = 0x6A, /* MII Expansion */
160 Config5 = 0xD8, /* Config5 */
161 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
162 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
163 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
164 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
165 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
166 TxThresh = 0xEC, /* Early Tx threshold */
167 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
168 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
170 /* Tx and Rx status descriptors */
171 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
172 RingEnd = (1 << 30), /* End of descriptor ring */
173 FirstFrag = (1 << 29), /* First segment of a packet */
174 LastFrag = (1 << 28), /* Final segment of a packet */
175 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
176 MSSShift = 16, /* MSS value position */
177 MSSMask = 0xfff, /* MSS value: 11 bits */
178 TxError = (1 << 23), /* Tx error summary */
179 RxError = (1 << 20), /* Rx error summary */
180 IPCS = (1 << 18), /* Calculate IP checksum */
181 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
182 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
183 TxVlanTag = (1 << 17), /* Add VLAN tag */
184 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
185 IPFail = (1 << 15), /* IP checksum failed */
186 UDPFail = (1 << 14), /* UDP/IP checksum failed */
187 TCPFail = (1 << 13), /* TCP/IP checksum failed */
188 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
189 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
190 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
194 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
195 TxOWC = (1 << 22), /* Tx Out-of-window collision */
196 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
197 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
198 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
199 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
200 RxErrFrame = (1 << 27), /* Rx frame alignment error */
201 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
202 RxErrCRC = (1 << 18), /* Rx CRC error */
203 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
204 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
205 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
207 /* StatsAddr register */
208 DumpStats = (1 << 3), /* Begin stats dump */
210 /* RxConfig register */
211 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
212 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
213 AcceptErr = 0x20, /* Accept packets with CRC errors */
214 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
215 AcceptBroadcast = 0x08, /* Accept broadcast packets */
216 AcceptMulticast = 0x04, /* Accept multicast packets */
217 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
218 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
220 /* IntrMask / IntrStatus registers */
221 PciErr = (1 << 15), /* System error on the PCI bus */
222 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
223 LenChg = (1 << 13), /* Cable length change */
224 SWInt = (1 << 8), /* Software-requested interrupt */
225 TxEmpty = (1 << 7), /* No Tx descriptors available */
226 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
227 LinkChg = (1 << 5), /* Packet underrun, or link change */
228 RxEmpty = (1 << 4), /* No Rx descriptors available */
229 TxErr = (1 << 3), /* Tx error */
230 TxOK = (1 << 2), /* Tx packet sent */
231 RxErr = (1 << 1), /* Rx error */
232 RxOK = (1 << 0), /* Rx packet received */
233 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
234 but hardware likes to raise it */
236 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
237 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
238 RxErr | RxOK | IntrResvd,
240 /* C mode command register */
241 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
242 RxOn = (1 << 3), /* Rx mode enable */
243 TxOn = (1 << 2), /* Tx mode enable */
245 /* C+ mode command register */
246 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
247 RxChkSum = (1 << 5), /* Rx checksum offload enable */
248 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
249 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
250 CpRxOn = (1 << 1), /* Rx mode enable */
251 CpTxOn = (1 << 0), /* Tx mode enable */
253 /* Cfg9436 EEPROM control register */
254 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
255 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
257 /* TxConfig register */
258 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
259 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
261 /* Early Tx Threshold register */
262 TxThreshMask = 0x3f, /* Mask bits 5-0 */
263 TxThreshMax = 2048, /* Max early Tx threshold */
265 /* Config1 register */
266 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
267 LWACT = (1 << 4), /* LWAKE active mode */
268 PMEnable = (1 << 0), /* Enable various PM features of chip */
270 /* Config3 register */
271 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
272 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
273 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
275 /* Config4 register */
276 LWPTN = (1 << 1), /* LWAKE Pattern */
277 LWPME = (1 << 4), /* LANWAKE vs PMEB */
279 /* Config5 register */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LANWake = (1 << 1), /* Enable LANWake signal */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
286 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
287 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
288 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
291 static const unsigned int cp_rx_config =
292 (RX_FIFO_THRESH << RxCfgFIFOShift) |
293 (RX_DMA_BURST << RxCfgDMAShift);
301 struct cp_dma_stats {
317 struct cp_extra_stats {
318 unsigned long rx_frags;
323 struct net_device *dev;
327 struct napi_struct napi;
329 struct pci_dev *pdev;
333 struct cp_extra_stats cp_stats;
335 unsigned rx_head ____cacheline_aligned;
337 struct cp_desc *rx_ring;
338 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
340 unsigned tx_head ____cacheline_aligned;
342 struct cp_desc *tx_ring;
343 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
346 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
350 struct mii_if_info mii_if;
353 #define cpr8(reg) readb(cp->regs + (reg))
354 #define cpr16(reg) readw(cp->regs + (reg))
355 #define cpr32(reg) readl(cp->regs + (reg))
356 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
357 #define cpw16(reg,val) writew((val), cp->regs + (reg))
358 #define cpw32(reg,val) writel((val), cp->regs + (reg))
359 #define cpw8_f(reg,val) do { \
360 writeb((val), cp->regs + (reg)); \
361 readb(cp->regs + (reg)); \
363 #define cpw16_f(reg,val) do { \
364 writew((val), cp->regs + (reg)); \
365 readw(cp->regs + (reg)); \
367 #define cpw32_f(reg,val) do { \
368 writel((val), cp->regs + (reg)); \
369 readl(cp->regs + (reg)); \
373 static void __cp_set_rx_mode (struct net_device *dev);
374 static void cp_tx (struct cp_private *cp);
375 static void cp_clean_rings (struct cp_private *cp);
376 #ifdef CONFIG_NET_POLL_CONTROLLER
377 static void cp_poll_controller(struct net_device *dev);
379 static int cp_get_eeprom_len(struct net_device *dev);
380 static int cp_get_eeprom(struct net_device *dev,
381 struct ethtool_eeprom *eeprom, u8 *data);
382 static int cp_set_eeprom(struct net_device *dev,
383 struct ethtool_eeprom *eeprom, u8 *data);
385 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
386 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
387 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
390 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
393 const char str[ETH_GSTRING_LEN];
394 } ethtool_stats_keys[] = {
412 static inline void cp_set_rxbufsize (struct cp_private *cp)
414 unsigned int mtu = cp->dev->mtu;
416 if (mtu > ETH_DATA_LEN)
417 /* MTU + ethernet header + FCS + optional VLAN tag */
418 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
420 cp->rx_buf_sz = PKT_BUF_SZ;
423 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
424 struct cp_desc *desc)
426 u32 opts2 = le32_to_cpu(desc->opts2);
428 skb->protocol = eth_type_trans (skb, cp->dev);
430 cp->dev->stats.rx_packets++;
431 cp->dev->stats.rx_bytes += skb->len;
433 if (opts2 & RxVlanTagged)
434 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
436 napi_gro_receive(&cp->napi, skb);
439 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
442 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
443 rx_tail, status, len);
444 cp->dev->stats.rx_errors++;
445 if (status & RxErrFrame)
446 cp->dev->stats.rx_frame_errors++;
447 if (status & RxErrCRC)
448 cp->dev->stats.rx_crc_errors++;
449 if ((status & RxErrRunt) || (status & RxErrLong))
450 cp->dev->stats.rx_length_errors++;
451 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
452 cp->dev->stats.rx_length_errors++;
453 if (status & RxErrFIFO)
454 cp->dev->stats.rx_fifo_errors++;
457 static inline unsigned int cp_rx_csum_ok (u32 status)
459 unsigned int protocol = (status >> 16) & 0x3;
461 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
462 ((protocol == RxProtoUDP) && !(status & UDPFail)))
468 static int cp_rx_poll(struct napi_struct *napi, int budget)
470 struct cp_private *cp = container_of(napi, struct cp_private, napi);
471 struct net_device *dev = cp->dev;
472 unsigned int rx_tail = cp->rx_tail;
477 cpw16(IntrStatus, cp_rx_intr_mask);
482 struct sk_buff *skb, *new_skb;
483 struct cp_desc *desc;
484 const unsigned buflen = cp->rx_buf_sz;
486 skb = cp->rx_skb[rx_tail];
489 desc = &cp->rx_ring[rx_tail];
490 status = le32_to_cpu(desc->opts1);
491 if (status & DescOwn)
494 len = (status & 0x1fff) - 4;
495 mapping = le64_to_cpu(desc->addr);
497 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
498 /* we don't support incoming fragmented frames.
499 * instead, we attempt to ensure that the
500 * pre-allocated RX skbs are properly sized such
501 * that RX fragments are never encountered
503 cp_rx_err_acct(cp, rx_tail, status, len);
504 dev->stats.rx_dropped++;
505 cp->cp_stats.rx_frags++;
509 if (status & (RxError | RxErrFIFO)) {
510 cp_rx_err_acct(cp, rx_tail, status, len);
514 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
515 rx_tail, status, len);
517 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
519 dev->stats.rx_dropped++;
523 dma_unmap_single(&cp->pdev->dev, mapping,
524 buflen, PCI_DMA_FROMDEVICE);
526 /* Handle checksum offloading for incoming packets. */
527 if (cp_rx_csum_ok(status))
528 skb->ip_summed = CHECKSUM_UNNECESSARY;
530 skb_checksum_none_assert(skb);
534 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
536 cp->rx_skb[rx_tail] = new_skb;
538 cp_rx_skb(cp, skb, desc);
542 cp->rx_ring[rx_tail].opts2 = 0;
543 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
544 if (rx_tail == (CP_RX_RING_SIZE - 1))
545 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
548 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
549 rx_tail = NEXT_RX(rx_tail);
555 cp->rx_tail = rx_tail;
557 /* if we did not reach work limit, then we're done with
558 * this round of polling
563 if (cpr16(IntrStatus) & cp_rx_intr_mask)
566 napi_gro_flush(napi);
567 spin_lock_irqsave(&cp->lock, flags);
568 __napi_complete(napi);
569 cpw16_f(IntrMask, cp_intr_mask);
570 spin_unlock_irqrestore(&cp->lock, flags);
576 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
578 struct net_device *dev = dev_instance;
579 struct cp_private *cp;
582 if (unlikely(dev == NULL))
584 cp = netdev_priv(dev);
586 status = cpr16(IntrStatus);
587 if (!status || (status == 0xFFFF))
590 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
591 status, cpr8(Cmd), cpr16(CpCmd));
593 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
595 spin_lock(&cp->lock);
597 /* close possible race's with dev_close */
598 if (unlikely(!netif_running(dev))) {
600 spin_unlock(&cp->lock);
604 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
605 if (napi_schedule_prep(&cp->napi)) {
606 cpw16_f(IntrMask, cp_norx_intr_mask);
607 __napi_schedule(&cp->napi);
610 if (status & (TxOK | TxErr | TxEmpty | SWInt))
612 if (status & LinkChg)
613 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
615 spin_unlock(&cp->lock);
617 if (status & PciErr) {
620 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
621 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
622 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
625 /* TODO: reset hardware */
631 #ifdef CONFIG_NET_POLL_CONTROLLER
633 * Polling receive - used by netconsole and other diagnostic tools
634 * to allow network i/o with interrupts disabled.
636 static void cp_poll_controller(struct net_device *dev)
638 disable_irq(dev->irq);
639 cp_interrupt(dev->irq, dev);
640 enable_irq(dev->irq);
644 static void cp_tx (struct cp_private *cp)
646 unsigned tx_head = cp->tx_head;
647 unsigned tx_tail = cp->tx_tail;
649 while (tx_tail != tx_head) {
650 struct cp_desc *txd = cp->tx_ring + tx_tail;
655 status = le32_to_cpu(txd->opts1);
656 if (status & DescOwn)
659 skb = cp->tx_skb[tx_tail];
662 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
663 le32_to_cpu(txd->opts1) & 0xffff,
666 if (status & LastFrag) {
667 if (status & (TxError | TxFIFOUnder)) {
668 netif_dbg(cp, tx_err, cp->dev,
669 "tx err, status 0x%x\n", status);
670 cp->dev->stats.tx_errors++;
672 cp->dev->stats.tx_window_errors++;
673 if (status & TxMaxCol)
674 cp->dev->stats.tx_aborted_errors++;
675 if (status & TxLinkFail)
676 cp->dev->stats.tx_carrier_errors++;
677 if (status & TxFIFOUnder)
678 cp->dev->stats.tx_fifo_errors++;
680 cp->dev->stats.collisions +=
681 ((status >> TxColCntShift) & TxColCntMask);
682 cp->dev->stats.tx_packets++;
683 cp->dev->stats.tx_bytes += skb->len;
684 netif_dbg(cp, tx_done, cp->dev,
685 "tx done, slot %d\n", tx_tail);
687 dev_kfree_skb_irq(skb);
690 cp->tx_skb[tx_tail] = NULL;
692 tx_tail = NEXT_TX(tx_tail);
695 cp->tx_tail = tx_tail;
697 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
698 netif_wake_queue(cp->dev);
701 static inline u32 cp_tx_vlan_tag(struct sk_buff *skb)
703 return vlan_tx_tag_present(skb) ?
704 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
707 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
708 struct net_device *dev)
710 struct cp_private *cp = netdev_priv(dev);
713 unsigned long intr_flags;
717 spin_lock_irqsave(&cp->lock, intr_flags);
719 /* This is a hard error, log it. */
720 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
721 netif_stop_queue(dev);
722 spin_unlock_irqrestore(&cp->lock, intr_flags);
723 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
724 return NETDEV_TX_BUSY;
728 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
729 mss = skb_shinfo(skb)->gso_size;
731 opts2 = cpu_to_le32(cp_tx_vlan_tag(skb));
733 if (skb_shinfo(skb)->nr_frags == 0) {
734 struct cp_desc *txd = &cp->tx_ring[entry];
739 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
741 txd->addr = cpu_to_le64(mapping);
744 flags = eor | len | DescOwn | FirstFrag | LastFrag;
747 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
748 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
749 const struct iphdr *ip = ip_hdr(skb);
750 if (ip->protocol == IPPROTO_TCP)
751 flags |= IPCS | TCPCS;
752 else if (ip->protocol == IPPROTO_UDP)
753 flags |= IPCS | UDPCS;
755 WARN_ON(1); /* we need a WARN() */
758 txd->opts1 = cpu_to_le32(flags);
761 cp->tx_skb[entry] = skb;
762 entry = NEXT_TX(entry);
765 u32 first_len, first_eor;
766 dma_addr_t first_mapping;
767 int frag, first_entry = entry;
768 const struct iphdr *ip = ip_hdr(skb);
770 /* We must give this initial chunk to the device last.
771 * Otherwise we could race with the device.
774 first_len = skb_headlen(skb);
775 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
776 first_len, PCI_DMA_TODEVICE);
777 cp->tx_skb[entry] = skb;
778 entry = NEXT_TX(entry);
780 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
781 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
786 len = skb_frag_size(this_frag);
787 mapping = dma_map_single(&cp->pdev->dev,
788 skb_frag_address(this_frag),
789 len, PCI_DMA_TODEVICE);
790 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
792 ctrl = eor | len | DescOwn;
796 ((mss & MSSMask) << MSSShift);
797 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
798 if (ip->protocol == IPPROTO_TCP)
799 ctrl |= IPCS | TCPCS;
800 else if (ip->protocol == IPPROTO_UDP)
801 ctrl |= IPCS | UDPCS;
806 if (frag == skb_shinfo(skb)->nr_frags - 1)
809 txd = &cp->tx_ring[entry];
811 txd->addr = cpu_to_le64(mapping);
814 txd->opts1 = cpu_to_le32(ctrl);
817 cp->tx_skb[entry] = skb;
818 entry = NEXT_TX(entry);
821 txd = &cp->tx_ring[first_entry];
823 txd->addr = cpu_to_le64(first_mapping);
826 if (skb->ip_summed == CHECKSUM_PARTIAL) {
827 if (ip->protocol == IPPROTO_TCP)
828 txd->opts1 = cpu_to_le32(first_eor | first_len |
829 FirstFrag | DescOwn |
831 else if (ip->protocol == IPPROTO_UDP)
832 txd->opts1 = cpu_to_le32(first_eor | first_len |
833 FirstFrag | DescOwn |
838 txd->opts1 = cpu_to_le32(first_eor | first_len |
839 FirstFrag | DescOwn);
843 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
845 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
846 netif_stop_queue(dev);
848 spin_unlock_irqrestore(&cp->lock, intr_flags);
850 cpw8(TxPoll, NormalTxPoll);
855 /* Set or clear the multicast filter for this adaptor.
856 This routine is not state sensitive and need not be SMP locked. */
858 static void __cp_set_rx_mode (struct net_device *dev)
860 struct cp_private *cp = netdev_priv(dev);
861 u32 mc_filter[2]; /* Multicast hash filter */
865 /* Note: do not reorder, GCC is clever about common statements. */
866 if (dev->flags & IFF_PROMISC) {
867 /* Unconditionally log net taps. */
869 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
871 mc_filter[1] = mc_filter[0] = 0xffffffff;
872 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
873 (dev->flags & IFF_ALLMULTI)) {
874 /* Too many to filter perfectly -- accept all multicasts. */
875 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
876 mc_filter[1] = mc_filter[0] = 0xffffffff;
878 struct netdev_hw_addr *ha;
879 rx_mode = AcceptBroadcast | AcceptMyPhys;
880 mc_filter[1] = mc_filter[0] = 0;
881 netdev_for_each_mc_addr(ha, dev) {
882 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
884 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
885 rx_mode |= AcceptMulticast;
889 /* We can safely update without stopping the chip. */
890 tmp = cp_rx_config | rx_mode;
891 if (cp->rx_config != tmp) {
892 cpw32_f (RxConfig, tmp);
895 cpw32_f (MAR0 + 0, mc_filter[0]);
896 cpw32_f (MAR0 + 4, mc_filter[1]);
899 static void cp_set_rx_mode (struct net_device *dev)
902 struct cp_private *cp = netdev_priv(dev);
904 spin_lock_irqsave (&cp->lock, flags);
905 __cp_set_rx_mode(dev);
906 spin_unlock_irqrestore (&cp->lock, flags);
909 static void __cp_get_stats(struct cp_private *cp)
911 /* only lower 24 bits valid; write any value to clear */
912 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
916 static struct net_device_stats *cp_get_stats(struct net_device *dev)
918 struct cp_private *cp = netdev_priv(dev);
921 /* The chip only need report frame silently dropped. */
922 spin_lock_irqsave(&cp->lock, flags);
923 if (netif_running(dev) && netif_device_present(dev))
925 spin_unlock_irqrestore(&cp->lock, flags);
930 static void cp_stop_hw (struct cp_private *cp)
932 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
933 cpw16_f(IntrMask, 0);
936 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
939 cp->tx_head = cp->tx_tail = 0;
942 static void cp_reset_hw (struct cp_private *cp)
944 unsigned work = 1000;
949 if (!(cpr8(Cmd) & CmdReset))
952 schedule_timeout_uninterruptible(10);
955 netdev_err(cp->dev, "hardware reset timeout\n");
958 static inline void cp_start_hw (struct cp_private *cp)
960 cpw16(CpCmd, cp->cpcmd);
961 cpw8(Cmd, RxOn | TxOn);
964 static void cp_enable_irq(struct cp_private *cp)
966 cpw16_f(IntrMask, cp_intr_mask);
969 static void cp_init_hw (struct cp_private *cp)
971 struct net_device *dev = cp->dev;
976 cpw8_f (Cfg9346, Cfg9346_Unlock);
978 /* Restore our idea of the MAC address. */
979 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
980 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
983 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
985 __cp_set_rx_mode(dev);
986 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
988 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
989 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
990 cpw8(Config3, PARMEnable);
993 cpw8(Config5, cpr8(Config5) & PMEStatus);
995 cpw32_f(HiTxRingAddr, 0);
996 cpw32_f(HiTxRingAddr + 4, 0);
998 ring_dma = cp->ring_dma;
999 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1000 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1002 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1003 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1004 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1006 cpw16(MultiIntr, 0);
1008 cpw8_f(Cfg9346, Cfg9346_Lock);
1011 static int cp_refill_rx(struct cp_private *cp)
1013 struct net_device *dev = cp->dev;
1016 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1017 struct sk_buff *skb;
1020 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1024 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1025 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1026 cp->rx_skb[i] = skb;
1028 cp->rx_ring[i].opts2 = 0;
1029 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1030 if (i == (CP_RX_RING_SIZE - 1))
1031 cp->rx_ring[i].opts1 =
1032 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1034 cp->rx_ring[i].opts1 =
1035 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1045 static void cp_init_rings_index (struct cp_private *cp)
1048 cp->tx_head = cp->tx_tail = 0;
1051 static int cp_init_rings (struct cp_private *cp)
1053 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1054 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1056 cp_init_rings_index(cp);
1058 return cp_refill_rx (cp);
1061 static int cp_alloc_rings (struct cp_private *cp)
1065 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1066 &cp->ring_dma, GFP_KERNEL);
1071 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1073 return cp_init_rings(cp);
1076 static void cp_clean_rings (struct cp_private *cp)
1078 struct cp_desc *desc;
1081 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1082 if (cp->rx_skb[i]) {
1083 desc = cp->rx_ring + i;
1084 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1085 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1086 dev_kfree_skb(cp->rx_skb[i]);
1090 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1091 if (cp->tx_skb[i]) {
1092 struct sk_buff *skb = cp->tx_skb[i];
1094 desc = cp->tx_ring + i;
1095 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1096 le32_to_cpu(desc->opts1) & 0xffff,
1098 if (le32_to_cpu(desc->opts1) & LastFrag)
1100 cp->dev->stats.tx_dropped++;
1104 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1105 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1107 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1108 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1111 static void cp_free_rings (struct cp_private *cp)
1114 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1120 static int cp_open (struct net_device *dev)
1122 struct cp_private *cp = netdev_priv(dev);
1125 netif_dbg(cp, ifup, dev, "enabling interface\n");
1127 rc = cp_alloc_rings(cp);
1131 napi_enable(&cp->napi);
1135 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1141 netif_carrier_off(dev);
1142 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1143 netif_start_queue(dev);
1148 napi_disable(&cp->napi);
1154 static int cp_close (struct net_device *dev)
1156 struct cp_private *cp = netdev_priv(dev);
1157 unsigned long flags;
1159 napi_disable(&cp->napi);
1161 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1163 spin_lock_irqsave(&cp->lock, flags);
1165 netif_stop_queue(dev);
1166 netif_carrier_off(dev);
1170 spin_unlock_irqrestore(&cp->lock, flags);
1172 free_irq(dev->irq, dev);
1178 static void cp_tx_timeout(struct net_device *dev)
1180 struct cp_private *cp = netdev_priv(dev);
1181 unsigned long flags;
1184 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1185 cpr8(Cmd), cpr16(CpCmd),
1186 cpr16(IntrStatus), cpr16(IntrMask));
1188 spin_lock_irqsave(&cp->lock, flags);
1192 rc = cp_init_rings(cp);
1195 netif_wake_queue(dev);
1197 spin_unlock_irqrestore(&cp->lock, flags);
1201 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1203 struct cp_private *cp = netdev_priv(dev);
1205 unsigned long flags;
1207 /* check for invalid MTU, according to hardware limits */
1208 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1211 /* if network interface not up, no need for complexity */
1212 if (!netif_running(dev)) {
1214 cp_set_rxbufsize(cp); /* set new rx buf size */
1218 spin_lock_irqsave(&cp->lock, flags);
1220 cp_stop_hw(cp); /* stop h/w and free rings */
1224 cp_set_rxbufsize(cp); /* set new rx buf size */
1226 rc = cp_init_rings(cp); /* realloc and restart h/w */
1229 spin_unlock_irqrestore(&cp->lock, flags);
1235 static const char mii_2_8139_map[8] = {
1246 static int mdio_read(struct net_device *dev, int phy_id, int location)
1248 struct cp_private *cp = netdev_priv(dev);
1250 return location < 8 && mii_2_8139_map[location] ?
1251 readw(cp->regs + mii_2_8139_map[location]) : 0;
1255 static void mdio_write(struct net_device *dev, int phy_id, int location,
1258 struct cp_private *cp = netdev_priv(dev);
1260 if (location == 0) {
1261 cpw8(Cfg9346, Cfg9346_Unlock);
1262 cpw16(BasicModeCtrl, value);
1263 cpw8(Cfg9346, Cfg9346_Lock);
1264 } else if (location < 8 && mii_2_8139_map[location])
1265 cpw16(mii_2_8139_map[location], value);
1268 /* Set the ethtool Wake-on-LAN settings */
1269 static int netdev_set_wol (struct cp_private *cp,
1270 const struct ethtool_wolinfo *wol)
1274 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1275 /* If WOL is being disabled, no need for complexity */
1277 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1278 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1281 cpw8 (Cfg9346, Cfg9346_Unlock);
1282 cpw8 (Config3, options);
1283 cpw8 (Cfg9346, Cfg9346_Lock);
1285 options = 0; /* Paranoia setting */
1286 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1287 /* If WOL is being disabled, no need for complexity */
1289 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1290 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1291 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1294 cpw8 (Config5, options);
1296 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1301 /* Get the ethtool Wake-on-LAN settings */
1302 static void netdev_get_wol (struct cp_private *cp,
1303 struct ethtool_wolinfo *wol)
1307 wol->wolopts = 0; /* Start from scratch */
1308 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1309 WAKE_MCAST | WAKE_UCAST;
1310 /* We don't need to go on if WOL is disabled */
1311 if (!cp->wol_enabled) return;
1313 options = cpr8 (Config3);
1314 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1315 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1317 options = 0; /* Paranoia setting */
1318 options = cpr8 (Config5);
1319 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1320 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1321 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1324 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1326 struct cp_private *cp = netdev_priv(dev);
1328 strcpy (info->driver, DRV_NAME);
1329 strcpy (info->version, DRV_VERSION);
1330 strcpy (info->bus_info, pci_name(cp->pdev));
1333 static void cp_get_ringparam(struct net_device *dev,
1334 struct ethtool_ringparam *ring)
1336 ring->rx_max_pending = CP_RX_RING_SIZE;
1337 ring->tx_max_pending = CP_TX_RING_SIZE;
1338 ring->rx_pending = CP_RX_RING_SIZE;
1339 ring->tx_pending = CP_TX_RING_SIZE;
1342 static int cp_get_regs_len(struct net_device *dev)
1344 return CP_REGS_SIZE;
1347 static int cp_get_sset_count (struct net_device *dev, int sset)
1351 return CP_NUM_STATS;
1357 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1359 struct cp_private *cp = netdev_priv(dev);
1361 unsigned long flags;
1363 spin_lock_irqsave(&cp->lock, flags);
1364 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1365 spin_unlock_irqrestore(&cp->lock, flags);
1370 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1372 struct cp_private *cp = netdev_priv(dev);
1374 unsigned long flags;
1376 spin_lock_irqsave(&cp->lock, flags);
1377 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1378 spin_unlock_irqrestore(&cp->lock, flags);
1383 static int cp_nway_reset(struct net_device *dev)
1385 struct cp_private *cp = netdev_priv(dev);
1386 return mii_nway_restart(&cp->mii_if);
1389 static u32 cp_get_msglevel(struct net_device *dev)
1391 struct cp_private *cp = netdev_priv(dev);
1392 return cp->msg_enable;
1395 static void cp_set_msglevel(struct net_device *dev, u32 value)
1397 struct cp_private *cp = netdev_priv(dev);
1398 cp->msg_enable = value;
1401 static int cp_set_features(struct net_device *dev, u32 features)
1403 struct cp_private *cp = netdev_priv(dev);
1404 unsigned long flags;
1406 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1409 spin_lock_irqsave(&cp->lock, flags);
1411 if (features & NETIF_F_RXCSUM)
1412 cp->cpcmd |= RxChkSum;
1414 cp->cpcmd &= ~RxChkSum;
1416 if (features & NETIF_F_HW_VLAN_RX)
1417 cp->cpcmd |= RxVlanOn;
1419 cp->cpcmd &= ~RxVlanOn;
1421 cpw16_f(CpCmd, cp->cpcmd);
1422 spin_unlock_irqrestore(&cp->lock, flags);
1427 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1430 struct cp_private *cp = netdev_priv(dev);
1431 unsigned long flags;
1433 if (regs->len < CP_REGS_SIZE)
1434 return /* -EINVAL */;
1436 regs->version = CP_REGS_VER;
1438 spin_lock_irqsave(&cp->lock, flags);
1439 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1440 spin_unlock_irqrestore(&cp->lock, flags);
1443 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1445 struct cp_private *cp = netdev_priv(dev);
1446 unsigned long flags;
1448 spin_lock_irqsave (&cp->lock, flags);
1449 netdev_get_wol (cp, wol);
1450 spin_unlock_irqrestore (&cp->lock, flags);
1453 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1455 struct cp_private *cp = netdev_priv(dev);
1456 unsigned long flags;
1459 spin_lock_irqsave (&cp->lock, flags);
1460 rc = netdev_set_wol (cp, wol);
1461 spin_unlock_irqrestore (&cp->lock, flags);
1466 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1468 switch (stringset) {
1470 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
1478 static void cp_get_ethtool_stats (struct net_device *dev,
1479 struct ethtool_stats *estats, u64 *tmp_stats)
1481 struct cp_private *cp = netdev_priv(dev);
1482 struct cp_dma_stats *nic_stats;
1486 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1491 /* begin NIC statistics dump */
1492 cpw32(StatsAddr + 4, (u64)dma >> 32);
1493 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1496 for (i = 0; i < 1000; i++) {
1497 if ((cpr32(StatsAddr) & DumpStats) == 0)
1501 cpw32(StatsAddr, 0);
1502 cpw32(StatsAddr + 4, 0);
1506 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1507 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1508 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1509 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1510 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1511 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1512 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1513 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1514 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1515 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1516 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1517 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1518 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1519 tmp_stats[i++] = cp->cp_stats.rx_frags;
1520 BUG_ON(i != CP_NUM_STATS);
1522 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1525 static const struct ethtool_ops cp_ethtool_ops = {
1526 .get_drvinfo = cp_get_drvinfo,
1527 .get_regs_len = cp_get_regs_len,
1528 .get_sset_count = cp_get_sset_count,
1529 .get_settings = cp_get_settings,
1530 .set_settings = cp_set_settings,
1531 .nway_reset = cp_nway_reset,
1532 .get_link = ethtool_op_get_link,
1533 .get_msglevel = cp_get_msglevel,
1534 .set_msglevel = cp_set_msglevel,
1535 .get_regs = cp_get_regs,
1536 .get_wol = cp_get_wol,
1537 .set_wol = cp_set_wol,
1538 .get_strings = cp_get_strings,
1539 .get_ethtool_stats = cp_get_ethtool_stats,
1540 .get_eeprom_len = cp_get_eeprom_len,
1541 .get_eeprom = cp_get_eeprom,
1542 .set_eeprom = cp_set_eeprom,
1543 .get_ringparam = cp_get_ringparam,
1546 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1548 struct cp_private *cp = netdev_priv(dev);
1550 unsigned long flags;
1552 if (!netif_running(dev))
1555 spin_lock_irqsave(&cp->lock, flags);
1556 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1557 spin_unlock_irqrestore(&cp->lock, flags);
1561 static int cp_set_mac_address(struct net_device *dev, void *p)
1563 struct cp_private *cp = netdev_priv(dev);
1564 struct sockaddr *addr = p;
1566 if (!is_valid_ether_addr(addr->sa_data))
1567 return -EADDRNOTAVAIL;
1569 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1571 spin_lock_irq(&cp->lock);
1573 cpw8_f(Cfg9346, Cfg9346_Unlock);
1574 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1575 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1576 cpw8_f(Cfg9346, Cfg9346_Lock);
1578 spin_unlock_irq(&cp->lock);
1583 /* Serial EEPROM section. */
1585 /* EEPROM_Ctrl bits. */
1586 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1587 #define EE_CS 0x08 /* EEPROM chip select. */
1588 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1589 #define EE_WRITE_0 0x00
1590 #define EE_WRITE_1 0x02
1591 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1592 #define EE_ENB (0x80 | EE_CS)
1594 /* Delay between EEPROM clock transitions.
1595 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1598 #define eeprom_delay() readl(ee_addr)
1600 /* The EEPROM commands include the alway-set leading bit. */
1601 #define EE_EXTEND_CMD (4)
1602 #define EE_WRITE_CMD (5)
1603 #define EE_READ_CMD (6)
1604 #define EE_ERASE_CMD (7)
1606 #define EE_EWDS_ADDR (0)
1607 #define EE_WRAL_ADDR (1)
1608 #define EE_ERAL_ADDR (2)
1609 #define EE_EWEN_ADDR (3)
1611 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1613 static void eeprom_cmd_start(void __iomem *ee_addr)
1615 writeb (EE_ENB & ~EE_CS, ee_addr);
1616 writeb (EE_ENB, ee_addr);
1620 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1624 /* Shift the command bits out. */
1625 for (i = cmd_len - 1; i >= 0; i--) {
1626 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1627 writeb (EE_ENB | dataval, ee_addr);
1629 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1632 writeb (EE_ENB, ee_addr);
1636 static void eeprom_cmd_end(void __iomem *ee_addr)
1638 writeb (~EE_CS, ee_addr);
1642 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1645 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1647 eeprom_cmd_start(ee_addr);
1648 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1649 eeprom_cmd_end(ee_addr);
1652 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1656 void __iomem *ee_addr = ioaddr + Cfg9346;
1657 int read_cmd = location | (EE_READ_CMD << addr_len);
1659 eeprom_cmd_start(ee_addr);
1660 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1662 for (i = 16; i > 0; i--) {
1663 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1666 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1668 writeb (EE_ENB, ee_addr);
1672 eeprom_cmd_end(ee_addr);
1677 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1681 void __iomem *ee_addr = ioaddr + Cfg9346;
1682 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1684 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1686 eeprom_cmd_start(ee_addr);
1687 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1688 eeprom_cmd(ee_addr, val, 16);
1689 eeprom_cmd_end(ee_addr);
1691 eeprom_cmd_start(ee_addr);
1692 for (i = 0; i < 20000; i++)
1693 if (readb(ee_addr) & EE_DATA_READ)
1695 eeprom_cmd_end(ee_addr);
1697 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1700 static int cp_get_eeprom_len(struct net_device *dev)
1702 struct cp_private *cp = netdev_priv(dev);
1705 spin_lock_irq(&cp->lock);
1706 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1707 spin_unlock_irq(&cp->lock);
1712 static int cp_get_eeprom(struct net_device *dev,
1713 struct ethtool_eeprom *eeprom, u8 *data)
1715 struct cp_private *cp = netdev_priv(dev);
1716 unsigned int addr_len;
1718 u32 offset = eeprom->offset >> 1;
1719 u32 len = eeprom->len;
1722 eeprom->magic = CP_EEPROM_MAGIC;
1724 spin_lock_irq(&cp->lock);
1726 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1728 if (eeprom->offset & 1) {
1729 val = read_eeprom(cp->regs, offset, addr_len);
1730 data[i++] = (u8)(val >> 8);
1734 while (i < len - 1) {
1735 val = read_eeprom(cp->regs, offset, addr_len);
1736 data[i++] = (u8)val;
1737 data[i++] = (u8)(val >> 8);
1742 val = read_eeprom(cp->regs, offset, addr_len);
1746 spin_unlock_irq(&cp->lock);
1750 static int cp_set_eeprom(struct net_device *dev,
1751 struct ethtool_eeprom *eeprom, u8 *data)
1753 struct cp_private *cp = netdev_priv(dev);
1754 unsigned int addr_len;
1756 u32 offset = eeprom->offset >> 1;
1757 u32 len = eeprom->len;
1760 if (eeprom->magic != CP_EEPROM_MAGIC)
1763 spin_lock_irq(&cp->lock);
1765 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1767 if (eeprom->offset & 1) {
1768 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1769 val |= (u16)data[i++] << 8;
1770 write_eeprom(cp->regs, offset, val, addr_len);
1774 while (i < len - 1) {
1775 val = (u16)data[i++];
1776 val |= (u16)data[i++] << 8;
1777 write_eeprom(cp->regs, offset, val, addr_len);
1782 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1783 val |= (u16)data[i];
1784 write_eeprom(cp->regs, offset, val, addr_len);
1787 spin_unlock_irq(&cp->lock);
1791 /* Put the board into D3cold state and wait for WakeUp signal */
1792 static void cp_set_d3_state (struct cp_private *cp)
1794 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1795 pci_set_power_state (cp->pdev, PCI_D3hot);
1798 static const struct net_device_ops cp_netdev_ops = {
1799 .ndo_open = cp_open,
1800 .ndo_stop = cp_close,
1801 .ndo_validate_addr = eth_validate_addr,
1802 .ndo_set_mac_address = cp_set_mac_address,
1803 .ndo_set_rx_mode = cp_set_rx_mode,
1804 .ndo_get_stats = cp_get_stats,
1805 .ndo_do_ioctl = cp_ioctl,
1806 .ndo_start_xmit = cp_start_xmit,
1807 .ndo_tx_timeout = cp_tx_timeout,
1808 .ndo_set_features = cp_set_features,
1810 .ndo_change_mtu = cp_change_mtu,
1813 #ifdef CONFIG_NET_POLL_CONTROLLER
1814 .ndo_poll_controller = cp_poll_controller,
1818 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1820 struct net_device *dev;
1821 struct cp_private *cp;
1824 resource_size_t pciaddr;
1825 unsigned int addr_len, i, pci_using_dac;
1828 static int version_printed;
1829 if (version_printed++ == 0)
1830 pr_info("%s", version);
1833 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1834 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1835 dev_info(&pdev->dev,
1836 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1837 pdev->vendor, pdev->device, pdev->revision);
1841 dev = alloc_etherdev(sizeof(struct cp_private));
1844 SET_NETDEV_DEV(dev, &pdev->dev);
1846 cp = netdev_priv(dev);
1849 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1850 spin_lock_init (&cp->lock);
1851 cp->mii_if.dev = dev;
1852 cp->mii_if.mdio_read = mdio_read;
1853 cp->mii_if.mdio_write = mdio_write;
1854 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1855 cp->mii_if.phy_id_mask = 0x1f;
1856 cp->mii_if.reg_num_mask = 0x1f;
1857 cp_set_rxbufsize(cp);
1859 rc = pci_enable_device(pdev);
1863 rc = pci_set_mwi(pdev);
1865 goto err_out_disable;
1867 rc = pci_request_regions(pdev, DRV_NAME);
1871 pciaddr = pci_resource_start(pdev, 1);
1874 dev_err(&pdev->dev, "no MMIO resource\n");
1877 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1879 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1880 (unsigned long long)pci_resource_len(pdev, 1));
1884 /* Configure DMA attributes. */
1885 if ((sizeof(dma_addr_t) > 4) &&
1886 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1887 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1892 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1895 "No usable DMA configuration, aborting\n");
1898 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1901 "No usable consistent DMA configuration, aborting\n");
1906 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1907 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1909 dev->features |= NETIF_F_RXCSUM;
1910 dev->hw_features |= NETIF_F_RXCSUM;
1912 regs = ioremap(pciaddr, CP_REGS_SIZE);
1915 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1916 (unsigned long long)pci_resource_len(pdev, 1),
1917 (unsigned long long)pciaddr);
1920 dev->base_addr = (unsigned long) regs;
1925 /* read MAC address from EEPROM */
1926 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1927 for (i = 0; i < 3; i++)
1928 ((__le16 *) (dev->dev_addr))[i] =
1929 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1930 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1932 dev->netdev_ops = &cp_netdev_ops;
1933 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1934 dev->ethtool_ops = &cp_ethtool_ops;
1935 dev->watchdog_timeo = TX_TIMEOUT;
1937 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1940 dev->features |= NETIF_F_HIGHDMA;
1942 /* disabled by default until verified */
1943 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1944 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1945 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
1948 dev->irq = pdev->irq;
1950 rc = register_netdev(dev);
1954 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1955 dev->base_addr, dev->dev_addr, dev->irq);
1957 pci_set_drvdata(pdev, dev);
1959 /* enable busmastering and memory-write-invalidate */
1960 pci_set_master(pdev);
1962 if (cp->wol_enabled)
1963 cp_set_d3_state (cp);
1970 pci_release_regions(pdev);
1972 pci_clear_mwi(pdev);
1974 pci_disable_device(pdev);
1980 static void cp_remove_one (struct pci_dev *pdev)
1982 struct net_device *dev = pci_get_drvdata(pdev);
1983 struct cp_private *cp = netdev_priv(dev);
1985 unregister_netdev(dev);
1987 if (cp->wol_enabled)
1988 pci_set_power_state (pdev, PCI_D0);
1989 pci_release_regions(pdev);
1990 pci_clear_mwi(pdev);
1991 pci_disable_device(pdev);
1992 pci_set_drvdata(pdev, NULL);
1997 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
1999 struct net_device *dev = pci_get_drvdata(pdev);
2000 struct cp_private *cp = netdev_priv(dev);
2001 unsigned long flags;
2003 if (!netif_running(dev))
2006 netif_device_detach (dev);
2007 netif_stop_queue (dev);
2009 spin_lock_irqsave (&cp->lock, flags);
2011 /* Disable Rx and Tx */
2012 cpw16 (IntrMask, 0);
2013 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2015 spin_unlock_irqrestore (&cp->lock, flags);
2017 pci_save_state(pdev);
2018 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2019 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2024 static int cp_resume (struct pci_dev *pdev)
2026 struct net_device *dev = pci_get_drvdata (pdev);
2027 struct cp_private *cp = netdev_priv(dev);
2028 unsigned long flags;
2030 if (!netif_running(dev))
2033 netif_device_attach (dev);
2035 pci_set_power_state(pdev, PCI_D0);
2036 pci_restore_state(pdev);
2037 pci_enable_wake(pdev, PCI_D0, 0);
2039 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2040 cp_init_rings_index (cp);
2043 netif_start_queue (dev);
2045 spin_lock_irqsave (&cp->lock, flags);
2047 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2049 spin_unlock_irqrestore (&cp->lock, flags);
2053 #endif /* CONFIG_PM */
2055 static struct pci_driver cp_driver = {
2057 .id_table = cp_pci_tbl,
2058 .probe = cp_init_one,
2059 .remove = cp_remove_one,
2061 .resume = cp_resume,
2062 .suspend = cp_suspend,
2066 static int __init cp_init (void)
2069 pr_info("%s", version);
2071 return pci_register_driver(&cp_driver);
2074 static void __exit cp_exit (void)
2076 pci_unregister_driver (&cp_driver);
2079 module_init(cp_init);
2080 module_exit(cp_exit);