2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/mlx4/cmd.h>
36 #include <linux/module.h>
37 #include <linux/cache.h>
43 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
44 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
45 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
48 extern void __buggy_use_of_MLX4_GET(void);
49 extern void __buggy_use_of_MLX4_PUT(void);
51 static int enable_qos;
52 module_param(enable_qos, bool, 0444);
53 MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55 #define MLX4_GET(dest, source, offset) \
57 void *__p = (char *) (source) + (offset); \
58 switch (sizeof (dest)) { \
59 case 1: (dest) = *(u8 *) __p; break; \
60 case 2: (dest) = be16_to_cpup(__p); break; \
61 case 4: (dest) = be32_to_cpup(__p); break; \
62 case 8: (dest) = be64_to_cpup(__p); break; \
63 default: __buggy_use_of_MLX4_GET(); \
67 #define MLX4_PUT(dest, source, offset) \
69 void *__d = ((char *) (dest) + (offset)); \
70 switch (sizeof(source)) { \
71 case 1: *(u8 *) __d = (source); break; \
72 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
73 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
74 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
75 default: __buggy_use_of_MLX4_PUT(); \
79 static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
81 static const char *fname[] = {
82 [ 0] = "RC transport",
83 [ 1] = "UC transport",
84 [ 2] = "UD transport",
85 [ 3] = "XRC transport",
86 [ 4] = "reliable multicast",
87 [ 5] = "FCoIB support",
89 [ 7] = "IPoIB checksum offload",
90 [ 8] = "P_Key violation counter",
91 [ 9] = "Q_Key violation counter",
94 [15] = "Big LSO headers",
97 [18] = "Atomic ops support",
98 [19] = "Raw multicast support",
99 [20] = "Address vector port checking support",
100 [21] = "UD multicast support",
101 [24] = "Demand paging support",
102 [25] = "Router support",
103 [30] = "IBoE support",
104 [32] = "Unicast loopback support",
105 [34] = "FCS header control",
106 [38] = "Wake On LAN support",
107 [40] = "UDP RSS support",
108 [41] = "Unicast VEP steering support",
109 [42] = "Multicast VEP steering support",
110 [48] = "Counters support",
114 mlx4_dbg(dev, "DEV_CAP flags:\n");
115 for (i = 0; i < ARRAY_SIZE(fname); ++i)
116 if (fname[i] && (flags & (1LL << i)))
117 mlx4_dbg(dev, " %s\n", fname[i]);
120 int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
122 struct mlx4_cmd_mailbox *mailbox;
126 #define MOD_STAT_CFG_IN_SIZE 0x100
128 #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
129 #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
131 mailbox = mlx4_alloc_cmd_mailbox(dev);
133 return PTR_ERR(mailbox);
134 inbox = mailbox->buf;
136 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
138 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
139 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
141 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
142 MLX4_CMD_TIME_CLASS_A);
144 mlx4_free_cmd_mailbox(dev, mailbox);
148 int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
150 struct mlx4_cmd_mailbox *mailbox;
153 u32 field32, flags, ext_flags;
159 #define QUERY_DEV_CAP_OUT_SIZE 0x100
160 #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
161 #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
162 #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
163 #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
164 #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
165 #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
166 #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
167 #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
168 #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
169 #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
170 #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
171 #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
172 #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
173 #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
174 #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
175 #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
176 #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
177 #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
178 #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
179 #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
180 #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
181 #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
182 #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
183 #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
184 #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
185 #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
186 #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
187 #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
188 #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
189 #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
190 #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
191 #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
192 #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
193 #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
194 #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
195 #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
196 #define QUERY_DEV_CAP_BF_OFFSET 0x4c
197 #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
198 #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
199 #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
200 #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
201 #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
202 #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
203 #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
204 #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
205 #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
206 #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
207 #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
208 #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
209 #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
210 #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
211 #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
212 #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
213 #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
214 #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
215 #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
216 #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
217 #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
218 #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
219 #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
220 #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
221 #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
222 #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
223 #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
224 #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
226 mailbox = mlx4_alloc_cmd_mailbox(dev);
228 return PTR_ERR(mailbox);
229 outbox = mailbox->buf;
231 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
232 MLX4_CMD_TIME_CLASS_A);
236 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
237 dev_cap->reserved_qps = 1 << (field & 0xf);
238 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
239 dev_cap->max_qps = 1 << (field & 0x1f);
240 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
241 dev_cap->reserved_srqs = 1 << (field >> 4);
242 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
243 dev_cap->max_srqs = 1 << (field & 0x1f);
244 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
245 dev_cap->max_cq_sz = 1 << field;
246 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
247 dev_cap->reserved_cqs = 1 << (field & 0xf);
248 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
249 dev_cap->max_cqs = 1 << (field & 0x1f);
250 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
251 dev_cap->max_mpts = 1 << (field & 0x3f);
252 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
253 dev_cap->reserved_eqs = field & 0xf;
254 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
255 dev_cap->max_eqs = 1 << (field & 0xf);
256 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
257 dev_cap->reserved_mtts = 1 << (field >> 4);
258 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
259 dev_cap->max_mrw_sz = 1 << field;
260 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
261 dev_cap->reserved_mrws = 1 << (field & 0xf);
262 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
263 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
264 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
265 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
266 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
267 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
268 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
271 dev_cap->max_gso_sz = 0;
273 dev_cap->max_gso_sz = 1 << field;
275 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
276 dev_cap->max_rdma_global = 1 << (field & 0x3f);
277 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
278 dev_cap->local_ca_ack_delay = field & 0x1f;
279 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
280 dev_cap->num_ports = field & 0xf;
281 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
282 dev_cap->max_msg_sz = 1 << (field & 0x1f);
283 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
284 dev_cap->stat_rate_support = stat_rate;
285 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
286 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
287 dev_cap->flags = flags | (u64)ext_flags << 32;
288 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
289 dev_cap->reserved_uars = field >> 4;
290 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
291 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
292 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
293 dev_cap->min_page_sz = 1 << field;
295 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
297 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
298 dev_cap->bf_reg_size = 1 << (field & 0x1f);
299 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
300 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
302 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
303 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
304 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
306 dev_cap->bf_reg_size = 0;
307 mlx4_dbg(dev, "BlueFlame not available\n");
310 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
311 dev_cap->max_sq_sg = field;
312 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
313 dev_cap->max_sq_desc_sz = size;
315 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
316 dev_cap->max_qp_per_mcg = 1 << field;
317 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
318 dev_cap->reserved_mgms = field & 0xf;
319 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
320 dev_cap->max_mcgs = 1 << field;
321 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
322 dev_cap->reserved_pds = field >> 4;
323 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
324 dev_cap->max_pds = 1 << (field & 0x3f);
325 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
326 dev_cap->reserved_xrcds = field >> 4;
327 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
328 dev_cap->max_xrcds = 1 << (field & 0x1f);
330 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
331 dev_cap->rdmarc_entry_sz = size;
332 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
333 dev_cap->qpc_entry_sz = size;
334 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
335 dev_cap->aux_entry_sz = size;
336 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
337 dev_cap->altc_entry_sz = size;
338 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
339 dev_cap->eqc_entry_sz = size;
340 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
341 dev_cap->cqc_entry_sz = size;
342 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
343 dev_cap->srq_entry_sz = size;
344 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
345 dev_cap->cmpt_entry_sz = size;
346 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
347 dev_cap->mtt_entry_sz = size;
348 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
349 dev_cap->dmpt_entry_sz = size;
351 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
352 dev_cap->max_srq_sz = 1 << field;
353 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
354 dev_cap->max_qp_sz = 1 << field;
355 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
356 dev_cap->resize_srq = field & 1;
357 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
358 dev_cap->max_rq_sg = field;
359 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
360 dev_cap->max_rq_desc_sz = size;
362 MLX4_GET(dev_cap->bmme_flags, outbox,
363 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
364 MLX4_GET(dev_cap->reserved_lkey, outbox,
365 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
366 MLX4_GET(dev_cap->max_icm_sz, outbox,
367 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
368 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
369 MLX4_GET(dev_cap->max_counters, outbox,
370 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
372 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
373 for (i = 1; i <= dev_cap->num_ports; ++i) {
374 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
375 dev_cap->max_vl[i] = field >> 4;
376 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
377 dev_cap->ib_mtu[i] = field >> 4;
378 dev_cap->max_port_width[i] = field & 0xf;
379 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
380 dev_cap->max_gids[i] = 1 << (field & 0xf);
381 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
382 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
385 #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
386 #define QUERY_PORT_MTU_OFFSET 0x01
387 #define QUERY_PORT_ETH_MTU_OFFSET 0x02
388 #define QUERY_PORT_WIDTH_OFFSET 0x06
389 #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
390 #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
391 #define QUERY_PORT_MAX_VL_OFFSET 0x0b
392 #define QUERY_PORT_MAC_OFFSET 0x10
393 #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
394 #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
395 #define QUERY_PORT_TRANS_CODE_OFFSET 0x20
397 for (i = 1; i <= dev_cap->num_ports; ++i) {
398 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
399 MLX4_CMD_TIME_CLASS_B);
403 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
404 dev_cap->supported_port_types[i] = field & 3;
405 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
406 dev_cap->ib_mtu[i] = field & 0xf;
407 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
408 dev_cap->max_port_width[i] = field & 0xf;
409 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
410 dev_cap->max_gids[i] = 1 << (field >> 4);
411 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
412 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
413 dev_cap->max_vl[i] = field & 0xf;
414 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
415 dev_cap->log_max_macs[i] = field & 0xf;
416 dev_cap->log_max_vlans[i] = field >> 4;
417 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
418 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
419 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
420 dev_cap->trans_type[i] = field32 >> 24;
421 dev_cap->vendor_oui[i] = field32 & 0xffffff;
422 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
423 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
427 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
428 dev_cap->bmme_flags, dev_cap->reserved_lkey);
431 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
432 * we can't use any EQs whose doorbell falls on that page,
433 * even if the EQ itself isn't reserved.
435 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
436 dev_cap->reserved_eqs);
438 mlx4_dbg(dev, "Max ICM size %lld MB\n",
439 (unsigned long long) dev_cap->max_icm_sz >> 20);
440 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
441 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
442 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
443 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
444 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
445 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
446 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
447 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
448 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
449 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
450 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
451 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
452 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
453 dev_cap->max_pds, dev_cap->reserved_mgms);
454 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
455 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
456 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
457 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
458 dev_cap->max_port_width[1]);
459 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
460 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
461 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
462 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
463 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
464 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
466 dump_dev_cap_flags(dev, dev_cap->flags);
469 mlx4_free_cmd_mailbox(dev, mailbox);
473 int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
475 struct mlx4_cmd_mailbox *mailbox;
476 struct mlx4_icm_iter iter;
484 mailbox = mlx4_alloc_cmd_mailbox(dev);
486 return PTR_ERR(mailbox);
487 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
488 pages = mailbox->buf;
490 for (mlx4_icm_first(icm, &iter);
491 !mlx4_icm_last(&iter);
492 mlx4_icm_next(&iter)) {
494 * We have to pass pages that are aligned to their
495 * size, so find the least significant 1 in the
496 * address or size and use that as our log2 size.
498 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
499 if (lg < MLX4_ICM_PAGE_SHIFT) {
500 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
502 (unsigned long long) mlx4_icm_addr(&iter),
503 mlx4_icm_size(&iter));
508 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
510 pages[nent * 2] = cpu_to_be64(virt);
514 pages[nent * 2 + 1] =
515 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
516 (lg - MLX4_ICM_PAGE_SHIFT));
517 ts += 1 << (lg - 10);
520 if (++nent == MLX4_MAILBOX_SIZE / 16) {
521 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
522 MLX4_CMD_TIME_CLASS_B);
531 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
536 case MLX4_CMD_MAP_FA:
537 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
539 case MLX4_CMD_MAP_ICM_AUX:
540 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
542 case MLX4_CMD_MAP_ICM:
543 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
544 tc, ts, (unsigned long long) virt - (ts << 10));
549 mlx4_free_cmd_mailbox(dev, mailbox);
553 int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
555 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
558 int mlx4_UNMAP_FA(struct mlx4_dev *dev)
560 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
564 int mlx4_RUN_FW(struct mlx4_dev *dev)
566 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
569 int mlx4_QUERY_FW(struct mlx4_dev *dev)
571 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
572 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
573 struct mlx4_cmd_mailbox *mailbox;
580 #define QUERY_FW_OUT_SIZE 0x100
581 #define QUERY_FW_VER_OFFSET 0x00
582 #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
583 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
584 #define QUERY_FW_ERR_START_OFFSET 0x30
585 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
586 #define QUERY_FW_ERR_BAR_OFFSET 0x3c
588 #define QUERY_FW_SIZE_OFFSET 0x00
589 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
590 #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
592 mailbox = mlx4_alloc_cmd_mailbox(dev);
594 return PTR_ERR(mailbox);
595 outbox = mailbox->buf;
597 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
598 MLX4_CMD_TIME_CLASS_A);
602 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
604 * FW subminor version is at more significant bits than minor
605 * version, so swap here.
607 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
608 ((fw_ver & 0xffff0000ull) >> 16) |
609 ((fw_ver & 0x0000ffffull) << 16);
611 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
612 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
613 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
614 mlx4_err(dev, "Installed FW has unsupported "
615 "command interface revision %d.\n",
617 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
618 (int) (dev->caps.fw_ver >> 32),
619 (int) (dev->caps.fw_ver >> 16) & 0xffff,
620 (int) dev->caps.fw_ver & 0xffff);
621 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
622 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
627 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
628 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
630 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
631 cmd->max_cmds = 1 << lg;
633 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
634 (int) (dev->caps.fw_ver >> 32),
635 (int) (dev->caps.fw_ver >> 16) & 0xffff,
636 (int) dev->caps.fw_ver & 0xffff,
637 cmd_if_rev, cmd->max_cmds);
639 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
640 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
641 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
642 fw->catas_bar = (fw->catas_bar >> 6) * 2;
644 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
645 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
647 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
648 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
649 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
650 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
652 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
655 * Round up number of system pages needed in case
656 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
659 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
660 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
662 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
663 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
666 mlx4_free_cmd_mailbox(dev, mailbox);
670 static void get_board_id(void *vsd, char *board_id)
674 #define VSD_OFFSET_SIG1 0x00
675 #define VSD_OFFSET_SIG2 0xde
676 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
677 #define VSD_OFFSET_TS_BOARD_ID 0x20
679 #define VSD_SIGNATURE_TOPSPIN 0x5ad
681 memset(board_id, 0, MLX4_BOARD_ID_LEN);
683 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
684 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
685 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
688 * The board ID is a string but the firmware byte
689 * swaps each 4-byte word before passing it back to
690 * us. Therefore we need to swab it before printing.
692 for (i = 0; i < 4; ++i)
693 ((u32 *) board_id)[i] =
694 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
698 int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
700 struct mlx4_cmd_mailbox *mailbox;
704 #define QUERY_ADAPTER_OUT_SIZE 0x100
705 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
706 #define QUERY_ADAPTER_VSD_OFFSET 0x20
708 mailbox = mlx4_alloc_cmd_mailbox(dev);
710 return PTR_ERR(mailbox);
711 outbox = mailbox->buf;
713 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
714 MLX4_CMD_TIME_CLASS_A);
718 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
720 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
724 mlx4_free_cmd_mailbox(dev, mailbox);
728 int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
730 struct mlx4_cmd_mailbox *mailbox;
734 #define INIT_HCA_IN_SIZE 0x200
735 #define INIT_HCA_VERSION_OFFSET 0x000
736 #define INIT_HCA_VERSION 2
737 #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
738 #define INIT_HCA_FLAGS_OFFSET 0x014
739 #define INIT_HCA_QPC_OFFSET 0x020
740 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
741 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
742 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
743 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
744 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
745 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
746 #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
747 #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
748 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
749 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
750 #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
751 #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
752 #define INIT_HCA_MCAST_OFFSET 0x0c0
753 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
754 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
755 #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
756 #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
757 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
758 #define INIT_HCA_TPT_OFFSET 0x0f0
759 #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
760 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
761 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
762 #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
763 #define INIT_HCA_UAR_OFFSET 0x120
764 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
765 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
767 mailbox = mlx4_alloc_cmd_mailbox(dev);
769 return PTR_ERR(mailbox);
770 inbox = mailbox->buf;
772 memset(inbox, 0, INIT_HCA_IN_SIZE);
774 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
776 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
777 (ilog2(cache_line_size()) - 4) << 5;
779 #if defined(__LITTLE_ENDIAN)
780 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
781 #elif defined(__BIG_ENDIAN)
782 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
784 #error Host endianness not defined
786 /* Check port for UD address vector: */
787 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
789 /* Enable IPoIB checksumming if we can: */
790 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
791 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
793 /* Enable QoS support if module parameter set */
795 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
797 /* enable counters */
798 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
799 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
801 /* QPC/EEC/CQC/EQC/RDMARC attributes */
803 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
804 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
805 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
806 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
807 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
808 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
809 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
810 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
811 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
812 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
813 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
814 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
816 /* multicast attributes */
818 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
819 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
820 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
821 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
822 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
823 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
827 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
828 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
829 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
830 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
834 MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
835 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
837 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
840 mlx4_err(dev, "INIT_HCA returns %d\n", err);
842 mlx4_free_cmd_mailbox(dev, mailbox);
846 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
848 struct mlx4_cmd_mailbox *mailbox;
854 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
855 #define INIT_PORT_IN_SIZE 256
856 #define INIT_PORT_FLAGS_OFFSET 0x00
857 #define INIT_PORT_FLAG_SIG (1 << 18)
858 #define INIT_PORT_FLAG_NG (1 << 17)
859 #define INIT_PORT_FLAG_G0 (1 << 16)
860 #define INIT_PORT_VL_SHIFT 4
861 #define INIT_PORT_PORT_WIDTH_SHIFT 8
862 #define INIT_PORT_MTU_OFFSET 0x04
863 #define INIT_PORT_MAX_GID_OFFSET 0x06
864 #define INIT_PORT_MAX_PKEY_OFFSET 0x0a
865 #define INIT_PORT_GUID0_OFFSET 0x10
866 #define INIT_PORT_NODE_GUID_OFFSET 0x18
867 #define INIT_PORT_SI_GUID_OFFSET 0x20
869 mailbox = mlx4_alloc_cmd_mailbox(dev);
871 return PTR_ERR(mailbox);
872 inbox = mailbox->buf;
874 memset(inbox, 0, INIT_PORT_IN_SIZE);
877 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
878 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
879 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
881 field = 128 << dev->caps.ib_mtu_cap[port];
882 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
883 field = dev->caps.gid_table_len[port];
884 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
885 field = dev->caps.pkey_table_len[port];
886 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
888 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
889 MLX4_CMD_TIME_CLASS_A);
891 mlx4_free_cmd_mailbox(dev, mailbox);
893 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
894 MLX4_CMD_TIME_CLASS_A);
898 EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
900 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
902 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
904 EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
906 int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
908 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
911 int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
913 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
914 MLX4_CMD_SET_ICM_SIZE,
915 MLX4_CMD_TIME_CLASS_A);
920 * Round up number of system pages needed in case
921 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
923 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
924 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
929 int mlx4_NOP(struct mlx4_dev *dev)
931 /* Input modifier of 0x1f means "finish as soon as possible." */
932 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
935 #define MLX4_WOL_SETUP_MODE (5 << 28)
936 int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
938 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
940 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
941 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A);
943 EXPORT_SYMBOL_GPL(mlx4_wol_read);
945 int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
947 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
949 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
950 MLX4_CMD_TIME_CLASS_A);
952 EXPORT_SYMBOL_GPL(mlx4_wol_write);