drivers/net/ethernet/jme.c

   1 /*
   2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
   3  *
   4  * Copyright 2008 JMicron Technology Corporation
   5  * http://www.jmicron.com/
   6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
   7  *
   8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  *
  23  */
  24
  25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  26
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/mii.h>
  34 #include <linux/crc32.h>
  35 #include <linux/delay.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/in.h>
  38 #include <linux/ip.h>
  39 #include <linux/ipv6.h>
  40 #include <linux/tcp.h>
  41 #include <linux/udp.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/slab.h>
  44 #include <net/ip6_checksum.h>
  45 #include "jme.h"
  46
  47 static int force_pseudohp = -1;
  48 static int no_pseudohp = -1;
  49 static int no_extplug = -1;
  50 module_param(force_pseudohp, int, 0);
  51 MODULE_PARM_DESC(force_pseudohp,
  52         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
  53 module_param(no_pseudohp, int, 0);
  54 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
  55 module_param(no_extplug, int, 0);
  56 MODULE_PARM_DESC(no_extplug,
  57         "Do not use external plug signal for pseudo hot-plug.");
  58
  59 static int
  60 jme_mdio_read(struct net_device *netdev, int phy, int reg)
  61 {
  62         struct jme_adapter *jme = netdev_priv(netdev);
  63         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
  64
  65 read_again:
  66         jwrite32(jme, JME_SMI, SMI_OP_REQ |
  67                                 smi_phy_addr(phy) |
  68                                 smi_reg_addr(reg));
  69
  70         wmb();
  71         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
  72                 udelay(20);
  73                 val = jread32(jme, JME_SMI);
  74                 if ((val & SMI_OP_REQ) == 0)
  75                         break;
  76         }
  77
  78         if (i == 0) {
  79                 pr_err("phy(%d) read timeout : %d\n", phy, reg);
  80                 return 0;
  81         }
  82
  83         if (again--)
  84                 goto read_again;
  85
  86         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
  87 }
  88
  89 static void
  90 jme_mdio_write(struct net_device *netdev,
  91                                 int phy, int reg, int val)
  92 {
  93         struct jme_adapter *jme = netdev_priv(netdev);
  94         int i;
  95
  96         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
  97                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
  98                 smi_phy_addr(phy) | smi_reg_addr(reg));
  99
 100         wmb();
 101         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
 102                 udelay(20);
 103                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
 104                         break;
 105         }
 106
 107         if (i == 0)
 108                 pr_err("phy(%d) write timeout : %d\n", phy, reg);
 109 }
 110
 111 static inline void
 112 jme_reset_phy_processor(struct jme_adapter *jme)
 113 {
 114         u32 val;
 115
 116         jme_mdio_write(jme->dev,
 117                         jme->mii_if.phy_id,
 118                         MII_ADVERTISE, ADVERTISE_ALL |
 119                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
 120
 121         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
 122                 jme_mdio_write(jme->dev,
 123                                 jme->mii_if.phy_id,
 124                                 MII_CTRL1000,
 125                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 126
 127         val = jme_mdio_read(jme->dev,
 128                                 jme->mii_if.phy_id,
 129                                 MII_BMCR);
 130
 131         jme_mdio_write(jme->dev,
 132                         jme->mii_if.phy_id,
 133                         MII_BMCR, val | BMCR_RESET);
 134 }
 135
 136 static void
 137 jme_setup_wakeup_frame(struct jme_adapter *jme,
 138                        const u32 *mask, u32 crc, int fnr)
 139 {
 140         int i;
 141
 142         /*
 143          * Setup CRC pattern
 144          */
 145         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
 146         wmb();
 147         jwrite32(jme, JME_WFODP, crc);
 148         wmb();
 149
 150         /*
 151          * Setup Mask
 152          */
 153         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
 154                 jwrite32(jme, JME_WFOI,
 155                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
 156                                 (fnr & WFOI_FRAME_SEL));
 157                 wmb();
 158                 jwrite32(jme, JME_WFODP, mask[i]);
 159                 wmb();
 160         }
 161 }
 162
 163 static inline void
 164 jme_mac_rxclk_off(struct jme_adapter *jme)
 165 {
 166         jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
 167         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
 168 }
 169
 170 static inline void
 171 jme_mac_rxclk_on(struct jme_adapter *jme)
 172 {
 173         jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
 174         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
 175 }
 176
 177 static inline void
 178 jme_mac_txclk_off(struct jme_adapter *jme)
 179 {
 180         jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
 181         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 182 }
 183
 184 static inline void
 185 jme_mac_txclk_on(struct jme_adapter *jme)
 186 {
 187         u32 speed = jme->reg_ghc & GHC_SPEED;
 188         if (speed == GHC_SPEED_1000M)
 189                 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
 190         else
 191                 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
 192         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 193 }
 194
 195 static inline void
 196 jme_reset_ghc_speed(struct jme_adapter *jme)
 197 {
 198         jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
 199         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 200 }
 201
 202 static inline void
 203 jme_reset_250A2_workaround(struct jme_adapter *jme)
 204 {
 205         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
 206                              GPREG1_RSSPATCH);
 207         jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
 208 }
 209
 210 static inline void
 211 jme_assert_ghc_reset(struct jme_adapter *jme)
 212 {
 213         jme->reg_ghc |= GHC_SWRST;
 214         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 215 }
 216
 217 static inline void
 218 jme_clear_ghc_reset(struct jme_adapter *jme)
 219 {
 220         jme->reg_ghc &= ~GHC_SWRST;
 221         jwrite32f(jme, JME_GHC, jme->reg_ghc);
 222 }
 223
 224 static inline void
 225 jme_reset_mac_processor(struct jme_adapter *jme)
 226 {
 227         static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
 228         u32 crc = 0xCDCDCDCD;
 229         u32 gpreg0;
 230         int i;
 231
 232         jme_reset_ghc_speed(jme);
 233         jme_reset_250A2_workaround(jme);
 234
 235         jme_mac_rxclk_on(jme);
 236         jme_mac_txclk_on(jme);
 237         udelay(1);
 238         jme_assert_ghc_reset(jme);
 239         udelay(1);
 240         jme_mac_rxclk_off(jme);
 241         jme_mac_txclk_off(jme);
 242         udelay(1);
 243         jme_clear_ghc_reset(jme);
 244         udelay(1);
 245         jme_mac_rxclk_on(jme);
 246         jme_mac_txclk_on(jme);
 247         udelay(1);
 248         jme_mac_rxclk_off(jme);
 249         jme_mac_txclk_off(jme);
 250
 251         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
 252         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
 253         jwrite32(jme, JME_RXQDC, 0x00000000);
 254         jwrite32(jme, JME_RXNDA, 0x00000000);
 255         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
 256         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
 257         jwrite32(jme, JME_TXQDC, 0x00000000);
 258         jwrite32(jme, JME_TXNDA, 0x00000000);
 259
 260         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
 261         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
 262         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
 263                 jme_setup_wakeup_frame(jme, mask, crc, i);
 264         if (jme->fpgaver)
 265                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
 266         else
 267                 gpreg0 = GPREG0_DEFAULT;
 268         jwrite32(jme, JME_GPREG0, gpreg0);
 269 }
 270
 271 static inline void
 272 jme_clear_pm_enable_wol(struct jme_adapter *jme)
 273 {
 274         jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
 275 }
 276
 277 static inline void
 278 jme_clear_pm_disable_wol(struct jme_adapter *jme)
 279 {
 280         jwrite32(jme, JME_PMCS, PMCS_STMASK);
 281 }
 282
 283 static int
 284 jme_reload_eeprom(struct jme_adapter *jme)
 285 {
 286         u32 val;
 287         int i;
 288
 289         val = jread32(jme, JME_SMBCSR);
 290
 291         if (val & SMBCSR_EEPROMD) {
 292                 val |= SMBCSR_CNACK;
 293                 jwrite32(jme, JME_SMBCSR, val);
 294                 val |= SMBCSR_RELOAD;
 295                 jwrite32(jme, JME_SMBCSR, val);
 296                 mdelay(12);
 297
 298                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
 299                         mdelay(1);
 300                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
 301                                 break;
 302                 }
 303
 304                 if (i == 0) {
 305                         pr_err("eeprom reload timeout\n");
 306                         return -EIO;
 307                 }
 308         }
 309
 310         return 0;
 311 }
 312
 313 static void
 314 jme_load_macaddr(struct net_device *netdev)
 315 {
 316         struct jme_adapter *jme = netdev_priv(netdev);
 317         unsigned char macaddr[6];
 318         u32 val;
 319
 320         spin_lock_bh(&jme->macaddr_lock);
 321         val = jread32(jme, JME_RXUMA_LO);
 322         macaddr[0] = (val >>  0) & 0xFF;
 323         macaddr[1] = (val >>  8) & 0xFF;
 324         macaddr[2] = (val >> 16) & 0xFF;
 325         macaddr[3] = (val >> 24) & 0xFF;
 326         val = jread32(jme, JME_RXUMA_HI);
 327         macaddr[4] = (val >>  0) & 0xFF;
 328         macaddr[5] = (val >>  8) & 0xFF;
 329         memcpy(netdev->dev_addr, macaddr, 6);
 330         spin_unlock_bh(&jme->macaddr_lock);
 331 }
 332
 333 static inline void
 334 jme_set_rx_pcc(struct jme_adapter *jme, int p)
 335 {
 336         switch (p) {
 337         case PCC_OFF:
 338                 jwrite32(jme, JME_PCCRX0,
 339                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 340                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 341                 break;
 342         case PCC_P1:
 343                 jwrite32(jme, JME_PCCRX0,
 344                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 345                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 346                 break;
 347         case PCC_P2:
 348                 jwrite32(jme, JME_PCCRX0,
 349                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 350                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 351                 break;
 352         case PCC_P3:
 353                 jwrite32(jme, JME_PCCRX0,
 354                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
 355                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
 356                 break;
 357         default:
 358                 break;
 359         }
 360         wmb();
 361
 362         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
 363                 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
 364 }
 365
 366 static void
 367 jme_start_irq(struct jme_adapter *jme)
 368 {
 369         register struct dynpcc_info *dpi = &(jme->dpi);
 370
 371         jme_set_rx_pcc(jme, PCC_P1);
 372         dpi->cur                = PCC_P1;
 373         dpi->attempt            = PCC_P1;
 374         dpi->cnt                = 0;
 375
 376         jwrite32(jme, JME_PCCTX,
 377                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
 378                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
 379                         PCCTXQ0_EN
 380                 );
 381
 382         /*
 383          * Enable Interrupts
 384          */
 385         jwrite32(jme, JME_IENS, INTR_ENABLE);
 386 }
 387
 388 static inline void
 389 jme_stop_irq(struct jme_adapter *jme)
 390 {
 391         /*
 392          * Disable Interrupts
 393          */
 394         jwrite32f(jme, JME_IENC, INTR_ENABLE);
 395 }
 396
 397 static u32
 398 jme_linkstat_from_phy(struct jme_adapter *jme)
 399 {
 400         u32 phylink, bmsr;
 401
 402         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
 403         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
 404         if (bmsr & BMSR_ANCOMP)
 405                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
 406
 407         return phylink;
 408 }
 409
 410 static inline void
 411 jme_set_phyfifo_5level(struct jme_adapter *jme)
 412 {
 413         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
 414 }
 415
 416 static inline void
 417 jme_set_phyfifo_8level(struct jme_adapter *jme)
 418 {
 419         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
 420 }
 421
 422 static int
 423 jme_check_link(struct net_device *netdev, int testonly)
 424 {
 425         struct jme_adapter *jme = netdev_priv(netdev);
 426         u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
 427         char linkmsg[64];
 428         int rc = 0;
 429
 430         linkmsg[0] = '\0';
 431
 432         if (jme->fpgaver)
 433                 phylink = jme_linkstat_from_phy(jme);
 434         else
 435                 phylink = jread32(jme, JME_PHY_LINK);
 436
 437         if (phylink & PHY_LINK_UP) {
 438                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
 439                         /*
 440                          * If we did not enable AN
 441                          * Speed/Duplex Info should be obtained from SMI
 442                          */
 443                         phylink = PHY_LINK_UP;
 444
 445                         bmcr = jme_mdio_read(jme->dev,
 446                                                 jme->mii_if.phy_id,
 447                                                 MII_BMCR);
 448
 449                         phylink |= ((bmcr & BMCR_SPEED1000) &&
 450                                         (bmcr & BMCR_SPEED100) == 0) ?
 451                                         PHY_LINK_SPEED_1000M :
 452                                         (bmcr & BMCR_SPEED100) ?
 453                                         PHY_LINK_SPEED_100M :
 454                                         PHY_LINK_SPEED_10M;
 455
 456                         phylink |= (bmcr & BMCR_FULLDPLX) ?
 457                                          PHY_LINK_DUPLEX : 0;
 458
 459                         strcat(linkmsg, "Forced: ");
 460                 } else {
 461                         /*
 462                          * Keep polling for speed/duplex resolve complete
 463                          */
 464                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
 465                                 --cnt) {
 466
 467                                 udelay(1);
 468
 469                                 if (jme->fpgaver)
 470                                         phylink = jme_linkstat_from_phy(jme);
 471                                 else
 472                                         phylink = jread32(jme, JME_PHY_LINK);
 473                         }
 474                         if (!cnt)
 475                                 pr_err("Waiting speed resolve timeout\n");
 476
 477                         strcat(linkmsg, "ANed: ");
 478                 }
 479
 480                 if (jme->phylink == phylink) {
 481                         rc = 1;
 482                         goto out;
 483                 }
 484                 if (testonly)
 485                         goto out;
 486
 487                 jme->phylink = phylink;
 488
 489                 /*
 490                  * The speed/duplex setting of jme->reg_ghc already cleared
 491                  * by jme_reset_mac_processor()
 492                  */
 493                 switch (phylink & PHY_LINK_SPEED_MASK) {
 494                 case PHY_LINK_SPEED_10M:
 495                         jme->reg_ghc |= GHC_SPEED_10M;
 496                         strcat(linkmsg, "10 Mbps, ");
 497                         break;
 498                 case PHY_LINK_SPEED_100M:
 499                         jme->reg_ghc |= GHC_SPEED_100M;
 500                         strcat(linkmsg, "100 Mbps, ");
 501                         break;
 502                 case PHY_LINK_SPEED_1000M:
 503                         jme->reg_ghc |= GHC_SPEED_1000M;
 504                         strcat(linkmsg, "1000 Mbps, ");
 505                         break;
 506                 default:
 507                         break;
 508                 }
 509
 510                 if (phylink & PHY_LINK_DUPLEX) {
 511                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
 512                         jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
 513                         jme->reg_ghc |= GHC_DPX;
 514                 } else {
 515                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
 516                                                 TXMCS_BACKOFF |
 517                                                 TXMCS_CARRIERSENSE |
 518                                                 TXMCS_COLLISION);
 519                         jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
 520                 }
 521
 522                 jwrite32(jme, JME_GHC, jme->reg_ghc);
 523
 524                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
 525                         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
 526                                              GPREG1_RSSPATCH);
 527                         if (!(phylink & PHY_LINK_DUPLEX))
 528                                 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
 529                         switch (phylink & PHY_LINK_SPEED_MASK) {
 530                         case PHY_LINK_SPEED_10M:
 531                                 jme_set_phyfifo_8level(jme);
 532                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
 533                                 break;
 534                         case PHY_LINK_SPEED_100M:
 535                                 jme_set_phyfifo_5level(jme);
 536                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
 537                                 break;
 538                         case PHY_LINK_SPEED_1000M:
 539                                 jme_set_phyfifo_8level(jme);
 540                                 break;
 541                         default:
 542                                 break;
 543                         }
 544                 }
 545                 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
 546
 547                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
 548                                         "Full-Duplex, " :
 549                                         "Half-Duplex, ");
 550                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
 551                                         "MDI-X" :
 552                                         "MDI");
 553                 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
 554                 netif_carrier_on(netdev);
 555         } else {
 556                 if (testonly)
 557                         goto out;
 558
 559                 netif_info(jme, link, jme->dev, "Link is down\n");
 560                 jme->phylink = 0;
 561                 netif_carrier_off(netdev);
 562         }
 563
 564 out:
 565         return rc;
 566 }
 567
 568 static int
 569 jme_setup_tx_resources(struct jme_adapter *jme)
 570 {
 571         struct jme_ring *txring = &(jme->txring[0]);
 572
 573         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 574                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 575                                    &(txring->dmaalloc),
 576                                    GFP_ATOMIC);
 577
 578         if (!txring->alloc)
 579                 goto err_set_null;
 580
 581         /*
 582          * 16 Bytes align
 583          */
 584         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
 585                                                 RING_DESC_ALIGN);
 586         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
 587         txring->next_to_use     = 0;
 588         atomic_set(&txring->next_to_clean, 0);
 589         atomic_set(&txring->nr_free, jme->tx_ring_size);
 590
 591         txring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
 592                                         jme->tx_ring_size, GFP_ATOMIC);
 593         if (unlikely(!(txring->bufinf)))
 594                 goto err_free_txring;
 595
 596         /*
 597          * Initialize Transmit Descriptors
 598          */
 599         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
 600         memset(txring->bufinf, 0,
 601                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
 602
 603         return 0;
 604
 605 err_free_txring:
 606         dma_free_coherent(&(jme->pdev->dev),
 607                           TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 608                           txring->alloc,
 609                           txring->dmaalloc);
 610
 611 err_set_null:
 612         txring->desc = NULL;
 613         txring->dmaalloc = 0;
 614         txring->dma = 0;
 615         txring->bufinf = NULL;
 616
 617         return -ENOMEM;
 618 }
 619
 620 static void
 621 jme_free_tx_resources(struct jme_adapter *jme)
 622 {
 623         int i;
 624         struct jme_ring *txring = &(jme->txring[0]);
 625         struct jme_buffer_info *txbi;
 626
 627         if (txring->alloc) {
 628                 if (txring->bufinf) {
 629                         for (i = 0 ; i < jme->tx_ring_size ; ++i) {
 630                                 txbi = txring->bufinf + i;
 631                                 if (txbi->skb) {
 632                                         dev_kfree_skb(txbi->skb);
 633                                         txbi->skb = NULL;
 634                                 }
 635                                 txbi->mapping           = 0;
 636                                 txbi->len               = 0;
 637                                 txbi->nr_desc           = 0;
 638                                 txbi->start_xmit        = 0;
 639                         }
 640                         kfree(txring->bufinf);
 641                 }
 642
 643                 dma_free_coherent(&(jme->pdev->dev),
 644                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
 645                                   txring->alloc,
 646                                   txring->dmaalloc);
 647
 648                 txring->alloc           = NULL;
 649                 txring->desc            = NULL;
 650                 txring->dmaalloc        = 0;
 651                 txring->dma             = 0;
 652                 txring->bufinf          = NULL;
 653         }
 654         txring->next_to_use     = 0;
 655         atomic_set(&txring->next_to_clean, 0);
 656         atomic_set(&txring->nr_free, 0);
 657 }
 658
 659 static inline void
 660 jme_enable_tx_engine(struct jme_adapter *jme)
 661 {
 662         /*
 663          * Select Queue 0
 664          */
 665         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
 666         wmb();
 667
 668         /*
 669          * Setup TX Queue 0 DMA Bass Address
 670          */
 671         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 672         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
 673         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
 674
 675         /*
 676          * Setup TX Descptor Count
 677          */
 678         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
 679
 680         /*
 681          * Enable TX Engine
 682          */
 683         wmb();
 684         jwrite32f(jme, JME_TXCS, jme->reg_txcs |
 685                                 TXCS_SELECT_QUEUE0 |
 686                                 TXCS_ENABLE);
 687
 688         /*
 689          * Start clock for TX MAC Processor
 690          */
 691         jme_mac_txclk_on(jme);
 692 }
 693
 694 static inline void
 695 jme_restart_tx_engine(struct jme_adapter *jme)
 696 {
 697         /*
 698          * Restart TX Engine
 699          */
 700         jwrite32(jme, JME_TXCS, jme->reg_txcs |
 701                                 TXCS_SELECT_QUEUE0 |
 702                                 TXCS_ENABLE);
 703 }
 704
 705 static inline void
 706 jme_disable_tx_engine(struct jme_adapter *jme)
 707 {
 708         int i;
 709         u32 val;
 710
 711         /*
 712          * Disable TX Engine
 713          */
 714         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
 715         wmb();
 716
 717         val = jread32(jme, JME_TXCS);
 718         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
 719                 mdelay(1);
 720                 val = jread32(jme, JME_TXCS);
 721                 rmb();
 722         }
 723
 724         if (!i)
 725                 pr_err("Disable TX engine timeout\n");
 726
 727         /*
 728          * Stop clock for TX MAC Processor
 729          */
 730         jme_mac_txclk_off(jme);
 731 }
 732
 733 static void
 734 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
 735 {
 736         struct jme_ring *rxring = &(jme->rxring[0]);
 737         register struct rxdesc *rxdesc = rxring->desc;
 738         struct jme_buffer_info *rxbi = rxring->bufinf;
 739         rxdesc += i;
 740         rxbi += i;
 741
 742         rxdesc->dw[0] = 0;
 743         rxdesc->dw[1] = 0;
 744         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
 745         rxdesc->desc1.bufaddrl  = cpu_to_le32(
 746                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
 747         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
 748         if (jme->dev->features & NETIF_F_HIGHDMA)
 749                 rxdesc->desc1.flags = RXFLAG_64BIT;
 750         wmb();
 751         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
 752 }
 753
 754 static int
 755 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
 756 {
 757         struct jme_ring *rxring = &(jme->rxring[0]);
 758         struct jme_buffer_info *rxbi = rxring->bufinf + i;
 759         struct sk_buff *skb;
 760         dma_addr_t mapping;
 761
 762         skb = netdev_alloc_skb(jme->dev,
 763                 jme->dev->mtu + RX_EXTRA_LEN);
 764         if (unlikely(!skb))
 765                 return -ENOMEM;
 766
 767         mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
 768                                offset_in_page(skb->data), skb_tailroom(skb),
 769                                PCI_DMA_FROMDEVICE);
 770         if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
 771                 dev_kfree_skb(skb);
 772                 return -ENOMEM;
 773         }
 774
 775         if (likely(rxbi->mapping))
 776                 pci_unmap_page(jme->pdev, rxbi->mapping,
 777                                rxbi->len, PCI_DMA_FROMDEVICE);
 778
 779         rxbi->skb = skb;
 780         rxbi->len = skb_tailroom(skb);
 781         rxbi->mapping = mapping;
 782         return 0;
 783 }
 784
 785 static void
 786 jme_free_rx_buf(struct jme_adapter *jme, int i)
 787 {
 788         struct jme_ring *rxring = &(jme->rxring[0]);
 789         struct jme_buffer_info *rxbi = rxring->bufinf;
 790         rxbi += i;
 791
 792         if (rxbi->skb) {
 793                 pci_unmap_page(jme->pdev,
 794                                  rxbi->mapping,
 795                                  rxbi->len,
 796                                  PCI_DMA_FROMDEVICE);
 797                 dev_kfree_skb(rxbi->skb);
 798                 rxbi->skb = NULL;
 799                 rxbi->mapping = 0;
 800                 rxbi->len = 0;
 801         }
 802 }
 803
 804 static void
 805 jme_free_rx_resources(struct jme_adapter *jme)
 806 {
 807         int i;
 808         struct jme_ring *rxring = &(jme->rxring[0]);
 809
 810         if (rxring->alloc) {
 811                 if (rxring->bufinf) {
 812                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
 813                                 jme_free_rx_buf(jme, i);
 814                         kfree(rxring->bufinf);
 815                 }
 816
 817                 dma_free_coherent(&(jme->pdev->dev),
 818                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 819                                   rxring->alloc,
 820                                   rxring->dmaalloc);
 821                 rxring->alloc    = NULL;
 822                 rxring->desc     = NULL;
 823                 rxring->dmaalloc = 0;
 824                 rxring->dma      = 0;
 825                 rxring->bufinf   = NULL;
 826         }
 827         rxring->next_to_use   = 0;
 828         atomic_set(&rxring->next_to_clean, 0);
 829 }
 830
 831 static int
 832 jme_setup_rx_resources(struct jme_adapter *jme)
 833 {
 834         int i;
 835         struct jme_ring *rxring = &(jme->rxring[0]);
 836
 837         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
 838                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 839                                    &(rxring->dmaalloc),
 840                                    GFP_ATOMIC);
 841         if (!rxring->alloc)
 842                 goto err_set_null;
 843
 844         /*
 845          * 16 Bytes align
 846          */
 847         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
 848                                                 RING_DESC_ALIGN);
 849         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
 850         rxring->next_to_use     = 0;
 851         atomic_set(&rxring->next_to_clean, 0);
 852
 853         rxring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
 854                                         jme->rx_ring_size, GFP_ATOMIC);
 855         if (unlikely(!(rxring->bufinf)))
 856                 goto err_free_rxring;
 857
 858         /*
 859          * Initiallize Receive Descriptors
 860          */
 861         memset(rxring->bufinf, 0,
 862                 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
 863         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
 864                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
 865                         jme_free_rx_resources(jme);
 866                         return -ENOMEM;
 867                 }
 868
 869                 jme_set_clean_rxdesc(jme, i);
 870         }
 871
 872         return 0;
 873
 874 err_free_rxring:
 875         dma_free_coherent(&(jme->pdev->dev),
 876                           RX_RING_ALLOC_SIZE(jme->rx_ring_size),
 877                           rxring->alloc,
 878                           rxring->dmaalloc);
 879 err_set_null:
 880         rxring->desc = NULL;
 881         rxring->dmaalloc = 0;
 882         rxring->dma = 0;
 883         rxring->bufinf = NULL;
 884
 885         return -ENOMEM;
 886 }
 887
 888 static inline void
 889 jme_enable_rx_engine(struct jme_adapter *jme)
 890 {
 891         /*
 892          * Select Queue 0
 893          */
 894         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 895                                 RXCS_QUEUESEL_Q0);
 896         wmb();
 897
 898         /*
 899          * Setup RX DMA Bass Address
 900          */
 901         jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
 902         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
 903         jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
 904
 905         /*
 906          * Setup RX Descriptor Count
 907          */
 908         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
 909
 910         /*
 911          * Setup Unicast Filter
 912          */
 913         jme_set_unicastaddr(jme->dev);
 914         jme_set_multi(jme->dev);
 915
 916         /*
 917          * Enable RX Engine
 918          */
 919         wmb();
 920         jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
 921                                 RXCS_QUEUESEL_Q0 |
 922                                 RXCS_ENABLE |
 923                                 RXCS_QST);
 924
 925         /*
 926          * Start clock for RX MAC Processor
 927          */
 928         jme_mac_rxclk_on(jme);
 929 }
 930
 931 static inline void
 932 jme_restart_rx_engine(struct jme_adapter *jme)
 933 {
 934         /*
 935          * Start RX Engine
 936          */
 937         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
 938                                 RXCS_QUEUESEL_Q0 |
 939                                 RXCS_ENABLE |
 940                                 RXCS_QST);
 941 }
 942
 943 static inline void
 944 jme_disable_rx_engine(struct jme_adapter *jme)
 945 {
 946         int i;
 947         u32 val;
 948
 949         /*
 950          * Disable RX Engine
 951          */
 952         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
 953         wmb();
 954
 955         val = jread32(jme, JME_RXCS);
 956         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
 957                 mdelay(1);
 958                 val = jread32(jme, JME_RXCS);
 959                 rmb();
 960         }
 961
 962         if (!i)
 963                 pr_err("Disable RX engine timeout\n");
 964
 965         /*
 966          * Stop clock for RX MAC Processor
 967          */
 968         jme_mac_rxclk_off(jme);
 969 }
 970
 971 static u16
 972 jme_udpsum(struct sk_buff *skb)
 973 {
 974         u16 csum = 0xFFFFu;
 975
 976         if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
 977                 return csum;
 978         if (skb->protocol != htons(ETH_P_IP))
 979                 return csum;
 980         skb_set_network_header(skb, ETH_HLEN);
 981         if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
 982             (skb->len < (ETH_HLEN +
 983                         (ip_hdr(skb)->ihl << 2) +
 984                         sizeof(struct udphdr)))) {
 985                 skb_reset_network_header(skb);
 986                 return csum;
 987         }
 988         skb_set_transport_header(skb,
 989                         ETH_HLEN + (ip_hdr(skb)->ihl << 2));
 990         csum = udp_hdr(skb)->check;
 991         skb_reset_transport_header(skb);
 992         skb_reset_network_header(skb);
 993
 994         return csum;
 995 }
 996
 997 static int
 998 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
 999 {
1000         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1001                 return false;
1002
1003         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1004                         == RXWBFLAG_TCPON)) {
1005                 if (flags & RXWBFLAG_IPV4)
1006                         netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1007                 return false;
1008         }
1009
1010         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1011                         == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1012                 if (flags & RXWBFLAG_IPV4)
1013                         netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1014                 return false;
1015         }
1016
1017         if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1018                         == RXWBFLAG_IPV4)) {
1019                 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1020                 return false;
1021         }
1022
1023         return true;
1024 }
1025
1026 static void
1027 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1028 {
1029         struct jme_ring *rxring = &(jme->rxring[0]);
1030         struct rxdesc *rxdesc = rxring->desc;
1031         struct jme_buffer_info *rxbi = rxring->bufinf;
1032         struct sk_buff *skb;
1033         int framesize;
1034
1035         rxdesc += idx;
1036         rxbi += idx;
1037
1038         skb = rxbi->skb;
1039         pci_dma_sync_single_for_cpu(jme->pdev,
1040                                         rxbi->mapping,
1041                                         rxbi->len,
1042                                         PCI_DMA_FROMDEVICE);
1043
1044         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1045                 pci_dma_sync_single_for_device(jme->pdev,
1046                                                 rxbi->mapping,
1047                                                 rxbi->len,
1048                                                 PCI_DMA_FROMDEVICE);
1049
1050                 ++(NET_STAT(jme).rx_dropped);
1051         } else {
1052                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1053                                 - RX_PREPAD_SIZE;
1054
1055                 skb_reserve(skb, RX_PREPAD_SIZE);
1056                 skb_put(skb, framesize);
1057                 skb->protocol = eth_type_trans(skb, jme->dev);
1058
1059                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1060                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1061                 else
1062                         skb_checksum_none_assert(skb);
1063
1064                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1065                         u16 vid = le16_to_cpu(rxdesc->descwb.vlan);
1066
1067                         __vlan_hwaccel_put_tag(skb, vid);
1068                         NET_STAT(jme).rx_bytes += 4;
1069                 }
1070                 jme->jme_rx(skb);
1071
1072                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1073                     cpu_to_le16(RXWBFLAG_DEST_MUL))
1074                         ++(NET_STAT(jme).multicast);
1075
1076                 NET_STAT(jme).rx_bytes += framesize;
1077                 ++(NET_STAT(jme).rx_packets);
1078         }
1079
1080         jme_set_clean_rxdesc(jme, idx);
1081
1082 }
1083
1084 static int
1085 jme_process_receive(struct jme_adapter *jme, int limit)
1086 {
1087         struct jme_ring *rxring = &(jme->rxring[0]);
1088         struct rxdesc *rxdesc = rxring->desc;
1089         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1090
1091         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1092                 goto out_inc;
1093
1094         if (unlikely(atomic_read(&jme->link_changing) != 1))
1095                 goto out_inc;
1096
1097         if (unlikely(!netif_carrier_ok(jme->dev)))
1098                 goto out_inc;
1099
1100         i = atomic_read(&rxring->next_to_clean);
1101         while (limit > 0) {
1102                 rxdesc = rxring->desc;
1103                 rxdesc += i;
1104
1105                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1106                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1107                         goto out;
1108                 --limit;
1109
1110                 rmb();
1111                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1112
1113                 if (unlikely(desccnt > 1 ||
1114                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1115
1116                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1117                                 ++(NET_STAT(jme).rx_crc_errors);
1118                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1119                                 ++(NET_STAT(jme).rx_fifo_errors);
1120                         else
1121                                 ++(NET_STAT(jme).rx_errors);
1122
1123                         if (desccnt > 1)
1124                                 limit -= desccnt - 1;
1125
1126                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1127                                 jme_set_clean_rxdesc(jme, j);
1128                                 j = (j + 1) & (mask);
1129                         }
1130
1131                 } else {
1132                         jme_alloc_and_feed_skb(jme, i);
1133                 }
1134
1135                 i = (i + desccnt) & (mask);
1136         }
1137
1138 out:
1139         atomic_set(&rxring->next_to_clean, i);
1140
1141 out_inc:
1142         atomic_inc(&jme->rx_cleaning);
1143
1144         return limit > 0 ? limit : 0;
1145
1146 }
1147
1148 static void
1149 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1150 {
1151         if (likely(atmp == dpi->cur)) {
1152                 dpi->cnt = 0;
1153                 return;
1154         }
1155
1156         if (dpi->attempt == atmp) {
1157                 ++(dpi->cnt);
1158         } else {
1159                 dpi->attempt = atmp;
1160                 dpi->cnt = 0;
1161         }
1162
1163 }
1164
1165 static void
1166 jme_dynamic_pcc(struct jme_adapter *jme)
1167 {
1168         register struct dynpcc_info *dpi = &(jme->dpi);
1169
1170         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1171                 jme_attempt_pcc(dpi, PCC_P3);
1172         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1173                  dpi->intr_cnt > PCC_INTR_THRESHOLD)
1174                 jme_attempt_pcc(dpi, PCC_P2);
1175         else
1176                 jme_attempt_pcc(dpi, PCC_P1);
1177
1178         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1179                 if (dpi->attempt < dpi->cur)
1180                         tasklet_schedule(&jme->rxclean_task);
1181                 jme_set_rx_pcc(jme, dpi->attempt);
1182                 dpi->cur = dpi->attempt;
1183                 dpi->cnt = 0;
1184         }
1185 }
1186
1187 static void
1188 jme_start_pcc_timer(struct jme_adapter *jme)
1189 {
1190         struct dynpcc_info *dpi = &(jme->dpi);
1191         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1192         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1193         dpi->intr_cnt           = 0;
1194         jwrite32(jme, JME_TMCSR,
1195                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1196 }
1197
1198 static inline void
1199 jme_stop_pcc_timer(struct jme_adapter *jme)
1200 {
1201         jwrite32(jme, JME_TMCSR, 0);
1202 }
1203
1204 static void
1205 jme_shutdown_nic(struct jme_adapter *jme)
1206 {
1207         u32 phylink;
1208
1209         phylink = jme_linkstat_from_phy(jme);
1210
1211         if (!(phylink & PHY_LINK_UP)) {
1212                 /*
1213                  * Disable all interrupt before issue timer
1214                  */
1215                 jme_stop_irq(jme);
1216                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1217         }
1218 }
1219
1220 static void
1221 jme_pcc_tasklet(unsigned long arg)
1222 {
1223         struct jme_adapter *jme = (struct jme_adapter *)arg;
1224         struct net_device *netdev = jme->dev;
1225
1226         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1227                 jme_shutdown_nic(jme);
1228                 return;
1229         }
1230
1231         if (unlikely(!netif_carrier_ok(netdev) ||
1232                 (atomic_read(&jme->link_changing) != 1)
1233         )) {
1234                 jme_stop_pcc_timer(jme);
1235                 return;
1236         }
1237
1238         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1239                 jme_dynamic_pcc(jme);
1240
1241         jme_start_pcc_timer(jme);
1242 }
1243
1244 static inline void
1245 jme_polling_mode(struct jme_adapter *jme)
1246 {
1247         jme_set_rx_pcc(jme, PCC_OFF);
1248 }
1249
1250 static inline void
1251 jme_interrupt_mode(struct jme_adapter *jme)
1252 {
1253         jme_set_rx_pcc(jme, PCC_P1);
1254 }
1255
1256 static inline int
1257 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1258 {
1259         u32 apmc;
1260         apmc = jread32(jme, JME_APMC);
1261         return apmc & JME_APMC_PSEUDO_HP_EN;
1262 }
1263
1264 static void
1265 jme_start_shutdown_timer(struct jme_adapter *jme)
1266 {
1267         u32 apmc;
1268
1269         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1270         apmc &= ~JME_APMC_EPIEN_CTRL;
1271         if (!no_extplug) {
1272                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1273                 wmb();
1274         }
1275         jwrite32f(jme, JME_APMC, apmc);
1276
1277         jwrite32f(jme, JME_TIMER2, 0);
1278         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1279         jwrite32(jme, JME_TMCSR,
1280                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1281 }
1282
1283 static void
1284 jme_stop_shutdown_timer(struct jme_adapter *jme)
1285 {
1286         u32 apmc;
1287
1288         jwrite32f(jme, JME_TMCSR, 0);
1289         jwrite32f(jme, JME_TIMER2, 0);
1290         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1291
1292         apmc = jread32(jme, JME_APMC);
1293         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1294         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1295         wmb();
1296         jwrite32f(jme, JME_APMC, apmc);
1297 }
1298
1299 static void
1300 jme_link_change_tasklet(unsigned long arg)
1301 {
1302         struct jme_adapter *jme = (struct jme_adapter *)arg;
1303         struct net_device *netdev = jme->dev;
1304         int rc;
1305
1306         while (!atomic_dec_and_test(&jme->link_changing)) {
1307                 atomic_inc(&jme->link_changing);
1308                 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1309                 while (atomic_read(&jme->link_changing) != 1)
1310                         netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1311         }
1312
1313         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1314                 goto out;
1315
1316         jme->old_mtu = netdev->mtu;
1317         netif_stop_queue(netdev);
1318         if (jme_pseudo_hotplug_enabled(jme))
1319                 jme_stop_shutdown_timer(jme);
1320
1321         jme_stop_pcc_timer(jme);
1322         tasklet_disable(&jme->txclean_task);
1323         tasklet_disable(&jme->rxclean_task);
1324         tasklet_disable(&jme->rxempty_task);
1325
1326         if (netif_carrier_ok(netdev)) {
1327                 jme_disable_rx_engine(jme);
1328                 jme_disable_tx_engine(jme);
1329                 jme_reset_mac_processor(jme);
1330                 jme_free_rx_resources(jme);
1331                 jme_free_tx_resources(jme);
1332
1333                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1334                         jme_polling_mode(jme);
1335
1336                 netif_carrier_off(netdev);
1337         }
1338
1339         jme_check_link(netdev, 0);
1340         if (netif_carrier_ok(netdev)) {
1341                 rc = jme_setup_rx_resources(jme);
1342                 if (rc) {
1343                         pr_err("Allocating resources for RX error, Device STOPPED!\n");
1344                         goto out_enable_tasklet;
1345                 }
1346
1347                 rc = jme_setup_tx_resources(jme);
1348                 if (rc) {
1349                         pr_err("Allocating resources for TX error, Device STOPPED!\n");
1350                         goto err_out_free_rx_resources;
1351                 }
1352
1353                 jme_enable_rx_engine(jme);
1354                 jme_enable_tx_engine(jme);
1355
1356                 netif_start_queue(netdev);
1357
1358                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1359                         jme_interrupt_mode(jme);
1360
1361                 jme_start_pcc_timer(jme);
1362         } else if (jme_pseudo_hotplug_enabled(jme)) {
1363                 jme_start_shutdown_timer(jme);
1364         }
1365
1366         goto out_enable_tasklet;
1367
1368 err_out_free_rx_resources:
1369         jme_free_rx_resources(jme);
1370 out_enable_tasklet:
1371         tasklet_enable(&jme->txclean_task);
1372         tasklet_hi_enable(&jme->rxclean_task);
1373         tasklet_hi_enable(&jme->rxempty_task);
1374 out:
1375         atomic_inc(&jme->link_changing);
1376 }
1377
1378 static void
1379 jme_rx_clean_tasklet(unsigned long arg)
1380 {
1381         struct jme_adapter *jme = (struct jme_adapter *)arg;
1382         struct dynpcc_info *dpi = &(jme->dpi);
1383
1384         jme_process_receive(jme, jme->rx_ring_size);
1385         ++(dpi->intr_cnt);
1386
1387 }
1388
1389 static int
1390 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1391 {
1392         struct jme_adapter *jme = jme_napi_priv(holder);
1393         int rest;
1394
1395         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1396
1397         while (atomic_read(&jme->rx_empty) > 0) {
1398                 atomic_dec(&jme->rx_empty);
1399                 ++(NET_STAT(jme).rx_dropped);
1400                 jme_restart_rx_engine(jme);
1401         }
1402         atomic_inc(&jme->rx_empty);
1403
1404         if (rest) {
1405                 JME_RX_COMPLETE(netdev, holder);
1406                 jme_interrupt_mode(jme);
1407         }
1408
1409         JME_NAPI_WEIGHT_SET(budget, rest);
1410         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1411 }
1412
1413 static void
1414 jme_rx_empty_tasklet(unsigned long arg)
1415 {
1416         struct jme_adapter *jme = (struct jme_adapter *)arg;
1417
1418         if (unlikely(atomic_read(&jme->link_changing) != 1))
1419                 return;
1420
1421         if (unlikely(!netif_carrier_ok(jme->dev)))
1422                 return;
1423
1424         netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1425
1426         jme_rx_clean_tasklet(arg);
1427
1428         while (atomic_read(&jme->rx_empty) > 0) {
1429                 atomic_dec(&jme->rx_empty);
1430                 ++(NET_STAT(jme).rx_dropped);
1431                 jme_restart_rx_engine(jme);
1432         }
1433         atomic_inc(&jme->rx_empty);
1434 }
1435
1436 static void
1437 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1438 {
1439         struct jme_ring *txring = &(jme->txring[0]);
1440
1441         smp_wmb();
1442         if (unlikely(netif_queue_stopped(jme->dev) &&
1443         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1444                 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1445                 netif_wake_queue(jme->dev);
1446         }
1447
1448 }
1449
1450 static void
1451 jme_tx_clean_tasklet(unsigned long arg)
1452 {
1453         struct jme_adapter *jme = (struct jme_adapter *)arg;
1454         struct jme_ring *txring = &(jme->txring[0]);
1455         struct txdesc *txdesc = txring->desc;
1456         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1457         int i, j, cnt = 0, max, err, mask;
1458
1459         tx_dbg(jme, "Into txclean\n");
1460
1461         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1462                 goto out;
1463
1464         if (unlikely(atomic_read(&jme->link_changing) != 1))
1465                 goto out;
1466
1467         if (unlikely(!netif_carrier_ok(jme->dev)))
1468                 goto out;
1469
1470         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1471         mask = jme->tx_ring_mask;
1472
1473         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1474
1475                 ctxbi = txbi + i;
1476
1477                 if (likely(ctxbi->skb &&
1478                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1479
1480                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1481                                i, ctxbi->nr_desc, jiffies);
1482
1483                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1484
1485                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1486                                 ttxbi = txbi + ((i + j) & (mask));
1487                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1488
1489                                 pci_unmap_page(jme->pdev,
1490                                                  ttxbi->mapping,
1491                                                  ttxbi->len,
1492                                                  PCI_DMA_TODEVICE);
1493
1494                                 ttxbi->mapping = 0;
1495                                 ttxbi->len = 0;
1496                         }
1497
1498                         dev_kfree_skb(ctxbi->skb);
1499
1500                         cnt += ctxbi->nr_desc;
1501
1502                         if (unlikely(err)) {
1503                                 ++(NET_STAT(jme).tx_carrier_errors);
1504                         } else {
1505                                 ++(NET_STAT(jme).tx_packets);
1506                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1507                         }
1508
1509                         ctxbi->skb = NULL;
1510                         ctxbi->len = 0;
1511                         ctxbi->start_xmit = 0;
1512
1513                 } else {
1514                         break;
1515                 }
1516
1517                 i = (i + ctxbi->nr_desc) & mask;
1518
1519                 ctxbi->nr_desc = 0;
1520         }
1521
1522         tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1523         atomic_set(&txring->next_to_clean, i);
1524         atomic_add(cnt, &txring->nr_free);
1525
1526         jme_wake_queue_if_stopped(jme);
1527
1528 out:
1529         atomic_inc(&jme->tx_cleaning);
1530 }
1531
1532 static void
1533 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1534 {
1535         /*
1536          * Disable interrupt
1537          */
1538         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1539
1540         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1541                 /*
1542                  * Link change event is critical
1543                  * all other events are ignored
1544                  */
1545                 jwrite32(jme, JME_IEVE, intrstat);
1546                 tasklet_schedule(&jme->linkch_task);
1547                 goto out_reenable;
1548         }
1549
1550         if (intrstat & INTR_TMINTR) {
1551                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1552                 tasklet_schedule(&jme->pcc_task);
1553         }
1554
1555         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1556                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1557                 tasklet_schedule(&jme->txclean_task);
1558         }
1559
1560         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1561                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1562                                                      INTR_PCCRX0 |
1563                                                      INTR_RX0EMP)) |
1564                                         INTR_RX0);
1565         }
1566
1567         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1568                 if (intrstat & INTR_RX0EMP)
1569                         atomic_inc(&jme->rx_empty);
1570
1571                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1572                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1573                                 jme_polling_mode(jme);
1574                                 JME_RX_SCHEDULE(jme);
1575                         }
1576                 }
1577         } else {
1578                 if (intrstat & INTR_RX0EMP) {
1579                         atomic_inc(&jme->rx_empty);
1580                         tasklet_hi_schedule(&jme->rxempty_task);
1581                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1582                         tasklet_hi_schedule(&jme->rxclean_task);
1583                 }
1584         }
1585
1586 out_reenable:
1587         /*
1588          * Re-enable interrupt
1589          */
1590         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1591 }
1592
1593 static irqreturn_t
1594 jme_intr(int irq, void *dev_id)
1595 {
1596         struct net_device *netdev = dev_id;
1597         struct jme_adapter *jme = netdev_priv(netdev);
1598         u32 intrstat;
1599
1600         intrstat = jread32(jme, JME_IEVE);
1601
1602         /*
1603          * Check if it's really an interrupt for us
1604          */
1605         if (unlikely((intrstat & INTR_ENABLE) == 0))
1606                 return IRQ_NONE;
1607
1608         /*
1609          * Check if the device still exist
1610          */
1611         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1612                 return IRQ_NONE;
1613
1614         jme_intr_msi(jme, intrstat);
1615
1616         return IRQ_HANDLED;
1617 }
1618
1619 static irqreturn_t
1620 jme_msi(int irq, void *dev_id)
1621 {
1622         struct net_device *netdev = dev_id;
1623         struct jme_adapter *jme = netdev_priv(netdev);
1624         u32 intrstat;
1625
1626         intrstat = jread32(jme, JME_IEVE);
1627
1628         jme_intr_msi(jme, intrstat);
1629
1630         return IRQ_HANDLED;
1631 }
1632
1633 static void
1634 jme_reset_link(struct jme_adapter *jme)
1635 {
1636         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1637 }
1638
1639 static void
1640 jme_restart_an(struct jme_adapter *jme)
1641 {
1642         u32 bmcr;
1643
1644         spin_lock_bh(&jme->phy_lock);
1645         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1646         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1647         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1648         spin_unlock_bh(&jme->phy_lock);
1649 }
1650
1651 static int
1652 jme_request_irq(struct jme_adapter *jme)
1653 {
1654         int rc;
1655         struct net_device *netdev = jme->dev;
1656         irq_handler_t handler = jme_intr;
1657         int irq_flags = IRQF_SHARED;
1658
1659         if (!pci_enable_msi(jme->pdev)) {
1660                 set_bit(JME_FLAG_MSI, &jme->flags);
1661                 handler = jme_msi;
1662                 irq_flags = 0;
1663         }
1664
1665         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1666                           netdev);
1667         if (rc) {
1668                 netdev_err(netdev,
1669                            "Unable to request %s interrupt (return: %d)\n",
1670                            test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1671                            rc);
1672
1673                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1674                         pci_disable_msi(jme->pdev);
1675                         clear_bit(JME_FLAG_MSI, &jme->flags);
1676                 }
1677         } else {
1678                 netdev->irq = jme->pdev->irq;
1679         }
1680
1681         return rc;
1682 }
1683
1684 static void
1685 jme_free_irq(struct jme_adapter *jme)
1686 {
1687         free_irq(jme->pdev->irq, jme->dev);
1688         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1689                 pci_disable_msi(jme->pdev);
1690                 clear_bit(JME_FLAG_MSI, &jme->flags);
1691                 jme->dev->irq = jme->pdev->irq;
1692         }
1693 }
1694
1695 static inline void
1696 jme_new_phy_on(struct jme_adapter *jme)
1697 {
1698         u32 reg;
1699
1700         reg = jread32(jme, JME_PHY_PWR);
1701         reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1702                  PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1703         jwrite32(jme, JME_PHY_PWR, reg);
1704
1705         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1706         reg &= ~PE1_GPREG0_PBG;
1707         reg |= PE1_GPREG0_ENBG;
1708         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1709 }
1710
1711 static inline void
1712 jme_new_phy_off(struct jme_adapter *jme)
1713 {
1714         u32 reg;
1715
1716         reg = jread32(jme, JME_PHY_PWR);
1717         reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1718                PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1719         jwrite32(jme, JME_PHY_PWR, reg);
1720
1721         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1722         reg &= ~PE1_GPREG0_PBG;
1723         reg |= PE1_GPREG0_PDD3COLD;
1724         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1725 }
1726
1727 static inline void
1728 jme_phy_on(struct jme_adapter *jme)
1729 {
1730         u32 bmcr;
1731
1732         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1733         bmcr &= ~BMCR_PDOWN;
1734         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1735
1736         if (new_phy_power_ctrl(jme->chip_main_rev))
1737                 jme_new_phy_on(jme);
1738 }
1739
1740 static inline void
1741 jme_phy_off(struct jme_adapter *jme)
1742 {
1743         u32 bmcr;
1744
1745         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1746         bmcr |= BMCR_PDOWN;
1747         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1748
1749         if (new_phy_power_ctrl(jme->chip_main_rev))
1750                 jme_new_phy_off(jme);
1751 }
1752
1753 static int
1754 jme_phy_specreg_read(struct jme_adapter *jme, u32 specreg)
1755 {
1756         u32 phy_addr;
1757
1758         phy_addr = JM_PHY_SPEC_REG_READ | specreg;
1759         jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1760                         phy_addr);
1761         return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
1762                         JM_PHY_SPEC_DATA_REG);
1763 }
1764
1765 static void
1766 jme_phy_specreg_write(struct jme_adapter *jme, u32 ext_reg, u32 phy_data)
1767 {
1768         u32 phy_addr;
1769
1770         phy_addr = JM_PHY_SPEC_REG_WRITE | ext_reg;
1771         jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_DATA_REG,
1772                         phy_data);
1773         jme_mdio_write(jme->dev, jme->mii_if.phy_id, JM_PHY_SPEC_ADDR_REG,
1774                         phy_addr);
1775 }
1776
1777 static int
1778 jme_phy_calibration(struct jme_adapter *jme)
1779 {
1780         u32 ctrl1000, phy_data;
1781
1782         jme_phy_off(jme);
1783         jme_phy_on(jme);
1784         /*  Enabel PHY test mode 1 */
1785         ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1786         ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1787         ctrl1000 |= PHY_GAD_TEST_MODE_1;
1788         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1789
1790         phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1791         phy_data &= ~JM_PHY_EXT_COMM_2_CALI_MODE_0;
1792         phy_data |= JM_PHY_EXT_COMM_2_CALI_LATCH |
1793                         JM_PHY_EXT_COMM_2_CALI_ENABLE;
1794         jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1795         msleep(20);
1796         phy_data = jme_phy_specreg_read(jme, JM_PHY_EXT_COMM_2_REG);
1797         phy_data &= ~(JM_PHY_EXT_COMM_2_CALI_ENABLE |
1798                         JM_PHY_EXT_COMM_2_CALI_MODE_0 |
1799                         JM_PHY_EXT_COMM_2_CALI_LATCH);
1800         jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_2_REG, phy_data);
1801
1802         /*  Disable PHY test mode */
1803         ctrl1000 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_CTRL1000);
1804         ctrl1000 &= ~PHY_GAD_TEST_MODE_MSK;
1805         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_CTRL1000, ctrl1000);
1806         return 0;
1807 }
1808
1809 static int
1810 jme_phy_setEA(struct jme_adapter *jme)
1811 {
1812         u32 phy_comm0 = 0, phy_comm1 = 0;
1813         u8 nic_ctrl;
1814
1815         pci_read_config_byte(jme->pdev, PCI_PRIV_SHARE_NICCTRL, &nic_ctrl);
1816         if ((nic_ctrl & 0x3) == JME_FLAG_PHYEA_ENABLE)
1817                 return 0;
1818
1819         switch (jme->pdev->device) {
1820         case PCI_DEVICE_ID_JMICRON_JMC250:
1821                 if (((jme->chip_main_rev == 5) &&
1822                         ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1823                         (jme->chip_sub_rev == 3))) ||
1824                         (jme->chip_main_rev >= 6)) {
1825                         phy_comm0 = 0x008A;
1826                         phy_comm1 = 0x4109;
1827                 }
1828                 if ((jme->chip_main_rev == 3) &&
1829                         ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1830                         phy_comm0 = 0xE088;
1831                 break;
1832         case PCI_DEVICE_ID_JMICRON_JMC260:
1833                 if (((jme->chip_main_rev == 5) &&
1834                         ((jme->chip_sub_rev == 0) || (jme->chip_sub_rev == 1) ||
1835                         (jme->chip_sub_rev == 3))) ||
1836                         (jme->chip_main_rev >= 6)) {
1837                         phy_comm0 = 0x008A;
1838                         phy_comm1 = 0x4109;
1839                 }
1840                 if ((jme->chip_main_rev == 3) &&
1841                         ((jme->chip_sub_rev == 1) || (jme->chip_sub_rev == 2)))
1842                         phy_comm0 = 0xE088;
1843                 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 0))
1844                         phy_comm0 = 0x608A;
1845                 if ((jme->chip_main_rev == 2) && (jme->chip_sub_rev == 2))
1846                         phy_comm0 = 0x408A;
1847                 break;
1848         default:
1849                 return -ENODEV;
1850         }
1851         if (phy_comm0)
1852                 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_0_REG, phy_comm0);
1853         if (phy_comm1)
1854                 jme_phy_specreg_write(jme, JM_PHY_EXT_COMM_1_REG, phy_comm1);
1855
1856         return 0;
1857 }
1858
1859 static int
1860 jme_open(struct net_device *netdev)
1861 {
1862         struct jme_adapter *jme = netdev_priv(netdev);
1863         int rc;
1864
1865         jme_clear_pm_disable_wol(jme);
1866         JME_NAPI_ENABLE(jme);
1867
1868         tasklet_enable(&jme->linkch_task);
1869         tasklet_enable(&jme->txclean_task);
1870         tasklet_hi_enable(&jme->rxclean_task);
1871         tasklet_hi_enable(&jme->rxempty_task);
1872
1873         rc = jme_request_irq(jme);
1874         if (rc)
1875                 goto err_out;
1876
1877         jme_start_irq(jme);
1878
1879         jme_phy_on(jme);
1880         if (test_bit(JME_FLAG_SSET, &jme->flags))
1881                 jme_set_settings(netdev, &jme->old_ecmd);
1882         else
1883                 jme_reset_phy_processor(jme);
1884         jme_phy_calibration(jme);
1885         jme_phy_setEA(jme);
1886         jme_reset_link(jme);
1887
1888         return 0;
1889
1890 err_out:
1891         netif_stop_queue(netdev);
1892         netif_carrier_off(netdev);
1893         return rc;
1894 }
1895
1896 static void
1897 jme_set_100m_half(struct jme_adapter *jme)
1898 {
1899         u32 bmcr, tmp;
1900
1901         jme_phy_on(jme);
1902         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1903         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1904                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1905         tmp |= BMCR_SPEED100;
1906
1907         if (bmcr != tmp)
1908                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1909
1910         if (jme->fpgaver)
1911                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1912         else
1913                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1914 }
1915
1916 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1917 static void
1918 jme_wait_link(struct jme_adapter *jme)
1919 {
1920         u32 phylink, to = JME_WAIT_LINK_TIME;
1921
1922         mdelay(1000);
1923         phylink = jme_linkstat_from_phy(jme);
1924         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1925                 mdelay(10);
1926                 phylink = jme_linkstat_from_phy(jme);
1927         }
1928 }
1929
1930 static void
1931 jme_powersave_phy(struct jme_adapter *jme)
1932 {
1933         if (jme->reg_pmcs && device_may_wakeup(&jme->pdev->dev)) {
1934                 jme_set_100m_half(jme);
1935                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1936                         jme_wait_link(jme);
1937                 jme_clear_pm_enable_wol(jme);
1938         } else {
1939                 jme_phy_off(jme);
1940         }
1941 }
1942
1943 static int
1944 jme_close(struct net_device *netdev)
1945 {
1946         struct jme_adapter *jme = netdev_priv(netdev);
1947
1948         netif_stop_queue(netdev);
1949         netif_carrier_off(netdev);
1950
1951         jme_stop_irq(jme);
1952         jme_free_irq(jme);
1953
1954         JME_NAPI_DISABLE(jme);
1955
1956         tasklet_disable(&jme->linkch_task);
1957         tasklet_disable(&jme->txclean_task);
1958         tasklet_disable(&jme->rxclean_task);
1959         tasklet_disable(&jme->rxempty_task);
1960
1961         jme_disable_rx_engine(jme);
1962         jme_disable_tx_engine(jme);
1963         jme_reset_mac_processor(jme);
1964         jme_free_rx_resources(jme);
1965         jme_free_tx_resources(jme);
1966         jme->phylink = 0;
1967         jme_phy_off(jme);
1968
1969         return 0;
1970 }
1971
1972 static int
1973 jme_alloc_txdesc(struct jme_adapter *jme,
1974                         struct sk_buff *skb)
1975 {
1976         struct jme_ring *txring = &(jme->txring[0]);
1977         int idx, nr_alloc, mask = jme->tx_ring_mask;
1978
1979         idx = txring->next_to_use;
1980         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1981
1982         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1983                 return -1;
1984
1985         atomic_sub(nr_alloc, &txring->nr_free);
1986
1987         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1988
1989         return idx;
1990 }
1991
1992 static void
1993 jme_fill_tx_map(struct pci_dev *pdev,
1994                 struct txdesc *txdesc,
1995                 struct jme_buffer_info *txbi,
1996                 struct page *page,
1997                 u32 page_offset,
1998                 u32 len,
1999                 u8 hidma)
2000 {
2001         dma_addr_t dmaaddr;
2002
2003         dmaaddr = pci_map_page(pdev,
2004                                 page,
2005                                 page_offset,
2006                                 len,
2007                                 PCI_DMA_TODEVICE);
2008
2009         pci_dma_sync_single_for_device(pdev,
2010                                        dmaaddr,
2011                                        len,
2012                                        PCI_DMA_TODEVICE);
2013
2014         txdesc->dw[0] = 0;
2015         txdesc->dw[1] = 0;
2016         txdesc->desc2.flags     = TXFLAG_OWN;
2017         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
2018         txdesc->desc2.datalen   = cpu_to_le16(len);
2019         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
2020         txdesc->desc2.bufaddrl  = cpu_to_le32(
2021                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
2022
2023         txbi->mapping = dmaaddr;
2024         txbi->len = len;
2025 }
2026
2027 static void
2028 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2029 {
2030         struct jme_ring *txring = &(jme->txring[0]);
2031         struct txdesc *txdesc = txring->desc, *ctxdesc;
2032         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
2033         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
2034         int i, nr_frags = skb_shinfo(skb)->nr_frags;
2035         int mask = jme->tx_ring_mask;
2036         const struct skb_frag_struct *frag;
2037         u32 len;
2038
2039         for (i = 0 ; i < nr_frags ; ++i) {
2040                 frag = &skb_shinfo(skb)->frags[i];
2041                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
2042                 ctxbi = txbi + ((idx + i + 2) & (mask));
2043
2044                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi,
2045                                 skb_frag_page(frag),
2046                                 frag->page_offset, skb_frag_size(frag), hidma);
2047         }
2048
2049         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
2050         ctxdesc = txdesc + ((idx + 1) & (mask));
2051         ctxbi = txbi + ((idx + 1) & (mask));
2052         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
2053                         offset_in_page(skb->data), len, hidma);
2054
2055 }
2056
2057 static int
2058 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2059 {
2060         if (unlikely(skb_shinfo(skb)->gso_size &&
2061                         skb_header_cloned(skb) &&
2062                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2063                 dev_kfree_skb(skb);
2064                 return -1;
2065         }
2066
2067         return 0;
2068 }
2069
2070 static int
2071 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2072 {
2073         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2074         if (*mss) {
2075                 *flags |= TXFLAG_LSEN;
2076
2077                 if (skb->protocol == htons(ETH_P_IP)) {
2078                         struct iphdr *iph = ip_hdr(skb);
2079
2080                         iph->check = 0;
2081                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2082                                                                 iph->daddr, 0,
2083                                                                 IPPROTO_TCP,
2084                                                                 0);
2085                 } else {
2086                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
2087
2088                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2089                                                                 &ip6h->daddr, 0,
2090                                                                 IPPROTO_TCP,
2091                                                                 0);
2092                 }
2093
2094                 return 0;
2095         }
2096
2097         return 1;
2098 }
2099
2100 static void
2101 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2102 {
2103         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2104                 u8 ip_proto;
2105
2106                 switch (skb->protocol) {
2107                 case htons(ETH_P_IP):
2108                         ip_proto = ip_hdr(skb)->protocol;
2109                         break;
2110                 case htons(ETH_P_IPV6):
2111                         ip_proto = ipv6_hdr(skb)->nexthdr;
2112                         break;
2113                 default:
2114                         ip_proto = 0;
2115                         break;
2116                 }
2117
2118                 switch (ip_proto) {
2119                 case IPPROTO_TCP:
2120                         *flags |= TXFLAG_TCPCS;
2121                         break;
2122                 case IPPROTO_UDP:
2123                         *flags |= TXFLAG_UDPCS;
2124                         break;
2125                 default:
2126                         netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2127                         break;
2128                 }
2129         }
2130 }
2131
2132 static inline void
2133 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2134 {
2135         if (vlan_tx_tag_present(skb)) {
2136                 *flags |= TXFLAG_TAGON;
2137                 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2138         }
2139 }
2140
2141 static int
2142 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2143 {
2144         struct jme_ring *txring = &(jme->txring[0]);
2145         struct txdesc *txdesc;
2146         struct jme_buffer_info *txbi;
2147         u8 flags;
2148
2149         txdesc = (struct txdesc *)txring->desc + idx;
2150         txbi = txring->bufinf + idx;
2151
2152         txdesc->dw[0] = 0;
2153         txdesc->dw[1] = 0;
2154         txdesc->dw[2] = 0;
2155         txdesc->dw[3] = 0;
2156         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2157         /*
2158          * Set OWN bit at final.
2159          * When kernel transmit faster than NIC.
2160          * And NIC trying to send this descriptor before we tell
2161          * it to start sending this TX queue.
2162          * Other fields are already filled correctly.
2163          */
2164         wmb();
2165         flags = TXFLAG_OWN | TXFLAG_INT;
2166         /*
2167          * Set checksum flags while not tso
2168          */
2169         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2170                 jme_tx_csum(jme, skb, &flags);
2171         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2172         jme_map_tx_skb(jme, skb, idx);
2173         txdesc->desc1.flags = flags;
2174         /*
2175          * Set tx buffer info after telling NIC to send
2176          * For better tx_clean timing
2177          */
2178         wmb();
2179         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2180         txbi->skb = skb;
2181         txbi->len = skb->len;
2182         txbi->start_xmit = jiffies;
2183         if (!txbi->start_xmit)
2184                 txbi->start_xmit = (0UL-1);
2185
2186         return 0;
2187 }
2188
2189 static void
2190 jme_stop_queue_if_full(struct jme_adapter *jme)
2191 {
2192         struct jme_ring *txring = &(jme->txring[0]);
2193         struct jme_buffer_info *txbi = txring->bufinf;
2194         int idx = atomic_read(&txring->next_to_clean);
2195
2196         txbi += idx;
2197
2198         smp_wmb();
2199         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2200                 netif_stop_queue(jme->dev);
2201                 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2202                 smp_wmb();
2203                 if (atomic_read(&txring->nr_free)
2204                         >= (jme->tx_wake_threshold)) {
2205                         netif_wake_queue(jme->dev);
2206                         netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2207                 }
2208         }
2209
2210         if (unlikely(txbi->start_xmit &&
2211                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2212                         txbi->skb)) {
2213                 netif_stop_queue(jme->dev);
2214                 netif_info(jme, tx_queued, jme->dev,
2215                            "TX Queue Stopped %d@%lu\n", idx, jiffies);
2216         }
2217 }
2218
2219 /*
2220  * This function is already protected by netif_tx_lock()
2221  */
2222
2223 static netdev_tx_t
2224 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2225 {
2226         struct jme_adapter *jme = netdev_priv(netdev);
2227         int idx;
2228
2229         if (unlikely(jme_expand_header(jme, skb))) {
2230                 ++(NET_STAT(jme).tx_dropped);
2231                 return NETDEV_TX_OK;
2232         }
2233
2234         idx = jme_alloc_txdesc(jme, skb);
2235
2236         if (unlikely(idx < 0)) {
2237                 netif_stop_queue(netdev);
2238                 netif_err(jme, tx_err, jme->dev,
2239                           "BUG! Tx ring full when queue awake!\n");
2240
2241                 return NETDEV_TX_BUSY;
2242         }
2243
2244         jme_fill_tx_desc(jme, skb, idx);
2245
2246         jwrite32(jme, JME_TXCS, jme->reg_txcs |
2247                                 TXCS_SELECT_QUEUE0 |
2248                                 TXCS_QUEUE0S |
2249                                 TXCS_ENABLE);
2250
2251         tx_dbg(jme, "xmit: %d+%d@%lu\n",
2252                idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2253         jme_stop_queue_if_full(jme);
2254
2255         return NETDEV_TX_OK;
2256 }
2257
2258 static void
2259 jme_set_unicastaddr(struct net_device *netdev)
2260 {
2261         struct jme_adapter *jme = netdev_priv(netdev);
2262         u32 val;
2263
2264         val = (netdev->dev_addr[3] & 0xff) << 24 |
2265               (netdev->dev_addr[2] & 0xff) << 16 |
2266               (netdev->dev_addr[1] & 0xff) <<  8 |
2267               (netdev->dev_addr[0] & 0xff);
2268         jwrite32(jme, JME_RXUMA_LO, val);
2269         val = (netdev->dev_addr[5] & 0xff) << 8 |
2270               (netdev->dev_addr[4] & 0xff);
2271         jwrite32(jme, JME_RXUMA_HI, val);
2272 }
2273
2274 static int
2275 jme_set_macaddr(struct net_device *netdev, void *p)
2276 {
2277         struct jme_adapter *jme = netdev_priv(netdev);
2278         struct sockaddr *addr = p;
2279
2280         if (netif_running(netdev))
2281                 return -EBUSY;
2282
2283         spin_lock_bh(&jme->macaddr_lock);
2284         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2285         jme_set_unicastaddr(netdev);
2286         spin_unlock_bh(&jme->macaddr_lock);
2287
2288         return 0;
2289 }
2290
2291 static void
2292 jme_set_multi(struct net_device *netdev)
2293 {
2294         struct jme_adapter *jme = netdev_priv(netdev);
2295         u32 mc_hash[2] = {};
2296
2297         spin_lock_bh(&jme->rxmcs_lock);
2298
2299         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2300
2301         if (netdev->flags & IFF_PROMISC) {
2302                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2303         } else if (netdev->flags & IFF_ALLMULTI) {
2304                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2305         } else if (netdev->flags & IFF_MULTICAST) {
2306                 struct netdev_hw_addr *ha;
2307                 int bit_nr;
2308
2309                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2310                 netdev_for_each_mc_addr(ha, netdev) {
2311                         bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2312                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2313                 }
2314
2315                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2316                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2317         }
2318
2319         wmb();
2320         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2321
2322         spin_unlock_bh(&jme->rxmcs_lock);
2323 }
2324
2325 static int
2326 jme_change_mtu(struct net_device *netdev, int new_mtu)
2327 {
2328         struct jme_adapter *jme = netdev_priv(netdev);
2329
2330         if (new_mtu == jme->old_mtu)
2331                 return 0;
2332
2333         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2334                 ((new_mtu) < IPV6_MIN_MTU))
2335                 return -EINVAL;
2336
2337
2338         netdev->mtu = new_mtu;
2339         netdev_update_features(netdev);
2340
2341         jme_restart_rx_engine(jme);
2342         jme_reset_link(jme);
2343
2344         return 0;
2345 }
2346
2347 static void
2348 jme_tx_timeout(struct net_device *netdev)
2349 {
2350         struct jme_adapter *jme = netdev_priv(netdev);
2351
2352         jme->phylink = 0;
2353         jme_reset_phy_processor(jme);
2354         if (test_bit(JME_FLAG_SSET, &jme->flags))
2355                 jme_set_settings(netdev, &jme->old_ecmd);
2356
2357         /*
2358          * Force to Reset the link again
2359          */
2360         jme_reset_link(jme);
2361 }
2362
2363 static inline void jme_pause_rx(struct jme_adapter *jme)
2364 {
2365         atomic_dec(&jme->link_changing);
2366
2367         jme_set_rx_pcc(jme, PCC_OFF);
2368         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2369                 JME_NAPI_DISABLE(jme);
2370         } else {
2371                 tasklet_disable(&jme->rxclean_task);
2372                 tasklet_disable(&jme->rxempty_task);
2373         }
2374 }
2375
2376 static inline void jme_resume_rx(struct jme_adapter *jme)
2377 {
2378         struct dynpcc_info *dpi = &(jme->dpi);
2379
2380         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2381                 JME_NAPI_ENABLE(jme);
2382         } else {
2383                 tasklet_hi_enable(&jme->rxclean_task);
2384                 tasklet_hi_enable(&jme->rxempty_task);
2385         }
2386         dpi->cur                = PCC_P1;
2387         dpi->attempt            = PCC_P1;
2388         dpi->cnt                = 0;
2389         jme_set_rx_pcc(jme, PCC_P1);
2390
2391         atomic_inc(&jme->link_changing);
2392 }
2393
2394 static void
2395 jme_get_drvinfo(struct net_device *netdev,
2396                      struct ethtool_drvinfo *info)
2397 {
2398         struct jme_adapter *jme = netdev_priv(netdev);
2399
2400         strcpy(info->driver, DRV_NAME);
2401         strcpy(info->version, DRV_VERSION);
2402         strcpy(info->bus_info, pci_name(jme->pdev));
2403 }
2404
2405 static int
2406 jme_get_regs_len(struct net_device *netdev)
2407 {
2408         return JME_REG_LEN;
2409 }
2410
2411 static void
2412 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2413 {
2414         int i;
2415
2416         for (i = 0 ; i < len ; i += 4)
2417                 p[i >> 2] = jread32(jme, reg + i);
2418 }
2419
2420 static void
2421 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2422 {
2423         int i;
2424         u16 *p16 = (u16 *)p;
2425
2426         for (i = 0 ; i < reg_nr ; ++i)
2427                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2428 }
2429
2430 static void
2431 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2432 {
2433         struct jme_adapter *jme = netdev_priv(netdev);
2434         u32 *p32 = (u32 *)p;
2435
2436         memset(p, 0xFF, JME_REG_LEN);
2437
2438         regs->version = 1;
2439         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2440
2441         p32 += 0x100 >> 2;
2442         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2443
2444         p32 += 0x100 >> 2;
2445         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2446
2447         p32 += 0x100 >> 2;
2448         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2449
2450         p32 += 0x100 >> 2;
2451         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2452 }
2453
2454 static int
2455 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2456 {
2457         struct jme_adapter *jme = netdev_priv(netdev);
2458
2459         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2460         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2461
2462         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2463                 ecmd->use_adaptive_rx_coalesce = false;
2464                 ecmd->rx_coalesce_usecs = 0;
2465                 ecmd->rx_max_coalesced_frames = 0;
2466                 return 0;
2467         }
2468
2469         ecmd->use_adaptive_rx_coalesce = true;
2470
2471         switch (jme->dpi.cur) {
2472         case PCC_P1:
2473                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2474                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2475                 break;
2476         case PCC_P2:
2477                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2478                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2479                 break;
2480         case PCC_P3:
2481                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2482                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2483                 break;
2484         default:
2485                 break;
2486         }
2487
2488         return 0;
2489 }
2490
2491 static int
2492 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2493 {
2494         struct jme_adapter *jme = netdev_priv(netdev);
2495         struct dynpcc_info *dpi = &(jme->dpi);
2496
2497         if (netif_running(netdev))
2498                 return -EBUSY;
2499
2500         if (ecmd->use_adaptive_rx_coalesce &&
2501             test_bit(JME_FLAG_POLL, &jme->flags)) {
2502                 clear_bit(JME_FLAG_POLL, &jme->flags);
2503                 jme->jme_rx = netif_rx;
2504                 dpi->cur                = PCC_P1;
2505                 dpi->attempt            = PCC_P1;
2506                 dpi->cnt                = 0;
2507                 jme_set_rx_pcc(jme, PCC_P1);
2508                 jme_interrupt_mode(jme);
2509         } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2510                    !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2511                 set_bit(JME_FLAG_POLL, &jme->flags);
2512                 jme->jme_rx = netif_receive_skb;
2513                 jme_interrupt_mode(jme);
2514         }
2515
2516         return 0;
2517 }
2518
2519 static void
2520 jme_get_pauseparam(struct net_device *netdev,
2521                         struct ethtool_pauseparam *ecmd)
2522 {
2523         struct jme_adapter *jme = netdev_priv(netdev);
2524         u32 val;
2525
2526         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2527         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2528
2529         spin_lock_bh(&jme->phy_lock);
2530         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2531         spin_unlock_bh(&jme->phy_lock);
2532
2533         ecmd->autoneg =
2534                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2535 }
2536
2537 static int
2538 jme_set_pauseparam(struct net_device *netdev,
2539                         struct ethtool_pauseparam *ecmd)
2540 {
2541         struct jme_adapter *jme = netdev_priv(netdev);
2542         u32 val;
2543
2544         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2545                 (ecmd->tx_pause != 0)) {
2546
2547                 if (ecmd->tx_pause)
2548                         jme->reg_txpfc |= TXPFC_PF_EN;
2549                 else
2550                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2551
2552                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2553         }
2554
2555         spin_lock_bh(&jme->rxmcs_lock);
2556         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2557                 (ecmd->rx_pause != 0)) {
2558
2559                 if (ecmd->rx_pause)
2560                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2561                 else
2562                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2563
2564                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2565         }
2566         spin_unlock_bh(&jme->rxmcs_lock);
2567
2568         spin_lock_bh(&jme->phy_lock);
2569         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2570         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2571                 (ecmd->autoneg != 0)) {
2572
2573                 if (ecmd->autoneg)
2574                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2575                 else
2576                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2577
2578                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2579                                 MII_ADVERTISE, val);
2580         }
2581         spin_unlock_bh(&jme->phy_lock);
2582
2583         return 0;
2584 }
2585
2586 static void
2587 jme_get_wol(struct net_device *netdev,
2588                 struct ethtool_wolinfo *wol)
2589 {
2590         struct jme_adapter *jme = netdev_priv(netdev);
2591
2592         wol->supported = WAKE_MAGIC | WAKE_PHY;
2593
2594         wol->wolopts = 0;
2595
2596         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2597                 wol->wolopts |= WAKE_PHY;
2598
2599         if (jme->reg_pmcs & PMCS_MFEN)
2600                 wol->wolopts |= WAKE_MAGIC;
2601
2602 }
2603
2604 static int
2605 jme_set_wol(struct net_device *netdev,
2606                 struct ethtool_wolinfo *wol)
2607 {
2608         struct jme_adapter *jme = netdev_priv(netdev);
2609
2610         if (wol->wolopts & (WAKE_MAGICSECURE |
2611                                 WAKE_UCAST |
2612                                 WAKE_MCAST |
2613                                 WAKE_BCAST |
2614                                 WAKE_ARP))
2615                 return -EOPNOTSUPP;
2616
2617         jme->reg_pmcs = 0;
2618
2619         if (wol->wolopts & WAKE_PHY)
2620                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2621
2622         if (wol->wolopts & WAKE_MAGIC)
2623                 jme->reg_pmcs |= PMCS_MFEN;
2624
2625         return 0;
2626 }
2627
2628 static int
2629 jme_get_settings(struct net_device *netdev,
2630                      struct ethtool_cmd *ecmd)
2631 {
2632         struct jme_adapter *jme = netdev_priv(netdev);
2633         int rc;
2634
2635         spin_lock_bh(&jme->phy_lock);
2636         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2637         spin_unlock_bh(&jme->phy_lock);
2638         return rc;
2639 }
2640
2641 static int
2642 jme_set_settings(struct net_device *netdev,
2643                      struct ethtool_cmd *ecmd)
2644 {
2645         struct jme_adapter *jme = netdev_priv(netdev);
2646         int rc, fdc = 0;
2647
2648         if (ethtool_cmd_speed(ecmd) == SPEED_1000
2649             && ecmd->autoneg != AUTONEG_ENABLE)
2650                 return -EINVAL;
2651
2652         /*
2653          * Check If user changed duplex only while force_media.
2654          * Hardware would not generate link change interrupt.
2655          */
2656         if (jme->mii_if.force_media &&
2657         ecmd->autoneg != AUTONEG_ENABLE &&
2658         (jme->mii_if.full_duplex != ecmd->duplex))
2659                 fdc = 1;
2660
2661         spin_lock_bh(&jme->phy_lock);
2662         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2663         spin_unlock_bh(&jme->phy_lock);
2664
2665         if (!rc) {
2666                 if (fdc)
2667                         jme_reset_link(jme);
2668                 jme->old_ecmd = *ecmd;
2669                 set_bit(JME_FLAG_SSET, &jme->flags);
2670         }
2671
2672         return rc;
2673 }
2674
2675 static int
2676 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2677 {
2678         int rc;
2679         struct jme_adapter *jme = netdev_priv(netdev);
2680         struct mii_ioctl_data *mii_data = if_mii(rq);
2681         unsigned int duplex_chg;
2682
2683         if (cmd == SIOCSMIIREG) {
2684                 u16 val = mii_data->val_in;
2685                 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2686                     (val & BMCR_SPEED1000))
2687                         return -EINVAL;
2688         }
2689
2690         spin_lock_bh(&jme->phy_lock);
2691         rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2692         spin_unlock_bh(&jme->phy_lock);
2693
2694         if (!rc && (cmd == SIOCSMIIREG)) {
2695                 if (duplex_chg)
2696                         jme_reset_link(jme);
2697                 jme_get_settings(netdev, &jme->old_ecmd);
2698                 set_bit(JME_FLAG_SSET, &jme->flags);
2699         }
2700
2701         return rc;
2702 }
2703
2704 static u32
2705 jme_get_link(struct net_device *netdev)
2706 {
2707         struct jme_adapter *jme = netdev_priv(netdev);
2708         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2709 }
2710
2711 static u32
2712 jme_get_msglevel(struct net_device *netdev)
2713 {
2714         struct jme_adapter *jme = netdev_priv(netdev);
2715         return jme->msg_enable;
2716 }
2717
2718 static void
2719 jme_set_msglevel(struct net_device *netdev, u32 value)
2720 {
2721         struct jme_adapter *jme = netdev_priv(netdev);
2722         jme->msg_enable = value;
2723 }
2724
2725 static u32
2726 jme_fix_features(struct net_device *netdev, u32 features)
2727 {
2728         if (netdev->mtu > 1900)
2729                 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2730         return features;
2731 }
2732
2733 static int
2734 jme_set_features(struct net_device *netdev, u32 features)
2735 {
2736         struct jme_adapter *jme = netdev_priv(netdev);
2737
2738         spin_lock_bh(&jme->rxmcs_lock);
2739         if (features & NETIF_F_RXCSUM)
2740                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2741         else
2742                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2743         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2744         spin_unlock_bh(&jme->rxmcs_lock);
2745
2746         return 0;
2747 }
2748
2749 static int
2750 jme_nway_reset(struct net_device *netdev)
2751 {
2752         struct jme_adapter *jme = netdev_priv(netdev);
2753         jme_restart_an(jme);
2754         return 0;
2755 }
2756
2757 static u8
2758 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2759 {
2760         u32 val;
2761         int to;
2762
2763         val = jread32(jme, JME_SMBCSR);
2764         to = JME_SMB_BUSY_TIMEOUT;
2765         while ((val & SMBCSR_BUSY) && --to) {
2766                 msleep(1);
2767                 val = jread32(jme, JME_SMBCSR);
2768         }
2769         if (!to) {
2770                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2771                 return 0xFF;
2772         }
2773
2774         jwrite32(jme, JME_SMBINTF,
2775                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2776                 SMBINTF_HWRWN_READ |
2777                 SMBINTF_HWCMD);
2778
2779         val = jread32(jme, JME_SMBINTF);
2780         to = JME_SMB_BUSY_TIMEOUT;
2781         while ((val & SMBINTF_HWCMD) && --to) {
2782                 msleep(1);
2783                 val = jread32(jme, JME_SMBINTF);
2784         }
2785         if (!to) {
2786                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2787                 return 0xFF;
2788         }
2789
2790         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2791 }
2792
2793 static void
2794 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2795 {
2796         u32 val;
2797         int to;
2798
2799         val = jread32(jme, JME_SMBCSR);
2800         to = JME_SMB_BUSY_TIMEOUT;
2801         while ((val & SMBCSR_BUSY) && --to) {
2802                 msleep(1);
2803                 val = jread32(jme, JME_SMBCSR);
2804         }
2805         if (!to) {
2806                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2807                 return;
2808         }
2809
2810         jwrite32(jme, JME_SMBINTF,
2811                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2812                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2813                 SMBINTF_HWRWN_WRITE |
2814                 SMBINTF_HWCMD);
2815
2816         val = jread32(jme, JME_SMBINTF);
2817         to = JME_SMB_BUSY_TIMEOUT;
2818         while ((val & SMBINTF_HWCMD) && --to) {
2819                 msleep(1);
2820                 val = jread32(jme, JME_SMBINTF);
2821         }
2822         if (!to) {
2823                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2824                 return;
2825         }
2826
2827         mdelay(2);
2828 }
2829
2830 static int
2831 jme_get_eeprom_len(struct net_device *netdev)
2832 {
2833         struct jme_adapter *jme = netdev_priv(netdev);
2834         u32 val;
2835         val = jread32(jme, JME_SMBCSR);
2836         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2837 }
2838
2839 static int
2840 jme_get_eeprom(struct net_device *netdev,
2841                 struct ethtool_eeprom *eeprom, u8 *data)
2842 {
2843         struct jme_adapter *jme = netdev_priv(netdev);
2844         int i, offset = eeprom->offset, len = eeprom->len;
2845
2846         /*
2847          * ethtool will check the boundary for us
2848          */
2849         eeprom->magic = JME_EEPROM_MAGIC;
2850         for (i = 0 ; i < len ; ++i)
2851                 data[i] = jme_smb_read(jme, i + offset);
2852
2853         return 0;
2854 }
2855
2856 static int
2857 jme_set_eeprom(struct net_device *netdev,
2858                 struct ethtool_eeprom *eeprom, u8 *data)
2859 {
2860         struct jme_adapter *jme = netdev_priv(netdev);
2861         int i, offset = eeprom->offset, len = eeprom->len;
2862
2863         if (eeprom->magic != JME_EEPROM_MAGIC)
2864                 return -EINVAL;
2865
2866         /*
2867          * ethtool will check the boundary for us
2868          */
2869         for (i = 0 ; i < len ; ++i)
2870                 jme_smb_write(jme, i + offset, data[i]);
2871
2872         return 0;
2873 }
2874
2875 static const struct ethtool_ops jme_ethtool_ops = {
2876         .get_drvinfo            = jme_get_drvinfo,
2877         .get_regs_len           = jme_get_regs_len,
2878         .get_regs               = jme_get_regs,
2879         .get_coalesce           = jme_get_coalesce,
2880         .set_coalesce           = jme_set_coalesce,
2881         .get_pauseparam         = jme_get_pauseparam,
2882         .set_pauseparam         = jme_set_pauseparam,
2883         .get_wol                = jme_get_wol,
2884         .set_wol                = jme_set_wol,
2885         .get_settings           = jme_get_settings,
2886         .set_settings           = jme_set_settings,
2887         .get_link               = jme_get_link,
2888         .get_msglevel           = jme_get_msglevel,
2889         .set_msglevel           = jme_set_msglevel,
2890         .nway_reset             = jme_nway_reset,
2891         .get_eeprom_len         = jme_get_eeprom_len,
2892         .get_eeprom             = jme_get_eeprom,
2893         .set_eeprom             = jme_set_eeprom,
2894 };
2895
2896 static int
2897 jme_pci_dma64(struct pci_dev *pdev)
2898 {
2899         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2900             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2901                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2902                         return 1;
2903
2904         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2905             !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2906                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2907                         return 1;
2908
2909         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2910                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2911                         return 0;
2912
2913         return -1;
2914 }
2915
2916 static inline void
2917 jme_phy_init(struct jme_adapter *jme)
2918 {
2919         u16 reg26;
2920
2921         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2922         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2923 }
2924
2925 static inline void
2926 jme_check_hw_ver(struct jme_adapter *jme)
2927 {
2928         u32 chipmode;
2929
2930         chipmode = jread32(jme, JME_CHIPMODE);
2931
2932         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2933         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2934         jme->chip_main_rev = jme->chiprev & 0xF;
2935         jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2936 }
2937
2938 static const struct net_device_ops jme_netdev_ops = {
2939         .ndo_open               = jme_open,
2940         .ndo_stop               = jme_close,
2941         .ndo_validate_addr      = eth_validate_addr,
2942         .ndo_do_ioctl           = jme_ioctl,
2943         .ndo_start_xmit         = jme_start_xmit,
2944         .ndo_set_mac_address    = jme_set_macaddr,
2945         .ndo_set_rx_mode        = jme_set_multi,
2946         .ndo_change_mtu         = jme_change_mtu,
2947         .ndo_tx_timeout         = jme_tx_timeout,
2948         .ndo_fix_features       = jme_fix_features,
2949         .ndo_set_features       = jme_set_features,
2950 };
2951
2952 static int __devinit
2953 jme_init_one(struct pci_dev *pdev,
2954              const struct pci_device_id *ent)
2955 {
2956         int rc = 0, using_dac, i;
2957         struct net_device *netdev;
2958         struct jme_adapter *jme;
2959         u16 bmcr, bmsr;
2960         u32 apmc;
2961
2962         /*
2963          * set up PCI device basics
2964          */
2965         rc = pci_enable_device(pdev);
2966         if (rc) {
2967                 pr_err("Cannot enable PCI device\n");
2968                 goto err_out;
2969         }
2970
2971         using_dac = jme_pci_dma64(pdev);
2972         if (using_dac < 0) {
2973                 pr_err("Cannot set PCI DMA Mask\n");
2974                 rc = -EIO;
2975                 goto err_out_disable_pdev;
2976         }
2977
2978         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2979                 pr_err("No PCI resource region found\n");
2980                 rc = -ENOMEM;
2981                 goto err_out_disable_pdev;
2982         }
2983
2984         rc = pci_request_regions(pdev, DRV_NAME);
2985         if (rc) {
2986                 pr_err("Cannot obtain PCI resource region\n");
2987                 goto err_out_disable_pdev;
2988         }
2989
2990         pci_set_master(pdev);
2991
2992         /*
2993          * alloc and init net device
2994          */
2995         netdev = alloc_etherdev(sizeof(*jme));
2996         if (!netdev) {
2997                 pr_err("Cannot allocate netdev structure\n");
2998                 rc = -ENOMEM;
2999                 goto err_out_release_regions;
3000         }
3001         netdev->netdev_ops = &jme_netdev_ops;
3002         netdev->ethtool_ops             = &jme_ethtool_ops;
3003         netdev->watchdog_timeo          = TX_TIMEOUT;
3004         netdev->hw_features             =       NETIF_F_IP_CSUM |
3005                                                 NETIF_F_IPV6_CSUM |
3006                                                 NETIF_F_SG |
3007                                                 NETIF_F_TSO |
3008                                                 NETIF_F_TSO6 |
3009                                                 NETIF_F_RXCSUM;
3010         netdev->features                =       NETIF_F_IP_CSUM |
3011                                                 NETIF_F_IPV6_CSUM |
3012                                                 NETIF_F_SG |
3013                                                 NETIF_F_TSO |
3014                                                 NETIF_F_TSO6 |
3015                                                 NETIF_F_HW_VLAN_TX |
3016                                                 NETIF_F_HW_VLAN_RX;
3017         if (using_dac)
3018                 netdev->features        |=      NETIF_F_HIGHDMA;
3019
3020         SET_NETDEV_DEV(netdev, &pdev->dev);
3021         pci_set_drvdata(pdev, netdev);
3022
3023         /*
3024          * init adapter info
3025          */
3026         jme = netdev_priv(netdev);
3027         jme->pdev = pdev;
3028         jme->dev = netdev;
3029         jme->jme_rx = netif_rx;
3030         jme->old_mtu = netdev->mtu = 1500;
3031         jme->phylink = 0;
3032         jme->tx_ring_size = 1 << 10;
3033         jme->tx_ring_mask = jme->tx_ring_size - 1;
3034         jme->tx_wake_threshold = 1 << 9;
3035         jme->rx_ring_size = 1 << 9;
3036         jme->rx_ring_mask = jme->rx_ring_size - 1;
3037         jme->msg_enable = JME_DEF_MSG_ENABLE;
3038         jme->regs = ioremap(pci_resource_start(pdev, 0),
3039                              pci_resource_len(pdev, 0));
3040         if (!(jme->regs)) {
3041                 pr_err("Mapping PCI resource region error\n");
3042                 rc = -ENOMEM;
3043                 goto err_out_free_netdev;
3044         }
3045
3046         if (no_pseudohp) {
3047                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3048                 jwrite32(jme, JME_APMC, apmc);
3049         } else if (force_pseudohp) {
3050                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3051                 jwrite32(jme, JME_APMC, apmc);
3052         }
3053
3054         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3055
3056         spin_lock_init(&jme->phy_lock);
3057         spin_lock_init(&jme->macaddr_lock);
3058         spin_lock_init(&jme->rxmcs_lock);
3059
3060         atomic_set(&jme->link_changing, 1);
3061         atomic_set(&jme->rx_cleaning, 1);
3062         atomic_set(&jme->tx_cleaning, 1);
3063         atomic_set(&jme->rx_empty, 1);
3064
3065         tasklet_init(&jme->pcc_task,
3066                      jme_pcc_tasklet,
3067                      (unsigned long) jme);
3068         tasklet_init(&jme->linkch_task,
3069                      jme_link_change_tasklet,
3070                      (unsigned long) jme);
3071         tasklet_init(&jme->txclean_task,
3072                      jme_tx_clean_tasklet,
3073                      (unsigned long) jme);
3074         tasklet_init(&jme->rxclean_task,
3075                      jme_rx_clean_tasklet,
3076                      (unsigned long) jme);
3077         tasklet_init(&jme->rxempty_task,
3078                      jme_rx_empty_tasklet,
3079                      (unsigned long) jme);
3080         tasklet_disable_nosync(&jme->linkch_task);
3081         tasklet_disable_nosync(&jme->txclean_task);
3082         tasklet_disable_nosync(&jme->rxclean_task);
3083         tasklet_disable_nosync(&jme->rxempty_task);
3084         jme->dpi.cur = PCC_P1;
3085
3086         jme->reg_ghc = 0;
3087         jme->reg_rxcs = RXCS_DEFAULT;
3088         jme->reg_rxmcs = RXMCS_DEFAULT;
3089         jme->reg_txpfc = 0;
3090         jme->reg_pmcs = PMCS_MFEN;
3091         jme->reg_gpreg1 = GPREG1_DEFAULT;
3092
3093         if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3094                 netdev->features |= NETIF_F_RXCSUM;
3095
3096         /*
3097          * Get Max Read Req Size from PCI Config Space
3098          */
3099         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3100         jme->mrrs &= PCI_DCSR_MRRS_MASK;
3101         switch (jme->mrrs) {
3102         case MRRS_128B:
3103                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3104                 break;
3105         case MRRS_256B:
3106                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3107                 break;
3108         default:
3109                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3110                 break;
3111         }
3112
3113         /*
3114          * Must check before reset_mac_processor
3115          */
3116         jme_check_hw_ver(jme);
3117         jme->mii_if.dev = netdev;
3118         if (jme->fpgaver) {
3119                 jme->mii_if.phy_id = 0;
3120                 for (i = 1 ; i < 32 ; ++i) {
3121                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3122                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3123                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3124                                 jme->mii_if.phy_id = i;
3125                                 break;
3126                         }
3127                 }
3128
3129                 if (!jme->mii_if.phy_id) {
3130                         rc = -EIO;
3131                         pr_err("Can not find phy_id\n");
3132                         goto err_out_unmap;
3133                 }
3134
3135                 jme->reg_ghc |= GHC_LINK_POLL;
3136         } else {
3137                 jme->mii_if.phy_id = 1;
3138         }
3139         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3140                 jme->mii_if.supports_gmii = true;
3141         else
3142                 jme->mii_if.supports_gmii = false;
3143         jme->mii_if.phy_id_mask = 0x1F;
3144         jme->mii_if.reg_num_mask = 0x1F;
3145         jme->mii_if.mdio_read = jme_mdio_read;
3146         jme->mii_if.mdio_write = jme_mdio_write;
3147
3148         jme_clear_pm_disable_wol(jme);
3149         pci_set_power_state(jme->pdev, PCI_D0);
3150         device_init_wakeup(&pdev->dev, true);
3151
3152         jme_set_phyfifo_5level(jme);
3153         jme->pcirev = pdev->revision;
3154         if (!jme->fpgaver)
3155                 jme_phy_init(jme);
3156         jme_phy_off(jme);
3157
3158         /*
3159          * Reset MAC processor and reload EEPROM for MAC Address
3160          */
3161         jme_reset_mac_processor(jme);
3162         rc = jme_reload_eeprom(jme);
3163         if (rc) {
3164                 pr_err("Reload eeprom for reading MAC Address error\n");
3165                 goto err_out_unmap;
3166         }
3167         jme_load_macaddr(netdev);
3168
3169         /*
3170          * Tell stack that we are not ready to work until open()
3171          */
3172         netif_carrier_off(netdev);
3173
3174         rc = register_netdev(netdev);
3175         if (rc) {
3176                 pr_err("Cannot register net device\n");
3177                 goto err_out_unmap;
3178         }
3179
3180         netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3181                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3182                    "JMC250 Gigabit Ethernet" :
3183                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3184                    "JMC260 Fast Ethernet" : "Unknown",
3185                    (jme->fpgaver != 0) ? " (FPGA)" : "",
3186                    (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3187                    jme->pcirev, netdev->dev_addr);
3188
3189         return 0;
3190
3191 err_out_unmap:
3192         iounmap(jme->regs);
3193 err_out_free_netdev:
3194         pci_set_drvdata(pdev, NULL);
3195         free_netdev(netdev);
3196 err_out_release_regions:
3197         pci_release_regions(pdev);
3198 err_out_disable_pdev:
3199         pci_disable_device(pdev);
3200 err_out:
3201         return rc;
3202 }
3203
3204 static void __devexit
3205 jme_remove_one(struct pci_dev *pdev)
3206 {
3207         struct net_device *netdev = pci_get_drvdata(pdev);
3208         struct jme_adapter *jme = netdev_priv(netdev);
3209
3210         unregister_netdev(netdev);
3211         iounmap(jme->regs);
3212         pci_set_drvdata(pdev, NULL);
3213         free_netdev(netdev);
3214         pci_release_regions(pdev);
3215         pci_disable_device(pdev);
3216
3217 }
3218
3219 static void
3220 jme_shutdown(struct pci_dev *pdev)
3221 {
3222         struct net_device *netdev = pci_get_drvdata(pdev);
3223         struct jme_adapter *jme = netdev_priv(netdev);
3224
3225         jme_powersave_phy(jme);
3226         pci_pme_active(pdev, true);
3227 }
3228
3229 #ifdef CONFIG_PM_SLEEP
3230 static int
3231 jme_suspend(struct device *dev)
3232 {
3233         struct pci_dev *pdev = to_pci_dev(dev);
3234         struct net_device *netdev = pci_get_drvdata(pdev);
3235         struct jme_adapter *jme = netdev_priv(netdev);
3236
3237         if (!netif_running(netdev))
3238                 return 0;
3239
3240         atomic_dec(&jme->link_changing);
3241
3242         netif_device_detach(netdev);
3243         netif_stop_queue(netdev);
3244         jme_stop_irq(jme);
3245
3246         tasklet_disable(&jme->txclean_task);
3247         tasklet_disable(&jme->rxclean_task);
3248         tasklet_disable(&jme->rxempty_task);
3249
3250         if (netif_carrier_ok(netdev)) {
3251                 if (test_bit(JME_FLAG_POLL, &jme->flags))
3252                         jme_polling_mode(jme);
3253
3254                 jme_stop_pcc_timer(jme);
3255                 jme_disable_rx_engine(jme);
3256                 jme_disable_tx_engine(jme);
3257                 jme_reset_mac_processor(jme);
3258                 jme_free_rx_resources(jme);
3259                 jme_free_tx_resources(jme);
3260                 netif_carrier_off(netdev);
3261                 jme->phylink = 0;
3262         }
3263
3264         tasklet_enable(&jme->txclean_task);
3265         tasklet_hi_enable(&jme->rxclean_task);
3266         tasklet_hi_enable(&jme->rxempty_task);
3267
3268         jme_powersave_phy(jme);
3269
3270         return 0;
3271 }
3272
3273 static int
3274 jme_resume(struct device *dev)
3275 {
3276         struct pci_dev *pdev = to_pci_dev(dev);
3277         struct net_device *netdev = pci_get_drvdata(pdev);
3278         struct jme_adapter *jme = netdev_priv(netdev);
3279
3280         if (!netif_running(netdev))
3281                 return 0;
3282
3283         jme_clear_pm_disable_wol(jme);
3284         jme_phy_on(jme);
3285         if (test_bit(JME_FLAG_SSET, &jme->flags))
3286                 jme_set_settings(netdev, &jme->old_ecmd);
3287         else
3288                 jme_reset_phy_processor(jme);
3289         jme_phy_calibration(jme);
3290         jme_phy_setEA(jme);
3291         netif_device_attach(netdev);
3292
3293         atomic_inc(&jme->link_changing);
3294
3295         jme_reset_link(jme);
3296
3297         jme_start_irq(jme);
3298
3299         return 0;
3300 }
3301
3302 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3303 #define JME_PM_OPS (&jme_pm_ops)
3304
3305 #else
3306
3307 #define JME_PM_OPS NULL
3308 #endif
3309
3310 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3311         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3312         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3313         { }
3314 };
3315
3316 static struct pci_driver jme_driver = {
3317         .name           = DRV_NAME,
3318         .id_table       = jme_pci_tbl,
3319         .probe          = jme_init_one,
3320         .remove         = __devexit_p(jme_remove_one),
3321         .shutdown       = jme_shutdown,
3322         .driver.pm      = JME_PM_OPS,
3323 };
3324
3325 static int __init
3326 jme_init_module(void)
3327 {
3328         pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3329         return pci_register_driver(&jme_driver);
3330 }
3331
3332 static void __exit
3333 jme_cleanup_module(void)
3334 {
3335         pci_unregister_driver(&jme_driver);
3336 }
3337
3338 module_init(jme_init_module);
3339 module_exit(jme_cleanup_module);
3340
3341 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3342 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3343 MODULE_LICENSE("GPL");
3344 MODULE_VERSION(DRV_VERSION);
3345 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);