1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <scsi/fc/fc_fcoe.h>
51 #include "ixgbe_common.h"
52 #include "ixgbe_dcb_82599.h"
53 #include "ixgbe_sriov.h"
55 char ixgbe_driver_name[] = "ixgbe";
56 static const char ixgbe_driver_string[] =
57 "Intel(R) 10 Gigabit PCI Express Network Driver";
61 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
62 __stringify(BUILD) "-k"
63 const char ixgbe_driver_version[] = DRV_VERSION;
64 static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
73 /* ixgbe_pci_tbl - PCI Device ID Table
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
81 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
135 /* required last entry */
138 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
140 #ifdef CONFIG_IXGBE_DCA
141 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
143 static struct notifier_block dca_notifier = {
144 .notifier_call = ixgbe_notify_dca,
150 #ifdef CONFIG_PCI_IOV
151 static unsigned int max_vfs;
152 module_param(max_vfs, uint, 0);
153 MODULE_PARM_DESC(max_vfs,
154 "Maximum number of virtual functions to allocate per physical function");
155 #endif /* CONFIG_PCI_IOV */
157 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
158 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_VERSION);
162 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
164 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
166 struct ixgbe_hw *hw = &adapter->hw;
171 #ifdef CONFIG_PCI_IOV
172 /* disable iov and allow time for transactions to clear */
173 pci_disable_sriov(adapter->pdev);
176 /* turn off device IOV mode */
177 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
178 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
179 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
180 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
181 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
182 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
184 /* set default pool back to 0 */
185 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
186 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
187 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
188 IXGBE_WRITE_FLUSH(hw);
190 /* take a breather then clean up driver data */
193 kfree(adapter->vfinfo);
194 adapter->vfinfo = NULL;
196 adapter->num_vfs = 0;
197 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
200 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
202 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
203 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
204 schedule_work(&adapter->service_task);
207 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
209 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
211 /* flush memory to make sure state is correct before next watchog */
212 smp_mb__before_clear_bit();
213 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
216 struct ixgbe_reg_info {
221 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
223 /* General Registers */
224 {IXGBE_CTRL, "CTRL"},
225 {IXGBE_STATUS, "STATUS"},
226 {IXGBE_CTRL_EXT, "CTRL_EXT"},
228 /* Interrupt Registers */
229 {IXGBE_EICR, "EICR"},
232 {IXGBE_SRRCTL(0), "SRRCTL"},
233 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
234 {IXGBE_RDLEN(0), "RDLEN"},
235 {IXGBE_RDH(0), "RDH"},
236 {IXGBE_RDT(0), "RDT"},
237 {IXGBE_RXDCTL(0), "RXDCTL"},
238 {IXGBE_RDBAL(0), "RDBAL"},
239 {IXGBE_RDBAH(0), "RDBAH"},
242 {IXGBE_TDBAL(0), "TDBAL"},
243 {IXGBE_TDBAH(0), "TDBAH"},
244 {IXGBE_TDLEN(0), "TDLEN"},
245 {IXGBE_TDH(0), "TDH"},
246 {IXGBE_TDT(0), "TDT"},
247 {IXGBE_TXDCTL(0), "TXDCTL"},
249 /* List Terminator */
255 * ixgbe_regdump - register printout routine
257 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
263 switch (reginfo->ofs) {
264 case IXGBE_SRRCTL(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
268 case IXGBE_DCA_RXCTRL(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
284 case IXGBE_RXDCTL(0):
285 for (i = 0; i < 64; i++)
286 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
289 for (i = 0; i < 64; i++)
290 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
293 for (i = 0; i < 64; i++)
294 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
297 for (i = 0; i < 64; i++)
298 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
301 for (i = 0; i < 64; i++)
302 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
305 for (i = 0; i < 64; i++)
306 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
309 for (i = 0; i < 64; i++)
310 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
313 for (i = 0; i < 64; i++)
314 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
316 case IXGBE_TXDCTL(0):
317 for (i = 0; i < 64; i++)
318 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
321 pr_info("%-15s %08x\n", reginfo->name,
322 IXGBE_READ_REG(hw, reginfo->ofs));
326 for (i = 0; i < 8; i++) {
327 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
328 pr_err("%-15s", rname);
329 for (j = 0; j < 8; j++)
330 pr_cont(" %08x", regs[i*8+j]);
337 * ixgbe_dump - Print registers, tx-rings and rx-rings
339 static void ixgbe_dump(struct ixgbe_adapter *adapter)
341 struct net_device *netdev = adapter->netdev;
342 struct ixgbe_hw *hw = &adapter->hw;
343 struct ixgbe_reg_info *reginfo;
345 struct ixgbe_ring *tx_ring;
346 struct ixgbe_tx_buffer *tx_buffer_info;
347 union ixgbe_adv_tx_desc *tx_desc;
348 struct my_u0 { u64 a; u64 b; } *u0;
349 struct ixgbe_ring *rx_ring;
350 union ixgbe_adv_rx_desc *rx_desc;
351 struct ixgbe_rx_buffer *rx_buffer_info;
355 if (!netif_msg_hw(adapter))
358 /* Print netdevice Info */
360 dev_info(&adapter->pdev->dev, "Net device Info\n");
361 pr_info("Device Name state "
362 "trans_start last_rx\n");
363 pr_info("%-15s %016lX %016lX %016lX\n",
370 /* Print Registers */
371 dev_info(&adapter->pdev->dev, "Register Dump\n");
372 pr_info(" Register Name Value\n");
373 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
374 reginfo->name; reginfo++) {
375 ixgbe_regdump(hw, reginfo);
378 /* Print TX Ring Summary */
379 if (!netdev || !netif_running(netdev))
382 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
383 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
384 for (n = 0; n < adapter->num_tx_queues; n++) {
385 tx_ring = adapter->tx_ring[n];
387 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
388 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
389 n, tx_ring->next_to_use, tx_ring->next_to_clean,
390 (u64)tx_buffer_info->dma,
391 tx_buffer_info->length,
392 tx_buffer_info->next_to_watch,
393 (u64)tx_buffer_info->time_stamp);
397 if (!netif_msg_tx_done(adapter))
398 goto rx_ring_summary;
400 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
402 /* Transmit Descriptor Formats
404 * Advanced Transmit Descriptor
405 * +--------------------------------------------------------------+
406 * 0 | Buffer Address [63:0] |
407 * +--------------------------------------------------------------+
408 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
409 * +--------------------------------------------------------------+
410 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
413 for (n = 0; n < adapter->num_tx_queues; n++) {
414 tx_ring = adapter->tx_ring[n];
415 pr_info("------------------------------------\n");
416 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
417 pr_info("------------------------------------\n");
418 pr_info("T [desc] [address 63:0 ] "
419 "[PlPOIdStDDt Ln] [bi->dma ] "
420 "leng ntw timestamp bi->skb\n");
422 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
423 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
424 tx_buffer_info = &tx_ring->tx_buffer_info[i];
425 u0 = (struct my_u0 *)tx_desc;
426 pr_info("T [0x%03X] %016llX %016llX %016llX"
427 " %04X %p %016llX %p", i,
430 (u64)tx_buffer_info->dma,
431 tx_buffer_info->length,
432 tx_buffer_info->next_to_watch,
433 (u64)tx_buffer_info->time_stamp,
434 tx_buffer_info->skb);
435 if (i == tx_ring->next_to_use &&
436 i == tx_ring->next_to_clean)
438 else if (i == tx_ring->next_to_use)
440 else if (i == tx_ring->next_to_clean)
445 if (netif_msg_pktdata(adapter) &&
446 tx_buffer_info->dma != 0)
447 print_hex_dump(KERN_INFO, "",
448 DUMP_PREFIX_ADDRESS, 16, 1,
449 phys_to_virt(tx_buffer_info->dma),
450 tx_buffer_info->length, true);
454 /* Print RX Rings Summary */
456 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
457 pr_info("Queue [NTU] [NTC]\n");
458 for (n = 0; n < adapter->num_rx_queues; n++) {
459 rx_ring = adapter->rx_ring[n];
460 pr_info("%5d %5X %5X\n",
461 n, rx_ring->next_to_use, rx_ring->next_to_clean);
465 if (!netif_msg_rx_status(adapter))
468 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
470 /* Advanced Receive Descriptor (Read) Format
472 * +-----------------------------------------------------+
473 * 0 | Packet Buffer Address [63:1] |A0/NSE|
474 * +----------------------------------------------+------+
475 * 8 | Header Buffer Address [63:1] | DD |
476 * +-----------------------------------------------------+
479 * Advanced Receive Descriptor (Write-Back) Format
481 * 63 48 47 32 31 30 21 20 16 15 4 3 0
482 * +------------------------------------------------------+
483 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
484 * | Checksum Ident | | | | Type | Type |
485 * +------------------------------------------------------+
486 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
487 * +------------------------------------------------------+
488 * 63 48 47 32 31 20 19 0
490 for (n = 0; n < adapter->num_rx_queues; n++) {
491 rx_ring = adapter->rx_ring[n];
492 pr_info("------------------------------------\n");
493 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
494 pr_info("------------------------------------\n");
495 pr_info("R [desc] [ PktBuf A0] "
496 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
497 "<-- Adv Rx Read format\n");
498 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
499 "[vl er S cks ln] ---------------- [bi->skb] "
500 "<-- Adv Rx Write-Back format\n");
502 for (i = 0; i < rx_ring->count; i++) {
503 rx_buffer_info = &rx_ring->rx_buffer_info[i];
504 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
505 u0 = (struct my_u0 *)rx_desc;
506 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
507 if (staterr & IXGBE_RXD_STAT_DD) {
508 /* Descriptor Done */
509 pr_info("RWB[0x%03X] %016llX "
510 "%016llX ---------------- %p", i,
513 rx_buffer_info->skb);
515 pr_info("R [0x%03X] %016llX "
516 "%016llX %016llX %p", i,
519 (u64)rx_buffer_info->dma,
520 rx_buffer_info->skb);
522 if (netif_msg_pktdata(adapter)) {
523 print_hex_dump(KERN_INFO, "",
524 DUMP_PREFIX_ADDRESS, 16, 1,
525 phys_to_virt(rx_buffer_info->dma),
526 rx_ring->rx_buf_len, true);
528 if (rx_ring->rx_buf_len
529 < IXGBE_RXBUFFER_2048)
530 print_hex_dump(KERN_INFO, "",
531 DUMP_PREFIX_ADDRESS, 16, 1,
533 rx_buffer_info->page_dma +
534 rx_buffer_info->page_offset
540 if (i == rx_ring->next_to_use)
542 else if (i == rx_ring->next_to_clean)
554 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
558 /* Let firmware take over control of h/w */
559 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
561 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
564 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
568 /* Let firmware know the driver has taken over */
569 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
571 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
575 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
576 * @adapter: pointer to adapter struct
577 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
578 * @queue: queue to map the corresponding interrupt to
579 * @msix_vector: the vector to map to the corresponding queue
582 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
583 u8 queue, u8 msix_vector)
586 struct ixgbe_hw *hw = &adapter->hw;
587 switch (hw->mac.type) {
588 case ixgbe_mac_82598EB:
589 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
592 index = (((direction * 64) + queue) >> 2) & 0x1F;
593 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
594 ivar &= ~(0xFF << (8 * (queue & 0x3)));
595 ivar |= (msix_vector << (8 * (queue & 0x3)));
596 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
598 case ixgbe_mac_82599EB:
600 if (direction == -1) {
602 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
603 index = ((queue & 1) * 8);
604 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
605 ivar &= ~(0xFF << index);
606 ivar |= (msix_vector << index);
607 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
610 /* tx or rx causes */
611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
612 index = ((16 * (queue & 1)) + (8 * direction));
613 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
614 ivar &= ~(0xFF << index);
615 ivar |= (msix_vector << index);
616 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
624 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
629 switch (adapter->hw.mac.type) {
630 case ixgbe_mac_82598EB:
631 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
634 case ixgbe_mac_82599EB:
636 mask = (qmask & 0xFFFFFFFF);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
638 mask = (qmask >> 32);
639 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
646 static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
647 struct ixgbe_tx_buffer *tx_buffer)
649 if (tx_buffer->dma) {
650 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
651 dma_unmap_page(ring->dev,
656 dma_unmap_single(ring->dev,
664 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
665 struct ixgbe_tx_buffer *tx_buffer_info)
667 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
668 if (tx_buffer_info->skb)
669 dev_kfree_skb_any(tx_buffer_info->skb);
670 tx_buffer_info->skb = NULL;
671 /* tx_buffer_info must be completely set up in the transmit path */
674 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
676 struct ixgbe_hw *hw = &adapter->hw;
677 struct ixgbe_hw_stats *hwstats = &adapter->stats;
682 if ((hw->fc.current_mode == ixgbe_fc_full) ||
683 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
684 switch (hw->mac.type) {
685 case ixgbe_mac_82598EB:
686 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
689 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
691 hwstats->lxoffrxc += data;
693 /* refill credits (no tx hang) if we received xoff */
697 for (i = 0; i < adapter->num_tx_queues; i++)
698 clear_bit(__IXGBE_HANG_CHECK_ARMED,
699 &adapter->tx_ring[i]->state);
701 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
704 /* update stats for each tc, only valid with PFC enabled */
705 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
706 switch (hw->mac.type) {
707 case ixgbe_mac_82598EB:
708 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
711 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
713 hwstats->pxoffrxc[i] += xoff[i];
716 /* disarm tx queues that have received xoff frames */
717 for (i = 0; i < adapter->num_tx_queues; i++) {
718 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
719 u8 tc = tx_ring->dcb_tc;
722 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
726 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
728 return ring->tx_stats.completed;
731 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
733 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
734 struct ixgbe_hw *hw = &adapter->hw;
736 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
737 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
740 return (head < tail) ?
741 tail - head : (tail + ring->count - head);
746 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
748 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
749 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
750 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
753 clear_check_for_tx_hang(tx_ring);
756 * Check for a hung queue, but be thorough. This verifies
757 * that a transmit has been completed since the previous
758 * check AND there is at least one packet pending. The
759 * ARMED bit is set to indicate a potential hang. The
760 * bit is cleared if a pause frame is received to remove
761 * false hang detection due to PFC or 802.3x frames. By
762 * requiring this to fail twice we avoid races with
763 * pfc clearing the ARMED bit and conditions where we
764 * run the check_tx_hang logic with a transmit completion
765 * pending but without time to complete it yet.
767 if ((tx_done_old == tx_done) && tx_pending) {
768 /* make sure it is true for two checks in a row */
769 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
772 /* update completed stats and continue */
773 tx_ring->tx_stats.tx_done_old = tx_done;
774 /* reset the countdown */
775 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
782 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
783 * @adapter: driver private struct
785 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
788 /* Do the reset outside of interrupt context */
789 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
790 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
791 ixgbe_service_event_schedule(adapter);
796 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
797 * @q_vector: structure containing interrupt and ring information
798 * @tx_ring: tx ring to clean
800 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
801 struct ixgbe_ring *tx_ring)
803 struct ixgbe_adapter *adapter = q_vector->adapter;
804 struct ixgbe_tx_buffer *tx_buffer;
805 union ixgbe_adv_tx_desc *tx_desc;
806 unsigned int total_bytes = 0, total_packets = 0;
807 u16 i = tx_ring->next_to_clean;
810 tx_buffer = &tx_ring->tx_buffer_info[i];
811 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
813 for (count = 0; count < q_vector->tx.work_limit; count++) {
814 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
816 /* if next_to_watch is not set then there is no work pending */
820 /* if DD is not set pending work has not been completed */
821 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
824 /* count the packet as being completed */
825 tx_ring->tx_stats.completed++;
827 /* clear next_to_watch to prevent false hangs */
828 tx_buffer->next_to_watch = NULL;
830 /* prevent any other reads prior to eop_desc being verified */
834 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
835 tx_desc->wb.status = 0;
836 if (likely(tx_desc == eop_desc)) {
838 dev_kfree_skb_any(tx_buffer->skb);
839 tx_buffer->skb = NULL;
841 total_bytes += tx_buffer->bytecount;
842 total_packets += tx_buffer->gso_segs;
848 if (unlikely(i == tx_ring->count)) {
851 tx_buffer = tx_ring->tx_buffer_info;
852 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
858 tx_ring->next_to_clean = i;
859 u64_stats_update_begin(&tx_ring->syncp);
860 tx_ring->stats.bytes += total_bytes;
861 tx_ring->stats.packets += total_packets;
862 u64_stats_update_end(&tx_ring->syncp);
863 q_vector->tx.total_bytes += total_bytes;
864 q_vector->tx.total_packets += total_packets;
866 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
867 /* schedule immediate reset if we believe we hung */
868 struct ixgbe_hw *hw = &adapter->hw;
869 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
870 e_err(drv, "Detected Tx Unit Hang\n"
872 " TDH, TDT <%x>, <%x>\n"
873 " next_to_use <%x>\n"
874 " next_to_clean <%x>\n"
875 "tx_buffer_info[next_to_clean]\n"
876 " time_stamp <%lx>\n"
878 tx_ring->queue_index,
879 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
880 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
881 tx_ring->next_to_use, i,
882 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
884 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
887 "tx hang %d detected on queue %d, resetting adapter\n",
888 adapter->tx_timeout_count + 1, tx_ring->queue_index);
890 /* schedule immediate reset if we believe we hung */
891 ixgbe_tx_timeout_reset(adapter);
893 /* the adapter is about to reset, no point in enabling stuff */
897 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
898 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
899 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
900 /* Make sure that anybody stopping the queue after this
901 * sees the new next_to_clean.
904 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
905 !test_bit(__IXGBE_DOWN, &adapter->state)) {
906 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
907 ++tx_ring->tx_stats.restart_queue;
911 return count < q_vector->tx.work_limit;
914 #ifdef CONFIG_IXGBE_DCA
915 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
916 struct ixgbe_ring *rx_ring,
919 struct ixgbe_hw *hw = &adapter->hw;
921 u8 reg_idx = rx_ring->reg_idx;
923 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
924 switch (hw->mac.type) {
925 case ixgbe_mac_82598EB:
926 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
927 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
929 case ixgbe_mac_82599EB:
931 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
932 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
933 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
938 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
939 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
940 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
941 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
944 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
945 struct ixgbe_ring *tx_ring,
948 struct ixgbe_hw *hw = &adapter->hw;
950 u8 reg_idx = tx_ring->reg_idx;
952 switch (hw->mac.type) {
953 case ixgbe_mac_82598EB:
954 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
955 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
956 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
957 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
958 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
960 case ixgbe_mac_82599EB:
962 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
963 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
964 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
965 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
966 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
967 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
974 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
976 struct ixgbe_adapter *adapter = q_vector->adapter;
981 if (q_vector->cpu == cpu)
984 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
985 for (i = 0; i < q_vector->tx.count; i++) {
986 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
987 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
991 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
992 for (i = 0; i < q_vector->rx.count; i++) {
993 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
994 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
1003 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1008 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1011 /* always use CB2 mode, difference is masked in the CB driver */
1012 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1014 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1015 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1019 for (i = 0; i < num_q_vectors; i++) {
1020 adapter->q_vector[i]->cpu = -1;
1021 ixgbe_update_dca(adapter->q_vector[i]);
1025 static int __ixgbe_notify_dca(struct device *dev, void *data)
1027 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1028 unsigned long event = *(unsigned long *)data;
1030 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1034 case DCA_PROVIDER_ADD:
1035 /* if we're already enabled, don't do it again */
1036 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1038 if (dca_add_requester(dev) == 0) {
1039 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1040 ixgbe_setup_dca(adapter);
1043 /* Fall Through since DCA is disabled. */
1044 case DCA_PROVIDER_REMOVE:
1045 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1046 dca_remove_requester(dev);
1047 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1048 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1055 #endif /* CONFIG_IXGBE_DCA */
1057 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1058 struct sk_buff *skb)
1060 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1064 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1065 * @adapter: address of board private structure
1066 * @rx_desc: advanced rx descriptor
1068 * Returns : true if it is FCoE pkt
1070 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1071 union ixgbe_adv_rx_desc *rx_desc)
1073 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1075 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1076 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1077 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1078 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1082 * ixgbe_receive_skb - Send a completed packet up the stack
1083 * @adapter: board private structure
1084 * @skb: packet to send up
1085 * @status: hardware indication of status of receive
1086 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1087 * @rx_desc: rx descriptor
1089 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1090 struct sk_buff *skb, u8 status,
1091 struct ixgbe_ring *ring,
1092 union ixgbe_adv_rx_desc *rx_desc)
1094 struct ixgbe_adapter *adapter = q_vector->adapter;
1095 struct napi_struct *napi = &q_vector->napi;
1096 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1097 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1099 if (is_vlan && (tag & VLAN_VID_MASK))
1100 __vlan_hwaccel_put_tag(skb, tag);
1102 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1103 napi_gro_receive(napi, skb);
1109 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1110 * @adapter: address of board private structure
1111 * @status_err: hardware indication of status of receive
1112 * @skb: skb currently being received and modified
1113 * @status_err: status error value of last descriptor in packet
1115 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1116 union ixgbe_adv_rx_desc *rx_desc,
1117 struct sk_buff *skb,
1120 skb->ip_summed = CHECKSUM_NONE;
1122 /* Rx csum disabled */
1123 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1126 /* if IP and error */
1127 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1128 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1129 adapter->hw_csum_rx_error++;
1133 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1136 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1137 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1140 * 82599 errata, UDP frames with a 0 checksum can be marked as
1143 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1144 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1147 adapter->hw_csum_rx_error++;
1151 /* It must be a TCP or UDP packet with a valid checksum */
1152 skb->ip_summed = CHECKSUM_UNNECESSARY;
1155 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1158 * Force memory writes to complete before letting h/w
1159 * know there are new descriptors to fetch. (Only
1160 * applicable for weak-ordered memory model archs,
1164 writel(val, rx_ring->tail);
1168 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1169 * @rx_ring: ring to place buffers on
1170 * @cleaned_count: number of buffers to replace
1172 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1174 union ixgbe_adv_rx_desc *rx_desc;
1175 struct ixgbe_rx_buffer *bi;
1176 struct sk_buff *skb;
1177 u16 i = rx_ring->next_to_use;
1179 /* do nothing if no valid netdev defined */
1180 if (!rx_ring->netdev)
1183 while (cleaned_count--) {
1184 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1185 bi = &rx_ring->rx_buffer_info[i];
1189 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1190 rx_ring->rx_buf_len);
1192 rx_ring->rx_stats.alloc_rx_buff_failed++;
1195 /* initialize queue mapping */
1196 skb_record_rx_queue(skb, rx_ring->queue_index);
1201 bi->dma = dma_map_single(rx_ring->dev,
1203 rx_ring->rx_buf_len,
1205 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1206 rx_ring->rx_stats.alloc_rx_buff_failed++;
1212 if (ring_is_ps_enabled(rx_ring)) {
1214 bi->page = netdev_alloc_page(rx_ring->netdev);
1216 rx_ring->rx_stats.alloc_rx_page_failed++;
1221 if (!bi->page_dma) {
1222 /* use a half page if we're re-using */
1223 bi->page_offset ^= PAGE_SIZE / 2;
1224 bi->page_dma = dma_map_page(rx_ring->dev,
1229 if (dma_mapping_error(rx_ring->dev,
1231 rx_ring->rx_stats.alloc_rx_page_failed++;
1237 /* Refresh the desc even if buffer_addrs didn't change
1238 * because each write-back erases this info. */
1239 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1240 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1242 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1243 rx_desc->read.hdr_addr = 0;
1247 if (i == rx_ring->count)
1252 if (rx_ring->next_to_use != i) {
1253 rx_ring->next_to_use = i;
1254 ixgbe_release_rx_desc(rx_ring, i);
1258 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1260 /* HW will not DMA in data larger than the given buffer, even if it
1261 * parses the (NFS, of course) header to be larger. In that case, it
1262 * fills the header buffer and spills the rest into the page.
1264 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1265 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1266 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1267 if (hlen > IXGBE_RX_HDR_SIZE)
1268 hlen = IXGBE_RX_HDR_SIZE;
1273 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1274 * @skb: pointer to the last skb in the rsc queue
1276 * This function changes a queue full of hw rsc buffers into a completed
1277 * packet. It uses the ->prev pointers to find the first packet and then
1278 * turns it into the frag list owner.
1280 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1282 unsigned int frag_list_size = 0;
1283 unsigned int skb_cnt = 1;
1286 struct sk_buff *prev = skb->prev;
1287 frag_list_size += skb->len;
1293 skb_shinfo(skb)->frag_list = skb->next;
1295 skb->len += frag_list_size;
1296 skb->data_len += frag_list_size;
1297 skb->truesize += frag_list_size;
1298 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1303 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1305 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1306 IXGBE_RXDADV_RSCCNT_MASK);
1309 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1310 struct ixgbe_ring *rx_ring,
1311 int *work_done, int work_to_do)
1313 struct ixgbe_adapter *adapter = q_vector->adapter;
1314 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1315 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1316 struct sk_buff *skb;
1317 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1318 const int current_node = numa_node_id();
1321 #endif /* IXGBE_FCOE */
1324 u16 cleaned_count = 0;
1325 bool pkt_is_rsc = false;
1327 i = rx_ring->next_to_clean;
1328 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1329 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1331 while (staterr & IXGBE_RXD_STAT_DD) {
1334 rmb(); /* read descriptor and rx_buffer_info after status DD */
1336 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1338 skb = rx_buffer_info->skb;
1339 rx_buffer_info->skb = NULL;
1340 prefetch(skb->data);
1342 if (ring_is_rsc_enabled(rx_ring))
1343 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1345 /* if this is a skb from previous receive DMA will be 0 */
1346 if (rx_buffer_info->dma) {
1349 !(staterr & IXGBE_RXD_STAT_EOP) &&
1352 * When HWRSC is enabled, delay unmapping
1353 * of the first packet. It carries the
1354 * header information, HW may still
1355 * access the header after the writeback.
1356 * Only unmap it when EOP is reached
1358 IXGBE_RSC_CB(skb)->delay_unmap = true;
1359 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1361 dma_unmap_single(rx_ring->dev,
1362 rx_buffer_info->dma,
1363 rx_ring->rx_buf_len,
1366 rx_buffer_info->dma = 0;
1368 if (ring_is_ps_enabled(rx_ring)) {
1369 hlen = ixgbe_get_hlen(rx_desc);
1370 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1372 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1377 /* assume packet split since header is unmapped */
1378 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1382 dma_unmap_page(rx_ring->dev,
1383 rx_buffer_info->page_dma,
1386 rx_buffer_info->page_dma = 0;
1387 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1388 rx_buffer_info->page,
1389 rx_buffer_info->page_offset,
1392 if ((page_count(rx_buffer_info->page) == 1) &&
1393 (page_to_nid(rx_buffer_info->page) == current_node))
1394 get_page(rx_buffer_info->page);
1396 rx_buffer_info->page = NULL;
1398 skb->len += upper_len;
1399 skb->data_len += upper_len;
1400 skb->truesize += upper_len;
1404 if (i == rx_ring->count)
1407 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1412 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1413 IXGBE_RXDADV_NEXTP_SHIFT;
1414 next_buffer = &rx_ring->rx_buffer_info[nextp];
1416 next_buffer = &rx_ring->rx_buffer_info[i];
1419 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1420 if (ring_is_ps_enabled(rx_ring)) {
1421 rx_buffer_info->skb = next_buffer->skb;
1422 rx_buffer_info->dma = next_buffer->dma;
1423 next_buffer->skb = skb;
1424 next_buffer->dma = 0;
1426 skb->next = next_buffer->skb;
1427 skb->next->prev = skb;
1429 rx_ring->rx_stats.non_eop_descs++;
1434 skb = ixgbe_transform_rsc_queue(skb);
1435 /* if we got here without RSC the packet is invalid */
1437 __pskb_trim(skb, 0);
1438 rx_buffer_info->skb = skb;
1443 if (ring_is_rsc_enabled(rx_ring)) {
1444 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1445 dma_unmap_single(rx_ring->dev,
1446 IXGBE_RSC_CB(skb)->dma,
1447 rx_ring->rx_buf_len,
1449 IXGBE_RSC_CB(skb)->dma = 0;
1450 IXGBE_RSC_CB(skb)->delay_unmap = false;
1454 if (ring_is_ps_enabled(rx_ring))
1455 rx_ring->rx_stats.rsc_count +=
1456 skb_shinfo(skb)->nr_frags;
1458 rx_ring->rx_stats.rsc_count +=
1459 IXGBE_RSC_CB(skb)->skb_cnt;
1460 rx_ring->rx_stats.rsc_flush++;
1463 /* ERR_MASK will only have valid bits if EOP set */
1464 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1465 dev_kfree_skb_any(skb);
1469 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
1470 if (adapter->netdev->features & NETIF_F_RXHASH)
1471 ixgbe_rx_hash(rx_desc, skb);
1473 /* probably a little skewed due to removing CRC */
1474 total_rx_bytes += skb->len;
1477 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1479 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1480 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1481 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1484 dev_kfree_skb_any(skb);
1488 #endif /* IXGBE_FCOE */
1489 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1492 rx_desc->wb.upper.status_error = 0;
1495 if (*work_done >= work_to_do)
1498 /* return some buffers to hardware, one at a time is too slow */
1499 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1500 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1504 /* use prefetched values */
1506 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1509 rx_ring->next_to_clean = i;
1510 cleaned_count = ixgbe_desc_unused(rx_ring);
1513 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1516 /* include DDPed FCoE data */
1517 if (ddp_bytes > 0) {
1520 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1521 sizeof(struct fc_frame_header) -
1522 sizeof(struct fcoe_crc_eof);
1525 total_rx_bytes += ddp_bytes;
1526 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1528 #endif /* IXGBE_FCOE */
1530 u64_stats_update_begin(&rx_ring->syncp);
1531 rx_ring->stats.packets += total_rx_packets;
1532 rx_ring->stats.bytes += total_rx_bytes;
1533 u64_stats_update_end(&rx_ring->syncp);
1534 q_vector->rx.total_packets += total_rx_packets;
1535 q_vector->rx.total_bytes += total_rx_bytes;
1538 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1540 * ixgbe_configure_msix - Configure MSI-X hardware
1541 * @adapter: board private structure
1543 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1546 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1548 struct ixgbe_q_vector *q_vector;
1549 int i, q_vectors, v_idx, r_idx;
1552 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1555 * Populate the IVAR table and set the ITR values to the
1556 * corresponding register.
1558 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1559 q_vector = adapter->q_vector[v_idx];
1560 /* XXX for_each_set_bit(...) */
1561 r_idx = find_first_bit(q_vector->rx.idx,
1562 adapter->num_rx_queues);
1564 for (i = 0; i < q_vector->rx.count; i++) {
1565 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1566 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1567 r_idx = find_next_bit(q_vector->rx.idx,
1568 adapter->num_rx_queues,
1571 r_idx = find_first_bit(q_vector->tx.idx,
1572 adapter->num_tx_queues);
1574 for (i = 0; i < q_vector->tx.count; i++) {
1575 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1576 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1577 r_idx = find_next_bit(q_vector->tx.idx,
1578 adapter->num_tx_queues,
1582 if (q_vector->tx.count && !q_vector->rx.count)
1584 q_vector->eitr = adapter->tx_eitr_param;
1585 else if (q_vector->rx.count)
1587 q_vector->eitr = adapter->rx_eitr_param;
1589 ixgbe_write_eitr(q_vector);
1590 /* If ATR is enabled, set interrupt affinity */
1591 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1593 * Allocate the affinity_hint cpumask, assign the mask
1594 * for this vector, and set our affinity_hint for
1597 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1600 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1601 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1602 q_vector->affinity_mask);
1606 switch (adapter->hw.mac.type) {
1607 case ixgbe_mac_82598EB:
1608 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1611 case ixgbe_mac_82599EB:
1612 case ixgbe_mac_X540:
1613 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1619 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1621 /* set up to autoclear timer, and the vectors */
1622 mask = IXGBE_EIMS_ENABLE_MASK;
1623 if (adapter->num_vfs)
1624 mask &= ~(IXGBE_EIMS_OTHER |
1625 IXGBE_EIMS_MAILBOX |
1628 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1629 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1632 enum latency_range {
1636 latency_invalid = 255
1640 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1641 * @q_vector: structure containing interrupt and ring information
1642 * @ring_container: structure containing ring performance data
1644 * Stores a new ITR value based on packets and byte
1645 * counts during the last interrupt. The advantage of per interrupt
1646 * computation is faster updates and more accurate ITR for the current
1647 * traffic pattern. Constants in this function were computed
1648 * based on theoretical maximum wire speed and thresholds were set based
1649 * on testing data as well as attempting to minimize response time
1650 * while increasing bulk throughput.
1651 * this functionality is controlled by the InterruptThrottleRate module
1652 * parameter (see ixgbe_param.c)
1654 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1655 struct ixgbe_ring_container *ring_container)
1658 struct ixgbe_adapter *adapter = q_vector->adapter;
1659 int bytes = ring_container->total_bytes;
1660 int packets = ring_container->total_packets;
1662 u8 itr_setting = ring_container->itr;
1667 /* simple throttlerate management
1668 * 0-20MB/s lowest (100000 ints/s)
1669 * 20-100MB/s low (20000 ints/s)
1670 * 100-1249MB/s bulk (8000 ints/s)
1672 /* what was last interrupt timeslice? */
1673 timepassed_us = 1000000/q_vector->eitr;
1674 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1676 switch (itr_setting) {
1677 case lowest_latency:
1678 if (bytes_perint > adapter->eitr_low)
1679 itr_setting = low_latency;
1682 if (bytes_perint > adapter->eitr_high)
1683 itr_setting = bulk_latency;
1684 else if (bytes_perint <= adapter->eitr_low)
1685 itr_setting = lowest_latency;
1688 if (bytes_perint <= adapter->eitr_high)
1689 itr_setting = low_latency;
1693 /* clear work counters since we have the values we need */
1694 ring_container->total_bytes = 0;
1695 ring_container->total_packets = 0;
1697 /* write updated itr to ring container */
1698 ring_container->itr = itr_setting;
1702 * ixgbe_write_eitr - write EITR register in hardware specific way
1703 * @q_vector: structure containing interrupt and ring information
1705 * This function is made to be called by ethtool and by the driver
1706 * when it needs to update EITR registers at runtime. Hardware
1707 * specific quirks/differences are taken care of here.
1709 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1711 struct ixgbe_adapter *adapter = q_vector->adapter;
1712 struct ixgbe_hw *hw = &adapter->hw;
1713 int v_idx = q_vector->v_idx;
1714 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1716 switch (adapter->hw.mac.type) {
1717 case ixgbe_mac_82598EB:
1718 /* must write high and low 16 bits to reset counter */
1719 itr_reg |= (itr_reg << 16);
1721 case ixgbe_mac_82599EB:
1722 case ixgbe_mac_X540:
1724 * 82599 and X540 can support a value of zero, so allow it for
1725 * max interrupt rate, but there is an errata where it can
1726 * not be zero with RSC
1729 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1733 * set the WDIS bit to not clear the timer bits and cause an
1734 * immediate assertion of the interrupt
1736 itr_reg |= IXGBE_EITR_CNT_WDIS;
1741 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1744 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
1746 u32 new_itr = q_vector->eitr;
1749 ixgbe_update_itr(q_vector, &q_vector->tx);
1750 ixgbe_update_itr(q_vector, &q_vector->rx);
1752 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1754 switch (current_itr) {
1755 /* counts and packets in update_itr are dependent on these numbers */
1756 case lowest_latency:
1760 new_itr = 20000; /* aka hwitr = ~200 */
1769 if (new_itr != q_vector->eitr) {
1770 /* do an exponential smoothing */
1771 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1773 /* save the algorithm value here */
1774 q_vector->eitr = new_itr;
1776 ixgbe_write_eitr(q_vector);
1781 * ixgbe_check_overtemp_subtask - check for over tempurature
1782 * @adapter: pointer to adapter
1784 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1786 struct ixgbe_hw *hw = &adapter->hw;
1787 u32 eicr = adapter->interrupt_event;
1789 if (test_bit(__IXGBE_DOWN, &adapter->state))
1792 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1793 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1796 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1798 switch (hw->device_id) {
1799 case IXGBE_DEV_ID_82599_T3_LOM:
1801 * Since the warning interrupt is for both ports
1802 * we don't have to check if:
1803 * - This interrupt wasn't for our port.
1804 * - We may have missed the interrupt so always have to
1805 * check if we got a LSC
1807 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1808 !(eicr & IXGBE_EICR_LSC))
1811 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1813 bool link_up = false;
1815 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1821 /* Check if this is not due to overtemp */
1822 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1827 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1832 "Network adapter has been stopped because it has over heated. "
1833 "Restart the computer. If the problem persists, "
1834 "power off the system and replace the adapter\n");
1836 adapter->interrupt_event = 0;
1839 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1841 struct ixgbe_hw *hw = &adapter->hw;
1843 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1844 (eicr & IXGBE_EICR_GPI_SDP1)) {
1845 e_crit(probe, "Fan has stopped, replace the adapter\n");
1846 /* write to clear the interrupt */
1847 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1851 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1853 struct ixgbe_hw *hw = &adapter->hw;
1855 if (eicr & IXGBE_EICR_GPI_SDP2) {
1856 /* Clear the interrupt */
1857 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1858 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1859 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1860 ixgbe_service_event_schedule(adapter);
1864 if (eicr & IXGBE_EICR_GPI_SDP1) {
1865 /* Clear the interrupt */
1866 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1867 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1868 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1869 ixgbe_service_event_schedule(adapter);
1874 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1876 struct ixgbe_hw *hw = &adapter->hw;
1879 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1880 adapter->link_check_timeout = jiffies;
1881 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1882 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1883 IXGBE_WRITE_FLUSH(hw);
1884 ixgbe_service_event_schedule(adapter);
1888 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1890 struct ixgbe_adapter *adapter = data;
1891 struct ixgbe_hw *hw = &adapter->hw;
1895 * Workaround for Silicon errata. Use clear-by-write instead
1896 * of clear-by-read. Reading with EICS will return the
1897 * interrupt causes without clearing, which later be done
1898 * with the write to EICR.
1900 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1901 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1903 if (eicr & IXGBE_EICR_LSC)
1904 ixgbe_check_lsc(adapter);
1906 if (eicr & IXGBE_EICR_MAILBOX)
1907 ixgbe_msg_task(adapter);
1909 switch (hw->mac.type) {
1910 case ixgbe_mac_82599EB:
1911 case ixgbe_mac_X540:
1912 /* Handle Flow Director Full threshold interrupt */
1913 if (eicr & IXGBE_EICR_FLOW_DIR) {
1914 int reinit_count = 0;
1916 for (i = 0; i < adapter->num_tx_queues; i++) {
1917 struct ixgbe_ring *ring = adapter->tx_ring[i];
1918 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1923 /* no more flow director interrupts until after init */
1924 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1925 eicr &= ~IXGBE_EICR_FLOW_DIR;
1926 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1927 ixgbe_service_event_schedule(adapter);
1930 ixgbe_check_sfp_event(adapter, eicr);
1931 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1932 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1933 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1934 adapter->interrupt_event = eicr;
1935 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1936 ixgbe_service_event_schedule(adapter);
1944 ixgbe_check_fan_failure(adapter, eicr);
1946 /* re-enable the original interrupt state, no lsc, no queues */
1947 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1948 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1949 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1954 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1958 struct ixgbe_hw *hw = &adapter->hw;
1960 switch (hw->mac.type) {
1961 case ixgbe_mac_82598EB:
1962 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1963 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1965 case ixgbe_mac_82599EB:
1966 case ixgbe_mac_X540:
1967 mask = (qmask & 0xFFFFFFFF);
1969 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1970 mask = (qmask >> 32);
1972 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1977 /* skip the flush */
1980 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1984 struct ixgbe_hw *hw = &adapter->hw;
1986 switch (hw->mac.type) {
1987 case ixgbe_mac_82598EB:
1988 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1989 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1991 case ixgbe_mac_82599EB:
1992 case ixgbe_mac_X540:
1993 mask = (qmask & 0xFFFFFFFF);
1995 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1996 mask = (qmask >> 32);
1998 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2003 /* skip the flush */
2006 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2008 struct ixgbe_q_vector *q_vector = data;
2009 struct ixgbe_adapter *adapter = q_vector->adapter;
2010 struct ixgbe_ring *tx_ring;
2013 if (!q_vector->tx.count)
2016 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2017 for (i = 0; i < q_vector->tx.count; i++) {
2018 tx_ring = adapter->tx_ring[r_idx];
2019 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2023 /* EIAM disabled interrupts (on this vector) for us */
2024 napi_schedule(&q_vector->napi);
2030 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2032 * @data: pointer to our q_vector struct for this interrupt vector
2034 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2036 struct ixgbe_q_vector *q_vector = data;
2037 struct ixgbe_adapter *adapter = q_vector->adapter;
2038 struct ixgbe_ring *rx_ring;
2042 #ifdef CONFIG_IXGBE_DCA
2043 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2044 ixgbe_update_dca(q_vector);
2047 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2048 for (i = 0; i < q_vector->rx.count; i++) {
2049 rx_ring = adapter->rx_ring[r_idx];
2050 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2054 if (!q_vector->rx.count)
2057 /* EIAM disabled interrupts (on this vector) for us */
2058 napi_schedule(&q_vector->napi);
2063 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2065 struct ixgbe_q_vector *q_vector = data;
2066 struct ixgbe_adapter *adapter = q_vector->adapter;
2067 struct ixgbe_ring *ring;
2071 if (!q_vector->tx.count && !q_vector->rx.count)
2074 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2075 for (i = 0; i < q_vector->tx.count; i++) {
2076 ring = adapter->tx_ring[r_idx];
2077 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2081 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2082 for (i = 0; i < q_vector->rx.count; i++) {
2083 ring = adapter->rx_ring[r_idx];
2084 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2088 /* EIAM disabled interrupts (on this vector) for us */
2089 napi_schedule(&q_vector->napi);
2095 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2096 * @napi: napi struct with our devices info in it
2097 * @budget: amount of work driver is allowed to do this pass, in packets
2099 * This function is optimized for cleaning one queue only on a single
2102 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2104 struct ixgbe_q_vector *q_vector =
2105 container_of(napi, struct ixgbe_q_vector, napi);
2106 struct ixgbe_adapter *adapter = q_vector->adapter;
2107 struct ixgbe_ring *rx_ring = NULL;
2111 #ifdef CONFIG_IXGBE_DCA
2112 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2113 ixgbe_update_dca(q_vector);
2116 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2117 rx_ring = adapter->rx_ring[r_idx];
2119 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2121 /* If all Rx work done, exit the polling mode */
2122 if (work_done < budget) {
2123 napi_complete(napi);
2124 if (adapter->rx_itr_setting & 1)
2125 ixgbe_set_itr(q_vector);
2126 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2127 ixgbe_irq_enable_queues(adapter,
2128 ((u64)1 << q_vector->v_idx));
2135 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2136 * @napi: napi struct with our devices info in it
2137 * @budget: amount of work driver is allowed to do this pass, in packets
2139 * This function will clean more than one rx queue associated with a
2142 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2144 struct ixgbe_q_vector *q_vector =
2145 container_of(napi, struct ixgbe_q_vector, napi);
2146 struct ixgbe_adapter *adapter = q_vector->adapter;
2147 struct ixgbe_ring *ring = NULL;
2148 int work_done = 0, i;
2150 bool tx_clean_complete = true;
2152 #ifdef CONFIG_IXGBE_DCA
2153 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2154 ixgbe_update_dca(q_vector);
2157 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2158 for (i = 0; i < q_vector->tx.count; i++) {
2159 ring = adapter->tx_ring[r_idx];
2160 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2161 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2165 /* attempt to distribute budget to each queue fairly, but don't allow
2166 * the budget to go below 1 because we'll exit polling */
2167 budget /= (q_vector->rx.count ?: 1);
2168 budget = max(budget, 1);
2169 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2170 for (i = 0; i < q_vector->rx.count; i++) {
2171 ring = adapter->rx_ring[r_idx];
2172 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2173 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2177 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2178 ring = adapter->rx_ring[r_idx];
2179 /* If all Rx work done, exit the polling mode */
2180 if (work_done < budget) {
2181 napi_complete(napi);
2182 if (adapter->rx_itr_setting & 1)
2183 ixgbe_set_itr(q_vector);
2184 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2185 ixgbe_irq_enable_queues(adapter,
2186 ((u64)1 << q_vector->v_idx));
2194 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2195 * @napi: napi struct with our devices info in it
2196 * @budget: amount of work driver is allowed to do this pass, in packets
2198 * This function is optimized for cleaning one queue only on a single
2201 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2203 struct ixgbe_q_vector *q_vector =
2204 container_of(napi, struct ixgbe_q_vector, napi);
2205 struct ixgbe_adapter *adapter = q_vector->adapter;
2206 struct ixgbe_ring *tx_ring = NULL;
2210 #ifdef CONFIG_IXGBE_DCA
2211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2212 ixgbe_update_dca(q_vector);
2215 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2216 tx_ring = adapter->tx_ring[r_idx];
2218 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2221 /* If all Tx work done, exit the polling mode */
2222 if (work_done < budget) {
2223 napi_complete(napi);
2224 if (adapter->tx_itr_setting & 1)
2225 ixgbe_set_itr(q_vector);
2226 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2227 ixgbe_irq_enable_queues(adapter,
2228 ((u64)1 << q_vector->v_idx));
2234 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2237 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2238 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2240 set_bit(r_idx, q_vector->rx.idx);
2241 q_vector->rx.count++;
2242 rx_ring->q_vector = q_vector;
2245 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2248 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2249 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2251 set_bit(t_idx, q_vector->tx.idx);
2252 q_vector->tx.count++;
2253 tx_ring->q_vector = q_vector;
2254 q_vector->tx.work_limit = a->tx_work_limit;
2258 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2259 * @adapter: board private structure to initialize
2261 * This function maps descriptor rings to the queue-specific vectors
2262 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2263 * one vector per ring/queue, but on a constrained vector budget, we
2264 * group the rings as "efficiently" as possible. You would add new
2265 * mapping configurations in here.
2267 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2271 int rxr_idx = 0, txr_idx = 0;
2272 int rxr_remaining = adapter->num_rx_queues;
2273 int txr_remaining = adapter->num_tx_queues;
2278 /* No mapping required if MSI-X is disabled. */
2279 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2282 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2285 * The ideal configuration...
2286 * We have enough vectors to map one per queue.
2288 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2289 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2290 map_vector_to_rxq(adapter, v_start, rxr_idx);
2292 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2293 map_vector_to_txq(adapter, v_start, txr_idx);
2299 * If we don't have enough vectors for a 1-to-1
2300 * mapping, we'll have to group them so there are
2301 * multiple queues per vector.
2303 /* Re-adjusting *qpv takes care of the remainder. */
2304 for (i = v_start; i < q_vectors; i++) {
2305 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2306 for (j = 0; j < rqpv; j++) {
2307 map_vector_to_rxq(adapter, i, rxr_idx);
2311 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2312 for (j = 0; j < tqpv; j++) {
2313 map_vector_to_txq(adapter, i, txr_idx);
2323 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2324 * @adapter: board private structure
2326 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2327 * interrupts from the kernel.
2329 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2331 struct net_device *netdev = adapter->netdev;
2332 irqreturn_t (*handler)(int, void *);
2333 int i, vector, q_vectors, err;
2336 /* Decrement for Other and TCP Timer vectors */
2337 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2339 err = ixgbe_map_rings_to_vectors(adapter);
2343 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
2344 ? &ixgbe_msix_clean_many : \
2345 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2346 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
2348 for (vector = 0; vector < q_vectors; vector++) {
2349 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2350 handler = SET_HANDLER(q_vector);
2352 if (handler == &ixgbe_msix_clean_rx) {
2353 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2354 "%s-%s-%d", netdev->name, "rx", ri++);
2355 } else if (handler == &ixgbe_msix_clean_tx) {
2356 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2357 "%s-%s-%d", netdev->name, "tx", ti++);
2358 } else if (handler == &ixgbe_msix_clean_many) {
2359 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2360 "%s-%s-%d", netdev->name, "TxRx", ri++);
2363 /* skip this unused q_vector */
2366 err = request_irq(adapter->msix_entries[vector].vector,
2367 handler, 0, q_vector->name,
2370 e_err(probe, "request_irq failed for MSIX interrupt "
2371 "Error: %d\n", err);
2372 goto free_queue_irqs;
2376 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2377 err = request_irq(adapter->msix_entries[vector].vector,
2378 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2380 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2381 goto free_queue_irqs;
2387 for (i = vector - 1; i >= 0; i--)
2388 free_irq(adapter->msix_entries[--vector].vector,
2389 adapter->q_vector[i]);
2390 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2391 pci_disable_msix(adapter->pdev);
2392 kfree(adapter->msix_entries);
2393 adapter->msix_entries = NULL;
2398 * ixgbe_irq_enable - Enable default interrupt generation settings
2399 * @adapter: board private structure
2401 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2406 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2407 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2408 mask |= IXGBE_EIMS_GPI_SDP0;
2409 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2410 mask |= IXGBE_EIMS_GPI_SDP1;
2411 switch (adapter->hw.mac.type) {
2412 case ixgbe_mac_82599EB:
2413 case ixgbe_mac_X540:
2414 mask |= IXGBE_EIMS_ECC;
2415 mask |= IXGBE_EIMS_GPI_SDP1;
2416 mask |= IXGBE_EIMS_GPI_SDP2;
2417 if (adapter->num_vfs)
2418 mask |= IXGBE_EIMS_MAILBOX;
2423 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2424 mask |= IXGBE_EIMS_FLOW_DIR;
2426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2428 ixgbe_irq_enable_queues(adapter, ~0);
2430 IXGBE_WRITE_FLUSH(&adapter->hw);
2432 if (adapter->num_vfs > 32) {
2433 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2434 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2439 * ixgbe_intr - legacy mode Interrupt Handler
2440 * @irq: interrupt number
2441 * @data: pointer to a network interface device structure
2443 static irqreturn_t ixgbe_intr(int irq, void *data)
2445 struct ixgbe_adapter *adapter = data;
2446 struct ixgbe_hw *hw = &adapter->hw;
2447 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2451 * Workaround for silicon errata on 82598. Mask the interrupts
2452 * before the read of EICR.
2454 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2456 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2457 * therefore no explict interrupt disable is necessary */
2458 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2461 * shared interrupt alert!
2462 * make sure interrupts are enabled because the read will
2463 * have disabled interrupts due to EIAM
2464 * finish the workaround of silicon errata on 82598. Unmask
2465 * the interrupt that we masked before the EICR read.
2467 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2468 ixgbe_irq_enable(adapter, true, true);
2469 return IRQ_NONE; /* Not our interrupt */
2472 if (eicr & IXGBE_EICR_LSC)
2473 ixgbe_check_lsc(adapter);
2475 switch (hw->mac.type) {
2476 case ixgbe_mac_82599EB:
2477 ixgbe_check_sfp_event(adapter, eicr);
2478 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2479 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2480 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2481 adapter->interrupt_event = eicr;
2482 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2483 ixgbe_service_event_schedule(adapter);
2491 ixgbe_check_fan_failure(adapter, eicr);
2493 if (napi_schedule_prep(&(q_vector->napi))) {
2494 /* would disable interrupts here but EIAM disabled it */
2495 __napi_schedule(&(q_vector->napi));
2499 * re-enable link(maybe) and non-queue interrupts, no flush.
2500 * ixgbe_poll will re-enable the queue interrupts
2503 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2504 ixgbe_irq_enable(adapter, false, false);
2509 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2511 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2513 for (i = 0; i < q_vectors; i++) {
2514 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2515 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2516 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2517 q_vector->rx.count = 0;
2518 q_vector->tx.count = 0;
2523 * ixgbe_request_irq - initialize interrupts
2524 * @adapter: board private structure
2526 * Attempts to configure interrupts using the best available
2527 * capabilities of the hardware and kernel.
2529 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2531 struct net_device *netdev = adapter->netdev;
2534 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2535 err = ixgbe_request_msix_irqs(adapter);
2536 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2537 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2538 netdev->name, adapter);
2540 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2541 netdev->name, adapter);
2545 e_err(probe, "request_irq failed, Error %d\n", err);
2550 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2552 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2555 q_vectors = adapter->num_msix_vectors;
2558 free_irq(adapter->msix_entries[i].vector, adapter);
2561 for (; i >= 0; i--) {
2562 /* free only the irqs that were actually requested */
2563 if (!adapter->q_vector[i]->rx.count &&
2564 !adapter->q_vector[i]->tx.count)
2567 free_irq(adapter->msix_entries[i].vector,
2568 adapter->q_vector[i]);
2571 ixgbe_reset_q_vectors(adapter);
2573 free_irq(adapter->pdev->irq, adapter);
2578 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2579 * @adapter: board private structure
2581 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2583 switch (adapter->hw.mac.type) {
2584 case ixgbe_mac_82598EB:
2585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2587 case ixgbe_mac_82599EB:
2588 case ixgbe_mac_X540:
2589 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2591 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2592 if (adapter->num_vfs > 32)
2593 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2598 IXGBE_WRITE_FLUSH(&adapter->hw);
2599 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2601 for (i = 0; i < adapter->num_msix_vectors; i++)
2602 synchronize_irq(adapter->msix_entries[i].vector);
2604 synchronize_irq(adapter->pdev->irq);
2609 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2612 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2614 struct ixgbe_hw *hw = &adapter->hw;
2616 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2617 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2619 ixgbe_set_ivar(adapter, 0, 0, 0);
2620 ixgbe_set_ivar(adapter, 1, 0, 0);
2622 map_vector_to_rxq(adapter, 0, 0);
2623 map_vector_to_txq(adapter, 0, 0);
2625 e_info(hw, "Legacy interrupt IVAR setup done\n");
2629 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2630 * @adapter: board private structure
2631 * @ring: structure containing ring specific data
2633 * Configure the Tx descriptor ring after a reset.
2635 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2636 struct ixgbe_ring *ring)
2638 struct ixgbe_hw *hw = &adapter->hw;
2639 u64 tdba = ring->dma;
2642 u8 reg_idx = ring->reg_idx;
2644 /* disable queue to avoid issues while updating state */
2645 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2646 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2647 txdctl & ~IXGBE_TXDCTL_ENABLE);
2648 IXGBE_WRITE_FLUSH(hw);
2650 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2651 (tdba & DMA_BIT_MASK(32)));
2652 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2653 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2654 ring->count * sizeof(union ixgbe_adv_tx_desc));
2655 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2656 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2657 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2659 /* configure fetching thresholds */
2660 if (adapter->rx_itr_setting == 0) {
2661 /* cannot set wthresh when itr==0 */
2662 txdctl &= ~0x007F0000;
2664 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2665 txdctl |= (8 << 16);
2667 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2668 /* PThresh workaround for Tx hang with DFP enabled. */
2672 /* reinitialize flowdirector state */
2673 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2674 adapter->atr_sample_rate) {
2675 ring->atr_sample_rate = adapter->atr_sample_rate;
2676 ring->atr_count = 0;
2677 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2679 ring->atr_sample_rate = 0;
2682 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2685 txdctl |= IXGBE_TXDCTL_ENABLE;
2686 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2688 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2689 if (hw->mac.type == ixgbe_mac_82598EB &&
2690 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2693 /* poll to verify queue is enabled */
2695 usleep_range(1000, 2000);
2696 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2697 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2699 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2702 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2704 struct ixgbe_hw *hw = &adapter->hw;
2707 u8 tcs = netdev_get_num_tc(adapter->netdev);
2709 if (hw->mac.type == ixgbe_mac_82598EB)
2712 /* disable the arbiter while setting MTQC */
2713 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2714 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2715 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2717 /* set transmit pool layout */
2718 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2719 case (IXGBE_FLAG_SRIOV_ENABLED):
2720 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2721 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2725 reg = IXGBE_MTQC_64Q_1PB;
2727 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2729 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2731 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2733 /* Enable Security TX Buffer IFG for multiple pb */
2735 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2736 reg |= IXGBE_SECTX_DCB;
2737 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2742 /* re-enable the arbiter */
2743 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2744 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2748 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2749 * @adapter: board private structure
2751 * Configure the Tx unit of the MAC after a reset.
2753 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2755 struct ixgbe_hw *hw = &adapter->hw;
2759 ixgbe_setup_mtqc(adapter);
2761 if (hw->mac.type != ixgbe_mac_82598EB) {
2762 /* DMATXCTL.EN must be before Tx queues are enabled */
2763 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2764 dmatxctl |= IXGBE_DMATXCTL_TE;
2765 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2768 /* Setup the HW Tx Head and Tail descriptor pointers */
2769 for (i = 0; i < adapter->num_tx_queues; i++)
2770 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2773 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2775 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2776 struct ixgbe_ring *rx_ring)
2779 u8 reg_idx = rx_ring->reg_idx;
2781 switch (adapter->hw.mac.type) {
2782 case ixgbe_mac_82598EB: {
2783 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2784 const int mask = feature[RING_F_RSS].mask;
2785 reg_idx = reg_idx & mask;
2788 case ixgbe_mac_82599EB:
2789 case ixgbe_mac_X540:
2794 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2796 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2797 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2798 if (adapter->num_vfs)
2799 srrctl |= IXGBE_SRRCTL_DROP_EN;
2801 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2802 IXGBE_SRRCTL_BSIZEHDR_MASK;
2804 if (ring_is_ps_enabled(rx_ring)) {
2805 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2806 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2808 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2810 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2812 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2813 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2814 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2817 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2820 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2822 struct ixgbe_hw *hw = &adapter->hw;
2823 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2824 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2825 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2826 u32 mrqc = 0, reta = 0;
2829 u8 tcs = netdev_get_num_tc(adapter->netdev);
2830 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2833 maxq = min(maxq, adapter->num_tx_queues / tcs);
2835 /* Fill out hash function seeds */
2836 for (i = 0; i < 10; i++)
2837 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2839 /* Fill out redirection table */
2840 for (i = 0, j = 0; i < 128; i++, j++) {
2843 /* reta = 4-byte sliding window of
2844 * 0x00..(indices-1)(indices-1)00..etc. */
2845 reta = (reta << 8) | (j * 0x11);
2847 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2850 /* Disable indicating checksum in descriptor, enables RSS hash */
2851 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2852 rxcsum |= IXGBE_RXCSUM_PCSD;
2853 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2855 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2856 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2857 mrqc = IXGBE_MRQC_RSSEN;
2859 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2860 | IXGBE_FLAG_SRIOV_ENABLED);
2863 case (IXGBE_FLAG_RSS_ENABLED):
2865 mrqc = IXGBE_MRQC_RSSEN;
2867 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2869 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2871 case (IXGBE_FLAG_SRIOV_ENABLED):
2872 mrqc = IXGBE_MRQC_VMDQEN;
2879 /* Perform hash on these packet types */
2880 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2881 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2882 | IXGBE_MRQC_RSS_FIELD_IPV6
2883 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2885 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2889 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2890 * @adapter: address of board private structure
2891 * @index: index of ring to set
2893 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2894 struct ixgbe_ring *ring)
2896 struct ixgbe_hw *hw = &adapter->hw;
2899 u8 reg_idx = ring->reg_idx;
2901 if (!ring_is_rsc_enabled(ring))
2904 rx_buf_len = ring->rx_buf_len;
2905 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2906 rscctrl |= IXGBE_RSCCTL_RSCEN;
2908 * we must limit the number of descriptors so that the
2909 * total size of max desc * buf_len is not greater
2912 if (ring_is_ps_enabled(ring)) {
2913 #if (MAX_SKB_FRAGS > 16)
2914 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2915 #elif (MAX_SKB_FRAGS > 8)
2916 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2917 #elif (MAX_SKB_FRAGS > 4)
2918 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2920 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2923 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2924 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2925 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2926 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2928 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2930 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2934 * ixgbe_set_uta - Set unicast filter table address
2935 * @adapter: board private structure
2937 * The unicast table address is a register array of 32-bit registers.
2938 * The table is meant to be used in a way similar to how the MTA is used
2939 * however due to certain limitations in the hardware it is necessary to
2940 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2941 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2943 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2945 struct ixgbe_hw *hw = &adapter->hw;
2948 /* The UTA table only exists on 82599 hardware and newer */
2949 if (hw->mac.type < ixgbe_mac_82599EB)
2952 /* we only need to do this if VMDq is enabled */
2953 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2956 for (i = 0; i < 128; i++)
2957 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2960 #define IXGBE_MAX_RX_DESC_POLL 10
2961 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2962 struct ixgbe_ring *ring)
2964 struct ixgbe_hw *hw = &adapter->hw;
2965 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2967 u8 reg_idx = ring->reg_idx;
2969 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2970 if (hw->mac.type == ixgbe_mac_82598EB &&
2971 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2975 usleep_range(1000, 2000);
2976 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2977 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2980 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2981 "the polling period\n", reg_idx);
2985 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2986 struct ixgbe_ring *ring)
2988 struct ixgbe_hw *hw = &adapter->hw;
2989 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2991 u8 reg_idx = ring->reg_idx;
2993 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2994 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2996 /* write value back with RXDCTL.ENABLE bit cleared */
2997 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2999 if (hw->mac.type == ixgbe_mac_82598EB &&
3000 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3003 /* the hardware may take up to 100us to really disable the rx queue */
3006 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3007 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3010 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3011 "the polling period\n", reg_idx);
3015 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3016 struct ixgbe_ring *ring)
3018 struct ixgbe_hw *hw = &adapter->hw;
3019 u64 rdba = ring->dma;
3021 u8 reg_idx = ring->reg_idx;
3023 /* disable queue to avoid issues while updating state */
3024 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3025 ixgbe_disable_rx_queue(adapter, ring);
3027 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3028 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3029 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3030 ring->count * sizeof(union ixgbe_adv_rx_desc));
3031 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3032 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3033 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3035 ixgbe_configure_srrctl(adapter, ring);
3036 ixgbe_configure_rscctl(adapter, ring);
3038 /* If operating in IOV mode set RLPML for X540 */
3039 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3040 hw->mac.type == ixgbe_mac_X540) {
3041 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3042 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3043 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3046 if (hw->mac.type == ixgbe_mac_82598EB) {
3048 * enable cache line friendly hardware writes:
3049 * PTHRESH=32 descriptors (half the internal cache),
3050 * this also removes ugly rx_no_buffer_count increment
3051 * HTHRESH=4 descriptors (to minimize latency on fetch)
3052 * WTHRESH=8 burst writeback up to two cache lines
3054 rxdctl &= ~0x3FFFFF;
3058 /* enable receive descriptor ring */
3059 rxdctl |= IXGBE_RXDCTL_ENABLE;
3060 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3062 ixgbe_rx_desc_queue_enable(adapter, ring);
3063 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3066 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3068 struct ixgbe_hw *hw = &adapter->hw;
3071 /* PSRTYPE must be initialized in non 82598 adapters */
3072 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3073 IXGBE_PSRTYPE_UDPHDR |
3074 IXGBE_PSRTYPE_IPV4HDR |
3075 IXGBE_PSRTYPE_L2HDR |
3076 IXGBE_PSRTYPE_IPV6HDR;
3078 if (hw->mac.type == ixgbe_mac_82598EB)
3081 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3082 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3084 for (p = 0; p < adapter->num_rx_pools; p++)
3085 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3089 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3091 struct ixgbe_hw *hw = &adapter->hw;
3094 u32 reg_offset, vf_shift;
3097 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3100 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3101 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3102 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3103 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3105 vf_shift = adapter->num_vfs % 32;
3106 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3108 /* Enable only the PF's pool for Tx/Rx */
3109 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3110 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3111 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3112 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3113 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3115 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3116 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3119 * Set up VF register offsets for selected VT Mode,
3120 * i.e. 32 or 64 VFs for SR-IOV
3122 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3123 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3124 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3125 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3127 /* enable Tx loopback for VF/PF communication */
3128 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3129 /* Enable MAC Anti-Spoofing */
3130 hw->mac.ops.set_mac_anti_spoofing(hw,
3131 (adapter->antispoofing_enabled =
3132 (adapter->num_vfs != 0)),
3136 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3138 struct ixgbe_hw *hw = &adapter->hw;
3139 struct net_device *netdev = adapter->netdev;
3140 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3142 struct ixgbe_ring *rx_ring;
3146 /* Decide whether to use packet split mode or not */
3148 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3150 /* Do not use packet split if we're in SR-IOV Mode */
3151 if (adapter->num_vfs)
3152 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3154 /* Disable packet split due to 82599 erratum #45 */
3155 if (hw->mac.type == ixgbe_mac_82599EB)
3156 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3158 /* Set the RX buffer length according to the mode */
3159 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3160 rx_buf_len = IXGBE_RX_HDR_SIZE;
3162 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3163 (netdev->mtu <= ETH_DATA_LEN))
3164 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3166 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3170 /* adjust max frame to be able to do baby jumbo for FCoE */
3171 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3172 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3173 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3175 #endif /* IXGBE_FCOE */
3176 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3177 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3178 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3179 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3181 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3184 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3185 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3186 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3187 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3190 * Setup the HW Rx Head and Tail Descriptor Pointers and
3191 * the Base and Length of the Rx Descriptor Ring
3193 for (i = 0; i < adapter->num_rx_queues; i++) {
3194 rx_ring = adapter->rx_ring[i];
3195 rx_ring->rx_buf_len = rx_buf_len;
3197 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3198 set_ring_ps_enabled(rx_ring);
3200 clear_ring_ps_enabled(rx_ring);
3202 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3203 set_ring_rsc_enabled(rx_ring);
3205 clear_ring_rsc_enabled(rx_ring);
3208 if (netdev->features & NETIF_F_FCOE_MTU) {
3209 struct ixgbe_ring_feature *f;
3210 f = &adapter->ring_feature[RING_F_FCOE];
3211 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3212 clear_ring_ps_enabled(rx_ring);
3213 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3214 rx_ring->rx_buf_len =
3215 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3216 } else if (!ring_is_rsc_enabled(rx_ring) &&
3217 !ring_is_ps_enabled(rx_ring)) {
3218 rx_ring->rx_buf_len =
3219 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3222 #endif /* IXGBE_FCOE */
3226 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3228 struct ixgbe_hw *hw = &adapter->hw;
3229 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3231 switch (hw->mac.type) {
3232 case ixgbe_mac_82598EB:
3234 * For VMDq support of different descriptor types or
3235 * buffer sizes through the use of multiple SRRCTL
3236 * registers, RDRXCTL.MVMEN must be set to 1
3238 * also, the manual doesn't mention it clearly but DCA hints
3239 * will only use queue 0's tags unless this bit is set. Side
3240 * effects of setting this bit are only that SRRCTL must be
3241 * fully programmed [0..15]
3243 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3245 case ixgbe_mac_82599EB:
3246 case ixgbe_mac_X540:
3247 /* Disable RSC for ACK packets */
3248 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3249 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3250 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3251 /* hardware requires some bits to be set by default */
3252 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3253 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3256 /* We should do nothing since we don't know this hardware */
3260 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3264 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3265 * @adapter: board private structure
3267 * Configure the Rx unit of the MAC after a reset.
3269 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3271 struct ixgbe_hw *hw = &adapter->hw;
3275 /* disable receives while setting up the descriptors */
3276 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3277 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3279 ixgbe_setup_psrtype(adapter);
3280 ixgbe_setup_rdrxctl(adapter);
3282 /* Program registers for the distribution of queues */
3283 ixgbe_setup_mrqc(adapter);
3285 ixgbe_set_uta(adapter);
3287 /* set_rx_buffer_len must be called before ring initialization */
3288 ixgbe_set_rx_buffer_len(adapter);
3291 * Setup the HW Rx Head and Tail Descriptor Pointers and
3292 * the Base and Length of the Rx Descriptor Ring
3294 for (i = 0; i < adapter->num_rx_queues; i++)
3295 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3297 /* disable drop enable for 82598 parts */
3298 if (hw->mac.type == ixgbe_mac_82598EB)
3299 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3301 /* enable all receives */
3302 rxctrl |= IXGBE_RXCTRL_RXEN;
3303 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3306 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3308 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3309 struct ixgbe_hw *hw = &adapter->hw;
3310 int pool_ndx = adapter->num_vfs;
3312 /* add VID to filter table */
3313 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3314 set_bit(vid, adapter->active_vlans);
3317 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3319 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3320 struct ixgbe_hw *hw = &adapter->hw;
3321 int pool_ndx = adapter->num_vfs;
3323 /* remove VID from filter table */
3324 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3325 clear_bit(vid, adapter->active_vlans);
3329 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3330 * @adapter: driver data
3332 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3334 struct ixgbe_hw *hw = &adapter->hw;
3337 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3338 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3339 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3343 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3344 * @adapter: driver data
3346 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3348 struct ixgbe_hw *hw = &adapter->hw;
3351 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3352 vlnctrl |= IXGBE_VLNCTRL_VFE;
3353 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3354 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3358 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3359 * @adapter: driver data
3361 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3363 struct ixgbe_hw *hw = &adapter->hw;
3367 switch (hw->mac.type) {
3368 case ixgbe_mac_82598EB:
3369 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3370 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3371 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3373 case ixgbe_mac_82599EB:
3374 case ixgbe_mac_X540:
3375 for (i = 0; i < adapter->num_rx_queues; i++) {
3376 j = adapter->rx_ring[i]->reg_idx;
3377 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3378 vlnctrl &= ~IXGBE_RXDCTL_VME;
3379 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3388 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3389 * @adapter: driver data
3391 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3393 struct ixgbe_hw *hw = &adapter->hw;
3397 switch (hw->mac.type) {
3398 case ixgbe_mac_82598EB:
3399 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3400 vlnctrl |= IXGBE_VLNCTRL_VME;
3401 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3403 case ixgbe_mac_82599EB:
3404 case ixgbe_mac_X540:
3405 for (i = 0; i < adapter->num_rx_queues; i++) {
3406 j = adapter->rx_ring[i]->reg_idx;
3407 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3408 vlnctrl |= IXGBE_RXDCTL_VME;
3409 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3417 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3421 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3423 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3424 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3428 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3429 * @netdev: network interface device structure
3431 * Writes unicast address list to the RAR table.
3432 * Returns: -ENOMEM on failure/insufficient address space
3433 * 0 on no addresses written
3434 * X on writing X addresses to the RAR table
3436 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3439 struct ixgbe_hw *hw = &adapter->hw;
3440 unsigned int vfn = adapter->num_vfs;
3441 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3444 /* return ENOMEM indicating insufficient memory for addresses */
3445 if (netdev_uc_count(netdev) > rar_entries)
3448 if (!netdev_uc_empty(netdev) && rar_entries) {
3449 struct netdev_hw_addr *ha;
3450 /* return error if we do not support writing to RAR table */
3451 if (!hw->mac.ops.set_rar)
3454 netdev_for_each_uc_addr(ha, netdev) {
3457 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3462 /* write the addresses in reverse order to avoid write combining */
3463 for (; rar_entries > 0 ; rar_entries--)
3464 hw->mac.ops.clear_rar(hw, rar_entries);
3470 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3471 * @netdev: network interface device structure
3473 * The set_rx_method entry point is called whenever the unicast/multicast
3474 * address list or the network interface flags are updated. This routine is
3475 * responsible for configuring the hardware for proper unicast, multicast and
3478 void ixgbe_set_rx_mode(struct net_device *netdev)
3480 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3481 struct ixgbe_hw *hw = &adapter->hw;
3482 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3485 /* Check for Promiscuous and All Multicast modes */
3487 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3489 /* set all bits that we expect to always be set */
3490 fctrl |= IXGBE_FCTRL_BAM;
3491 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3492 fctrl |= IXGBE_FCTRL_PMCF;
3494 /* clear the bits we are changing the status of */
3495 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3497 if (netdev->flags & IFF_PROMISC) {
3498 hw->addr_ctrl.user_set_promisc = true;
3499 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3500 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3501 /* don't hardware filter vlans in promisc mode */
3502 ixgbe_vlan_filter_disable(adapter);
3504 if (netdev->flags & IFF_ALLMULTI) {
3505 fctrl |= IXGBE_FCTRL_MPE;
3506 vmolr |= IXGBE_VMOLR_MPE;
3509 * Write addresses to the MTA, if the attempt fails
3510 * then we should just turn on promiscuous mode so
3511 * that we can at least receive multicast traffic
3513 hw->mac.ops.update_mc_addr_list(hw, netdev);
3514 vmolr |= IXGBE_VMOLR_ROMPE;
3516 ixgbe_vlan_filter_enable(adapter);
3517 hw->addr_ctrl.user_set_promisc = false;
3519 * Write addresses to available RAR registers, if there is not
3520 * sufficient space to store all the addresses then enable
3521 * unicast promiscuous mode
3523 count = ixgbe_write_uc_addr_list(netdev);
3525 fctrl |= IXGBE_FCTRL_UPE;
3526 vmolr |= IXGBE_VMOLR_ROPE;
3530 if (adapter->num_vfs) {
3531 ixgbe_restore_vf_multicasts(adapter);
3532 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3533 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3535 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3538 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3540 if (netdev->features & NETIF_F_HW_VLAN_RX)
3541 ixgbe_vlan_strip_enable(adapter);
3543 ixgbe_vlan_strip_disable(adapter);
3546 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3549 struct ixgbe_q_vector *q_vector;
3550 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3552 /* legacy and MSI only use one vector */
3553 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3556 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3557 struct napi_struct *napi;
3558 q_vector = adapter->q_vector[q_idx];
3559 napi = &q_vector->napi;
3560 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3561 if (!q_vector->rx.count || !q_vector->tx.count) {
3562 if (q_vector->tx.count == 1)
3563 napi->poll = &ixgbe_clean_txonly;
3564 else if (q_vector->rx.count == 1)
3565 napi->poll = &ixgbe_clean_rxonly;
3573 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3576 struct ixgbe_q_vector *q_vector;
3577 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3579 /* legacy and MSI only use one vector */
3580 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3583 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3584 q_vector = adapter->q_vector[q_idx];
3585 napi_disable(&q_vector->napi);
3589 #ifdef CONFIG_IXGBE_DCB
3591 * ixgbe_configure_dcb - Configure DCB hardware
3592 * @adapter: ixgbe adapter struct
3594 * This is called by the driver on open to configure the DCB hardware.
3595 * This is also called by the gennetlink interface when reconfiguring
3598 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3600 struct ixgbe_hw *hw = &adapter->hw;
3601 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3603 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3604 if (hw->mac.type == ixgbe_mac_82598EB)
3605 netif_set_gso_max_size(adapter->netdev, 65536);
3609 if (hw->mac.type == ixgbe_mac_82598EB)
3610 netif_set_gso_max_size(adapter->netdev, 32768);
3613 /* Enable VLAN tag insert/strip */
3614 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3616 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3618 /* reconfigure the hardware */
3619 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3621 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3622 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3624 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3626 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3628 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3630 struct net_device *dev = adapter->netdev;
3632 if (adapter->ixgbe_ieee_ets)
3633 dev->dcbnl_ops->ieee_setets(dev,
3634 adapter->ixgbe_ieee_ets);
3635 if (adapter->ixgbe_ieee_pfc)
3636 dev->dcbnl_ops->ieee_setpfc(dev,
3637 adapter->ixgbe_ieee_pfc);
3640 /* Enable RSS Hash per TC */
3641 if (hw->mac.type != ixgbe_mac_82598EB) {
3645 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3647 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3652 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3654 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3660 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3663 int num_tc = netdev_get_num_tc(adapter->netdev);
3664 struct ixgbe_hw *hw = &adapter->hw;
3666 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3667 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3668 hdrm = 64 << adapter->fdir_pballoc;
3670 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3673 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3675 struct ixgbe_hw *hw = &adapter->hw;
3676 struct hlist_node *node, *node2;
3677 struct ixgbe_fdir_filter *filter;
3679 spin_lock(&adapter->fdir_perfect_lock);
3681 if (!hlist_empty(&adapter->fdir_filter_list))
3682 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3684 hlist_for_each_entry_safe(filter, node, node2,
3685 &adapter->fdir_filter_list, fdir_node) {
3686 ixgbe_fdir_write_perfect_filter_82599(hw,
3689 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3690 IXGBE_FDIR_DROP_QUEUE :
3691 adapter->rx_ring[filter->action]->reg_idx);
3694 spin_unlock(&adapter->fdir_perfect_lock);
3697 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3699 struct net_device *netdev = adapter->netdev;
3700 struct ixgbe_hw *hw = &adapter->hw;
3703 ixgbe_configure_pb(adapter);
3704 #ifdef CONFIG_IXGBE_DCB
3705 ixgbe_configure_dcb(adapter);
3708 ixgbe_set_rx_mode(netdev);
3709 ixgbe_restore_vlan(adapter);
3712 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3713 ixgbe_configure_fcoe(adapter);
3715 #endif /* IXGBE_FCOE */
3716 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3717 for (i = 0; i < adapter->num_tx_queues; i++)
3718 adapter->tx_ring[i]->atr_sample_rate =
3719 adapter->atr_sample_rate;
3720 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3721 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3722 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3723 adapter->fdir_pballoc);
3724 ixgbe_fdir_filter_restore(adapter);
3726 ixgbe_configure_virtualization(adapter);
3728 ixgbe_configure_tx(adapter);
3729 ixgbe_configure_rx(adapter);
3732 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3734 switch (hw->phy.type) {
3735 case ixgbe_phy_sfp_avago:
3736 case ixgbe_phy_sfp_ftl:
3737 case ixgbe_phy_sfp_intel:
3738 case ixgbe_phy_sfp_unknown:
3739 case ixgbe_phy_sfp_passive_tyco:
3740 case ixgbe_phy_sfp_passive_unknown:
3741 case ixgbe_phy_sfp_active_unknown:
3742 case ixgbe_phy_sfp_ftl_active:
3750 * ixgbe_sfp_link_config - set up SFP+ link
3751 * @adapter: pointer to private adapter struct
3753 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3756 * We are assuming the worst case scenerio here, and that
3757 * is that an SFP was inserted/removed after the reset
3758 * but before SFP detection was enabled. As such the best
3759 * solution is to just start searching as soon as we start
3761 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3762 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3764 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3768 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3769 * @hw: pointer to private hardware struct
3771 * Returns 0 on success, negative on failure
3773 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3776 bool negotiation, link_up = false;
3777 u32 ret = IXGBE_ERR_LINK_SETUP;
3779 if (hw->mac.ops.check_link)
3780 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3785 autoneg = hw->phy.autoneg_advertised;
3786 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3787 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3792 if (hw->mac.ops.setup_link)
3793 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3798 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3800 struct ixgbe_hw *hw = &adapter->hw;
3803 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3804 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3806 gpie |= IXGBE_GPIE_EIAME;
3808 * use EIAM to auto-mask when MSI-X interrupt is asserted
3809 * this saves a register write for every interrupt
3811 switch (hw->mac.type) {
3812 case ixgbe_mac_82598EB:
3813 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3815 case ixgbe_mac_82599EB:
3816 case ixgbe_mac_X540:
3818 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3819 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3823 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3824 * specifically only auto mask tx and rx interrupts */
3825 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3828 /* XXX: to interrupt immediately for EICS writes, enable this */
3829 /* gpie |= IXGBE_GPIE_EIMEN; */
3831 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3832 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3833 gpie |= IXGBE_GPIE_VTMODE_64;
3836 /* Enable fan failure interrupt */
3837 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3838 gpie |= IXGBE_SDP1_GPIEN;
3840 if (hw->mac.type == ixgbe_mac_82599EB) {
3841 gpie |= IXGBE_SDP1_GPIEN;
3842 gpie |= IXGBE_SDP2_GPIEN;
3845 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3848 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3850 struct ixgbe_hw *hw = &adapter->hw;
3854 ixgbe_get_hw_control(adapter);
3855 ixgbe_setup_gpie(adapter);
3857 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3858 ixgbe_configure_msix(adapter);
3860 ixgbe_configure_msi_and_legacy(adapter);
3862 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3863 if (hw->mac.ops.enable_tx_laser &&
3864 ((hw->phy.multispeed_fiber) ||
3865 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3866 (hw->mac.type == ixgbe_mac_82599EB))))
3867 hw->mac.ops.enable_tx_laser(hw);
3869 clear_bit(__IXGBE_DOWN, &adapter->state);
3870 ixgbe_napi_enable_all(adapter);
3872 if (ixgbe_is_sfp(hw)) {
3873 ixgbe_sfp_link_config(adapter);
3875 err = ixgbe_non_sfp_link_config(hw);
3877 e_err(probe, "link_config FAILED %d\n", err);
3880 /* clear any pending interrupts, may auto mask */
3881 IXGBE_READ_REG(hw, IXGBE_EICR);
3882 ixgbe_irq_enable(adapter, true, true);
3885 * If this adapter has a fan, check to see if we had a failure
3886 * before we enabled the interrupt.
3888 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3889 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3890 if (esdp & IXGBE_ESDP_SDP1)
3891 e_crit(drv, "Fan has stopped, replace the adapter\n");
3894 /* enable transmits */
3895 netif_tx_start_all_queues(adapter->netdev);
3897 /* bring the link up in the watchdog, this could race with our first
3898 * link up interrupt but shouldn't be a problem */
3899 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3900 adapter->link_check_timeout = jiffies;
3901 mod_timer(&adapter->service_timer, jiffies);
3903 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3904 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3905 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3906 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3911 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3913 WARN_ON(in_interrupt());
3914 /* put off any impending NetWatchDogTimeout */
3915 adapter->netdev->trans_start = jiffies;
3917 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3918 usleep_range(1000, 2000);
3919 ixgbe_down(adapter);
3921 * If SR-IOV enabled then wait a bit before bringing the adapter
3922 * back up to give the VFs time to respond to the reset. The
3923 * two second wait is based upon the watchdog timer cycle in
3926 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3929 clear_bit(__IXGBE_RESETTING, &adapter->state);
3932 int ixgbe_up(struct ixgbe_adapter *adapter)
3934 /* hardware has been reset, we need to reload some things */
3935 ixgbe_configure(adapter);
3937 return ixgbe_up_complete(adapter);
3940 void ixgbe_reset(struct ixgbe_adapter *adapter)
3942 struct ixgbe_hw *hw = &adapter->hw;
3945 /* lock SFP init bit to prevent race conditions with the watchdog */
3946 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3947 usleep_range(1000, 2000);
3949 /* clear all SFP and link config related flags while holding SFP_INIT */
3950 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3951 IXGBE_FLAG2_SFP_NEEDS_RESET);
3952 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3954 err = hw->mac.ops.init_hw(hw);
3957 case IXGBE_ERR_SFP_NOT_PRESENT:
3958 case IXGBE_ERR_SFP_NOT_SUPPORTED:
3960 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3961 e_dev_err("master disable timed out\n");
3963 case IXGBE_ERR_EEPROM_VERSION:
3964 /* We are running on a pre-production device, log a warning */
3965 e_dev_warn("This device is a pre-production adapter/LOM. "
3966 "Please be aware there may be issuesassociated with "
3967 "your hardware. If you are experiencing problems "
3968 "please contact your Intel or hardware "
3969 "representative who provided you with this "
3973 e_dev_err("Hardware Error: %d\n", err);
3976 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3978 /* reprogram the RAR[0] in case user changed it. */
3979 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3984 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3985 * @rx_ring: ring to free buffers from
3987 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3989 struct device *dev = rx_ring->dev;
3993 /* ring already cleared, nothing to do */
3994 if (!rx_ring->rx_buffer_info)
3997 /* Free all the Rx ring sk_buffs */
3998 for (i = 0; i < rx_ring->count; i++) {
3999 struct ixgbe_rx_buffer *rx_buffer_info;
4001 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4002 if (rx_buffer_info->dma) {
4003 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4004 rx_ring->rx_buf_len,
4006 rx_buffer_info->dma = 0;
4008 if (rx_buffer_info->skb) {
4009 struct sk_buff *skb = rx_buffer_info->skb;
4010 rx_buffer_info->skb = NULL;
4012 struct sk_buff *this = skb;
4013 if (IXGBE_RSC_CB(this)->delay_unmap) {
4014 dma_unmap_single(dev,
4015 IXGBE_RSC_CB(this)->dma,
4016 rx_ring->rx_buf_len,
4018 IXGBE_RSC_CB(this)->dma = 0;
4019 IXGBE_RSC_CB(skb)->delay_unmap = false;
4022 dev_kfree_skb(this);
4025 if (!rx_buffer_info->page)
4027 if (rx_buffer_info->page_dma) {
4028 dma_unmap_page(dev, rx_buffer_info->page_dma,
4029 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4030 rx_buffer_info->page_dma = 0;
4032 put_page(rx_buffer_info->page);
4033 rx_buffer_info->page = NULL;
4034 rx_buffer_info->page_offset = 0;
4037 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4038 memset(rx_ring->rx_buffer_info, 0, size);
4040 /* Zero out the descriptor ring */
4041 memset(rx_ring->desc, 0, rx_ring->size);
4043 rx_ring->next_to_clean = 0;
4044 rx_ring->next_to_use = 0;
4048 * ixgbe_clean_tx_ring - Free Tx Buffers
4049 * @tx_ring: ring to be cleaned
4051 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4053 struct ixgbe_tx_buffer *tx_buffer_info;
4057 /* ring already cleared, nothing to do */
4058 if (!tx_ring->tx_buffer_info)
4061 /* Free all the Tx ring sk_buffs */
4062 for (i = 0; i < tx_ring->count; i++) {
4063 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4064 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4067 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4068 memset(tx_ring->tx_buffer_info, 0, size);
4070 /* Zero out the descriptor ring */
4071 memset(tx_ring->desc, 0, tx_ring->size);
4073 tx_ring->next_to_use = 0;
4074 tx_ring->next_to_clean = 0;
4078 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4079 * @adapter: board private structure
4081 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4085 for (i = 0; i < adapter->num_rx_queues; i++)
4086 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4090 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4091 * @adapter: board private structure
4093 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4097 for (i = 0; i < adapter->num_tx_queues; i++)
4098 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4101 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4103 struct hlist_node *node, *node2;
4104 struct ixgbe_fdir_filter *filter;
4106 spin_lock(&adapter->fdir_perfect_lock);
4108 hlist_for_each_entry_safe(filter, node, node2,
4109 &adapter->fdir_filter_list, fdir_node) {
4110 hlist_del(&filter->fdir_node);
4113 adapter->fdir_filter_count = 0;
4115 spin_unlock(&adapter->fdir_perfect_lock);
4118 void ixgbe_down(struct ixgbe_adapter *adapter)
4120 struct net_device *netdev = adapter->netdev;
4121 struct ixgbe_hw *hw = &adapter->hw;
4124 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4126 /* signal that we are down to the interrupt handler */
4127 set_bit(__IXGBE_DOWN, &adapter->state);
4129 /* disable receives */
4130 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4131 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4133 /* disable all enabled rx queues */
4134 for (i = 0; i < adapter->num_rx_queues; i++)
4135 /* this call also flushes the previous write */
4136 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4138 usleep_range(10000, 20000);
4140 netif_tx_stop_all_queues(netdev);
4142 /* call carrier off first to avoid false dev_watchdog timeouts */
4143 netif_carrier_off(netdev);
4144 netif_tx_disable(netdev);
4146 ixgbe_irq_disable(adapter);
4148 ixgbe_napi_disable_all(adapter);
4150 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4151 IXGBE_FLAG2_RESET_REQUESTED);
4152 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4154 del_timer_sync(&adapter->service_timer);
4156 /* disable receive for all VFs and wait one second */
4157 if (adapter->num_vfs) {
4158 /* ping all the active vfs to let them know we are going down */
4159 ixgbe_ping_all_vfs(adapter);
4161 /* Disable all VFTE/VFRE TX/RX */
4162 ixgbe_disable_tx_rx(adapter);
4164 /* Mark all the VFs as inactive */
4165 for (i = 0 ; i < adapter->num_vfs; i++)
4166 adapter->vfinfo[i].clear_to_send = 0;
4169 /* Cleanup the affinity_hint CPU mask memory and callback */
4170 for (i = 0; i < num_q_vectors; i++) {
4171 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4172 /* clear the affinity_mask in the IRQ descriptor */
4173 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4174 /* release the CPU mask memory */
4175 free_cpumask_var(q_vector->affinity_mask);
4178 /* disable transmits in the hardware now that interrupts are off */
4179 for (i = 0; i < adapter->num_tx_queues; i++) {
4180 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4181 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4184 /* Disable the Tx DMA engine on 82599 and X540 */
4185 switch (hw->mac.type) {
4186 case ixgbe_mac_82599EB:
4187 case ixgbe_mac_X540:
4188 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4189 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4190 ~IXGBE_DMATXCTL_TE));
4196 if (!pci_channel_offline(adapter->pdev))
4197 ixgbe_reset(adapter);
4199 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4200 if (hw->mac.ops.disable_tx_laser &&
4201 ((hw->phy.multispeed_fiber) ||
4202 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4203 (hw->mac.type == ixgbe_mac_82599EB))))
4204 hw->mac.ops.disable_tx_laser(hw);
4206 ixgbe_clean_all_tx_rings(adapter);
4207 ixgbe_clean_all_rx_rings(adapter);
4209 #ifdef CONFIG_IXGBE_DCA
4210 /* since we reset the hardware DCA settings were cleared */
4211 ixgbe_setup_dca(adapter);
4216 * ixgbe_poll - NAPI Rx polling callback
4217 * @napi: structure for representing this polling device
4218 * @budget: how many packets driver is allowed to clean
4220 * This function is used for legacy and MSI, NAPI mode
4222 static int ixgbe_poll(struct napi_struct *napi, int budget)
4224 struct ixgbe_q_vector *q_vector =
4225 container_of(napi, struct ixgbe_q_vector, napi);
4226 struct ixgbe_adapter *adapter = q_vector->adapter;
4227 int tx_clean_complete, work_done = 0;
4229 #ifdef CONFIG_IXGBE_DCA
4230 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4231 ixgbe_update_dca(q_vector);
4234 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4235 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4237 if (!tx_clean_complete)
4240 /* If budget not fully consumed, exit the polling mode */
4241 if (work_done < budget) {
4242 napi_complete(napi);
4243 if (adapter->rx_itr_setting & 1)
4244 ixgbe_set_itr(q_vector);
4245 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4246 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4252 * ixgbe_tx_timeout - Respond to a Tx Hang
4253 * @netdev: network interface device structure
4255 static void ixgbe_tx_timeout(struct net_device *netdev)
4257 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4259 /* Do the reset outside of interrupt context */
4260 ixgbe_tx_timeout_reset(adapter);
4264 * ixgbe_set_rss_queues: Allocate queues for RSS
4265 * @adapter: board private structure to initialize
4267 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4268 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4271 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4274 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4276 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4278 adapter->num_rx_queues = f->indices;
4279 adapter->num_tx_queues = f->indices;
4289 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4290 * @adapter: board private structure to initialize
4292 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4293 * to the original CPU that initiated the Tx session. This runs in addition
4294 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4295 * Rx load across CPUs using RSS.
4298 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4301 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4303 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4306 /* Flow Director must have RSS enabled */
4307 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4308 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4309 adapter->num_tx_queues = f_fdir->indices;
4310 adapter->num_rx_queues = f_fdir->indices;
4313 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4320 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4321 * @adapter: board private structure to initialize
4323 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4324 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4325 * rx queues out of the max number of rx queues, instead, it is used as the
4326 * index of the first rx queue used by FCoE.
4329 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4331 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4333 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4336 f->indices = min((int)num_online_cpus(), f->indices);
4338 adapter->num_rx_queues = 1;
4339 adapter->num_tx_queues = 1;
4341 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4342 e_info(probe, "FCoE enabled with RSS\n");
4343 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4344 ixgbe_set_fdir_queues(adapter);
4346 ixgbe_set_rss_queues(adapter);
4349 /* adding FCoE rx rings to the end */
4350 f->mask = adapter->num_rx_queues;
4351 adapter->num_rx_queues += f->indices;
4352 adapter->num_tx_queues += f->indices;
4356 #endif /* IXGBE_FCOE */
4358 /* Artificial max queue cap per traffic class in DCB mode */
4359 #define DCB_QUEUE_CAP 8
4361 #ifdef CONFIG_IXGBE_DCB
4362 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4364 int per_tc_q, q, i, offset = 0;
4365 struct net_device *dev = adapter->netdev;
4366 int tcs = netdev_get_num_tc(dev);
4371 /* Map queue offset and counts onto allocated tx queues */
4372 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4373 q = min((int)num_online_cpus(), per_tc_q);
4375 for (i = 0; i < tcs; i++) {
4376 netdev_set_prio_tc_map(dev, i, i);
4377 netdev_set_tc_queue(dev, i, q, offset);
4381 adapter->num_tx_queues = q * tcs;
4382 adapter->num_rx_queues = q * tcs;
4385 /* FCoE enabled queues require special configuration indexed
4386 * by feature specific indices and mask. Here we map FCoE
4387 * indices onto the DCB queue pairs allowing FCoE to own
4388 * configuration later.
4390 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4392 struct ixgbe_ring_feature *f =
4393 &adapter->ring_feature[RING_F_FCOE];
4395 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4396 f->indices = dev->tc_to_txq[tc].count;
4397 f->mask = dev->tc_to_txq[tc].offset;
4406 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4407 * @adapter: board private structure to initialize
4409 * IOV doesn't actually use anything, so just NAK the
4410 * request for now and let the other queue routines
4411 * figure out what to do.
4413 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4419 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4420 * @adapter: board private structure to initialize
4422 * This is the top level queue allocation routine. The order here is very
4423 * important, starting with the "most" number of features turned on at once,
4424 * and ending with the smallest set of features. This way large combinations
4425 * can be allocated if they're turned on, and smaller combinations are the
4426 * fallthrough conditions.
4429 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4431 /* Start with base case */
4432 adapter->num_rx_queues = 1;
4433 adapter->num_tx_queues = 1;
4434 adapter->num_rx_pools = adapter->num_rx_queues;
4435 adapter->num_rx_queues_per_pool = 1;
4437 if (ixgbe_set_sriov_queues(adapter))
4440 #ifdef CONFIG_IXGBE_DCB
4441 if (ixgbe_set_dcb_queues(adapter))
4446 if (ixgbe_set_fcoe_queues(adapter))
4449 #endif /* IXGBE_FCOE */
4450 if (ixgbe_set_fdir_queues(adapter))
4453 if (ixgbe_set_rss_queues(adapter))
4456 /* fallback to base case */
4457 adapter->num_rx_queues = 1;
4458 adapter->num_tx_queues = 1;
4461 /* Notify the stack of the (possibly) reduced queue counts. */
4462 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4463 return netif_set_real_num_rx_queues(adapter->netdev,
4464 adapter->num_rx_queues);
4467 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4470 int err, vector_threshold;
4472 /* We'll want at least 3 (vector_threshold):
4475 * 3) Other (Link Status Change, etc.)
4476 * 4) TCP Timer (optional)
4478 vector_threshold = MIN_MSIX_COUNT;
4480 /* The more we get, the more we will assign to Tx/Rx Cleanup
4481 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4482 * Right now, we simply care about how many we'll get; we'll
4483 * set them up later while requesting irq's.
4485 while (vectors >= vector_threshold) {
4486 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4488 if (!err) /* Success in acquiring all requested vectors. */
4491 vectors = 0; /* Nasty failure, quit now */
4492 else /* err == number of vectors we should try again with */
4496 if (vectors < vector_threshold) {
4497 /* Can't allocate enough MSI-X interrupts? Oh well.
4498 * This just means we'll go with either a single MSI
4499 * vector or fall back to legacy interrupts.
4501 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4502 "Unable to allocate MSI-X interrupts\n");
4503 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4504 kfree(adapter->msix_entries);
4505 adapter->msix_entries = NULL;
4507 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4509 * Adjust for only the vectors we'll use, which is minimum
4510 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4511 * vectors we were allocated.
4513 adapter->num_msix_vectors = min(vectors,
4514 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4519 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4520 * @adapter: board private structure to initialize
4522 * Cache the descriptor ring offsets for RSS to the assigned rings.
4525 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4529 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4532 for (i = 0; i < adapter->num_rx_queues; i++)
4533 adapter->rx_ring[i]->reg_idx = i;
4534 for (i = 0; i < adapter->num_tx_queues; i++)
4535 adapter->tx_ring[i]->reg_idx = i;
4540 #ifdef CONFIG_IXGBE_DCB
4542 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4543 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4544 unsigned int *tx, unsigned int *rx)
4546 struct net_device *dev = adapter->netdev;
4547 struct ixgbe_hw *hw = &adapter->hw;
4548 u8 num_tcs = netdev_get_num_tc(dev);
4553 switch (hw->mac.type) {
4554 case ixgbe_mac_82598EB:
4558 case ixgbe_mac_82599EB:
4559 case ixgbe_mac_X540:
4564 } else if (tc < 5) {
4565 *tx = ((tc + 2) << 4);
4567 } else if (tc < num_tcs) {
4568 *tx = ((tc + 8) << 3);
4571 } else if (num_tcs == 4) {
4597 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4598 * @adapter: board private structure to initialize
4600 * Cache the descriptor ring offsets for DCB to the assigned rings.
4603 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4605 struct net_device *dev = adapter->netdev;
4607 u8 num_tcs = netdev_get_num_tc(dev);
4612 for (i = 0, k = 0; i < num_tcs; i++) {
4613 unsigned int tx_s, rx_s;
4614 u16 count = dev->tc_to_txq[i].count;
4616 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4617 for (j = 0; j < count; j++, k++) {
4618 adapter->tx_ring[k]->reg_idx = tx_s + j;
4619 adapter->rx_ring[k]->reg_idx = rx_s + j;
4620 adapter->tx_ring[k]->dcb_tc = i;
4621 adapter->rx_ring[k]->dcb_tc = i;
4630 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4631 * @adapter: board private structure to initialize
4633 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4636 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4641 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4642 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4643 for (i = 0; i < adapter->num_rx_queues; i++)
4644 adapter->rx_ring[i]->reg_idx = i;
4645 for (i = 0; i < adapter->num_tx_queues; i++)
4646 adapter->tx_ring[i]->reg_idx = i;
4655 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4656 * @adapter: board private structure to initialize
4658 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4661 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4663 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4665 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4667 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4670 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4671 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4672 ixgbe_cache_ring_fdir(adapter);
4674 ixgbe_cache_ring_rss(adapter);
4676 fcoe_rx_i = f->mask;
4677 fcoe_tx_i = f->mask;
4679 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4680 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4681 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4686 #endif /* IXGBE_FCOE */
4688 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4689 * @adapter: board private structure to initialize
4691 * SR-IOV doesn't use any descriptor rings but changes the default if
4692 * no other mapping is used.
4695 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4697 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4698 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4699 if (adapter->num_vfs)
4706 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4707 * @adapter: board private structure to initialize
4709 * Once we know the feature-set enabled for the device, we'll cache
4710 * the register offset the descriptor ring is assigned to.
4712 * Note, the order the various feature calls is important. It must start with
4713 * the "most" features enabled at the same time, then trickle down to the
4714 * least amount of features turned on at once.
4716 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4718 /* start with default case */
4719 adapter->rx_ring[0]->reg_idx = 0;
4720 adapter->tx_ring[0]->reg_idx = 0;
4722 if (ixgbe_cache_ring_sriov(adapter))
4725 #ifdef CONFIG_IXGBE_DCB
4726 if (ixgbe_cache_ring_dcb(adapter))
4731 if (ixgbe_cache_ring_fcoe(adapter))
4733 #endif /* IXGBE_FCOE */
4735 if (ixgbe_cache_ring_fdir(adapter))
4738 if (ixgbe_cache_ring_rss(adapter))
4743 * ixgbe_alloc_queues - Allocate memory for all rings
4744 * @adapter: board private structure to initialize
4746 * We allocate one ring per queue at run-time since we don't know the
4747 * number of queues at compile-time. The polling_netdev array is
4748 * intended for Multiqueue, but should work fine with a single queue.
4750 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4752 int rx = 0, tx = 0, nid = adapter->node;
4754 if (nid < 0 || !node_online(nid))
4755 nid = first_online_node;
4757 for (; tx < adapter->num_tx_queues; tx++) {
4758 struct ixgbe_ring *ring;
4760 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4762 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4764 goto err_allocation;
4765 ring->count = adapter->tx_ring_count;
4766 ring->queue_index = tx;
4767 ring->numa_node = nid;
4768 ring->dev = &adapter->pdev->dev;
4769 ring->netdev = adapter->netdev;
4771 adapter->tx_ring[tx] = ring;
4774 for (; rx < adapter->num_rx_queues; rx++) {
4775 struct ixgbe_ring *ring;
4777 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4779 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4781 goto err_allocation;
4782 ring->count = adapter->rx_ring_count;
4783 ring->queue_index = rx;
4784 ring->numa_node = nid;
4785 ring->dev = &adapter->pdev->dev;
4786 ring->netdev = adapter->netdev;
4788 adapter->rx_ring[rx] = ring;
4791 ixgbe_cache_ring_register(adapter);
4797 kfree(adapter->tx_ring[--tx]);
4800 kfree(adapter->rx_ring[--rx]);
4805 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4806 * @adapter: board private structure to initialize
4808 * Attempt to configure the interrupts using the best available
4809 * capabilities of the hardware and the kernel.
4811 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4813 struct ixgbe_hw *hw = &adapter->hw;
4815 int vector, v_budget;
4818 * It's easy to be greedy for MSI-X vectors, but it really
4819 * doesn't do us much good if we have a lot more vectors
4820 * than CPU's. So let's be conservative and only ask for
4821 * (roughly) the same number of vectors as there are CPU's.
4823 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4824 (int)num_online_cpus()) + NON_Q_VECTORS;
4827 * At the same time, hardware can only support a maximum of
4828 * hw.mac->max_msix_vectors vectors. With features
4829 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4830 * descriptor queues supported by our device. Thus, we cap it off in
4831 * those rare cases where the cpu count also exceeds our vector limit.
4833 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4835 /* A failure in MSI-X entry allocation isn't fatal, but it does
4836 * mean we disable MSI-X capabilities of the adapter. */
4837 adapter->msix_entries = kcalloc(v_budget,
4838 sizeof(struct msix_entry), GFP_KERNEL);
4839 if (adapter->msix_entries) {
4840 for (vector = 0; vector < v_budget; vector++)
4841 adapter->msix_entries[vector].entry = vector;
4843 ixgbe_acquire_msix_vectors(adapter, v_budget);
4845 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4849 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4850 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4851 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4853 "ATR is not supported while multiple "
4854 "queues are disabled. Disabling Flow Director\n");
4856 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4857 adapter->atr_sample_rate = 0;
4858 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4859 ixgbe_disable_sriov(adapter);
4861 err = ixgbe_set_num_queues(adapter);
4865 err = pci_enable_msi(adapter->pdev);
4867 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4869 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4870 "Unable to allocate MSI interrupt, "
4871 "falling back to legacy. Error: %d\n", err);
4881 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4882 * @adapter: board private structure to initialize
4884 * We allocate one q_vector per queue interrupt. If allocation fails we
4887 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4889 int q_idx, num_q_vectors;
4890 struct ixgbe_q_vector *q_vector;
4891 int (*poll)(struct napi_struct *, int);
4893 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4894 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4895 poll = &ixgbe_clean_rxtx_many;
4901 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4902 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4903 GFP_KERNEL, adapter->node);
4905 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4909 q_vector->adapter = adapter;
4910 if (q_vector->tx.count && !q_vector->rx.count)
4911 q_vector->eitr = adapter->tx_eitr_param;
4913 q_vector->eitr = adapter->rx_eitr_param;
4914 q_vector->v_idx = q_idx;
4915 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4916 adapter->q_vector[q_idx] = q_vector;
4924 q_vector = adapter->q_vector[q_idx];
4925 netif_napi_del(&q_vector->napi);
4927 adapter->q_vector[q_idx] = NULL;
4933 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4934 * @adapter: board private structure to initialize
4936 * This function frees the memory allocated to the q_vectors. In addition if
4937 * NAPI is enabled it will delete any references to the NAPI struct prior
4938 * to freeing the q_vector.
4940 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4942 int q_idx, num_q_vectors;
4944 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4945 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4949 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4950 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4951 adapter->q_vector[q_idx] = NULL;
4952 netif_napi_del(&q_vector->napi);
4957 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4959 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4960 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4961 pci_disable_msix(adapter->pdev);
4962 kfree(adapter->msix_entries);
4963 adapter->msix_entries = NULL;
4964 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4965 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4966 pci_disable_msi(adapter->pdev);
4971 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4972 * @adapter: board private structure to initialize
4974 * We determine which interrupt scheme to use based on...
4975 * - Kernel support (MSI, MSI-X)
4976 * - which can be user-defined (via MODULE_PARAM)
4977 * - Hardware queue count (num_*_queues)
4978 * - defined by miscellaneous hardware support/features (RSS, etc.)
4980 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4984 /* Number of supported queues */
4985 err = ixgbe_set_num_queues(adapter);
4989 err = ixgbe_set_interrupt_capability(adapter);
4991 e_dev_err("Unable to setup interrupt capabilities\n");
4992 goto err_set_interrupt;
4995 err = ixgbe_alloc_q_vectors(adapter);
4997 e_dev_err("Unable to allocate memory for queue vectors\n");
4998 goto err_alloc_q_vectors;
5001 err = ixgbe_alloc_queues(adapter);
5003 e_dev_err("Unable to allocate memory for queues\n");
5004 goto err_alloc_queues;
5007 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5008 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5009 adapter->num_rx_queues, adapter->num_tx_queues);
5011 set_bit(__IXGBE_DOWN, &adapter->state);
5016 ixgbe_free_q_vectors(adapter);
5017 err_alloc_q_vectors:
5018 ixgbe_reset_interrupt_capability(adapter);
5024 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5025 * @adapter: board private structure to clear interrupt scheme on
5027 * We go through and clear interrupt specific resources and reset the structure
5028 * to pre-load conditions
5030 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5034 for (i = 0; i < adapter->num_tx_queues; i++) {
5035 kfree(adapter->tx_ring[i]);
5036 adapter->tx_ring[i] = NULL;
5038 for (i = 0; i < adapter->num_rx_queues; i++) {
5039 struct ixgbe_ring *ring = adapter->rx_ring[i];
5041 /* ixgbe_get_stats64() might access this ring, we must wait
5042 * a grace period before freeing it.
5044 kfree_rcu(ring, rcu);
5045 adapter->rx_ring[i] = NULL;
5048 adapter->num_tx_queues = 0;
5049 adapter->num_rx_queues = 0;
5051 ixgbe_free_q_vectors(adapter);
5052 ixgbe_reset_interrupt_capability(adapter);
5056 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5057 * @adapter: board private structure to initialize
5059 * ixgbe_sw_init initializes the Adapter private data structure.
5060 * Fields are initialized based on PCI device information and
5061 * OS network device settings (MTU size).
5063 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5065 struct ixgbe_hw *hw = &adapter->hw;
5066 struct pci_dev *pdev = adapter->pdev;
5067 struct net_device *dev = adapter->netdev;
5069 #ifdef CONFIG_IXGBE_DCB
5071 struct tc_configuration *tc;
5073 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5075 /* PCI config space info */
5077 hw->vendor_id = pdev->vendor;
5078 hw->device_id = pdev->device;
5079 hw->revision_id = pdev->revision;
5080 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5081 hw->subsystem_device_id = pdev->subsystem_device;
5083 /* Set capability flags */
5084 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5085 adapter->ring_feature[RING_F_RSS].indices = rss;
5086 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5087 switch (hw->mac.type) {
5088 case ixgbe_mac_82598EB:
5089 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5090 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5091 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5093 case ixgbe_mac_82599EB:
5094 case ixgbe_mac_X540:
5095 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5096 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5097 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5098 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5099 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5100 /* Flow Director hash filters enabled */
5101 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5102 adapter->atr_sample_rate = 20;
5103 adapter->ring_feature[RING_F_FDIR].indices =
5104 IXGBE_MAX_FDIR_INDICES;
5105 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5107 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5108 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5109 adapter->ring_feature[RING_F_FCOE].indices = 0;
5110 #ifdef CONFIG_IXGBE_DCB
5111 /* Default traffic class to use for FCoE */
5112 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5114 #endif /* IXGBE_FCOE */
5120 /* n-tuple support exists, always init our spinlock */
5121 spin_lock_init(&adapter->fdir_perfect_lock);
5123 #ifdef CONFIG_IXGBE_DCB
5124 /* Configure DCB traffic classes */
5125 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5126 tc = &adapter->dcb_cfg.tc_config[j];
5127 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5128 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5129 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5130 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5131 tc->dcb_pfc = pfc_disabled;
5133 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5134 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5135 adapter->dcb_cfg.pfc_mode_enable = false;
5136 adapter->dcb_set_bitmap = 0x00;
5137 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5138 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5143 /* default flow control settings */
5144 hw->fc.requested_mode = ixgbe_fc_full;
5145 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5147 adapter->last_lfc_mode = hw->fc.current_mode;
5149 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5150 hw->fc.low_water = FC_LOW_WATER(max_frame);
5151 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5152 hw->fc.send_xon = true;
5153 hw->fc.disable_fc_autoneg = false;
5155 /* enable itr by default in dynamic mode */
5156 adapter->rx_itr_setting = 1;
5157 adapter->rx_eitr_param = 20000;
5158 adapter->tx_itr_setting = 1;
5159 adapter->tx_eitr_param = 10000;
5161 /* set defaults for eitr in MegaBytes */
5162 adapter->eitr_low = 10;
5163 adapter->eitr_high = 20;
5165 /* set default ring sizes */
5166 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5167 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5169 /* set default work limits */
5170 adapter->tx_work_limit = adapter->tx_ring_count;
5172 /* initialize eeprom parameters */
5173 if (ixgbe_init_eeprom_params_generic(hw)) {
5174 e_dev_err("EEPROM initialization failed\n");
5178 /* enable rx csum by default */
5179 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5181 /* get assigned NUMA node */
5182 adapter->node = dev_to_node(&pdev->dev);
5184 set_bit(__IXGBE_DOWN, &adapter->state);
5190 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5191 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5193 * Return 0 on success, negative on failure
5195 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5197 struct device *dev = tx_ring->dev;
5200 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5201 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5202 if (!tx_ring->tx_buffer_info)
5203 tx_ring->tx_buffer_info = vzalloc(size);
5204 if (!tx_ring->tx_buffer_info)
5207 /* round up to nearest 4K */
5208 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5209 tx_ring->size = ALIGN(tx_ring->size, 4096);
5211 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5212 &tx_ring->dma, GFP_KERNEL);
5216 tx_ring->next_to_use = 0;
5217 tx_ring->next_to_clean = 0;
5221 vfree(tx_ring->tx_buffer_info);
5222 tx_ring->tx_buffer_info = NULL;
5223 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5228 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5229 * @adapter: board private structure
5231 * If this function returns with an error, then it's possible one or
5232 * more of the rings is populated (while the rest are not). It is the
5233 * callers duty to clean those orphaned rings.
5235 * Return 0 on success, negative on failure
5237 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5241 for (i = 0; i < adapter->num_tx_queues; i++) {
5242 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5245 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5253 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5254 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5256 * Returns 0 on success, negative on failure
5258 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5260 struct device *dev = rx_ring->dev;
5263 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5264 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5265 if (!rx_ring->rx_buffer_info)
5266 rx_ring->rx_buffer_info = vzalloc(size);
5267 if (!rx_ring->rx_buffer_info)
5270 /* Round up to nearest 4K */
5271 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5272 rx_ring->size = ALIGN(rx_ring->size, 4096);
5274 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5275 &rx_ring->dma, GFP_KERNEL);
5280 rx_ring->next_to_clean = 0;
5281 rx_ring->next_to_use = 0;
5285 vfree(rx_ring->rx_buffer_info);
5286 rx_ring->rx_buffer_info = NULL;
5287 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5292 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5293 * @adapter: board private structure
5295 * If this function returns with an error, then it's possible one or
5296 * more of the rings is populated (while the rest are not). It is the
5297 * callers duty to clean those orphaned rings.
5299 * Return 0 on success, negative on failure
5301 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5305 for (i = 0; i < adapter->num_rx_queues; i++) {
5306 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5309 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5317 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5318 * @tx_ring: Tx descriptor ring for a specific queue
5320 * Free all transmit software resources
5322 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5324 ixgbe_clean_tx_ring(tx_ring);
5326 vfree(tx_ring->tx_buffer_info);
5327 tx_ring->tx_buffer_info = NULL;
5329 /* if not set, then don't free */
5333 dma_free_coherent(tx_ring->dev, tx_ring->size,
5334 tx_ring->desc, tx_ring->dma);
5336 tx_ring->desc = NULL;
5340 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5341 * @adapter: board private structure
5343 * Free all transmit software resources
5345 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5349 for (i = 0; i < adapter->num_tx_queues; i++)
5350 if (adapter->tx_ring[i]->desc)
5351 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5355 * ixgbe_free_rx_resources - Free Rx Resources
5356 * @rx_ring: ring to clean the resources from
5358 * Free all receive software resources
5360 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5362 ixgbe_clean_rx_ring(rx_ring);
5364 vfree(rx_ring->rx_buffer_info);
5365 rx_ring->rx_buffer_info = NULL;
5367 /* if not set, then don't free */
5371 dma_free_coherent(rx_ring->dev, rx_ring->size,
5372 rx_ring->desc, rx_ring->dma);
5374 rx_ring->desc = NULL;
5378 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5379 * @adapter: board private structure
5381 * Free all receive software resources
5383 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5387 for (i = 0; i < adapter->num_rx_queues; i++)
5388 if (adapter->rx_ring[i]->desc)
5389 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5393 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5394 * @netdev: network interface device structure
5395 * @new_mtu: new value for maximum frame size
5397 * Returns 0 on success, negative on failure
5399 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5401 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5402 struct ixgbe_hw *hw = &adapter->hw;
5403 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5405 /* MTU < 68 is an error and causes problems on some kernels */
5406 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5407 hw->mac.type != ixgbe_mac_X540) {
5408 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5411 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5415 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5416 /* must set new MTU before calling down or up */
5417 netdev->mtu = new_mtu;
5419 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5420 hw->fc.low_water = FC_LOW_WATER(max_frame);
5422 if (netif_running(netdev))
5423 ixgbe_reinit_locked(adapter);
5429 * ixgbe_open - Called when a network interface is made active
5430 * @netdev: network interface device structure
5432 * Returns 0 on success, negative value on failure
5434 * The open entry point is called when a network interface is made
5435 * active by the system (IFF_UP). At this point all resources needed
5436 * for transmit and receive operations are allocated, the interrupt
5437 * handler is registered with the OS, the watchdog timer is started,
5438 * and the stack is notified that the interface is ready.
5440 static int ixgbe_open(struct net_device *netdev)
5442 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5445 /* disallow open during test */
5446 if (test_bit(__IXGBE_TESTING, &adapter->state))
5449 netif_carrier_off(netdev);
5451 /* allocate transmit descriptors */
5452 err = ixgbe_setup_all_tx_resources(adapter);
5456 /* allocate receive descriptors */
5457 err = ixgbe_setup_all_rx_resources(adapter);
5461 ixgbe_configure(adapter);
5463 err = ixgbe_request_irq(adapter);
5467 err = ixgbe_up_complete(adapter);
5471 netif_tx_start_all_queues(netdev);
5476 ixgbe_release_hw_control(adapter);
5477 ixgbe_free_irq(adapter);
5480 ixgbe_free_all_rx_resources(adapter);
5482 ixgbe_free_all_tx_resources(adapter);
5483 ixgbe_reset(adapter);
5489 * ixgbe_close - Disables a network interface
5490 * @netdev: network interface device structure
5492 * Returns 0, this is not allowed to fail
5494 * The close entry point is called when an interface is de-activated
5495 * by the OS. The hardware is still under the drivers control, but
5496 * needs to be disabled. A global MAC reset is issued to stop the
5497 * hardware, and all transmit and receive resources are freed.
5499 static int ixgbe_close(struct net_device *netdev)
5501 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5503 ixgbe_down(adapter);
5504 ixgbe_free_irq(adapter);
5506 ixgbe_fdir_filter_exit(adapter);
5508 ixgbe_free_all_tx_resources(adapter);
5509 ixgbe_free_all_rx_resources(adapter);
5511 ixgbe_release_hw_control(adapter);
5517 static int ixgbe_resume(struct pci_dev *pdev)
5519 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5520 struct net_device *netdev = adapter->netdev;
5523 pci_set_power_state(pdev, PCI_D0);
5524 pci_restore_state(pdev);
5526 * pci_restore_state clears dev->state_saved so call
5527 * pci_save_state to restore it.
5529 pci_save_state(pdev);
5531 err = pci_enable_device_mem(pdev);
5533 e_dev_err("Cannot enable PCI device from suspend\n");
5536 pci_set_master(pdev);
5538 pci_wake_from_d3(pdev, false);
5540 err = ixgbe_init_interrupt_scheme(adapter);
5542 e_dev_err("Cannot initialize interrupts for device\n");
5546 ixgbe_reset(adapter);
5548 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5550 if (netif_running(netdev)) {
5551 err = ixgbe_open(netdev);
5556 netif_device_attach(netdev);
5560 #endif /* CONFIG_PM */
5562 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5564 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5565 struct net_device *netdev = adapter->netdev;
5566 struct ixgbe_hw *hw = &adapter->hw;
5568 u32 wufc = adapter->wol;
5573 netif_device_detach(netdev);
5575 if (netif_running(netdev)) {
5576 ixgbe_down(adapter);
5577 ixgbe_free_irq(adapter);
5578 ixgbe_free_all_tx_resources(adapter);
5579 ixgbe_free_all_rx_resources(adapter);
5582 ixgbe_clear_interrupt_scheme(adapter);
5584 kfree(adapter->ixgbe_ieee_pfc);
5585 kfree(adapter->ixgbe_ieee_ets);
5589 retval = pci_save_state(pdev);
5595 ixgbe_set_rx_mode(netdev);
5597 /* turn on all-multi mode if wake on multicast is enabled */
5598 if (wufc & IXGBE_WUFC_MC) {
5599 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5600 fctrl |= IXGBE_FCTRL_MPE;
5601 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5604 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5605 ctrl |= IXGBE_CTRL_GIO_DIS;
5606 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5608 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5610 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5611 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5614 switch (hw->mac.type) {
5615 case ixgbe_mac_82598EB:
5616 pci_wake_from_d3(pdev, false);
5618 case ixgbe_mac_82599EB:
5619 case ixgbe_mac_X540:
5620 pci_wake_from_d3(pdev, !!wufc);
5626 *enable_wake = !!wufc;
5628 ixgbe_release_hw_control(adapter);
5630 pci_disable_device(pdev);
5636 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5641 retval = __ixgbe_shutdown(pdev, &wake);
5646 pci_prepare_to_sleep(pdev);
5648 pci_wake_from_d3(pdev, false);
5649 pci_set_power_state(pdev, PCI_D3hot);
5654 #endif /* CONFIG_PM */
5656 static void ixgbe_shutdown(struct pci_dev *pdev)
5660 __ixgbe_shutdown(pdev, &wake);
5662 if (system_state == SYSTEM_POWER_OFF) {
5663 pci_wake_from_d3(pdev, wake);
5664 pci_set_power_state(pdev, PCI_D3hot);
5669 * ixgbe_update_stats - Update the board statistics counters.
5670 * @adapter: board private structure
5672 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5674 struct net_device *netdev = adapter->netdev;
5675 struct ixgbe_hw *hw = &adapter->hw;
5676 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5678 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5679 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5680 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5681 u64 bytes = 0, packets = 0;
5683 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5684 test_bit(__IXGBE_RESETTING, &adapter->state))
5687 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5690 for (i = 0; i < 16; i++)
5691 adapter->hw_rx_no_dma_resources +=
5692 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5693 for (i = 0; i < adapter->num_rx_queues; i++) {
5694 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5695 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5697 adapter->rsc_total_count = rsc_count;
5698 adapter->rsc_total_flush = rsc_flush;
5701 for (i = 0; i < adapter->num_rx_queues; i++) {
5702 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5703 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5704 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5705 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5706 bytes += rx_ring->stats.bytes;
5707 packets += rx_ring->stats.packets;
5709 adapter->non_eop_descs = non_eop_descs;
5710 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5711 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5712 netdev->stats.rx_bytes = bytes;
5713 netdev->stats.rx_packets = packets;
5717 /* gather some stats to the adapter struct that are per queue */
5718 for (i = 0; i < adapter->num_tx_queues; i++) {
5719 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5720 restart_queue += tx_ring->tx_stats.restart_queue;
5721 tx_busy += tx_ring->tx_stats.tx_busy;
5722 bytes += tx_ring->stats.bytes;
5723 packets += tx_ring->stats.packets;
5725 adapter->restart_queue = restart_queue;
5726 adapter->tx_busy = tx_busy;
5727 netdev->stats.tx_bytes = bytes;
5728 netdev->stats.tx_packets = packets;
5730 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5731 for (i = 0; i < 8; i++) {
5732 /* for packet buffers not used, the register should read 0 */
5733 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5735 hwstats->mpc[i] += mpc;
5736 total_mpc += hwstats->mpc[i];
5737 if (hw->mac.type == ixgbe_mac_82598EB)
5738 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5739 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5740 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5741 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5742 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5743 switch (hw->mac.type) {
5744 case ixgbe_mac_82598EB:
5745 hwstats->pxonrxc[i] +=
5746 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5748 case ixgbe_mac_82599EB:
5749 case ixgbe_mac_X540:
5750 hwstats->pxonrxc[i] +=
5751 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5756 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5757 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5759 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5760 /* work around hardware counting issue */
5761 hwstats->gprc -= missed_rx;
5763 ixgbe_update_xoff_received(adapter);
5765 /* 82598 hardware only has a 32 bit counter in the high register */
5766 switch (hw->mac.type) {
5767 case ixgbe_mac_82598EB:
5768 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5769 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5770 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5771 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5773 case ixgbe_mac_X540:
5774 /* OS2BMC stats are X540 only*/
5775 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5776 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5777 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5778 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5779 case ixgbe_mac_82599EB:
5780 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5781 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5782 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5783 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5784 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5785 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5786 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5787 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5788 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5790 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5791 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5792 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5793 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5794 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5795 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5796 #endif /* IXGBE_FCOE */
5801 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5802 hwstats->bprc += bprc;
5803 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5804 if (hw->mac.type == ixgbe_mac_82598EB)
5805 hwstats->mprc -= bprc;
5806 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5807 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5808 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5809 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5810 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5811 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5812 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5813 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5814 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5815 hwstats->lxontxc += lxon;
5816 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5817 hwstats->lxofftxc += lxoff;
5818 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5819 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5820 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5822 * 82598 errata - tx of flow control packets is included in tx counters
5824 xon_off_tot = lxon + lxoff;
5825 hwstats->gptc -= xon_off_tot;
5826 hwstats->mptc -= xon_off_tot;
5827 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5828 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5829 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5830 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5831 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5832 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5833 hwstats->ptc64 -= xon_off_tot;
5834 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5835 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5836 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5837 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5838 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5839 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5841 /* Fill out the OS statistics structure */
5842 netdev->stats.multicast = hwstats->mprc;
5845 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5846 netdev->stats.rx_dropped = 0;
5847 netdev->stats.rx_length_errors = hwstats->rlec;
5848 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5849 netdev->stats.rx_missed_errors = total_mpc;
5853 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5854 * @adapter - pointer to the device adapter structure
5856 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5858 struct ixgbe_hw *hw = &adapter->hw;
5861 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5864 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5866 /* if interface is down do nothing */
5867 if (test_bit(__IXGBE_DOWN, &adapter->state))
5870 /* do nothing if we are not using signature filters */
5871 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5874 adapter->fdir_overflow++;
5876 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5877 for (i = 0; i < adapter->num_tx_queues; i++)
5878 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5879 &(adapter->tx_ring[i]->state));
5880 /* re-enable flow director interrupts */
5881 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5883 e_err(probe, "failed to finish FDIR re-initialization, "
5884 "ignored adding FDIR ATR filters\n");
5889 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5890 * @adapter - pointer to the device adapter structure
5892 * This function serves two purposes. First it strobes the interrupt lines
5893 * in order to make certain interrupts are occuring. Secondly it sets the
5894 * bits needed to check for TX hangs. As a result we should immediately
5895 * determine if a hang has occured.
5897 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5899 struct ixgbe_hw *hw = &adapter->hw;
5903 /* If we're down or resetting, just bail */
5904 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5905 test_bit(__IXGBE_RESETTING, &adapter->state))
5908 /* Force detection of hung controller */
5909 if (netif_carrier_ok(adapter->netdev)) {
5910 for (i = 0; i < adapter->num_tx_queues; i++)
5911 set_check_for_tx_hang(adapter->tx_ring[i]);
5914 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5916 * for legacy and MSI interrupts don't set any bits
5917 * that are enabled for EIAM, because this operation
5918 * would set *both* EIMS and EICS for any bit in EIAM
5920 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5921 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5923 /* get one bit for every active tx/rx interrupt vector */
5924 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5925 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5926 if (qv->rx.count || qv->tx.count)
5927 eics |= ((u64)1 << i);
5931 /* Cause software interrupt to ensure rings are cleaned */
5932 ixgbe_irq_rearm_queues(adapter, eics);
5937 * ixgbe_watchdog_update_link - update the link status
5938 * @adapter - pointer to the device adapter structure
5939 * @link_speed - pointer to a u32 to store the link_speed
5941 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5943 struct ixgbe_hw *hw = &adapter->hw;
5944 u32 link_speed = adapter->link_speed;
5945 bool link_up = adapter->link_up;
5948 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5951 if (hw->mac.ops.check_link) {
5952 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5954 /* always assume link is up, if no check link function */
5955 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5959 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5960 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5961 hw->mac.ops.fc_enable(hw, i);
5963 hw->mac.ops.fc_enable(hw, 0);
5968 time_after(jiffies, (adapter->link_check_timeout +
5969 IXGBE_TRY_LINK_TIMEOUT))) {
5970 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5971 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5972 IXGBE_WRITE_FLUSH(hw);
5975 adapter->link_up = link_up;
5976 adapter->link_speed = link_speed;
5980 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5981 * print link up message
5982 * @adapter - pointer to the device adapter structure
5984 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
5986 struct net_device *netdev = adapter->netdev;
5987 struct ixgbe_hw *hw = &adapter->hw;
5988 u32 link_speed = adapter->link_speed;
5989 bool flow_rx, flow_tx;
5991 /* only continue if link was previously down */
5992 if (netif_carrier_ok(netdev))
5995 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
5997 switch (hw->mac.type) {
5998 case ixgbe_mac_82598EB: {
5999 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6000 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6001 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6002 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6005 case ixgbe_mac_X540:
6006 case ixgbe_mac_82599EB: {
6007 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6008 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6009 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6010 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6018 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6019 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6021 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6023 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6026 ((flow_rx && flow_tx) ? "RX/TX" :
6028 (flow_tx ? "TX" : "None"))));
6030 netif_carrier_on(netdev);
6031 ixgbe_check_vf_rate_limit(adapter);
6035 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6036 * print link down message
6037 * @adapter - pointer to the adapter structure
6039 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6041 struct net_device *netdev = adapter->netdev;
6042 struct ixgbe_hw *hw = &adapter->hw;
6044 adapter->link_up = false;
6045 adapter->link_speed = 0;
6047 /* only continue if link was up previously */
6048 if (!netif_carrier_ok(netdev))
6051 /* poll for SFP+ cable when link is down */
6052 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6053 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6055 e_info(drv, "NIC Link is Down\n");
6056 netif_carrier_off(netdev);
6060 * ixgbe_watchdog_flush_tx - flush queues on link down
6061 * @adapter - pointer to the device adapter structure
6063 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6066 int some_tx_pending = 0;
6068 if (!netif_carrier_ok(adapter->netdev)) {
6069 for (i = 0; i < adapter->num_tx_queues; i++) {
6070 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6071 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6072 some_tx_pending = 1;
6077 if (some_tx_pending) {
6078 /* We've lost link, so the controller stops DMA,
6079 * but we've got queued Tx work that's never going
6080 * to get done, so reset controller to flush Tx.
6081 * (Do the reset outside of interrupt context).
6083 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6088 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6092 /* Do not perform spoof check for 82598 */
6093 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6096 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6099 * ssvpc register is cleared on read, if zero then no
6100 * spoofed packets in the last interval.
6105 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6109 * ixgbe_watchdog_subtask - check and bring link up
6110 * @adapter - pointer to the device adapter structure
6112 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6114 /* if interface is down do nothing */
6115 if (test_bit(__IXGBE_DOWN, &adapter->state))
6118 ixgbe_watchdog_update_link(adapter);
6120 if (adapter->link_up)
6121 ixgbe_watchdog_link_is_up(adapter);
6123 ixgbe_watchdog_link_is_down(adapter);
6125 ixgbe_spoof_check(adapter);
6126 ixgbe_update_stats(adapter);
6128 ixgbe_watchdog_flush_tx(adapter);
6132 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6133 * @adapter - the ixgbe adapter structure
6135 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6137 struct ixgbe_hw *hw = &adapter->hw;
6140 /* not searching for SFP so there is nothing to do here */
6141 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6142 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6145 /* someone else is in init, wait until next service event */
6146 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6149 err = hw->phy.ops.identify_sfp(hw);
6150 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6153 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6154 /* If no cable is present, then we need to reset
6155 * the next time we find a good cable. */
6156 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6163 /* exit if reset not needed */
6164 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6167 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6170 * A module may be identified correctly, but the EEPROM may not have
6171 * support for that module. setup_sfp() will fail in that case, so
6172 * we should not allow that module to load.
6174 if (hw->mac.type == ixgbe_mac_82598EB)
6175 err = hw->phy.ops.reset(hw);
6177 err = hw->mac.ops.setup_sfp(hw);
6179 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6182 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6183 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6186 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6188 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6189 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6190 e_dev_err("failed to initialize because an unsupported "
6191 "SFP+ module type was detected.\n");
6192 e_dev_err("Reload the driver after installing a "
6193 "supported module.\n");
6194 unregister_netdev(adapter->netdev);
6199 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6200 * @adapter - the ixgbe adapter structure
6202 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6204 struct ixgbe_hw *hw = &adapter->hw;
6208 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6211 /* someone else is in init, wait until next service event */
6212 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6215 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6217 autoneg = hw->phy.autoneg_advertised;
6218 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6219 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6220 hw->mac.autotry_restart = false;
6221 if (hw->mac.ops.setup_link)
6222 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6224 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6225 adapter->link_check_timeout = jiffies;
6226 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6230 * ixgbe_service_timer - Timer Call-back
6231 * @data: pointer to adapter cast into an unsigned long
6233 static void ixgbe_service_timer(unsigned long data)
6235 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6236 unsigned long next_event_offset;
6238 /* poll faster when waiting for link */
6239 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6240 next_event_offset = HZ / 10;
6242 next_event_offset = HZ * 2;
6244 /* Reset the timer */
6245 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6247 ixgbe_service_event_schedule(adapter);
6250 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6252 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6255 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6257 /* If we're already down or resetting, just bail */
6258 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6259 test_bit(__IXGBE_RESETTING, &adapter->state))
6262 ixgbe_dump(adapter);
6263 netdev_err(adapter->netdev, "Reset adapter\n");
6264 adapter->tx_timeout_count++;
6266 ixgbe_reinit_locked(adapter);
6270 * ixgbe_service_task - manages and runs subtasks
6271 * @work: pointer to work_struct containing our data
6273 static void ixgbe_service_task(struct work_struct *work)
6275 struct ixgbe_adapter *adapter = container_of(work,
6276 struct ixgbe_adapter,
6279 ixgbe_reset_subtask(adapter);
6280 ixgbe_sfp_detection_subtask(adapter);
6281 ixgbe_sfp_link_config_subtask(adapter);
6282 ixgbe_check_overtemp_subtask(adapter);
6283 ixgbe_watchdog_subtask(adapter);
6284 ixgbe_fdir_reinit_subtask(adapter);
6285 ixgbe_check_hang_subtask(adapter);
6287 ixgbe_service_event_complete(adapter);
6290 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6291 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6293 struct ixgbe_adv_tx_context_desc *context_desc;
6294 u16 i = tx_ring->next_to_use;
6296 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6299 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6301 /* set bits to identify this as an advanced context descriptor */
6302 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6304 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6305 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6306 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6307 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6310 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6311 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6314 u32 vlan_macip_lens, type_tucmd;
6315 u32 mss_l4len_idx, l4len;
6317 if (!skb_is_gso(skb))
6320 if (skb_header_cloned(skb)) {
6321 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6326 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6327 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6329 if (protocol == __constant_htons(ETH_P_IP)) {
6330 struct iphdr *iph = ip_hdr(skb);
6333 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6337 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6338 } else if (skb_is_gso_v6(skb)) {
6339 ipv6_hdr(skb)->payload_len = 0;
6340 tcp_hdr(skb)->check =
6341 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6342 &ipv6_hdr(skb)->daddr,
6346 l4len = tcp_hdrlen(skb);
6347 *hdr_len = skb_transport_offset(skb) + l4len;
6349 /* mss_l4len_id: use 1 as index for TSO */
6350 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6351 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6352 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6354 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6355 vlan_macip_lens = skb_network_header_len(skb);
6356 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6357 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6359 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6365 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6366 struct sk_buff *skb, u32 tx_flags,
6369 u32 vlan_macip_lens = 0;
6370 u32 mss_l4len_idx = 0;
6373 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6374 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN))
6379 case __constant_htons(ETH_P_IP):
6380 vlan_macip_lens |= skb_network_header_len(skb);
6381 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6382 l4_hdr = ip_hdr(skb)->protocol;
6384 case __constant_htons(ETH_P_IPV6):
6385 vlan_macip_lens |= skb_network_header_len(skb);
6386 l4_hdr = ipv6_hdr(skb)->nexthdr;
6389 if (unlikely(net_ratelimit())) {
6390 dev_warn(tx_ring->dev,
6391 "partial checksum but proto=%x!\n",
6399 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6400 mss_l4len_idx = tcp_hdrlen(skb) <<
6401 IXGBE_ADVTXD_L4LEN_SHIFT;
6404 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6405 mss_l4len_idx = sizeof(struct sctphdr) <<
6406 IXGBE_ADVTXD_L4LEN_SHIFT;
6409 mss_l4len_idx = sizeof(struct udphdr) <<
6410 IXGBE_ADVTXD_L4LEN_SHIFT;
6413 if (unlikely(net_ratelimit())) {
6414 dev_warn(tx_ring->dev,
6415 "partial checksum but l4 proto=%x!\n",
6422 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6423 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6425 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6426 type_tucmd, mss_l4len_idx);
6428 return (skb->ip_summed == CHECKSUM_PARTIAL);
6431 static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
6433 /* set type for advanced descriptor with frame checksum insertion */
6434 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6435 IXGBE_ADVTXD_DCMD_IFCS |
6436 IXGBE_ADVTXD_DCMD_DEXT);
6438 /* set HW vlan bit if vlan is present */
6439 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
6440 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
6442 /* set segmentation enable bits for TSO/FSO */
6444 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6446 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6448 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
6453 static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6455 __le32 olinfo_status =
6456 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
6458 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6459 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6460 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6461 /* enble IPv4 checksum for TSO */
6462 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6463 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
6466 /* enable L4 checksum for TSO and TX checksum offload */
6467 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6468 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
6471 /* use index 1 context for FCOE/FSO */
6472 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6473 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6474 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6477 return olinfo_status;
6480 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6483 static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6484 struct sk_buff *skb,
6485 struct ixgbe_tx_buffer *first,
6489 struct device *dev = tx_ring->dev;
6490 struct ixgbe_tx_buffer *tx_buffer_info;
6491 union ixgbe_adv_tx_desc *tx_desc;
6493 __le32 cmd_type, olinfo_status;
6494 struct skb_frag_struct *frag;
6496 unsigned int data_len = skb->data_len;
6497 unsigned int size = skb_headlen(skb);
6499 u32 paylen = skb->len - hdr_len;
6500 u16 i = tx_ring->next_to_use;
6504 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6505 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6506 data_len -= sizeof(struct fcoe_crc_eof);
6508 size -= sizeof(struct fcoe_crc_eof) - data_len;
6514 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6515 if (dma_mapping_error(dev, dma))
6518 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6519 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
6521 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6524 while (size > IXGBE_MAX_DATA_PER_TXD) {
6525 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6526 tx_desc->read.cmd_type_len =
6527 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6528 tx_desc->read.olinfo_status = olinfo_status;
6530 offset += IXGBE_MAX_DATA_PER_TXD;
6531 size -= IXGBE_MAX_DATA_PER_TXD;
6535 if (i == tx_ring->count) {
6536 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6541 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6542 tx_buffer_info->length = offset + size;
6543 tx_buffer_info->tx_flags = tx_flags;
6544 tx_buffer_info->dma = dma;
6546 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6547 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6548 tx_desc->read.olinfo_status = olinfo_status;
6553 frag = &skb_shinfo(skb)->frags[f];
6555 size = min_t(unsigned int, data_len, frag->size);
6563 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
6565 dma = dma_map_page(dev, frag->page, frag->page_offset,
6566 size, DMA_TO_DEVICE);
6567 if (dma_mapping_error(dev, dma))
6572 if (i == tx_ring->count) {
6573 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6578 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
6581 if (i == tx_ring->count)
6584 tx_ring->next_to_use = i;
6586 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6587 gso_segs = skb_shinfo(skb)->gso_segs;
6589 /* adjust for FCoE Sequence Offload */
6590 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6591 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6592 skb_shinfo(skb)->gso_size);
6593 #endif /* IXGBE_FCOE */
6597 /* multiply data chunks by size of headers */
6598 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6599 tx_buffer_info->gso_segs = gso_segs;
6600 tx_buffer_info->skb = skb;
6602 /* set the timestamp */
6603 first->time_stamp = jiffies;
6606 * Force memory writes to complete before letting h/w
6607 * know there are new descriptors to fetch. (Only
6608 * applicable for weak-ordered memory model archs,
6613 /* set next_to_watch value indicating a packet is present */
6614 first->next_to_watch = tx_desc;
6616 /* notify HW of packet */
6617 writel(i, tx_ring->tail);
6621 dev_err(dev, "TX DMA map failed\n");
6623 /* clear dma mappings for failed tx_buffer_info map */
6625 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6626 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6627 if (tx_buffer_info == first)
6634 dev_kfree_skb_any(skb);
6636 tx_ring->next_to_use = i;
6639 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6640 u32 tx_flags, __be16 protocol)
6642 struct ixgbe_q_vector *q_vector = ring->q_vector;
6643 union ixgbe_atr_hash_dword input = { .dword = 0 };
6644 union ixgbe_atr_hash_dword common = { .dword = 0 };
6646 unsigned char *network;
6648 struct ipv6hdr *ipv6;
6653 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6657 /* do nothing if sampling is disabled */
6658 if (!ring->atr_sample_rate)
6663 /* snag network header to get L4 type and address */
6664 hdr.network = skb_network_header(skb);
6666 /* Currently only IPv4/IPv6 with TCP is supported */
6667 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6668 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6669 (protocol != __constant_htons(ETH_P_IP) ||
6670 hdr.ipv4->protocol != IPPROTO_TCP))
6675 /* skip this packet since it is invalid or the socket is closing */
6679 /* sample on all syn packets or once every atr sample count */
6680 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6683 /* reset sample count */
6684 ring->atr_count = 0;
6686 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6689 * src and dst are inverted, think how the receiver sees them
6691 * The input is broken into two sections, a non-compressed section
6692 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6693 * is XORed together and stored in the compressed dword.
6695 input.formatted.vlan_id = vlan_id;
6698 * since src port and flex bytes occupy the same word XOR them together
6699 * and write the value to source port portion of compressed dword
6701 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
6702 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6704 common.port.src ^= th->dest ^ protocol;
6705 common.port.dst ^= th->source;
6707 if (protocol == __constant_htons(ETH_P_IP)) {
6708 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6709 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6711 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6712 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6713 hdr.ipv6->saddr.s6_addr32[1] ^
6714 hdr.ipv6->saddr.s6_addr32[2] ^
6715 hdr.ipv6->saddr.s6_addr32[3] ^
6716 hdr.ipv6->daddr.s6_addr32[0] ^
6717 hdr.ipv6->daddr.s6_addr32[1] ^
6718 hdr.ipv6->daddr.s6_addr32[2] ^
6719 hdr.ipv6->daddr.s6_addr32[3];
6722 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6723 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6724 input, common, ring->queue_index);
6727 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6729 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6730 /* Herbert's original patch had:
6731 * smp_mb__after_netif_stop_queue();
6732 * but since that doesn't exist yet, just open code it. */
6735 /* We need to check again in a case another CPU has just
6736 * made room available. */
6737 if (likely(ixgbe_desc_unused(tx_ring) < size))
6740 /* A reprieve! - use start_queue because it doesn't call schedule */
6741 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6742 ++tx_ring->tx_stats.restart_queue;
6746 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6748 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6750 return __ixgbe_maybe_stop_tx(tx_ring, size);
6753 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6755 struct ixgbe_adapter *adapter = netdev_priv(dev);
6756 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6759 __be16 protocol = vlan_get_protocol(skb);
6761 if (((protocol == htons(ETH_P_FCOE)) ||
6762 (protocol == htons(ETH_P_FIP))) &&
6763 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6764 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6765 txq += adapter->ring_feature[RING_F_FCOE].mask;
6770 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6771 while (unlikely(txq >= dev->real_num_tx_queues))
6772 txq -= dev->real_num_tx_queues;
6776 return skb_tx_hash(dev, skb);
6779 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6780 struct ixgbe_adapter *adapter,
6781 struct ixgbe_ring *tx_ring)
6783 struct ixgbe_tx_buffer *first;
6786 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6789 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6790 __be16 protocol = skb->protocol;
6794 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6795 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6796 * + 2 desc gap to keep tail from touching head,
6797 * + 1 desc for context descriptor,
6798 * otherwise try next time
6800 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6801 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6802 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6804 count += skb_shinfo(skb)->nr_frags;
6806 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6807 tx_ring->tx_stats.tx_busy++;
6808 return NETDEV_TX_BUSY;
6811 /* if we have a HW VLAN tag being added default to the HW one */
6812 if (vlan_tx_tag_present(skb)) {
6813 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6814 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6815 /* else if it is a SW VLAN check the next protocol and store the tag */
6816 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6817 struct vlan_hdr *vhdr, _vhdr;
6818 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6822 protocol = vhdr->h_vlan_encapsulated_proto;
6823 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6824 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6827 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
6828 skb->priority != TC_PRIO_CONTROL) {
6829 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6830 tx_flags |= tx_ring->dcb_tc <<
6831 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
6832 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6833 struct vlan_ethhdr *vhdr;
6834 if (skb_header_cloned(skb) &&
6835 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6837 vhdr = (struct vlan_ethhdr *)skb->data;
6838 vhdr->h_vlan_TCI = htons(tx_flags >>
6839 IXGBE_TX_FLAGS_VLAN_SHIFT);
6841 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6845 /* record the location of the first descriptor for this packet */
6846 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6849 /* setup tx offload for FCoE */
6850 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6851 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6852 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6856 tx_flags |= IXGBE_TX_FLAGS_FSO |
6857 IXGBE_TX_FLAGS_FCOE;
6859 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6864 #endif /* IXGBE_FCOE */
6865 /* setup IPv4/IPv6 offloads */
6866 if (protocol == __constant_htons(ETH_P_IP))
6867 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6869 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6873 tx_flags |= IXGBE_TX_FLAGS_TSO;
6874 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6875 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6877 /* add the ATR filter if ATR is on */
6878 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6879 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6883 #endif /* IXGBE_FCOE */
6884 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6886 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6888 return NETDEV_TX_OK;
6891 dev_kfree_skb_any(skb);
6892 return NETDEV_TX_OK;
6895 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6897 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6898 struct ixgbe_ring *tx_ring;
6900 tx_ring = adapter->tx_ring[skb->queue_mapping];
6901 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6905 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6906 * @netdev: network interface device structure
6907 * @p: pointer to an address structure
6909 * Returns 0 on success, negative on failure
6911 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6913 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6914 struct ixgbe_hw *hw = &adapter->hw;
6915 struct sockaddr *addr = p;
6917 if (!is_valid_ether_addr(addr->sa_data))
6918 return -EADDRNOTAVAIL;
6920 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6921 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6923 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6930 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6932 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6933 struct ixgbe_hw *hw = &adapter->hw;
6937 if (prtad != hw->phy.mdio.prtad)
6939 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6945 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6946 u16 addr, u16 value)
6948 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6949 struct ixgbe_hw *hw = &adapter->hw;
6951 if (prtad != hw->phy.mdio.prtad)
6953 return hw->phy.ops.write_reg(hw, addr, devad, value);
6956 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6958 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6960 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6964 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6966 * @netdev: network interface device structure
6968 * Returns non-zero on failure
6970 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6973 struct ixgbe_adapter *adapter = netdev_priv(dev);
6974 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6976 if (is_valid_ether_addr(mac->san_addr)) {
6978 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6985 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6987 * @netdev: network interface device structure
6989 * Returns non-zero on failure
6991 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6994 struct ixgbe_adapter *adapter = netdev_priv(dev);
6995 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6997 if (is_valid_ether_addr(mac->san_addr)) {
6999 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7005 #ifdef CONFIG_NET_POLL_CONTROLLER
7007 * Polling 'interrupt' - used by things like netconsole to send skbs
7008 * without having to re-enable interrupts. It's not called while
7009 * the interrupt routine is executing.
7011 static void ixgbe_netpoll(struct net_device *netdev)
7013 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7016 /* if interface is down do nothing */
7017 if (test_bit(__IXGBE_DOWN, &adapter->state))
7020 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7021 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7022 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7023 for (i = 0; i < num_q_vectors; i++) {
7024 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7025 ixgbe_msix_clean_many(0, q_vector);
7028 ixgbe_intr(adapter->pdev->irq, netdev);
7030 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7034 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7035 struct rtnl_link_stats64 *stats)
7037 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7041 for (i = 0; i < adapter->num_rx_queues; i++) {
7042 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7048 start = u64_stats_fetch_begin_bh(&ring->syncp);
7049 packets = ring->stats.packets;
7050 bytes = ring->stats.bytes;
7051 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7052 stats->rx_packets += packets;
7053 stats->rx_bytes += bytes;
7057 for (i = 0; i < adapter->num_tx_queues; i++) {
7058 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7064 start = u64_stats_fetch_begin_bh(&ring->syncp);
7065 packets = ring->stats.packets;
7066 bytes = ring->stats.bytes;
7067 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7068 stats->tx_packets += packets;
7069 stats->tx_bytes += bytes;
7073 /* following stats updated by ixgbe_watchdog_task() */
7074 stats->multicast = netdev->stats.multicast;
7075 stats->rx_errors = netdev->stats.rx_errors;
7076 stats->rx_length_errors = netdev->stats.rx_length_errors;
7077 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7078 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7082 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7083 * #adapter: pointer to ixgbe_adapter
7084 * @tc: number of traffic classes currently enabled
7086 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7087 * 802.1Q priority maps to a packet buffer that exists.
7089 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7091 struct ixgbe_hw *hw = &adapter->hw;
7095 /* 82598 have a static priority to TC mapping that can not
7096 * be changed so no validation is needed.
7098 if (hw->mac.type == ixgbe_mac_82598EB)
7101 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7104 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7105 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7107 /* If up2tc is out of bounds default to zero */
7109 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7113 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7119 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7122 * @netdev: net device to configure
7123 * @tc: number of traffic classes to enable
7125 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7127 struct ixgbe_adapter *adapter = netdev_priv(dev);
7128 struct ixgbe_hw *hw = &adapter->hw;
7130 /* If DCB is anabled do not remove traffic classes, multiple
7131 * traffic classes are required to implement DCB
7133 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7136 /* Hardware supports up to 8 traffic classes */
7137 if (tc > MAX_TRAFFIC_CLASS ||
7138 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7141 /* Hardware has to reinitialize queues and interrupts to
7142 * match packet buffer alignment. Unfortunantly, the
7143 * hardware is not flexible enough to do this dynamically.
7145 if (netif_running(dev))
7147 ixgbe_clear_interrupt_scheme(adapter);
7150 netdev_set_num_tc(dev, tc);
7152 netdev_reset_tc(dev);
7154 ixgbe_init_interrupt_scheme(adapter);
7155 ixgbe_validate_rtr(adapter, tc);
7156 if (netif_running(dev))
7162 void ixgbe_do_reset(struct net_device *netdev)
7164 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7166 if (netif_running(netdev))
7167 ixgbe_reinit_locked(adapter);
7169 ixgbe_reset(adapter);
7172 static u32 ixgbe_fix_features(struct net_device *netdev, u32 data)
7174 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7177 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7178 data &= ~NETIF_F_HW_VLAN_RX;
7181 /* return error if RXHASH is being enabled when RSS is not supported */
7182 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7183 data &= ~NETIF_F_RXHASH;
7185 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7186 if (!(data & NETIF_F_RXCSUM))
7187 data &= ~NETIF_F_LRO;
7189 /* Turn off LRO if not RSC capable or invalid ITR settings */
7190 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7191 data &= ~NETIF_F_LRO;
7192 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7193 (adapter->rx_itr_setting != 1 &&
7194 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7195 data &= ~NETIF_F_LRO;
7196 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7202 static int ixgbe_set_features(struct net_device *netdev, u32 data)
7204 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7205 bool need_reset = false;
7207 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7208 if (!(data & NETIF_F_RXCSUM))
7209 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7211 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7213 /* Make sure RSC matches LRO, reset if change */
7214 if (!!(data & NETIF_F_LRO) !=
7215 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7216 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7217 switch (adapter->hw.mac.type) {
7218 case ixgbe_mac_X540:
7219 case ixgbe_mac_82599EB:
7228 * Check if Flow Director n-tuple support was enabled or disabled. If
7229 * the state changed, we need to reset.
7231 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7232 /* turn off ATR, enable perfect filters and reset */
7233 if (data & NETIF_F_NTUPLE) {
7234 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7235 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7238 } else if (!(data & NETIF_F_NTUPLE)) {
7239 /* turn off Flow Director, set ATR and reset */
7240 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7241 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7242 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7243 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7248 ixgbe_do_reset(netdev);
7254 static const struct net_device_ops ixgbe_netdev_ops = {
7255 .ndo_open = ixgbe_open,
7256 .ndo_stop = ixgbe_close,
7257 .ndo_start_xmit = ixgbe_xmit_frame,
7258 .ndo_select_queue = ixgbe_select_queue,
7259 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7260 .ndo_validate_addr = eth_validate_addr,
7261 .ndo_set_mac_address = ixgbe_set_mac,
7262 .ndo_change_mtu = ixgbe_change_mtu,
7263 .ndo_tx_timeout = ixgbe_tx_timeout,
7264 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7265 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7266 .ndo_do_ioctl = ixgbe_ioctl,
7267 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7268 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7269 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7270 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7271 .ndo_get_stats64 = ixgbe_get_stats64,
7272 .ndo_setup_tc = ixgbe_setup_tc,
7273 #ifdef CONFIG_NET_POLL_CONTROLLER
7274 .ndo_poll_controller = ixgbe_netpoll,
7277 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7278 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7279 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7280 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7281 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7282 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7283 #endif /* IXGBE_FCOE */
7284 .ndo_set_features = ixgbe_set_features,
7285 .ndo_fix_features = ixgbe_fix_features,
7288 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7289 const struct ixgbe_info *ii)
7291 #ifdef CONFIG_PCI_IOV
7292 struct ixgbe_hw *hw = &adapter->hw;
7294 int num_vf_macvlans, i;
7295 struct vf_macvlans *mv_list;
7297 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7300 /* The 82599 supports up to 64 VFs per physical function
7301 * but this implementation limits allocation to 63 so that
7302 * basic networking resources are still available to the
7305 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7306 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7307 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7309 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7313 num_vf_macvlans = hw->mac.num_rar_entries -
7314 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7316 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7317 sizeof(struct vf_macvlans),
7320 /* Initialize list of VF macvlans */
7321 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7322 for (i = 0; i < num_vf_macvlans; i++) {
7324 mv_list->free = true;
7325 mv_list->rar_entry = hw->mac.num_rar_entries -
7326 (i + adapter->num_vfs + 1);
7327 list_add(&mv_list->l, &adapter->vf_mvs.l);
7332 /* If call to enable VFs succeeded then allocate memory
7333 * for per VF control structures.
7336 kcalloc(adapter->num_vfs,
7337 sizeof(struct vf_data_storage), GFP_KERNEL);
7338 if (adapter->vfinfo) {
7339 /* Now that we're sure SR-IOV is enabled
7340 * and memory allocated set up the mailbox parameters
7342 ixgbe_init_mbx_params_pf(hw);
7343 memcpy(&hw->mbx.ops, ii->mbx_ops,
7344 sizeof(hw->mbx.ops));
7346 /* Disable RSC when in SR-IOV mode */
7347 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7348 IXGBE_FLAG2_RSC_ENABLED);
7353 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7354 "SRIOV disabled\n");
7355 pci_disable_sriov(adapter->pdev);
7358 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7359 adapter->num_vfs = 0;
7360 #endif /* CONFIG_PCI_IOV */
7364 * ixgbe_probe - Device Initialization Routine
7365 * @pdev: PCI device information struct
7366 * @ent: entry in ixgbe_pci_tbl
7368 * Returns 0 on success, negative on failure
7370 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7371 * The OS initialization, configuring of the adapter private structure,
7372 * and a hardware reset occur.
7374 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7375 const struct pci_device_id *ent)
7377 struct net_device *netdev;
7378 struct ixgbe_adapter *adapter = NULL;
7379 struct ixgbe_hw *hw;
7380 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7381 static int cards_found;
7382 int i, err, pci_using_dac;
7383 u8 part_str[IXGBE_PBANUM_LENGTH];
7384 unsigned int indices = num_possible_cpus();
7390 /* Catch broken hardware that put the wrong VF device ID in
7391 * the PCIe SR-IOV capability.
7393 if (pdev->is_virtfn) {
7394 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7395 pci_name(pdev), pdev->vendor, pdev->device);
7399 err = pci_enable_device_mem(pdev);
7403 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7404 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7407 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7409 err = dma_set_coherent_mask(&pdev->dev,
7413 "No usable DMA configuration, aborting\n");
7420 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7421 IORESOURCE_MEM), ixgbe_driver_name);
7424 "pci_request_selected_regions failed 0x%x\n", err);
7428 pci_enable_pcie_error_reporting(pdev);
7430 pci_set_master(pdev);
7431 pci_save_state(pdev);
7433 #ifdef CONFIG_IXGBE_DCB
7434 indices *= MAX_TRAFFIC_CLASS;
7437 if (ii->mac == ixgbe_mac_82598EB)
7438 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7440 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7443 indices += min_t(unsigned int, num_possible_cpus(),
7444 IXGBE_MAX_FCOE_INDICES);
7446 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7449 goto err_alloc_etherdev;
7452 SET_NETDEV_DEV(netdev, &pdev->dev);
7454 adapter = netdev_priv(netdev);
7455 pci_set_drvdata(pdev, adapter);
7457 adapter->netdev = netdev;
7458 adapter->pdev = pdev;
7461 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7463 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7464 pci_resource_len(pdev, 0));
7470 for (i = 1; i <= 5; i++) {
7471 if (pci_resource_len(pdev, i) == 0)
7475 netdev->netdev_ops = &ixgbe_netdev_ops;
7476 ixgbe_set_ethtool_ops(netdev);
7477 netdev->watchdog_timeo = 5 * HZ;
7478 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7480 adapter->bd_number = cards_found;
7483 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7484 hw->mac.type = ii->mac;
7487 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7488 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7489 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7490 if (!(eec & (1 << 8)))
7491 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7494 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7495 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7496 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7497 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7498 hw->phy.mdio.mmds = 0;
7499 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7500 hw->phy.mdio.dev = netdev;
7501 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7502 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7504 ii->get_invariants(hw);
7506 /* setup the private structure */
7507 err = ixgbe_sw_init(adapter);
7511 /* Make it possible the adapter to be woken up via WOL */
7512 switch (adapter->hw.mac.type) {
7513 case ixgbe_mac_82599EB:
7514 case ixgbe_mac_X540:
7515 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7522 * If there is a fan on this device and it has failed log the
7525 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7526 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7527 if (esdp & IXGBE_ESDP_SDP1)
7528 e_crit(probe, "Fan has stopped, replace the adapter\n");
7531 /* reset_hw fills in the perm_addr as well */
7532 hw->phy.reset_if_overtemp = true;
7533 err = hw->mac.ops.reset_hw(hw);
7534 hw->phy.reset_if_overtemp = false;
7535 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7536 hw->mac.type == ixgbe_mac_82598EB) {
7538 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7539 e_dev_err("failed to load because an unsupported SFP+ "
7540 "module type was detected.\n");
7541 e_dev_err("Reload the driver after installing a supported "
7545 e_dev_err("HW Init failed: %d\n", err);
7549 ixgbe_probe_vf(adapter, ii);
7551 netdev->features = NETIF_F_SG |
7554 NETIF_F_HW_VLAN_TX |
7555 NETIF_F_HW_VLAN_RX |
7556 NETIF_F_HW_VLAN_FILTER |
7563 netdev->hw_features = netdev->features;
7565 switch (adapter->hw.mac.type) {
7566 case ixgbe_mac_82599EB:
7567 case ixgbe_mac_X540:
7568 netdev->features |= NETIF_F_SCTP_CSUM;
7569 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7576 netdev->vlan_features |= NETIF_F_TSO;
7577 netdev->vlan_features |= NETIF_F_TSO6;
7578 netdev->vlan_features |= NETIF_F_IP_CSUM;
7579 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7580 netdev->vlan_features |= NETIF_F_SG;
7582 netdev->priv_flags |= IFF_UNICAST_FLT;
7584 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7585 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7586 IXGBE_FLAG_DCB_ENABLED);
7588 #ifdef CONFIG_IXGBE_DCB
7589 netdev->dcbnl_ops = &dcbnl_ops;
7593 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7594 if (hw->mac.ops.get_device_caps) {
7595 hw->mac.ops.get_device_caps(hw, &device_caps);
7596 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7597 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7600 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7601 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7602 netdev->vlan_features |= NETIF_F_FSO;
7603 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7605 #endif /* IXGBE_FCOE */
7606 if (pci_using_dac) {
7607 netdev->features |= NETIF_F_HIGHDMA;
7608 netdev->vlan_features |= NETIF_F_HIGHDMA;
7611 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7612 netdev->hw_features |= NETIF_F_LRO;
7613 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7614 netdev->features |= NETIF_F_LRO;
7616 /* make sure the EEPROM is good */
7617 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7618 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7623 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7624 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7626 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7627 e_dev_err("invalid MAC address\n");
7632 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7633 if (hw->mac.ops.disable_tx_laser &&
7634 ((hw->phy.multispeed_fiber) ||
7635 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7636 (hw->mac.type == ixgbe_mac_82599EB))))
7637 hw->mac.ops.disable_tx_laser(hw);
7639 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7640 (unsigned long) adapter);
7642 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7643 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7645 err = ixgbe_init_interrupt_scheme(adapter);
7649 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7650 netdev->hw_features &= ~NETIF_F_RXHASH;
7651 netdev->features &= ~NETIF_F_RXHASH;
7654 switch (pdev->device) {
7655 case IXGBE_DEV_ID_82599_SFP:
7656 /* Only this subdevice supports WOL */
7657 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7658 adapter->wol = IXGBE_WUFC_MAG;
7660 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7661 /* All except this subdevice support WOL */
7662 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7663 adapter->wol = IXGBE_WUFC_MAG;
7665 case IXGBE_DEV_ID_82599_KX4:
7666 adapter->wol = IXGBE_WUFC_MAG;
7672 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7674 /* pick up the PCI bus settings for reporting later */
7675 hw->mac.ops.get_bus_info(hw);
7677 /* print bus type/speed/width info */
7678 e_dev_info("(PCI Express:%s:%s) %pM\n",
7679 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7680 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7682 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7683 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7684 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7688 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7690 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7691 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7692 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7693 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7696 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7697 hw->mac.type, hw->phy.type, part_str);
7699 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7700 e_dev_warn("PCI-Express bandwidth available for this card is "
7701 "not sufficient for optimal performance.\n");
7702 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7706 /* save off EEPROM version number */
7707 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7709 /* reset the hardware with the new settings */
7710 err = hw->mac.ops.start_hw(hw);
7712 if (err == IXGBE_ERR_EEPROM_VERSION) {
7713 /* We are running on a pre-production device, log a warning */
7714 e_dev_warn("This device is a pre-production adapter/LOM. "
7715 "Please be aware there may be issues associated "
7716 "with your hardware. If you are experiencing "
7717 "problems please contact your Intel or hardware "
7718 "representative who provided you with this "
7721 strcpy(netdev->name, "eth%d");
7722 err = register_netdev(netdev);
7726 /* carrier off reporting is important to ethtool even BEFORE open */
7727 netif_carrier_off(netdev);
7729 #ifdef CONFIG_IXGBE_DCA
7730 if (dca_add_requester(&pdev->dev) == 0) {
7731 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7732 ixgbe_setup_dca(adapter);
7735 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7736 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7737 for (i = 0; i < adapter->num_vfs; i++)
7738 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7741 /* Inform firmware of driver version */
7742 if (hw->mac.ops.set_fw_drv_ver)
7743 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7746 /* add san mac addr to netdev */
7747 ixgbe_add_sanmac_netdev(netdev);
7749 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7754 ixgbe_release_hw_control(adapter);
7755 ixgbe_clear_interrupt_scheme(adapter);
7758 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7759 ixgbe_disable_sriov(adapter);
7760 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7761 iounmap(hw->hw_addr);
7763 free_netdev(netdev);
7765 pci_release_selected_regions(pdev,
7766 pci_select_bars(pdev, IORESOURCE_MEM));
7769 pci_disable_device(pdev);
7774 * ixgbe_remove - Device Removal Routine
7775 * @pdev: PCI device information struct
7777 * ixgbe_remove is called by the PCI subsystem to alert the driver
7778 * that it should release a PCI device. The could be caused by a
7779 * Hot-Plug event, or because the driver is going to be removed from
7782 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7784 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7785 struct net_device *netdev = adapter->netdev;
7787 set_bit(__IXGBE_DOWN, &adapter->state);
7788 cancel_work_sync(&adapter->service_task);
7790 #ifdef CONFIG_IXGBE_DCA
7791 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7792 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7793 dca_remove_requester(&pdev->dev);
7794 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7799 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7800 ixgbe_cleanup_fcoe(adapter);
7802 #endif /* IXGBE_FCOE */
7804 /* remove the added san mac */
7805 ixgbe_del_sanmac_netdev(netdev);
7807 if (netdev->reg_state == NETREG_REGISTERED)
7808 unregister_netdev(netdev);
7810 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7811 ixgbe_disable_sriov(adapter);
7813 ixgbe_clear_interrupt_scheme(adapter);
7815 ixgbe_release_hw_control(adapter);
7817 iounmap(adapter->hw.hw_addr);
7818 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7821 e_dev_info("complete\n");
7823 free_netdev(netdev);
7825 pci_disable_pcie_error_reporting(pdev);
7827 pci_disable_device(pdev);
7831 * ixgbe_io_error_detected - called when PCI error is detected
7832 * @pdev: Pointer to PCI device
7833 * @state: The current pci connection state
7835 * This function is called after a PCI bus error affecting
7836 * this device has been detected.
7838 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7839 pci_channel_state_t state)
7841 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7842 struct net_device *netdev = adapter->netdev;
7844 netif_device_detach(netdev);
7846 if (state == pci_channel_io_perm_failure)
7847 return PCI_ERS_RESULT_DISCONNECT;
7849 if (netif_running(netdev))
7850 ixgbe_down(adapter);
7851 pci_disable_device(pdev);
7853 /* Request a slot reset. */
7854 return PCI_ERS_RESULT_NEED_RESET;
7858 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7859 * @pdev: Pointer to PCI device
7861 * Restart the card from scratch, as if from a cold-boot.
7863 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7865 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7866 pci_ers_result_t result;
7869 if (pci_enable_device_mem(pdev)) {
7870 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7871 result = PCI_ERS_RESULT_DISCONNECT;
7873 pci_set_master(pdev);
7874 pci_restore_state(pdev);
7875 pci_save_state(pdev);
7877 pci_wake_from_d3(pdev, false);
7879 ixgbe_reset(adapter);
7880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7881 result = PCI_ERS_RESULT_RECOVERED;
7884 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7886 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7887 "failed 0x%0x\n", err);
7888 /* non-fatal, continue */
7895 * ixgbe_io_resume - called when traffic can start flowing again.
7896 * @pdev: Pointer to PCI device
7898 * This callback is called when the error recovery driver tells us that
7899 * its OK to resume normal operation.
7901 static void ixgbe_io_resume(struct pci_dev *pdev)
7903 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7904 struct net_device *netdev = adapter->netdev;
7906 if (netif_running(netdev)) {
7907 if (ixgbe_up(adapter)) {
7908 e_info(probe, "ixgbe_up failed after reset\n");
7913 netif_device_attach(netdev);
7916 static struct pci_error_handlers ixgbe_err_handler = {
7917 .error_detected = ixgbe_io_error_detected,
7918 .slot_reset = ixgbe_io_slot_reset,
7919 .resume = ixgbe_io_resume,
7922 static struct pci_driver ixgbe_driver = {
7923 .name = ixgbe_driver_name,
7924 .id_table = ixgbe_pci_tbl,
7925 .probe = ixgbe_probe,
7926 .remove = __devexit_p(ixgbe_remove),
7928 .suspend = ixgbe_suspend,
7929 .resume = ixgbe_resume,
7931 .shutdown = ixgbe_shutdown,
7932 .err_handler = &ixgbe_err_handler
7936 * ixgbe_init_module - Driver Registration Routine
7938 * ixgbe_init_module is the first routine called when the driver is
7939 * loaded. All it does is register with the PCI subsystem.
7941 static int __init ixgbe_init_module(void)
7944 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7945 pr_info("%s\n", ixgbe_copyright);
7947 #ifdef CONFIG_IXGBE_DCA
7948 dca_register_notify(&dca_notifier);
7951 ret = pci_register_driver(&ixgbe_driver);
7955 module_init(ixgbe_init_module);
7958 * ixgbe_exit_module - Driver Exit Cleanup Routine
7960 * ixgbe_exit_module is called just before the driver is removed
7963 static void __exit ixgbe_exit_module(void)
7965 #ifdef CONFIG_IXGBE_DCA
7966 dca_unregister_notify(&dca_notifier);
7968 pci_unregister_driver(&ixgbe_driver);
7969 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7972 #ifdef CONFIG_IXGBE_DCA
7973 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7978 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7979 __ixgbe_notify_dca);
7981 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7984 #endif /* CONFIG_IXGBE_DCA */
7986 module_exit(ixgbe_exit_module);